Convert CONFIG_SYS_MAX_NAND_DEVICE to Kconfig
authorTom Rini <trini@konsulko.com>
Sat, 29 Oct 2022 00:27:04 +0000 (20:27 -0400)
committerTom Rini <trini@konsulko.com>
Thu, 10 Nov 2022 15:08:54 +0000 (10:08 -0500)
This converts the following to Kconfig:
   CONFIG_SYS_MAX_NAND_DEVICE

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
116 files changed:
configs/CHIP_pro_defconfig
configs/Nintendo_NES_Classic_Edition_defconfig
configs/etamin_defconfig
doc/README.nand
drivers/mtd/nand/raw/Kconfig
include/configs/M5329EVB.h
include/configs/M5373EVB.h
include/configs/MCR3000.h
include/configs/P1010RDB.h
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/at91sam9260ek.h
include/configs/at91sam9261ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9n12ek.h
include/configs/at91sam9rlek.h
include/configs/at91sam9x5ek.h
include/configs/bcm963158.h
include/configs/bcm96855.h
include/configs/bcm96856.h
include/configs/bcm96858.h
include/configs/bk4r1.h
include/configs/broadcom_bcm968380gerg.h
include/configs/cm_fx6.h
include/configs/colibri-imx6ull.h
include/configs/colibri_imx7.h
include/configs/colibri_t20.h
include/configs/colibri_vf.h
include/configs/comtrend_vr3032u.h
include/configs/corvus.h
include/configs/da850evm.h
include/configs/devkit3250.h
include/configs/etamin.h
include/configs/ethernut5.h
include/configs/gardena-smart-gateway-at91sam.h
include/configs/gw_ventana.h
include/configs/harmony.h
include/configs/imx27lite-common.h
include/configs/imx6-engicam.h
include/configs/imx6_logic.h
include/configs/imx6ulz_smm_m2.h
include/configs/imx8mn_bsh_smm_s2.h
include/configs/imx8mp_rsb3720.h
include/configs/km/km-mpc83xx.h
include/configs/km/pg-wcom-ls102xa.h
include/configs/kmcent2.h
include/configs/kmcoge5ne.h
include/configs/ls1021aqds.h
include/configs/ls1043aqds.h
include/configs/ls1043ardb.h
include/configs/ls1046afrwy.h
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h
include/configs/ls1088aqds.h
include/configs/ls1088ardb.h
include/configs/ls2080aqds.h
include/configs/ls2080ardb.h
include/configs/m53menlo.h
include/configs/medcom-wide.h
include/configs/meesc.h
include/configs/mt7621.h
include/configs/mv-common.h
include/configs/mvebu_armada-8k.h
include/configs/mx6sabreauto.h
include/configs/mx6sxsabreauto.h
include/configs/mx7dsabresd.h
include/configs/mxs.h
include/configs/mys_6ulx.h
include/configs/npi_imx6ull.h
include/configs/octeontx_common.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_logic.h
include/configs/omapl138_lcdk.h
include/configs/p1_p2_rdb_pc.h
include/configs/pcl063.h
include/configs/pcl063_ull.h
include/configs/pcm052.h
include/configs/pcm058.h
include/configs/plutux.h
include/configs/pm9261.h
include/configs/pm9263.h
include/configs/pm9g45.h
include/configs/presidio_asic.h
include/configs/sam9x60ek.h
include/configs/sama5d2_ptc_ek.h
include/configs/sama5d3_xplained.h
include/configs/sama5d3xek.h
include/configs/sama5d4_xplained.h
include/configs/sama5d4ek.h
include/configs/seaboard.h
include/configs/siemens-am33x-common.h
include/configs/smartweb.h
include/configs/snapper9g45.h
include/configs/socfpga_common.h
include/configs/socrates.h
include/configs/stm32mp13_common.h
include/configs/stm32mp15_common.h
include/configs/sunxi-common.h
include/configs/taurus.h
include/configs/tec.h
include/configs/ti816x_evm.h
include/configs/ti_armv7_keystone2.h
include/configs/ti_armv7_omap.h
include/configs/uniphier.h
include/configs/usb_a9263.h
include/configs/vf610twr.h
include/configs/work_92105.h
include/configs/x530.h
include/configs/xilinx_zynqmp.h
include/configs/zynq-common.h

index 2917960..5a12fbb 100644 (file)
@@ -19,6 +19,7 @@ CONFIG_SYS_I2C_SPEED=400000
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_SIZE=0x1000
index b660234..89fb441 100644 (file)
@@ -14,6 +14,7 @@ CONFIG_CMD_MTDPARTS=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 7bc3ac2..ee731f3 100644 (file)
@@ -98,6 +98,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=3
 CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index ffcea90..d1ce307 100644 (file)
@@ -99,9 +99,6 @@ Configuration Options:
    CONFIG_CMD_NAND_TORTURE
       Enables the torture command (see description of this command below).
 
-   CONFIG_SYS_MAX_NAND_DEVICE
-      The maximum number of NAND devices you want to support.
-
    CONFIG_SYS_NAND_MAX_ECCPOS
       If specified, overrides the maximum number of ECC bytes
       supported.  Useful for reducing image size, especially with SPL.
index d6e3eeb..a7196d5 100644 (file)
@@ -26,6 +26,10 @@ config TPL_SYS_NAND_SELF_INIT
 config TPL_NAND_INIT
        bool
 
+config SYS_MAX_NAND_DEVICE
+       int "Maximum number of NAND devices to support"
+       default 1
+
 config SYS_NAND_DRIVER_ECC_LAYOUT
        bool "Omit standard ECC layouts to save space"
        help
index a6c953f..474480c 100644 (file)
@@ -95,7 +95,6 @@
 #endif
 
 #ifdef CONFIG_CMD_NAND
-#      define CONFIG_SYS_MAX_NAND_DEVICE       1
 #      define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 #      define CONFIG_SYS_NAND_SIZE             1
 #      define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
index f519bef..2e1c857 100644 (file)
@@ -96,7 +96,6 @@
 #      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 #endif
 
-#      define CONFIG_SYS_MAX_NAND_DEVICE       1
 #      define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 #      define CONFIG_SYS_NAND_SIZE             1
 #      define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
index 1c46702..371ae20 100644 (file)
@@ -83,7 +83,6 @@
 /* Ethernet configuration part */
 
 /* NAND configuration part */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x0C000000
 
 #endif /* __CONFIG_H */
index b87118c..88d9bec 100644 (file)
@@ -202,7 +202,6 @@ extern unsigned long get_sdram_size(void);
 #endif
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 /* NAND Flash Timing Params */
index 60b0963..317784e 100644 (file)
 #endif
 
 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
index f6a911c..88700cb 100644 (file)
 
 #define CONFIG_SYS_NAND_DDR_LAW                11
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
index d9ee873..6474b6f 100644 (file)
 
 #define CONFIG_SYS_NAND_DDR_LAW                11
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
index 6701eab..10126a8 100644 (file)
 
 #define CONFIG_SYS_NAND_DDR_LAW                11
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
index 86c92de..a74225b 100644 (file)
 
 #define CONFIG_SYS_NAND_DDR_LAW                11
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
index 1ad8223..42d1095 100644 (file)
 
 #define CONFIG_SYS_NAND_DDR_LAW                11
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
index ca5815f..d51da9d 100644 (file)
@@ -43,7 +43,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index 5576a5f..5dc8f21 100644 (file)
@@ -24,7 +24,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   0x40000000
 #define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD22 */
index fb65880..3406373 100644 (file)
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8                  1
 /* our ALE is AD21 */
index 2d257c4..9a6f80f 100644 (file)
@@ -20,7 +20,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
index f2ca4f3..862179b 100644 (file)
@@ -21,7 +21,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE       (1 << 22)
index bc687fc..c60c248 100644 (file)
@@ -25,7 +25,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8                  1
 /* our ALE is AD21 */
index 0e76658..71246ce 100644 (file)
@@ -27,7 +27,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_DBW_8          1
 /* our ALE is AD21 */
index f473963..b15c411 100644 (file)
@@ -8,8 +8,4 @@
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif /* CONFIG_MTD_RAW_NAND */
-
 #endif
index ba2d8a3..6e420f2 100644 (file)
@@ -8,8 +8,4 @@
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif /* CONFIG_MTD_RAW_NAND */
-
 #endif
index 3050cf3..a7ae71e 100644 (file)
@@ -8,8 +8,4 @@
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif /* CONFIG_MTD_RAW_NAND */
-
 #endif
index 8bd1169..4e584b4 100644 (file)
@@ -8,8 +8,4 @@
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif /* CONFIG_MTD_RAW_NAND */
-
 #endif
index b3e1fdd..ca2bc19 100644 (file)
@@ -51,7 +51,6 @@
 #include <linux/sizes.h>
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
 
 #define IMX_FEC1_BASE                  ENET1_BASE_ADDR
 
index c1c1b37..bad1439 100644 (file)
@@ -6,6 +6,3 @@
 #include <configs/bmips_common.h>
 #include <configs/bmips_bcm6838.h>
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif /* CONFIG_MTD_RAW_NAND */
index cbba726..e5e8c13 100644 (file)
 
 /* NAND */
 #define CONFIG_SYS_NAND_BASE           0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 /* APBH DMA is required for NAND support */
 
 /* Ethernet */
index 321edab..31426b6 100644 (file)
 
 #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 /* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
 #define CONFIG_SYS_NAND_BASE           -1
 #endif
index b8d0dc9..c95b732 100644 (file)
 
 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
 #endif
index 73d1844..b758086 100644 (file)
@@ -16,7 +16,6 @@
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTA_BASE
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #define UBOOT_UPDATE \
        "update_uboot=nand erase.part u-boot && " \
index 268afbb..0f6f99d 100644 (file)
@@ -15,7 +15,6 @@
 #include <linux/sizes.h>
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #define CONFIG_IPADDR          192.168.10.2
 #define CONFIG_NETMASK         255.255.255.0
index a46b394..e8b0724 100644 (file)
@@ -6,6 +6,3 @@
 #include <configs/bmips_common.h>
 #include <configs/bmips_bcm63268.h>
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif /* CONFIG_MTD_RAW_NAND */
index 5e43c21..0596afb 100644 (file)
@@ -37,7 +37,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
index 58c9024..3625f92 100644 (file)
 #define CONFIG_SYS_NAND_MASK_CLE               0x10
 #define CONFIG_SYS_NAND_MASK_ALE               0x8
 #undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    0x40000
 #define CONFIG_SYS_NAND_U_BOOT_DST     0xc1080000
index 66fb25b..e5639fb 100644 (file)
@@ -36,7 +36,6 @@
  * NAND controller
  */
 #define CONFIG_SYS_NAND_BASE           SLC_NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 
 /*
index 7923fbb..75322a3 100644 (file)
@@ -45,8 +45,6 @@
 #define CONFIG_SYS_NAND_ECCSIZE 512
 #define CONFIG_SYS_NAND_ECCBYTES 26
 
-#undef CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_MAX_NAND_DEVICE      3
 #define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
                                        CONFIG_SYS_NAND_BASE2}
index 7a3c800..22647ab 100644 (file)
@@ -37,7 +37,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
index 635d0f0..a091ec5 100644 (file)
@@ -22,7 +22,6 @@
 #define CONFIG_SYS_SDRAM_SIZE          0x08000000      /* 128 megs */
 
 /* NAND flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_DBW_8          1
 /* our ALE is AD21 */
index bba64af..714f8d8 100644 (file)
@@ -20,7 +20,6 @@
 #define CONFIG_MXC_UART_BASE          UART2_BASE
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
index 879bd5c..fe4b02c 100644 (file)
@@ -24,7 +24,6 @@
 #endif
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Environment in NAND (which is 512M), aligned to start of last sector */
 
index 6ebdc3d..4042845 100644 (file)
@@ -97,7 +97,6 @@
  * NAND
  */
 #define CONFIG_MXC_NAND_REGS_BASE      0xd8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0xd8000000
 #define CONFIG_MXC_NAND_HWECC
 
index fa73cab..f52367c 100644 (file)
 
 /* NAND */
 #ifdef CONFIG_NAND_MXS
-# define CONFIG_SYS_MAX_NAND_DEVICE    1
 # define CONFIG_SYS_NAND_BASE          0x40000000
 # define CONFIG_SYS_NAND_U_BOOT_START  CONFIG_TEXT_BASE
 
index 9ab3f8a..a82641b 100644 (file)
 /* Environment organization */
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_TEXT_BASE
 
index 50885c5..46a96f1 100644 (file)
@@ -71,7 +71,6 @@
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #define CONFIG_SYS_NAND_BASE           0x20000000
 
index c6b2962..a2323bd 100644 (file)
@@ -43,7 +43,6 @@
 #define PHYS_SDRAM_SIZE                        SZ_256M
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #define CONFIG_SYS_NAND_BASE           0x20000000
 
index ddc035a..8eb7456 100644 (file)
 #ifdef CONFIG_NAND_MXS
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x20000000
 #endif /* CONFIG_NAND_MXS */
 
index 61c7134..f05aeac 100644 (file)
@@ -60,7 +60,6 @@
 
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           CONFIG_SYS_KMBEC_FPGA_BASE
 #endif
 
index 9565cea..1f5a025 100644 (file)
 #define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 
 /* QRIO FPGA Definitions */
index e5cc62e..6032f39 100644 (file)
 
 /* More NAND Flash Params */
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* QRIO on IFC CS2 */
 #define CONFIG_SYS_QRIO_BASE           0xfb000000
index b9d20c9..d6b60d8 100644 (file)
@@ -11,7 +11,6 @@
 #define CONFIG_HOSTNAME                "kmcoge5ne"
 #define CONFIG_NAND_ECC_BCH
 #define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define NAND_MAX_CHIPS                         1
 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 
index 37b8cd7..a788c30 100644 (file)
 #define CONFIG_SYS_NAND_FTIM3           0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #endif
 
 /*
index 4158d15..d207e47 100644 (file)
 #define CONFIG_SYS_NAND_FTIM3           0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #endif
 
index 4bfe4e3..206de7e 100644 (file)
@@ -82,7 +82,6 @@
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #ifdef CONFIG_NAND_BOOT
index 2df5f3f..582b1ee 100644 (file)
@@ -45,7 +45,6 @@
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 /* IFC Timing Params */
index b411efd..037d462 100644 (file)
 #define CONFIG_SYS_NAND_FTIM3           0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #endif
 
index 5d32957..f5f16ba 100644 (file)
@@ -50,7 +50,6 @@
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 /*
index 2d3351e..d50b76b 100644 (file)
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CONFIG_SYS_I2C_FPGA_ADDR       0x66
index d98ed39..4edf40b 100644 (file)
@@ -86,7 +86,6 @@
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CONFIG_SYS_I2C_FPGA_ADDR       0x66
index d02d7fc..1fa4aa3 100644 (file)
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH             0x06
index 09484dc..e1c66c5 100644 (file)
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH             0x06
index 4bf4496..f8bd31d 100644 (file)
@@ -44,7 +44,6 @@
  * NAND
  */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_IP_REGS_BASE   NFC_BASE_ADDR
index b35ba59..b90a84d 100644 (file)
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Environment in NAND, aligned to start of last sector */
 
index cffcd9d..9f913fa 100644 (file)
@@ -52,7 +52,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_MAX_NAND_DEVICE            1
 # define CONFIG_SYS_NAND_BASE                  ATMEL_BASE_CS3 /* 0x40000000 */
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE              (1 << 21)
index 554c435..6a55e7a 100644 (file)
@@ -21,7 +21,6 @@
 #define MMC_SUPPORTS_TUNING
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
index 20e00ec..6d4fff3 100644 (file)
@@ -61,8 +61,5 @@
 /*
  * Common NAND configuration
  */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif
 
 #endif /* _MV_COMMON_H */
index 5a956f0..5debd91 100644 (file)
@@ -25,8 +25,6 @@
 
 /* When runtime detection fails this is the default */
 
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-
 /* USB ethernet */
 
 /*
index c76e7ea..7e54bb2 100644 (file)
@@ -36,7 +36,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
index c878041..407b643 100644 (file)
@@ -86,7 +86,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC3_BASE_ADDR
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
index b96341a..2a97d2f 100644 (file)
@@ -93,7 +93,6 @@
  */
 #ifdef CONFIG_NAND_MXS
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
index fc15ed8..e861038 100644 (file)
@@ -83,7 +83,6 @@
 
 /* NAND */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x60000000
 #endif
 
index 4162ee8..bb68ddb 100644 (file)
@@ -30,7 +30,6 @@
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* USB Configs */
index 217427a..8ff26fe 100644 (file)
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* USB Configs */
index 373eb91..6e69b3d 100644 (file)
@@ -46,8 +46,4 @@
 
 /** EMMC specific defines */
 
-#if defined(CONFIG_NAND_OCTEONTX)
-#define CONFIG_SYS_MAX_NAND_DEVICE 8
-#endif
-
 #endif /* __OCTEONTX_COMMON_H__ */
index ad3dbbc..d46ca33 100644 (file)
@@ -21,7 +21,6 @@
 /* NAND */
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_FLASH_BASE          NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
                                          10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE         512
index c47d557..77629d7 100644 (file)
@@ -26,7 +26,6 @@
 /* NAND */
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_FLASH_BASE          NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
                                          10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE         512
index 1af87b2..442a3ca 100644 (file)
@@ -16,7 +16,6 @@
 
 /* Board NAND Info. */
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1         /* Max number of */
                                                  /* NAND devices */
 #define CONFIG_SYS_NAND_ECCPOS         {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
                                         13, 14, 16, 17, 18, 19, 20, 21, 22, \
index c644768..df4a16f 100644 (file)
 #define CONFIG_SYS_NAND_MASK_CLE       0x10
 #define CONFIG_SYS_NAND_MASK_ALE       0x8
 #undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    SZ_512K
index fcb287d..2555953 100644 (file)
 #endif
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
        | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
index 6e593da..5b38a94 100644 (file)
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* USB Configs */
index ae81b8e..688d161 100644 (file)
@@ -44,7 +44,6 @@
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 
 /* USB Configs */
index a8cfec9..a04a03a 100644 (file)
@@ -14,8 +14,6 @@
 
 /* NAND support */
 
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-
 /* if no target-specific extra environment settings were defined by the
    target, define an empty one */
 #ifndef PCM052_EXTRA_ENV_SETTINGS
index cff71df..0119090 100644 (file)
@@ -15,7 +15,6 @@
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 
 /* Enable NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
index 9a4a632..09f0ed9 100644 (file)
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Environment in NAND, aligned to start of last sector */
 
index 7f9442a..278f1b5 100644 (file)
 #define PHYS_SDRAM_SIZE                                0x04000000      /* 64 megs */
 
 /* NAND flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   0x40000000
 #define CONFIG_SYS_NAND_DBW_8                  1
 /* our ALE is AD22 */
index 00d159f..7c23206 100644 (file)
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_DBW_8          1
 /* our ALE is AD21 */
index 69f3d06..fa47a3e 100644 (file)
@@ -25,7 +25,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
index 90f548c..ebf5467 100644 (file)
@@ -58,7 +58,6 @@
 
 /* nand driver parameters */
 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
-       #define CONFIG_SYS_MAX_NAND_DEVICE      1
        #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
        #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 #endif
index b9b56d9..70c6ec5 100644 (file)
@@ -28,7 +28,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_MASK_ALE       BIT(21)
 #define CONFIG_SYS_NAND_MASK_CLE       BIT(22)
index 3b91e83..9281c7c 100644 (file)
@@ -21,7 +21,6 @@
 
 /* NAND Flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE       BIT(21)
index fad65cb..301e8c9 100644 (file)
@@ -29,7 +29,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x60000000
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index ccb3842..1c94193 100644 (file)
@@ -38,7 +38,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x60000000
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index d5cd45c..eac4144 100644 (file)
@@ -17,7 +17,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x80000000
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index 411ed29..bc5312d 100644 (file)
@@ -17,7 +17,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x80000000
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index e6c200f..c7f03a1 100644 (file)
@@ -29,7 +29,6 @@
 /* NAND support */
 
 /* Max number of NAND devices */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 #include "tegra-common-post.h"
 
index 5759794..87da5e4 100644 (file)
 #define CONFIG_SYS_NAND_BASE           (0x08000000)    /* physical address */
                                                        /* to access nand at */
                                                        /* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND
-                                                          devices */
 #endif
 
 #endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
index 802ed07..a77215d 100644 (file)
@@ -54,7 +54,6 @@
  */
 
 /* NAND flash settings */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index 59bba7d..c56fb37 100644 (file)
@@ -30,7 +30,6 @@
 
 /* NAND Flash */
 #define CONFIG_SYS_NAND_ECC_BASE       ATMEL_BASE_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21) /* AD21 */
index c3f30af..f0a33ed 100644 (file)
@@ -80,7 +80,6 @@
  * NAND Support
  */
 #ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_REGS_BASE      SOCFPGA_NANDREGS_ADDRESS
 #define CONFIG_SYS_NAND_DATA_BASE      SOCFPGA_NANDDATA_ADDRESS
 #endif
index 00e8136..122aec2 100644 (file)
 #define CONFIG_SYS_FPGA_SIZE           0x00100000      /* 1 MB         */
 
 #define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_FPGA_BASE + 0x70)
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* LIME GDC */
 #define CONFIG_SYS_LIME_BASE           0xc8000000
index 78089b9..222e69c 100644 (file)
@@ -25,7 +25,6 @@
 #define CONFIG_SYS_MMC_MAX_DEVICE      2
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /*****************************************************************************/
 #ifdef CONFIG_DISTRO_DEFAULTS
index 214901c..6103c2c 100644 (file)
@@ -25,7 +25,6 @@
 #define CONFIG_SYS_MMC_MAX_DEVICE      3
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Ethernet need */
 #ifdef CONFIG_DWC_ETH_QOS
index 12666b7..f9c701b 100644 (file)
@@ -73,7 +73,6 @@
 
 #ifdef CONFIG_NAND_SUNXI
 #define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#define CONFIG_SYS_MAX_NAND_DEVICE 8
 #endif
 
 /* mmc config */
index a29652d..45780d9 100644 (file)
@@ -54,7 +54,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
 #define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
index 432ccbd..2377b47 100644 (file)
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 /* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Environment in NAND, aligned to start of last sector */
 
index 1aca83a..82add65 100644 (file)
@@ -43,7 +43,6 @@
  * access CS0 at is 0x8000000.
  */
 #define CONFIG_SYS_NAND_BASE           0x8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* NAND: SPL related configs */
 
index 29a6038..4078413 100644 (file)
@@ -69,7 +69,6 @@
 
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_NAND_BASE_LIST              { 0x30000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 
 #define DFU_ALT_INFO_MMC \
index 727c648..44706c7 100644 (file)
@@ -19,7 +19,6 @@
 #ifndef CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE           0x8000000
 #endif
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #endif
 
 /* Now for the remaining common defines */
index d9e95ab..b92fe38 100644 (file)
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_TIMER_RATE                  1000000
 #endif
 
-#define CONFIG_SYS_MAX_NAND_DEVICE                     1
 #define CONFIG_SYS_NAND_REGS_BASE                      0x68100000
 #define CONFIG_SYS_NAND_DATA_BASE                      0x68000000
 
index e0dde1c..44eaeda 100644 (file)
@@ -33,7 +33,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
index c13f2ba..dde6d13 100644 (file)
@@ -14,7 +14,6 @@
 /* NAND support */
 
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
 
 /* Dynamic MTD partition support */
index f53ea3c..e1f9f12 100644 (file)
@@ -42,7 +42,6 @@
  */
 
 /* driver configuration */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
 #define CONFIG_SYS_MAX_NAND_CHIPS 1
 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
 
index cb12683..0add626 100644 (file)
@@ -27,7 +27,6 @@
  */
 
 /* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
 
 #define BBT_CUSTOM_SCAN
 #define BBT_CUSTOM_SCAN_PAGE 0
index f72f3e6..60f007a 100644 (file)
        EFI_GUID(0xcf9ecfd4, 0x938b, 0x41c5, 0x85, 0x51, \
                 0x1f, 0x88, 0x3a, 0xb7, 0xdc, 0x18)
 
-#ifdef CONFIG_NAND_ARASAN
-# define CONFIG_SYS_MAX_NAND_DEVICE    1
-#endif
-
 /* Miscellaneous configurable options */
 
 #if defined(CONFIG_ZYNQMP_USB)
index dc0cba0..e194e77 100644 (file)
 # define CONFIG_FLASH_SHOW_PROGRESS    10
 #endif
 
-#ifdef CONFIG_NAND_ZYNQ
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#endif
-
 #ifdef CONFIG_USB_EHCI_ZYNQ
 # define DFU_DEFAULT_POLL_TIMEOUT      300
 # define CONFIG_THOR_RESET_OFF