1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
8 #include <linux/stringify.h>
11 * Memory configurations
13 #define PHYS_SDRAM_1 0x0
14 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
15 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
16 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
17 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
18 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
19 /* SPL memory allocation configuration, this is for FAT implementation */
20 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
21 CONFIG_SYS_SPL_MALLOC_SIZE)
25 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
26 * SRAM as bootcounter storage. Make sure to not put the stack directly
27 * at this address to not overwrite the bootcounter by checking, if the
28 * bootcounter address is located in the internal SRAM.
30 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
31 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
32 CONFIG_SYS_INIT_RAM_SIZE)))
36 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
37 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
38 * in U-Boot pre-reloc is higher than in SPL.
41 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
44 * U-Boot general configurations
46 /* Print buffer size */
51 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
57 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
58 #define CONFIG_SYS_TIMER_COUNTS_DOWN
59 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
60 #ifndef CONFIG_SYS_TIMER_RATE
61 #define CONFIG_SYS_TIMER_RATE 25000000
68 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
75 /* using smaller max blk cnt to avoid flooding the limited stack we have */
76 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
82 #ifdef CONFIG_NAND_DENALI
83 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
84 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
92 * USB Gadget (DFU, UMS)
94 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
95 #define DFU_DEFAULT_POLL_TIMEOUT 300
98 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
99 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
106 /* Environment for SDMMC boot */
108 /* Environment for QSPI boot */
113 * SRAM Memory layout for gen 5:
115 * 0xFFFF_0000 ...... Start of SRAM
116 * 0xFFFF_xxxx ...... Top of stack (grows down)
117 * 0xFFFF_yyyy ...... Global Data
118 * 0xFFFF_zzzz ...... Malloc area
119 * 0xFFFF_FFFF ...... End of SRAM
121 * SRAM Memory layout for Arria 10:
122 * 0xFFE0_0000 ...... Start of SRAM (bottom)
123 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
124 * 0xFFEy_yyyy ...... Global Data
125 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
126 * 0xFFE3_FFFF ...... End of SRAM (top)
129 /* SPL QSPI boot support */
131 /* SPL NAND boot support */
133 /* Extra Environment */
134 #ifndef CONFIG_SPL_BUILD
136 #ifdef CONFIG_CMD_DHCP
137 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
139 #define BOOT_TARGET_DEVICES_DHCP(func)
142 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
143 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
145 #define BOOT_TARGET_DEVICES_PXE(func)
148 #ifdef CONFIG_CMD_MMC
149 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
151 #define BOOT_TARGET_DEVICES_MMC(func)
154 #define BOOT_TARGET_DEVICES(func) \
155 BOOT_TARGET_DEVICES_MMC(func) \
156 BOOT_TARGET_DEVICES_PXE(func) \
157 BOOT_TARGET_DEVICES_DHCP(func)
159 #include <config_distro_bootcmd.h>
161 #ifndef CONFIG_EXTRA_ENV_SETTINGS
162 #define CONFIG_EXTRA_ENV_SETTINGS \
163 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
164 "bootm_size=0xa000000\0" \
165 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
166 "fdt_addr_r=0x02000000\0" \
167 "scriptaddr=0x02100000\0" \
168 "pxefile_addr_r=0x02200000\0" \
169 "ramdisk_addr_r=0x02300000\0" \
170 "socfpga_legacy_reset_compat=1\0" \
176 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */