include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #define SYS_NO_FLASH
  14 #endif
  15
  16 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  17
  18 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  19 #define SPD_EEPROM_ADDRESS      0x51
  20
  21
  22 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  23 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  24 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  25 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  26
  27 #define CONFIG_SYS_NOR0_CSPR                                    \
  28         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  29         CSPR_PORT_SIZE_16                                       | \
  30         CSPR_MSEL_NOR                                           | \
  31         CSPR_V)
  32 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  33         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  34         CSPR_PORT_SIZE_16                                       | \
  35         CSPR_MSEL_NOR                                           | \
  36         CSPR_V)
  37 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  38 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  39                                 FTIM0_NOR_TEADC(0x1) | \
  40                                 FTIM0_NOR_TEAHC(0x1))
  41 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  42                                 FTIM1_NOR_TRAD_NOR(0x1))
  43 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  44                                 FTIM2_NOR_TCH(0x0) | \
  45                                 FTIM2_NOR_TWP(0x1))
  46 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  47 #define CONFIG_SYS_IFC_CCR      0x01000000
  48
  49 #ifndef SYS_NO_FLASH
  50 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  51
  52 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  53 #endif
  54 #endif
  55
  56 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  57 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  58
  59 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  60 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  61                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  62                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  63                                 | CSPR_V)
  64 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  65
  66 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  67                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  68                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  69                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  70                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  71                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  72                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  73
  74 /* ONFI NAND Flash mode0 Timing Params */
  75 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  76                                         FTIM0_NAND_TWP(0x18)   | \
  77                                         FTIM0_NAND_TWCHT(0x07) | \
  78                                         FTIM0_NAND_TWH(0x0a))
  79 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  80                                         FTIM1_NAND_TWBE(0x39)  | \
  81                                         FTIM1_NAND_TRR(0x0e)   | \
  82                                         FTIM1_NAND_TRP(0x18))
  83 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
  84                                         FTIM2_NAND_TREH(0x0a) | \
  85                                         FTIM2_NAND_TWHRE(0x1e))
  86 #define CONFIG_SYS_NAND_FTIM3           0x0
  87
  88 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  89 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  90 #define CONFIG_MTD_NAND_VERIFY_WRITE
  91
  92 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  93 #define QIXIS_BRDCFG4_OFFSET            0x54
  94 #define QIXIS_LBMAP_SWITCH              2
  95 #define QIXIS_QMAP_MASK                 0xe0
  96 #define QIXIS_QMAP_SHIFT                5
  97 #define QIXIS_LBMAP_MASK                0x1f
  98 #define QIXIS_LBMAP_SHIFT               5
  99 #define QIXIS_LBMAP_DFLTBANK            0x00
 100 #define QIXIS_LBMAP_ALTBANK             0x20
 101 #define QIXIS_LBMAP_SD                  0x00
 102 #define QIXIS_LBMAP_EMMC                0x00
 103 #define QIXIS_LBMAP_SD_QSPI             0x00
 104 #define QIXIS_LBMAP_QSPI                0x00
 105 #define QIXIS_RCW_SRC_SD                0x40
 106 #define QIXIS_RCW_SRC_EMMC              0x41
 107 #define QIXIS_RCW_SRC_QSPI              0x62
 108 #define QIXIS_RST_CTL_RESET             0x31
 109 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 110 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 111 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 112 #define QIXIS_RST_FORCE_MEM             0x01
 113
 114 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 115 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 116                                         | CSPR_PORT_SIZE_8 \
 117                                         | CSPR_MSEL_GPCM \
 118                                         | CSPR_V)
 119 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 120                                         | CSPR_PORT_SIZE_8 \
 121                                         | CSPR_MSEL_GPCM \
 122                                         | CSPR_V)
 123
 124 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 125 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 126 /* QIXIS Timing parameters*/
 127 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 128                                         FTIM0_GPCM_TEADC(0x0e) | \
 129                                         FTIM0_GPCM_TEAHC(0x0e))
 130 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 131                                         FTIM1_GPCM_TRAD(0x3f))
 132 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 133                                         FTIM2_GPCM_TCH(0xf) | \
 134                                         FTIM2_GPCM_TWP(0x3E))
 135 #define SYS_FPGA_CS_FTIM3       0x0
 136
 137 #if defined(CONFIG_TFABOOT) || \
 138         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 139 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 140 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 141 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 142 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 143 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 144 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 145 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 146 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 147 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 148 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 149 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 150 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 151 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 152 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 153 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 154 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 155 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 156 #else
 157 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 158 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 159 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 160 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 161 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 162 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 163 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 164 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 165 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 166 #endif
 167
 168 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 169
 170 #define I2C_MUX_CH_VOL_MONITOR         0xA
 171 /* Voltage monitor on channel 2*/
 172 #define I2C_VOL_MONITOR_ADDR           0x63
 173 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 174 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 175 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 176 #define I2C_SVDD_MONITOR_ADDR           0x4F
 177
 178 /* The lowest and highest voltage allowed for LS1088ARDB */
 179 #define VDD_MV_MIN                      819
 180 #define VDD_MV_MAX                      1212
 181
 182 #define PWM_CHANNEL0                    0x0
 183
 184 /*
 185  * I2C bus multiplexer
 186  */
 187 #define I2C_MUX_PCA_ADDR_PRI            0x77
 188 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 189 #define I2C_RETIMER_ADDR                0x18
 190 #define I2C_MUX_CH_DEFAULT              0x8
 191 #define I2C_MUX_CH5                     0xD
 192
 193 #ifndef SPL_NO_RTC
 194 /*
 195 * RTC configuration
 196 */
 197 #define RTC
 198 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 199 #endif
 200
 201 #ifndef SPL_NO_ENV
 202 /* Initial environment variables */
 203 #ifdef CONFIG_TFABOOT
 204 #define QSPI_MC_INIT_CMD                                \
 205         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 206         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 207         "env exists secureboot && "                     \
 208         "sf read 0x80640000 0x640000 0x40000 && "       \
 209         "sf read 0x80680000 0x680000 0x40000 && "       \
 210         "esbc_validate 0x80640000 && "                  \
 211         "esbc_validate 0x80680000 ;"                    \
 212         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 213 #define SD_MC_INIT_CMD                          \
 214         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 215         "mmc read 0x80e00000 0x7000 0x800;"                             \
 216         "env exists secureboot && "                     \
 217         "mmc read 0x80640000 0x3200 0x20 && "           \
 218         "mmc read 0x80680000 0x3400 0x20 && "           \
 219         "esbc_validate 0x80640000 && "                  \
 220         "esbc_validate 0x80680000 ;"                    \
 221         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 222 #else
 223 #if defined(CONFIG_QSPI_BOOT)
 224 #define MC_INIT_CMD                             \
 225         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 226         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 227         "env exists secureboot && "                     \
 228         "sf read 0x80640000 0x640000 0x40000 && "       \
 229         "sf read 0x80680000 0x680000 0x40000 && "       \
 230         "esbc_validate 0x80640000 && "                  \
 231         "esbc_validate 0x80680000 ;"                    \
 232         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 233         "mcmemsize=0x70000000\0"
 234 #elif defined(CONFIG_SD_BOOT)
 235 #define MC_INIT_CMD                             \
 236         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 237         "mmc read 0x80e00000 0x7000 0x800;"                             \
 238         "env exists secureboot && "                     \
 239         "mmc read 0x80640000 0x3200 0x20 && "           \
 240         "mmc read 0x80680000 0x3400 0x20 && "           \
 241         "esbc_validate 0x80640000 && "                  \
 242         "esbc_validate 0x80680000 ;"                    \
 243         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 244         "mcmemsize=0x70000000\0"
 245 #endif
 246 #endif /* CONFIG_TFABOOT */
 247
 248 #undef CONFIG_EXTRA_ENV_SETTINGS
 249 #ifdef CONFIG_TFABOOT
 250 #define CONFIG_EXTRA_ENV_SETTINGS               \
 251         "BOARD=ls1088ardb\0"                    \
 252         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 253         "ramdisk_addr=0x800000\0"               \
 254         "ramdisk_size=0x2000000\0"              \
 255         "fdt_high=0xa0000000\0"                 \
 256         "initrd_high=0xffffffffffffffff\0"      \
 257         "kernel_addr=0x1000000\0"               \
 258         "kernel_addr_sd=0x8000\0"               \
 259         "kernelhdr_addr_sd=0x3000\0"            \
 260         "kernel_start=0x580100000\0"            \
 261         "kernelheader_start=0x580600000\0"      \
 262         "scriptaddr=0x80000000\0"               \
 263         "scripthdraddr=0x80080000\0"            \
 264         "fdtheader_addr_r=0x80100000\0"         \
 265         "kernelheader_addr=0x600000\0"          \
 266         "kernelheader_addr_r=0x80200000\0"      \
 267         "kernel_addr_r=0x81000000\0"            \
 268         "kernelheader_size=0x40000\0"           \
 269         "fdt_addr_r=0x90000000\0"               \
 270         "load_addr=0xa0000000\0"                \
 271         "kernel_size=0x2800000\0"               \
 272         "kernel_size_sd=0x14000\0"              \
 273         "kernelhdr_size_sd=0x20\0"              \
 274         QSPI_MC_INIT_CMD                        \
 275         "mcmemsize=0x70000000\0"                \
 276         BOOTENV                                 \
 277         "boot_scripts=ls1088ardb_boot.scr\0"    \
 278         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 279         "scan_dev_for_boot_part="               \
 280                 "part list ${devtype} ${devnum} devplist; "     \
 281                 "env exists devplist || setenv devplist 1; "    \
 282                 "for distro_bootpart in ${devplist}; do "       \
 283                         "if fstype ${devtype} "                 \
 284                                 "${devnum}:${distro_bootpart} " \
 285                                 "bootfstype; then "             \
 286                                 "run scan_dev_for_boot; "       \
 287                         "fi; "                                  \
 288                 "done\0"                                        \
 289         "boot_a_script="                                        \
 290                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 291                 "${scriptaddr} ${prefix}${script}; "            \
 292         "env exists secureboot && load ${devtype} "             \
 293                 "${devnum}:${distro_bootpart} "                 \
 294                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 295                 "env exists secureboot "                        \
 296                 "&& esbc_validate ${scripthdraddr};"            \
 297                 "source ${scriptaddr}\0"                        \
 298         "installer=load mmc 0:2 $load_addr "                    \
 299                 "/flex_installer_arm64.itb; "                   \
 300                 "env exists mcinitcmd && run mcinitcmd && "     \
 301                 "mmc read 0x80001000 0x6800 0x800;"             \
 302                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 303                 "bootm $load_addr#ls1088ardb\0"                 \
 304         "qspi_bootcmd=echo Trying load from qspi..;"            \
 305                 "sf probe && sf read $load_addr "               \
 306                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 307                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 308                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 309                 "bootm $load_addr#$BOARD\0"                     \
 310                 "sd_bootcmd=echo Trying load from sd card..;"           \
 311                 "mmcinfo; mmc read $load_addr "                 \
 312                 "$kernel_addr_sd $kernel_size_sd ;"             \
 313                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 314                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 315                 " && esbc_validate ${kernelheader_addr_r};"     \
 316                 "bootm $load_addr#$BOARD\0"
 317 #else
 318 #define CONFIG_EXTRA_ENV_SETTINGS               \
 319         "BOARD=ls1088ardb\0"                    \
 320         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 321         "ramdisk_addr=0x800000\0"               \
 322         "ramdisk_size=0x2000000\0"              \
 323         "fdt_high=0xa0000000\0"                 \
 324         "initrd_high=0xffffffffffffffff\0"      \
 325         "kernel_addr=0x1000000\0"               \
 326         "kernel_addr_sd=0x8000\0"               \
 327         "kernelhdr_addr_sd=0x3000\0"            \
 328         "kernel_start=0x580100000\0"            \
 329         "kernelheader_start=0x580800000\0"      \
 330         "scriptaddr=0x80000000\0"               \
 331         "scripthdraddr=0x80080000\0"            \
 332         "fdtheader_addr_r=0x80100000\0"         \
 333         "kernelheader_addr=0x600000\0"          \
 334         "kernelheader_addr_r=0x80200000\0"      \
 335         "kernel_addr_r=0x81000000\0"            \
 336         "kernelheader_size=0x40000\0"           \
 337         "fdt_addr_r=0x90000000\0"               \
 338         "load_addr=0xa0000000\0"                \
 339         "kernel_size=0x2800000\0"               \
 340         "kernel_size_sd=0x14000\0"              \
 341         "kernelhdr_size_sd=0x20\0"              \
 342         MC_INIT_CMD                             \
 343         BOOTENV                                 \
 344         "boot_scripts=ls1088ardb_boot.scr\0"    \
 345         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 346         "scan_dev_for_boot_part="               \
 347                 "part list ${devtype} ${devnum} devplist; "     \
 348                 "env exists devplist || setenv devplist 1; "    \
 349                 "for distro_bootpart in ${devplist}; do "       \
 350                         "if fstype ${devtype} "                 \
 351                                 "${devnum}:${distro_bootpart} " \
 352                                 "bootfstype; then "             \
 353                                 "run scan_dev_for_boot; "       \
 354                         "fi; "                                  \
 355                 "done\0"                                        \
 356         "boot_a_script="                                        \
 357                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 358                 "${scriptaddr} ${prefix}${script}; "            \
 359         "env exists secureboot && load ${devtype} "             \
 360                 "${devnum}:${distro_bootpart} "                 \
 361                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 362                 "&& esbc_validate ${scripthdraddr};"            \
 363                 "source ${scriptaddr}\0"                        \
 364         "installer=load mmc 0:2 $load_addr "                    \
 365                 "/flex_installer_arm64.itb; "                   \
 366                 "env exists mcinitcmd && run mcinitcmd && "     \
 367                 "mmc read 0x80001000 0x6800 0x800;"             \
 368                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 369                 "bootm $load_addr#ls1088ardb\0"                 \
 370         "qspi_bootcmd=echo Trying load from qspi..;"            \
 371                 "sf probe && sf read $load_addr "               \
 372                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 373                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 374                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 375                 "bootm $load_addr#$BOARD\0"                     \
 376                 "sd_bootcmd=echo Trying load from sd card..;"           \
 377                 "mmcinfo; mmc read $load_addr "                 \
 378                 "$kernel_addr_sd $kernel_size_sd ;"             \
 379                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 380                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 381                 " && esbc_validate ${kernelheader_addr_r};"     \
 382                 "bootm $load_addr#$BOARD\0"
 383 #endif /* CONFIG_TFABOOT */
 384
 385 #ifdef CONFIG_TFABOOT
 386 #define QSPI_NOR_BOOTCOMMAND                                    \
 387         "sf read 0x80001000 0xd00000 0x100000;"         \
 388                 "env exists mcinitcmd && env exists secureboot "        \
 389                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 390                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 391                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 392                 "run distro_bootcmd;run qspi_bootcmd;"          \
 393                 "env exists secureboot && esbc_halt;"
 394 #define SD_BOOTCOMMAND                                          \
 395                 "env exists mcinitcmd && mmcinfo; "             \
 396                 "mmc read 0x80001000 0x6800 0x800; "            \
 397                 "env exists mcinitcmd && env exists secureboot "        \
 398                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 399                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 400                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 401                 "run distro_bootcmd;run sd_bootcmd;"            \
 402                 "env exists secureboot && esbc_halt;"
 403 #else
 404 #if defined(CONFIG_QSPI_BOOT)
 405 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 406
 407 /* Try to boot an on-SD kernel first, then do normal distro boot */
 408 #endif
 409 #endif /* CONFIG_TFABOOT */
 410
 411 /* MAC/PHY configuration */
 412 #ifdef CONFIG_FSL_MC_ENET
 413 #define AQ_PHY_ADDR1                    0x00
 414 #define AQR105_IRQ_MASK                 0x00000004
 415
 416 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 417 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 418 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 419 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 420 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 421 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 422 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 423 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 424 #endif
 425 #endif
 426
 427 #ifndef SPL_NO_ENV
 428
 429 #define BOOT_TARGET_DEVICES(func) \
 430         func(MMC, mmc, 0) \
 431         func(USB, usb, 0) \
 432         func(SCSI, scsi, 0) \
 433         func(DHCP, dhcp, na)
 434 #include <config_distro_bootcmd.h>
 435 #endif
 436
 437 #include <asm/fsl_secure_boot.h>
 438
 439 #endif /* __LS1088A_RDB_H */