1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9263EK board.
13 #include <linux/stringify.h>
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
19 #include <asm/hardware.h>
21 /* ARM asynchronous clock */
22 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
23 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
26 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
27 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
29 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
30 #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
32 /* NOR flash, if populated */
33 #ifdef CONFIG_SYS_USE_NORFLASH
34 #define PHYS_FLASH_1 0x10000000
35 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
37 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
39 /* Address and size of Primary Environment Sector */
41 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
44 "protect off ${monitor_base} +${filesize};" \
45 "erase ${monitor_base} +${filesize};" \
46 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
47 "protect on ${monitor_base} +${filesize}\0"
49 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
50 #define MASTER_PLL_MUL 171
51 #define MASTER_PLL_DIV 14
52 #define MASTER_PLL_OUT 3
55 #define CONFIG_SYS_MOR_VAL \
56 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
57 #define CONFIG_SYS_PLLAR_VAL \
58 (AT91_PMC_PLLAR_29 | \
59 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
60 AT91_PMC_PLLXR_PLLCOUNT(63) | \
61 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
62 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
64 /* PCK/2 = MCK Master Clock from PLLA */
65 #define CONFIG_SYS_MCKR1_VAL \
66 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
69 /* PCK/2 = MCK Master Clock from PLLA */
70 #define CONFIG_SYS_MCKR2_VAL \
71 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
74 /* define PDC[31:16] as DATA[31:16] */
75 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
76 /* no pull-up for D[31:16] */
77 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
78 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
79 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
80 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
81 AT91_MATRIX_CSA_EBI_CS1A)
84 /* SDRAMC_MR Mode register */
85 #define CONFIG_SYS_SDRC_MR_VAL1 0
86 /* SDRAMC_TR - Refresh Timer register */
87 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
88 /* SDRAMC_CR - Configuration register*/
89 #define CONFIG_SYS_SDRC_CR_VAL \
94 AT91_SDRAMC_DBW_32 | \
95 (1 << 8) | /* Write Recovery Delay */ \
96 (7 << 12) | /* Row Cycle Delay */ \
97 (2 << 16) | /* Row Precharge Delay */ \
98 (2 << 20) | /* Row to Column Delay */ \
99 (5 << 24) | /* Active to Precharge Delay */ \
100 (1 << 28)) /* Exit Self Refresh to Active Delay */
102 /* Memory Device Register -> SDRAM */
103 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
104 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
105 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
106 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
107 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
108 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
109 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
110 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
111 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
112 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
113 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
114 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
115 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
116 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
117 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
118 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
119 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
120 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
122 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
123 #define CONFIG_SYS_SMC0_SETUP0_VAL \
124 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
125 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
126 #define CONFIG_SYS_SMC0_PULSE0_VAL \
127 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
128 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
129 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
130 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
131 #define CONFIG_SYS_SMC0_MODE0_VAL \
132 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
133 AT91_SMC_MODE_DBW_16 | \
134 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
136 /* user reset enable */
137 #define CONFIG_SYS_RSTC_RMR_VAL \
139 AT91_RSTC_MR_URSTEN | \
140 AT91_RSTC_MR_ERSTL(15))
142 /* Disable Watchdog */
143 #define CONFIG_SYS_WDTC_WDMR_VAL \
144 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
145 AT91_WDT_MR_WDV(0xfff) | \
146 AT91_WDT_MR_WDDIS | \
147 AT91_WDT_MR_WDD(0xfff))
150 #include <linux/stringify.h>
154 #ifdef CONFIG_CMD_NAND
155 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
156 #define CONFIG_SYS_NAND_DBW_8 1
157 /* our ALE is AD21 */
158 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
159 /* our CLE is AD22 */
160 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
161 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
162 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
166 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */