1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
16 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
18 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #define SPD_EEPROM_ADDRESS 0x51
22 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
23 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
24 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
25 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
27 #define CONFIG_SYS_NOR0_CSPR \
28 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
32 #define CONFIG_SYS_NOR0_CSPR_EARLY \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
37 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
38 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
39 FTIM0_NOR_TEADC(0x1) | \
41 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
42 FTIM1_NOR_TRAD_NOR(0x1))
43 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
44 FTIM2_NOR_TCH(0x0) | \
46 #define CONFIG_SYS_NOR_FTIM3 0x04000000
47 #define CONFIG_SYS_IFC_CCR 0x01000000
50 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
52 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
56 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
57 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
59 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
60 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
61 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
62 | CSPR_MSEL_NAND /* MSEL = NAND */ \
64 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
66 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
67 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
68 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
69 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
70 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
71 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
72 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
74 /* ONFI NAND Flash mode0 Timing Params */
75 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
76 FTIM0_NAND_TWP(0x18) | \
77 FTIM0_NAND_TWCHT(0x07) | \
79 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
80 FTIM1_NAND_TWBE(0x39) | \
81 FTIM1_NAND_TRR(0x0e) | \
83 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
84 FTIM2_NAND_TREH(0x0a) | \
85 FTIM2_NAND_TWHRE(0x1e))
86 #define CONFIG_SYS_NAND_FTIM3 0x0
88 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
89 #define CONFIG_MTD_NAND_VERIFY_WRITE
91 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
92 #define QIXIS_BRDCFG4_OFFSET 0x54
93 #define QIXIS_LBMAP_SWITCH 2
94 #define QIXIS_QMAP_MASK 0xe0
95 #define QIXIS_QMAP_SHIFT 5
96 #define QIXIS_LBMAP_MASK 0x1f
97 #define QIXIS_LBMAP_SHIFT 5
98 #define QIXIS_LBMAP_DFLTBANK 0x00
99 #define QIXIS_LBMAP_ALTBANK 0x20
100 #define QIXIS_LBMAP_SD 0x00
101 #define QIXIS_LBMAP_EMMC 0x00
102 #define QIXIS_LBMAP_SD_QSPI 0x00
103 #define QIXIS_LBMAP_QSPI 0x00
104 #define QIXIS_RCW_SRC_SD 0x40
105 #define QIXIS_RCW_SRC_EMMC 0x41
106 #define QIXIS_RCW_SRC_QSPI 0x62
107 #define QIXIS_RST_CTL_RESET 0x31
108 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
109 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
110 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
111 #define QIXIS_RST_FORCE_MEM 0x01
113 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
114 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
118 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
123 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
124 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
125 /* QIXIS Timing parameters*/
126 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
127 FTIM0_GPCM_TEADC(0x0e) | \
128 FTIM0_GPCM_TEAHC(0x0e))
129 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
130 FTIM1_GPCM_TRAD(0x3f))
131 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
132 FTIM2_GPCM_TCH(0xf) | \
133 FTIM2_GPCM_TWP(0x3E))
134 #define SYS_FPGA_CS_FTIM3 0x0
136 #if defined(CONFIG_TFABOOT) || \
137 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
138 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
139 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
140 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
141 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
142 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
143 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
144 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
145 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
146 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
147 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
148 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
149 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
150 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
151 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
152 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
153 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
154 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
156 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
157 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
158 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
159 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
160 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
161 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
162 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
163 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
164 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
167 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
169 #define I2C_MUX_CH_VOL_MONITOR 0xA
170 /* Voltage monitor on channel 2*/
171 #define I2C_VOL_MONITOR_ADDR 0x63
172 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
173 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
174 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
175 #define I2C_SVDD_MONITOR_ADDR 0x4F
177 /* The lowest and highest voltage allowed for LS1088ARDB */
178 #define VDD_MV_MIN 819
179 #define VDD_MV_MAX 1212
181 #define PWM_CHANNEL0 0x0
184 * I2C bus multiplexer
186 #define I2C_MUX_PCA_ADDR_PRI 0x77
187 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
188 #define I2C_RETIMER_ADDR 0x18
189 #define I2C_MUX_CH_DEFAULT 0x8
190 #define I2C_MUX_CH5 0xD
197 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
201 /* Initial environment variables */
202 #ifdef CONFIG_TFABOOT
203 #define QSPI_MC_INIT_CMD \
204 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
205 "sf read 0x80e00000 0xE00000 0x100000;" \
206 "env exists secureboot && " \
207 "sf read 0x80640000 0x640000 0x40000 && " \
208 "sf read 0x80680000 0x680000 0x40000 && " \
209 "esbc_validate 0x80640000 && " \
210 "esbc_validate 0x80680000 ;" \
211 "fsl_mc start mc 0x80a00000 0x80e00000\0"
212 #define SD_MC_INIT_CMD \
213 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
214 "mmc read 0x80e00000 0x7000 0x800;" \
215 "env exists secureboot && " \
216 "mmc read 0x80640000 0x3200 0x20 && " \
217 "mmc read 0x80680000 0x3400 0x20 && " \
218 "esbc_validate 0x80640000 && " \
219 "esbc_validate 0x80680000 ;" \
220 "fsl_mc start mc 0x80a00000 0x80e00000\0"
222 #if defined(CONFIG_QSPI_BOOT)
223 #define MC_INIT_CMD \
224 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
225 "sf read 0x80e00000 0xE00000 0x100000;" \
226 "env exists secureboot && " \
227 "sf read 0x80640000 0x640000 0x40000 && " \
228 "sf read 0x80680000 0x680000 0x40000 && " \
229 "esbc_validate 0x80640000 && " \
230 "esbc_validate 0x80680000 ;" \
231 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
232 "mcmemsize=0x70000000\0"
233 #elif defined(CONFIG_SD_BOOT)
234 #define MC_INIT_CMD \
235 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
236 "mmc read 0x80e00000 0x7000 0x800;" \
237 "env exists secureboot && " \
238 "mmc read 0x80640000 0x3200 0x20 && " \
239 "mmc read 0x80680000 0x3400 0x20 && " \
240 "esbc_validate 0x80640000 && " \
241 "esbc_validate 0x80680000 ;" \
242 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
243 "mcmemsize=0x70000000\0"
245 #endif /* CONFIG_TFABOOT */
247 #undef CONFIG_EXTRA_ENV_SETTINGS
248 #ifdef CONFIG_TFABOOT
249 #define CONFIG_EXTRA_ENV_SETTINGS \
250 "BOARD=ls1088ardb\0" \
251 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
252 "ramdisk_addr=0x800000\0" \
253 "ramdisk_size=0x2000000\0" \
254 "fdt_high=0xa0000000\0" \
255 "initrd_high=0xffffffffffffffff\0" \
256 "kernel_addr=0x1000000\0" \
257 "kernel_addr_sd=0x8000\0" \
258 "kernelhdr_addr_sd=0x3000\0" \
259 "kernel_start=0x580100000\0" \
260 "kernelheader_start=0x580600000\0" \
261 "scriptaddr=0x80000000\0" \
262 "scripthdraddr=0x80080000\0" \
263 "fdtheader_addr_r=0x80100000\0" \
264 "kernelheader_addr=0x600000\0" \
265 "kernelheader_addr_r=0x80200000\0" \
266 "kernel_addr_r=0x81000000\0" \
267 "kernelheader_size=0x40000\0" \
268 "fdt_addr_r=0x90000000\0" \
269 "load_addr=0xa0000000\0" \
270 "kernel_size=0x2800000\0" \
271 "kernel_size_sd=0x14000\0" \
272 "kernelhdr_size_sd=0x20\0" \
274 "mcmemsize=0x70000000\0" \
276 "boot_scripts=ls1088ardb_boot.scr\0" \
277 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
278 "scan_dev_for_boot_part=" \
279 "part list ${devtype} ${devnum} devplist; " \
280 "env exists devplist || setenv devplist 1; " \
281 "for distro_bootpart in ${devplist}; do " \
282 "if fstype ${devtype} " \
283 "${devnum}:${distro_bootpart} " \
284 "bootfstype; then " \
285 "run scan_dev_for_boot; " \
289 "load ${devtype} ${devnum}:${distro_bootpart} " \
290 "${scriptaddr} ${prefix}${script}; " \
291 "env exists secureboot && load ${devtype} " \
292 "${devnum}:${distro_bootpart} " \
293 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
294 "env exists secureboot " \
295 "&& esbc_validate ${scripthdraddr};" \
296 "source ${scriptaddr}\0" \
297 "installer=load mmc 0:2 $load_addr " \
298 "/flex_installer_arm64.itb; " \
299 "env exists mcinitcmd && run mcinitcmd && " \
300 "mmc read 0x80001000 0x6800 0x800;" \
301 "fsl_mc lazyapply dpl 0x80001000;" \
302 "bootm $load_addr#ls1088ardb\0" \
303 "qspi_bootcmd=echo Trying load from qspi..;" \
304 "sf probe && sf read $load_addr " \
305 "$kernel_addr $kernel_size ; env exists secureboot " \
306 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
307 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
308 "bootm $load_addr#$BOARD\0" \
309 "sd_bootcmd=echo Trying load from sd card..;" \
310 "mmcinfo; mmc read $load_addr " \
311 "$kernel_addr_sd $kernel_size_sd ;" \
312 "env exists secureboot && mmc read $kernelheader_addr_r "\
313 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
314 " && esbc_validate ${kernelheader_addr_r};" \
315 "bootm $load_addr#$BOARD\0"
317 #define CONFIG_EXTRA_ENV_SETTINGS \
318 "BOARD=ls1088ardb\0" \
319 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
320 "ramdisk_addr=0x800000\0" \
321 "ramdisk_size=0x2000000\0" \
322 "fdt_high=0xa0000000\0" \
323 "initrd_high=0xffffffffffffffff\0" \
324 "kernel_addr=0x1000000\0" \
325 "kernel_addr_sd=0x8000\0" \
326 "kernelhdr_addr_sd=0x3000\0" \
327 "kernel_start=0x580100000\0" \
328 "kernelheader_start=0x580800000\0" \
329 "scriptaddr=0x80000000\0" \
330 "scripthdraddr=0x80080000\0" \
331 "fdtheader_addr_r=0x80100000\0" \
332 "kernelheader_addr=0x600000\0" \
333 "kernelheader_addr_r=0x80200000\0" \
334 "kernel_addr_r=0x81000000\0" \
335 "kernelheader_size=0x40000\0" \
336 "fdt_addr_r=0x90000000\0" \
337 "load_addr=0xa0000000\0" \
338 "kernel_size=0x2800000\0" \
339 "kernel_size_sd=0x14000\0" \
340 "kernelhdr_size_sd=0x20\0" \
343 "boot_scripts=ls1088ardb_boot.scr\0" \
344 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
345 "scan_dev_for_boot_part=" \
346 "part list ${devtype} ${devnum} devplist; " \
347 "env exists devplist || setenv devplist 1; " \
348 "for distro_bootpart in ${devplist}; do " \
349 "if fstype ${devtype} " \
350 "${devnum}:${distro_bootpart} " \
351 "bootfstype; then " \
352 "run scan_dev_for_boot; " \
356 "load ${devtype} ${devnum}:${distro_bootpart} " \
357 "${scriptaddr} ${prefix}${script}; " \
358 "env exists secureboot && load ${devtype} " \
359 "${devnum}:${distro_bootpart} " \
360 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
361 "&& esbc_validate ${scripthdraddr};" \
362 "source ${scriptaddr}\0" \
363 "installer=load mmc 0:2 $load_addr " \
364 "/flex_installer_arm64.itb; " \
365 "env exists mcinitcmd && run mcinitcmd && " \
366 "mmc read 0x80001000 0x6800 0x800;" \
367 "fsl_mc lazyapply dpl 0x80001000;" \
368 "bootm $load_addr#ls1088ardb\0" \
369 "qspi_bootcmd=echo Trying load from qspi..;" \
370 "sf probe && sf read $load_addr " \
371 "$kernel_addr $kernel_size ; env exists secureboot " \
372 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
373 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
374 "bootm $load_addr#$BOARD\0" \
375 "sd_bootcmd=echo Trying load from sd card..;" \
376 "mmcinfo; mmc read $load_addr " \
377 "$kernel_addr_sd $kernel_size_sd ;" \
378 "env exists secureboot && mmc read $kernelheader_addr_r "\
379 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
380 " && esbc_validate ${kernelheader_addr_r};" \
381 "bootm $load_addr#$BOARD\0"
382 #endif /* CONFIG_TFABOOT */
384 #ifdef CONFIG_TFABOOT
385 #define QSPI_NOR_BOOTCOMMAND \
386 "sf read 0x80001000 0xd00000 0x100000;" \
387 "env exists mcinitcmd && env exists secureboot " \
388 " && sf read 0x806C0000 0x6C0000 0x100000 " \
389 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
390 "&& fsl_mc lazyapply dpl 0x80001000;" \
391 "run distro_bootcmd;run qspi_bootcmd;" \
392 "env exists secureboot && esbc_halt;"
393 #define SD_BOOTCOMMAND \
394 "env exists mcinitcmd && mmcinfo; " \
395 "mmc read 0x80001000 0x6800 0x800; " \
396 "env exists mcinitcmd && env exists secureboot " \
397 " && mmc read 0x806C0000 0x3600 0x20 " \
398 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
399 "&& fsl_mc lazyapply dpl 0x80001000;" \
400 "run distro_bootcmd;run sd_bootcmd;" \
401 "env exists secureboot && esbc_halt;"
403 #if defined(CONFIG_QSPI_BOOT)
404 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
406 /* Try to boot an on-SD kernel first, then do normal distro boot */
408 #endif /* CONFIG_TFABOOT */
410 /* MAC/PHY configuration */
411 #ifdef CONFIG_FSL_MC_ENET
412 #define AQ_PHY_ADDR1 0x00
413 #define AQR105_IRQ_MASK 0x00000004
415 #define QSGMII1_PORT1_PHY_ADDR 0x0c
416 #define QSGMII1_PORT2_PHY_ADDR 0x0d
417 #define QSGMII1_PORT3_PHY_ADDR 0x0e
418 #define QSGMII1_PORT4_PHY_ADDR 0x0f
419 #define QSGMII2_PORT1_PHY_ADDR 0x1c
420 #define QSGMII2_PORT2_PHY_ADDR 0x1d
421 #define QSGMII2_PORT3_PHY_ADDR 0x1e
422 #define QSGMII2_PORT4_PHY_ADDR 0x1f
428 #define BOOT_TARGET_DEVICES(func) \
431 func(SCSI, scsi, 0) \
433 #include <config_distro_bootcmd.h>
436 #include <asm/fsl_secure_boot.h>
438 #endif /* __LS1088A_RDB_H */