include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  20 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  21 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  22 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  23 #endif
  24
  25 #ifdef CONFIG_SPIFLASH
  26 #ifdef CONFIG_NXP_ESBC
  27 #define CONFIG_RAMBOOT_SPIFLASH
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  29 #else
  30 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_MTD_RAW_NAND
  38 #ifdef CONFIG_NXP_ESBC
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  42 #else
  43 #ifdef CONFIG_TPL_BUILD
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  46 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  47 #elif defined(CONFIG_SPL_BUILD)
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  50 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 /* High Level Configuration Options */
  64
  65 #if defined(CONFIG_PCI)
  66 /*
  67  * PCI Windows
  68  * Memory space is mapped 1-1, but I/O space must start from 0.
  69  */
  70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  71 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  72 #ifdef CONFIG_PHYS_64BIT
  73 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  74 #else
  75 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
  76 #endif
  77 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
  80 #else
  81 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
  82 #endif
  83
  84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  85 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
  88 #else
  89 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
  90 #endif
  91 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
  94 #else
  95 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
  96 #endif
  97 #endif
  98
  99 #define CONFIG_HWCONFIG
 100 /*
 101  * These can be toggled for performance analysis, otherwise use default.
 102  */
 103 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 104
 105 /* DDR Setup */
 106 #define SPD_EEPROM_ADDRESS              0x52
 107
 108 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 109
 110 #ifndef __ASSEMBLY__
 111 extern unsigned long get_sdram_size(void);
 112 #endif
 113 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 114 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 115 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 116
 117 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 119
 120 /*
 121  * Memory map
 122  *
 123  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 124  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 125  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 126  *
 127  * Localbus non-cacheable
 128  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 129  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 130  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 131  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 132  */
 133
 134 /*
 135  * IFC Definitions
 136  */
 137 /* NOR Flash on IFC */
 138
 139 #define CONFIG_SYS_FLASH_BASE           0xee000000
 140
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 143 #else
 144 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 145 #endif
 146
 147 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 148                                 CSPR_PORT_SIZE_16 | \
 149                                 CSPR_MSEL_NOR | \
 150                                 CSPR_V)
 151 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 152 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 153 /* NOR Flash Timing Params */
 154 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 155                                 FTIM0_NOR_TEADC(0x5) | \
 156                                 FTIM0_NOR_TEAHC(0x5)
 157 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 158                                 FTIM1_NOR_TRAD_NOR(0x0f)
 159 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 160                                 FTIM2_NOR_TCH(0x4) | \
 161                                 FTIM2_NOR_TWP(0x1c)
 162 #define CONFIG_SYS_NOR_FTIM3    0x0
 163
 164 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 165 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 166
 167 /* CFI for NOR Flash */
 168
 169 /* NAND Flash on IFC */
 170 #define CONFIG_SYS_NAND_BASE            0xff800000
 171 #ifdef CONFIG_PHYS_64BIT
 172 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 173 #else
 174 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 175 #endif
 176
 177 #define CONFIG_MTD_PARTITION
 178
 179 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 180                                 | CSPR_PORT_SIZE_8      \
 181                                 | CSPR_MSEL_NAND        \
 182                                 | CSPR_V)
 183 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 184
 185 #if defined(CONFIG_TARGET_P1010RDB_PA)
 186 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 187                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 188                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 189                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 190                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 191                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 192                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 193
 194 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 195 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 196                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 197                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 198                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 199                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 200                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 201                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 202 #endif
 203
 204 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 205 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 206
 207 #if defined(CONFIG_TARGET_P1010RDB_PA)
 208 /* NAND Flash Timing Params */
 209 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 210                                         FTIM0_NAND_TWP(0x0C)   | \
 211                                         FTIM0_NAND_TWCHT(0x04) | \
 212                                         FTIM0_NAND_TWH(0x05)
 213 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 214                                         FTIM1_NAND_TWBE(0x1d)  | \
 215                                         FTIM1_NAND_TRR(0x07)   | \
 216                                         FTIM1_NAND_TRP(0x0c)
 217 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 218                                         FTIM2_NAND_TREH(0x05) | \
 219                                         FTIM2_NAND_TWHRE(0x0f)
 220 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 221
 222 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 223 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 224 /* ONFI NAND Flash mode0 Timing Params */
 225 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 226                                         FTIM0_NAND_TWP(0x18)   | \
 227                                         FTIM0_NAND_TWCHT(0x07) | \
 228                                         FTIM0_NAND_TWH(0x0a))
 229 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 230                                         FTIM1_NAND_TWBE(0x39)  | \
 231                                         FTIM1_NAND_TRR(0x0e)   | \
 232                                         FTIM1_NAND_TRP(0x18))
 233 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 234                                         FTIM2_NAND_TREH(0x0a)  | \
 235                                         FTIM2_NAND_TWHRE(0x1e))
 236 #define CONFIG_SYS_NAND_FTIM3   0x0
 237 #endif
 238
 239 #define CONFIG_SYS_NAND_DDR_LAW         11
 240
 241 /* Set up IFC registers for boot location NOR/NAND */
 242 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 243 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 244 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 245 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 246 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 247 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 248 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 249 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 250 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 251 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 252 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 253 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 254 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 255 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 256 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 257 #else
 258 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 259 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 260 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 261 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 262 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 263 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 264 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 265 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 266 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 267 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 268 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 269 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 270 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 271 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 272 #endif
 273
 274 /* CPLD on IFC */
 275 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 276
 277 #ifdef CONFIG_PHYS_64BIT
 278 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 279 #else
 280 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 281 #endif
 282
 283 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 284                                 | CSPR_PORT_SIZE_8 \
 285                                 | CSPR_MSEL_GPCM \
 286                                 | CSPR_V)
 287 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 288 #define CONFIG_SYS_CSOR3                0x0
 289 /* CPLD Timing parameters for IFC CS3 */
 290 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 291                                         FTIM0_GPCM_TEADC(0x0e) | \
 292                                         FTIM0_GPCM_TEAHC(0x0e))
 293 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 294                                         FTIM1_GPCM_TRAD(0x1f))
 295 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 296                                         FTIM2_GPCM_TCH(0x8) | \
 297                                         FTIM2_GPCM_TWP(0x1f))
 298 #define CONFIG_SYS_CS3_FTIM3            0x0
 299
 300 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 301 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 302
 303 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 304
 305 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 306
 307 /*
 308  * Config the L2 Cache as L2 SRAM
 309  */
 310 #if defined(CONFIG_SPL_BUILD)
 311 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 312 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 313 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 314 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 315 #elif defined(CONFIG_MTD_RAW_NAND)
 316 #ifdef CONFIG_TPL_BUILD
 317 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 318 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 319 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 320 #else
 321 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 322 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 323 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 324 #endif
 325 #endif
 326 #endif
 327
 328 /* Serial Port */
 329 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 330 #define CONFIG_SYS_NS16550_SERIAL
 331 #define CONFIG_SYS_NS16550_REG_SIZE     1
 332 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 333 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
 334 #define CONFIG_NS16550_MIN_FUNCTIONS
 335 #endif
 336
 337 #define CONFIG_SYS_BAUDRATE_TABLE       \
 338         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 339
 340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 342
 343 /* I2C */
 344 #define I2C_PCA9557_ADDR1               0x18
 345 #define I2C_PCA9557_ADDR2               0x19
 346 #define I2C_PCA9557_BUS_NUM             0
 347
 348 /* I2C EEPROM */
 349 #if defined(CONFIG_TARGET_P1010RDB_PB)
 350 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 351 #endif
 352 /* enable read and write access to EEPROM */
 353
 354 /* RTC */
 355 #define CONFIG_RTC_PT7C4338
 356 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 357
 358 /*
 359  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 360  * used for SLIC
 361  */
 362 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 363 /* eSPI - Enhanced SPI */
 364 #endif
 365
 366 #if defined(CONFIG_TSEC_ENET)
 367 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 368 #define CONFIG_TSEC1    1
 369 #define CONFIG_TSEC1_NAME       "eTSEC1"
 370 #define CONFIG_TSEC2    1
 371 #define CONFIG_TSEC2_NAME       "eTSEC2"
 372 #define CONFIG_TSEC3    1
 373 #define CONFIG_TSEC3_NAME       "eTSEC3"
 374
 375 #define TSEC1_PHY_ADDR          1
 376 #define TSEC2_PHY_ADDR          0
 377 #define TSEC3_PHY_ADDR          2
 378
 379 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 380 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 381 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 382
 383 #define TSEC1_PHYIDX            0
 384 #define TSEC2_PHYIDX            0
 385 #define TSEC3_PHYIDX            0
 386
 387 /* TBI PHY configuration for SGMII mode */
 388 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 389                 TBICR_PHY_RESET \
 390                 | TBICR_ANEG_ENABLE \
 391                 | TBICR_FULL_DUPLEX \
 392                 | TBICR_SPEED1_SET \
 393                 )
 394
 395 #endif  /* CONFIG_TSEC_ENET */
 396
 397 #ifdef CONFIG_MMC
 398 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 399 #endif
 400
 401 /*
 402  * Environment
 403  */
 404 #if defined(CONFIG_MTD_RAW_NAND)
 405 #ifdef CONFIG_TPL_BUILD
 406 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 407 #endif
 408 #endif
 409
 410 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 411                  || defined(CONFIG_FSL_SATA)
 412 #endif
 413
 414 /*
 415  * Miscellaneous configurable options
 416  */
 417
 418 /*
 419  * For booting Linux, the board info and command line data
 420  * have to be in the first 64 MB of memory, since this is
 421  * the maximum mapped by the Linux kernel during initialization.
 422  */
 423 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 424
 425 /*
 426  * Environment Configuration
 427  */
 428
 429 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 430 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 431
 432 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 433         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 434         "netdev=eth0\0"                                         \
 435         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 436         "loadaddr=1000000\0"                    \
 437         "consoledev=ttyS0\0"                            \
 438         "ramdiskaddr=2000000\0"                 \
 439         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 440         "fdtaddr=1e00000\0"                             \
 441         "fdtfile=p1010rdb.dtb\0"                \
 442         "bdev=sda1\0"   \
 443         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 444         "othbootargs=ramdisk_size=600000\0" \
 445         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 446         "console=$consoledev,$baudrate $othbootargs; "  \
 447         "usb start;"                    \
 448         "fatload usb 0:2 $loadaddr $bootfile;"          \
 449         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 450         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 451         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 452         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 453         "console=$consoledev,$baudrate $othbootargs; "  \
 454         "usb start;"                    \
 455         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 456         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 457         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 458         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 459         BOOTMODE
 460
 461 #if defined(CONFIG_TARGET_P1010RDB_PA)
 462 #define BOOTMODE \
 463         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 464         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 465         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 466         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 467         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 468         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 469
 470 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 471 #define BOOTMODE \
 472         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 473         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 474         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 475         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 476         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 477         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 478         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 479         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 480         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 481         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 482 #endif
 483
 484 #include <asm/fsl_secure_boot.h>
 485
 486 #endif  /* __CONFIG_H */