include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  12 #define SYS_NO_FLASH
  13 #endif
  14
  15 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  16
  17 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  18 #define SPD_EEPROM_ADDRESS              0x51
  19
  20
  21 /*
  22  * IFC Definitions
  23  */
  24 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  25 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  26 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  27 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  28
  29 #define CONFIG_SYS_NOR0_CSPR                                    \
  30         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  31         CSPR_PORT_SIZE_16                                       | \
  32         CSPR_MSEL_NOR                                           | \
  33         CSPR_V)
  34 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  35         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  36         CSPR_PORT_SIZE_16                                       | \
  37         CSPR_MSEL_NOR                                           | \
  38         CSPR_V)
  39 #define CONFIG_SYS_NOR1_CSPR                                    \
  40         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  45         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  50 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  51                                 FTIM0_NOR_TEADC(0x5) | \
  52                                 FTIM0_NOR_TAVDS(0x6) | \
  53                                 FTIM0_NOR_TEAHC(0x5))
  54 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  55                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  56                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  57 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  58                                 FTIM2_NOR_TCH(0x8) | \
  59                                 FTIM2_NOR_TWPH(0xe) | \
  60                                 FTIM2_NOR_TWP(0x1c))
  61 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  62 #define CONFIG_SYS_IFC_CCR      0x01000000
  63
  64 #ifndef SYS_NO_FLASH
  65 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  66
  67 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  68                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  69 #endif
  70 #endif
  71
  72 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  73 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  74
  75 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  76 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  77                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  78                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  79                                 | CSPR_V)
  80 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  81
  82 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  83                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  84                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  85                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  86                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  87                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  88                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  89
  90 /* ONFI NAND Flash mode0 Timing Params */
  91 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  92                                         FTIM0_NAND_TWP(0x18)   | \
  93                                         FTIM0_NAND_TWCHT(0x07) | \
  94                                         FTIM0_NAND_TWH(0x0a))
  95 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  96                                         FTIM1_NAND_TWBE(0x39)  | \
  97                                         FTIM1_NAND_TRR(0x0e)   | \
  98                                         FTIM1_NAND_TRP(0x18))
  99 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 100                                         FTIM2_NAND_TREH(0x0a) | \
 101                                         FTIM2_NAND_TWHRE(0x1e))
 102 #define CONFIG_SYS_NAND_FTIM3           0x0
 103
 104 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 105 #define CONFIG_MTD_NAND_VERIFY_WRITE
 106
 107 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 108 #define QIXIS_LBMAP_SWITCH              6
 109 #define QIXIS_QMAP_MASK                 0xe0
 110 #define QIXIS_QMAP_SHIFT                5
 111 #define QIXIS_LBMAP_MASK                0x0f
 112 #define QIXIS_LBMAP_SHIFT               0
 113 #define QIXIS_LBMAP_DFLTBANK            0x0e
 114 #define QIXIS_LBMAP_ALTBANK             0x2e
 115 #define QIXIS_LBMAP_SD                  0x00
 116 #define QIXIS_LBMAP_EMMC                0x00
 117 #define QIXIS_LBMAP_IFC                 0x00
 118 #define QIXIS_LBMAP_SD_QSPI             0x0e
 119 #define QIXIS_LBMAP_QSPI                0x0e
 120 #define QIXIS_RCW_SRC_IFC               0x25
 121 #define QIXIS_RCW_SRC_SD                0x40
 122 #define QIXIS_RCW_SRC_EMMC              0x41
 123 #define QIXIS_RCW_SRC_QSPI              0x62
 124 #define QIXIS_RST_CTL_RESET             0x41
 125 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 126 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 127 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 128 #define QIXIS_RST_FORCE_MEM             0x01
 129 #define QIXIS_STAT_PRES1                0xb
 130 #define QIXIS_SDID_MASK                 0x07
 131 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 132
 133 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 134 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 135                                         | CSPR_PORT_SIZE_8 \
 136                                         | CSPR_MSEL_GPCM \
 137                                         | CSPR_V)
 138 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 139                                         | CSPR_PORT_SIZE_8 \
 140                                         | CSPR_MSEL_GPCM \
 141                                         | CSPR_V)
 142
 143 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 144 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 145 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 146 #else
 147 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 148 #endif
 149 /* QIXIS Timing parameters*/
 150 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 151                                         FTIM0_GPCM_TEADC(0x0e) | \
 152                                         FTIM0_GPCM_TEAHC(0x0e))
 153 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 154                                         FTIM1_GPCM_TRAD(0x3f))
 155 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 156                                         FTIM2_GPCM_TCH(0xf) | \
 157                                         FTIM2_GPCM_TWP(0x3E))
 158 #define SYS_FPGA_CS_FTIM3       0x0
 159
 160 #ifdef CONFIG_TFABOOT
 161 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 162 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 163 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 164 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 165 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 166 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 167 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 168 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 169 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 170 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 171 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 172 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 173 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 174 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 175 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 176 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 177 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 178 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 179 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 180 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 181 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 182 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 183 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 184 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 185 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 186 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 187 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 188 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 189 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 190 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 191 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 192 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 193 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 194 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 195 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 196 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 197 #else
 198 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 199 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 200 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 201 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 202 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 203 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 204 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 205 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 206 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 207 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 208 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 209 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 210 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 211 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 212 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 213 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 214 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 215 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 216 #else
 217 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 218 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 219 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 220 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 221 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 222 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 223 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 224 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 225 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 226 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 227 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 228 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 229 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 230 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 231 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 232 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 233 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 234 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 235 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 236 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 237 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 238 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 239 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 240 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 241 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 242 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 243 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 244 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 245 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 246 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 247 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 248 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 249 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 250 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 251 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 252 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 253 #endif
 254 #endif
 255
 256 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 257
 258 /*
 259  * I2C bus multiplexer
 260  */
 261 #define I2C_MUX_PCA_ADDR_PRI            0x77
 262 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 263 #define I2C_RETIMER_ADDR                0x18
 264 #define I2C_RETIMER_ADDR2               0x19
 265 #define I2C_MUX_CH_DEFAULT              0x8
 266 #define I2C_MUX_CH5                     0xD
 267
 268 #define I2C_MUX_CH_VOL_MONITOR          0xA
 269
 270 /* Voltage monitor on channel 2*/
 271 #define I2C_VOL_MONITOR_ADDR           0x63
 272 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 273 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 274 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 275 #define I2C_SVDD_MONITOR_ADDR           0x4F
 276
 277 /* The lowest and highest voltage allowed for LS1088AQDS */
 278 #define VDD_MV_MIN                      819
 279 #define VDD_MV_MAX                      1212
 280
 281 #define PWM_CHANNEL0                    0x0
 282
 283 /*
 284 * RTC configuration
 285 */
 286 #define RTC
 287 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 288
 289 #ifdef CONFIG_FSL_DSPI
 290 #if !defined(CONFIG_TFABOOT) && \
 291         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 292 #endif
 293 #endif
 294
 295 #define COMMON_ENV \
 296         "kernelheader_addr_r=0x80200000\0"      \
 297         "fdtheader_addr_r=0x80100000\0"         \
 298         "kernel_addr_r=0x81000000\0"            \
 299         "fdt_addr_r=0x90000000\0"               \
 300         "load_addr=0xa0000000\0"
 301
 302 /* Initial environment variables */
 303 #ifdef CONFIG_NXP_ESBC
 304 #undef CONFIG_EXTRA_ENV_SETTINGS
 305 #define CONFIG_EXTRA_ENV_SETTINGS               \
 306         COMMON_ENV                              \
 307         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 308         "loadaddr=0x90100000\0"                 \
 309         "kernel_addr=0x100000\0"                \
 310         "ramdisk_addr=0x800000\0"               \
 311         "ramdisk_size=0x2000000\0"              \
 312         "fdt_high=0xa0000000\0"                 \
 313         "initrd_high=0xffffffffffffffff\0"      \
 314         "kernel_start=0x1000000\0"              \
 315         "kernel_load=0xa0000000\0"              \
 316         "kernel_size=0x2800000\0"               \
 317         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 318         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 319         "sf read 0xa0e00000 0xe00000 0x100000;" \
 320         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 321         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 322         "mcmemsize=0x70000000 \0"
 323 #else /* if !(CONFIG_NXP_ESBC) */
 324 #ifdef CONFIG_TFABOOT
 325 #define QSPI_MC_INIT_CMD                                \
 326         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 327         "sf read 0x80e00000 0xE00000 0x100000;" \
 328         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 329 #define SD_MC_INIT_CMD                          \
 330         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 331         "mmc read 0x80e00000 0x7000 0x800;" \
 332         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 333 #define IFC_MC_INIT_CMD                         \
 334         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 335
 336 #undef CONFIG_EXTRA_ENV_SETTINGS
 337 #define CONFIG_EXTRA_ENV_SETTINGS               \
 338         COMMON_ENV                              \
 339         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 340         "loadaddr=0x90100000\0"                 \
 341         "kernel_addr=0x100000\0"                \
 342         "kernel_addr_sd=0x800\0"                \
 343         "ramdisk_addr=0x800000\0"               \
 344         "ramdisk_size=0x2000000\0"              \
 345         "fdt_high=0xa0000000\0"                 \
 346         "initrd_high=0xffffffffffffffff\0"      \
 347         "kernel_start=0x1000000\0"              \
 348         "kernel_start_sd=0x8000\0"              \
 349         "kernel_load=0xa0000000\0"              \
 350         "kernel_size=0x2800000\0"               \
 351         "kernel_size_sd=0x14000\0"               \
 352         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 353         "sf read 0x80e00000 0xE00000 0x100000;" \
 354         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 355         "mcmemsize=0x70000000 \0"               \
 356         "BOARD=ls1088aqds\0" \
 357         "scriptaddr=0x80000000\0"               \
 358         "scripthdraddr=0x80080000\0"            \
 359         BOOTENV                                 \
 360         "boot_scripts=ls1088aqds_boot.scr\0"    \
 361         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 362         "scan_dev_for_boot_part="               \
 363                 "part list ${devtype} ${devnum} devplist; "     \
 364                 "env exists devplist || setenv devplist 1; "    \
 365                 "for distro_bootpart in ${devplist}; do "       \
 366                         "if fstype ${devtype} "                 \
 367                                 "${devnum}:${distro_bootpart} " \
 368                                 "bootfstype; then "             \
 369                                 "run scan_dev_for_boot; "       \
 370                         "fi; "                                  \
 371                 "done\0"                                        \
 372         "boot_a_script="                                        \
 373                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 374                 "${scriptaddr} ${prefix}${script}; "            \
 375         "env exists secureboot && load ${devtype} "             \
 376                 "${devnum}:${distro_bootpart} "                 \
 377                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 378                 "env exists secureboot "                        \
 379                 "&& esbc_validate ${scripthdraddr};"            \
 380                 "source ${scriptaddr}\0"                        \
 381         "qspi_bootcmd=echo Trying load from qspi..; " \
 382                 "sf probe 0:0; " \
 383                 "sf read 0x80001000 0xd00000 0x100000; " \
 384                 "fsl_mc lazyapply dpl 0x80001000 && " \
 385                 "sf read $kernel_load $kernel_start " \
 386                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 387         "sd_bootcmd=echo Trying load from sd card..; " \
 388                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 389                 "fsl_mc lazyapply dpl 0x80001000 && " \
 390                 "mmc read $kernel_load $kernel_start_sd " \
 391                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 392         "nor_bootcmd=echo Trying load from nor..; " \
 393                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 394                 "cp.b $kernel_start $kernel_load " \
 395                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 396 #else
 397 #if defined(CONFIG_QSPI_BOOT)
 398 #undef CONFIG_EXTRA_ENV_SETTINGS
 399 #define CONFIG_EXTRA_ENV_SETTINGS               \
 400         COMMON_ENV                              \
 401         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 402         "loadaddr=0x90100000\0"                 \
 403         "kernel_addr=0x100000\0"                \
 404         "ramdisk_addr=0x800000\0"               \
 405         "ramdisk_size=0x2000000\0"              \
 406         "fdt_high=0xa0000000\0"                 \
 407         "initrd_high=0xffffffffffffffff\0"      \
 408         "kernel_start=0x1000000\0"              \
 409         "kernel_load=0xa0000000\0"              \
 410         "kernel_size=0x2800000\0"               \
 411         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 412         "sf read 0x80e00000 0xE00000 0x100000;" \
 413         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 414         "mcmemsize=0x70000000 \0"
 415 #elif defined(CONFIG_SD_BOOT)
 416 #undef CONFIG_EXTRA_ENV_SETTINGS
 417 #define CONFIG_EXTRA_ENV_SETTINGS               \
 418         COMMON_ENV                              \
 419         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 420         "loadaddr=0x90100000\0"                 \
 421         "kernel_addr=0x800\0"                \
 422         "ramdisk_addr=0x800000\0"               \
 423         "ramdisk_size=0x2000000\0"              \
 424         "fdt_high=0xa0000000\0"                 \
 425         "initrd_high=0xffffffffffffffff\0"      \
 426         "kernel_start=0x8000\0"              \
 427         "kernel_load=0xa0000000\0"              \
 428         "kernel_size=0x14000\0"               \
 429         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 430         "mmc read 0x80e00000 0x7000 0x800;" \
 431         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 432         "mcmemsize=0x70000000 \0"
 433 #else   /* NOR BOOT */
 434 #undef CONFIG_EXTRA_ENV_SETTINGS
 435 #define CONFIG_EXTRA_ENV_SETTINGS               \
 436         COMMON_ENV                              \
 437         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 438         "loadaddr=0x90100000\0"                 \
 439         "kernel_addr=0x100000\0"                \
 440         "ramdisk_addr=0x800000\0"               \
 441         "ramdisk_size=0x2000000\0"              \
 442         "fdt_high=0xa0000000\0"                 \
 443         "initrd_high=0xffffffffffffffff\0"      \
 444         "kernel_start=0x1000000\0"              \
 445         "kernel_load=0xa0000000\0"              \
 446         "kernel_size=0x2800000\0"               \
 447         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 448         "mcmemsize=0x70000000 \0"
 449 #endif
 450 #endif /* CONFIG_TFABOOT */
 451 #endif /* CONFIG_NXP_ESBC */
 452
 453 #ifdef CONFIG_TFABOOT
 454 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 455                            "env exists secureboot && esbc_halt;;"
 456 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 457                            "env exists secureboot && esbc_halt;;"
 458 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 459                            "env exists secureboot && esbc_halt;;"
 460 #endif
 461
 462 #ifdef CONFIG_FSL_MC_ENET
 463 #define RGMII_PHY1_ADDR         0x1
 464 #define RGMII_PHY2_ADDR         0x2
 465 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 466 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 467 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 468 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 469
 470 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 471 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 472 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 473 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 474 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 475 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 476 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 477 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 478 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 479 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 480 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 481 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 482 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 483 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 484 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 485 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 486
 487 #endif
 488
 489 #define BOOT_TARGET_DEVICES(func) \
 490         func(USB, usb, 0) \
 491         func(MMC, mmc, 0) \
 492         func(SCSI, scsi, 0) \
 493         func(DHCP, dhcp, na)
 494 #include <config_distro_bootcmd.h>
 495
 496 #include <asm/fsl_secure_boot.h>
 497
 498 #endif /* __LS1088A_QDS_H */