windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
evb_ast2500:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
+ vexpress_ca9x4:
+ TEST_PY_BD: "vexpress_ca9x4"
+ TEST_PY_ID: "--id qemu"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"
r2dplus_tulip:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
+ sifive_unleashed_sdcard:
+ TEST_PY_BD: "sifive_unleashed"
+ TEST_PY_ID: "--id sdcard_qemu"
+ sifive_unleashed_spi-nor:
+ TEST_PY_BD: "sifive_unleashed"
+ TEST_PY_ID: "--id spi-nor_qemu"
xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu"
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
+ if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
+ # create sdcard / spi-nor images for sifive unleashed using genimage
+ if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+ mkdir -p root;
+ cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
+ cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
+ rm -rf tmp;
+ genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
+ cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
+ rm -rf tmp;
+ genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
+ cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
+ fi
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
+image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
# We run some tests in different order, to catch some failures quicker.
stages:
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
+ - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
- cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
- cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
- cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
+ # create sdcard / spi-nor images for sifive unleashed using genimage
+ - if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+ mkdir -p root;
+ cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
+ cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
+ rm -rf tmp;
+ genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
+ cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
+ rm -rf tmp;
+ genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
+ cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
+ fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt
TEST_PY_BD: "sandbox_flattree"
<<: *buildman_and_testpy_dfn
+vexpress_ca9x4 test.py:
+ variables:
+ TEST_PY_BD: "vexpress_ca9x4"
+ TEST_PY_ID: "--id qemu"
+ <<: *buildman_and_testpy_dfn
+
integratorcp_cm926ejs test.py:
variables:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id tulip_qemu"
<<: *buildman_and_testpy_dfn
+sifive_unleashed_sdcard test.py:
+ variables:
+ TEST_PY_BD: "sifive_unleashed"
+ TEST_PY_ID: "--id sdcard_qemu"
+ <<: *buildman_and_testpy_dfn
+
+sifive_unleashed_spi-nor test.py:
+ variables:
+ TEST_PY_BD: "sifive_unleashed"
+ TEST_PY_ID: "--id spi-nor_qemu"
+ <<: *buildman_and_testpy_dfn
+
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
+Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Markus Klotzbuecher <mk@denx.de>
config OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
- default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
config SPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in SPL"
depends on SPL
- default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
config LTO
bool "Enable Link Time Optimizations"
depends on ARCH_SUPPORTS_LTO
- default n
help
This option enables Link Time Optimization (LTO), a mechanism which
allows the compiler to optimize between different compilation units.
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
- default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
- depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
- default 0x2000000 if ARCH_ROCKCHIP
+ default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
+ default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S
+ default 0x200000 if ARCH_BMIPS || X86
+ default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S
+ default 0x400000
help
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
config SYS_MALLOC_DEFAULT_TO_INIT
bool "Default malloc to init while reserving the memory for it"
- default n
help
It may happen that one needs to move the dynamic allocation
from one to another memory range, eg. when moving the malloc
Path within the source tree to the linker script to use for the
main U-Boot binary.
+config SYS_LOAD_ADDR
+ hex "Address in memory to use by default"
+ default 0x01000000 if ARCH_SOCFPGA
+ default 0x02000000 if PPC || X86
+ default 0x22000000 if MACH_SUN9I
+ default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
+ default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
+ default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
+ default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
+ default 0x80800000 if ARCH_MX7
+ default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
+ help
+ Address in memory to use as the default safe load address.
+
config ERR_PTR_OFFSET
hex
default 0x0
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
default y if TARGET_TRICORDER
- default n
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
on the Library (independent of the use of the Library in a tool for
writing it). Whether that is true depends on what the Library does
and what the program that uses the Library does.
-
+
1. You may copy and distribute verbatim copies of the Library's
complete source code as you receive it, in any medium, provided that
you conspicuously and appropriately publish on each copy an
F: board/atmel/
F: drivers/cpu/at91_cpu.c
F: drivers/misc/microchip_flexcom.c
+F: include/dt-bindings/mfd/atmel-flexcom.h
F: drivers/timer/mchp-pit64b-timer.c
ARM NEXELL S5P4418
S: Maintained
F: arch/arm/dts/ste-*
F: arch/arm/mach-u8500/
+F: drivers/gpio/nmk_gpio.c
+F: drivers/phy/phy-ab8500-usb.c
+F: drivers/power/pmic/ab8500.c
F: drivers/timer/nomadik-mtu-timer.c
+F: drivers/usb/musb-new/ux500.c
+F: drivers/video/mcde_simple.c
ARM UNIPHIER
S: Orphan (Since 2020-09)
T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
F: drivers/i2c/
+KWBIMAGE / KWBOOT TOOLS
+M: Pali Rohár <pali@kernel.org>
+M: Marek Behún <marek.behun@nic.cz>
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
+F: doc/README.kwbimage
+F: doc/kwboot.1
+F: tools/kwb*
+
LOGGING
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \
- $(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
+ $(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
# Snow Leopards build environment has no longer restrictions as described above
HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc")
KBUILD_HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp")
KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
-# macOS Mojave (10.14.X)
+# macOS Mojave (10.14.X)
# Undefined symbols for architecture x86_64: "_PyArg_ParseTuple"
KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "")
endif
libs-y += net/
libs-y += disk/
libs-y += drivers/
-libs-y += drivers/dma/
-libs-y += drivers/gpio/
-libs-y += drivers/net/
-libs-y += drivers/net/phy/
-libs-y += drivers/power/ \
- drivers/power/domain/ \
- drivers/power/fuel_gauge/ \
- drivers/power/mfd/ \
- drivers/power/pmic/ \
- drivers/power/battery/ \
- drivers/power/regulator/
-libs-y += drivers/spi/
-libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
-libs-y += drivers/serial/
libs-y += drivers/usb/cdns3/
libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
# Use 'make BINMAN_VERBOSE=3' to set vebosity level
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
-# Tell binman whether we have a devicetree for SPL and TPL
-have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL))
-have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL))
-
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \
-a scp-path=$(SCP) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
- -a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \
+ -a spl-dtb=$(CONFIG_SPL_OF_REAL) \
+ -a tpl-dtb=$(CONFIG_SPL_OF_REAL) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
# May be overridden by arch/$(ARCH)/config.mk
ifdef CONFIG_LTO
quiet_cmd_u-boot__ ?= LTO $@
- cmd_u-boot__ ?= \
+ cmd_u-boot__ ?= \
$(CC) -nostdlib -nostartfiles \
$(LTO_FINAL_LDFLAGS) $(c_flags) \
$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
- LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \
else \
return 42; \
LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
- LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \
fi)
endef
- loads U-Boot or (in falcon mode) Linux
-
Configuration Options:
----------------------
Board config to use DDR3L. It can be enabled for SoCs with
DDR3L controllers.
- CONFIG_SYS_FSL_DDR4
- Board config to use DDR4. It can be enabled for SoCs with
- DDR4 controllers.
-
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_PBL_PBI
- It enables addition of RCW (Power on reset configuration) in built image.
- Please refer doc/README.pblimage for more details
-
- CONFIG_SYS_FSL_PBL_RCW
- It adds PBI(pre-boot instructions) commands in u-boot build image.
- PBI commands can be used to configure SoC before it starts the execution.
- Please refer doc/README.pblimage for more details
-
CONFIG_SYS_FSL_DDR_BE
Defines the DDR controller register space as Big Endian
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
- CONFIG_MACH_TYPE [relevant for ARM only][mandatory]
-
- This setting is mandatory for all boards that have only one
- machine type and must be used to specify the machine type
- number as it appears in the ARM machine registry
- (see https://www.arm.linux.org.uk/developer/machines/).
- Only boards that have multiple machine types supported
- in a single configuration file and the machine type is
- runtime discoverable, do not have to use this setting.
-
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
time on others. This setting #define's the initial
value of the "loads_echo" environment variable.
-- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
- CONFIG_KGDB_BAUDRATE
- Select one of the baudrates listed in
- CONFIG_SYS_BAUDRATE_TABLE, see below.
-
- Removal of commands
If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line
Support for National dp8382[01] gigabit chips.
- NETWORK Support (other):
-
- CONFIG_DRIVER_AT91EMAC
- Support for AT91RM9200 EMAC.
-
- CONFIG_RMII
- Define this to use reduced MII inteface
-
- CONFIG_DRIVER_AT91EMAC_QUIET
- If this defined, the driver is quiet.
- The driver doen't show link status messages.
-
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
-- I2C Support: CONFIG_SYS_I2C_LEGACY
-
- Note: This is deprecated in favour of driver model. Use
- CONFIG_DM_I2C instead.
-
- This enable the legacy i2c subsystem, and will allow you to use
- i2c commands at the u-boot command line (as long as you set
- CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
- for defining speed and slave address
- - activate second bus with I2C_SOFT_DECLARATIONS2 define
- CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
- for defining speed and slave address
- - activate third bus with I2C_SOFT_DECLARATIONS3 define
- CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
- for defining speed and slave address
- - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
- CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
- for defining speed and slave address
-
- - drivers/i2c/fsl_i2c.c:
- - activate i2c driver with CONFIG_SYS_I2C_FSL
- define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
- offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
- CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
- bus.
- - If your board supports a second fsl i2c bus, define
- CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
- CONFIG_SYS_FSL_I2C2_SPEED for the speed and
- CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
- second bus.
-
- - drivers/i2c/tegra_i2c.c:
- - activate this driver with CONFIG_SYS_I2C_TEGRA
- - This driver adds 4 i2c buses with a fix speed from
- 100000 and the slave addr 0!
-
- - drivers/i2c/ppc4xx_i2c.c
- - activate this driver with CONFIG_SYS_I2C_PPC4XX
- - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
- - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
-
- - drivers/i2c/i2c_mxc.c
- - activate this driver with CONFIG_SYS_I2C_MXC
- - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
- - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
- - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
- - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
- - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
- - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
- - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
- - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
- - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
- If those defines are not set, default value is 100000
- for speed, and 0 for slave.
-
- - drivers/i2c/rcar_i2c.c:
- - activate this driver with CONFIG_SYS_I2C_RCAR
- - This driver adds 4 i2c buses
-
- - drivers/i2c/sh_i2c.c:
- - activate this driver with CONFIG_SYS_I2C_SH
- - This driver adds from 2 to 5 i2c buses
-
- - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
- - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
- - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
- - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
- - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
- - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
- - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
- - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
- - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
- - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
- - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
-
- - drivers/i2c/omap24xx_i2c.c
- - activate this driver with CONFIG_SYS_I2C_OMAP24XX
- - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
- - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
- - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
- - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
- - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
- - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
- - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
- - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
- - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
- - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
-
- - drivers/i2c/s3c24x0_i2c.c:
- - activate this driver with CONFIG_SYS_I2C_S3C24X0
- - This driver adds i2c buses (11 for Exynos5250, Exynos5420
- 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
- with a fix speed from 100000 and the slave addr 0!
-
- - drivers/i2c/ihs_i2c.c
- - activate this driver with CONFIG_SYS_I2C_IHS
- - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
- - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
- - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
- - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
- - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
- - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
- - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
- - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
- - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
- - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
- - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
- - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
- - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
- - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
- - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
- - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
- - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
- - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
- - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
- - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
- - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
-
- additional defines:
-
+- I2C Support:
CONFIG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
- CONFIG_SYS_NAND_U_BOOT_OFFS
- Location in NAND to read U-Boot from
-
CONFIG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to
This only takes effect if the memory commands are activated
globally (CONFIG_CMD_MEMORY).
-- CONFIG_SKIP_LOWLEVEL_INIT
- [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
- low level initializations (like setting up the memory
- controller) are omitted and/or U-Boot does not
- relocate itself into RAM.
-
- Normally this variable MUST NOT be defined. The only
- exception is when U-Boot is loaded (to RAM) by some
- other boot loader or by a debugger which performs
- these initializations itself.
-
-- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
- [ARM926EJ-S only] This allows just the call to lowlevel_init()
- to be skipped. The normal CP15 init (such as enabling the
- instruction cache) is still performed.
-
- CONFIG_SPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the SPL (as opposed to the TPL or U-Boot
config API
bool "Enable U-Boot API"
- default n
help
This option enables the U-Boot API. See api/README for more information.
config NEEDS_MANUAL_RELOC
bool
+config SYS_CACHE_SHIFT_4
+ bool
+
+config SYS_CACHE_SHIFT_5
+ bool
+
+config SYS_CACHE_SHIFT_6
+ bool
+
+config SYS_CACHE_SHIFT_7
+ bool
+
+config SYS_CACHELINE_SIZE
+ int
+ default 128 if SYS_CACHE_SHIFT_7
+ default 64 if SYS_CACHE_SHIFT_6
+ default 32 if SYS_CACHE_SHIFT_5
+ default 16 if SYS_CACHE_SHIFT_4
+ # Fall-back for MIPS
+ default 32 if MIPS
+
config LINKER_LIST_ALIGN
int
default 32 if SANDBOX
select DM
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
+ select SYS_CACHE_SHIFT_7
select TIMER
config ARM
select NEEDS_MANUAL_RELOC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
+ select SYS_CACHE_SHIFT_4
select SUPPORT_OF_CONTROL
config MICROBLAZE
imply SPL_OF_CONTROL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_TIMER
config SANDBOX
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
+ select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN
imply BITREVERSE
select OF_CONTROL
select PCI
select SUPPORT_OF_CONTROL
+ select SYS_CACHE_SHIFT_6
select TIMER
select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_SPI_FLASH_SUPPORT
- imply SPL_SPI_SUPPORT
+ imply SPL_SPI
imply SPL_OF_CONTROL
imply SPL_TIMER
imply SPL_REGMAP
imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
- imply TPL_SERIAL_SUPPORT
+ imply TPL_SERIAL
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
Note that, its up to the individual architectures to implement
this functionality.
+config SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on ARM || NDS32 || MIPS || RISCV
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config SPL_SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on SPL && (ARM || NDS32 || MIPS || RISCV)
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config TPL_SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on SPL && ARM
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
+config SPL_SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on SPL && ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
+config TPL_SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on TPL && ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"
config CPU_BIG_ENDIAN
bool "Enable Big Endian Mode"
- default n
help
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
bool "Do not enable icache"
- default n
help
Do not enable instruction cache in U-Boot.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
- default n
help
Do not enable data cache in U-Boot.
menuconfig ARC_DBG
bool "ARC debugging"
- default n
if ARC_DBG
config ARC_DBG_IOC_ENABLE
bool "Enable IO coherency unit"
depends on CPU_ARCHS38
- default n
help
Enable IO coherency unit to debug problems with caches and
DMA peripherals.
*/
#define ARCH_DMA_MINALIGN 128
-/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
-
#if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2)
#include <env.h>
#include <image.h>
#include <irq_func.h>
-#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- ulong sp;
-
- /*
- * Booting a (Linux) kernel image
- *
- * Allocate space for command line and board info - the
- * address should be as high as possible within the reach of
- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
- * memory, which means far enough below the current stack
- * pointer.
- */
- sp = get_sp();
- debug("## Current stack ends at 0x%08lx ", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= 4096;
- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
-}
-
static int cleanup_before_linux(void)
{
disable_interrupts();
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
} else {
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/log2.h>
+#include <lmb.h>
#include <asm/arcregs.h>
#include <asm/arc-bcr.h>
#include <asm/cache.h>
__ic_entire_invalidate();
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
typedef unsigned int UHItype __attribute__ ((mode (HI)));
#if MIN_UNITS_PER_WORD > 1
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
#if __SIZEOF_LONG_LONG__ > 4
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
-if ARM64
+config ARM64_CRC32
+ bool "Enable support for CRC32 instruction"
+ depends on ARM64
+ default y
+ help
+ ARMv8 implements dedicated crc32 instruction for crc32 calculation.
+ This is faster than software crc32 calculation. This instruction may
+ not be present on all ARMv8.0, but is always present on ARMv8.1 and
+ newer.
+
config POSITION_INDEPENDENT
bool "Generate position-independent pre-relocation code"
+ depends on ARM64 || CPU_V7A
help
U-Boot expects to be linked to a specific hard-coded address, and to
be loaded to and run from that address. This option lifts that
config INIT_SP_RELATIVE
bool "Specify the early stack pointer relative to the .bss section"
+ depends on ARM64
default n if ARCH_QEMU
default y if POSITION_INDEPENDENT
help
config SYS_INIT_SP_BSS_OFFSET
int "Early stack offset from the .bss base address"
+ depends on ARM64
depends on INIT_SP_RELATIVE
default 524288
help
do not overlap any appended DTB.
config LINUX_KERNEL_IMAGE_HEADER
+ depends on ARM64
bool
help
Place a Linux kernel image header at the start of the U-Boot binary.
image header reports the amount of memory (BSS and similar) that
U-Boot needs to use, but which isn't part of the binary.
-if LINUX_KERNEL_IMAGE_HEADER
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ depends on LINUX_KERNEL_IMAGE_HEADER
hex
help
The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
TEXT_OFFSET value written to the Linux kernel image header.
-endif
-endif
+
+config GICV2
+ bool
+
+config GICV3
+ bool
config GIC_V3_ITS
bool "ARM GICV3 ITS"
config SYS_ICACHE_OFF
bool "Do not enable icache"
- default n
help
Do not enable instruction cache in U-Boot.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
- default n
help
Do not enable data cache in U-Boot.
default 4 if CPU_SA1100
default 8 if ARM64
-config SYS_CACHE_SHIFT_5
- bool
-
-config SYS_CACHE_SHIFT_6
- bool
-
-config SYS_CACHE_SHIFT_7
- bool
-
-config SYS_CACHELINE_SIZE
- int
- default 128 if SYS_CACHE_SHIFT_7
- default 64 if SYS_CACHE_SHIFT_6
- default 32 if SYS_CACHE_SHIFT_5
-
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
config ARM_CORTEX_CPU_IS_UP
bool
- default n
config USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy"
- default y
- depends on !ARM64
+ default y if !ARM64
+ depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
config SPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for SPL"
default y if USE_ARCH_MEMCPY
- depends on !ARM64 && SPL
+ depends on SPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
config TPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for TPL"
default y if USE_ARCH_MEMCPY
- depends on !ARM64 && TPL
+ depends on TPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
+config USE_ARCH_MEMMOVE
+ bool "Use an assembly optimized implementation of memmove" if !ARM64
+ default USE_ARCH_MEMCPY if ARM64
+ depends on ARM64
+ help
+ Enable the generation of an optimized version of memmove.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config SPL_USE_ARCH_MEMMOVE
+ bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
+ default SPL_USE_ARCH_MEMCPY if ARM64
+ depends on SPL && ARM64
+ help
+ Enable the generation of an optimized version of memmove.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config TPL_USE_ARCH_MEMMOVE
+ bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
+ default TPL_USE_ARCH_MEMCPY if ARM64
+ depends on TPL && ARM64
+ help
+ Enable the generation of an optimized version of memmove.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
- default y
- depends on !ARM64
+ default y if !ARM64
+ depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
config SPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for SPL"
default y if USE_ARCH_MEMSET
- depends on !ARM64 && SPL
+ depends on SPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
config TPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for TPL"
default y if USE_ARCH_MEMSET
- depends on !ARM64 && TPL
+ depends on TPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
-config TARGET_ASPENITE
- bool "Support aspenite"
- select CPU_ARM926EJS
- select GPIO_EXTRA_HEADER
-
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
select SPI_FLASH
imply CMD_DM
-config TARGET_FLEA3
- bool "Support flea3"
- select CPU_ARM1136
- select GPIO_EXTRA_HEADER
-
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
+config TARGET_VEXPRESS_CA9X4
+ bool "Support vexpress_ca9x4"
+ select CPU_V7A
+ select PL011_SERIAL
+
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
bool "TI Keystone"
select CMD_POWEROFF
select CPU_V7A
+ select DDR_SPD
select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select SYS_ARCH_TIMER
select ARM64
select DM
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select OF_CONTROL
select ENABLE_ARM_SOC_BOOT0_HOOK
bool "NXP i.MX8M platform"
select ARM64
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
+ select SYS_I2C_MXC
select DM
select SUPPORT_SPL
imply CMD_DM
bool "NXP i.MX8ULP platform"
select ARM64
select DM
+ select MACH_IMX
select OF_CONTROL
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select SUPPORT_SPL
imply CMD_DM
bool "NXP i.MX23 family"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select PL011_SERIAL
select SUPPORT_SPL
-config ARCH_MX25
- bool "NXP MX25"
- select CPU_ARM926EJS
- select GPIO_EXTRA_HEADER
- imply MXC_GPIO
-
config ARCH_MX28
bool "NXP i.MX28 family"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
+ select MACH_IMX
select SUPPORT_SPL
config ARCH_MX31
bool "NXP i.MX31 family"
select CPU_ARM1136
select GPIO_EXTRA_HEADER
+ select MACH_IMX
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7A
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ARCH_MISC_INIT
select CPU_V7A
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
bool "Freescale MX6"
select CPU_V7A
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select BOARD_EARLY_INIT_F
select CPU_V7A
select GPIO_EXTRA_HEADER
+ select MACH_IMX
imply MXC_GPIO
config ARCH_NEXELL
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
+ select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
- select SPL_SERIAL_SUPPORT
+ select SPL_SERIAL
select SPL_SYSRESET
select SPL_WATCHDOG
select SUPPORT_SPL
imply SPL_DM_SPI
imply SPL_DM_SPI_FLASH
imply SPL_LIBDISK_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
- imply SPL_SPI_SUPPORT
+ imply SPL_SPI
imply L2X0_CACHE
config ARCH_SUNXI
select DM
select DM_ETH
select DM_GPIO
+ select DM_I2C if I2C
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI
imply SPL_GPIO
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT if MMC
+ imply SPL_MMC if MMC
imply SPL_POWER
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply USB_GADGET
config ARCH_U8500
select DM_GPIO
select DM_MMC if MMC
select DM_SERIAL
+ select DM_USB_GADGET if DM_USB
select OF_CONTROL
select SYSRESET
select TIMER
+ imply AB8500_USB_PHY
imply ARM_PL180_MMCI
+ imply CLK
+ imply DM_PMIC
imply DM_RTC
+ imply NOMADIK_GPIO
imply NOMADIK_MTU_TIMER
+ imply PHY
imply PL01X_SERIAL
+ imply PMIC_AB8500
imply RTC_PL031
+ imply SYS_THUMB_BUILD
imply SYSRESET_SYSCON
config ARCH_VERSAL
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GICV3
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SOC_DEVICE
bool "Freescale Vybrid"
select CPU_V7A
select GPIO_EXTRA_HEADER
+ select MACH_IMX
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
imply MTD_RAW_NAND
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select FIRMWARE
+ select GICV2
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
+ select GICV2
config TARGET_XENGUEST_ARM64
bool "Xen guest ARM64"
select SSCANF
endchoice
+config SUPPORT_PASSING_ATAGS
+ bool "Support pre-devicetree ATAG-based booting"
+ depends on !ARM64
+ imply SETUP_MEMORY_TAGS
+ help
+ Support for booting older Linux kernels, using ATAGs rather than
+ passing a devicetree. This is option is rarely used, and the
+ semantics are defined at
+ https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
+
+config SETUP_MEMORY_TAGS
+ bool "Pass memory size information via ATAG"
+ depends on SUPPORT_PASSING_ATAGS
+
+config CMDLINE_TAG
+ bool "Pass Linux kernel cmdline via ATAG"
+ depends on SUPPORT_PASSING_ATAGS
+
+config INITRD_TAG
+ bool "Pass initrd starting point and size via ATAG"
+ depends on SUPPORT_PASSING_ATAGS
+
+config REVISION_TAG
+ bool "Pass system revision via ATAG"
+ depends on SUPPORT_PASSING_ATAGS
+
+config SERIAL_TAG
+ bool "Pass system serial number via ATAG"
+ depends on SUPPORT_PASSING_ATAGS
+
+config STATIC_MACH_TYPE
+ bool "Statically define the Machine ID number"
+ help
+ When booting via ATAGs, enable this option if we know the correct
+ machine ID number to use at compile time. Some systems will be
+ passed the number dynamically by whatever loads U-Boot.
+
+config MACH_TYPE
+ int "Machine ID number"
+ depends on STATIC_MACH_TYPE
+ help
+ When booting via ATAGs, the machine type must be passed as a number.
+ For the full list see https://www.arm.linux.org.uk/developer/machines
+
config ARCH_SUPPORT_TFABOOT
bool
config TFABOOT
bool "Support for booting from TF-A"
depends on ARCH_SUPPORT_TFABOOT
- default n
help
Some platforms support the setup of secure registers (for instance
for CPU errata handling) or provide secure services like PSCI.
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-source "arch/arm/mach-imx/mx2/Kconfig"
-
source "arch/arm/mach-imx/mx3/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
-source "board/CarMediaLab/flea3/Kconfig"
-source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
+source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
source "board/broadcom/bcm963158/Kconfig"
$(call cc-option, -march=armv7))
arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
+ifeq ($(CONFIG_ARM64_CRC32),y)
+arch-$(CONFIG_ARM64) =-march=armv8-a+crc
+else
arch-$(CONFIG_ARM64) =-march=armv8-a
+endif
# On Tegra systems we must build SPL for the armv4 core on the device
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
libs-y += arch/arm/mach-imx/
endif
else
PLATFORM_RELFLAGS += -fno-common -ffixed-r9
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+ $(call cc-option,-mgeneral-regs-only) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
# LLVM support
OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
endif
-ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_MACH_IMX
+ifneq ($(CONFIG_IMX_CONFIG),"")
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
INPUTS-y += SPL
INPUTS-y += u-boot.vyb
endif
endif
+endif
EFI_LDS := elf_arm_efi.lds
EFI_CRT0 := crt0_arm_efi.o
obj-y += ../arm11/
obj-$(CONFIG_MX31) += mx31/
-obj-$(CONFIG_MX35) += mx35/
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y += generic.o
-obj-y += timer.o
-obj-y += mx35_sdram.o
-obj-y += relocate.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <div64.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC_IMX
-#include <fsl_esdhc_imx.h>
-#endif
-#include <netdev.h>
-#include <spl.h>
-
-#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
-#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
-#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
-#define CLK_CODE_PATH(c) ((c) & 0xFF)
-
-#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static int g_clk_mux_auto[8] = {
- CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
- CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
-};
-
-static int g_clk_mux_consumer[16] = {
- CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
- -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
- CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
- -1, -1, CLK_CODE(4, 2, 0), -1,
-};
-
-static int hsp_div_table[3][16] = {
- {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
- {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
- {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
-};
-
-u32 get_cpu_rev(void)
-{
- int reg;
- struct iim_regs *iim =
- (struct iim_regs *)IIM_BASE_ADDR;
- reg = readl(&iim->iim_srev);
- if (!reg) {
- reg = readw(ROMPATCH_REV);
- reg <<= 4;
- } else {
- reg += CHIP_REV_1_0;
- }
-
- return 0x35000 + (reg & 0xFF);
-}
-
-static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
-{
- int *pclk_mux;
- if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
- pclk_mux = g_clk_mux_consumer +
- ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
- MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
- } else {
- pclk_mux = g_clk_mux_auto +
- ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
- MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
- }
-
- if ((*pclk_mux) == -1)
- return -1;
-
- if (fi && fd) {
- if (!CLK_CODE_PATH(*pclk_mux)) {
- *fi = *fd = 1;
- return CLK_CODE_ARM(*pclk_mux);
- }
- if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
- *fi = 3;
- *fd = 4;
- } else {
- *fi = 2;
- *fd = 3;
- }
- }
- return CLK_CODE_ARM(*pclk_mux);
-}
-
-static int get_ahb_div(u32 pdr0)
-{
- int *pclk_mux;
-
- pclk_mux = g_clk_mux_consumer +
- ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
- MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-
- if ((*pclk_mux) == -1)
- return -1;
-
- return CLK_CODE_AHB(*pclk_mux);
-}
-
-static u32 decode_pll(u32 reg, u32 infreq)
-{
- u32 mfi = (reg >> 10) & 0xf;
- s32 mfn = reg & 0x3ff;
- u32 mfd = (reg >> 16) & 0x3ff;
- u32 pd = (reg >> 26) & 0xf;
-
- mfi = mfi <= 5 ? 5 : mfi;
- mfn = mfn >= 512 ? mfn - 1024 : mfn;
- mfd += 1;
- pd += 1;
-
- return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
- mfd * pd);
-}
-
-static u32 get_mcu_main_clk(void)
-{
- u32 arm_div = 0, fi = 0, fd = 0;
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
- arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
- fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
- return fi / (arm_div * fd);
-}
-
-static u32 get_ipg_clk(void)
-{
- u32 freq = get_mcu_main_clk();
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
- u32 pdr0 = readl(&ccm->pdr0);
-
- return freq / (get_ahb_div(pdr0) * 2);
-}
-
-static u32 get_ipg_per_clk(void)
-{
- u32 freq = get_mcu_main_clk();
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
- u32 pdr0 = readl(&ccm->pdr0);
- u32 pdr4 = readl(&ccm->pdr4);
- u32 div;
- if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
- div = CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_PER0_PODF_MASK,
- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
- } else {
- div = CCM_GET_DIVIDER(pdr0,
- MXC_CCM_PDR0_PER_PODF_MASK,
- MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
- div *= get_ahb_div(pdr0);
- }
- return freq / div;
-}
-
-u32 imx_get_uartclk(void)
-{
- u32 freq;
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
- u32 pdr4 = readl(&ccm->pdr4);
-
- if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
- freq = get_mcu_main_clk();
- else
- freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
- freq /= CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_UART_PODF_MASK,
- MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
- return freq;
-}
-
-unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
-{
- u32 nfc_pdf, hsp_podf;
- u32 pll, ret_val = 0, usb_podf;
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- u32 reg = readl(&ccm->pdr0);
- u32 reg4 = readl(&ccm->pdr4);
-
- reg |= 0x1;
-
- switch (clk) {
- case CPU_CLK:
- ret_val = get_mcu_main_clk();
- break;
- case AHB_CLK:
- ret_val = get_mcu_main_clk();
- break;
- case HSP_CLK:
- if (reg & CLKMODE_CONSUMER) {
- hsp_podf = (reg >> 20) & 0x3;
- pll = get_mcu_main_clk();
- hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
- if (hsp_podf > 0) {
- ret_val = pll / hsp_podf;
- } else {
- puts("mismatch HSP with ARM clock setting\n");
- ret_val = 0;
- }
- } else {
- ret_val = get_mcu_main_clk();
- }
- break;
- case IPG_CLK:
- ret_val = get_ipg_clk();
- break;
- case IPG_PER_CLK:
- ret_val = get_ipg_per_clk();
- break;
- case NFC_CLK:
- nfc_pdf = (reg4 >> 28) & 0xF;
- pll = get_mcu_main_clk();
- /* AHB/nfc_pdf */
- ret_val = pll / (nfc_pdf + 1);
- break;
- case USB_CLK:
- usb_podf = (reg4 >> 22) & 0x3F;
- if (reg4 & 0x200)
- pll = get_mcu_main_clk();
- else
- pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
-
- ret_val = pll / (usb_podf + 1);
- break;
- default:
- printf("Unknown clock: %d\n", clk);
- break;
- }
-
- return ret_val;
-}
-unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
- u32 mpdr2 = readl(&ccm->pdr2);
- u32 mpdr3 = readl(&ccm->pdr3);
- u32 mpdr4 = readl(&ccm->pdr4);
-
- switch (clk) {
- case UART1_BAUD:
- case UART2_BAUD:
- case UART3_BAUD:
- clk_sel = mpdr3 & (1 << 14);
- pdf = (mpdr4 >> 10) & 0x3F;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
- break;
- case SSI1_BAUD:
- pre_pdf = (mpdr2 >> 24) & 0x7;
- pdf = mpdr2 & 0x3F;
- clk_sel = mpdr2 & (1 << 6);
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- case SSI2_BAUD:
- pre_pdf = (mpdr2 >> 27) & 0x7;
- pdf = (mpdr2 >> 8) & 0x3F;
- clk_sel = mpdr2 & (1 << 6);
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- case CSI_BAUD:
- clk_sel = mpdr2 & (1 << 7);
- pdf = (mpdr2 >> 16) & 0x3F;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
- break;
- case MSHC_CLK:
- pre_pdf = readl(&ccm->pdr1);
- clk_sel = (pre_pdf & 0x80);
- pdf = (pre_pdf >> 22) & 0x3F;
- pre_pdf = (pre_pdf >> 28) & 0x7;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- case ESDHC1_CLK:
- clk_sel = mpdr3 & 0x40;
- pdf = mpdr3 & 0x3F;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
- break;
- case ESDHC2_CLK:
- clk_sel = mpdr3 & 0x40;
- pdf = (mpdr3 >> 8) & 0x3F;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
- break;
- case ESDHC3_CLK:
- clk_sel = mpdr3 & 0x40;
- pdf = (mpdr3 >> 16) & 0x3F;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
- break;
- case SPDIF_CLK:
- clk_sel = mpdr3 & 0x400000;
- pre_pdf = (mpdr3 >> 29) & 0x7;
- pdf = (mpdr3 >> 23) & 0x3F;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- default:
- printf("%s(): This clock: %d not supported yet\n",
- __func__, clk);
- break;
- }
-
- return ret_val;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_AHB_CLK:
- break;
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_IPG_PERCLK:
- case MXC_I2C_CLK:
- return get_ipg_per_clk();
- case MXC_UART_CLK:
- return imx_get_uartclk();
- case MXC_ESDHC1_CLK:
- return mxc_get_peri_clock(ESDHC1_CLK);
- case MXC_ESDHC2_CLK:
- return mxc_get_peri_clock(ESDHC2_CLK);
- case MXC_ESDHC3_CLK:
- return mxc_get_peri_clock(ESDHC3_CLK);
- case MXC_USB_CLK:
- return mxc_get_main_clock(USB_CLK);
- case MXC_FEC_CLK:
- return get_ipg_clk();
- case MXC_CSPI_CLK:
- return get_ipg_clk();
- }
- return -1;
-}
-
-#ifdef CONFIG_FEC_MXC
-/*
- * The MX35 has no fuse for MAC, return a NULL MAC
- */
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- memset(mac, 0, 6);
-}
-
-u32 imx_get_fecclk(void)
-{
- return mxc_get_clock(MXC_IPG_CLK);
-}
-#endif
-
-int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- u32 cpufreq = get_mcu_main_clk();
- printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
- printf("ipg clock : %dHz\n", get_ipg_clk());
- printf("ipg per clock : %dHz\n", get_ipg_per_clk());
- printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
-
- return 0;
-}
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
- "display clocks",
- ""
-);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_reset_cause(void)
-{
- /* read RCSR register from CCM module */
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- u32 cause = readl(&ccm->rcsr) & 0x0F;
-
- switch (cause) {
- case 0x0000:
- return "POR";
- case 0x0002:
- return "JTAG";
- case 0x0004:
- return "RST";
- case 0x0008:
- return "WDOG";
- default:
- return "unknown reset";
- }
-}
-
-int print_cpuinfo(void)
-{
- u32 srev = get_cpu_rev();
-
- printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
- (srev & 0xF0) >> 4, (srev & 0x0F),
- get_mcu_main_clk() / 1000000);
-
- printf("Reset cause: %s\n", get_reset_cause());
-
- return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(struct bd_info *bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
- rc = fecmxc_initialize(bis);
-#endif
-
- return rc;
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(struct bd_info *bis)
-{
- return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#else
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
-#endif
-#endif
- return 0;
-}
-
-#define RCSR_MEM_CTL_WEIM 0
-#define RCSR_MEM_CTL_NAND 1
-#define RCSR_MEM_CTL_ATA 2
-#define RCSR_MEM_CTL_EXPANSION 3
-#define RCSR_MEM_TYPE_NOR 0
-#define RCSR_MEM_TYPE_ONENAND 2
-#define RCSR_MEM_TYPE_SD 0
-#define RCSR_MEM_TYPE_I2C 2
-#define RCSR_MEM_TYPE_SPI 3
-
-u32 spl_boot_device(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- u32 rcsr = readl(&ccm->rcsr);
- u32 mem_type, mem_ctl;
-
- /* In external mode, no boot device is returned */
- if ((rcsr >> 10) & 0x03)
- return BOOT_DEVICE_NONE;
-
- mem_ctl = (rcsr >> 25) & 0x03;
- mem_type = (rcsr >> 23) & 0x03;
-
- switch (mem_ctl) {
- case RCSR_MEM_CTL_WEIM:
- switch (mem_type) {
- case RCSR_MEM_TYPE_NOR:
- return BOOT_DEVICE_NOR;
- case RCSR_MEM_TYPE_ONENAND:
- return BOOT_DEVICE_ONENAND;
- default:
- return BOOT_DEVICE_NONE;
- }
- case RCSR_MEM_CTL_NAND:
- return BOOT_DEVICE_NAND;
- case RCSR_MEM_CTL_EXPANSION:
- switch (mem_type) {
- case RCSR_MEM_TYPE_SD:
- return BOOT_DEVICE_MMC1;
- case RCSR_MEM_TYPE_I2C:
- return BOOT_DEVICE_I2C;
- case RCSR_MEM_TYPE_SPI:
- return BOOT_DEVICE_SPI;
- default:
- return BOOT_DEVICE_NONE;
- }
- }
-
- return BOOT_DEVICE_NONE;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
- */
-
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <linux/types.h>
-#include <asm/arch/sys_proto.h>
-
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_PRECHARGE 0x00000400
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-enum {
- SMODE_NORMAL = 0,
- SMODE_PRECHARGE,
- SMODE_AUTO_REFRESH,
- SMODE_LOAD_REG,
- SMODE_MANUAL_REFRESH
-};
-
-#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
-
-static inline void dram_wait(unsigned int count)
-{
- volatile unsigned int wait = count;
-
- while (wait--)
- ;
-
-}
-
-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
- u32 row, u32 col, u32 dsize, u32 refresh)
-{
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
- u32 *cfg_reg, *ctl_reg;
- u32 val;
- u32 ctlval;
-
- switch (start_address) {
- case CSD0_BASE_ADDR:
- cfg_reg = &esdc->esdcfg0;
- ctl_reg = &esdc->esdctl0;
- break;
- case CSD1_BASE_ADDR:
- cfg_reg = &esdc->esdcfg1;
- ctl_reg = &esdc->esdctl1;
- break;
- default:
- return;
- }
-
- /* The MX35 supports 11 up to 14 rows */
- if (row < 11 || row > 14 || col < 8 || col > 10)
- return;
- ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
-
- /* Initialize MISC register for DDR2 */
- val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
- ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
- writel(val, &esdc->esdmisc);
- val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
- writel(val, &esdc->esdmisc);
-
- /*
- * according to DDR2 specs, wait a while before
- * the PRECHARGE_ALL command
- */
- dram_wait(0x20000);
-
- /* Load DDR2 config and timing */
- writel(ddr2_config, cfg_reg);
-
- /* Precharge ALL */
- writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
- ctl_reg);
- writel(0xda, start_address + ESDCTL_PRECHARGE);
-
- /* Load mode */
- writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
- ctl_reg);
- writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
- writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
- writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
- /* Precharge ALL */
- writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
- ctl_reg);
- writel(0xda, start_address + ESDCTL_PRECHARGE);
-
- /* Set mode auto refresh : at least two refresh are required */
- writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
- ctl_reg);
- writel(0xda, start_address);
- writel(0xda, start_address);
-
- writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
- ctl_reg);
- writeb(0xda, start_address + ESDCTL_DDR2_MR);
- writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
- /* OCD mode exit */
- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
- /* Set normal mode */
- writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
- ctl_reg);
-
- dram_wait(0x20000);
-
- /* Do not set delay lines, only for MDDR */
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * relocate - i.MX35-specific vector relocation
- *
- * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <linux/linkage.h>
-
-/*
- * The i.MX35 SoC is very specific with respect to exceptions: it
- * does not provide RAM at the high vectors address (0xFFFF0000),
- * thus only the low address (0x00000000) is useable; but that is
- * in ROM, so let's avoid relocating the vectors.
- */
- .section .text.relocate_vectors,"ax",%progbits
-
-ENTRY(relocate_vectors)
-
- bx lr
-
-ENDPROC(relocate_vectors)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/ptrace.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-
-/*
- * nothing really to do with interrupts, just starts up a counter.
- * The 32KHz 32-bit timer overruns in 134217 seconds
- */
-int timer_init(void)
-{
- int i;
- struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
- struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
-
- /* setup GP Timer 1 */
- writel(GPTCR_SWR, &gpt->ctrl);
-
- writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
-
- for (i = 0; i < 100; i++)
- writel(0, &gpt->ctrl); /* We have no udelay by now */
- writel(0, &gpt->pre); /* prescaler = 1 */
- /* Freerun Mode, 32KHz input */
- writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
- &gpt->ctrl);
- writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
-
- return 0;
-}
msr cpsr,r0
/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
*
*************************************************************************
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
mov lr, ip /* restore link */
#endif
mov pc, lr /* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
*************************************************************************
*/
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
mov lr, ip
mov pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
orr r0, r0, #0xd3
msr cpsr, r0
-#if defined(CONFIG_AT91RM9200DK)
- /*
- * relocate exception table
- */
- ldr r0, =_start
- ldr r1, =0x0
- mov r2, #16
-copyex:
- subs r2, r2, #1
- ldr r3, [r0], #4
- str r3, [r1], #4
- bne copyex
-#endif
-
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
mov lr, ip
#endif
mov pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
endif
endif
-obj-$(CONFIG_ARMADA100) += armada100/
-obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-
-obj-y = cpu.o timer.o dram.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct armd1cpu_registers *cpuregs =
- (struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
- struct armd1apb1_registers *apb1clkres =
- (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-
- struct armd1mpmu_registers *mpmu =
- (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-
- /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Enable Clocks for all hardware units */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on AIB and AIB-APB Functional clock */
- writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
-
- /* ensure L2 cache is not mapped as SRAM */
- val = readl(&cpuregs->cpu_conf);
- val = val & ~(L2C_RAM_SEL);
- writel(val, &cpuregs->cpu_conf);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apb1clkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable general I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
- writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
-
- /* Enable power I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
- writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
-#endif
-
- /*
- * Enable Functional and APB clock at 14.7456MHz
- * for configured UART console
- */
-#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
- writel(UARTCLK14745KHZ, &apb1clkres->uart3);
-#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
- writel(UARTCLK14745KHZ, &apb1clkres->uart2);
-#else
- writel(UARTCLK14745KHZ, &apb1clkres->uart1);
-#endif
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct armd1cpu_registers *cpuregs =
- (struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * ARMADA100 DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet Appendix A.17
- */
-struct armd1ddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct armd1ddr_registers {
- u8 pad[0x100 - 0x000];
- struct armd1ddr_map_registers mmap[2];
-};
-
-/*
- * armd1_sdram_base - reads SDRAM Base Address Register
- */
-u32 armd1_sdram_base(int chip_sel)
-{
- struct armd1ddr_registers *ddr_regs =
- (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * armd1_sdram_size - reads SDRAM size
- */
-u32 armd1_sdram_size(int chip_sel)
-{
- struct armd1ddr_registers *ddr_regs =
- (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = armd1_sdram_base(i);
- gd->bd->bi_dram[i].size = armd1_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /* If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-int dram_init_banksize(void)
-{
- dram_init();
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <time.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-/*
- * Timer registers
- * Refer Section A.6 in Datasheet
- */
-struct armd1tmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr;
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/* For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct armd1tmr_registers *armd1timers =
- (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
- volatile int loop=100;
-
- writel(COUNT_RD_REQ, &armd1timers->cvwr);
- while (loop--);
- return(readl(&armd1timers->cvwr));
-}
-
-static ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime);
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct armd1apb1_registers *apb1clkres =
- (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
- struct armd1tmr_registers *armd1timers =
- (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-
- /* Enable Timer clock at 3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &armd1timers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &armd1timers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &armd1timers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &armd1timers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu(void)
-{
- struct armd1mpmu_registers *mpmu =
- (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
- struct armd1tmr_registers *armd1timers =
- (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
- readl(&mpmu->wdtpcr);
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
- readl(&mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &armd1timers->wfar);
- writel(TMP_WSAR, &armd1timers->wsar);
- writel(0, &armd1timers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &armd1timers->wfar);
- writel(TMP_WSAR, &armd1timers->wsar);
- writel(0xf, &armd1timers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &armd1timers->wfar);
- writel(TMP_WSAR, &armd1timers->wsar);
- writel(0x3, &armd1timers->wdt_match_en);
-
- while(1);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
dcache_enable();
#endif
}
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on mx27/generic.c:
- * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <div64.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <vsprintf.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch-imx/cpu.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-#include <fsl_esdhc_imx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-/*
- * get the system pll clock in Hz
- *
- * mfi + mfn / (mfd +1)
- * f = 2 * f_ref * --------------------
- * pd + 1
- */
-static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
-{
- unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
- & CCM_PLL_MFI_MASK;
- int mfn = (pll >> CCM_PLL_MFN_SHIFT)
- & CCM_PLL_MFN_MASK;
- unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
- & CCM_PLL_MFD_MASK;
- unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
- & CCM_PLL_PD_MASK;
-
- mfi = mfi <= 5 ? 5 : mfi;
- mfn = mfn >= 512 ? mfn - 1024 : mfn;
- mfd += 1;
- pd += 1;
-
- return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
- mfd * pd);
-}
-
-static ulong imx_get_mpllclk(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong fref = MXC_HCLK;
-
- return imx_decode_pll(readl(&ccm->mpctl), fref);
-}
-
-static ulong imx_get_upllclk(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong fref = MXC_HCLK;
-
- return imx_decode_pll(readl(&ccm->upctl), fref);
-}
-
-static ulong imx_get_armclk(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong cctl = readl(&ccm->cctl);
- ulong fref = imx_get_mpllclk();
- ulong div;
-
- if (cctl & CCM_CCTL_ARM_SRC)
- fref = lldiv((u64) fref * 3, 4);
-
- div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
- & CCM_CCTL_ARM_DIV_MASK) + 1;
-
- return fref / div;
-}
-
-static ulong imx_get_ahbclk(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong cctl = readl(&ccm->cctl);
- ulong fref = imx_get_armclk();
- ulong div;
-
- div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
- & CCM_CCTL_AHB_DIV_MASK) + 1;
-
- return fref / div;
-}
-
-static ulong imx_get_ipgclk(void)
-{
- return imx_get_ahbclk() / 2;
-}
-
-static ulong imx_get_perclk(int clk)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
- imx_get_ahbclk();
- ulong div;
-
- div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
- div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
-
- return fref / div;
-}
-
-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
- ulong div = (fref + freq - 1) / freq;
-
- if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
- return -EINVAL;
-
- clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
- CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
- div << CCM_PERCLK_SHIFT(clk));
- if (from_upll)
- setbits_le32(&ccm->mcr, 1 << clk);
- else
- clrbits_le32(&ccm->mcr, 1 << clk);
- return 0;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- if (clk >= MXC_CLK_NUM)
- return -1;
- switch (clk) {
- case MXC_ARM_CLK:
- return imx_get_armclk();
- case MXC_AHB_CLK:
- return imx_get_ahbclk();
- case MXC_IPG_CLK:
- case MXC_CSPI_CLK:
- case MXC_FEC_CLK:
- return imx_get_ipgclk();
- default:
- return imx_get_perclk(clk);
- }
-}
-
-u32 get_cpu_rev(void)
-{
- u32 srev;
- u32 system_rev = 0x25000;
-
- /* read SREV register from IIM module */
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- srev = readl(&iim->iim_srev);
-
- switch (srev) {
- case 0x00:
- system_rev |= CHIP_REV_1_0;
- break;
- case 0x01:
- system_rev |= CHIP_REV_1_1;
- break;
- case 0x02:
- system_rev |= CHIP_REV_1_2;
- break;
- default:
- system_rev |= 0x8000;
- break;
- }
-
- return system_rev;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_reset_cause(void)
-{
- /* read RCSR register from CCM module */
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- u32 cause = readl(&ccm->rcsr) & 0x0f;
-
- if (cause == 0)
- return "POR";
- else if (cause == 1)
- return "RST";
- else if ((cause & 2) == 2)
- return "WDOG";
- else if ((cause & 4) == 4)
- return "SW RESET";
- else if ((cause & 8) == 8)
- return "JTAG";
- else
- return "unknown reset";
-
-}
-
-int print_cpuinfo(void)
-{
- char buf[32];
- u32 cpurev = get_cpu_rev();
-
- printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
- (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
- ((cpurev & 0x8000) ? " unknown" : ""),
- strmhz(buf, imx_get_armclk()));
- printf("Reset cause: %s\n", get_reset_cause());
- return 0;
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(struct bd_info *bis)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- ulong val;
-
- val = readl(&ccm->cgr0);
- val |= (1 << 23);
- writel(val, &ccm->cgr0);
- return fecmxc_initialize(bis);
-}
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#else
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
-#endif
-#endif
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(struct bd_info *bis)
-{
- return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- int i;
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[0];
- struct fuse_bank0_regs *fuse =
- (struct fuse_bank0_regs *)bank->fuse_regs;
-
- for (i = 0; i < 6; i++)
- mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif /* CONFIG_FEC_MXC */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * relocate - i.MX25-specific vector relocation
- *
- * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <linux/linkage.h>
-
-/*
- * The i.MX25 SoC is very specific with respect to exceptions: it
- * does not provide RAM at the high vectors address (0xFFFF0000),
- * thus only the low address (0x00000000) is useable; but that is
- * in ROM, so let's avoid relocating the vectors.
- */
- .section .text.relocate_vectors,"ax",%progbits
-
-ENTRY(relocate_vectors)
-
- bx lr
-
-ENDPROC(relocate_vectors)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu(void)
-{
- struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
- /* Disable watchdog and set Time-Out field to 0 */
- writew(0, ®s->wcr);
-
- /* Write Service Sequence */
- writew(WSR_UNLOCK1, ®s->wsr);
- writew(WSR_UNLOCK2, ®s->wsr);
-
- /* Enable watchdog */
- writew(WCR_WDE, ®s->wcr);
-
- while (1) ;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- * Add support for MX25
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/ptrace.h>
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32KHz 32-bit timer overruns in 134217 seconds */
-int timer_init(void)
-{
- int i;
- struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
- /* setup GP Timer 1 */
- writel(GPT_CTRL_SWR, &gpt->ctrl);
-
- writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
-
- for (i = 0; i < 100; i++)
- writel(0, &gpt->ctrl); /* We have no udelay by now */
- writel(0, &gpt->pre); /* prescaler = 1 */
- /* Freerun Mode, 32KHz input */
- writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
- &gpt->ctrl);
- writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
-
- return 0;
-}
DECLARE_GLOBAL_DATA_PTR;
static gd_t gdata __section(".data");
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
static struct bd_info bdata __section(".data");
#endif
static void mxs_spl_console_init(void)
{
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
gd->bd = &bdata;
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
*
*************************************************************************
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush D cache before disabling it
#endif
mcr p15, 0, r0, c1, c0, 0
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov lr, r4 /* restore link */
#endif
mov pc, lr /* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Go setup Memory and board specific bits prior to relocation.
*/
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
-ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
+ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
+ select SYS_I2C_MXC
imply CMD_PCI
imply SCSI
imply SCSI_AHCI
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
sys_info->freq_systembus = sysclk;
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
return BOOT_DEVICE_MMC1;
#endif
return BOOT_DEVICE_NAND;
{
return psci_context_id[cpu];
}
-
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
+#ifdef CONFIG_POSITION_INDEPENDENT
+ /*
+ * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
+ * executed at a different address than it was linked at.
+ */
+pie_fixup:
+ adr r0, reset /* r0 <- Runtime value of reset label */
+ ldr r1, =reset /* r1 <- Linked value of reset label */
+ subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */
+ beq pie_fixup_done
+
+ adr r0, pie_fixup
+ ldr r1, _rel_dyn_start_ofs
+ add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */
+ ldr r1, _rel_dyn_end_ofs
+ add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */
+
+pie_fix_loop:
+ ldr r0, [r2] /* r0 <- Link location */
+ ldr r1, [r2, #4] /* r1 <- fixup */
+ cmp r1, #23 /* relative fixup? */
+ bne pie_skip_reloc
+
+ /* relative fix: increase location by offset */
+ add r0, r4
+ ldr r1, [r0]
+ add r1, r4
+ str r1, [r0]
+ str r0, [r2]
+ add r2, #8
+pie_skip_reloc:
+ cmp r2, r3
+ blo pie_fix_loop
+pie_fixup_done:
+#endif
+
#ifdef CONFIG_ARMV7_LPAE
/*
* check for Hypervisor support
#endif
/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#ifdef CONFIG_CPU_V7A
bl cpu_init_cp15
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
#endif
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers
b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
+
+#if CONFIG_POSITION_INDEPENDENT
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - pie_fixup
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - pie_fixup
+#endif
config ARMV8_SPL_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
depends on SPL
- default n
help
The default exception vector table is only used for the crash
dump, but still takes quite a lot of space in the image size.
config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
- default n
help
PSCI is Power State Coordination Interface defined by ARM.
The PSCI in U-boot provides a general framework and each platform
config ARMV8_EA_EL3_FIRST
bool "External aborts and SError interrupt exception are taken in EL3"
- default n
help
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
- and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
+ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
+ ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
+ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
- mov x3, #0x3ff
- and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
clz w5, w3 /* bit position of #ways */
- mov x4, #0x7fff
- and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
- lsr x11, x10, #24
- and x11, x11, #0x7 /* x11 <- loc */
+ ubfx x11, x10, #24, #3 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
/* x15 <- return address */
loop_level:
- lsl x12, x0, #1
- add x12, x12, x0 /* x0 <- tripled cache level */
+ add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
lsr x12, x10, x12
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
- lsr x3, x3, #16
- and x3, x3, #0xf
+ ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */
.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
- ubfm x3, x3, #16, #19
+ ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
- .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
- .word 0xe5901008 // ldr r1, [r0, #8]
- .word 0xe129f001 // msr CPSR_fc, r1
+ .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
+ .word 0xe5901008 // ldr r1, [r0, #8]
+ .word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
- .word 0xe590d000 // ldr sp, [r0]
- .word 0xe590e004 // ldr lr, [r0, #4]
- .word 0xe5901010 // ldr r1, [r0, #16]
- .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
- .word 0xe590100c // ldr r1, [r0, #12]
- .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
+ .word 0xe590d000 // ldr sp, [r0]
+ .word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901010 // ldr r1, [r0, #16]
+ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
+ .word 0xe590100c // ldr r1, [r0, #12]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
- .word 0xe12fff1e // bx lr ; return to FEL
+ .word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply CMD_PCI
+ imply ID_EEPROM
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ imply ID_EEPROM
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LS1088A
bool
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
+ imply ID_EEPROM
imply SCSI
+ imply SPL_SYS_I2C_LEGACY
imply PANIC_HANG
config ARCH_LS2080A
select ARM_ERRATA_833471
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
+ imply ID_EEPROM
imply PANIC_HANG
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
+ imply ID_EEPROM
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config FSL_LSCH2
bool
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
config FSPI_AHB_EN_4BYTE
bool "Enable 4-byte Fast Read command for AHB mode"
- default n
help
The default setting for FlexSPI AHB bus just supports 3-byte addressing.
But some FlexSPI flash sizes are up to 64MBytes.
#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
- * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+ * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
pre-silicon platforms (simulator and emulator):
-------------------------
- | FIT Image |
+ | FIT Image |
| (linux + DTB + RFS) |
------------------------- ----> 0x0120_0000
- | Debug Server FW |
+ | Debug Server FW |
------------------------- ----> 0x00C0_0000
- | AIOP FW |
+ | AIOP FW |
------------------------- ----> 0x0070_0000
- | MC FW |
+ | MC FW |
------------------------- ----> 0x006C_0000
- | MC DPL Blob |
+ | MC DPL Blob |
------------------------- ----> 0x0020_0000
- | BootLoader + Env|
+ | BootLoader + Env|
------------------------- ----> 0x0000_1000
- | PBI |
+ | PBI |
------------------------- ----> 0x0000_0080
- | RCW |
+ | RCW |
------------------------- ----> 0x0000_0000
32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
----------------------------------------- ----> 0x5_8790_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8510_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_84F0_0000 | 64K
| Debug Server FW (2M) | | Alt
----------------------------------------- ----> 0x5_84D0_0000 | Bank
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8490_0000 (vbank4)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8480_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8470_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8430_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8420_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8410_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8400_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8390_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8110_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_80F0_0000 | 64K
| Debug Server FW (2M) | | Bank
----------------------------------------- ----> 0x5_80D0_0000 |
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8090_0000 (vbank0)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8080_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8070_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8030_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8020_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8010_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8000_0000 ---
128-MB NOR flash layout for QDS and RDB boards
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x 10GBase-R supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
- Two PLLs per four-lane SerDes
- Support for 10G operation
- Ethernet interfaces by FMan
- - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+ - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
Single WRIOP tile supporting 130Gbps using 18 MACs
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
- Support for XFI (and 10GBase-KR)
+ Support for 10GBase-R (and 10GBase-KR)
Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
Ethernet interfaces
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
- Support for XFI (and 10GBase-KR)
+ Support for 10GBase-R (and 10GBase-KR)
Support for CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
#endif
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
void *offset;
sys_info->freq_systembus = sysclk;
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus2 = get_board_ddr_clk();
#endif
#else
sys_info->freq_ddrbus = sysclk;
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
- * placeholders.
+ * placeholders.
*/
.macro tzasc_prog, xreg
mov x16, #0x10000
mul x14, \xreg, x16
add x14, x14,x12
- mov x1, #0x8
+ mov x1, #0x8
add x1, x1, x14
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/*
- * LS1044A/1048A support only one XFI port
+ * LS1044A/1048A support only one 10GBase-R port
* Disable MAC1 for LS1044A/1048A
*/
if (serdes == FSL_SRDS_1 && lane == 2) {
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
u8 __iomem *ptr;
#ifdef I2C1_BASE_ADDR
ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
4:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
switch_el x7, _dead_loop, 0f, _dead_loop
-0: armv8_switch_to_el1_m x4, x6, x7
+0: armv8_switch_to_el1_m x4, x6, x7, x9
#else
switch_el x7, 0f, _dead_loop, _dead_loop
0: armv8_switch_to_el2_m x4, x6, x7
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
return BOOT_DEVICE_MMC1;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
preloader_console_init();
spl_set_bd();
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
#ifdef CONFIG_SPL_I2C
i2c_init_all();
#endif
* now, jump to the address saved in x4.
*/
br x4
-1: armv8_switch_to_el1_m x4, x5, x6
+1: armv8_switch_to_el1_m x4, x5, x6, x7
ENDPROC(armv8_switch_to_el1)
.popsection
HYPERCALL2(event_channel_op);
HYPERCALL2(hvm_op);
HYPERCALL2(memory_op);
-
orr r0,r0,#0xd3
msr cpsr,r0
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
*
*************************************************************************
*/
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
cpu_init_crit:
/*
* flush v4 I/D caches
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
/*
* Enable MMU to use DCache as DRAM.
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
ldr r1, cpuspeed
str r1, [r0, #PPCR]
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
s5p4418-nanopi2.dtb
dtb-$(CONFIG_ARCH_MESON) += \
+ meson-axg-s400.dtb \
+ meson-axg-jethome-jethub-j100.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
- meson-gxl-s905x-p212.dtb \
meson-gxl-s805x-libretech-ac.dtb \
+ meson-gxl-s905d-libretech-pc.dtb \
+ meson-gxl-s905w-jethome-jethub-j80.dtb \
+ meson-gxl-s905x-khadas-vim.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-libretech-cc-v2.dtb \
- meson-gxl-s905x-khadas-vim.dtb \
- meson-gxl-s905d-libretech-pc.dtb \
+ meson-gxl-s905x-p212.dtb \
meson-gxm-khadas-vim2.dtb \
meson-gxm-s912-libretech-pc.dtb \
meson-gxm-wetek-core2.dtb \
- meson-axg-s400.dtb \
- meson-g12a-u200.dtb \
+ meson-g12a-radxa-zero.dtb \
meson-g12a-sei510.dtb \
+ meson-g12a-u200.dtb \
+ meson-g12b-a311d-khadas-vim3.dtb \
meson-g12b-gtking.dtb \
meson-g12b-gtking-pro.dtb \
+ meson-g12b-gsking-x.dtb \
meson-g12b-odroid-n2.dtb \
meson-g12b-odroid-n2-plus.dtb \
- meson-g12b-a311d-khadas-vim3.dtb \
+ meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
+ meson-sm1-odroid-hc4.dtb \
meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
sun50i-h5-libretech-all-h5-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-nanopi-r1s-h5.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach-u-boot.dtb
-dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
+dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
keystone-k2g-evm.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
-dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
+dtb-$(CONFIG_SOC_K3_AM6) += \
+ k3-am654-base-board.dtb \
+ k3-am654-r5-base-board.dtb \
+ k3-am65-iot2050-spl.dtb \
+ k3-am6528-iot2050-basic.dtb \
+ k3-am6528-iot2050-basic-pg2.dtb \
+ k3-am6548-iot2050-advanced.dtb \
+ k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
+dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
+
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0490>, <0x045c>, <0x0468>;
+ reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0488>, <0x0420>, <0x042c>;
+ reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0494>, <0x0434>, <0x0440>;
+ reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0498>, <0x0448>, <0x0454>;
+ reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x048c>, <0x0470>, <0x049c>;
+ reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+ reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+ reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2da0>, <0x2da4>, <0x2dac>;
+ reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+ reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2de0>, <0x2de4>, <0x2dec>;
+ reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+ reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
- * with size a power of two. Use one 64 KiB window for
+ * with size a power of two. Use one 1 MiB window for
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
ranges = <0x82000000 0 0xe8000000
0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
- 0x81000000 0 0xefff0000
- 0 0xefff0000 0 0x10000>; /* Port 0 IO*/
+ 0x81000000 0 0xeff00000
+ 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
};
};
};
&cp1_mdio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_smi_pins>;
+
cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
/*
* MPP Bus:
* [0-5] TDM
- * [6,7] CP1_UART 0
- * [8] CP1 10G SFP LOS
- * [9] CP1 10G PHY RESET
- * [10] CP1 10G SFP TX Disable
- * [11] CP1 10G SFP Mode
- * [12] SPI1 CS1n
- * [13] SPI1 MISO (TDM and SPI ROM shared)
- * [14] SPI1 CS0n
- * [15] SPI1 MOSI (TDM and SPI ROM shared)
- * [16] SPI1 CLK (TDM and SPI ROM shared)
- * [24] CP1 2.5G SFP TX Disable
- * [26] CP0 10G SFP TX Fault
- * [27] CP0 10G SFP Mode
- * [28] CP0 10G SFP LOS
- * [29] CP0 10G SFP TX Disable
- * [30] USB Over current indication
- * [31] 10G Port 0 phy reset
+ * [27-28] SMI
+ * [29-30] CP1 MSS I2C
+ * [6-26, 31] GPIO
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
- pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
- 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
- 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
- 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8
+ 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
+
+ cp1_smi_pins: cp1-smi-pins {
+ marvell,pins = < 27 28 >;
+ marvell,function = <8>;
+ };
};
&ap_spi0 {
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
+ status = "disabled";
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
+ status = "disabled";
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
+ status = "disabled";
};
wdt4: watchdog@1e7850C0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
+ status = "disabled";
};
lpc: lpc@1e789000 {
};
ahb {
- usb1: ohci@00400000 {
+ usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 42 0>;
pinctrl-names = "default";
status = "okay";
};
- usb2: ehci@00500000 {
+ usb2: ehci@500000 {
status = "okay";
};
};
};
-&sdmmc0 {
+&pinctrl_mikrobus1_uart {
u-boot,dm-pre-reloc;
};
-&uart0 { /* mikrobus1 uart */
+&pinctrl_qspi1_sck_cs_default {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_qspi1_dat_default {
u-boot,dm-pre-reloc;
};
u-boot,dm-pre-reloc;
};
-&pinctrl_mikrobus1_uart {
+&qspi1 {
u-boot,dm-pre-reloc;
+
+ flash@0 {
+ u-boot,dm-pre-reloc;
+ };
};
+
+&sdmmc0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 { /* mikrobus1 uart */
+ u-boot,dm-pre-reloc;
+};
+
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board
- * SAMA5D2 Industrial Connectivity Board
+ * SAMA5D2 Industrial Connectivity Platform
*
* Copyright (c) 2018, Microchip Technology Inc.
* 2018, Eugen Hristev <eugen.hristev@microchip.com>
};
apb {
- uart0: serial@f801c000 { /* mikrobus1 uart */
+
+ qspi1: spi@f0024000 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mikrobus1_uart>;
+ pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>;
status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <83000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
};
macb0: ethernet@f8008000 {
status = "okay";
};
+ uart0: serial@f801c000 { /* mikrobus1 uart */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_uart>;
+ status = "okay";
+ };
+
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pagesize = <16>;
};
};
+
pioA: gpio@fc038000 {
status = "okay";
pinctrl {
bias-pull-up;
};
+ pinctrl_mikrobus1_uart: mikrobus1_uart {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
+ pinmux = <PIN_PA6__QSPI1_SCK>,
+ <PIN_PA11__QSPI1_CS>;
+ bias-disable;
+ };
+
+ pinctrl_qspi1_dat_default: qspi1_dat_default {
+ pinmux = <PIN_PA7__QSPI1_IO0>,
+ <PIN_PA8__QSPI1_IO1>,
+ <PIN_PA9__QSPI1_IO2>,
+ <PIN_PA10__QSPI1_IO3>;
+ bias-pull-up;
+ };
+
pinctrl_sdmmc0_default: sdmmc0_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
-
- pinctrl_mikrobus1_uart: mikrobus1_uart {
- pinmux = <PIN_PB26__URXD0>,
- <PIN_PB27__UTXD0>;
- bias-disable;
- };
};
};
};
status = "okay";
};
- usb1: ohci@00400000 {
+ usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PB12 GPIO_ACTIVE_HIGH
status = "okay";
};
- usb2: ehci@00500000 {
+ usb2: ehci@500000 {
status = "okay";
};
stdout-path = &uart1;
};
+ memory {
+ reg = <0x20000000 0x20000000>;
+ };
+
onewire_tm: onewire {
gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
};
ahb {
- usb1: ohci@00400000 {
+ usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 42 0>;
pinctrl-names = "default";
status = "okay";
};
- usb2: ehci@00500000 {
+ usb2: ehci@500000 {
status = "okay";
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
&enetc0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
&mscc_felix_port0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot1 {
&mscc_felix_port0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*
*/
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot2 {
&mscc_felix_port1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot3 {
&mscc_felix_port2 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac1 {
status = "okay";
phy-handle = <&mdio1_phy1>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-handle = <&mdio1_phy2>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-handle = <&mdio1_phy3>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-handle = <&mdio1_phy4>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-handle = <&mdio2_phy1>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-handle = <&mdio2_phy2>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-handle = <&mdio2_phy3>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-handle = <&mdio2_phy4>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&emdio1 {
/*
* Device tree fragment for RCW SCH-24801 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* Device tree fragment for RCW SCH-28021 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* Device tree fragment for RCW SCH-30841 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
- * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
+ * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/
/*
* Device tree fragment for RCW SCH-30842 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
- * SGMII-2500, USXGMII, XFI.
+ * 2500base-x, USXGMII, 10GBase-R.
* PHY address is 0x02.
*/
phy@02 {
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
};
};
+ main_conf: syscon@43000000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x0 0x43000000 0x0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x43000000 0x20000>;
+
+ serdes_ln_ctrl: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
};
};
- dmss: dmss {
+ dmss: bus@48000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
- ranges;
+ ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
ti,sci-dev-id = <25>;
};
};
- dmsc: dmsc@44043000 {
+ dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
#power-domain-cells = <2>;
};
- k3_clks: clocks {
+ k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
clocks = <&k3_clks 145 0>;
};
+ main_gpio_intr: interrupt-controller@a00000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <3>;
+ ti,interrupt-ranges = <0 32 16>;
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00600000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <190>, <191>, <192>,
+ <193>, <194>, <195>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <87>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 77 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio1: gpio@601000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00601000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <180>, <181>, <182>,
+ <183>, <184>, <185>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <88>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 78 0>;
+ clock-names = "gpio";
+ };
+
sdhci0: mmc@fa10000 {
compatible = "ti,am64-sdhci-8bit";
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 de ad be ef];
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&main_conf 0x200>;
};
cpsw_port2: port@2 {
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
- mac-address = [00 01 de ad be ef];
+ mac-address = [00 00 00 00 00 00];
};
};
};
};
- main_gpio0: gpio@600000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00600000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
- <77 1 IRQ_TYPE_EDGE_RISING>,
- <77 2 IRQ_TYPE_EDGE_RISING>,
- <77 3 IRQ_TYPE_EDGE_RISING>,
- <77 4 IRQ_TYPE_EDGE_RISING>,
- <77 5 IRQ_TYPE_EDGE_RISING>,
- <77 6 IRQ_TYPE_EDGE_RISING>,
- <77 7 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
+ cpts@39000000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x39000000 0x0 0x400>;
+ reg-names = "cpts";
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 84 0>;
+ clock-names = "cpts";
+ assigned-clocks = <&k3_clks 84 0>;
+ assigned-clock-parents = <&k3_clks 84 8>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
};
usbss0: cdns-usb@f900000{
- compatible = "ti,am64-usb", "ti,j721e-usb";
+ compatible = "ti,am64-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
};
};
- main_gpio1: gpio@601000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00601000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
- <78 1 IRQ_TYPE_EDGE_RISING>,
- <78 2 IRQ_TYPE_EDGE_RISING>,
- <78 3 IRQ_TYPE_EDGE_RISING>,
- <78 4 IRQ_TYPE_EDGE_RISING>,
- <78 5 IRQ_TYPE_EDGE_RISING>,
- <78 6 IRQ_TYPE_EDGE_RISING>,
- <78 7 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
+ tscadc0: tscadc@28001000 {
+ compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 0 0>;
+ assigned-clocks = <&k3_clks 0 0>;
+ assigned-clock-parents = <&k3_clks 0 3>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "adc_tsc_fck";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am654-adc", "ti,am3359-adc";
+ };
};
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x0 0x20000000 0x0 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 102 2>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clocks = <&k3_clks 75 6>;
+ assigned-clocks = <&k3_clks 75 6>;
+ assigned-clock-parents = <&k3_clks 75 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ };
};
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x0 0x20010000 0x0 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster2: mailbox@29020000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29020000 0x00 0x200>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster3: mailbox@29030000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29030000 0x00 0x200>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster4: mailbox@29040000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29040000 0x00 0x200>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster5: mailbox@29050000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29050000 0x00 0x200>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster6: mailbox@29060000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29060000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster7: mailbox@29070000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29070000 0x00 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ main_r5fss0: r5fss@78000000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
#address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 103 2>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ #size-cells = <1>;
+ ranges = <0x78000000 0x00 0x78000000 0x10000>,
+ <0x78100000 0x00 0x78100000 0x10000>,
+ <0x78200000 0x00 0x78200000 0x08000>,
+ <0x78300000 0x00 0x78300000 0x08000>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@78000000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78000000 0x00010000>,
+ <0x78100000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <121>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 121 1>;
+ firmware-name = "am64-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@78200000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78200000 0x00008000>,
+ <0x78300000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <122>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 122 1>;
+ firmware-name = "am64-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
};
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x0 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ main_r5fss1: r5fss@78400000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
#address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 104 2>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ #size-cells = <1>;
+ ranges = <0x78400000 0x00 0x78400000 0x10000>,
+ <0x78500000 0x00 0x78500000 0x10000>,
+ <0x78600000 0x00 0x78600000 0x08000>,
+ <0x78700000 0x00 0x78700000 0x08000>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@78400000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78400000 0x00010000>,
+ <0x78500000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <123>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 123 1>;
+ firmware-name = "am64-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@78600000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78600000 0x00008000>,
+ <0x78700000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <124>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 124 1>;
+ firmware-name = "am64-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
};
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x0 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ serdes_wiz0: wiz@f000000 {
+ compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+
+ assigned-clocks = <&k3_clks 162 1>;
+ assigned-clock-parents = <&k3_clks 162 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 162 1>,
+ <&k3_clks 162 1>,
+ <&k3_clks 162 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
+ };
+
+ pcie0_ep: pcie-ep@f102000 {
+ compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
clock-names = "fck";
- clocks = <&k3_clks 105 2>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ max-functions = /bits/ 8 <1>;
};
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
};
+
+ mcu_gpio_intr: interrupt-controller@4210000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x04210000 0x00 0x200>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <5>;
+ ti,interrupt-ranges = <0 104 4>;
+ };
+
+ mcu_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x4201000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&mcu_gpio_intr>;
+ interrupts = <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <23>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 79 0>;
+ clock-names = "gpio";
+ };
};
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
- i2c0 = &main_i2c0;
- i2c1 = &main_i2c1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
/dts-v1/;
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
evm_12v0: fixedregulator-evm12v0 {
>;
};
+ main_spi0_pins_default: main-spi0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
+ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
+ AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
+ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
+ >;
+ };
+
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
+
+ ospi0_pins_default: ospi0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
+ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
+ AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
+ AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
+ AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
+ AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
+ AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
+ AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
+ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
+ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
+ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
+ >;
+ };
};
&main_uart0 {
};
};
+/* mcu_gpio0 is reserved for mcu firmware usage */
+&mcu_gpio0 {
+ status = "reserved";
+};
+
&mcu_i2c0 {
status = "disabled";
};
status = "disabled";
};
-&cpsw3g {
+&main_spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
- &rgmii2_pins_default>;
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy3>;
-};
-
-&cpsw3g_mdio {
- cpsw3g_phy0: ethernet-phy@0 {
+ pinctrl-0 = <&main_spi0_pins_default>;
+ ti,pindir-d0-out-d1-in;
+ eeprom@0 {
+ compatible = "microchip,93lc46b";
reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ spi-max-frequency = <1000000>;
+ spi-cs-high;
+ data-size = <16>;
};
};
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&tscadc0 {
+ /* ADC is reserved for R5 usage */
+ status = "reserved";
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&mailbox0_cluster2 {
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ mbox_m4_0: mbox-m4-0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
/dts-v1/;
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ vusb_main: fixed-regulator-vusb-main5v0 {
+ /* USB MAIN INPUT 5V DC */
+ compatible = "regulator-fixed";
+ regulator-name = "vusb_main5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
+ /* output of LP8733xx */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vusb_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixed-regulator-sd {
+ /* TPS2051BD */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vcc_3v3_sys>;
+ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
};
>;
};
+ main_usb0_pins_default: main-usb0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
+
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
+
+ ospi0_pins_default: ospi0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
+ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
+ AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
+ AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
+ AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
+ AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
+ AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
+ AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
+ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
+ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
+ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
+ >;
+ };
+};
+
+&mcu_uart0 {
+ status = "disabled";
+};
+
+&mcu_uart1 {
+ status = "disabled";
};
&main_uart1 {
status = "disabled";
};
+&mcu_i2c0 {
+ status = "disabled";
+};
+
+&mcu_i2c1 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
+ "PRU_DETECT", "MMC1_SD_EN",
+ "VPP_LDO_EN", "RPI_PS_3V3_En",
+ "RPI_PS_5V0_En", "RPI_HAT_DETECT";
+ };
+};
+
+&main_i2c3 {
+ status = "disabled";
+};
+
+&mcu_spi0 {
+ status = "disabled";
+};
+
+&mcu_spi1 {
+ status = "disabled";
+};
+
+/* mcu_gpio0 is reserved for mcu firmware usage */
+&mcu_gpio0 {
+ status = "reserved";
+};
+
&sdhci1 {
/* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
};
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes0 {
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
phy-handle = <&cpsw3g_phy0>;
};
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&tscadc0 {
+ status = "disabled";
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&mailbox0_cluster2 {
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ mbox_m4_0: mbox-m4-0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * Authors:
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ * Chao Zeng <chao.zeng@siemens.com>
+ */
+
+#include <config.h>
+
+/ {
+ binman {
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ size = <0x8c0000>;
+
+ blob-ext@0x000000 {
+ offset = <0x000000>;
+ filename = "tiboot3.bin";
+ };
+
+ blob@0x080000 {
+ offset = <0x080000>;
+ filename = "tispl.bin";
+ };
+
+ fit@0x280000 {
+ description = "U-Boot for IOT2050";
+ offset = <0x280000>;
+ images {
+ u-boot {
+ description = "U-Boot";
+ type = "standalone";
+ arch = "arm64";
+ os = "u-boot";
+ compression = "none";
+ load = <0x80800000>;
+ entry = <0x80800000>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-iot2050-basic {
+ description = "k3-am6528-iot2050-basic.dtb";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ blob {
+ filename = "arch/arm/dts/k3-am6528-iot2050-basic.dtb";
+ };
+ };
+
+ fdt-iot2050-basic-pg2 {
+ description = "k3-am6528-iot2050-basic-pg2.dtb";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ blob {
+ filename = "arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb";
+ };
+ };
+
+ fdt-iot2050-advanced {
+ description = "k3-am6548-iot2050-advanced.dtb";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ blob {
+ filename = "arch/arm/dts/k3-am6548-iot2050-advanced.dtb";
+ };
+ };
+
+ fdt-iot2050-advanced-pg2 {
+ description = "k3-am6548-iot2050-advanced-pg2.dtb";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ blob {
+ filename = "arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb";
+ };
+ };
+
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+ k3-rti-wdt-firmware {
+ type = "firmware";
+ load = <0x82000000>;
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = CONFIG_WDT_K3_RTI_FW_FILE;
+ missing-msg = "k3-rti-wdt-firmware";
+ };
+ };
+#endif
+ };
+
+ configurations {
+ default = "conf-iot2050-basic";
+
+ conf-iot2050-basic {
+ description = "iot2050-basic";
+ firmware = "u-boot";
+ fdt = "fdt-iot2050-basic";
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+ loadables = "k3-rti-wdt-firmware";
+#endif
+ };
+
+ conf-iot2050-basic-pg2 {
+ description = "iot2050-basic-pg2";
+ firmware = "u-boot";
+ fdt = "fdt-iot2050-basic-pg2";
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+ loadables = "k3-rti-wdt-firmware";
+#endif
+ };
+
+ conf-iot2050-advanced {
+ description = "iot2050-advanced";
+ firmware = "u-boot";
+ fdt = "fdt-iot2050-advanced";
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+ loadables = "k3-rti-wdt-firmware";
+#endif
+ };
+
+ conf-iot2050-advanced-pg2 {
+ description = "iot2050-advanced-pg2";
+ firmware = "u-boot";
+ fdt = "fdt-iot2050-advanced-pg2";
+#ifdef CONFIG_WDT_K3_RTI_FW_FILE
+ loadables = "k3-rti-wdt-firmware";
+#endif
+ };
+ };
+ };
+
+ /* primary env */
+ fill@0x680000 {
+ offset = <0x680000>;
+ size = <0x020000>;
+ fill-byte = [00];
+ };
+ /* secondary env */
+ fill@0x6a0000 {
+ offset = <0x6a0000>;
+ size = <0x020000>;
+ fill-byte = [00];
+ };
+
+ /* PG1 sysfw, basic variant */
+ blob-ext@0x6c0000 {
+ offset = <0x6c0000>;
+ filename = "sysfw.itb";
+ };
+ /* PG1 sysfw, advanced variant */
+ blob-ext@0x740000 {
+ offset = <0x740000>;
+ filename = "sysfw.itb_HS";
+ };
+ /* PG2 sysfw, basic variant */
+ blob-ext@0x7c0000 {
+ offset = <0x7c0000>;
+ filename = "sysfw_sr2.itb";
+ };
+ /* PG2 sysfw, advanced variant */
+ blob-ext@0x840000 {
+ offset = <0x840000>;
+ filename = "sysfw_sr2.itb_HS";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2021
+ *
+ * Authors:
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic and Advanced variants, PG1
+ */
+
+&dss {
+ assigned-clocks = <&k3_clks 67 2>;
+ assigned-clock-parents = <&k3_clks 67 5>;
+};
+
+&serdes0 {
+ status = "disabled";
+};
+
+&sdhci1 {
+ no-1-8-v;
+};
+
+&tx_pru0_0 {
+ status = "disabled";
+};
+
+&tx_pru0_1 {
+ status = "disabled";
+};
+
+&tx_pru1_0 {
+ status = "disabled";
+};
+
+&tx_pru1_1 {
+ status = "disabled";
+};
+
+&tx_pru2_0 {
+ status = "disabled";
+};
+
+&tx_pru2_1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Chao Zeng <chao.zeng@siemens.com>
+ *
+ * U-Boot bits of the IOT2050 Advanced PG2 variants
+ * (downgrade of usb0 to USB 2.0 mode)
+ */
+
+&serdes0 {
+ status = "disabled";
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
+ /delete-property/ phys;
+ /delete-property/ phy-names;
+};
+
+&usb0 {
+ maximum-speed = "high-speed";
+ /delete-property/ snps,dis-u1-entry-quirk;
+ /delete-property/ snps,dis-u2-entry-quirk;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2021
+ *
+ * Authors:
+ * Chao Zeng <chao.zeng@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic and Advanced variants, PG2
+ */
+
+&main_pmx0 {
+ cp2102n_reset_pin_default: cp2102n-reset-pin-default {
+ pinctrl-single,pins = <
+ /* (AF12) GPIO1_24, used as cp2102 reset */
+ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
+ >;
+ };
+};
+
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2102n_reset_pin_default>;
+ gpio-line-names =
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "CP2102N-RESET";
+};
+
+&dss {
+ /* Workaround needed to get DP clock of 154Mhz */
+ assigned-clocks = <&k3_clks 67 0>;
+};
+
+&serdes0 {
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+ phys = <&serdes0 PHY_TYPE_USB3 0>;
+ phy-names = "usb3-phy";
+};
+
+&usb0 {
+ maximum-speed = "super-speed";
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+};
+
+#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common U-Boot bits of the IOT2050 Basic and Advanced variants
+ */
+
+/ {
+ aliases {
+ spi0 = &ospi0;
+ };
+
+ leds {
+ u-boot,dm-spl;
+ status-led-red {
+ u-boot,dm-spl;
+ };
+ status-led-green {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&cbass_mcu {
+ u-boot,dm-spl;
+};
+
+&cbass_wakeup {
+ u-boot,dm-spl;
+};
+
+&cbass_main {
+ u-boot,dm-spl;
+ main_navss: bus@30800000 {
+ u-boot,dm-spl;
+ };
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+ mcu-fss0-ospi0-pins-default {
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main-uart1-pins-default {
+ u-boot,dm-spl;
+ };
+};
+
+&main_uart1 {
+ u-boot,dm-spl;
+ current-speed = <115200>;
+};
+
+&wkup_gpio0 {
+ u-boot,dm-spl;
+};
+
+&ospi0 {
+ u-boot,dm-spl;
+ flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&fss {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
+ */
+
+#include "k3-am654.dtsi"
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ aliases {
+ spi0 = &mcu_spi0;
+ mmc0 = &sdhci1;
+ mmc1 = &sdhci0;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ bootargs = "earlycon=ns16550a,mmio32,0x02810000";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: secure-ddr@9e800000 {
+ reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa0000000 0 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa0100000 0 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa1000000 0 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa1100000 0 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a2000000 {
+ reg = <0x00 0xa2000000 0x00 0x00200000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>;
+
+ status-led-red {
+ gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
+ panic-indicator;
+ };
+
+ status-led-green {
+ gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
+ };
+
+ user-led1-red {
+ gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ user-led1-green {
+ gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ user-led2-red {
+ gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ user-led2-green {
+ gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ dp_refclk: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+};
+
+&wkup_pmx0 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ /* (AC7) WKUP_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
+ /* (AD6) WKUP_I2C0_SDA */
+ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
+ >;
+ };
+
+ mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+ pinctrl-single,pins = <
+ /* (AD8) MCU_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
+ /* (AD7) MCU_I2C0_SDA */
+ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0)
+ >;
+ };
+
+ arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
+ pinctrl-single,pins = <
+ /* (R2) WKUP_GPIO0_21 */
+ AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
+ >;
+ };
+
+ push_button_pins_default: push-button-pins-default {
+ pinctrl-single,pins = <
+ /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
+ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
+ >;
+ };
+
+ arduino_uart_pins_default: arduino-uart-pins-default {
+ pinctrl-single,pins = <
+ /* (P4) MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
+ /* (P5) MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
+ >;
+ };
+
+ arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
+ pinctrl-single,pins = <
+ /* (P1) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
+ >;
+ };
+
+ arduino_io_oe_pins_default: arduino-io-oe-pins-default {
+ pinctrl-single,pins = <
+ /* (N4) WKUP_GPIO0_34 */
+ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
+ /* (M2) WKUP_GPIO0_36 */
+ AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
+ /* (M3) WKUP_GPIO0_37 */
+ AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
+ /* (M4) WKUP_GPIO0_38 */
+ AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
+ /* (M1) WKUP_GPIO0_41 */
+ AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
+ >;
+ };
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ /* (V1) MCU_OSPI0_CLK */
+ AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
+ /* (U2) MCU_OSPI0_DQS */
+ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)
+ /* (U4) MCU_OSPI0_D0 */
+ AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)
+ /* (U5) MCU_OSPI0_D1 */
+ AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)
+ /* (R4) MCU_OSPI0_CSn0 */
+ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
+ >;
+ };
+
+ db9_com_mode_pins_default: db9-com-mode-pins-default {
+ pinctrl-single,pins = <
+ /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
+ AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
+ /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
+ AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
+ /* (AC1) WKUP_GPIO0_7, used as uart0 term */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
+ /* (AC2) WKUP_GPIO0_6, used as uart0 en */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
+ >;
+ };
+
+ leds_pins_default: leds-pins-default {
+ pinctrl-single,pins = <
+ /* (T2) WKUP_GPIO0_17, used as user led1 red */
+ AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
+ /* (R3) WKUP_GPIO0_22, used as user led1 green */
+ AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
+ /* (R5) WKUP_GPIO0_24, used as status led red */
+ AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
+ /* (N2) WKUP_GPIO0_32, used as status led green */
+ AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
+ >;
+ };
+
+ mcu_spi0_pins_default: mcu-spi0-pins-default {
+ pinctrl-single,pins = <
+ /* (Y1) MCU_SPI0_CLK */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
+ /* (Y3) MCU_SPI0_D0 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
+ /* (Y2) MCU_SPI0_D1 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
+ /* (Y4) MCU_SPI0_CS0 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
+ >;
+ };
+
+ minipcie_pins_default: minipcie-pins-default {
+ pinctrl-single,pins = <
+ /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
+ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
+ >;
+ };
+};
+
+&main_pmx0 {
+ main_uart1_pins_default: main-uart1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
+ AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
+ AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */
+ AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
+ AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
+ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
+ AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
+ AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
+ AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
+ AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
+ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
+ AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
+ >;
+ };
+
+ usb0_pins_default: usb0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+ >;
+ };
+
+ usb1_pins_default: usb1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
+ >;
+ };
+
+ arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
+ >;
+ };
+
+ dss_vout1_pins_default: dss-vout1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
+ AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
+ AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
+ AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
+ AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
+ AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
+ AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
+ AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
+ AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
+ AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
+ AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
+ AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
+ AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
+ AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
+ AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
+ AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
+ AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
+ AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
+ AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
+ AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
+ AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
+ AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
+ AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
+ AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
+ AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
+ AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
+ AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
+ AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
+ >;
+ };
+
+ dp_pins_default: dp-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
+ >;
+ };
+
+ main_i2c2_pins_default: main-i2c2-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
+ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
+ >;
+ };
+};
+
+&main_pmx1 {
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
+ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
+ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
+ >;
+ };
+
+ ecap0_pins_default: ecap0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "reserved";
+};
+
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&mcu_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&arduino_uart_pins_default>;
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
+ gpio-line-names =
+ "main_gpio0-base", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "IO4", "", "IO5", "", "", "IO6", "",
+ "", "", "", "IO7", "", "", "", "", "IO8", "",
+ "", "IO9";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &arduino_io_d2_to_d3_pins_default
+ &arduino_i2c_aio_switch_pins_default
+ &arduino_io_oe_pins_default
+ &push_button_pins_default
+ &db9_com_mode_pins_default
+ >;
+ gpio-line-names =
+ /* 0..9 */
+ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
+ "UART0-enable", "UART0-terminate", "", "WIFI-disable",
+ /* 10..19 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 20..29 */
+ "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
+ /* 30..39 */
+ "IO1", "IO2", "", "IO3", "IO17-direction", "A5",
+ "IO16-direction", "IO15-direction", "IO14-direction", "A3",
+ /* 40..49 */
+ "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
+ "IO11",
+ /* 50..51 */
+ "IO12", "IO10";
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&mcu_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ psu: regulator@60 {
+ compatible = "ti,tps62363";
+ reg = <0x60>;
+ regulator-name = "tps62363-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ ti,enable-vout-discharge;
+ };
+
+ /* D4200 */
+ pcal9535_1: gpio@20 {
+ compatible = "nxp,pcal9535";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
+ "A5-pull", "", "",
+ "IO14-enable", "IO15-enable", "IO16-enable",
+ "IO17-enable", "IO18-enable", "IO19-enable";
+ };
+
+ /* D4201 */
+ pcal9535_2: gpio@21 {
+ compatible = "nxp,pcal9535";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "IO0-direction", "IO1-direction", "IO2-direction",
+ "IO3-direction", "IO4-direction", "IO5-direction",
+ "IO6-direction", "IO7-direction",
+ "IO8-direction", "IO9-direction", "IO10-direction",
+ "IO11-direction", "IO12-direction", "IO13-direction",
+ "IO19-direction";
+ };
+
+ /* D4202 */
+ pcal9535_3: gpio@25 {
+ compatible = "nxp,pcal9535";
+ reg = <0x25>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
+ "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
+ "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
+ "IO12-pull", "IO13-pull";
+ };
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ rtc: rtc8564@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+
+ eeprom: eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp-bridge@f {
+ compatible = "toshiba,tc358767";
+ reg = <0x0f>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_pins_default>;
+ reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
+
+ clock-names = "ref";
+ clocks = <&dp_refclk>;
+
+ toshiba,hpd-pin = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ bridge_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ };
+ };
+};
+
+&mcu_cpsw {
+ status = "disabled";
+};
+
+&ecap0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins_default>;
+};
+
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_default>;
+ dr_mode = "host";
+};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_default>;
+ dr_mode = "host";
+};
+
+&mcu_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_spi0_pins_default>;
+
+ #address-cells = <1>;
+ #size-cells= <0>;
+ ti,pindir-d0-out-d1-in;
+};
+
+&tscadc0 {
+ status = "disabled";
+};
+
+&tscadc1 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5>;
+ };
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ spi-max-frequency = <50000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout1_pins_default>;
+
+ assigned-clocks = <&k3_clks 67 2>;
+ assigned-clock-parents = <&k3_clks 67 5>;
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+
+ dpi_out: endpoint {
+ remote-endpoint = <&bridge_in>;
+ };
+ };
+};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+};
+
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_pins_default>;
+
+ num-lanes = <1>;
+ phys = <&serdes1 PHY_TYPE_PCIE 0>;
+ phy-names = "pcie-phy0";
+ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+};
+
+&mcu_r5fss0_core1 {
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&icssg2_mdio {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+/dts-v1/;
+
+#include "k3-am65-iot2050-common.dtsi"
+#include "k3-am65-iot2050-common-u-boot.dtsi"
+
+/ {
+ compatible = "siemens,iot2050", "ti,am654";
+ model = "Siemens IOT2050";
+};
main_uart0: serial@2800000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart1: serial@2810000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
main_uart2: serial@2820000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
#size-cells = <0>;
};
- sdhci0: sdhci@4f80000 {
+ sdhci0: mmc@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
ti,otap-del-sel-sdr12 = <0x0>;
ti,otap-del-sel-sdr25 = <0x0>;
ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-sdr104 = <0x7>;
ti,otap-del-sel-ddr50 = <0x5>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x5>;
ti,otap-del-sel-hs400 = <0x0>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-mmc-hs = <0x1>;
- ti,itap-del-sel-sdr12 = <0xa>;
- ti,itap-del-sel-sdr25 = <0x1>;
- ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
};
- sdhci1: sdhci@4fa0000 {
+ sdhci1: mmc@4fa0000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,otap-del-sel-ddr50 = <0x4>;
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-mmc-hs = <0x1>;
- ti,itap-del-sel-sdr12 = <0xa>;
- ti,itap-del-sel-sdr25 = <0x1>;
ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
#phy-cells = <0>;
};
- intr_main_gpio: interrupt-controller0 {
+ intr_main_gpio: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
+ reg = <0x0 0x00a00000 0x0 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
ti,interrupt-ranges = <0 392 32>;
};
- main-navss {
+ main_navss: bus@30800000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <118>;
- intr_main_navss: interrupt-controller1 {
+ intr_main_navss: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
+ reg = <0x0 0x310e0000 0x0 0x2000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
+ device_type = "pci";
};
pcie0_ep: pcie-ep@5500000 {
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ device_type = "pci";
};
pcie1_ep: pcie-ep@5600000 {
};
};
- icssg0_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg0_iepclk_mux>;
- };
-
- icssg0_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg0_iepclk_mux>;
- };
-
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
- status = "disabled";
};
};
};
};
- icssg1_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg1_iepclk_mux>;
- };
-
- icssg1_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg1_iepclk_mux>;
- };
-
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
- status = "disabled";
};
};
};
};
- icssg2_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg2_iepclk_mux>;
- };
-
- icssg2_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg2_iepclk_mux>;
- };
-
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
- status = "disabled";
};
};
-
};
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
};
};
- mcu-navss {
+ mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
ti,loczrama = <1>;
};
};
+
+ mcu_rti1: watchdog@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x0 0x40610000 0x0 0x100>;
+ clocks = <&k3_clks 135 0>;
+ power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
+ assigned-clocks = <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 135 4>;
+ };
};
*/
&cbass_wakeup {
- dmsc: dmsc {
+ dmsc: system-controller@44083000 {
compatible = "ti,am654-sci";
ti,host-id = <12>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x44083000 0x1000>;
+
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
- k3_clks: clocks {
+ k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x42300000 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
- intr_wkup_gpio: interrupt-controller2 {
+ intr_wkup_gpio: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
+ reg = <0x42200000 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a53-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic variant, PG1 and PG2
+ */
+
+#include "k3-am65-iot2050-common.dtsi"
+
+#include "k3-am65-iot2050-common-u-boot.dtsi"
+#include "k3-am65-iot2050-boot-image.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 1G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+ };
+
+ cpus {
+ cpu-map {
+ /delete-node/ cluster1;
+ };
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+ };
+
+ /delete-node/ l2-cache1;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "disabled";
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
+ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
+ AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
+ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
+ AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
+ AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
+ AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
+ AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
+ >;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on Basic boards */
+ ti,cluster-mode = <0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2
+ * 1 GB RAM, no eMMC, main_uart0 on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6528-iot2050-basic-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-basic-pg2", "ti,am654";
+ model = "SIMATIC IOT2050 Basic PG2";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1
+ * 1 GB RAM, no eMMC, main_uart0 on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6528-iot2050-basic-common.dtsi"
+#include "k3-am65-iot2050-common-pg1.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-basic", "ti,am654";
+ model = "SIMATIC IOT2050 Basic";
+};
};
};
- clk_ov5640_fixed: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc3v3_io: fixedregulator-vcc3v3io {
+ /* Output of TPS54334 */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&evm_12v0>;
+ };
+
+ vdd_mmc1_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vcc3v3_io>;
+ gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
};
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
- AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+ AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
>;
};
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
-
- ov5640: camera@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
-
- clocks = <&clk_ov5640_fixed>;
- clock-names = "xclk";
-
- port {
- csi2_cam0: endpoint {
- remote-endpoint = <&csi2_phy0>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
- };
- };
-
};
&main_i2c2 {
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
flash@0{
compatible = "jedec,spi-nor";
* disable sdhci1
*/
&sdhci1 {
+ vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
- sdhci-caps-mask = <0x7 0x0>;
disable-wp;
};
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
- spi-max-frequency = <40000000>;
+ spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
};
};
-&csi2_0 {
- csi2_phy0: endpoint {
- remote-endpoint = <&csi2_cam0>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
-};
-
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
&dss {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&icssg2_mdio {
+ status = "disabled";
+};
&cbass_main{
u-boot,dm-spl;
- main-navss {
+ main_navss: bus@30800000 {
u-boot,dm-spl;
};
};
&cbass_mcu {
u-boot,dm-spl;
- mcu-navss {
+ mcu_navss: bus@28380000 {
u-boot,dm-spl;
ringacc@2b800000 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Advanced variant, PG1 and PG2
+ */
+
+/dts-v1/;
+
+#include "k3-am65-iot2050-common.dtsi"
+
+#include "k3-am65-iot2050-common-u-boot.dtsi"
+#include "k3-am65-iot2050-boot-image.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ };
+};
+
+&main_pmx0 {
+ main_mmc0_pins_default: main-mmc0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
+ AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
+};
+
+/* eMMC */
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_uart0 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2
+ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
+ model = "SIMATIC IOT2050 Advanced PG2";
+};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on this board */
+ ti,cluster-mode = <0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1
+ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg1.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-advanced", "ti,am654";
+ model = "SIMATIC IOT2050 Advanced";
+};
u-boot,dm-spl;
};
- mcu-navss{
+ mcu_navss: bus@28380000 {
u-boot,dm-spl;
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-spl;
};
-&wkup_i2c0_pins_default {
- u-boot,dm-spl;
-};
-
&wkup_i2c0 {
u-boot,dm-spl;
};
u-boot,dm-spl;
};
-&wkup_gpio_pins_default {
- u-boot,dm-spl;
-};
-
&mcu_fss0_hpb0_pins_default {
u-boot,dm-spl;
};
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
- aliases {
- remoteproc0 = &mcu_r5fss0_core0;
- remoteproc1 = &mcu_r5fss0_core1;
- remoteproc2 = &main_r5fss0_core0;
- remoteproc3 = &main_r5fss0_core1;
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
};
vdd_mmc1: fixedregulator-sd {
+ /* Output of TPS22918 */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
+ vin-supply = <&vsys_3v3>;
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
};
- vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+ vdd_sd_dv: gpio-regulator-TLV71033 {
+ /* Output of TLV71033 */
compatible = "regulator-gpio";
- regulator-name = "vdd_sd_dv";
+ regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0
- 3300000 0x1>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
};
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
- >;
- };
-
- wkup_gpio_pins_default: wkup-gpio-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
- >;
- };
-
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
>;
};
- vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
+ main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
- J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
+ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
- main_usbss0_pins_default: main-usbss0-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
+ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
};
};
status = "disabled";
};
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};
&serdes0 {
- serdes0_pcie_link: link@0 {
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
- serdes0_qsgmii_link: link@1 {
+ serdes0_qsgmii_link: phy@1 {
reg = <2>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
resets = <&serdes_wiz0 3>;
};
};
+
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie1_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
/*
* Device Tree Source for J7200 SoC Family Main Domain peripherals
*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
};
};
- main_gpio_intr: interrupt-controller0 {
+ main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
+ dma-coherent;
+ dma-ranges;
- main_navss_intr: interrupt-controller1 {
+ main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
+ reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
clock-names = "fclk";
};
- main_sdhci0: sdhci@4f80000 {
- compatible = "ti,j721e-sdhci-8bit";
- reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x6>;
- ti,otap-del-sel-hs200 = <0x8>;
- ti,otap-del-sel-hs400 = <0x5>;
- ti,itap-del-sel-legacy = <0x10>;
- ti,itap-del-sel-mmc-hs = <0xa>;
- ti,strobe-sel = <0x77>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs200-1_8v;
- mmc-ddr-1_8v;
- dma-coherent;
- };
-
- main_sdhci1: sdhci@4fb0000 {
- compatible = "ti,j721e-sdhci-4bit";
- reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- };
-
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x2000000 0x00 0x100>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
- main_gpio0: gpio@600000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
- <105 1 IRQ_TYPE_EDGE_RISING>,
- <105 2 IRQ_TYPE_EDGE_RISING>,
- <105 3 IRQ_TYPE_EDGE_RISING>,
- <105 4 IRQ_TYPE_EDGE_RISING>,
- <105 5 IRQ_TYPE_EDGE_RISING>,
- <105 6 IRQ_TYPE_EDGE_RISING>,
- <105 7 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 0>;
- clock-names = "gpio";
+ main_sdhci0: mmc@4f80000 {
+ compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
+ reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_ahb", "clk_xin";
+ clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x5>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,strobe-sel = <0x77>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ dma-coherent;
+ };
+
+ main_sdhci1: mmc@4fb0000 {
+ compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
+ reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_ahb", "clk_xin";
+ clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
};
serdes_wiz0: wiz@5060000 {
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = /bits/ 16 <0x104c>;
+ device-id = /bits/ 16 <0xb00f>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ dma-coherent;
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
+ cdns,phyrst-a-enable;
};
};
+ main_gpio0: gpio@600000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00600000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <145>, <146>, <147>, <148>,
+ <149>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio2: gpio@610000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00610000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <154>, <155>, <156>, <157>,
+ <158>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio4: gpio@620000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00620000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <163>, <164>, <165>, <166>,
+ <167>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 109 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio6: gpio@630000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00630000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <172>, <173>, <174>, <175>,
+ <176>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 111 0>;
+ clock-names = "gpio";
+ };
+
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j7200-r5fss";
- ti,cluster-mode = <0>;
+ ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x06 0xFF>;
+ ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 245 1>;
firmware-name = "j7200-main-r5f0_0-fw";
ti,atcm-enable = <1>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <246>;
- ti,sci-proc-ids = <0x07 0xFF>;
+ ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 246 1>;
firmware-name = "j7200-main-r5f0_1-fw";
ti,atcm-enable = <1>;
/*
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
- dmsc: dmsc@44083000 {
+ dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
#power-domain-cells = <2>;
};
- k3_clks: clocks {
+ k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
clock-names = "fclk";
};
- wkup_gpio_intr: interrupt-controller2 {
+ wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
+ reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
ti,interrupt-ranges = <16 960 16>;
};
+ wkup_gpio0: gpio@42110000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x42110000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <85>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 113 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_gpio1: gpio@42100000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x42100000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <85>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "gpio";
+ };
+
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
};
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 103 0>;
+ assigned-clocks = <&k3_clks 103 0>;
+ assigned-clock-parents = <&k3_clks 103 2>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
tscadc0: tscadc@40200000 {
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
alignment = <0x1000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a4000000 {
+ reg = <0x00 0xa4000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
};
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
+ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
+ J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
+ J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
+ J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
+ J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
+ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
+ J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
+ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
+ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
+ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
+ >;
+ };
};
&main_pmx0 {
status = "disabled";
};
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
"GPIO_LIN_EN", "CAN_STB";
};
};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
&cbass_main{
u-boot,dm-spl;
- main-navss {
+ main_navss: bus@30000000 {
u-boot,dm-spl;
};
};
u-boot,dm-spl;
};
- mcu-navss {
+ mcu_navss: bus@28380000 {
u-boot,dm-spl;
ringacc@2b800000 {
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
/ {
chosen {
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
status = "disabled";
};
+&cmn_refclk1 {
+ clock-frequency = <100000000>;
+};
+
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_pll1_refclk {
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_pll1_refclk {
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
&serdes0 {
- serdes0_pcie_link: link@0 {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz1_pll1_refclk>;
+
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz2_pll1_refclk>;
+
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
&dss {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
+/ {
+ cmn_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cmn_refclk1: clock-cmnrefclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- pcie0_ctrl: syscon@4070 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00004070 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x4070 0x4070 0x4>;
- };
-
- pcie1_ctrl: syscon@4074 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00004074 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x4074 0x4074 0x4>;
- };
-
- pcie2_ctrl: syscon@4078 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00004078 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x4078 0x4078 0x4>;
- };
-
- pcie3_ctrl: syscon@407c {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x0000407c 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x407c 0x407c 0x4>;
- };
-
serdes_ln_ctrl: mux@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
};
};
- main_gpio_intr: interrupt-controller0 {
+ main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
ti,interrupt-ranges = <8 392 56>;
};
- main-navss {
+ main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <199>;
- main_navss_intr: interrupt-controller1 {
+ main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
+ reg = <0x0 0x310e0000 0x0 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
pinctrl-single,function-mask = <0xffffffff>;
};
- dummy_cmn_refclk: dummy-cmn-refclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
- dummy_cmn_refclk1: dummy-cmn-refclk1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
reg = <0x5000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
+ <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
ranges = <0x5010000 0x0 0x5010000 0x10000>;
wiz1_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>;
assigned-clock-parents = <&k3_clks 293 13>;
};
wiz1_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&k3_clks 293 0>;
};
wiz1_refclk_dig: refclk-dig {
- clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&k3_clks 293 13>;
reg = <0x5010000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz1 0>;
reset-names = "sierra_reset";
- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
+ <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
ranges = <0x5020000 0x0 0x5020000 0x10000>;
wiz2_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 294 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll0_refclk>;
assigned-clock-parents = <&k3_clks 294 11>;
};
wiz2_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&k3_clks 294 0>;
};
wiz2_refclk_dig: refclk-dig {
- clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&k3_clks 294 11>;
reg = <0x5020000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz2 0>;
reset-names = "sierra_reset";
- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
+ <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
ranges = <0x5030000 0x0 0x5030000 0x10000>;
wiz3_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 295 9>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 9>;
};
wiz3_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll1_refclk>;
assigned-clock-parents = <&k3_clks 295 0>;
};
wiz3_refclk_dig: refclk-dig {
- clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_refclk_dig>;
assigned-clock-parents = <&k3_clks 295 9>;
reg = <0x5030000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz3 0>;
reset-names = "sierra_reset";
- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
+ <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
clock-names = "gpio";
};
- main_sdhci0: sdhci@4f80000 {
+ main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
+ clock-names = "clk_ahb", "clk_xin";
+ clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
bus-width = <8>;
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
+ ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
ti,trm-icp = <0x8>;
+ ti,strobe-sel = <0x77>;
dma-coherent;
};
- main_sdhci1: sdhci@4fb0000 {
+ main_sdhci1: mmc@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
+ clock-names = "clk_ahb", "clk_xin";
+ clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
sdhci-caps-mask = <0x2 0x0>;
};
- main_sdhci2: sdhci@4f98000 {
+ main_sdhci2: mmc@4f98000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
+ clock-names = "clk_ahb", "clk_xin";
+ clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
assigned-clocks = <&k3_clks 93 0>;
assigned-clock-parents = <&k3_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
resets = <&k3_reset 15 1>;
firmware-name = "j7-c71_0-fw";
};
+
+ icssg0: icssg@b000000 {
+ compatible = "ti,j721e-icssg";
+ reg = <0x00 0xb000000 0x00 0x80000>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x0b000000 0x100000>;
+
+ icssg0_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ icssg0_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg0_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
+ <&k3_clks 119 1>; /* icssg0_iclk */
+ assigned-clocks = <&icssg0_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 119 1>;
+ };
+
+ icssg0_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
+ <&icssg0_coreclk_mux>; /* core_clk */
+ assigned-clocks = <&icssg0_iepclk_mux>;
+ assigned-clock-parents = <&icssg0_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg0_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg0_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg0_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru0_0: pru@34000 {
+ compatible = "ti,j721e-pru";
+ reg = <0x34000 0x3000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-pru0_0-fw";
+ };
+
+ rtu0_0: rtu@4000 {
+ compatible = "ti,j721e-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-rtu0_0-fw";
+ };
+
+ tx_pru0_0: txpru@a000 {
+ compatible = "ti,j721e-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-txpru0_0-fw";
+ };
+
+ pru0_1: pru@38000 {
+ compatible = "ti,j721e-pru";
+ reg = <0x38000 0x3000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-pru0_1-fw";
+ };
+
+ rtu0_1: rtu@6000 {
+ compatible = "ti,j721e-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-rtu0_1-fw";
+ };
+
+ tx_pru0_1: txpru@c000 {
+ compatible = "ti,j721e-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-txpru0_1-fw";
+ };
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 119 1>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
+ };
+
+ icssg1: icssg@b100000 {
+ compatible = "ti,j721e-icssg";
+ reg = <0x00 0xb100000 0x00 0x80000>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x0b100000 0x100000>;
+
+ icssg1_mem: memories@b100000 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ icssg1_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
+ <&k3_clks 120 4>; /* icssg1_iclk */
+ assigned-clocks = <&icssg1_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 120 4>;
+ };
+
+ icssg1_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
+ <&icssg1_coreclk_mux>; /* core_clk */
+ assigned-clocks = <&icssg1_iepclk_mux>;
+ assigned-clock-parents = <&icssg1_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg1_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg1_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg1_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru1_0: pru@34000 {
+ compatible = "ti,j721e-pru";
+ reg = <0x34000 0x4000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-pru1_0-fw";
+ };
+
+ rtu1_0: rtu@4000 {
+ compatible = "ti,j721e-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-rtu1_0-fw";
+ };
+
+ tx_pru1_0: txpru@a000 {
+ compatible = "ti,j721e-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-txpru1_0-fw";
+ };
+
+ pru1_1: pru@38000 {
+ compatible = "ti,j721e-pru";
+ reg = <0x38000 0x4000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-pru1_1-fw";
+ };
+
+ rtu1_1: rtu@6000 {
+ compatible = "ti,j721e-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-rtu1_1-fw";
+ };
+
+ tx_pru1_1: txpru@c000 {
+ compatible = "ti,j721e-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "j7-txpru1_1-fw";
+ };
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 120 4>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
+ };
};
*/
&cbass_mcu_wakeup {
- dmsc: dmsc@44083000 {
+ dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
#power-domain-cells = <2>;
};
- k3_clks: clocks {
+ k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
clock-names = "fclk";
};
- wkup_gpio_intr: interrupt-controller2 {
+ wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
+ reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#size-cells = <2>;
ranges;
- hbmc_mux: hbmc-mux {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* HBMC select */
- };
-
- hbmc: hyperbus@47034000 {
- compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
- reg = <0x0 0x47034000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <1>;
- mux-controls = <&hbmc_mux 0>;
- assigned-clocks = <&k3_clks 102 0>;
- assigned-clock-rates = <250000000>;
- };
-
ospi0: spi@47040000 {
- compatible = "ti,am654-ospi";
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
};
ospi1: spi@47050000 {
- compatible = "ti,am654-ospi";
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47050000 0x0 0x100>,
<0x7 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
};
};
- mcu-navss {
+ mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
>;
};
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
- >;
- };
-
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
};
};
-&hbmc {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
- <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
-
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x4000000>;
- };
-};
-
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
- spi-max-frequency = <40000000>;
+ spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
- <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2018 NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
+ * Copyright (c) 2020 JetHome
+ * Author: Aleksandr Kazantsev <ak@tvip.ru>
+ * Author: Alexey Shevelkin <ash@tvip.ru>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-axg.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";
+ model = "JetHome JetHub J100";
+ aliases {
+ serial0 = &uart_AO; /* Console */
+ serial1 = &uart_AO_B; /* External UART (Wireless Module) */
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* 1024MB RAM */
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0x0 0x400000>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
+ regulator-always-on;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&scpi_sensors 0>;
+ trips {
+ cpu_passive: cpu-passive {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+
+ cpu_hot: cpu-hot {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "hot";
+ };
+
+ cpu_critical: cpu-critical {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&cpu_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>;
+ #gpio-cells = <1>;
+ };
+};
+
+&efuse {
+ sn: sn@32 {
+ reg = <0x32 0x20>;
+ };
+
+ eth_mac: eth_mac@0 {
+ reg = <0x0 0x6>;
+ };
+
+ bt_mac: bt_mac@6 {
+ reg = <0x6 0x6>;
+ };
+
+ wifi_mac: wifi_mac@c {
+ reg = <0xc 0x6>;
+ };
+
+ bid: bid@12 {
+ reg = <0x12 0x20>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rmii_x_pins>;
+ pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+ phy-mode = "rmii";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */
+ eth_phy0: ethernet-phy@0 {
+ /* compatible = "ethernet-phy-id0243.0c54";*/
+ max-speed = <100>;
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* Internal I2C bus (on CPU module) */
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_z_pins>;
+ pinctrl-names = "default";
+
+ /* RTC */
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "okay";
+ };
+};
+
+/* Peripheral I2C bus (on motherboard) */
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_a_x20_pins>;
+ pinctrl-names = "default";
+};
+
+/* wifi module */
+&sd_emmc_b {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr104;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* emmc storage */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* UART Bluetooth */
+&uart_B {
+ status = "okay";
+ pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* UART Console */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* UART Wireless module */
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&spicc1 {
+ status = "okay";
+ pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>;
+ pinctrl-names = "default";
+};
+
+&gpio {
+ gpio-line-names =
+ "", "", "", "", "", // 0 - 4
+ "", "", "", "", "", // 5 - 9
+ "UserButton", "", "", "", "", // 10 - 14
+ "", "", "", "", "", // 15 - 19
+ "", "", "", "", "", // 20 - 24
+ "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29
+ "Output1", "", "", "", "", // 30 - 34
+ "", "ZigBeeBOOT", "", "", "", // 35 - 39
+ "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44
+ "Input2", "Input1", "", "", "", // 45 - 49
+ "", "", "", "", "", // 50 - 54
+ "", "", "", "", "", // 55 - 59
+ "", "", "", "", "", // 60 - 64
+ "", "", "", "", "", // 65 - 69
+ "", "", "", "", "", // 70 - 74
+ "", "", "", "", "", // 75 - 79
+ "", "", "", "", "", // 80 - 84
+ "", ""; // 85-86
+};
+
+&cpu0 {
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ #cooling-cells = <2>;
+};
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
-#include "meson-axg-u-boot.dtsi"
-
/* wifi module */
&sd_emmc_b {
status = "disabled";
status = "okay";
};
-&usb {
- status = "okay";
- dr_mode = "otg";
- vbus-supply = <&usb_pwr>;
-};
-
&usb2_phy1 {
phy-supply = <&vcc_5v>;
};
status = "okay";
};
+&pcieA {
+ reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcieB {
+ reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+ vbus-supply = <&usb_pwr>;
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/ {
- soc {
- usb: usb@ffe09080 {
- compatible = "amlogic,meson-gxl-usb-ctrl";
- reg = <0x0 0xffe09080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
- clock-names = "usb_ctrl", "ddr";
- resets = <&reset RESET_USB_OTG>;
-
- dr_mode = "otg";
-
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy1";
-
- dwc2: usb@ff400000 {
- compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
- reg = <0x0 0xff400000 0x0 0x40000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB1>;
- clock-names = "otg";
- phys = <&usb2_phy1>;
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
-
- dwc3: usb@ff500000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff500000 0x0 0x100000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- maximum-speed = "high-speed";
- snps,dis_u2_susphy_quirk;
- };
- };
- };
-};
-
-&apb {
- usb2_phy1: phy@9020 {
- compatible = "amlogic,meson-gxl-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0x9020 0x0 0x20>;
- clocks = <&clkc CLKID_USB>;
- clock-names = "phy";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "phy";
- status = "okay";
- };
-};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+#include <dt-bindings/power/meson-axg-power.h>
/ {
compatible = "amlogic,meson-axg";
#size-cells = <2>;
ranges;
+ pcieA: pcie@f9800000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf9800000 0x0 0x400000>,
+ <0x0 0xff646000 0x0 0x2000>,
+ <0x0 0xf9f00000 0x0 0x100000>;
+ reg-names = "elbi", "cfg", "config";
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
+ clock-names = "general", "pclk", "port";
+ resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
+ reset-names = "port", "apb";
+ num-lanes = <1>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
+ pcieB: pcie@fa000000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xfa000000 0x0 0x400000>,
+ <0x0 0xff648000 0x0 0x2000>,
+ <0x0 0xfa400000 0x0 0x100000>;
+ reg-names = "elbi", "cfg", "config";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
+ clock-names = "general", "pclk", "port";
+ resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
+ reset-names = "port", "apb";
+ num-lanes = <1>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
+ usb: usb@ffe09080 {
+ compatible = "amlogic,meson-axg-usb-ctrl";
+ reg = <0x0 0xffe09080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "usb_ctrl", "ddr";
+ resets = <&reset RESET_USB_OTG>;
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc2: usb@ff400000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1>;
+ clock-names = "otg";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
+ power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
status = "disabled";
};
+ pcie_phy: phy@ff644000 {
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x1c>;
+ resets = <&reset RESET_PCIE_PHY>;
+ phys = <&mipi_pcie_analog_dphy>;
+ phy-names = "analog";
+ #phy-cells = <0>;
+ };
+
pdm: audio-controller@ff632000 {
compatible = "amlogic,axg-pdm";
reg = <0x0 0xff632000 0x0 0x34>;
clocks = <&xtal>;
clock-names = "xtal";
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-axg-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&sysctrl_AO>;
+ resets = <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_VCBUS>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VID_LOCK>;
+ reset-names = "viu", "venc", "vcbus",
+ "vencl", "vid_lock";
+ clocks = <&clkc CLKID_VPU>,
+ <&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ /*
+ * VPU clocking is provided by two identical clock paths
+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ * Same for VAPB but with a final gate after the glitch free mux.
+ */
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_VPU>, /* Glitch free mux */
+ <&clkc CLKID_VAPB_0_SEL>,
+ <&clkc CLKID_VAPB_0>,
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VAPB_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <250000000>,
+ <0>, /* Do Nothing */
+ <0>, /* Do Nothing */
+ <250000000>,
+ <0>; /* Do Nothing */
+ };
+
+ mipi_pcie_analog_dphy: phy {
+ compatible = "amlogic,axg-mipi-pcie-analog-phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
};
#mbox-cells = <1>;
};
+ mipi_dphy: phy@ff640000 {
+ compatible = "amlogic,axg-mipi-dphy";
+ reg = <0x0 0xff640000 0x0 0x100>;
+ clocks = <&clkc CLKID_MIPI_DSI_PHY>;
+ clock-names = "pclk";
+ resets = <&reset RESET_MIPI_PHY>;
+ reset-names = "phy";
+ phys = <&mipi_pcie_analog_dphy>;
+ phy-names = "analog";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
audio: bus@ff642000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
};
};
+ ge2d: ge2d@ff940000 {
+ compatible = "amlogic,axg-ge2d";
+ reg = <0x0 0xff940000 0x0 0x10000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_VAPB>;
+ resets = <&reset RESET_GE2D>;
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
+ fifo-size = <128>;
};
};
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
+
+ usb2_phy1: phy@9020 {
+ compatible = "amlogic,meson-gxl-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x9020 0x0 0x20>;
+ clocks = <&clkc CLKID_USB>;
+ clock-names = "phy";
+ resets = <&reset RESET_USB_OTG>;
+ reset-names = "phy";
+ };
};
sram: sram@fffc0000 {
*/
/ {
+ /* Keep HW order from U-boot */
+ aliases {
+ /delete-property/ mmc0;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ mmc0 = &sd_emmc_b; /* SD card */
+ mmc1 = &sd_emmc_c; /* eMMC */
+ mmc2 = &sd_emmc_a; /* SDIO */
+ };
+
chosen {
#address-cells = <2>;
#size-cells = <2>;
pcie: pcie@fc000000 {
compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
- reg = <0x0 0xfc000000 0x0 0x400000
- 0x0 0xff648000 0x0 0x2000
- 0x0 0xfc400000 0x0 0x200000>;
+ reg = <0x0 0xfc000000 0x0 0x400000>,
+ <0x0 0xff648000 0x0 0x2000>,
+ <0x0 0xfc400000 0x0 0x200000>;
reg-names = "elbi", "cfg", "config";
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
- 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
+ ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
+ <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
clocks = <&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_COMB
};
ethmac: ethernet@ff3f0000 {
- compatible = "amlogic,meson-axg-dwmac",
+ compatible = "amlogic,meson-g12a-dwmac",
"snps,dwmac-3.70a",
"snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000>,
hwrng: rng@218 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x218 0x0 0x4>;
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
};
};
};
};
- vrtc: rtc@0a8 {
+ vrtc: rtc@a8 {
compatible = "amlogic,meson-vrtc";
reg = <0x0 0x000a8 0x0 0x4>;
};
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
};
+ watchdog: watchdog@f0d0 {
+ compatible = "amlogic,meson-gxbb-wdt";
+ reg = <0x0 0xf0d0 0x0 0x10>;
+ clocks = <&xtal>;
+ };
+
spicc0: spi@13000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x44>;
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ fifo-size = <128>;
};
};
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_u2_susphy_quirk;
- snps,quirk-frame-length-adjustment;
+ snps,quirk-frame-length-adjustment = <0x20>;
snps,parkmode-disable-ss-quirk;
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "radxa,zero", "amlogic,g12a";
+ model = "Radxa Zero";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ cvbs-connector {
+ status = "disabled";
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ hdmi_pw: regulator-hdmi_pw {
+ compatible = "regulator-fixed";
+ regulator-name = "HDMI_PW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&ao_5v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "RADXA-ZERO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_pw>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "disabled";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12A-SEI510";
+ model = "SEI510";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b";
+ model = "Beelink GS-King X";
+
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "GSKING-X";
+ audio-aux-devs = <&tdmout_a>;
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 1",
+ "TDM_A Playback", "TDMOUT_A OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_a>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
+&tdmif_a {
+ status = "okay";
+};
+
+&tdmout_a {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
- compatible = "azw,gtking", "amlogic,g12b";
+ compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GT-King Pro";
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
leds {
compatible = "gpio-leds";
- white {
+ led-white {
label = "power:white";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
default-state = "on";
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-GTKING-PRO";
+ model = "GTKING-PRO";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
status = "okay";
};
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
&tdmif_b {
status = "okay";
};
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
- compatible = "azw,gtking", "amlogic,g12b";
+ compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GT-King";
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
spdif_dit: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-GTKING";
+ model = "GTKING";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
status = "okay";
};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
&spdifout {
pinctrl-0 = <&spdif_out_h_pins>;
pinctrl-names = "default";
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1040000>;
- pwms = <&pwm_AO_cd 1 1500 0>;
+ pwms = <&pwm_ab 0 1500 0>;
};
&vddcpu_b {
aliases {
serial0 = &uart_AO;
ethernet0 = ðmac;
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
};
dioo2133: audio-amplifier-0 {
leds {
compatible = "gpio-leds";
- blue {
+ led-blue {
label = "n2:blue";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-ODROID-N2";
+ model = "ODROID-N2";
audio-widgets = "Line", "Lineout";
audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
<&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
&ext_mdio {
external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
+ /* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
};
&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOH */
+ "", "", "", "", "", "", "", "",
+ "",
+ /* BOOT */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOC */
+ "", "", "", "", "", "", "", "",
+ /* GPIOA */
+ "PIN_44", /* GPIOA_0 */
+ "PIN_46", /* GPIOA_1 */
+ "PIN_45", /* GPIOA_2 */
+ "PIN_47", /* GPIOA_3 */
+ "PIN_26", /* GPIOA_4 */
+ "", "", "", "", "", "",
+ "PIN_42", /* GPIOA_11 */
+ "PIN_32", /* GPIOA_12 */
+ "PIN_7", /* GPIOA_13 */
+ "PIN_27", /* GPIOA_14 */
+ "PIN_28", /* GPIOA_15 */
+ /* GPIOX */
+ "PIN_16", /* GPIOX_0 */
+ "PIN_18", /* GPIOX_1 */
+ "PIN_22", /* GPIOX_2 */
+ "PIN_11", /* GPIOX_3 */
+ "PIN_13", /* GPIOX_4 */
+ "PIN_33", /* GPIOX_5 */
+ "PIN_35", /* GPIOX_6 */
+ "PIN_15", /* GPIOX_7 */
+ "PIN_19", /* GPIOX_8 */
+ "PIN_21", /* GPIOX_9 */
+ "PIN_24", /* GPIOX_10 */
+ "PIN_23", /* GPIOX_11 */
+ "PIN_8", /* GPIOX_12 */
+ "PIN_10", /* GPIOX_13 */
+ "PIN_29", /* GPIOX_14 */
+ "PIN_31", /* GPIOX_15 */
+ "PIN_12", /* GPIOX_16 */
+ "PIN_3", /* GPIOX_17 */
+ "PIN_5", /* GPIOX_18 */
+ "PIN_36"; /* GPIOX_19 */
/*
* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
- usb-hub {
+ hog-0 {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
linux,rc-map-name = "rc-odroid";
};
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
status = "okay";
};
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
/* SD card */
&sd_emmc_b {
status = "okay";
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
};
};
};
+
+&mali {
+ dma-coherent;
+};
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S9XX-PC";
+ model = "LIBRETECH-PC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Speaker", "7J4-14 LEFT",
"Speaker", "7J4-11 RIGHT";
sound {
compatible = "amlogic,gx-sound-card";
- model = "GX-P230-Q200";
+ model = "P230-Q200";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLP",
*/
/ {
+ /* Keep HW order from U-boot */
+ aliases {
+ /delete-property/ mmc0;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ mmc0 = &sd_emmc_b; /* SD card */
+ mmc1 = &sd_emmc_c; /* eMMC */
+ mmc2 = &sd_emmc_a; /* SDIO */
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ fifo-size = <128>;
};
uart_B: serial@84dc {
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "NANOPI-K2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "ODROID-C2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
- usb-hub {
+ hog-0 {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S805X-AC";
+ model = "LIBRETECH-AC";
audio-widgets = "Speaker", "9J5-3 LEFT",
"Speaker", "9J5-2 RIGHT";
audio-routing = "9J5-3 LEFT", "ACODEC LOLN",
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
+ * Copyright (c) 2020 JetHome
+ * Author: Aleksandr Kazantsev <ak@tvip.ru>
+ * Author: Alexey Shevelkin <ash@tvip.ru>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl.dtsi"
+
+/ {
+ compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
+ model = "JetHome JetHub J80";
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO; /* Console */
+ serial1 = &uart_A; /* Bluetooth */
+ serial2 = &uart_AO_B; /* Wireless module 1 */
+ serial3 = &uart_C; /* Wireless module 2 */
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+&efuse {
+ bt_mac: bt_mac@6 {
+ reg = <0x6 0x6>;
+ };
+
+ wifi_mac: wifi_mac@C {
+ reg = <0xc 0x6>;
+ };
+};
+
+&sn {
+ reg = <0x32 0x20>;
+};
+
+ð_mac {
+ reg = <0x0 0x6>;
+};
+
+&bid {
+ reg = <0x12 0x20>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* Console UART */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* S905W only has access to its internal PHY */
+ðmac {
+ status = "okay";
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&internal_phy {
+ status = "okay";
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&uart_C {
+ status = "okay";
+ pinctrl-0 = <&uart_c_pins>;
+ pinctrl-names = "default";
+};
+
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&i2c_B {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_b_pins>;
+
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "okay";
+ };
+};
/dts-v1/;
-#include <dt-bindings/input/input.h>
-
#include "meson-gxl-s905x-p212.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
};
};
- pwmleds {
+ led-controller {
compatible = "pwm-leds";
- power {
+ led-1 {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "KHADAS-VIM";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
pinctrl-names = "default";
rtc: rtc@51 {
- /* has to be enabled manually when a battery is connected: */
- status = "disabled";
+ status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
regulator-always-on;
};
-
vcck: regulator-vcck {
compatible = "regulator-fixed";
regulator-name = "VCCK";
regulator-always-on;
};
-
vddio_card: regulator-vddio-card {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S905X-CC-V2";
+ model = "LIBRETECH-CC-V2";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
};
};
-
&aiu {
status = "okay";
};
hdmi-phandle = <&hdmi_tx>;
};
-
ðmac {
status = "okay";
};
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S905X-CC";
+ model = "LIBRETECH-CC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLN",
/dts-v1/;
-#include <dt-bindings/input/input.h>
-
#include "meson-gxm.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
};
};
- pwmleds {
+ led-controller {
compatible = "pwm-leds";
- power {
+ led-1 {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "KHADAS-VIM2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
hdmi-phandle = <&hdmi_tx>;
};
-
&cpu_cooling_maps {
map0 {
cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
pinctrl-names = "default";
rtc: rtc@51 {
- /* has to be enabled manually when a battery is connected: */
- status = "disabled";
+ status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
#size-cells = <1>;
compatible = "winbond,w25q16", "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <3000000>;
+ spi-max-frequency = <104000000>;
};
};
leds {
compatible = "gpio-leds";
- blue {
+ led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
};
};
+ cpu0: cpu@0 {
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu1: cpu@1 {
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu2: cpu@2 {
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu3: cpu@3 {
+ capacity-dmips-mhz = <1024>;
+ };
+
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
*/
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
aliases {
serial0 = &uart_AO;
ethernet0 = ðmac;
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
};
chosen {
compatible = "gpio-leds";
led-white {
- label = "vim3:white:sys";
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-red {
- label = "vim3:red";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-KHADAS-VIM3";
- audio-aux-devs = <&tdmout_a>;
+ model = "KHADAS-VIM3";
+ audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 3", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
sound-dai = <&frddr_c>;
};
- /* 8ch hdmi interface */
dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
};
/* hdmi glue */
- dai-link-4 {
+ dai-link-7 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
};
ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
};
&frddr_a {
#gpio-cells = <2>;
};
- rtc@51 {
+ rtc: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
};
&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
};
&saradc {
};
};
-
&tdmif_a {
status = "okay";
};
+&tdmin_a {
+ status = "okay";
+};
+
&tdmout_a {
status = "okay";
};
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
&tohdmitx {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m5", "amlogic,sm1";
+ model = "Banana Pi BPI-M5";
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ key {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* TOFIX: handle CVBS_DET on SARADC channel 0 */
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M5";
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
+ <&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "Lineout", "ACODEC LOLP",
+ "Lineout", "ACODEC LORP";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-8 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub on the BPI-M5 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
regulator-boot-on;
regulator-always-on;
};
+
+ sound {
+ model = "G12B-KHADAS-VIM3L";
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 13", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
+ };
};
&cpu0 {
status = "okay";
};
-&sd_emmc_a {
- sd-uhs-sdr50;
-};
-
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/
+&sd_emmc_a {
+ sd-uhs-sdr50;
+};
/dts-v1/;
-#include "meson-sm1.dtsi"
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+#include "meson-sm1-odroid.dtsi"
/ {
compatible = "hardkernel,odroid-c4", "amlogic,sm1";
model = "Hardkernel ODROID-C4";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
leds {
compatible = "gpio-leds";
};
};
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
-
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- tf_io: gpio-regulator-tf_io {
- compatible = "regulator-gpio";
-
- regulator-name = "TF_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&main_12v>;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the microUSB port power enable */
- gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
sound {
- compatible = "amlogic,axg-sound-card";
- model = "SM1-ODROID-C4";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ model = "ODROID-C4";
};
};
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
&gpio {
- gpio-line-names =
- /* GPIOZ */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOH */
- "", "", "", "", "",
- "PIN_36", /* GPIOH_5 */
- "PIN_26", /* GPIOH_6 */
- "PIN_32", /* GPIOH_7 */
- "",
- /* BOOT */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOC */
- "", "", "", "", "", "", "", "",
- /* GPIOA */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "",
- "PIN_27", /* GPIOA_14 */
- "PIN_28", /* GPIOA_15 */
- /* GPIOX */
- "PIN_16", /* GPIOX_0 */
- "PIN_18", /* GPIOX_1 */
- "PIN_22", /* GPIOX_2 */
- "PIN_11", /* GPIOX_3 */
- "PIN_13", /* GPIOX_4 */
- "PIN_7", /* GPIOX_5 */
- "PIN_33", /* GPIOX_6 */
- "PIN_15", /* GPIOX_7 */
- "PIN_19", /* GPIOX_8 */
- "PIN_21", /* GPIOX_9 */
- "PIN_24", /* GPIOX_10 */
- "PIN_23", /* GPIOX_11 */
- "PIN_8", /* GPIOX_12 */
- "PIN_10", /* GPIOX_13 */
- "PIN_29", /* GPIOX_14 */
- "PIN_31", /* GPIOX_15 */
- "PIN_12", /* GPIOX_16 */
- "PIN_3", /* GPIOX_17 */
- "PIN_5", /* GPIOX_18 */
- "PIN_35"; /* GPIOX_19 */
-
/*
* WARNING: The USB Hub on the Odroid-C4 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
- usb-hub {
+ hog-0 {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
};
};
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "", "", "", "",
- "PIN_47", /* GPIOAO_4 */
- "", "",
- "PIN_45", /* GPIOAO_7 */
- "PIN_46", /* GPIOAO_8 */
- "PIN_44", /* GPIOAO_9 */
- "PIN_42", /* GPIOAO_10 */
- "",
- /* GPIOE */
- "", "", "";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
linux,rc-map-name = "rc-odroid";
};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <200000000>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&tf_io>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
+
+/* SARADC is needed for proper board variant detection */
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+&tflash_vdd {
+ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-odroid.dtsi"
+
+/ {
+ compatible = "hardkernel,odroid-hc4", "amlogic,sm1";
+ model = "Hardkernel ODROID-HC4";
+
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-min-state = <0>;
+ cooling-max-state = <3>;
+ cooling-levels = <0 120 170 220>;
+ pwms = <&pwm_cd 1 40000 0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
+ p12v_0: regulator-p12v_0 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
+ p12v_1: regulator-p12v_1 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_1";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sound {
+ model = "ODROID-HC4";
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ map {
+ trip = <&cpu_passive>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&ir {
+ linux,rc-map-name = "rc-odroid";
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ status = "okay";
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
+&pcie {
+ status = "okay";
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_cd {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_d_x6_pins>;
+};
+
+&sd_emmc_c {
+ status = "disabled";
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
+&usb {
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+};
+
+&usb2_phy0 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
+ */
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * MP8756GD Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&main_12v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the microUSB port power enable */
+ gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOH */
+ "", "", "", "", "",
+ "PIN_36", /* GPIOH_5 */
+ "PIN_26", /* GPIOH_6 */
+ "PIN_32", /* GPIOH_7 */
+ "",
+ /* BOOT */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOC */
+ "", "", "", "", "", "", "", "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "PIN_27", /* GPIOA_14 */
+ "PIN_28", /* GPIOA_15 */
+ /* GPIOX */
+ "PIN_16", /* GPIOX_0 */
+ "PIN_18", /* GPIOX_1 */
+ "PIN_22", /* GPIOX_2 */
+ "PIN_11", /* GPIOX_3 */
+ "PIN_13", /* GPIOX_4 */
+ "PIN_7", /* GPIOX_5 */
+ "PIN_33", /* GPIOX_6 */
+ "PIN_15", /* GPIOX_7 */
+ "PIN_19", /* GPIOX_8 */
+ "PIN_21", /* GPIOX_9 */
+ "PIN_24", /* GPIOX_10 */
+ "PIN_23", /* GPIOX_11 */
+ "PIN_8", /* GPIOX_12 */
+ "PIN_10", /* GPIOX_13 */
+ "PIN_29", /* GPIOX_14 */
+ "PIN_31", /* GPIOX_15 */
+ "PIN_12", /* GPIOX_16 */
+ "PIN_3", /* GPIOX_17 */
+ "PIN_5", /* GPIOX_18 */
+ "PIN_35"; /* GPIOX_19 */
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "", "", "", "",
+ "PIN_47", /* GPIOAO_4 */
+ "", "",
+ "PIN_45", /* GPIOAO_7 */
+ "PIN_46", /* GPIOAO_8 */
+ "PIN_44", /* GPIOAO_9 */
+ "PIN_42", /* GPIOAO_10 */
+ "",
+ /* GPIOE */
+ "", "", "";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <200000000>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
+
};
};
- leds {
+ led-controller-1 {
compatible = "gpio-leds";
- led-bluetooth {
+ led-1 {
label = "sei610:blue:bt";
gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
default-state = "off";
};
};
- pwmleds {
+ led-controller-2 {
compatible = "pwm-leds";
- power {
+ led-2 {
label = "sei610:red:power";
pwms = <&pwm_AO_ab 0 30518 0>;
max-brightness = <255>;
sound {
compatible = "amlogic,axg-sound-card";
- model = "SM1-SEI610";
+ model = "SEI610";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
opp-microvolt = <790000>;
};
- opp-1512000000 {
+ opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <800000>;
};
status = "disabled";
};
+ toacodec: audio-controller@740 {
+ compatible = "amlogic,sm1-toacodec",
+ "amlogic,g12a-toacodec";
+ reg = <0x0 0x740 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOACODEC";
+ resets = <&clkc_audio AUD_RESET_TOACODEC>;
+ status = "disabled";
+ };
+
tohdmitx: audio-controller@744 {
compatible = "amlogic,sm1-tohdmitx",
"amlogic,g12a-tohdmitx";
};
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ARM9260_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
+ clock-names = "cpu", "master", "xtal";
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
* Author: Sandeep Sheriker M <Sandeepsheriker.mallikarjun@microchip.com>
*/
/dts-v1/;
+#include <dt-bindings/mfd/atmel-flexcom.h>
#include "sam9x60.dtsi"
/ {
};
flx0: flexcom@f801c600 {
- atmel,flexcom-mode = <3>;
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c@600 {
#size-cells = <1>;
u-boot,dm-pre-reloc;
- usb1: ohci@00400000 {
+ usb1: ohci@400000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00400000 0x100000>;
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
status = "disabled";
};
- usb2: ehci@00500000 {
+ usb2: ehci@500000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00500000 0x100000>;
clocks = <&utmi>, <&uhphs_clk>;
status = "disabled";
};
+ pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
rstc@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3)
#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2)
#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1)
-
* 2020, Claudiu Beznea <claudiu.beznea@microchip.com>
*/
/dts-v1/;
+#include <dt-bindings/mfd/atmel-flexcom.h>
#include "sama7g5.dtsi"
#include "sama7g5-pinfunc.h"
};
&flx1 {
- atmel,flexcom-mode = <3>;
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
};
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
gpadc: ab8500-gpadc {
compatible = "stericsson,ab8500-gpadc";
- interrupts = <32 IRQ_TYPE_LEVEL_HIGH
- 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
+ <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "HW_CONV_END", "SW_CONV_END";
vddadc-supply = <&ab8500_ldo_tvout_reg>;
#address-cells = <1>;
ab8500_temp {
compatible = "stericsson,abx500-temp";
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ABX500_TEMP_WARM";
io-channels = <&gpadc 0x06>,
<&gpadc 0x07>;
- io-channel-name = "aux1", "aux2";
+ io-channel-names = "aux1", "aux2";
};
ab8500_battery: ab8500_battery {
ab8500_fg {
compatible = "stericsson,ab8500-fg";
- battery = <&ab8500_battery>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <8 IRQ_TYPE_LEVEL_HIGH>,
+ <28 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "NCONV_ACCU",
+ "BATT_OVV",
+ "LOW_BAT_F",
+ "CC_INT_CALIB",
+ "CCEOC";
+ battery = <&ab8500_battery>;
io-channels = <&gpadc 0x08>;
- io-channel-name = "main_bat_v";
+ io-channel-names = "main_bat_v";
};
ab8500_btemp {
compatible = "stericsson,ab8500-btemp";
- battery = <&ab8500_battery>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>,
+ <80 IRQ_TYPE_LEVEL_HIGH>,
+ <83 IRQ_TYPE_LEVEL_HIGH>,
+ <81 IRQ_TYPE_LEVEL_HIGH>,
+ <82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "BAT_CTRL_INDB",
+ "BTEMP_LOW",
+ "BTEMP_HIGH",
+ "BTEMP_LOW_MEDIUM",
+ "BTEMP_MEDIUM_HIGH";
+ battery = <&ab8500_battery>;
io-channels = <&gpadc 0x02>,
<&gpadc 0x01>;
- io-channel-name = "btemp_ball",
+ io-channel-names = "btemp_ball",
"bat_ctrl";
};
ab8500_charger {
- compatible = "stericsson,ab8500-charger";
+ compatible = "stericsson,ab8500-charger";
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 IRQ_TYPE_LEVEL_HIGH>,
+ <107 IRQ_TYPE_LEVEL_HIGH>,
+ <106 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <105 IRQ_TYPE_LEVEL_HIGH>,
+ <104 IRQ_TYPE_LEVEL_HIGH>,
+ <89 IRQ_TYPE_LEVEL_HIGH>,
+ <22 IRQ_TYPE_LEVEL_HIGH>,
+ <21 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "MAIN_CH_UNPLUG_DET",
+ "MAIN_CHARGE_PLUG_DET",
+ "MAIN_EXT_CH_NOT_OK",
+ "MAIN_CH_TH_PROT_R",
+ "MAIN_CH_TH_PROT_F",
+ "VBUS_DET_F",
+ "VBUS_DET_R",
+ "USB_LINK_STATUS",
+ "USB_CH_TH_PROT_R",
+ "USB_CH_TH_PROT_F",
+ "USB_CHARGER_NOT_OKR",
+ "VBUS_OVV",
+ "CH_WD_EXP",
+ "VBUS_CH_DROP_END";
battery = <&ab8500_battery>;
vddadc-supply = <&ab8500_ldo_tvout_reg>;
io-channels = <&gpadc 0x03>,
<&gpadc 0x0a>,
<&gpadc 0x09>,
<&gpadc 0x0b>;
- io-channel-name = "main_charger_v",
+ io-channel-names = "main_charger_v",
"main_charger_c",
"vbus_v",
"usb_charger_c";
battery = <&ab8500_battery>;
};
- ab8500_usb {
+ ab8500_usb: ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
musb_1v8-supply = <&db8500_vsmps2_reg>;
clocks = <&prcmu_clk PRCMU_SYSCLK>;
clock-names = "sysclk";
+ #phy-cells = <0>;
};
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
compatible = "stericsson,ab8500-sysctrl";
};
- ab8500-pwm {
+ ab8500-pwm-1 {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-pwm-2 {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-pwm-3 {
compatible = "stericsson,ab8500-pwm";
clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
clock-names = "intclk";
// supplies to the display/camera
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2900000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
/* BUG: If turned off MMC will be affected. */
regulator-always-on;
vana-supply = <&ab8500_ldo_ana_reg>;
};
};
+
+ usb_per5@a03e0000 {
+ phys = <&ab8500_usb>;
+ phy-names = "usb";
+ };
};
};
<&gpadc 0x08>, /* Main battery voltage */
<&gpadc 0x09>, /* VBUS */
<&gpadc 0x0b>, /* Charger current */
- <&gpadc 0x0c>; /* Backup battery voltage */
+ <&gpadc 0x0c>, /* Backup battery voltage */
+ <&gpadc 0x0d>; /* Die temperature */
};
soc {
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
gpadc: ab8500-gpadc {
compatible = "stericsson,ab8500-gpadc";
- interrupts = <32 IRQ_TYPE_LEVEL_HIGH
- 39 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "HW_CONV_END", "SW_CONV_END";
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "SW_CONV_END";
vddadc-supply = <&ab8500_ldo_adc_reg>;
#address-cells = <1>;
#size-cells = <0>;
bk_bat_v: channel@0c {
reg = <0x0c>;
};
+ die_temp: channel@0d {
+ reg = <0x0d>;
+ };
usb_id: channel@0e {
reg = <0x0e>;
};
};
ab8500_battery: ab8500_battery {
- status = "disabled";
+ stericsson,battery-type = "LIPO";
thermistor-on-batctrl;
};
ab8500_fg {
status = "disabled";
compatible = "stericsson,ab8500-fg";
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <8 IRQ_TYPE_LEVEL_HIGH>,
+ <28 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "NCONV_ACCU",
+ "BATT_OVV",
+ "LOW_BAT_F",
+ "CC_INT_CALIB",
+ "CCEOC";
battery = <&ab8500_battery>;
io-channels = <&gpadc 0x08>;
- io-channel-name = "main_bat_v";
+ io-channel-names = "main_bat_v";
};
ab8500_btemp {
status = "disabled";
compatible = "stericsson,ab8500-btemp";
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>,
+ <80 IRQ_TYPE_LEVEL_HIGH>,
+ <83 IRQ_TYPE_LEVEL_HIGH>,
+ <81 IRQ_TYPE_LEVEL_HIGH>,
+ <82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "BAT_CTRL_INDB",
+ "BTEMP_LOW",
+ "BTEMP_HIGH",
+ "BTEMP_LOW_MEDIUM",
+ "BTEMP_MEDIUM_HIGH";
battery = <&ab8500_battery>;
io-channels = <&gpadc 0x02>,
<&gpadc 0x01>;
- io-channel-name = "btemp_ball",
+ io-channel-names = "btemp_ball",
"bat_ctrl";
};
ab8500_charger {
status = "disabled";
compatible = "stericsson,ab8500-charger";
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 IRQ_TYPE_LEVEL_HIGH>,
+ <107 IRQ_TYPE_LEVEL_HIGH>,
+ <106 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <105 IRQ_TYPE_LEVEL_HIGH>,
+ <104 IRQ_TYPE_LEVEL_HIGH>,
+ <89 IRQ_TYPE_LEVEL_HIGH>,
+ <22 IRQ_TYPE_LEVEL_HIGH>,
+ <21 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "MAIN_CH_UNPLUG_DET",
+ "MAIN_CHARGE_PLUG_DET",
+ "MAIN_EXT_CH_NOT_OK",
+ "MAIN_CH_TH_PROT_R",
+ "MAIN_CH_TH_PROT_F",
+ "VBUS_DET_F",
+ "VBUS_DET_R",
+ "USB_LINK_STATUS",
+ "USB_CH_TH_PROT_R",
+ "USB_CH_TH_PROT_F",
+ "USB_CHARGER_NOT_OKR",
+ "VBUS_OVV",
+ "CH_WD_EXP",
+ "VBUS_CH_DROP_END";
battery = <&ab8500_battery>;
vddadc-supply = <&ab8500_ldo_adc_reg>;
io-channels = <&gpadc 0x09>,
<&gpadc 0x0b>;
- io-channel-name = "vbus_v",
+ io-channel-names = "vbus_v",
"usb_charger_c";
};
ab8500_usb: ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
musb_1v8-supply = <&db8500_vsmps2_reg>;
clocks = <&prcmu_clk PRCMU_SYSCLK>;
clock-names = "sysclk";
+ #phy-cells = <0>;
};
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
vana-supply = <&ab8500_ldo_ana_reg>;
};
};
+
+ usb_per5@a03e0000 {
+ phys = <&ab8500_usb>;
+ phy-names = "usb";
+ };
};
};
#include "ste-dbx5x0.dtsi"
/ {
+ /* FIXME: Remove this when clk driver is implemented */
+ sdmmcclk: sdmmcclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
soc {
- /* FIXME: Remove this when clk driver is implemented */
mtu@a03c6000 {
clock-frequency = <133000000>;
};
uart@80007000 {
clock = <38400000>;
};
+ mmc@80005000 {
+ clocks = <&sdmmcclk>;
+ };
};
reboot {
reg = <0x80150000 0x2000>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xa0412000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdi0_per1@80126000 {
+ mmc@80126000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80126000 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdi1_per2@80118000 {
+ mmc@80118000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80118000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdi2_per3@80005000 {
+ mmc@80005000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80005000 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdi3_per2@80119000 {
+ mmc@80119000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80119000 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdi4_per2@80114000 {
+ mmc@80114000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80114000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdi5_per3@80008000 {
+ mmc@80008000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80008000 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
+ /* eMMC */
+ mmc@80005000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <8>;
+
+ non-removable;
+ cap-mmc-highspeed;
+ };
+
/* Debugging console UART */
uart@80007000 {
status = "okay";
};
+
+ mcde@a0350000 {
+ status = "okay";
+ };
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+ smb@4000000 {
+ motherboard {
+ model = "V2M-P1";
+ arm,hbi = <0x190>;
+ arm,vexpress,site = <0>;
+ compatible = "arm,vexpress,v2m-p1", "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ ranges;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <1 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@2,00000000 {
+ compatible = "arm,vexpress-psram", "mtd-ram";
+ reg = <2 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ ethernet@3,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <3 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ vdd33a-supply = <&v2m_fixed_3v3>;
+ vddvario-supply = <&v2m_fixed_3v3>;
+ };
+
+ usb@3,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <3 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga@7,00000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 7 0 0x20000>;
+
+ v2m_sysreg: sysreg@0 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+
+ v2m_led_gpios: gpio@8 {
+ compatible = "arm,vexpress-sysreg,sys_led";
+ reg = <0x008 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ v2m_mmc_gpios: gpio@48 {
+ compatible = "arm,vexpress-sysreg,sys_mci";
+ reg = <0x048 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ v2m_flash_gpios: gpio@4c {
+ compatible = "arm,vexpress-sysreg,sys_flash";
+ reg = <0x04c 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ v2m_sysctl: sysctl@1000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x01000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@2000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x02000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@4000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x04000 0x1000>;
+ interrupts = <11>;
+ clocks = <&smbclk>;
+ clock-names = "apb_pclk";
+ };
+
+ mmc0: mmci@5000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x05000 0x1000>;
+ interrupts = <9>, <10>;
+ cd-gpios = <&v2m_mmc_gpios 0 0>;
+ wp-gpios = <&v2m_mmc_gpios 1 0>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&v2m_fixed_3v3>;
+ clocks = <&v2m_clk24mhz>, <&smbclk>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ v2m_serial0: uart@9000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x09000 0x1000>;
+ interrupts = <5>;
+ clocks = <&v2m_oscclk2>, <&smbclk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_serial1: uart@a000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a000 0x1000>;
+ interrupts = <6>;
+ clocks = <&v2m_oscclk2>, <&smbclk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_serial2: uart@b000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b000 0x1000>;
+ interrupts = <7>;
+ clocks = <&v2m_oscclk2>, <&smbclk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_serial3: uart@c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c000 0x1000>;
+ interrupts = <8>;
+ clocks = <&v2m_oscclk2>, <&smbclk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_timer01: timer@11000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x11000 0x1000>;
+ interrupts = <2>;
+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
+ };
+
+ v2m_timer23: timer@12000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <3>;
+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
+ };
+
+ /* DVI I2C bus */
+ v2m_i2c_dvi: i2c@16000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x16000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter@39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Both the core tile and the motherboard routes their output
+ * pads to this transmitter. The motherboard system controller
+ * can select one of them as input using a mux register in
+ * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
+ * the only platform with this specific set-up.
+ */
+ port@0 {
+ reg = <0>;
+ dvi_bridge_in_ct: endpoint {
+ remote-endpoint = <&clcd_pads_ct>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ dvi_bridge_in_mb: endpoint {
+ remote-endpoint = <&clcd_pads_mb>;
+ };
+ };
+ };
+ };
+
+ dvi-transmitter@60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@17000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x17000 0x1000>;
+ interrupts = <4>;
+ clocks = <&smbclk>;
+ clock-names = "apb_pclk";
+ };
+
+ compact-flash@1a000 {
+ compatible = "arm,vexpress-cf", "ata-generic";
+ reg = <0x1a000 0x100
+ 0x1a100 0xf00>;
+ reg-shift = <2>;
+ };
+
+
+ clcd@1f000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f000 0x1000>;
+ interrupt-names = "combined";
+ interrupts = <14>;
+ clocks = <&v2m_oscclk1>, <&smbclk>;
+ clock-names = "clcdclk", "apb_pclk";
+ /* 800x600 16bpp @36MHz works fine */
+ max-memory-bandwidth = <54000000>;
+ memory-region = <&vram>;
+
+ port {
+ clcd_pads_mb: endpoint {
+ remote-endpoint = <&dvi_bridge_in_mb>;
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+ };
+ };
+ };
+ };
+
+ v2m_fixed_3v3: fixed-regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ v2m_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "v2m:clk24mhz";
+ };
+
+ v2m_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "v2m:refclk1mhz";
+ };
+
+ v2m_refclk32khz: refclk32khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "v2m:refclk32khz";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user1 {
+ label = "v2m:green:user1";
+ gpios = <&v2m_led_gpios 0 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user2 {
+ label = "v2m:green:user2";
+ gpios = <&v2m_led_gpios 1 0>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user3 {
+ label = "v2m:green:user3";
+ gpios = <&v2m_led_gpios 2 0>;
+ linux,default-trigger = "cpu0";
+ };
+
+ user4 {
+ label = "v2m:green:user4";
+ gpios = <&v2m_led_gpios 3 0>;
+ linux,default-trigger = "cpu1";
+ };
+
+ user5 {
+ label = "v2m:green:user5";
+ gpios = <&v2m_led_gpios 4 0>;
+ linux,default-trigger = "cpu2";
+ };
+
+ user6 {
+ label = "v2m:green:user6";
+ gpios = <&v2m_led_gpios 5 0>;
+ linux,default-trigger = "cpu3";
+ };
+
+ user7 {
+ label = "v2m:green:user7";
+ gpios = <&v2m_led_gpios 6 0>;
+ linux,default-trigger = "cpu4";
+ };
+
+ user8 {
+ label = "v2m:green:user8";
+ gpios = <&v2m_led_gpios 7 0>;
+ linux,default-trigger = "cpu5";
+ };
+ };
+
+ mcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ oscclk0 {
+ /* MCC static memory clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 0>;
+ freq-range = <25000000 60000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk0";
+ };
+
+ v2m_oscclk1: oscclk1 {
+ /* CLCD clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 1>;
+ freq-range = <23750000 65000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk1";
+ };
+
+ v2m_oscclk2: oscclk2 {
+ /* IO FPGA peripheral clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 2>;
+ freq-range = <24000000 24000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk2";
+ };
+
+ volt-vio {
+ /* Logic level voltage */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 0>;
+ regulator-name = "VIO";
+ regulator-always-on;
+ label = "VIO";
+ };
+
+ temp-mcc {
+ /* MCC internal operating temperature */
+ compatible = "arm,vexpress-temp";
+ arm,vexpress-sysreg,func = <4 0>;
+ label = "MCC";
+ };
+
+ reset {
+ compatible = "arm,vexpress-reset";
+ arm,vexpress-sysreg,func = <5 0>;
+ };
+
+ muxfpga {
+ compatible = "arm,vexpress-muxfpga";
+ arm,vexpress-sysreg,func = <7 0>;
+ };
+
+ shutdown {
+ compatible = "arm,vexpress-shutdown";
+ arm,vexpress-sysreg,func = <8 0>;
+ };
+
+ reboot {
+ compatible = "arm,vexpress-reboot";
+ arm,vexpress-sysreg,func = <9 0>;
+ };
+
+ dvimode {
+ compatible = "arm,vexpress-dvimode";
+ arm,vexpress-sysreg,func = <11 0>;
+ };
+ };
+ };
+ };
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+#include "vexpress-v2m.dtsi"
+
+/ {
+ model = "V2P-CA9";
+ arm,hbi = <0x191>;
+ arm,vexpress,site = <0xf>;
+ compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ mmc0 = &mmc0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A9_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ A9_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ A9_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ A9_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Chipselect 3 is physically at 0x4c000000 */
+ vram: vram@4c000000 {
+ /* 8 MB of designated video RAM */
+ compatible = "shared-dma-pool";
+ reg = <0x4c000000 0x00800000>;
+ no-map;
+ };
+ };
+
+ clcd@10020000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x10020000 0x1000>;
+ interrupt-names = "combined";
+ interrupts = <0 44 4>;
+ clocks = <&oscclk1>, <&oscclk2>;
+ clock-names = "clcdclk", "apb_pclk";
+ /* 1024x768 16bpp @65MHz */
+ max-memory-bandwidth = <95000000>;
+
+ port {
+ clcd_pads_ct: endpoint {
+ remote-endpoint = <&dvi_bridge_in_ct>;
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+ };
+ };
+ };
+
+ memory-controller@100e0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x100e0000 0x1000>;
+ clocks = <&oscclk2>;
+ clock-names = "apb_pclk";
+ };
+
+ memory-controller@100e1000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x100e1000 0x1000>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ clocks = <&oscclk2>;
+ clock-names = "apb_pclk";
+ };
+
+ timer@100e4000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x100e4000 0x1000>;
+ interrupts = <0 48 4>,
+ <0 49 4>;
+ clocks = <&oscclk2>, <&oscclk2>;
+ clock-names = "timclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ watchdog@100e5000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x100e5000 0x1000>;
+ interrupts = <0 51 4>;
+ clocks = <&oscclk2>, <&oscclk2>;
+ clock-names = "wdogclk", "apb_pclk";
+ };
+
+ scu@1e000000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x1e000000 0x58>;
+ };
+
+ timer@1e000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x1e000600 0x20>;
+ interrupts = <1 13 0xf04>;
+ };
+
+ watchdog@1e000620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x1e000620 0x20>;
+ interrupts = <1 14 0xf04>;
+ };
+
+ gic: interrupt-controller@1e001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1e001000 0x1000>,
+ <0x1e000100 0x100>;
+ };
+
+ L2: cache-controller@1e00a000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1e00a000 0x1000>;
+ interrupts = <0 43 4>;
+ cache-unified;
+ cache-level = <2>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 60 4>,
+ <0 61 4>,
+ <0 62 4>,
+ <0 63 4>;
+ interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
+
+ };
+
+ dcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ oscclk0: extsaxiclk {
+ /* ACLK clock to the AXI master port on the test chip */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 0>;
+ freq-range = <30000000 50000000>;
+ #clock-cells = <0>;
+ clock-output-names = "extsaxiclk";
+ };
+
+ oscclk1: clcdclk {
+ /* Reference clock for the CLCD */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 1>;
+ freq-range = <10000000 80000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clcdclk";
+ };
+
+ smbclk: oscclk2: tcrefclk {
+ /* Reference clock for the test chip internal PLLs */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 2>;
+ freq-range = <33000000 100000000>;
+ #clock-cells = <0>;
+ clock-output-names = "tcrefclk";
+ };
+
+ volt-vd10 {
+ /* Test Chip internal logic voltage */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 0>;
+ regulator-name = "VD10";
+ regulator-always-on;
+ label = "VD10";
+ };
+
+ volt-vd10-s2 {
+ /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 1>;
+ regulator-name = "VD10_S2";
+ regulator-always-on;
+ label = "VD10_S2";
+ };
+
+ volt-vd10-s3 {
+ /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 2>;
+ regulator-name = "VD10_S3";
+ regulator-always-on;
+ label = "VD10_S3";
+ };
+
+ volt-vcc1v8 {
+ /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 3>;
+ regulator-name = "VCC1V8";
+ regulator-always-on;
+ label = "VCC1V8";
+ };
+
+ volt-ddr2vtt {
+ /* DDR2 SDRAM VTT termination voltage */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 4>;
+ regulator-name = "DDR2VTT";
+ regulator-always-on;
+ label = "DDR2VTT";
+ };
+
+ volt-vcc3v3 {
+ /* Local board supply for miscellaneous logic external to the Test Chip */
+ arm,vexpress-sysreg,func = <2 5>;
+ compatible = "arm,vexpress-volt";
+ regulator-name = "VCC3V3";
+ regulator-always-on;
+ label = "VCC3V3";
+ };
+
+ amp-vd10-s2 {
+ /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+ compatible = "arm,vexpress-amp";
+ arm,vexpress-sysreg,func = <3 0>;
+ label = "VD10_S2";
+ };
+
+ amp-vd10-s3 {
+ /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+ compatible = "arm,vexpress-amp";
+ arm,vexpress-sysreg,func = <3 1>;
+ label = "VD10_S3";
+ };
+
+ power-vd10-s2 {
+ /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+ compatible = "arm,vexpress-power";
+ arm,vexpress-sysreg,func = <12 0>;
+ label = "PVD10_S2";
+ };
+
+ power-vd10-s3 {
+ /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+ compatible = "arm,vexpress-power";
+ arm,vexpress-sysreg,func = <12 1>;
+ label = "PVD10_S3";
+ };
+ };
+
+ smb: smb@4000000 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x40000000 0x04000000>,
+ <1 0 0x44000000 0x04000000>,
+ <2 0 0x48000000 0x04000000>,
+ <3 0 0x4c000000 0x04000000>,
+ <7 0 0x10000000 0x00020000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+
+ site2: hsb@e0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe0000000 0x20000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 3>;
+ interrupt-map = <0 0 &gic 0 36 4>,
+ <0 1 &gic 0 37 4>,
+ <0 2 &gic 0 38 4>,
+ <0 3 &gic 0 39 4>;
+ };
+};
#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
status = "okay";
num-cs = <1>;
flash@0 {
- compatible = "spansion,s25fl256s", "jedec,spi-nor";
+ compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
m25p,fast-read;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
+ nvmem1 = &eeprom_ebm;
+ nvmem2 = &eeprom_fmc1;
+ nvmem3 = &eeprom_fmc2;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
silabs,skip-recall;
};
/* and connector J212D */
+ eeprom_ebm: eeprom@52 { /* x-ebm module */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x52>;
+ };
};
fmc1: i2c@1 { /* FMCP1_IIC */
#address-cells = <1>;
reg = <1>;
/* FIXME connection to Samtec J51C */
/* expected eeprom 0x50 FMC cards */
+ eeprom_fmc1: eeprom@50 {
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x50>;
+ };
};
fmc2: i2c@2 { /* FMCP2_IIC */
#address-cells = <1>;
reg = <2>;
/* FIXME connection to Samtec J53C */
/* expected eeprom 0x50 FMC cards */
+ eeprom_fmc2: eeprom@50 {
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x50>;
+ };
};
i2c@3 { /* DDR4_DIMM1 */
#address-cells = <1>;
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-0";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-1";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
void chilisom_enable_pin_mux(void);
void chilisom_spl_board_init(void);
#endif
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
+/* CM_SSC_DELTAM_DPLL */
+#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
+#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0)
+#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18
+#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18)
+
+/* CM_SSC_MODFREQ_DPLL */
+#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0
+#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0)
+#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7
+#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8)
+
struct dpll_params {
u32 m;
u32 n;
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
unsigned int resv2[11];
- unsigned int clkselmacclk; /* offset 0x34 */
+ unsigned int clkselmacclk; /* offset 0x34 */
};
#endif /* CONFIG_AM43XX */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef _ASM_ARCH_ARMADA100_H
-#define _ASM_ARCH_ARMADA100_H
-
-#if defined (CONFIG_ARMADA100)
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
-#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
-#define APBC_RST (1<<2) /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
-
-/* Fast Ethernet Controller Clock register definition */
-#define FE_CLK_RST 0x1
-#define FE_CLK_ENA 0x8
-
-/* SSP2 Clock Control */
-#define SSP2_APBCLK 0x01
-#define SSP2_FNCLK 0x02
-
-/* USB Clock/reset control bits */
-#define USB_SPH_AXICLK_EN 0x10
-#define USB_SPH_AXI_RST 0x02
-
-/* MPMU Clocks */
-#define APB2_26M_EN (1 << 20)
-#define AP_26M (1 << 4)
-
-/* Register Base Addresses */
-#define ARMD1_DRAM_BASE 0xB0000000
-#define ARMD1_FEC_BASE 0xC0800000
-#define ARMD1_TIMER_BASE 0xD4014000
-#define ARMD1_APBC1_BASE 0xD4015000
-#define ARMD1_APBC2_BASE 0xD4015800
-#define ARMD1_UART1_BASE 0xD4017000
-#define ARMD1_UART2_BASE 0xD4018000
-#define ARMD1_GPIO_BASE 0xD4019000
-#define ARMD1_SSP1_BASE 0xD401B000
-#define ARMD1_SSP2_BASE 0xD401C000
-#define ARMD1_MFPR_BASE 0xD401E000
-#define ARMD1_SSP3_BASE 0xD401F000
-#define ARMD1_SSP4_BASE 0xD4020000
-#define ARMD1_SSP5_BASE 0xD4021000
-#define ARMD1_UART3_BASE 0xD4026000
-#define ARMD1_MPMU_BASE 0xD4050000
-#define ARMD1_USB_HOST_BASE 0xD4209000
-#define ARMD1_APMU_BASE 0xD4282800
-#define ARMD1_CPU_BASE 0xD4282C00
-
-#endif /* CONFIG_ARMADA100 */
-#endif /* _ASM_ARCH_ARMADA100_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Armada100 platform
- */
-
-#ifndef _ARMD1_CONFIG_H
-#define _ARMD1_CONFIG_H
-
-#include <asm/arch/armada100.h>
-
-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
-#define MV_MFPR_BASE ARMD1_MFPR_BASE
-#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
- represents UART Unit Enable */
-
-#endif /* _ARMD1_CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef _ARMADA100CPU_H
-#define _ARMADA100CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Datasheet Appendix A.8
- */
-struct armd1mpmu_registers {
- u8 pad0[0x08 - 0x00];
- u32 fccr; /*0x0008*/
- u32 pocr; /*0x000c*/
- u32 posr; /*0x0010*/
- u32 succr; /*0x0014*/
- u8 pad1[0x030 - 0x014 - 4];
- u32 gpcr; /*0x0030*/
- u8 pad2[0x200 - 0x030 - 4];
- u32 wdtpcr; /*0x0200*/
- u8 pad3[0x1000 - 0x200 - 4];
- u32 apcr; /*0x1000*/
- u32 apsr; /*0x1004*/
- u8 pad4[0x1020 - 0x1004 - 4];
- u32 aprr; /*0x1020*/
- u32 acgr; /*0x1024*/
- u32 arsr; /*0x1028*/
-};
-
-/*
- * Application Subsystem Power Management
- * Refer Datasheet Appendix A.9
- */
-struct armd1apmu_registers {
- u32 pcr; /* 0x000 */
- u32 ccr; /* 0x004 */
- u32 pad1;
- u32 ccsr; /* 0x00C */
- u32 fc_timer; /* 0x010 */
- u32 pad2;
- u32 ideal_cfg; /* 0x018 */
- u8 pad3[0x04C - 0x018 - 4];
- u32 lcdcrc; /* 0x04C */
- u32 cciccrc; /* 0x050 */
- u32 sd1crc; /* 0x054 */
- u32 sd2crc; /* 0x058 */
- u32 usbcrc; /* 0x05C */
- u32 nfccrc; /* 0x060 */
- u32 dmacrc; /* 0x064 */
- u32 pad4;
- u32 buscrc; /* 0x06C */
- u8 pad5[0x07C - 0x06C - 4];
- u32 wake_clr; /* 0x07C */
- u8 pad6[0x090 - 0x07C - 4];
- u32 core_status; /* 0x090 */
- u32 rfsc; /* 0x094 */
- u32 imr; /* 0x098 */
- u32 irwc; /* 0x09C */
- u32 isr; /* 0x0A0 */
- u8 pad7[0x0B0 - 0x0A0 - 4];
- u32 mhst; /* 0x0B0 */
- u32 msr; /* 0x0B4 */
- u8 pad8[0x0C0 - 0x0B4 - 4];
- u32 msst; /* 0x0C0 */
- u32 pllss; /* 0x0C4 */
- u32 smb; /* 0x0C8 */
- u32 gccrc; /* 0x0CC */
- u8 pad9[0x0D4 - 0x0CC - 4];
- u32 smccrc; /* 0x0D4 */
- u32 pad10;
- u32 xdcrc; /* 0x0DC */
- u32 sd3crc; /* 0x0E0 */
- u32 sd4crc; /* 0x0E4 */
- u8 pad11[0x0F0 - 0x0E4 - 4];
- u32 cfcrc; /* 0x0F0 */
- u32 mspcrc; /* 0x0F4 */
- u32 cmucrc; /* 0x0F8 */
- u32 fecrc; /* 0x0FC */
- u32 pciecrc; /* 0x100 */
- u32 epdcrc; /* 0x104 */
-};
-
-/*
- * APB1 Clock Reset/Control Registers
- * Refer Datasheet Appendix A.10
- */
-struct armd1apb1_registers {
- u32 uart1; /*0x000*/
- u32 uart2; /*0x004*/
- u32 gpio; /*0x008*/
- u32 pwm1; /*0x00c*/
- u32 pwm2; /*0x010*/
- u32 pwm3; /*0x014*/
- u32 pwm4; /*0x018*/
- u8 pad0[0x028 - 0x018 - 4];
- u32 rtc; /*0x028*/
- u32 twsi0; /*0x02c*/
- u32 kpc; /*0x030*/
- u32 timers; /*0x034*/
- u8 pad1[0x03c - 0x034 - 4];
- u32 aib; /*0x03c*/
- u32 sw_jtag; /*0x040*/
- u32 timer1; /*0x044*/
- u32 onewire; /*0x048*/
- u8 pad2[0x050 - 0x048 - 4];
- u32 asfar; /*0x050 AIB Secure First Access Reg*/
- u32 assar; /*0x054 AIB Secure Second Access Reg*/
- u8 pad3[0x06c - 0x054 - 4];
- u32 twsi1; /*0x06c*/
- u32 uart3; /*0x070*/
- u8 pad4[0x07c - 0x070 - 4];
- u32 timer2; /*0x07C*/
- u8 pad5[0x084 - 0x07c - 4];
- u32 ac97; /*0x084*/
-};
-
-/*
-* APB2 Clock Reset/Control Registers
-* Refer Datasheet Appendix A.11
-*/
-struct armd1apb2_registers {
- u32 pad1[0x01C - 0x000];
- u32 ssp1_clkrst; /* 0x01C */
- u32 ssp2_clkrst; /* 0x020 */
- u32 pad2[0x04C - 0x020 - 4];
- u32 ssp3_clkrst; /* 0x04C */
- u32 pad3[0x058 - 0x04C - 4];
- u32 ssp4_clkrst; /* 0x058 */
- u32 ssp5_clkrst; /* 0x05C */
-};
-
-/*
- * CPU Interface Registers
- * Refer Datasheet Appendix A.2
- */
-struct armd1cpu_registers {
- u32 chip_id; /* Chip Id Reg */
- u32 pad;
- u32 cpu_conf; /* CPU Conf Reg */
- u32 pad1;
- u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
- u32 pad2;
- u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
- u32 mcb_conf; /* MCB Conf Reg */
- u32 sys_boot_ctl; /* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 armd1_sdram_base(int);
-u32 armd1_sdram_size(int);
-
-#endif /* _ARMADA100CPU_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef _ASM_ARCH_GPIO_H
-#define _ASM_ARCH_GPIO_H
-
-#include <asm/types.h>
-#include <asm/arch/armada100.h>
-
-#define GPIO_HIGH 1
-#define GPIO_LOW 0
-
-#define GPIO_TO_REG(gp) (gp >> 5)
-#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
-#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
-
-static inline void *get_gpio_base(int bank)
-{
- const unsigned int offset[4] = {0, 4, 8, 0x100};
- /* gpio register bank offset - refer Appendix A.36 */
- return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
-}
-
-#endif /* _ASM_ARCH_GPIO_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
- * (C) Copyright 2007
- * Marvell Semiconductor <www.marvell.com>
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef __ARMADA100_MFP_H
-#define __ARMADA100_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART1 */
-#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
-#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
-#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
-#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
-#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* UART2 */
-#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* UART3 */
-#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* I2c */
-#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-
-/* Fast Ethernet */
-#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-
-/* SPI */
-#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-
-#define MFP_PIN_MAX 117
-
-#endif /* __ARMADA100_MFP_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef __ARMADA100_SPI_H_
-#define __ARMADA100_SPI_H_
-
-#include <asm/arch/armada100.h>
-
-#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
-#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
-
-/*
- * SSP Serial Port Registers
- * refer Appendix A.26
- */
-struct ssp_reg {
- u32 sscr0; /* SSP Control Register 0 - 0x000 */
- u32 sscr1; /* SSP Control Register 1 - 0x004 */
- u32 sssr; /* SSP Status Register - 0x008 */
- u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
- u32 ssdr; /* SSP Data Register - 0x010 */
- u32 pad1[5];
- u32 ssto; /* SSP Timeout Register - 0x028 */
- u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
- u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
- u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
- u32 sstss; /* SSP Timeslot Status Register - 0x038 */
-};
-
-#define DEFAULT_WORD_LEN 8
-#define SSP_FLUSH_NUM 0x2000
-#define RX_THRESH_DEF 8
-#define TX_THRESH_DEF 8
-#define TIMEOUT_DEF 1000
-
-#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
-#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
-#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
-#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
- setting */
-#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
-#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
-#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
-#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
-
-#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
-#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
-#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
- Interrupt enable */
-
-#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
-#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
-#define SSCR0_FRF 0x30 /* FRame Format (mask) */
-#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
- Peripheral Interface */
-#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
- Serial Protocol (SSP) */
-#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
-#define SSCR0_ECS (1 << 6) /* External clock select */
-#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
- Enable */
-
-#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
-#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
-#define SSSR_BSY (1 << 4) /* SSP Busy */
-#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
-#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
-#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
-#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
-
-#endif /* __ARMADA100_SPI_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef __UTMI_ARMADA100__
-#define __UTMI_ARMADA100__
-
-#define UTMI_PHY_BASE 0xD4206000
-
-/* utmi_ctrl - bits */
-#define INPKT_DELAY_SOF (1 << 28)
-#define PLL_PWR_UP 2
-#define PHY_PWR_UP 1
-
-/* utmi_pll - bits */
-#define PLL_FBDIV_MASK 0x00000FF0
-#define PLL_FBDIV 4
-#define PLL_REFDIV_MASK 0x0000000F
-#define PLL_REFDIV 0
-#define PLL_READY 0x800000
-#define VCOCAL_START (1 << 21)
-
-#define N_DIVIDER 0xEE
-#define M_DIVIDER 0x0B
-
-/* utmi_tx - bits */
-#define CK60_PHSEL 17
-#define PHSEL_VAL 0x4
-#define RCAL_START (1 << 12)
-
-/*
- * USB PHY registers
- * Refer Datasheet Appendix A.21
- */
-struct armd1usb_phy_reg {
- u32 utmi_rev; /* USB PHY Revision */
- u32 utmi_ctrl; /* USB PHY Control register */
- u32 utmi_pll; /* PLL register */
- u32 utmi_tx; /* Tx register */
- u32 utmi_rx; /* Rx register */
- u32 utmi_ivref; /* IVREF register */
- u32 utmi_tst_g0; /* Test group 0 register */
- u32 utmi_tst_g1; /* Test group 1 register */
- u32 utmi_tst_g2; /* Test group 2 register */
- u32 utmi_tst_g3; /* Test group 3 register */
- u32 utmi_tst_g4; /* Test group 4 register */
- u32 utmi_tst_g5; /* Test group 5 register */
- u32 utmi_reserve; /* Reserve Register */
- u32 utmi_usb_int; /* USB interuppt register */
- u32 utmi_dbg_ctl; /* Debug control register */
- u32 utmi_otg_addon; /* OTG addon register */
-};
-
-int utmi_init(void);
-
-#endif /* __UTMI_ARMADA100__ */
#elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_GICV3
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define TZPC_BASE 0x02200000
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_EARLY_INIT
-#endif
#define SRDS_MAX_LANES 8
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
#define _ASM_ARCH_IMXRT_H
#endif /* _ASM_ARCH_IMXRT_H */
-
#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
-#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
-#endif
-
#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE 16
#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#else
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
#endif
#define CONFIG_SYS_NAND_ECCSIZE 0x100
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
#endif /* CONFIG_NAND_LPC32XX_SLC */
/* NOR Flash */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
- *
- * Modified for mx25 by John Rigby <jrigby@gmail.com>
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#ifdef CONFIG_MX25_HCLK_FREQ
-#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
-#else
-#define MXC_HCLK 24000000
-#endif
-
-#ifdef CONFIG_MX25_CLK32
-#define MXC_CLK32 CONFIG_MX25_CLK32
-#else
-#define MXC_CLK32 32768
-#endif
-
-enum mxc_clock {
- /* PER clocks (do not change order) */
- MXC_CSI_CLK,
- MXC_EPIT_CLK,
- MXC_ESAI_CLK,
- MXC_ESDHC1_CLK,
- MXC_ESDHC2_CLK,
- MXC_GPT_CLK,
- MXC_I2C_CLK,
- MXC_LCDC_CLK,
- MXC_NFC_CLK,
- MXC_OWIRE_CLK,
- MXC_PWM_CLK,
- MXC_SIM1_CLK,
- MXC_SIM2_CLK,
- MXC_SSI1_CLK,
- MXC_SSI2_CLK,
- MXC_UART_CLK,
- /* Other clocks */
- MXC_ARM_CLK,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_CSPI_CLK,
- MXC_FEC_CLK,
- MXC_CLK_NUM
-};
-
-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
-#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
-
-#endif /* __ASM_ARCH_CLOCK_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- */
-
-
-#ifndef __ASM_ARCH_MX25_GPIO_H
-#define __ASM_ARCH_MX25_GPIO_H
-
-#include <asm/mach-imx/gpio.h>
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009, DENX Software Engineering
- * Author: John Rigby <jcrigby@gmail.com
- *
- * Based on arch-mx31/imx-regs.h
- * Copyright (C) 2009 Ilya Yanok,
- * Emcraft Systems <yanok@emcraft.com>
- * and arch-mx27/imx-regs.h
- * Copyright (C) 2007 Pengutronix,
- * Sascha Hauer <s.hauer@pengutronix.de>
- * Copyright (C) 2009 Ilya Yanok,
- * Emcraft Systems <yanok@emcraft.com>
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
- u32 mpctl; /* Core PLL Control */
- u32 upctl; /* USB PLL Control */
- u32 cctl; /* Clock Control */
- u32 cgr0; /* Clock Gating Control 0 */
- u32 cgr1; /* Clock Gating Control 1 */
- u32 cgr2; /* Clock Gating Control 2 */
- u32 pcdr[4]; /* PER Clock Dividers */
- u32 rcsr; /* CCM Status */
- u32 crdr; /* CCM Reset and Debug */
- u32 dcvr0; /* DPTC Comparator Value 0 */
- u32 dcvr1; /* DPTC Comparator Value 1 */
- u32 dcvr2; /* DPTC Comparator Value 2 */
- u32 dcvr3; /* DPTC Comparator Value 3 */
- u32 ltr0; /* Load Tracking 0 */
- u32 ltr1; /* Load Tracking 1 */
- u32 ltr2; /* Load Tracking 2 */
- u32 ltr3; /* Load Tracking 3 */
- u32 ltbr0; /* Load Tracking Buffer 0 */
- u32 ltbr1; /* Load Tracking Buffer 1 */
- u32 pcmr0; /* Power Management Control 0 */
- u32 pcmr1; /* Power Management Control 1 */
- u32 pcmr2; /* Power Management Control 2 */
- u32 mcr; /* Miscellaneous Control */
- u32 lpimr0; /* Low Power Interrupt Mask 0 */
- u32 lpimr1; /* Low Power Interrupt Mask 1 */
-};
-
-/* Enhanced SDRAM Controller (ESDRAMC) registers */
-struct esdramc_regs {
- u32 ctl0; /* control 0 */
- u32 cfg0; /* configuration 0 */
- u32 ctl1; /* control 1 */
- u32 cfg1; /* configuration 1 */
- u32 misc; /* miscellaneous */
- u32 pad[3];
- u32 cdly1; /* Delay Line 1 configuration debug */
- u32 cdly2; /* delay line 2 configuration debug */
- u32 cdly3; /* delay line 3 configuration debug */
- u32 cdly4; /* delay line 4 configuration debug */
- u32 cdly5; /* delay line 5 configuration debug */
- u32 cdlyl; /* delay line cycle length debug */
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
- u32 ctrl; /* control */
- u32 pre; /* prescaler */
- u32 stat; /* status */
- u32 intr; /* interrupt */
- u32 cmp[3]; /* output compare 1-3 */
- u32 capt[2]; /* input capture 1-2 */
- u32 counter; /* counter */
-};
-
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
- u16 wcr; /* Control */
- u16 wsr; /* Service */
- u16 wrsr; /* Reset Status */
- u16 wicr; /* Interrupt Control */
- u16 wmcr; /* Misc Control */
-};
-
-/* IIM control registers */
-struct iim_regs {
- u32 iim_stat;
- u32 iim_statm;
- u32 iim_err;
- u32 iim_emask;
- u32 iim_fctl;
- u32 iim_ua;
- u32 iim_la;
- u32 iim_sdat;
- u32 iim_prev;
- u32 iim_srev;
- u32 iim_prg_p;
- u32 iim_scs0;
- u32 iim_scs1;
- u32 iim_scs2;
- u32 iim_scs3;
- u32 res1[0x1f1];
- struct fuse_bank {
- u32 fuse_regs[0x20];
- u32 fuse_rsvd[0xe0];
- } bank[3];
-};
-
-struct fuse_bank0_regs {
- u32 fuse0_7[8];
- u32 uid[8];
- u32 fuse16_25[0xa];
- u32 mac_addr[6];
-};
-
-struct fuse_bank1_regs {
- u32 fuse0_21[0x16];
- u32 usr5;
- u32 fuse23_29[7];
- u32 usr6[2];
-};
-
-/* Multi-Layer AHB Crossbar Switch (MAX) registers */
-struct max_regs {
- u32 mpr0;
- u32 pad00[3];
- u32 sgpcr0;
- u32 pad01[59];
- u32 mpr1;
- u32 pad02[3];
- u32 sgpcr1;
- u32 pad03[59];
- u32 mpr2;
- u32 pad04[3];
- u32 sgpcr2;
- u32 pad05[59];
- u32 mpr3;
- u32 pad06[3];
- u32 sgpcr3;
- u32 pad07[59];
- u32 mpr4;
- u32 pad08[3];
- u32 sgpcr4;
- u32 pad09[251];
- u32 mgpcr0;
- u32 pad10[63];
- u32 mgpcr1;
- u32 pad11[63];
- u32 mgpcr2;
- u32 pad12[63];
- u32 mgpcr3;
- u32 pad13[63];
- u32 mgpcr4;
-};
-
-/* AHB <-> IP-Bus Interface (AIPS) */
-struct aips_regs {
- u32 mpr_0_7;
- u32 mpr_8_15;
-};
-/* LCD controller registers */
-struct lcdc_regs {
- u32 lssar; /* Screen Start Address */
- u32 lsr; /* Size */
- u32 lvpwr; /* Virtual Page Width */
- u32 lcpr; /* Cursor Position */
- u32 lcwhb; /* Cursor Width Height and Blink */
- u32 lccmr; /* Color Cursor Mapping */
- u32 lpcr; /* Panel Configuration */
- u32 lhcr; /* Horizontal Configuration */
- u32 lvcr; /* Vertical Configuration */
- u32 lpor; /* Panning Offset */
- u32 lscr; /* Sharp Configuration */
- u32 lpccr; /* PWM Contrast Control */
- u32 ldcr; /* DMA Control */
- u32 lrmcr; /* Refresh Mode Control */
- u32 licr; /* Interrupt Configuration */
- u32 lier; /* Interrupt Enable */
- u32 lisr; /* Interrupt Status */
- u32 res0[3];
- u32 lgwsar; /* Graphic Window Start Address */
- u32 lgwsr; /* Graphic Window Size */
- u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
- u32 lgwpor; /* Graphic Window Panning Offset */
- u32 lgwpr; /* Graphic Window Position */
- u32 lgwcr; /* Graphic Window Control */
- u32 lgwdcr; /* Graphic Window DMA Control */
- u32 res1[5];
- u32 lauscr; /* AUS Mode Control */
- u32 lausccr; /* AUS mode Cursor Control */
- u32 res2[31 + 64*7];
- u32 bglut; /* Background Lookup Table */
- u32 gwlut; /* Graphic Window Lookup Table */
-};
-
-/* Wireless External Interface Module Registers */
-struct weim_regs {
- u32 cscr0u; /* Chip Select 0 Upper Register */
- u32 cscr0l; /* Chip Select 0 Lower Register */
- u32 cscr0a; /* Chip Select 0 Addition Register */
- u32 pad0;
- u32 cscr1u; /* Chip Select 1 Upper Register */
- u32 cscr1l; /* Chip Select 1 Lower Register */
- u32 cscr1a; /* Chip Select 1 Addition Register */
- u32 pad1;
- u32 cscr2u; /* Chip Select 2 Upper Register */
- u32 cscr2l; /* Chip Select 2 Lower Register */
- u32 cscr2a; /* Chip Select 2 Addition Register */
- u32 pad2;
- u32 cscr3u; /* Chip Select 3 Upper Register */
- u32 cscr3l; /* Chip Select 3 Lower Register */
- u32 cscr3a; /* Chip Select 3 Addition Register */
- u32 pad3;
- u32 cscr4u; /* Chip Select 4 Upper Register */
- u32 cscr4l; /* Chip Select 4 Lower Register */
- u32 cscr4a; /* Chip Select 4 Addition Register */
- u32 pad4;
- u32 cscr5u; /* Chip Select 5 Upper Register */
- u32 cscr5l; /* Chip Select 5 Lower Register */
- u32 cscr5a; /* Chip Select 5 Addition Register */
- u32 pad5;
- u32 wcr; /* WEIM Configuration Register */
-};
-
-/* Multi-Master Memory Interface */
-struct m3if_regs {
- u32 ctl; /* Control Register */
- u32 wcfg0; /* Watermark Configuration Register 0 */
- u32 wcfg1; /* Watermark Configuration Register1 */
- u32 wcfg2; /* Watermark Configuration Register2 */
- u32 wcfg3; /* Watermark Configuration Register 3 */
- u32 wcfg4; /* Watermark Configuration Register 4 */
- u32 wcfg5; /* Watermark Configuration Register 5 */
- u32 wcfg6; /* Watermark Configuration Register 6 */
- u32 wcfg7; /* Watermark Configuration Register 7 */
- u32 wcsr; /* Watermark Control and Status Register */
- u32 scfg0; /* Snooping Configuration Register 0 */
- u32 scfg1; /* Snooping Configuration Register 1 */
- u32 scfg2; /* Snooping Configuration Register 2 */
- u32 ssr0; /* Snooping Status Register 0 */
- u32 ssr1; /* Snooping Status Register 1 */
- u32 res0;
- u32 mlwe0; /* Master Lock WEIM CS0 Register */
- u32 mlwe1; /* Master Lock WEIM CS1 Register */
- u32 mlwe2; /* Master Lock WEIM CS2 Register */
- u32 mlwe3; /* Master Lock WEIM CS3 Register */
- u32 mlwe4; /* Master Lock WEIM CS4 Register */
- u32 mlwe5; /* Master Lock WEIM CS5 Register */
-};
-
-/* Pulse width modulation */
-struct pwm_regs {
- u32 cr; /* Control Register */
- u32 sr; /* Status Register */
- u32 ir; /* Interrupt Register */
- u32 sar; /* Sample Register */
- u32 pr; /* Period Register */
- u32 cnr; /* Counter Register */
-};
-
-/* Enhanced Periodic Interrupt Timer */
-struct epit_regs {
- u32 cr; /* Control register */
- u32 sr; /* Status register */
- u32 lr; /* Load register */
- u32 cmpr; /* Compare register */
- u32 cnr; /* Counter register */
-};
-
-#endif
-
-#define ARCH_MXC
-
-/* AIPS 1 */
-#define IMX_AIPS1_BASE (0x43F00000)
-#define IMX_MAX_BASE (0x43F04000)
-#define IMX_CLKCTL_BASE (0x43F08000)
-#define IMX_ETB_SLOT4_BASE (0x43F0C000)
-#define IMX_ETB_SLOT5_BASE (0x43F10000)
-#define IMX_ECT_CTIO_BASE (0x43F18000)
-#define I2C1_BASE_ADDR (0x43F80000)
-#define I2C3_BASE_ADDR (0x43F84000)
-#define IMX_CAN1_BASE (0x43F88000)
-#define IMX_CAN2_BASE (0x43F8C000)
-#define UART1_BASE (0x43F90000)
-#define UART2_BASE (0x43F94000)
-#define I2C2_BASE_ADDR (0x43F98000)
-#define IMX_OWIRE_BASE (0x43F9C000)
-#define IMX_CSPI1_BASE (0x43FA4000)
-#define IMX_KPP_BASE (0x43FA8000)
-#define IMX_IOPADMUX_BASE (0x43FAC000)
-#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
-#define IMX_IOPADCTL_BASE (0x43FAC22C)
-#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
-#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
-#define IMX_AUDMUX_BASE (0x43FB0000)
-#define IMX_ECT_IP1_BASE (0x43FB8000)
-#define IMX_ECT_IP2_BASE (0x43FBC000)
-
-/* SPBA */
-#define IMX_SPBA_BASE (0x50000000)
-#define IMX_CSPI3_BASE (0x50004000)
-#define UART4_BASE (0x50008000)
-#define UART3_BASE (0x5000C000)
-#define IMX_CSPI2_BASE (0x50010000)
-#define IMX_SSI2_BASE (0x50014000)
-#define IMX_ESAI_BASE (0x50018000)
-#define IMX_ATA_DMA_BASE (0x50020000)
-#define IMX_SIM1_BASE (0x50024000)
-#define IMX_SIM2_BASE (0x50028000)
-#define UART5_BASE (0x5002C000)
-#define IMX_TSC_BASE (0x50030000)
-#define IMX_SSI1_BASE (0x50034000)
-#define IMX_FEC_BASE (0x50038000)
-#define IMX_SPBA_CTRL_BASE (0x5003C000)
-
-/* AIPS 2 */
-#define IMX_AIPS2_BASE (0x53F00000)
-#define IMX_CCM_BASE (0x53F80000)
-#define IMX_GPT4_BASE (0x53F84000)
-#define IMX_GPT3_BASE (0x53F88000)
-#define IMX_GPT2_BASE (0x53F8C000)
-#define IMX_GPT1_BASE (0x53F90000)
-#define IMX_EPIT1_BASE (0x53F94000)
-#define IMX_EPIT2_BASE (0x53F98000)
-#define IMX_GPIO4_BASE (0x53F9C000)
-#define IMX_PWM2_BASE (0x53FA0000)
-#define IMX_GPIO3_BASE (0x53FA4000)
-#define IMX_PWM3_BASE (0x53FA8000)
-#define IMX_SCC_BASE (0x53FAC000)
-#define IMX_SCM_BASE (0x53FAE000)
-#define IMX_SMN_BASE (0x53FAF000)
-#define IMX_RNGD_BASE (0x53FB0000)
-#define IMX_MMC_SDHC1_BASE (0x53FB4000)
-#define IMX_MMC_SDHC2_BASE (0x53FB8000)
-#define IMX_LCDC_BASE (0x53FBC000)
-#define IMX_SLCDC_BASE (0x53FC0000)
-#define IMX_PWM4_BASE (0x53FC8000)
-#define IMX_GPIO1_BASE (0x53FCC000)
-#define IMX_GPIO2_BASE (0x53FD0000)
-#define IMX_SDMA_BASE (0x53FD4000)
-#define IMX_WDT_BASE (0x53FDC000)
-#define WDOG1_BASE_ADDR IMX_WDT_BASE
-#define IMX_PWM1_BASE (0x53FE0000)
-#define IMX_RTIC_BASE (0x53FEC000)
-#define IMX_IIM_BASE (0x53FF0000)
-#define IIM_BASE_ADDR IMX_IIM_BASE
-#define IMX_USB_BASE (0x53FF4000)
-/*
- * This is in contradiction to the imx25 reference manual, which says that
- * port 1's registers start at 0x53FF4200. The correct base address for
- * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
- */
-#define IMX_USB_PORT_OFFSET 0x400
-#define IMX_CSI_BASE (0x53FF8000)
-#define IMX_DRYICE_BASE (0x53FFC000)
-
-#define IMX_ARM926_ROMPATCH (0x60000000)
-#define IMX_ARM926_ASIC (0x68000000)
-
-/* 128K Internal Static RAM */
-#define IMX_RAM_BASE (0x78000000)
-#define IMX_RAM_SIZE (128 * 1024)
-
-/* SDRAM BANKS */
-#define IMX_SDRAM_BANK0_BASE (0x80000000)
-#define IMX_SDRAM_BANK1_BASE (0x90000000)
-
-#define IMX_WEIM_CS0 (0xA0000000)
-#define IMX_WEIM_CS1 (0xA8000000)
-#define IMX_WEIM_CS2 (0xB0000000)
-#define IMX_WEIM_CS3 (0xB2000000)
-#define IMX_WEIM_CS4 (0xB4000000)
-#define IMX_ESDRAMC_BASE (0xB8001000)
-#define IMX_WEIM_CTRL_BASE (0xB8002000)
-#define IMX_M3IF_CTRL_BASE (0xB8003000)
-#define IMX_EMI_CTRL_BASE (0xB8004000)
-
-/* NAND Flash Controller */
-#define IMX_NFC_BASE (0xBB000000)
-#define NFC_BASE_ADDR IMX_NFC_BASE
-
-/* CCM bitfields */
-#define CCM_PLL_MFI_SHIFT 10
-#define CCM_PLL_MFI_MASK 0xf
-#define CCM_PLL_MFN_SHIFT 0
-#define CCM_PLL_MFN_MASK 0x3ff
-#define CCM_PLL_MFD_SHIFT 16
-#define CCM_PLL_MFD_MASK 0x3ff
-#define CCM_PLL_PD_SHIFT 26
-#define CCM_PLL_PD_MASK 0xf
-#define CCM_CCTL_ARM_DIV_SHIFT 30
-#define CCM_CCTL_ARM_DIV_MASK 3
-#define CCM_CCTL_AHB_DIV_SHIFT 28
-#define CCM_CCTL_AHB_DIV_MASK 3
-#define CCM_CCTL_ARM_SRC (1 << 14)
-#define CCM_CGR1_GPT1 (1 << 19)
-#define CCM_PERCLK_REG(clk) (clk / 4)
-#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
-#define CCM_PERCLK_MASK 0x3f
-#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
-#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
-#define CCM_CRDR_BT_UART_SRC_SHIFT 29
-#define CCM_CRDR_BT_UART_SRC_MASK 7
-
-/* ESDRAM Controller register bitfields */
-#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
-#define ESDCTL_BL (1 << 7)
-#define ESDCTL_FP (1 << 8)
-#define ESDCTL_PWDT(x) (((x) & 3) << 10)
-#define ESDCTL_SREFR(x) (((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER (0 << 16)
-#define ESDCTL_DSIZ_16_LOWER (1 << 16)
-#define ESDCTL_DSIZ_32 (2 << 16)
-#define ESDCTL_COL8 (0 << 20)
-#define ESDCTL_COL9 (1 << 20)
-#define ESDCTL_COL10 (2 << 20)
-#define ESDCTL_ROW11 (0 << 24)
-#define ESDCTL_ROW12 (1 << 24)
-#define ESDCTL_ROW13 (2 << 24)
-#define ESDCTL_ROW14 (3 << 24)
-#define ESDCTL_ROW15 (4 << 24)
-#define ESDCTL_SP (1 << 27)
-#define ESDCTL_SMODE_NORMAL (0 << 28)
-#define ESDCTL_SMODE_PRECHARGE (1 << 28)
-#define ESDCTL_SMODE_AUTO_REF (2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
-#define ESDCTL_SMODE_MAN_REF (4 << 28)
-#define ESDCTL_SDE (1 << 31)
-
-#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
-#define ESDCFG_TWR (1 << 15)
-#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
-#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
-#define ESDCFG_TWTR (1 << 20)
-#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
-
-#define ESDMISC_RST (1 << 1)
-#define ESDMISC_MDDREN (1 << 2)
-#define ESDMISC_MDDR_DL_RST (1 << 3)
-#define ESDMISC_MDDR_MDIS (1 << 4)
-#define ESDMISC_LHD (1 << 5)
-#define ESDMISC_MA10_SHARE (1 << 6)
-#define ESDMISC_SDRAM_RDY (1 << 31)
-
-/* GPT bits */
-#define GPT_CTRL_SWR (1 << 15) /* Software reset */
-#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
-#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
-#define GPT_CTRL_TEN 1 /* Timer enable */
-
-/* WDOG enable */
-#define WCR_WDE 0x04
-#define WSR_UNLOCK1 0x5555
-#define WSR_UNLOCK2 0xAAAA
-
-/* MAX bits */
-#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
-
-/* M3IF bits */
-#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
-
-/* WEIM bits */
-/* 13 fields of the upper CS control register */
-#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
- cnc, wsc, ew, wws, edc) \
- ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
- (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
- (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
-/* 12 fields of the lower CS control register */
-#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
- csa, ebc, dsz, csn, psr, cre, wrap, csen) \
- ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
- (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
- (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
-/* 14 fields of the additional CS control register */
-#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
- wwu, age, cnc2, fce) \
- ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
- (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
- (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
- (age) << 2 | (cnc2) << 1 | (fce) << 0)
-
-/* Names used in GPIO driver */
-#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
-#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
-#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
-#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
-
-/*
- * CSPI register definitions
- */
-#define MXC_SPI_BASE_ADDRESSES \
- IMX_CSPI1_BASE, \
- IMX_CSPI2_BASE, \
- IMX_CSPI3_BASE
-
-#endif /* _IMX_REGS_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 ADVANSEE
- * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
- *
- * Based on mainline Linux i.MX iomux-mx25.h file:
- * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
- *
- * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- */
-
-#ifndef __IOMUX_MX25_H__
-#define __IOMUX_MX25_H__
-
-#include <asm/mach-imx/iomux-v3.h>
-
-/* Pad control groupings */
-#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
-#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-/*
- * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux-v3.h
- */
-
-/* PAD MUX ALT INPSE PATH PADCTRL */
-enum {
- MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
-
- MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
- MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
-
- MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
-
- MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
-
- MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
-
- MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
- MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
- MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
- MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
- MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
- MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
- MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
- MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
- MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
-
- MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
-
- MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
-
- MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
- MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
- MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
-
- MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
-
- MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
-
- MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
-
- MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
-
- MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
-
- MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
-
- MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
- MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
- MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
- MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
- MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
- MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
- MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
- MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
- MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
- MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
- MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
- MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
-
- /*
- * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
- * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
- * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
- * bug that configuring the SD1_CMD function doesn't enable the input path for
- * this pin.
- * This might have side effects for other hardware units that are connected to
- * that pin and use the respective function as input.
- */
- MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
- MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
- MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
- MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
- MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
- MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
- MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
- MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
- MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
- MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
- MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
- MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
- MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
- MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
- MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
- MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
- MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
- MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
- MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
- MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
- MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
- MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
- MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
- MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
- MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
- MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
- MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
- MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
- MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
- MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
- MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
- MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
- MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
- MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
-
- MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
- MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
-
- MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
-
- MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
-
- MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
- MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
- MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
- MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
- MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
- MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
- MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
-
- MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
-};
-
-#endif /* __IOMUX_MX25_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Matthias Weisser <weisserm@arcor.de>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Common asm macros for imx25
- */
-
-#ifndef __ASM_ARM_ARCH_MACRO_H__
-#define __ASM_ARM_ARCH_MACRO_H__
-#ifdef __ASSEMBLY__
-
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <asm/macro.h>
-
-/*
- * AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.
- *
- * Default argument values:
- * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
- * user-mode.
- */
-.macro init_aips mpr=0x77777777
- ldr r0, =IMX_AIPS1_BASE
- ldr r1, =\mpr
- str r1, [r0, #AIPS_MPR_0_7]
- str r1, [r0, #AIPS_MPR_8_15]
- ldr r2, =IMX_AIPS2_BASE
- str r1, [r2, #AIPS_MPR_0_7]
- str r1, [r2, #AIPS_MPR_8_15]
-.endm
-
-/*
- * MAX (Multi-Layer AHB Crossbar Switch) setup
- *
- * Default argument values:
- * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
- * - SGPCR: always park on last master
- * - MGPCR: restore default values
- */
-.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
- ldr r0, =IMX_MAX_BASE
- ldr r1, =\mpr
- str r1, [r0, #MAX_MPR0] /* for S0 */
- str r1, [r0, #MAX_MPR1] /* for S1 */
- str r1, [r0, #MAX_MPR2] /* for S2 */
- str r1, [r0, #MAX_MPR3] /* for S3 */
- str r1, [r0, #MAX_MPR4] /* for S4 */
- ldr r1, =\sgpcr
- str r1, [r0, #MAX_SGPCR0] /* for S0 */
- str r1, [r0, #MAX_SGPCR1] /* for S1 */
- str r1, [r0, #MAX_SGPCR2] /* for S2 */
- str r1, [r0, #MAX_SGPCR3] /* for S3 */
- str r1, [r0, #MAX_SGPCR4] /* for S4 */
- ldr r1, =\mgpcr
- str r1, [r0, #MAX_MGPCR0] /* for M0 */
- str r1, [r0, #MAX_MGPCR1] /* for M1 */
- str r1, [r0, #MAX_MGPCR2] /* for M2 */
- str r1, [r0, #MAX_MGPCR3] /* for M3 */
- str r1, [r0, #MAX_MGPCR4] /* for M4 */
-.endm
-
-/*
- * M3IF setup
- *
- * Default argument values:
- * - CTL:
- * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
- * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
- * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
- * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
- * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
- * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
- * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
- * ------------
- * 0x00000001
- */
-.macro init_m3if ctl=0x00000001
- /* M3IF Control Register (M3IFCTL) */
- write32 IMX_M3IF_CTRL_BASE, \ctl
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARM_ARCH_MACRO_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#ifdef CONFIG_MX35_HCLK_FREQ
-#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
-#else
-#define MXC_HCLK 24000000
-#endif
-
-#ifdef CONFIG_MX35_CLK32
-#define MXC_CLK32 CONFIG_MX35_CLK32
-#else
-#define MXC_CLK32 32768
-#endif
-
-enum mxc_clock {
- MXC_ARM_CLK,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_IPG_PERCLK,
- MXC_UART_CLK,
- MXC_ESDHC1_CLK,
- MXC_ESDHC2_CLK,
- MXC_ESDHC3_CLK,
- MXC_USB_CLK,
- MXC_CSPI_CLK,
- MXC_FEC_CLK,
- MXC_I2C_CLK,
-};
-
-enum mxc_main_clock {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- NFC_CLK,
- USB_CLK,
- HSP_CLK,
-};
-
-enum mxc_peri_clock {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSHC_CLK,
- ESDHC1_CLK,
- ESDHC2_CLK,
- ESDHC3_CLK,
- SPDIF_CLK,
- SPI1_CLK,
- SPI2_CLK,
-};
-
-u32 imx_get_uartclk(void);
-u32 imx_get_fecclk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#endif /* __ASM_ARCH_CLOCK_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
-#define __CPU_ARM1136_MX35_CRM_REGS_H__
-
-/* Register bit definitions */
-#define MXC_CCM_CCMR_WFI (1 << 30)
-#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29)
-#define MXC_CCM_CCMR_VSTBY (1 << 28)
-#define MXC_CCM_CCMR_WBEN (1 << 27)
-#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20
-#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
-#define MXC_CCM_CCMR_ROMW_OFFSET 18
-#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET 16
-#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
-#define MXC_CCM_CCMR_LPM_OFFSET 14
-#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
-#define MXC_CCM_CCMR_UPE (1 << 9)
-#define MXC_CCM_CCMR_MPE (1 << 3)
-
-#define MXC_CCM_PDR0_PER_SEL (1 << 26)
-#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23)
-#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20
-#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
-#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16
-#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
-#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
-#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
-#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
-#define MXC_CCM_PDR0_AUTO_CON 0x1
-
-#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28
-#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
-#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22
-#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22)
-#define MXC_CCM_PDR1_MSHC_M_U (1 << 7)
-
-#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27
-#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
-#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
-#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
-#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16)
-#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
-#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
-#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
-#define MXC_CCM_PDR2_SSI_M_U (1 << 6)
-#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0
-#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F)
-
-#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29
-#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29)
-#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
-#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
-#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16)
-#define MXC_CCM_PDR3_UART_M_U (1 << 14)
-#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8)
-#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
-
-#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
-#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
-#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
-#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22)
-#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
-#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16)
-#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
-#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10)
-#define MXC_CCM_PDR4_USB_M_U (1 << 9)
-
-/* Bit definitions for RCSR */
-#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29)
-#define MXC_CCM_RCSR_BUS_16BIT (1 << 29)
-#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27)
-#define MXC_CCM_RCSR_PAGE_512 (0 << 27)
-#define MXC_CCM_RCSR_PAGE_2K (1 << 27)
-#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27)
-#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27)
-#define MXC_CCM_RCSR_SOFT_RESET (1 << 15)
-#define MXC_CCM_RCSR_NF16B (1 << 14)
-#define MXC_CCM_RCSR_NFC_4K (1 << 9)
-#define MXC_CCM_RCSR_NFC_FMS (1 << 8)
-
-/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
-#define MXC_CCM_PCTL_BRM 0x80000000
-#define MXC_CCM_PCTL_PD_OFFSET 26
-#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
-#define MXC_CCM_PCTL_MFD_OFFSET 16
-#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
-#define MXC_CCM_PCTL_MFI_OFFSET 10
-#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
-#define MXC_CCM_PCTL_MFN_OFFSET 0
-#define MXC_CCM_PCTL_MFN_MASK 0x3FF
-
-/* Bit definitions for Audio clock mux register*/
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12)
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8)
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4)
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
-
-/* Bit definitions for Clock gating Register*/
-#define MXC_CCM_CGR_CG_MASK 0x3
-#define MXC_CCM_CGR_CG_OFF 0x0
-#define MXC_CCM_CGR_CG_RUN_ON 0x1
-#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2
-#define MXC_CCM_CGR_CG_ON 0x3
-
-#define MXC_CCM_CGR0_ASRC_OFFSET 0
-#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
-#define MXC_CCM_CGR0_ATA_OFFSET 2
-#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
-#define MXC_CCM_CGR0_CAN1_OFFSET 6
-#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
-#define MXC_CCM_CGR0_CAN2_OFFSET 8
-#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
-#define MXC_CCM_CGR0_CSPI1_OFFSET 10
-#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10)
-#define MXC_CCM_CGR0_CSPI2_OFFSET 12
-#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
-#define MXC_CCM_CGR0_ECT_OFFSET 14
-#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
-#define MXC_CCM_CGR0_EDIO_OFFSET 16
-#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16)
-#define MXC_CCM_CGR0_EMI_OFFSET 18
-#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
-#define MXC_CCM_CGR0_EPIT1_OFFSET 20
-#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20)
-#define MXC_CCM_CGR0_EPIT2_OFFSET 22
-#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22)
-#define MXC_CCM_CGR0_ESAI_OFFSET 24
-#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24)
-#define MXC_CCM_CGR0_ESDHC1_OFFSET 26
-#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26)
-#define MXC_CCM_CGR0_ESDHC2_OFFSET 28
-#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28)
-#define MXC_CCM_CGR0_ESDHC3_OFFSET 30
-#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30)
-
-#define MXC_CCM_CGR1_FEC_OFFSET 0
-#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0)
-#define MXC_CCM_CGR1_GPIO1_OFFSET 2
-#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2)
-#define MXC_CCM_CGR1_GPIO2_OFFSET 4
-#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4)
-#define MXC_CCM_CGR1_GPIO3_OFFSET 6
-#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6)
-#define MXC_CCM_CGR1_GPT_OFFSET 8
-#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8)
-#define MXC_CCM_CGR1_I2C1_OFFSET 10
-#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10)
-#define MXC_CCM_CGR1_I2C2_OFFSET 12
-#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12)
-#define MXC_CCM_CGR1_I2C3_OFFSET 14
-#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14)
-#define MXC_CCM_CGR1_IOMUXC_OFFSET 16
-#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16)
-#define MXC_CCM_CGR1_IPU_OFFSET 18
-#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18)
-#define MXC_CCM_CGR1_KPP_OFFSET 20
-#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
-#define MXC_CCM_CGR1_MLB_OFFSET 22
-#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22)
-#define MXC_CCM_CGR1_MSHC_OFFSET 24
-#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24)
-#define MXC_CCM_CGR1_OWIRE_OFFSET 26
-#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26)
-#define MXC_CCM_CGR1_PWM_OFFSET 28
-#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28)
-#define MXC_CCM_CGR1_RNGC_OFFSET 30
-#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30)
-
-#define MXC_CCM_CGR2_RTC_OFFSET 0
-#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0)
-#define MXC_CCM_CGR2_RTIC_OFFSET 2
-#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2)
-#define MXC_CCM_CGR2_SCC_OFFSET 4
-#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4)
-#define MXC_CCM_CGR2_SDMA_OFFSET 6
-#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6)
-#define MXC_CCM_CGR2_SPBA_OFFSET 8
-#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8)
-#define MXC_CCM_CGR2_SPDIF_OFFSET 10
-#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10)
-#define MXC_CCM_CGR2_SSI1_OFFSET 12
-#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12)
-#define MXC_CCM_CGR2_SSI2_OFFSET 14
-#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14)
-#define MXC_CCM_CGR2_UART1_OFFSET 16
-#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16)
-#define MXC_CCM_CGR2_UART2_OFFSET 18
-#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18)
-#define MXC_CCM_CGR2_UART3_OFFSET 20
-#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20)
-#define MXC_CCM_CGR2_USBOTG_OFFSET 22
-#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22)
-#define MXC_CCM_CGR2_WDOG_OFFSET 24
-#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24)
-#define MXC_CCM_CGR2_MAX_OFFSET 26
-#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26)
-#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26)
-#define MXC_CCM_CGR2_AUDMUX_OFFSET 30
-#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30)
-
-#define MXC_CCM_CGR3_CSI_OFFSET 0
-#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0)
-#define MXC_CCM_CGR3_IIM_OFFSET 2
-#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2)
-#define MXC_CCM_CGR3_GPU2D_OFFSET 4
-#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4)
-
-#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F
-#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
-#define MXC_CCM_COSR_CLKOEN (1 << 5)
-#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
-#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10)
-#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20)
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22)
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22
-#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- */
-
-
-#ifndef __ASM_ARCH_MX35_GPIO_H
-#define __ASM_ARCH_MX35_GPIO_H
-
-#include <asm/mach-imx/gpio.h>
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_MX35_H
-#define __ASM_ARCH_MX35_H
-
-#define ARCH_MXC
-
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
-#define IRAM_SIZE 0x00020000 /* 128 KB */
-
-#define LOW_LEVEL_SRAM_STACK 0x1001E000
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 0x43F00000
-#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
-#define MAX_BASE_ADDR 0x43F04000
-#define EVTMON_BASE_ADDR 0x43F08000
-#define CLKCTL_BASE_ADDR 0x43F0C000
-#define I2C1_BASE_ADDR 0x43F80000
-#define I2C3_BASE_ADDR 0x43F84000
-#define ATA_BASE_ADDR 0x43F8C000
-#define UART1_BASE 0x43F90000
-#define UART2_BASE 0x43F94000
-#define I2C2_BASE_ADDR 0x43F98000
-#define CSPI1_BASE_ADDR 0x43FA4000
-#define IOMUXC_BASE_ADDR 0x43FAC000
-
-/*
- * SPBA
- */
-#define SPBA_BASE_ADDR 0x50000000
-#define UART3_BASE 0x5000C000
-#define CSPI2_BASE_ADDR 0x50010000
-#define ATA_DMA_BASE_ADDR 0x50020000
-#define FEC_BASE_ADDR 0x50038000
-#define SPBA_CTRL_BASE_ADDR 0x5003C000
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR 0x53F00000
-#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
-#define CCM_BASE_ADDR 0x53F80000
-#define GPT1_BASE_ADDR 0x53F90000
-#define EPIT1_BASE_ADDR 0x53F94000
-#define EPIT2_BASE_ADDR 0x53F98000
-#define GPIO3_BASE_ADDR 0x53FA4000
-#define MMC_SDHC1_BASE_ADDR 0x53FB4000
-#define MMC_SDHC2_BASE_ADDR 0x53FB8000
-#define MMC_SDHC3_BASE_ADDR 0x53FBC000
-#define IPU_CTRL_BASE_ADDR 0x53FC0000
-#define GPIO1_BASE_ADDR 0x53FCC000
-#define GPIO2_BASE_ADDR 0x53FD0000
-#define SDMA_BASE_ADDR 0x53FD4000
-#define RTC_BASE_ADDR 0x53FD8000
-#define WDOG1_BASE_ADDR 0x53FDC000
-#define PWM_BASE_ADDR 0x53FE0000
-#define RTIC_BASE_ADDR 0x53FEC000
-#define IIM_BASE_ADDR 0x53FF0000
-#define IMX_USB_BASE 0x53FF4000
-#define IMX_USB_PORT_OFFSET 0x400
-
-#define IMX_CCM_BASE CCM_BASE_ADDR
-
-/*
- * ROMPATCH and AVIC
- */
-#define ROMPATCH_BASE_ADDR 0x60000000
-#define AVIC_BASE_ADDR 0x68000000
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define EXT_MEM_CTRL_BASE 0xB8000000
-#define ESDCTL_BASE_ADDR 0xB8001000
-#define WEIM_BASE_ADDR 0xB8002000
-#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
-#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
-#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
-#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
-#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
-#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
-#define M3IF_BASE_ADDR 0xB8003000
-#define EMI_BASE_ADDR 0xB8004000
-
-#define NFC_BASE_ADDR 0xBB000000
-
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR 0x70000000
-#define CSD0_BASE_ADDR 0x80000000
-#define CSD1_BASE_ADDR 0x90000000
-#define CS0_BASE_ADDR 0xA0000000
-#define CS1_BASE_ADDR 0xA8000000
-#define CS2_BASE_ADDR 0xB0000000
-#define CS3_BASE_ADDR 0xB2000000
-#define CS4_BASE_ADDR 0xB4000000
-#define CS5_BASE_ADDR 0xB6000000
-
-/*
- * IRQ Controller Register Definitions.
- */
-#define AVIC_NIMASK 0x04
-#define AVIC_INTTYPEH 0x18
-#define AVIC_INTTYPEL 0x1C
-
-/* L210 */
-#define L2CC_BASE_ADDR 0x30000000
-#define L2_CACHE_LINE_SIZE 32
-#define L2_CACHE_CTL_REG 0x100
-#define L2_CACHE_AUX_CTL_REG 0x104
-#define L2_CACHE_SYNC_REG 0x730
-#define L2_CACHE_INV_LINE_REG 0x770
-#define L2_CACHE_INV_WAY_REG 0x77C
-#define L2_CACHE_CLEAN_LINE_REG 0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
-#define L2_CACHE_DBG_CTL_REG 0xF40
-
-#define CLKMODE_AUTO 0
-#define CLKMODE_CONSUMER 1
-
-#define PLL_PD(x) (((x) & 0xf) << 26)
-#define PLL_MFD(x) (((x) & 0x3ff) << 16)
-#define PLL_MFI(x) (((x) & 0xf) << 10)
-#define PLL_MFN(x) (((x) & 0x3ff) << 0)
-
-#define _PLL_BRM(x) ((x) << 31)
-#define _PLL_PD(x) (((x) - 1) << 26)
-#define _PLL_MFD(x) (((x) - 1) << 16)
-#define _PLL_MFI(x) ((x) << 10)
-#define _PLL_MFN(x) (x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
- (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
- _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
-#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
-#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
-#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
-
-#define IIM_SREV 0x24
-#define ROMPATCH_REV 0x40
-
-#define IPU_CONF IPU_CTRL_BASE_ADDR
-
-#define IPU_CONF_PXL_ENDIAN (1<<8)
-#define IPU_CONF_DU_EN (1<<7)
-#define IPU_CONF_DI_EN (1<<6)
-#define IPU_CONF_ADC_EN (1<<5)
-#define IPU_CONF_SDC_EN (1<<4)
-#define IPU_CONF_PF_EN (1<<3)
-#define IPU_CONF_ROT_EN (1<<2)
-#define IPU_CONF_IC_EN (1<<1)
-#define IPU_CONF_CSI_EN (1<<0)
-
-/*
- * CSPI register definitions
- */
-#define MXC_SPI_BASE_ADDRESSES \
- 0x43fa4000, \
- 0x50010000,
-
-#define GPIO_PORT_NUM 3
-#define GPIO_NUM_PIN 32
-
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_2_0 0x20
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
- u32 ccmr; /* Control */
- u32 pdr0; /* Post divider 0 */
- u32 pdr1; /* Post divider 1 */
- u32 pdr2; /* Post divider 2 */
- u32 pdr3; /* Post divider 3 */
- u32 pdr4; /* Post divider 4 */
- u32 rcsr; /* CCM Status */
- u32 mpctl; /* Core PLL Control */
- u32 ppctl; /* Peripheral PLL Control */
- u32 acmr; /* Audio clock mux */
- u32 cosr; /* Clock out source */
- u32 cgr0; /* Clock Gating Control 0 */
- u32 cgr1; /* Clock Gating Control 1 */
- u32 cgr2; /* Clock Gating Control 2 */
- u32 cgr3; /* Clock Gating Control 3 */
- u32 reserved;
- u32 dcvr0; /* DPTC Comparator 0 */
- u32 dcvr1; /* DPTC Comparator 0 */
- u32 dcvr2; /* DPTC Comparator 0 */
- u32 dcvr3; /* DPTC Comparator 0 */
- u32 ltr0; /* Load Tracking 0 */
- u32 ltr1; /* Load Tracking 1 */
- u32 ltr2; /* Load Tracking 2 */
- u32 ltr3; /* Load Tracking 3 */
- u32 ltbr0; /* Load Tracking Buffer 0 */
-};
-
-/* IIM control registers */
-struct iim_regs {
- u32 iim_stat;
- u32 iim_statm;
- u32 iim_err;
- u32 iim_emask;
- u32 iim_fctl;
- u32 iim_ua;
- u32 iim_la;
- u32 iim_sdat;
- u32 iim_prev;
- u32 iim_srev;
- u32 iim_prg_p;
- u32 iim_scs0;
- u32 iim_scs1;
- u32 iim_scs2;
- u32 iim_scs3;
- u32 res1[0x1f1];
- struct fuse_bank {
- u32 fuse_regs[0x20];
- u32 fuse_rsvd[0xe0];
- } bank[3];
-};
-
-struct fuse_bank0_regs {
- u32 fuse0_7[8];
- u32 uid[8];
- u32 fuse16_31[0x10];
-};
-
-struct fuse_bank1_regs {
- u32 fuse0_21[0x16];
- u32 usr;
- u32 fuse23_31[9];
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
- u32 ctrl; /* control */
- u32 pre; /* prescaler */
- u32 stat; /* status */
- u32 intr; /* interrupt */
- u32 cmp[3]; /* output compare 1-3 */
- u32 capt[2]; /* input capture 1-2 */
- u32 counter; /* counter */
-};
-
-struct esdc_regs {
- u32 esdctl0;
- u32 esdcfg0;
- u32 esdctl1;
- u32 esdcfg1;
- u32 esdmisc;
- u32 reserved[4];
- u32 esdcdly[5];
- u32 esdcdlyl;
-};
-
-#define ESDC_MISC_RST (1 << 1)
-#define ESDC_MISC_MDDR_EN (1 << 2)
-#define ESDC_MISC_MDDR_DL_RST (1 << 3)
-#define ESDC_MISC_DDR_EN (1 << 8)
-#define ESDC_MISC_DDR2_EN (1 << 9)
-
-/* Multi-Layer AHB Crossbar Switch (MAX) registers */
-struct max_regs {
- u32 mpr0;
- u32 pad00[3];
- u32 sgpcr0;
- u32 pad01[59];
- u32 mpr1;
- u32 pad02[3];
- u32 sgpcr1;
- u32 pad03[59];
- u32 mpr2;
- u32 pad04[3];
- u32 sgpcr2;
- u32 pad05[59];
- u32 mpr3;
- u32 pad06[3];
- u32 sgpcr3;
- u32 pad07[59];
- u32 mpr4;
- u32 pad08[3];
- u32 sgpcr4;
- u32 pad09[251];
- u32 mgpcr0;
- u32 pad10[63];
- u32 mgpcr1;
- u32 pad11[63];
- u32 mgpcr2;
- u32 pad12[63];
- u32 mgpcr3;
- u32 pad13[63];
- u32 mgpcr4;
- u32 pad14[63];
- u32 mgpcr5;
-};
-
-/* AHB <-> IP-Bus Interface (AIPS) */
-struct aips_regs {
- u32 mpr_0_7;
- u32 mpr_8_15;
- u32 pad0[6];
- u32 pacr_0_7;
- u32 pacr_8_15;
- u32 pacr_16_23;
- u32 pacr_24_31;
- u32 pad1[4];
- u32 opacr_0_7;
- u32 opacr_8_15;
- u32 opacr_16_23;
- u32 opacr_24_31;
- u32 opacr_32_39;
-};
-
-/*
- * NFMS bit in RCSR register for pagesize of nandflash
- */
-#define NFMS_BIT 8
-#define NFMS_NF_DWIDTH 14
-#define NFMS_NF_PG_SZ 8
-
-#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
-
-#endif
-
-/*
- * Generic timer support
- */
-#ifdef CONFIG_MX35_CLK32
-#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32
-#else
-#define CONFIG_SYS_TIMER_RATE 32768
-#endif
-
-#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36)
-
-#endif /* __ASM_ARCH_MX35_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 ADVANSEE
- * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
- *
- * Based on mainline Linux i.MX iomux-mx35.h file:
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- */
-
-#ifndef __IOMUX_MX35_H__
-#define __IOMUX_MX35_H__
-
-#include <asm/mach-imx/iomux-v3.h>
-
-/*
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
- * See also iomux-v3.h
- */
-
-/* PAD MUX ALT INPSE PATH PADCTRL */
-enum {
- MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
- MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
- MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
-
- MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
- MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
-
- MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
- MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
-
- MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
-
- MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
- MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
-
- MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
- MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
- MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
-
- MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
-
- MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
- MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
- MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
- MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
- MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
- MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
- MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
- MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
- MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
- MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
- MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
- MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
- MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
- MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
- MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
- MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
-
- MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
- MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
- MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
- MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
- MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
- MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
- MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
- MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
- MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
- MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
- MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
- MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
- MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
- MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
- MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
- MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
- MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
- MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
- MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
- MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
- MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
- MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
-
- MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
- MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
- MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
-
- MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
- MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
- MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
- MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
-
- MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
- MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
- MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
- MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
-
- MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
- MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
- MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
-
- MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
- MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
- MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
-
- MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
- MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
- MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
- MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
-
- MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
- MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
- MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
- MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
- MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
-
- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
- MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
- MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
- MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
- MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
- MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
- MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
- MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
- MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
- MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
- MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
- MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
- MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
- MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
- MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
- MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
- MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
- MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
-
- MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
- MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
- MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
- MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
- MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
- MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
- MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
- MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
- MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
- MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
- MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
-
- MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
- MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
- MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
- MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
- MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
- MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
- MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
- MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
- MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
- MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
- MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
- MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
- MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
- MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
- MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
- MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
- MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
- MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
- MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
- MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
- MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
- MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
- MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
- MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
- MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
- MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
- MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
- MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
- MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
- MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
- MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
- MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
- MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
- MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
- MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
- MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
- MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
- MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
- MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
- MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
- MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
-
- MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
- MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
-
- MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
-
- MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
-
- MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
- MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
-
- MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
- MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
- MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
- MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
- MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
-
- MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
- MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
-
- MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
- MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-
- MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
-};
-
-#endif /* __IOMUX_MX35_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <asm/macro.h>
-
-/*
- * AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.
- *
- * Default argument values:
- * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
- * user-mode.
- * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
- * SDMA to access them.
- */
-.macro init_aips mpr=0x77777777, opacr=0x00000000
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =\mpr
- str r1, [r0, #AIPS_MPR_0_7]
- str r1, [r0, #AIPS_MPR_8_15]
- ldr r2, =AIPS2_BASE_ADDR
- str r1, [r2, #AIPS_MPR_0_7]
- str r1, [r2, #AIPS_MPR_8_15]
-
- /* Did not change the AIPS control registers access type. */
- ldr r1, =\opacr
- str r1, [r0, #AIPS_OPACR_0_7]
- str r1, [r0, #AIPS_OPACR_8_15]
- str r1, [r0, #AIPS_OPACR_16_23]
- str r1, [r0, #AIPS_OPACR_24_31]
- str r1, [r0, #AIPS_OPACR_32_39]
- str r1, [r2, #AIPS_OPACR_0_7]
- str r1, [r2, #AIPS_OPACR_8_15]
- str r1, [r2, #AIPS_OPACR_16_23]
- str r1, [r2, #AIPS_OPACR_24_31]
- str r1, [r2, #AIPS_OPACR_32_39]
-.endm
-
-/*
- * MAX (Multi-Layer AHB Crossbar Switch) setup
- *
- * Default argument values:
- * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
- * - SGPCR: always park on last master
- * - MGPCR: restore default values
- */
-.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
- ldr r0, =MAX_BASE_ADDR
- ldr r1, =\mpr
- str r1, [r0, #MAX_MPR0] /* for S0 */
- str r1, [r0, #MAX_MPR1] /* for S1 */
- str r1, [r0, #MAX_MPR2] /* for S2 */
- str r1, [r0, #MAX_MPR3] /* for S3 */
- str r1, [r0, #MAX_MPR4] /* for S4 */
- ldr r1, =\sgpcr
- str r1, [r0, #MAX_SGPCR0] /* for S0 */
- str r1, [r0, #MAX_SGPCR1] /* for S1 */
- str r1, [r0, #MAX_SGPCR2] /* for S2 */
- str r1, [r0, #MAX_SGPCR3] /* for S3 */
- str r1, [r0, #MAX_SGPCR4] /* for S4 */
- ldr r1, =\mgpcr
- str r1, [r0, #MAX_MGPCR0] /* for M0 */
- str r1, [r0, #MAX_MGPCR1] /* for M1 */
- str r1, [r0, #MAX_MGPCR2] /* for M2 */
- str r1, [r0, #MAX_MGPCR3] /* for M3 */
- str r1, [r0, #MAX_MGPCR4] /* for M4 */
- str r1, [r0, #MAX_MGPCR5] /* for M5 */
-.endm
-
-/*
- * M3IF setup
- *
- * Default argument values:
- * - CTL:
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
- * ------------
- * 0x00000040
- */
-.macro init_m3if ctl=0x00000040
- /* M3IF Control Register (M3IFCTL) */
- write32 M3IF_BASE_ADDR, \ctl
-.endm
-
-.macro core_init
- mrc p15, 0, r1, c1, c0, 0
-
- /* Set branch prediction enable */
- mrc p15, 0, r0, c1, c0, 1
- orr r0, r0, #7
- mcr p15, 0, r0, c1, c0, 1
- orr r1, r1, #1 << 11
-
- /* Set unaligned access enable */
- orr r1, r1, #1 << 22
-
- /* Set low int latency enable */
- orr r1, r1, #1 << 21
-
- mcr p15, 0, r1, c1, c0, 0
-
- mov r0, #0
-
- mcr p15, 0, r0, c15, c2, 4
-
- mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
- mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
- mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
-
- /* Setup the Peripheral Port Memory Remap Register */
- ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
- mcr p15, 0, r0, c15, c2, 4
-.endm
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- */
-
-#ifndef MMC_HOST_DEF_H
-#define MMC_HOST_DEF_H
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-
-#endif /* MMC_HOST_DEF_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- */
-
-#ifndef _MX35_SYS_PROTO_H_
-#define _MX35_SYS_PROTO_H_
-
-#include <asm/mach-imx/sys_proto.h>
-
-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
- u32 col, u32 dsize, u32 refresh);
-
-#endif
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#else
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
-#define ROM_VERSION_OFFSET 0x48
+#define ROM_VERSION_OFFSET 0x48
#endif
#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
/* GLB_RST_CON */
PMU_GLB_SRST_CTRL_SHIFT = 2,
PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
- PMU_RST_BY_FST_GLB_SRST = 0,
- PMU_RST_BY_SND_GLB_SRST = 1,
+ PMU_RST_BY_FST_GLB_SRST = 0,
+ PMU_RST_BY_SND_GLB_SRST = 1,
PMU_RST_DISABLE = 2,
WDT_GLB_SRST_CTRL_SHIFT = 1,
WDT_GLB_SRST_CTRL_MASK = BIT(1),
- WDT_TRIGGER_SND_GLB_SRST = 0,
- WDT_TRIGGER_FST_GLB_SRST = 1,
- TSADC_GLB_SRST_CTRL_SHIFT = 0,
- TSADC_GLB_SRST_CTRL_MASK = BIT(0),
- TSADC_TRIGGER_SND_GLB_SRST = 0,
- TSADC_TRIGGER_FST_GLB_SRST = 1,
+ WDT_TRIGGER_SND_GLB_SRST = 0,
+ WDT_TRIGGER_FST_GLB_SRST = 1,
+ TSADC_GLB_SRST_CTRL_SHIFT = 0,
+ TSADC_GLB_SRST_CTRL_MASK = BIT(0),
+ TSADC_TRIGGER_SND_GLB_SRST = 0,
+ TSADC_TRIGGER_FST_GLB_SRST = 1,
};
#endif
/* init rockusb device, tell rockusb which device you want to read/write*/
void rockusb_dev_init(char *dev_type, int dev_index);
#endif /* _F_ROCKUSB_H_ */
-
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_STM32F_H */
-
extern int clock_setup(enum periph_clock);
#endif
-
#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
/* GPIO bank sizes */
-#define SUNXI_GPIO_A_NR 32
-#define SUNXI_GPIO_B_NR 32
-#define SUNXI_GPIO_C_NR 32
-#define SUNXI_GPIO_D_NR 32
-#define SUNXI_GPIO_E_NR 32
-#define SUNXI_GPIO_F_NR 32
-#define SUNXI_GPIO_G_NR 32
-#define SUNXI_GPIO_H_NR 32
-#define SUNXI_GPIO_I_NR 32
-#define SUNXI_GPIO_L_NR 32
-#define SUNXI_GPIO_M_NR 32
+#define SUNXI_GPIOS_PER_BANK 32
#define SUNXI_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + 0)
+ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
enum sunxi_gpio_number {
SUNXI_GPIO_A_START = 0,
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
-#define SUN6I_GPA_SDC2 5
-#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
-#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
-#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
-int sunxi_name_to_gpio_bank(const char *name);
int sunxi_name_to_gpio(const char *name);
-#define name_to_gpio(name) sunxi_name_to_gpio(name)
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
int axp_gpio_init(void);
VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+ VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
- VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
extern void udc_disconnect(void);
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
+#ifdef CONFIG_SUPPORT_PASSING_ATAGS
# define BOOTM_ENABLE_TAGS 1
#else
# define BOOTM_ENABLE_TAGS 0
struct tag_serialnr;
#ifdef CONFIG_SERIAL_TAG
#define BOOTM_ENABLE_SERIAL_TAG 1
-void get_board_serial(struct tag_serialnr *serialnr);
#else
#define BOOTM_ENABLE_SERIAL_TAG 0
+#endif
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
static inline void get_board_serial(struct tag_serialnr *serialnr)
{
}
#define MACH_TYPE_BMS 259
#define MACH_TYPE_IXCDP1100 260
#define MACH_TYPE_PRPMC1100 261
-#define MACH_TYPE_AT91RM9200DK 262
#define MACH_TYPE_ARMSTICK 263
#define MACH_TYPE_ARMONIE 264
#define MACH_TYPE_MPORT1 265
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
#else
- b \master_label
+ b \master_label
#endif
.endm
* For loading 64-bit OS, x0 is physical address to the FDT blob.
* They will be passed to the guest.
*/
-.macro armv8_switch_to_el1_m, ep, flag, tmp
+.macro armv8_switch_to_el1_m, ep, flag, tmp, tmp2
/* Initialize Generic Timers */
mrs \tmp, cnthctl_el2
/* Enable EL1 access to timers */
b.eq 1f
/* Initialize HCR_EL2 */
- ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+ /* Only disable PAuth traps if PAuth is supported */
+ mrs \tmp, id_aa64isar1_el1
+ ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \
+ ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA)
+ tst \tmp, \tmp2
+ mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+ orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API)
+ csel \tmp, \tmp2, \tmp, eq
msr hcr_el2, \tmp
/* Return to the EL1_SP1 mode from EL2 */
#endif
extern void * memcpy(void *, const void *, __kernel_size_t);
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE)
+#define __HAVE_ARCH_MEMMOVE
+#else
#undef __HAVE_ARCH_MEMMOVE
+#endif
extern void * memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR
/*
* HCR_EL2 bits definitions
*/
+#define HCR_EL2_API (1 << 41) /* Trap pointer authentication
+ instructions */
+#define HCR_EL2_APK (1 << 40) /* Trap pointer authentication
+ key access */
#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
/*
+ * ID_AA64ISAR1_EL1 bits definitions
+ */
+#define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic
+ code auth algorithm */
+#define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth
+ algorithm */
+#define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address
+ auth algorithm */
+#define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */
+
+/*
* ID_AA64PFR0_EL1 bits definitions
*/
#define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */
u32 psci_migrate_info_type(void);
void psci_system_off(void);
void psci_system_reset(void);
-s32 psci_features(u32 function_id, u32 psci_fid);
#endif
#endif /* __ASSEMBLY__ */
#ifndef _DAVINCI_NAND_H_
#define _DAVINCI_NAND_H_
-#include <linux/mtd/rawnand.h>
#include <asm/arch/hardware.h>
-#define NAND_READ_START 0x00
-#define NAND_READ_END 0x30
-#define NAND_STATUS 0x70
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
#define MASK_CLE 0x10
#define MASK_ALE 0x08
*/
extern unsigned long rom_pointer[];
-
obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
endif
+ifdef CONFIG_ARM64
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o
+else
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
+endif
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
obj-y += bdinfo.o
#include <linux/kbuild.h>
#include <linux/arm-smccc.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
+#if defined(CONFIG_MX27) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
* code. Is it better to define the macros directly in headers?
*/
-#if defined(CONFIG_MX25)
- /* Clock Control Module */
- DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
- DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
- DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
- DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
- DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
- DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
-
- /* Enhanced SDRAM Controller */
- DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
- DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
- DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
-
- /* Multi-Layer AHB Crossbar Switch */
- DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
- DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
- DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
- DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
- DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
- DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
- DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
- DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
- DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
- DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
- DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
- DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
- DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
- DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
- DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-
- /* AHB <-> IP-Bus Interface */
- DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
- DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-#endif
-
#if defined(CONFIG_MX27)
DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
offsetof(struct system_control_regs, fmcr));
#endif
-#if defined(CONFIG_MX35)
- /* Round up to make sure size gives nice stack alignment */
- DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
- DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
- DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
- DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
- DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
- DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
- DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
- DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
- DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
- DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
- DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
- DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
- DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
- DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
- DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
-
- /* Multi-Layer AHB Crossbar Switch */
- DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
- DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
- DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
- DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
- DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
- DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
- DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
- DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
- DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
- DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
- DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
- DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
- DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
- DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
- DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
- DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
-
- /* AHB <-> IP-Bus Interface */
- DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
- DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
- DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
- DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
- DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
- DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
- DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
- DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
- DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
- DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
- DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
-#endif
-
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Macros for asm code.
+ *
+ * Copyright (c) 2019, Arm Limited.
+ */
+
+#ifndef _ASMDEFS_H
+#define _ASMDEFS_H
+
+#if defined(__aarch64__)
+
+/* Branch Target Identitication support. */
+#define BTI_C hint 34
+#define BTI_J hint 36
+/* Return address signing support (pac-ret). */
+#define PACIASP hint 25; .cfi_window_save
+#define AUTIASP hint 29; .cfi_window_save
+
+/* GNU_PROPERTY_AARCH64_* macros from elf.h. */
+#define FEATURE_1_AND 0xc0000000
+#define FEATURE_1_BTI 1
+#define FEATURE_1_PAC 2
+
+/* Add a NT_GNU_PROPERTY_TYPE_0 note. */
+#define GNU_PROPERTY(type, value) \
+ .section .note.gnu.property, "a"; \
+ .p2align 3; \
+ .word 4; \
+ .word 16; \
+ .word 5; \
+ .asciz "GNU"; \
+ .word type; \
+ .word 4; \
+ .word value; \
+ .word 0; \
+ .text
+
+/* If set then the GNU Property Note section will be added to
+ mark objects to support BTI and PAC-RET. */
+#ifndef WANT_GNU_PROPERTY
+#define WANT_GNU_PROPERTY 1
+#endif
+
+#if WANT_GNU_PROPERTY
+/* Add property note with supported features to all asm files. */
+GNU_PROPERTY (FEATURE_1_AND, FEATURE_1_BTI|FEATURE_1_PAC)
+#endif
+
+#define ENTRY_ALIGN(name, alignment) \
+ .global name; \
+ .type name,%function; \
+ .align alignment; \
+ name: \
+ .cfi_startproc; \
+ BTI_C;
+
+#else
+
+#define END_FILE
+
+#define ENTRY_ALIGN(name, alignment) \
+ .global name; \
+ .type name,%function; \
+ .align alignment; \
+ name: \
+ .cfi_startproc;
+
+#endif
+
+#define ENTRY(name) ENTRY_ALIGN(name, 6)
+
+#define ENTRY_ALIAS(name) \
+ .global name; \
+ .type name,%function; \
+ name:
+
+#define END(name) \
+ .cfi_endproc; \
+ .size name, .-name;
+
+#define L(l) .L ## l
+
+#ifdef __ILP32__
+ /* Sanitize padding bits of pointer arguments as per aapcs64 */
+#define PTR_ARG(n) mov w##n, w##n
+#else
+#define PTR_ARG(n)
+#endif
+
+#ifdef __ILP32__
+ /* Sanitize padding bits of size arguments as per aapcs64 */
+#define SIZE_ARG(n) mov w##n, w##n
+#else
+#define SIZE_ARG(n)
+#endif
+
+#endif
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
-#include <lmb.h>
#include <log.h>
#include <asm/global_data.h>
#include <dm/root.h>
static struct tag *params;
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- ulong sp, bank_end;
- int bank;
-
- /*
- * Booting a (Linux) kernel image
- *
- * Allocate space for command line and board info - the
- * address should be as high as possible within the reach of
- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
- * memory, which means far enough below the current stack
- * pointer.
- */
- sp = get_sp();
- debug("## Current stack ends at 0x%08lx ", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= 4096;
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (!gd->bd->bi_dram[bank].size ||
- sp < gd->bd->bi_dram[bank].start)
- continue;
- /* Watch out for RAM at end of address space! */
- bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size - 1;
- if (sp > bank_end)
- continue;
- if (bank_end > gd->ram_top)
- bank_end = gd->ram_top - 1;
-
- lmb_reserve(lmb, sp, bank_end - sp + 1);
- break;
- }
-}
-
__weak void board_quiesce_devices(void)
{
}
{
char *commandline = env_get("bootargs");
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
announce_and_cleanup(fake);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
r2 = (unsigned long)images->ft_addr;
else
r2 = gd->bd->bi_boot_params;
/*************************************************************************
*
* void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
- * CCI_MN_DVM_DOMAIN_CTL_SET);
+ * CCI_MN_DVM_DOMAIN_CTL_SET);
*
* Add fully-coherent masters to DVM domain
*
ret
ENDPROC(ccn504_set_aux)
-
ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */
adr lr, here
+#if defined(CONFIG_POSITION_INDEPENDENT)
+ adr r0, _main
+ ldr r1, _start_ofs
+ add r0, r1
+ ldr r1, =CONFIG_SYS_TEXT_BASE
+ sub r1, r0
+ add lr, r1
+#endif
ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */
add lr, lr, r0
#if defined(CONFIG_CPU_V7M)
#endif
ENDPROC(_main)
+
+_start_ofs:
+ .word _start - _main
* This is meant to be used by do_div() from include/asm/div64.h only.
*
* Input parameters:
- * xh-xl = dividend (clobbered)
- * r4 = divisor (preserved)
+ * xh-xl = dividend (clobbered)
+ * r4 = divisor (preserved)
*
* Output values:
- * yh-yl = result
- * xh = remainder
+ * yh-yl = result
+ * xh = remainder
*
* Clobbered regs: xl, ip
*/
#endif
@ The division loop for needed upper bit positions.
- @ Break out early if dividend reaches 0.
+ @ Break out early if dividend reaches 0.
2: cmp xh, yl
orrcs yh, yh, ip
subscs xh, xh, yl
mov \divisor, \divisor, lsl \result
mov \curbit, \curbit, lsl \result
mov \result, #0
-
+
#else
@ Initially shift the divisor left 3 bits if possible,
@ Unless the divisor is very big, shift it up in multiples of
@ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
+ @ division loop. Continue shifting until the divisor is
@ larger than the dividend.
1: cmp \divisor, #0x10000000
cmplo \divisor, \dividend
@ Unless the divisor is very big, shift it up in multiples of
@ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
+ @ division loop. Continue shifting until the divisor is
@ larger than the dividend.
1: cmp \divisor, #0x10000000
cmplo \divisor, \dividend
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * memcpy - copy memory area
+ *
+ * Copyright (c) 2012-2020, Arm Limited.
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses.
+ *
+ */
+
+#include "asmdefs.h"
+
+#define dstin x0
+#define src x1
+#define count x2
+#define dst x3
+#define srcend x4
+#define dstend x5
+#define A_l x6
+#define A_lw w6
+#define A_h x7
+#define B_l x8
+#define B_lw w8
+#define B_h x9
+#define C_l x10
+#define C_lw w10
+#define C_h x11
+#define D_l x12
+#define D_h x13
+#define E_l x14
+#define E_h x15
+#define F_l x16
+#define F_h x17
+#define G_l count
+#define G_h dst
+#define H_l src
+#define H_h srcend
+#define tmp1 x14
+
+/* This implementation handles overlaps and supports both memcpy and memmove
+ from a single entry point. It uses unaligned accesses and branchless
+ sequences to keep the code small, simple and improve performance.
+
+ Copies are split into 3 main cases: small copies of up to 32 bytes, medium
+ copies of up to 128 bytes, and large copies. The overhead of the overlap
+ check is negligible since it is only required for large copies.
+
+ Large copies use a software pipelined loop processing 64 bytes per iteration.
+ The destination pointer is 16-byte aligned to minimize unaligned accesses.
+ The loop tail is handled by always copying 64 bytes from the end.
+*/
+
+ENTRY_ALIAS (memmove)
+ENTRY (memcpy)
+ PTR_ARG (0)
+ PTR_ARG (1)
+ SIZE_ARG (2)
+ add srcend, src, count
+ add dstend, dstin, count
+ cmp count, 128
+ b.hi L(copy_long)
+ cmp count, 32
+ b.hi L(copy32_128)
+
+ /* Small copies: 0..32 bytes. */
+ cmp count, 16
+ b.lo L(copy16)
+ ldp A_l, A_h, [src]
+ ldp D_l, D_h, [srcend, -16]
+ stp A_l, A_h, [dstin]
+ stp D_l, D_h, [dstend, -16]
+ ret
+
+ /* Copy 8-15 bytes. */
+L(copy16):
+ tbz count, 3, L(copy8)
+ ldr A_l, [src]
+ ldr A_h, [srcend, -8]
+ str A_l, [dstin]
+ str A_h, [dstend, -8]
+ ret
+
+ .p2align 3
+ /* Copy 4-7 bytes. */
+L(copy8):
+ tbz count, 2, L(copy4)
+ ldr A_lw, [src]
+ ldr B_lw, [srcend, -4]
+ str A_lw, [dstin]
+ str B_lw, [dstend, -4]
+ ret
+
+ /* Copy 0..3 bytes using a branchless sequence. */
+L(copy4):
+ cbz count, L(copy0)
+ lsr tmp1, count, 1
+ ldrb A_lw, [src]
+ ldrb C_lw, [srcend, -1]
+ ldrb B_lw, [src, tmp1]
+ strb A_lw, [dstin]
+ strb B_lw, [dstin, tmp1]
+ strb C_lw, [dstend, -1]
+L(copy0):
+ ret
+
+ .p2align 4
+ /* Medium copies: 33..128 bytes. */
+L(copy32_128):
+ ldp A_l, A_h, [src]
+ ldp B_l, B_h, [src, 16]
+ ldp C_l, C_h, [srcend, -32]
+ ldp D_l, D_h, [srcend, -16]
+ cmp count, 64
+ b.hi L(copy128)
+ stp A_l, A_h, [dstin]
+ stp B_l, B_h, [dstin, 16]
+ stp C_l, C_h, [dstend, -32]
+ stp D_l, D_h, [dstend, -16]
+ ret
+
+ .p2align 4
+ /* Copy 65..128 bytes. */
+L(copy128):
+ ldp E_l, E_h, [src, 32]
+ ldp F_l, F_h, [src, 48]
+ cmp count, 96
+ b.ls L(copy96)
+ ldp G_l, G_h, [srcend, -64]
+ ldp H_l, H_h, [srcend, -48]
+ stp G_l, G_h, [dstend, -64]
+ stp H_l, H_h, [dstend, -48]
+L(copy96):
+ stp A_l, A_h, [dstin]
+ stp B_l, B_h, [dstin, 16]
+ stp E_l, E_h, [dstin, 32]
+ stp F_l, F_h, [dstin, 48]
+ stp C_l, C_h, [dstend, -32]
+ stp D_l, D_h, [dstend, -16]
+ ret
+
+ .p2align 4
+ /* Copy more than 128 bytes. */
+L(copy_long):
+ /* Use backwards copy if there is an overlap. */
+ sub tmp1, dstin, src
+ cbz tmp1, L(copy0)
+ cmp tmp1, count
+ b.lo L(copy_long_backwards)
+
+ /* Copy 16 bytes and then align dst to 16-byte alignment. */
+
+ ldp D_l, D_h, [src]
+ and tmp1, dstin, 15
+ bic dst, dstin, 15
+ sub src, src, tmp1
+ add count, count, tmp1 /* Count is now 16 too large. */
+ ldp A_l, A_h, [src, 16]
+ stp D_l, D_h, [dstin]
+ ldp B_l, B_h, [src, 32]
+ ldp C_l, C_h, [src, 48]
+ ldp D_l, D_h, [src, 64]!
+ subs count, count, 128 + 16 /* Test and readjust count. */
+ b.ls L(copy64_from_end)
+
+L(loop64):
+ stp A_l, A_h, [dst, 16]
+ ldp A_l, A_h, [src, 16]
+ stp B_l, B_h, [dst, 32]
+ ldp B_l, B_h, [src, 32]
+ stp C_l, C_h, [dst, 48]
+ ldp C_l, C_h, [src, 48]
+ stp D_l, D_h, [dst, 64]!
+ ldp D_l, D_h, [src, 64]!
+ subs count, count, 64
+ b.hi L(loop64)
+
+ /* Write the last iteration and copy 64 bytes from the end. */
+L(copy64_from_end):
+ ldp E_l, E_h, [srcend, -64]
+ stp A_l, A_h, [dst, 16]
+ ldp A_l, A_h, [srcend, -48]
+ stp B_l, B_h, [dst, 32]
+ ldp B_l, B_h, [srcend, -32]
+ stp C_l, C_h, [dst, 48]
+ ldp C_l, C_h, [srcend, -16]
+ stp D_l, D_h, [dst, 64]
+ stp E_l, E_h, [dstend, -64]
+ stp A_l, A_h, [dstend, -48]
+ stp B_l, B_h, [dstend, -32]
+ stp C_l, C_h, [dstend, -16]
+ ret
+
+ .p2align 4
+
+ /* Large backwards copy for overlapping copies.
+ Copy 16 bytes and then align dst to 16-byte alignment. */
+L(copy_long_backwards):
+ ldp D_l, D_h, [srcend, -16]
+ and tmp1, dstend, 15
+ sub srcend, srcend, tmp1
+ sub count, count, tmp1
+ ldp A_l, A_h, [srcend, -16]
+ stp D_l, D_h, [dstend, -16]
+ ldp B_l, B_h, [srcend, -32]
+ ldp C_l, C_h, [srcend, -48]
+ ldp D_l, D_h, [srcend, -64]!
+ sub dstend, dstend, tmp1
+ subs count, count, 128
+ b.ls L(copy64_from_start)
+
+L(loop64_backwards):
+ stp A_l, A_h, [dstend, -16]
+ ldp A_l, A_h, [srcend, -16]
+ stp B_l, B_h, [dstend, -32]
+ ldp B_l, B_h, [srcend, -32]
+ stp C_l, C_h, [dstend, -48]
+ ldp C_l, C_h, [srcend, -48]
+ stp D_l, D_h, [dstend, -64]!
+ ldp D_l, D_h, [srcend, -64]!
+ subs count, count, 64
+ b.hi L(loop64_backwards)
+
+ /* Write the last iteration and copy 64 bytes from the start. */
+L(copy64_from_start):
+ ldp G_l, G_h, [src, 48]
+ stp A_l, A_h, [dstend, -16]
+ ldp A_l, A_h, [src, 32]
+ stp B_l, B_h, [dstend, -32]
+ ldp B_l, B_h, [src, 16]
+ stp C_l, C_h, [dstend, -48]
+ ldp C_l, C_h, [src]
+ stp D_l, D_h, [dstend, -64]
+ stp G_l, G_h, [dstin, 48]
+ stp A_l, A_h, [dstin, 32]
+ stp B_l, B_h, [dstin, 16]
+ stp C_l, C_h, [dstin]
+ ret
+
+END (memcpy)
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * memset - fill memory with a constant byte
+ *
+ * Copyright (c) 2012-2021, Arm Limited.
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
+ *
+ */
+
+#include <asm/macro.h>
+#include "asmdefs.h"
+
+#define dstin x0
+#define val x1
+#define valw w1
+#define count x2
+#define dst x3
+#define dstend x4
+#define zva_val x5
+
+ENTRY (memset)
+ PTR_ARG (0)
+ SIZE_ARG (2)
+
+ /*
+ * The optimized memset uses the dc opcode, which causes problems
+ * when the cache is disabled. Let's check if the cache is disabled
+ * and use a very simple memset implementation in this case. Otherwise
+ * jump to the optimized version.
+ */
+ switch_el x6, 3f, 2f, 1f
+3: mrs x6, sctlr_el3
+ b 0f
+2: mrs x6, sctlr_el2
+ b 0f
+1: mrs x6, sctlr_el1
+0:
+ tst x6, #CR_C
+ bne 9f
+
+ /*
+ * A very "simple" memset implementation without the use of the
+ * dc opcode. Can be run with caches disabled.
+ */
+ mov x3, #0x0
+ cmp count, x3 /* check for zero length */
+ beq 8f
+4: strb valw, [dstin, x3]
+ add x3, x3, #0x1
+ cmp count, x3
+ bne 4b
+8: ret
+9:
+
+ /* Here the optimized memset version starts */
+ dup v0.16B, valw
+ add dstend, dstin, count
+
+ cmp count, 96
+ b.hi L(set_long)
+ cmp count, 16
+ b.hs L(set_medium)
+ mov val, v0.D[0]
+
+ /* Set 0..15 bytes. */
+ tbz count, 3, 1f
+ str val, [dstin]
+ str val, [dstend, -8]
+ ret
+ .p2align 4
+1: tbz count, 2, 2f
+ str valw, [dstin]
+ str valw, [dstend, -4]
+ ret
+2: cbz count, 3f
+ strb valw, [dstin]
+ tbz count, 1, 3f
+ strh valw, [dstend, -2]
+3: ret
+
+ /* Set 17..96 bytes. */
+L(set_medium):
+ str q0, [dstin]
+ tbnz count, 6, L(set96)
+ str q0, [dstend, -16]
+ tbz count, 5, 1f
+ str q0, [dstin, 16]
+ str q0, [dstend, -32]
+1: ret
+
+ .p2align 4
+ /* Set 64..96 bytes. Write 64 bytes from the start and
+ 32 bytes from the end. */
+L(set96):
+ str q0, [dstin, 16]
+ stp q0, q0, [dstin, 32]
+ stp q0, q0, [dstend, -32]
+ ret
+
+ .p2align 4
+L(set_long):
+ and valw, valw, 255
+ bic dst, dstin, 15
+ str q0, [dstin]
+ cmp count, 160
+ ccmp valw, 0, 0, hs
+ b.ne L(no_zva)
+
+#ifndef SKIP_ZVA_CHECK
+ mrs zva_val, dczid_el0
+ and zva_val, zva_val, 31
+ cmp zva_val, 4 /* ZVA size is 64 bytes. */
+ b.ne L(no_zva)
+#endif
+ str q0, [dst, 16]
+ stp q0, q0, [dst, 32]
+ bic dst, dst, 63
+ sub count, dstend, dst /* Count is now 64 too large. */
+ sub count, count, 128 /* Adjust count and bias for loop. */
+
+ .p2align 4
+L(zva_loop):
+ add dst, dst, 64
+ dc zva, dst
+ subs count, count, 64
+ b.hi L(zva_loop)
+ stp q0, q0, [dstend, -64]
+ stp q0, q0, [dstend, -32]
+ ret
+
+L(no_zva):
+ sub count, dstend, dst /* Count is 16 too large. */
+ sub dst, dst, 16 /* Dst is biased by -32. */
+ sub count, count, 64 + 16 /* Adjust count and bias for loop. */
+L(no_zva_loop):
+ stp q0, q0, [dst, 32]
+ stp q0, q0, [dst, 64]!
+ subs count, count, 64
+ b.hi L(no_zva_loop)
+ stp q0, q0, [dstend, -64]
+ stp q0, q0, [dstend, -32]
+ ret
+
+END (memset)
*/
ENTRY(relocate_code)
- ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
- subs r4, r0, r1 /* r4 <- relocation offset */
- beq relocate_done /* skip relocation */
- ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */
-
+ adr r3, relocate_code
+ ldr r1, _image_copy_start_ofs
+ add r1, r3 /* r1 <- Run &__image_copy_start */
+ subs r4, r0, r1 /* r4 <- Run to copy offset */
+ beq relocate_done /* skip relocation */
+ ldr r1, _image_copy_start_ofs
+ add r1, r3 /* r1 <- Run &__image_copy_start */
+ ldr r2, _image_copy_end_ofs
+ add r2, r3 /* r2 <- Run &__image_copy_end */
copy_loop:
- ldmia r1!, {r10-r11} /* copy from source address [r1] */
- stmia r0!, {r10-r11} /* copy to target address [r0] */
- cmp r1, r2 /* until source end address [r2] */
+ ldmia r1!, {r10-r11} /* copy from source address [r1] */
+ stmia r0!, {r10-r11} /* copy to target address [r0] */
+ cmp r1, r2 /* until source end address [r2] */
blo copy_loop
/*
* fix .rel.dyn relocations
*/
- ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */
- ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */
+ ldr r1, _rel_dyn_start_ofs
+ add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */
+ ldr r1, _rel_dyn_end_ofs
+ add r3, r1, r3 /* r3 <- Run &__rel_dyn_end */
fixloop:
ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */
and r1, r1, #0xff
#endif
ENDPROC(relocate_code)
+
+_image_copy_start_ofs:
+ .word __image_copy_start - relocate_code
+_image_copy_end_ofs:
+ .word __image_copy_end - relocate_code
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - relocate_code
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - relocate_code
*/
#include <common.h>
#include <init.h>
+#include <lmb.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 16384);
+}
config ATMEL_SFR
bool
- default n
config SYS_SOC
default "at91"
#include <config.h>
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#include <asm/arch/hardware.h>
#include <asm/arch/at91_mc.h>
.word CONFIG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o
obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o
obj-y += cpu.o
-obj-y += reset.o
+ifndef CONFIG_$(SPL_TPL_)SYSRESET
+obj-y += reset.o
+endif
ifneq ($(CONFIG_ATMEL_PIT_TIMER),y)
ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y)
# old non-DM timer driver
return "SAMA5D28-CU";
case ARCH_EXID_SAMA5D28CN:
return "SAMA5D28-CN";
+ case ARCH_EXID_SAMA5D29CN:
+ return "SAMA5D29-CN";
}
}
else
writel(0, &sfr->ddrcfg);
}
-
#ifndef __ASSEMBLY__
typedef struct at91_ebi {
- u32 csa; /* 0x00 Chip Select Assignment Register */
+ u32 csa; /* 0x00 Chip Select Assignment Register */
u32 cfgr; /* 0x04 Configuration Register */
u32 reserved[2];
} at91_ebi_t;
#define AT91_EBI_CSA_CS4A 0x0010
typedef struct at91_sdramc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
- u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
- u32 cr; /* 0x08 SDRAMC Configuration Register */
- u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
- u32 lpr; /* 0x10 SDRAMC Low Power Register */
- u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
- u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
- u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
- u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
+ u32 cr; /* 0x08 SDRAMC Configuration Register */
+ u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
+ u32 lpr; /* 0x10 SDRAMC Low Power Register */
+ u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
+ u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
+ u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
+ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
u32 reserved[3];
} at91_sdramc_t;
typedef struct at91_smc {
- u32 csr[8]; /* 0x00 SDRAMC Mode Register */
+ u32 csr[8]; /* 0x00 SDRAMC Mode Register */
} at91_smc_t;
#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
typedef struct at91_bfc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 mr; /* 0x00 SDRAMC Mode Register */
} at91_bfc_t;
typedef struct at91_mc {
#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
#define AT91_ST_WDMR_RSTEN 0x00010000
-#define AT91_ST_WDMR_EXTEN 0x00020000
+#define AT91_ST_WDMR_EXTEN 0x00020000
#endif
#define ARCH_EXID_SAMA5D27CN 0x00000021
#define ARCH_EXID_SAMA5D28CU 0x00000010
#define ARCH_EXID_SAMA5D28CN 0x00000020
+#define ARCH_EXID_SAMA5D29CN 0x00000023
#define ARCH_ID_SAMA5D2_SIP 0x8a5c08c2
#define ARCH_EXID_SAMA5D225C_D1M 0x00000053
at91_periph_clk_enable(ATMEL_ID_PIOC);
#endif
-#if defined(CONFIG_SPL_SERIAL_SUPPORT)
+#if defined(CONFIG_SPL_SERIAL)
/* init console */
at91_seriald_hw_init();
preloader_console_init();
struct da8xx_usb_regs {
dv_reg revision;
dv_reg control;
- dv_reg status;
- dv_reg emulation;
- dv_reg mode;
- dv_reg autoreq;
- dv_reg srpfixtime;
- dv_reg teardown;
- dv_reg intsrc;
- dv_reg intsrc_set;
- dv_reg intsrc_clr;
- dv_reg intmsk;
- dv_reg intmsk_set;
- dv_reg intmsk_clr;
- dv_reg intsrcmsk;
- dv_reg eoi;
- dv_reg intvector;
- dv_reg grndis_size[4];
+ dv_reg status;
+ dv_reg emulation;
+ dv_reg mode;
+ dv_reg autoreq;
+ dv_reg srpfixtime;
+ dv_reg teardown;
+ dv_reg intsrc;
+ dv_reg intsrc_set;
+ dv_reg intsrc_clr;
+ dv_reg intmsk;
+ dv_reg intmsk_set;
+ dv_reg intmsk_clr;
+ dv_reg intsrcmsk;
+ dv_reg eoi;
+ dv_reg intvector;
+ dv_reg grndis_size[4];
};
#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
#define CFGCHIP2_OTGMODE (3 << 13)
#define CFGCHIP2_NO_OVERRIDE (0 << 13)
#define CFGCHIP2_FORCE_HOST (1 << 13)
-#define CFGCHIP2_FORCE_DEVICE (2 << 13)
+#define CFGCHIP2_FORCE_DEVICE (2 << 13)
#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
#define CFGCHIP2_PHYPWRDN (1 << 10)
#define CFGCHIP2_OTGPWRDN (1 << 9)
-#define CFGCHIP2_DATPOL (1 << 8)
+#define CFGCHIP2_DATPOL (1 << 8)
#define CFGCHIP2_USB1SUSPENDM (1 << 7)
#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
/* pin table definition */
struct pinmux_resource {
const struct pinmux_config *pins;
- const int n_pins;
+ const int n_pins;
};
#define PINMUX_ITEM(item) { \
const int lpsc_no;
};
-int dvevm_read_mac_address(uint8_t *buf);
void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
#ifdef CONFIG_DRIVER_TI_EMAC
/*
- * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
- * Returns 1 if found, 0 otherwise.
- */
-int dvevm_read_mac_address(uint8_t *buf)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- /* Read MAC address. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
- goto i2cerr;
-
- /* Check that MAC address is valid. */
- if (!is_valid_ethaddr(buf))
- goto err;
-
- return 1; /* Found */
-
-i2cerr:
- printf("Read from EEPROM @ 0x%02x failed\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
-err:
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
-
- return 0;
-}
-
-/*
* Set the mii mode as MII or RMII
*/
void davinci_emac_mii_mode_sel(int mode_sel)
return BOOT_DEVICE_NAND;
#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
case DAVINCI_SD_OR_MMC_BOOT:
case DAVINCI_MMC_ONLY_BOOT:
return BOOT_DEVICE_MMC1;
choice
prompt "EXYNOS7 board select"
-config TARGET_ESPRESSO7420
+config TARGET_ESPRESSO7420
bool "ESPRESSO7420 board"
select ARM64
select ARMV8_MULTIENTRY
if (actions & DO_CLOCKS) {
system_clock_init();
#ifdef CONFIG_DEBUG_UART
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
!defined(CONFIG_SPL_BUILD)
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
debug_uart_init();
+config MACH_IMX
+ bool
+
config HAS_CAAM
bool
config IMX_CONFIG
- string
+ string "DCD script to use"
+ depends on MACH_IMX
+ default "arch/arm/mach-imx/spl_sd.cfg"
config ROM_UNIFIED_SECTIONS
bool
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7))
-obj-y += cpu.o
+obj-y += cpu.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
-obj-y += cache.o init.o
+obj-y += cache.o init.o
obj-$(CONFIG_FEC_MXC) += mac.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
ifneq ($(CONFIG_SPL_BUILD),y)
#include <jffs2/jffs2.h>
#include <linux/bch.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/imx-nandbcb.h>
return (image_get_image_size((image_header_t *)img_addr)
+ 0x1000 - 1) & ~(0x1000 - 1);
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
#endif
return -ENOMEM;
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
if (dev_type == MMC_DEV) {
unsigned long count = 0;
struct mmc *mmc = (struct mmc *)dev;
}
#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
{
return boot_dev;
}
-#ifdef CONFIG_SERIAL_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define FUSE_UNIQUE_ID_WORD0 16
#define FUSE_UNIQUE_ID_WORD1 17
void get_board_serial(struct tag_serialnr *serialnr)
serialnr->low = val1;
serialnr->high = val2;
}
-#endif /*CONFIG_SERIAL_TAG*/
+#endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/
#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
return 0;
}
-#ifdef CONFIG_SERIAL_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
void get_board_serial(struct tag_serialnr *serialnr)
{
u32 uid[4];
return 0;
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void board_lmb_reserve(struct lmb *lmb)
-{
- ulong sp, bank_end;
- int bank;
-
- sp = get_sp();
- debug("## Current stack ends at 0x%08lx ", sp);
-
- /* adjust sp by 16K to be safe */
- sp -= 4096 << 2;
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (sp < gd->bd->bi_dram[bank].start)
- continue;
- bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size;
- if (sp >= bank_end)
- continue;
- lmb_reserve(lmb, sp, bank_end - sp);
- break;
- }
-}
+++ /dev/null
-if ARCH_MX25
-
-config MX25
- bool
- default y
- select SYS_FSL_ERRATUM_ESDHC_A001
-choice
- prompt "MX25 board select"
- optional
-
-config TARGET_ZMX25
- bool "Support zmx25"
- select BOARD_LATE_INIT
- select CPU_ARM926EJS
-
-endchoice
-
-config SYS_SOC
- default "mx25"
-
-source "board/syteco/zmx25/Kconfig"
-
-endif
config MX6_DDRCAL
bool "Include dynamic DDR calibration routines"
depends on SPL
- default n
help
Say "Y" if your board uses dynamic (per-boot) DDR calibration.
If unsure, say N.
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBDISK_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
- select SPL_MMC_SUPPORT if SPL
+ select SPL_MMC if SPL
select SPL_OF_CONTROL if SPL
select SPL_OF_LIBFDT if SPL
select SPL_PINCTRL if SPL
select SPL_SEPARATE_BSS if SPL
- select SPL_SERIAL_SUPPORT if SPL
+ select SPL_SERIAL if SPL
select SPL_USB_GADGET if SPL
select SPL_USB_HOST if SPL
select SPL_USB_SDP_SUPPORT if SPL
depends on SPL
default 0x00912000
+config OPTEE_TZDRAM_SIZE
+ hex "Amount of Trust-Zone RAM for the OPTEE image"
+ default 0x0000000
+ depends on OPTEE_LIB
+ help
+ The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
+ runtime.
+
choice
prompt "MX7 board select"
optional
select DM
select DM_SERIAL
select DM_THERMAL
+ select MX7D
imply CMD_DM
endchoice
#include <asm/arch/imx-rdc.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
+#include <asm/bootm.h>
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
};
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* enable all periherial can be accessed in nosec mode */
static void init_csu(void)
{
int arch_misc_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ struct tag_serialnr serialnr;
+ char serial_string[0x20];
+
if (is_mx7d())
env_set("soc", "imx7d");
else
env_set("soc", "imx7s");
+
+ /* Set serial# standard environment variable based on OTP settings */
+ get_board_serial(&serialnr);
+ snprintf(serial_string, sizeof(serial_string), "0x%08x%08x",
+ serialnr.low, serialnr.high);
+ env_set("serial#", serial_string);
#endif
#ifdef CONFIG_FSL_CAAM
}
#endif
-#ifdef CONFIG_SERIAL_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/*
* OCOTP_TESTER
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
#endif
#endif
}
-
prompt "MX28 board select"
optional
-config TARGET_BG0900
- bool "Support bg0900"
-
config TARGET_MX28EVK
bool "Support mx28evk"
select BOARD_EARLY_INIT_F
source "board/freescale/mx28evk/Kconfig"
source "board/liebherr/xea/Kconfig"
-source "board/ppcag/bg0900/Kconfig"
endif
}
#endif
-#if defined(CONFIG_SPL_MMC_SUPPORT)
+#if defined(CONFIG_SPL_MMC)
/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
u32 spl_mmc_boot_mode(const u32 boot_device)
{
return usec;
}
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
+source "board/siemens/iot2050/Kconfig"
endif
/* Load combined System Controller firmware and config data image */
switch (bootdev.boot_device) {
-#if CONFIG_IS_ENABLED(MMC_SUPPORT)
+#if CONFIG_IS_ENABLED(MMC)
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
+ select SOC_K2HK
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
+ select SOC_K2E
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
+ select SOC_K2L
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
config TARGET_K2G_EVM
bool "TI Keystone 2 Galileo EVM"
select BOARD_LATE_INIT
+ select SOC_K2G
select SPL_BOARD_INIT if SPL
select TI_I2C_BOARD_DETECT
select CMD_DDR3
endchoice
+config SOC_K2E
+ bool
+
+config SOC_K2G
+ bool
+
+config SOC_K2HK
+ bool
+
+config SOC_K2L
+ bool
+
config SYS_SOC
default "keystone"
#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
-#define KS2_UART0_BASE 0x02530c00
-#define KS2_UART1_BASE 0x02531000
+#define KS2_UART0_BASE 0x02530c00
+#define KS2_UART1_BASE 0x02531000
/* Boot Config */
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#endif
/* AEMIF */
-#define KS2_AEMIF_CNTRL_BASE 0x21000a00
+#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
#endif /* CONFIG_IDE */
-/*
- * I2C related stuff
- */
-#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
-#endif
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
/* Use common timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
config MT8512
bool "MediaTek MT8512 SoC"
- default n
choice
prompt "MediaTek board select"
endchoice
-source "board/mediatek/mt7622/Kconfig"
-source "board/mediatek/mt7623/Kconfig"
-source "board/mediatek/mt7629/Kconfig"
-source "board/mediatek/mt8183/Kconfig"
-source "board/mediatek/mt8512/Kconfig"
-source "board/mediatek/mt8516/Kconfig"
-source "board/mediatek/mt8518/Kconfig"
+config SYS_BOARD
+ string "Board name"
+ default "mt7622" if TARGET_MT7622
+ default "mt7623" if TARGET_MT7623
+ default "mt7629" if TARGET_MT7629
+ default "mt8183" if TARGET_MT8183
+ default "mt8512" if TARGET_MT8512
+ default "mt8516" if TARGET_MT8516
+ default "mt8518" if TARGET_MT8518
+ default ""
+ help
+ This option contains information about board name.
+ Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
+ be used.
+
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "mt7622" if TARGET_MT7622
+ default "mt7623" if TARGET_MT7623
+ default "mt7629" if TARGET_MT7629
+ default "mt8183" if TARGET_MT8183
+ default "mt8512" if TARGET_MT8512
+ default "mt8516" if TARGET_MT8516
+ default "mt8518" if TARGET_MT8518
+ default ""
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "lk=1" if TARGET_MT7623
endif
u32 spl_boot_device(void)
{
-#if defined(CONFIG_SPL_SPI_SUPPORT)
+#if defined(CONFIG_SPL_SPI)
return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_SPL_MMC_SUPPORT)
+#elif defined(CONFIG_SPL_MMC)
return BOOT_DEVICE_MMC1;
#elif defined(CONFIG_SPL_NAND_SUPPORT)
return BOOT_DEVICE_NAND;
{ "A113X", 0x25, 0x37, 0xff },
{ "A113D", 0x25, 0x22, 0xff },
{ "S905D2", 0x28, 0x10, 0xf0 },
+ { "S905Y2", 0x28, 0x30, 0xf0 },
{ "S905X2", 0x28, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S922X", 0x29, 0x40, 0xf0 },
config HAVE_MVEBU_EFUSE
bool
- default n
config ARMADA_32BIT
bool
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
+ select SPL_SKIP_LOWLEVEL_INIT
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
select TRANSLATION_OFFSET
endchoice
+choice
+ prompt "DDR bus width"
+ default DDR_64BIT
+ depends on ARMADA_XP
+
+config DDR_64BIT
+ bool "64bit bus width"
+
+config DDR_32BIT
+ bool "32bit bus width"
+
+endchoice
+
+config DDR_LOG_LEVEL
+ int "DDR training code log level"
+ depends on ARMADA_XP
+ default 0
+ range 0 3
+ help
+ Amount of information provided on error while running the DDR
+ training code. At level 0, provides an error code in a case of
+ failure, RL, WL errors and other algorithm failure. At level 1,
+ provides the D-Unit setup (SPD/Static configuration). At level 2,
+ provides the windows margin as a results of DQS centeralization.
+ At level 3, rovides the windows margin of each DQ as a results of
+ DQS centeralization.
+
config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
default "helios4" if TARGET_HELIOS4
imply SPL_DM_SPI
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_LOAD
- imply SPL_SPI_SUPPORT
+ imply SPL_SPI
select SPL_BOOTROM_SUPPORT
config MVEBU_SPL_BOOT_DEVICE_MMC
imply SPL_DM_MMC
imply SPL_GPIO
imply SPL_LIBDISK_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
select SPL_BOOTROM_SUPPORT
config MVEBU_SPL_BOOT_DEVICE_SATA
bool "SATA"
- imply SPL_SATA_SUPPORT
+ imply SPL_SATA
imply SPL_LIBDISK_SUPPORT
select SPL_BOOTROM_SUPPORT
config MVEBU_EFUSE
bool "Enable eFuse support"
- default n
depends on HAVE_MVEBU_EFUSE
help
Enable support for reading and writing eFuses on mvebu SoCs.
config MVEBU_EFUSE_FAKE
bool "Fake eFuse access (dry run)"
- default n
depends on MVEBU_EFUSE
help
This enables a "dry run" mode where eFuses are not really programmed.
#define CONFIG_SYS_L2_PL310
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
-
/*
* By default the generated mvebu kwbimage.cfg is used
* If for some board, different configuration file need to be used,
#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_I2C_MVTWSI
#endif
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
#endif
/* Use common timer */
int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
{
- u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
- temp_reg, addr, dev_id, ctrl_mode;
enum serdes_type serdes_type;
- u32 idx;
+ u32 idx, tmp;
DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- /* configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
- tmp &= ~(0xf << 20);
- tmp |= (0x4 << 20);
- reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
- }
-
- tmp = reg_read(SOC_CTRL_REG);
+ tmp = reg_read(SOC_CONTROL_REG1);
tmp &= ~0x03;
for (idx = 0; idx < count; idx++) {
}
}
- reg_write(SOC_CTRL_REG, tmp);
-
- /* Support gen1/gen2 */
- DEBUG_INIT_FULL_S("Support gen1/gen2\n");
+ reg_write(SOC_CONTROL_REG1, tmp);
board_pex_config();
- next_busno = 0;
- mdelay(150);
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- DEBUG_INIT_FULL_S(" serdes_type=0x");
- DEBUG_INIT_FULL_D(serdes_type, 8);
- DEBUG_INIT_FULL_S("\n");
- DEBUG_INIT_FULL_S(" idx=0x");
- DEBUG_INIT_FULL_D(idx, 8);
- DEBUG_INIT_FULL_S("\n");
-
- /* Configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
-
- first_busno = next_busno;
- if ((tmp & 0x7f) != 0x7e) {
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S(": detected no link\n");
- continue;
- }
-
- next_busno++;
- temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_LINK_CAPABILITY_REG)));
- temp_pex_reg &= 0xf;
- if (temp_pex_reg != 0x2)
- continue;
-
- temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
- pex_idx,
- PEX_LINK_CTRL_STAT_REG)) &
- 0xf0000) >> 16;
-
- /* Check if the link established is GEN1 */
- DEBUG_INIT_FULL_S
- ("Checking if the link established is gen1\n");
- if (temp_reg != 0x1)
- continue;
-
- pex_local_bus_num_set(pex_idx, first_busno);
- pex_local_dev_num_set(pex_idx, 1);
- DEBUG_INIT_FULL_S("PCIe, Idx ");
- DEBUG_INIT_FULL_D(pex_idx, 1);
-
- DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
- /* link is Gen1, check the EP capability */
- addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
- DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
- if (addr == 0xff) {
- DEBUG_INIT_FULL_C
- ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
- pex_idx, 1);
- continue;
- }
-
- while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
- & 0xff) != 0x10) {
- addr = (pex_config_read(pex_idx, first_busno, 0,
- 0, addr) & 0xff00) >> 8;
- }
-
- /* Check for Gen2 and above */
- if ((pex_config_read(pex_idx, first_busno, 0, 0,
- addr + 0xc) & 0xf) < 0x2) {
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S(": remains Gen1\n");
- continue;
- }
-
- tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
- DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
- tmp &= ~(BIT(0) | BIT(1));
- tmp |= BIT(1);
- tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
- reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
- DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
-
- tmp = reg_read(PEX_CTRL_REG(pex_idx));
- DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
- tmp |= BIT(10);
- reg_write(PEX_CTRL_REG(pex_idx), tmp);
- DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
-
- /*
- * We need to wait 10ms before reading the PEX_DBG_STATUS_REG
- * in order not to read the status of the former state
- */
- mdelay(10);
-
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S
- (": Link upgraded to Gen2 based on client capabilities\n");
- }
-
- /* Update pex DEVICE ID */
- ctrl_mode = sys_env_model_get();
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- /* configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_DEVICE_AND_VENDOR_ID));
- dev_id &= 0xffff;
- dev_id |= ((ctrl_mode << 16) & 0xffff0000);
- reg_write(PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
- }
- DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
-
return MV_OK;
}
-
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
-{
- u32 pex_status;
-
- DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
-
- if (bus_num >= MAX_PEX_BUSSES) {
- DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
- bus_num, 4);
- return MV_BAD_PARAM;
- }
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
- pex_status |=
- (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), pex_status);
-
- return MV_OK;
-}
-
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
-{
- u32 pex_status;
-
- DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
- pex_status |=
- (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), pex_status);
-
- return MV_OK;
-}
-
-/*
- * pex_config_read - Read from configuration space
- *
- * DESCRIPTION:
- * This function performs a 32 bit read from PEX configuration space.
- * It supports both type 0 and type 1 of Configuration Transactions
- * (local and over bridge). In order to read from local bus segment, use
- * bus number retrieved from pex_local_bus_num_get(). Other bus numbers
- * will result configuration transaction of type 1 (over bridge).
- *
- * INPUT:
- * pex_if - PEX interface number.
- * bus - PEX segment bus number.
- * dev - PEX device number.
- * func - Function number.
- * reg_offs - Register offset.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * 32bit register data, 0xffffffff on error
- */
-u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
-{
- u32 pex_data = 0;
- u32 local_dev, local_bus;
- u32 pex_status;
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- local_dev =
- ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
- local_bus =
- ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
-
- /*
- * In PCI Express we have only one device number
- * and this number is the first number we encounter
- * else that the local_dev
- * spec pex define return on config read/write on any device
- */
- if (bus == local_bus) {
- if (local_dev == 0) {
- /*
- * if local dev is 0 then the first number we encounter
- * after 0 is 1
- */
- if ((dev != 1) && (dev != local_dev))
- return MV_ERROR;
- } else {
- /*
- * if local dev is not 0 then the first number we
- * encounter is 0
- */
- if ((dev != 0) && (dev != local_dev))
- return MV_ERROR;
- }
- }
-
- /* Creating PEX address to be passed */
- pex_data = (bus << PXCAR_BUS_NUM_OFFS);
- pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
- pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
- /* Legacy register space */
- pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
- /* Extended register space */
- pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
- PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
- pex_data |= PXCAR_CONFIG_EN;
-
- /* Write the address to the PEX configuration address register */
- reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
-
- /*
- * In order to let the PEX controller absorbed the address
- * of the read transaction we perform a validity check that
- * the address was written
- */
- if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
- return MV_ERROR;
-
- /* Cleaning Master Abort */
- reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
- PXSAC_MABORT);
- /* Read the Data returned in the PEX Data register */
- pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
-
- DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
-
- return pex_data;
-}
#ifndef _CTRL_PEX_H
#define _CTRL_PEX_H
+#include <pci.h>
#include "high_speed_env_spec.h"
-/* Sample at Reset */
-#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
+/* Direct access to PEX0 Root Port's PCIe Capability structure */
+#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
-/* PCI Express Control and Status Registers */
-#define MAX_PEX_BUSSES 256
-
-#define MISC_REGS_OFFSET 0x18200
-#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
-#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
-
-#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
- (0x40000 + ((if) - 1) * 0x4000) : \
- 0x80000)
-#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if))
-#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
-#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
-#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
-#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
-#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64)
-#define PEX_LINK_CAPABILITY_REG 0x6c
-#define PEX_LINK_CTRL_STAT_REG 0x70
-#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
-#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
-#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
-#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
-
-/* PEX_CAPABILITIES_REG fields */
+/* SOC_CONTROL_REG1 fields */
#define PCIE0_ENABLE_OFFS 0
#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
#define PCIE1_ENABLE_OFFS 1
#define PCIE3_ENABLE_OFFS 3
#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
-/* Controller revision info */
-#define PEX_DEVICE_AND_VENDOR_ID 0x000
-#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
-
-/* PCI Express Configuration Address Register */
-#define PXCAR_REG_NUM_OFFS 2
-#define PXCAR_REG_NUM_MAX 0x3f
-#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \
- PXCAR_REG_NUM_OFFS)
-#define PXCAR_FUNC_NUM_OFFS 8
-#define PXCAR_FUNC_NUM_MAX 0x7
-#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \
- PXCAR_FUNC_NUM_OFFS)
-#define PXCAR_DEVICE_NUM_OFFS 11
-#define PXCAR_DEVICE_NUM_MAX 0x1f
-#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \
- PXCAR_DEVICE_NUM_OFFS)
-#define PXCAR_BUS_NUM_OFFS 16
-#define PXCAR_BUS_NUM_MAX 0xff
-#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \
- PXCAR_BUS_NUM_OFFS)
-#define PXCAR_EXT_REG_NUM_OFFS 24
-#define PXCAR_EXT_REG_NUM_MAX 0xf
-
-#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8)
-#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc)
-
-#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
-#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS)
-
-#define PXCAR_CONFIG_EN BIT(31)
-#define PEX_STATUS_AND_COMMAND 0x004
-#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */
-
int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
-u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
-
void board_pex_config(void);
#endif
#include "sys_env_lib.h"
#include "ctrl_pex.h"
-
-
/*
* serdes_seq_db - holds all serdes sequences, their size and the
* relevant index in the data array initialized in serdes_seq_init
(serdes_mode == PEX_END_POINT_X1);
pex_idx = serdes_type - PEX0;
- if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
+ if (serdes_type == PEX0) {
/* For PEX by 4, init only the PEX 0 */
reg_data = reg_read(SOC_CONTROL_REG1);
if (is_pex_by1 == 1)
reg_data &= ~0x4000;
reg_write(SOC_CONTROL_REG1, reg_data);
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x6c));
- reg_data &= ~0x3f0;
- if (is_pex_by1 == 1)
- reg_data |= 0x10;
- else
- reg_data |= 0x40;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
- reg_data);
-
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x6c));
- reg_data &= ~0xf;
- reg_data |= 0x2;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
- reg_data);
-
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x70));
- reg_data &= ~0x40;
- reg_data |= 0x40;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
- reg_data);
+ /*
+ * Set Maximum Link Width to X1 or X4 in Root
+ * Port's PCIe Link Capability register.
+ * This register is read-only but if is not set
+ * correctly then access to PCI config space of
+ * endpoint card behind this Root Port does not
+ * work.
+ */
+ reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET +
+ PCI_EXP_LNKCAP);
+ reg_data &= ~PCI_EXP_LNKCAP_MLW;
+ reg_data |= (is_pex_by1 ? 1 : 4) << 4;
+ reg_write(PEX0_RP_PCIE_CFG_OFFSET +
+ PCI_EXP_LNKCAP, reg_data);
}
CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC_SUPPORT) || defined(CONFIG_SPL_SATA_SUPPORT)
+#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \
+ defined(CONFIG_SPL_SATA)
/*
* When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must
* and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET need to point to the
* kwbimage main header.
*/
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported
#endif
* stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be
* set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper.
*/
-#ifdef CONFIG_SPL_SATA_SUPPORT
+#ifdef CONFIG_SPL_SATA
#if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1
#error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1
#endif
uint8_t checksum; /* 0x1F */
} __packed;
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
u32 spl_mmc_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
mhdr->blockid != IBR_HDR_SPI_ID &&
#endif
-#ifdef CONFIG_SPL_SATA_SUPPORT
+#ifdef CONFIG_SPL_SATA
mhdr->blockid != IBR_HDR_SATA_ID &&
#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
mhdr->blockid != IBR_HDR_SDIO_ID &&
#endif
1
spl_image->offset = mhdr->srcaddr;
-#ifdef CONFIG_SPL_SATA_SUPPORT
+#ifdef CONFIG_SPL_SATA
/*
* For SATA srcaddr is specified in number of sectors.
* The main header is must be stored at sector number 1.
}
#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
/*
* For SDIO (eMMC) srcaddr is specified in number of sectors.
* This expects that sector size is 512 bytes and recalculates
* If SPL is compiled with chosen boot_device support
* then use SPL driver for loading U-Boot proper.
*/
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
case BOOT_DEVICE_MMC1:
return BOOT_DEVICE_MMC1;
#endif
-#ifdef CONFIG_SPL_SATA_SUPPORT
+#ifdef CONFIG_SPL_SATA
case BOOT_FROM_SATA:
return BOOT_FROM_SATA;
#endif
# */
obj-y += lowlevel_init.o clock.o cpu.o
-
# */
obj-y += lowlevel_init.o clock.o cpu.o
-
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
imply SPL_NAND_SUPPORT
imply SPL_OMAP3_ID_NAND
imply SPL_POWER
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
imply SYS_THUMB_BUILD
imply TWL4030_POWER
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
imply SPL_NAND_SIMPLE
imply SPL_NAND_SUPPORT
imply SPL_POWER
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
imply SYS_THUMB_BUILD
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_SUPPORT
imply SPL_POWER
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
config TI814X
select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
+ imply SKIP_LOWLEVEL_INIT
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_SUPPORT
imply SYS_I2C_OMAP24XX
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
imply SPL_NAND_SUPPORT
imply SPL_OF_LIBFDT
imply SPL_POWER
imply SPL_SEPARATE_BSS
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_WATCHDOG
imply SPL_YMODEM_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT
+ imply SPL_MMC
imply SPL_NAND_SUPPORT
imply SPL_POWER
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_WATCHDOG
imply SPL_YMODEM_SUPPORT
help
obj-$(CONFIG_TI816X) += clock_ti816x.o
obj-y += sys_info.o
obj-y += ddr.o
-ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y += emif4.o
endif
obj-$(CONFIG_TI816X) += ti816x_emif4.o
int dram_init(void)
{
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
sdram_init();
#endif
#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
int arch_cpu_init_dm(void)
{
hw_data_init();
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
early_system_init();
#endif
return 0;
#include <power/tps65217.h>
#include <spl.h>
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
&ddr3_chilisom_emif_reg_data, 0);
}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
gpmc_init();
#endif
#if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW)
arch_misc_init();
if (pv->value[opp]) {
/* Handle non-empty members only */
pv->value[opp] = optimize_vcore_voltage(pv, opp);
- px = (struct volts *)vcores;
+ px = (struct volts *)vcores;
j = 0;
while (px < pv) {
/*
static int gpi2c = 1;
if (gpi2c) {
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE);
gpi2c = 0;
}
}
hw_data_init();
}
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/******************************************************************************
* Routine: secure_unlock
go_to_speed_end:
#endif
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash ip register */
.control_std_fuse_die_id_1 = 0x4A002208,
.control_std_fuse_die_id_2 = 0x4A00220C,
.control_std_fuse_die_id_3 = 0x4A002210,
- .control_phy_power_usb = 0x4A002370,
+ .control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
obj-y += dram.o
obj-y += timer.o
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
endif
#define TVR_ARM_TIMER_OFFS 0
#define TVR_ARM_TIMER_MASK 0xffffffff
#define TVR_ARM_TIMER_MAX 0xffffffff
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
static inline ulong read_timer(void)
{
imply SPL_GZIP
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_TINY_MEMSET
imply SPL_YMODEM_SUPPORT
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
- default n
choice
prompt "Qos setting primary"
config R8A774A1
bool "Renesas SoC R8A774A1"
+ select GICV2
imply CLK_R8A774A1
imply PINCTRL_PFC_R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
+ select GICV2
imply CLK_R8A774B1
imply PINCTRL_PFC_R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
+ select GICV2
imply CLK_R8A774C0
imply PINCTRL_PFC_R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
+ select GICV2
imply CLK_R8A774E1
imply PINCTRL_PFC_R8A774E1
config R8A7795
bool "Renesas SoC R8A7795"
+ select GICV2
imply CLK_R8A7795
imply PINCTRL_PFC_R8A7795
config R8A7796
bool "Renesas SoC R8A7796"
+ select GICV2
imply CLK_R8A7796
imply PINCTRL_PFC_R8A7796
config R8A77965
bool "Renesas SoC R8A77965"
+ select GICV2
imply CLK_R8A77965
imply PINCTRL_PFC_R8A77965
config R8A77970
bool "Renesas SoC R8A77970"
+ select GICV2
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
config R8A77980
bool "Renesas SoC R8A77980"
+ select GICV2
imply CLK_R8A77980
imply PINCTRL_PFC_R8A77980
config R8A77990
bool "Renesas SoC R8A77990"
+ select GICV2
imply CLK_R8A77990
imply PINCTRL_PFC_R8A77990
config R8A77995
bool "Renesas SoC R8A77995"
+ select GICV2
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
config R8A779A0
bool "Renesas SoC R8A779A0"
+ select GICV3
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
#include "rcar-base.h"
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
-#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
-
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640801
#define MSTP1_BITS 0xDB6E9BDF
* R-Car (R8A7791) I/O Addresses
*/
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
-
/* SDHI */
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
#include "rcar-base.h"
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
-#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
-
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00400801
#define MSTP1_BITS 0x9B6F987F
* R8A7793 I/O Addresses
*/
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
-
/* SDHI */
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
#include "rcar-base.h"
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
-
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00440801
#define MSTP1_BITS 0x936899DA
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
-/*
- * SH-I2C
- * Ch2 and ch3 are different address. These are defined
- * in the header of each SoCs.
- */
-#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
-#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
-
/* RCAR-I2C */
#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
#define PUEN_USB1_OVC (1 << 2)
#define PUEN_USB1_PWEN (1 << 1)
-/* IICDVFS (I2C) */
-#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000
-
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <linux/bitops.h>
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
#define CPU_32_PORT0_16(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
+ PORT_10(fn, pfx, sfx), \
PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
- select SPL_SERIAL_SUPPORT
- select TPL_SERIAL_SUPPORT
+ select SPL_SERIAL
+ select TPL_SERIAL
select DEBUG_UART_BOARD_INIT
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_DRIVERS_MISC
imply ROCKCHIP_COMMON_BOARD
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_ROCKCHIP_COMMON_BOARD
- imply TPL_SERIAL_SUPPORT
+ imply TPL_SERIAL
imply TPL_ROCKCHIP_COMMON_BOARD
select TPL_LIBCOMMON_SUPPORT
select TPL_LIBGENERIC_SUPPORT
bool "Support Rockchip RK3288"
select CPU_V7A
select OF_BOARD_SETUP
+ select SKIP_LOWLEVEL_INIT_ONLY
select SUPPORT_SPL
select SPL
select SUPPORT_TPL
imply TPL_RAM
imply TPL_REGMAP
imply TPL_ROCKCHIP_COMMON_BOARD
- imply TPL_SERIAL_SUPPORT
+ imply TPL_SERIAL
imply TPL_SYSCON
imply USB_FUNCTION_ROCKUSB
imply CMD_ROCKUSB
imply SPL_REGMAP
imply SPL_SYSCON
imply SPL_RAM
- imply SPL_SERIAL_SUPPORT
- imply TPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
+ imply TPL_SERIAL
imply SPL_SEPARATE_BSS
help
The Rockchip RK3308 is a ARM-based Soc which embedded with quad
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
- imply SPL_SERIAL_SUPPORT
- imply TPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
+ imply TPL_SERIAL
imply SPL_SEPARATE_BSS
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SEPARATE_BSS
- imply SPL_SERIAL_SUPPORT
- imply TPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
+ imply TPL_SERIAL
imply TPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
- select SPL_SERIAL_SUPPORT
+ select SPL_SERIAL
select SPL_DRIVERS_MISC
select CLK
select FIT
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_ROCKCHIP_COMMON_BOARD
- imply TPL_SERIAL_SUPPORT
+ imply TPL_SERIAL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SYS_MALLOC_SIMPLE
This enables support code in the BOOT0 hook for the TPL stage
to allow multiple entries.
-config SPL_MMC_SUPPORT
+config SPL_MMC
default y if !SPL_ROCKCHIP_BACK_TO_BROM
config ROCKCHIP_SPI_IMAGE
#include <init.h>
#include <ram.h>
#include <spl.h>
-#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/sdram_px30.h>
config SYS_MALLOC_F_LEN
default 0x400
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config TPL_LDSCRIPT
config SYS_MALLOC_F_LEN
default 0x400
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
source "board/rockchip/evb_rk3036/Kconfig"
config SPL_LIBGENERIC_SUPPORT
default y
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config TPL_LIBCOMMON_SUPPORT
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3188.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/ofnode.h>
#include <linux/err.h>
#define GRF_BASE 0x20008000
}
#ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
char *led_name;
int ret;
- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+ led_name = ofnode_conf_read_str("u-boot,boot-led");
if (!led_name)
return 0;
ret = led_get_by_label(led_name, &dev);
config SPL_LIBGENERIC_SUPPORT
default y
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config TPL_MAX_SIZE
config SPL_LIBGENERIC_SUPPORT
default y
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config TPL_LDSCRIPT
config SYS_MALLOC_F_LEN
default 0x400
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config ROCKCHIP_BOOT_MODE_REG
# Copyright (c) 2016 Andreas Färber
obj-y += clk_rk3368.o
obj-y += rk3368.o
-obj-y += syscon_rk3368.o
+obj-y += syscon_rk3368.o
U_BOOT_DRIVER(syscon_rk3399) = {
.name = "rk3399_syscon",
.id = UCLASS_SYSCON,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_match = rk3399_syscon_ids,
.name = "rk3568_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3568_syscon_ids,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
};
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#else
-#ifdef CONFIG_SPL_OPTEE
+#ifdef CONFIG_SPL_OPTEE_IMAGE
struct tos_parameter_t *tos_parameter;
tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
#include <asm/arch-rockchip/bootrom.h>
#include <linux/bitops.h>
+#if CONFIG_IS_ENABLED(BANNER_PRINT)
+#include <timestamp.h>
+#endif
+
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
struct udevice *dev;
int ret;
-#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
/*
* Debug UART can be used from here if required:
*
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
*
- * Only SROMC is defined as of now
+ * Only SROMC is defined as of now
*/
#ifndef __ASM_ARCH_SROMC_H_
#include <common.h>
#include <mmc.h>
#include <asm/arch/misc.h>
+#include <asm/unaligned.h>
/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */
#define UNSTUFF_BITS(resp, start, size) \
if (!mmc_dev)
return 0;
+ if (mmc_init(mmc_dev))
+ return 0;
+
return UNSTUFF_BITS(mmc_dev->cid, 16, 32);
}
void msm_generate_mac_addr(u8 *mac)
{
- int i;
- char sn[9];
-
- snprintf(sn, 9, "%08x", msm_board_serial());
-
- /* fill in the mac with serialno, use locally adminstrated pool */
+ /* use locally adminstrated pool */
mac[0] = 0x02;
- mac[1] = 00;
- for (i = 3; i >= 0; i--) {
- mac[i + 2] = hextoul(&sn[2 * i], NULL);
- sn[2 * i] = 0;
- }
+ mac[1] = 0x00;
+
+ /*
+ * Put the 32-bit serial number in the last 32-bit of the MAC address.
+ * Use big endian order so it is consistent with the serial number
+ * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd
+ */
+ put_unaligned_be32(msm_board_serial(), &mac[2]);
}
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
}
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
u32 spl_mmc_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
}
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
u32 spl_mmc_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return BOOT_DEVICE_MMC1;
}
-#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT)
+#if IS_ENABLED(CONFIG_SPL_MMC)
u32 spl_boot_mode(const u32 boot_device)
{
if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
select SPL_OF_TRANSLATE
select SPL_PINCTRL
select SPL_RAM
- select SPL_SERIAL_SUPPORT
+ select SPL_SERIAL
select SPL_SYS_MALLOC_SIMPLE
select SPL_TIMER
select SPL_XIP_SUPPORT
select SPL_PINCTRL
select SPL_REGMAP
select SPL_DM_RESET
- select SPL_SERIAL_SUPPORT
+ select SPL_SERIAL
select SPL_SYSCON
select SPL_WATCHDOG if WATCHDOG
imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
imply SPL_LIBDISK_SUPPORT
- imply SPL_SPI_LOAD if SPL_SPI_SUPPORT
+ imply SPL_SPI_LOAD if SPL_SPI
config SYS_SOC
default "stm32mp"
config CMD_STM32KEY
bool "command stm32key to fuse public key hash"
- default n
help
fuse public key hash in corresponding fuse used to authenticate
binary.
* when FIP is not used by TF-A
*/
if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
- CONFIG_IS_ENABLED(OPTEE) &&
!tee_find_device(NULL, NULL, NULL, NULL))
stm32_fdt_disable_optee(blob);
feature.
endif
-config SUN6I_P2WI
- bool "Allwinner sun6i internal P2WI controller"
- help
- If you say yes to this option, support will be included for the
- P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
- SOCs.
- The P2WI looks like an SMBus controller (which supports only byte
- accesses), except that it only supports one slave device.
- This interface is used to connect to specific PMIC devices (like the
- AXP221).
-
config SUN6I_PRCM
bool
help
in A31 SoC.
config AXP_PMIC_BUS
- bool "Sunxi AXP PMIC bus access helpers"
+ bool
+ select DM_PMIC if DM_I2C
+ select PMIC_AXP if DM_I2C
help
Select this PMIC bus access helpers for Sunxi platform PRCM or other
AXP family PMIC devices.
-config SUN8I_RSB
- bool "Allwinner sunXi Reduced Serial Bus Driver"
- help
- Say y here to enable support for Allwinner's Reduced Serial Bus
- (RSB) support. This controller is responsible for communicating
- with various RSB based devices, such as AXP223, AXP8XX PMICs,
- and AC100/AC200 ICs.
-
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
config MACH_SUNXI_H3_H5
bool
- select DM_I2C
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_DRAM_DW
select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
+ imply SPL_SYS_I2C_LEGACY
+ imply SYS_I2C_LEGACY
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
imply CONS_INDEX_2 if !DM_SERIAL
+ imply SPL_SYS_I2C_LEGACY
+ imply SYS_I2C_LEGACY
config MACH_SUN6I
bool "sun6i (Allwinner A31)"
select ARCH_SUPPORT_PSCI
select DRAM_SUN6I
select PHY_SUN4I_USB
- select SUN6I_P2WI
+ select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN6I_P2WI
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN7I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply SPL_SYS_I2C_LEGACY
+ imply SYS_I2C_LEGACY
config MACH_SUN8I_A23
bool "sun8i (Allwinner A23)"
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A23
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A33
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
select CPU_V7A
select DRAM_SUN8I_A83T
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select MMC_SUNXI_HAS_MODE_SWITCH
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
select PHY_SUN4I_USB
+ imply SPL_SYS_I2C_LEGACY
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3/V3s/S3/S3L)"
bool "sun9i (Allwinner A80)"
select CPU_V7A
select DRAM_SUN9I
+ select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
- select SUN8I_RSB
select SUPPORT_SPL
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SPI
- select DM_I2C
select DM_SPI if SPI
select DM_SPI_FLASH
select PHY_SUN4I_USB
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- select SUN8I_RSB
select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
- default n
---help---
Repurpose the SD card slot for getting access to the UART0 serial
console. Primarily useful only for low level u-boot debugging on
config OLD_SUNXI_KERNEL_COMPAT
bool "Enable workarounds for booting old kernels"
- default n
---help---
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
---help---
See MMC0_CD_PIN help text.
-config MMC1_PINS
- string "Pins for mmc1"
- default ""
+config MMC1_PINS_PH
+ bool "Pins for mmc1 are on Port H"
+ depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
---help---
- Set the pins used for mmc1, when applicable. This takes a string in the
- format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
-
-config MMC2_PINS
- string "Pins for mmc2"
- default ""
- ---help---
- See MMC1_PINS help text.
-
-config MMC3_PINS
- string "Pins for mmc3"
- default ""
- ---help---
- See MMC1_PINS help text.
+ Select this option for boards where mmc1 uses the Port H pinmux.
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
config I2C1_ENABLE
bool "Enable I2C/TWI controller 1"
- default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
config I2C2_ENABLE
bool "Enable I2C/TWI controller 2"
- default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
if MACH_SUN6I || MACH_SUN7I
config I2C3_ENABLE
bool "Enable I2C/TWI controller 3"
- default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
if MACH_SUN7I
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
- default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
config AXP_GPIO
bool "Enable support for gpio-s on axp PMICs"
- default n
+ depends on AXP_PMIC_BUS
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
config VIDEO_VGA
bool "VGA output support"
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
- default n
---help---
Say Y here to add support for outputting video over VGA.
config VIDEO_VGA_VIA_LCD
bool "VGA via LCD controller support"
depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
- default n
---help---
Say Y here to add support for external DACs connected to the parallel
LCD interface driving a VGA connector, such as found on the
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
bool "Force sync active high for VGA via LCD controller support"
depends on VIDEO_VGA_VIA_LCD
- default n
---help---
Say Y here if you've a board which uses opendrain drivers for the vga
hsync and vsync signals. Opendrain drivers cannot generate steep enough
config VIDEO_COMPOSITE
bool "Composite video output support"
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
- default n
---help---
Say Y here to add support for outputting composite video.
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO_SUNXI
- default n
- select CMD_I2C
+ select DM_I2C_GPIO
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
-config VIDEO_LCD_PANEL_I2C_SDA
- string "LCD panel i2c interface SDA pin"
+config VIDEO_LCD_PANEL_I2C_NAME
+ string "LCD panel i2c interface node name"
depends on VIDEO_LCD_PANEL_I2C
- default "PG12"
+ default "i2c@0"
---help---
- Set the SDA pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_PANEL_I2C_SCL
- string "LCD panel i2c interface SCL pin"
- depends on VIDEO_LCD_PANEL_I2C
- default "PG10"
- ---help---
- Set the SCL pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
+ Set the device tree node name for the LCD i2c interface.
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
config SUNXI_DE2
bool
- default n
config VIDEO_DE2
bool "Display Engine 2 video driver"
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
-obj-$(CONFIG_SUN6I_P2WI) += p2wi.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
-obj-$(CONFIG_SUN8I_RSB) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
spl_init();
preloader_console_init();
-#ifdef CONFIG_SPL_I2C
+#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/gtbus.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_SPL_BUILD
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
- } else {
+ } else {
/* any other frequency that is a multiple of 24 */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
/* Set work mode register */
mctl_set_cr(para);
* MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
* write levelling disabled, TDQS disabled, output buffer enabled
* MR2: manual full array self refresh, dynamic ODT off,
- * CAS write latency (CWL): 8
+ * CAS write latency (CWL): 8
*/
static u32 mr_ddr3[7] = {
0x00001c70, 0x00000040, 0x00000018, 0x00000000,
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Sunxi A31 Power Management Unit
- *
- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
- * http://linux-sunxi.org
- *
- * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
- *
- * (C) Copyright 2006-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-void p2wi_init(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- /* Enable p2wi and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
- /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
- writel(P2WI_CTRL_RESET, &p2wi->ctrl);
- sdelay(0x100);
- writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
- &p2wi->cc);
-}
-
-int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(P2WI_PM_DEV_ADDR(slave_addr) |
- P2WI_PM_CTRL_ADDR(ctrl_reg) |
- P2WI_PM_INIT_DATA(init_data) |
- P2WI_PM_INIT_SEND,
- &p2wi->pm);
-
- while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return 0;
-}
-
-static int p2wi_await_trans(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- int ret;
- u8 reg;
-
- while (1) {
- reg = readl(&p2wi->status);
- if (reg & P2WI_STAT_TRANS_ERR) {
- ret = -EIO;
- break;
- }
- if (reg & P2WI_STAT_TRANS_DONE) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(reg, &p2wi->status); /* Clear status bits */
- return ret;
-}
-
-int p2wi_read(const u8 addr, u8 *data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- int ret;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_NUM_BYTES(1) |
- P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- ret = p2wi_await_trans();
-
- *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
- return ret;
-}
-
-int p2wi_write(const u8 addr, u8 data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
- writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- return p2wi_await_trans();
-}
* axp223 uses the rsb bus, these functions abstract this.
*/
+#include <axp_pmic.h>
#include <common.h>
+#include <dm.h>
#include <asm/arch/p2wi.h>
#include <asm/arch/rsb.h>
#include <i2c.h>
+#include <power/pmic.h>
#include <asm/arch/pmic_bus.h>
#define AXP152_I2C_ADDR 0x30
#define AXP305_I2C_ADDR 0x36
#define AXP221_CHIP_ADDR 0x68
-#define AXP221_CTRL_ADDR 0x3e
-#define AXP221_INIT_DATA 0x3e
-/* AXP818 device and runtime addresses are same as AXP223 */
-#define AXP223_DEVICE_ADDR 0x3a3
-#define AXP223_RUNTIME_ADDR 0x2d
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+static struct udevice *pmic;
+#else
+static int pmic_i2c_address(void)
+{
+ if (IS_ENABLED(CONFIG_AXP152_POWER))
+ return AXP152_I2C_ADDR;
+ if (IS_ENABLED(CONFIG_AXP305_POWER))
+ return AXP305_I2C_ADDR;
+
+ /* Other AXP2xx and AXP8xx variants */
+ return AXP209_I2C_ADDR;
+}
+#endif
int pmic_bus_init(void)
{
/* This cannot be 0 because it is used in SPL before BSS is ready */
static int needs_init = 1;
- __maybe_unused int ret;
+ int ret = 0;
if (!needs_init)
return 0;
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- p2wi_init();
- ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
- AXP221_INIT_DATA);
-# elif defined CONFIG_MACH_SUN8I_R40
- /* Nothing. R40 uses the AXP221s in I2C mode */
- ret = 0;
-# else
- ret = rsb_init();
- if (ret)
- return ret;
-
- ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
-# endif
- if (ret)
- return ret;
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic),
+ &pmic);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) {
+ p2wi_init();
+ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR,
+ AXP_PMIC_MODE_REG,
+ AXP_PMIC_MODE_P2WI);
+ } else if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) {
+ ret = rsb_init();
+ if (ret)
+ return ret;
+
+ ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR,
+ AXP_PMIC_PRI_RUNTIME_ADDR);
+ }
#endif
- needs_init = 0;
- return 0;
+ needs_init = ret;
+
+ return ret;
}
int pmic_bus_read(u8 reg, u8 *data)
{
-#ifdef CONFIG_AXP152_POWER
- return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP305_POWER
- return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_read(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-# else
- return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
-# endif
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ return pmic_read(pmic, reg, data, 1);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
+ return p2wi_read(reg, data);
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
+ return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
+
+ return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
#endif
}
int pmic_bus_write(u8 reg, u8 data)
{
-#ifdef CONFIG_AXP152_POWER
- return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP305_POWER
- return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_write(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-# else
- return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
-# endif
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ return pmic_write(pmic, reg, &data, 1);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
+ return p2wi_write(reg, data);
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
+ return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
+
+ return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
#endif
}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Based on allwinner u-boot sources rsb code which is:
- * (C) Copyright 2007-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * lixiang <lixiang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/rsb.h>
-
-static int rsb_set_device_mode(void);
-
-static void rsb_cfg_io(void)
-{
-#ifdef CONFIG_MACH_SUN8I
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
- sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
-#else
-#error unsupported MACH_SUNXI
-#endif
-}
-
-static void rsb_set_clk(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- u32 div = 0;
- u32 cd_odly = 0;
-
- /* Source is Hosc24M, set RSB clk to 3Mhz */
- div = 24000000 / 3000000 / 2 - 1;
- cd_odly = div >> 1;
- if (!cd_odly)
- cd_odly = 1;
-
- writel((cd_odly << 8) | div, &rsb->ccr);
-}
-
-int rsb_init(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- /* Enable RSB and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
-
- /* Setup external pins */
- rsb_cfg_io();
-
- writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
- rsb_set_clk();
-
- return rsb_set_device_mode();
-}
-
-static int rsb_await_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- u32 stat;
- int ret;
-
- while (1) {
- stat = readl(&rsb->stat);
- if (stat & RSB_STAT_LBSY_INT) {
- ret = -EBUSY;
- break;
- }
- if (stat & RSB_STAT_TERR_INT) {
- ret = -EIO;
- break;
- }
- if (stat & RSB_STAT_TOVER_INT) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(stat, &rsb->stat); /* Clear status bits */
-
- return ret;
-}
-
-static int rsb_set_device_mode(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
- &rsb->dmcr);
-
- while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return rsb_await_trans();
-}
-
-static int rsb_do_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
- return rsb_await_trans();
-}
-
-int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
- RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
- writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(data, &rsb->data);
- writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- int ret;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(RSB_CMD_BYTE_READ, &rsb->cmd);
-
- ret = rsb_do_trans();
- if (ret)
- return ret;
-
- *data = readl(&rsb->data) & 0xff;
-
- return 0;
-}
config SPL_LIBGENERIC_SUPPORT
default y
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config TEGRA_CLKRST
select CPU_V7A
select SPL
select SPL_BOARD_INIT if SPL
+ select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
select SUPPORT_SPL
select TEGRA_CLKRST
select TEGRA_COMMON
config TEGRA210
bool "Tegra210 family"
+ select GICV2
select TEGRA_ARMV8_COMMON
select TEGRA_CLKRST
select TEGRA_GPIO
config TEGRA186
bool "Tegra186 family"
select DM_MAILBOX
+ select GICV2
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
#include <asm/arch-tegra/dc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
-
The Samsung "stemmy" board supports Samsung smartphones released with
the ST-Ericsson NovaThor U8500 SoC, e.g.
- - Samsung Galaxy S III mini (GT-I8190) "golden"
+ - Samsung Galaxy Ace 2 (GT-I8160) "codina"
+ - Samsung Galaxy Amp (SGH-I407) "kyle"
+ - Samsung Galaxy Beam (GT-I8530) "gavini"
+ - Samsung Galaxy Exhibit (SGH-T599) "codina" (TMO)
- Samsung Galaxy S Advance (GT-I9070) "janice"
+ - Samsung Galaxy S III mini (GT-I8190) "golden"
- Samsung Galaxy Xcover 2 (GT-S7710) "skomer"
- - Samsung Galaxy Ace 2 (GT-I8160) "codina"
-
- and likely others as well (untested).
- See board/ste/stemmy/README for details.
+ See doc/board/ste/stemmy.rst for details.
endchoice
obj-y += spl_board_init.o
obj-y += memconf.o
obj-y += bcu/
-obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc-boot-mode.o
+obj-$(CONFIG_SPL_MMC) += mmc-boot-mode.o
else
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
-config GICV3
- def_bool y
-
config SYS_MALLOC_LEN
default 0x2000000
config SPL_LIBGENERIC_SUPPORT
default y
-config SPL_MMC_SUPPORT
+config SPL_MMC
default y if MMC_SDHCI_ZYNQ
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config SPL_SPI_FLASH_SUPPORT
default y if ZYNQ_QSPI
-config SPL_SPI_SUPPORT
+config SPL_SPI
default y if ZYNQ_QSPI
config ZYNQ_DDRC_INIT
u32 mode;
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#ifdef CONFIG_SPL_SPI
case ZYNQ_BM_QSPI:
mode = BOOT_DEVICE_SPI;
break;
case ZYNQ_BM_NOR:
mode = BOOT_DEVICE_NOR;
break;
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
case ZYNQ_BM_SD:
mode = BOOT_DEVICE_MMC1;
break;
config SPL_LIBGENERIC_SUPPORT
default y
-config SPL_MMC_SUPPORT
+config SPL_MMC
default y if MMC_SDHCI_ZYNQ
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
default y
config SPL_SPI_FLASH_SUPPORT
default y if ZYNQ_QSPI
-config SPL_SPI_SUPPORT
+config SPL_SPI
default y if ZYNQ_QSPI
config SYS_BOARD
switch (bootmode) {
case JTAG_MODE:
return BOOT_DEVICE_RAM;
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
return BOOT_DEVICE_MMC2;
case USB_MODE:
return BOOT_DEVICE_DFU;
#endif
-#ifdef CONFIG_SPL_SATA_SUPPORT
+#ifdef CONFIG_SPL_SATA
case SW_SATA_MODE:
return BOOT_DEVICE_SATA;
#endif
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#ifdef CONFIG_SPL_SPI
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
return BOOT_DEVICE_SPI;
#include <asm-offsets.h>
#include <config.h>
-#include "version.h"
#include <asm/cache.h>
#define _START _start
_vectors:
#if defined(CONFIG_CF_SBF)
INITSP: .long 0 /* Initial SP */
-INITPC: .long ASM_DRAMINIT /* Initial PC */
+INITPC: .long ASM_DRAMINIT /* Initial PC */
#else
INITSP: .long 0 /* Initial SP */
-INITPC: .long _START /* Initial PC */
+INITPC: .long _START /* Initial PC */
#endif
vector02_0F:
/******************************************************************************/
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
#include <asm-offsets.h>
#include <config.h>
-#include "version.h"
#include <asm/cache.h>
#define _START _start
/******************************************************************************/
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
#include <asm-offsets.h>
#include <config.h>
-#include "version.h"
#include <asm/cache.h>
#define _START _start
/******************************************************************************/
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
extra-y = start.o
obj-y = interrupts.o cpu.o speed.o cpu_init.o
-
#include <asm-offsets.h>
#include <config.h>
-#include "version.h"
#include <asm/cache.h>
#define _START _start
/******************************************************************************/
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION
-.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
-.ascii CONFIG_IDENT_STRING, "\0"
.align 4
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
{
#include <asm-offsets.h>
#include <config.h>
-#include "version.h"
#include <asm/cache.h>
#define _START _start
/******************************************************************************/
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
#include <common.h>
#include <asm-offsets.h>
#include <config.h>
-#include <timestamp.h>
-#include "version.h"
#include <asm/cache.h>
#define _START _start
INITSP: .long 0 /* Initial SP */
#ifdef CONFIG_CF_SBF
-INITPC: .long ASM_DRAMINIT /* Initial PC */
+INITPC: .long ASM_DRAMINIT /* Initial PC */
#endif
#ifdef CONFIG_SYS_NAND_BOOT
-INITPC: .long ASM_DRAMINIT_N /* Initial PC */
+INITPC: .long ASM_DRAMINIT_N /* Initial PC */
#endif
#else
INITSP: .long 0 /* Initial SP */
-INITPC: .long _START /* Initial PC */
+INITPC: .long _START /* Initial PC */
#endif
/******************************************************************************/
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
#include <config.h>
OUTPUT_ARCH(m68k)
+ENTRY(_start)
#ifndef LDS_BOARD_TEXT
#define LDS_BOARD_TEXT
} gpio_t;
#endif /* __IMMAP_5307__ */
-
#define MCF_GPIO_PAR_TIMER 0x10004C
#define MCF_DSCR_EIM 0x100050
-#define MCF_DCSR_FEC12C 0x100052
+#define MCF_DCSR_FEC12C 0x100052
#define MCF_DCSR_UART 0x100053
#define MCF_DCSR_QSPI 0x100054
#define MCF_DCSR_TIMER 0x100055
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
#endif /* mcf5307_h */
-
void arch_lmb_reserve(struct lmb *lmb)
{
- ulong sp;
-
- /*
- * Booting a (Linux) kernel image
- *
- * Allocate space for command line and board info - the
- * address should be as high as possible within the reach of
- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
- * memory, which means far enough below the current stack
- * pointer.
- */
- sp = get_sp();
- debug ("## Current stack ends at 0x%08lx ", sp);
-
- /* adjust sp by 1K to be safe */
- sp -= 1024;
- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024);
}
int do_bootm_linux(int flag, int argc, char *const argv[],
umul_ppmm (__w.s.high, __w.s.low, u, v); \
__w.ll; })
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef int word_type __attribute__ ((mode (__word__)));
void arch_lmb_reserve(struct lmb *lmb)
{
- ulong sp, bank_end;
- int bank;
-
- /*
- * Booting a (Linux) kernel image
- *
- * Allocate space for command line and board info - the
- * address should be as high as possible within the reach of
- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
- * memory, which means far enough below the current stack
- * pointer.
- */
- sp = get_sp();
- debug("## Current stack ends at 0x%08lx ", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= 4096;
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (sp < gd->bd->bi_dram[bank].start)
- continue;
- bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size;
- if (sp >= bank_end)
- continue;
- lmb_reserve(lmb, sp, bank_end - sp);
- break;
- }
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}
static void boot_jump_linux(bootm_headers_t *images, int flag)
static void boot_prep_linux(bootm_headers_t *images)
{
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
select MIPS_INSERT_BOOT_CONFIG
- select MIPS_L1_CACHE_SHIFT_6
+ select SYS_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_CONTROL
select OF_ISA_BUS
select DM
select DM_SERIAL
select MIPS_CM
- select MIPS_L1_CACHE_SHIFT_6
+ select SYS_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_BOARD_SETUP
select OF_CONTROL
select DM_ETH
select DM_GPIO
select DM_SERIAL
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select OF_CONTROL
select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
config RESTORE_EXCEPTION_VECTOR_BASE
bool "Restore exception vector base before booting linux kernel"
- default n
help
In U-Boot the exception vector base will be moved to top of memory,
to be used to display register dump when exception occurs.
config OVERRIDE_EXCEPTION_VECTOR_BASE
bool "Override the exception vector base to be restored"
depends on RESTORE_EXCEPTION_VECTOR_BASE
- default n
help
Enable this option if you want to use a different exception vector
base rather than the previously saved one.
config INIT_STACK_WITHOUT_MALLOC_F
bool "Do not reserve malloc space on initial stack"
- default n
help
Enable this option if you don't want to reserve malloc space on
initial stack. This is useful if the initial stack can't hold large
config SPL_INIT_STACK_WITHOUT_MALLOC_F
bool "Do not reserve malloc space on initial stack in SPL"
- default n
help
Enable this option if you don't want to reserve malloc space on
initial stack. This is useful if the initial stack can't hold large
config SPL_LOADER_SUPPORT
bool
- default n
help
Enable this option if you want to use SPL loaders without DM enabled.
config MIPS_BOOT_FDT
bool "Hand over a flattened device tree to Linux kernel"
- default n
help
Enable this option if you want U-Boot to hand over a flattened
device tree to the kernel. According to UHI register $a0 will be set
config MIPS_INIT_STACK_IN_SRAM
bool
- default n
help
Select this if the initial stack frame could be setup in SRAM.
Normally the initial stack frame is set up in DRAM which is often
config MIPS_SRAM_INIT
bool
- default n
depends on MIPS_INIT_STACK_IN_SRAM
help
Select this if the SRAM for initial stack needs to be initialized
so if you know the cache configuration for your system at compile
time it would be beneficial to configure it.
-config MIPS_L1_CACHE_SHIFT_4
- bool
-
-config MIPS_L1_CACHE_SHIFT_5
- bool
-
-config MIPS_L1_CACHE_SHIFT_6
- bool
-
-config MIPS_L1_CACHE_SHIFT_7
- bool
-
-config MIPS_L1_CACHE_SHIFT
- int
- default "7" if MIPS_L1_CACHE_SHIFT_7
- default "6" if MIPS_L1_CACHE_SHIFT_6
- default "5" if MIPS_L1_CACHE_SHIFT_5
- default "4" if MIPS_L1_CACHE_SHIFT_4
- default "5"
-
config MIPS_L2_CACHE
bool
help
config MIPS_INSERT_BOOT_CONFIG
bool
- default n
help
Enable this to insert some board-specific boot configuration in
the U-Boot binary at offset 0x10.
# endif
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
nop
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
#ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__
-#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
-
-/*
- * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
- * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
- * of ARCH_DMA_MINALIGN for now.
- */
-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#ifndef __ASSEMBLY__
/**
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac0 \n" \
- " .set pop \n" \
- : "=r" (mflo0)); \
+ " .set pop \n" \
+ : "=r" (mflo0)); \
mflo0; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac1 \n" \
- " .set pop \n" \
- : "=r" (mflo1)); \
+ " .set pop \n" \
+ : "=r" (mflo1)); \
mflo1; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac2 \n" \
- " .set pop \n" \
- : "=r" (mflo2)); \
+ " .set pop \n" \
+ : "=r" (mflo2)); \
mflo2; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac3 \n" \
- " .set pop \n" \
- : "=r" (mflo3)); \
+ " .set pop \n" \
+ : "=r" (mflo3)); \
mflo3; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac0 \n" \
- " .set pop \n" \
- : "=r" (mfhi0)); \
+ " .set pop \n" \
+ : "=r" (mfhi0)); \
mfhi0; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac1 \n" \
- " .set pop \n" \
- : "=r" (mfhi1)); \
+ " .set pop \n" \
+ : "=r" (mfhi1)); \
mfhi1; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac2 \n" \
- " .set pop \n" \
- : "=r" (mfhi2)); \
+ " .set pop \n" \
+ : "=r" (mfhi2)); \
mfhi2; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac3 \n" \
- " .set pop \n" \
- : "=r" (mfhi3)); \
+ " .set pop \n" \
+ : "=r" (mfhi3)); \
mfhi3; \
})
void arch_lmb_reserve(struct lmb *lmb)
{
- ulong sp;
-
- sp = arch_get_sp();
- debug("## Current stack ends at 0x%08lx\n", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= 4096;
- lmb_reserve(lmb, sp, gd->ram_top - sp);
+ arch_lmb_reserve_generic(lmb, arch_get_sp(), gd->ram_top, 4096);
}
static void linux_cmdline_init(void)
config SOC_BMIPS_BCM3380
bool "BMIPS BCM3380 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6318
bool "BMIPS BCM6318 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6338
bool "BMIPS BCM6338 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6348
bool "BMIPS BCM6348 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6368
bool "BMIPS BCM6368 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6362
bool "BMIPS BCM6362 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
config SOC_BMIPS_BCM6838
bool "BMIPS BCM6838 family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
void sdram_init(void);
#endif /* __JZ4780_DRAM_H__ */
-
menu "MediaTek MIPS platforms"
depends on ARCH_MTMIPS
+config SYS_VENDOR
+ default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
+
config SYS_MALLOC_F_LEN
default 0x1000
config SOC_MT7620
bool "MT7620"
- select MIPS_L1_CACHE_SHIFT_5
+ select SYS_CACHE_SHIFT_5
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select PINCTRL_MT7620
select MT7620_SERIAL
config SOC_MT7628
bool "MT7628"
- select MIPS_L1_CACHE_SHIFT_5
+ select SYS_CACHE_SHIFT_5
select MIPS_INIT_STACK_IN_SRAM
select MIPS_SRAM_INIT
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select SPL_OF_CONTROL if SPL_DM
select SPL_SIMPLE_BUS if SPL_DM
select SPL_DM_SERIAL if SPL_DM
- select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
+ select SPL_CLK if SPL_DM && SPL_SERIAL
select SPL_SYSRESET if SPL_DM
select SPL_OF_LIBFDT if SPL_OF_CONTROL
help
default 6 if CPU_FREQ_600MHZ
default 7 if CPU_FREQ_620MHZ
-source "board/mediatek/mt7620/Kconfig"
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
+
+config SYS_BOARD
+ string "Board name"
+ default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
endif
void mtmips_spl_serial_init(void)
{
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
#if CONFIG_CONS_INDEX == 1
clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M,
UARTF_MODE_UARTF_GPIO << UARTF_SHARE_MODE_S);
#endif
-#endif /* CONFIG_SPL_SERIAL_SUPPORT */
+#endif /* CONFIG_SPL_SERIAL */
}
config BOARD_VOCORE2
bool "VoCore2"
- select SPL_SERIAL_SUPPORT
+ select SPL_SERIAL
select SPL_UART2_SPIS_PINMUX
help
VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM
config SPL_UART2_SPIS_PINMUX
bool "Use alternative pinmux for UART2 in SPL stage"
- depends on SPL_SERIAL_SUPPORT
- default n
+ depends on SPL_SERIAL
help
Select this if the UART2 of your board is connected to GPIO 16/17
(shared with SPIS) rather than the usual GPIO 20/21.
+config SYS_BOARD
+ string "Board name"
+ default "mt7628" if BOARD_MT7628_RFB
+
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "mt7628" if BOARD_MT7628_RFB
+
source "board/gardena/smart-gateway-mt7688/Kconfig"
-source "board/mediatek/mt7628/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
source "board/vocore/vocore2/Kconfig"
.set noreorder
LEAF(mips_sram_init)
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* Setup CPU PLL */
li t0, DELAY_USEC(1000000)
li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
bnez a1, 3b
nop
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
jr ra
nop
void mtmips_spl_serial_init(void)
{
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
#if CONFIG_CONS_INDEX == 1
1 << SPIS_MODE_S);
#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
#endif /* CONFIG_CONS_INDEX */
-#endif /* CONFIG_SPL_SERIAL_SUPPORT */
+#endif /* CONFIG_SPL_SERIAL */
}
{
spl_init();
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
/*
* mtmips_spl_serial_init() is useful if debug uart is enabled,
* or DM based serial is not enabled.
config SOC_PIC32MZDA
bool "Microchip PIC32MZ[DA] family"
- select MIPS_L1_CACHE_SHIFT_4
+ select SYS_CACHE_SHIFT_4
select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
config SYS_ICACHE_OFF
bool "Do not enable icache"
- default n
help
Do not enable instruction cache in U-Boot.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
- default n
help
Do not enable data cache in U-Boot.
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
-#define BOARD_ID_FAMILY_MASK 0xfff000
-#define BOARD_ID_FAMILY_V5 0x556000
-#define BOARD_ID_FAMILY_K7 0x74b000
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
move $lp, $r11
ret
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
ret
#endif
-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
-#define BOARD_ID_FAMILY_MASK 0xfff000
-#define BOARD_ID_FAMILY_V5 0x556000
-#define BOARD_ID_FAMILY_K7 0x74b000
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
ret
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
.globl lowlevel_init
lowlevel_init:
li $r8, (CONFIG_DEBUG_LED)
swi $r7, [$r8]
ret
-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
#define WD_ENABLE 0x1
! Turn off the watchdog, according to Faraday FTWDT010 spec
- li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
lwi $p1, [$p0] ! Get the config of WD
andi $p1, $p1, 0x1f ! Wipe out useless bits
li $r0, ~WD_ENABLE
*/
#define ENA_DCAC 2UL
#define DIS_DCAC ~ENA_DCAC
-#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
+#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
jal mem_init
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
jal lowlevel_init
/*
* gp = ~VMA for burn mode
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 1 ! Determine interruption type
- bal do_interruption
+ bal do_interruption
.align 5
tlb_not_present:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 2 ! Determine interruption type
- bal do_interruption
+ bal do_interruption
.align 5
tlb_misc:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 3 ! Determine interruption type
- bal do_interruption
+ bal do_interruption
.align 5
tlb_vlpt_miss:
extern void udc_disconnect(void);
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
+#ifdef CONFIG_SUPPORT_PASSING_ATAGS
# define BOOTM_ENABLE_TAGS 1
#else
# define BOOTM_ENABLE_TAGS 0
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
+#ifdef CONFIG_SUPPORT_PASSING_ATAGS
static void setup_start_tag(struct bd_info *bd);
# ifdef CONFIG_SETUP_MEMORY_TAGS
static void setup_end_tag(struct bd_info *bd);
static struct tag *params;
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+#endif /* CONFIG_SUPPORT_PASSING_ATAGS */
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
}
#endif
} else if (BOOTM_ENABLE_TAGS) {
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
+#ifdef CONFIG_SUPPORT_PASSING_ATAGS
setup_start_tag(bd);
#ifdef CONFIG_SERIAL_TAG
setup_serial_tag(¶ms);
#endif
}
cleanup_before_linux();
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
theKernel(0, machid, (unsigned long)images->ft_addr);
else
theKernel(0, machid, bd->bi_boot_params);
return 1;
}
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
+#ifdef CONFIG_SUPPORT_PASSING_ATAGS
static void setup_start_tag(struct bd_info *bd)
{
params = (struct tag *)bd->bi_boot_params;
params->hdr.size = 0;
}
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+#endif /* CONFIG_SUPPORT_PASSING_ATAGS */
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("move %0, $sp" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
/*
* icache and dcache configuration used only for start.S.
#include <image.h>
#include <irq_func.h>
#include <log.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
return 1;
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
prompt "Target select"
optional
-config TARGET_MPC8349EMDS
- bool "Support MPC8349EMDS"
- select ARCH_MPC8349
- select BOARD_EARLY_INIT_F
- select SYS_FSL_DDR
- select SYS_FSL_DDR_BE
- select SYS_FSL_HAS_DDR2
-
-config TARGET_MPC8349EMDS_SDRAM
- bool "Support MPC8349EMDS_SDRAM"
- select ARCH_MPC8349
- select BOARD_EARLY_INIT_F
- select SYS_FSL_DDR
- select SYS_FSL_DDR_BE
- select SYS_FSL_HAS_DDR2
-
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
select ARCH_MPC837X
config MPC83XX_SDHC_SUPPORT
bool
-config MPC83XX_SATA_SUPPORT
+config MPC83XX_SATA
bool
config MPC83XX_SECOND_I2C
config ARCH_MPC830X
bool
select MPC83XX_SDHC_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8308
bool
select MPC83XX_PCI_SUPPORT
select MPC83XX_TSEC1_SUPPORT
select MPC83XX_TSEC2_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8313
bool
bool
select MPC83XX_QUICC_ENGINE
select MPC83XX_PCI_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC834X
bool
-
-config ARCH_MPC8349
- bool
- select ARCH_MPC834X
- select MPC83XX_PCI_SUPPORT
- select MPC83XX_TSEC1_SUPPORT
- select MPC83XX_TSEC2_SUPPORT
- select MPC83XX_LDP_PIN
- select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8360
bool
select MPC83XX_PCI_SUPPORT
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC837X
bool
select MPC83XX_PCIE1_SUPPORT
select MPC83XX_PCIE2_SUPPORT
select MPC83XX_SDHC_SUPPORT
- select MPC83XX_SATA_SUPPORT
+ select MPC83XX_SATA
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
select FSL_ELBC
config SYS_IMMR
source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
-menu "Legacy options"
-
-if ARCH_MPC8349
-
-#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
-choice
- prompt "PMC slot configuration"
-
-config PCI_ALL_PCI1
- bool "All PMC slots on PCI1"
-
-config PCI_ONE_PCI1
- bool "First PMC1 on PCI1"
-
-config PCI_TWO_PCI1
- bool "First two PMC1 on PCI1"
-
-endchoice
-
-config PCI_64BIT
- bool "PMC2 is 64bit"
-
-endif
-
-endmenu
-
config FSL_ELBC
bool
-source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
-obj-y += ecc.o
+obj-$(CONFIG_DDR_ECC_CMD) += ecc.o
ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
endif
#include <mpc83xx.h>
#include <command.h>
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
" - writes pattern injecting errors with word access\n"
" - writes pattern with word access, generates error\n"
" - disables injects\n" " - re-inits memory");
-#endif
config BR0_PORTSIZE_32BIT
depends on !BR0_MACHINE_FCM
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit"
endchoice
bool "GPCM"
config BR0_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM"
config BR0_MACHINE_SDRAM
- depends on ARCH_MPC8349 || ARCH_MPC8360
+ depends on ARCH_MPC8360
bool "SDRAM"
config BR0_MACHINE_UPMA
config BR1_PORTSIZE_32BIT
depends on !BR1_MACHINE_FCM
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit"
endchoice
bool "GPCM"
config BR1_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM"
config BR1_MACHINE_SDRAM
- depends on ARCH_MPC8349 || ARCH_MPC8360
+ depends on ARCH_MPC8360
bool "SDRAM"
config BR1_MACHINE_UPMA
config BR2_PORTSIZE_32BIT
depends on !BR2_MACHINE_FCM
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit"
endchoice
bool "GPCM"
config BR2_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM"
config BR2_MACHINE_SDRAM
- depends on ARCH_MPC8349 || ARCH_MPC8360
+ depends on ARCH_MPC8360
bool "SDRAM"
config BR2_MACHINE_UPMA
config BR3_PORTSIZE_32BIT
depends on !BR3_MACHINE_FCM
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit"
endchoice
bool "GPCM"
config BR3_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM"
config BR3_MACHINE_SDRAM
- depends on ARCH_MPC8349 || ARCH_MPC8360
+ depends on ARCH_MPC8360
bool "SDRAM"
config BR3_MACHINE_UPMA
config BR4_PORTSIZE_32BIT
depends on !BR4_MACHINE_FCM
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit"
endchoice
bool "GPCM"
config BR4_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM"
config BR4_MACHINE_SDRAM
- depends on ARCH_MPC8349 || ARCH_MPC8360
+ depends on ARCH_MPC8360
bool "SDRAM"
config BR4_MACHINE_UPMA
config HID2_IWLCK_2
bool "Way 0 through 2 locked"
-if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+if ARCH_MPC8360 || ARCH_MPC8379
config HID2_IWLCK_3
bool "Way 0 through 3 locked"
config HID2_DWLCK_2
bool "Way 0 through 2 locked"
-if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+if ARCH_MPC8360 || ARCH_MPC8379
config HID2_DWLCK_3
bool "Way 0 through 3 locked"
bool "1 : 1"
config LBMC_CLOCK_MODE_1_2
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360 || ARCH_MPC837X
bool "1 : 2"
endchoice
bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360 || ARCH_MPC837X
bool "1 : 1"
endchoice
-if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
+if !ARCH_MPC8313 && !ARCH_MPC832X
choice
prompt "System PLL VCO division"
bool "6 : 1"
config SYSTEM_PLL_FACTOR_7_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "7 : 1"
config SYSTEM_PLL_FACTOR_8_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "8 : 1"
config SYSTEM_PLL_FACTOR_9_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "9 : 1"
config SYSTEM_PLL_FACTOR_10_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "10 : 1"
config SYSTEM_PLL_FACTOR_11_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "11 : 1"
config SYSTEM_PLL_FACTOR_12_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "12 : 1"
config SYSTEM_PLL_FACTOR_13_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "13 : 1"
config SYSTEM_PLL_FACTOR_14_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "14 : 1"
config SYSTEM_PLL_FACTOR_15_1
- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ depends on ARCH_MPV8360 || ARCH_MPC837X
bool "15 : 1"
config SYSTEM_PLL_FACTOR_16_1
- depends on ARCH_MPC8349 || ARCH_MPV8360
+ depends on ARCH_MPV8360
bool "16 : 1"
endchoice
endchoice
-if ARCH_MPC8349
-
-choice
- prompt "PCI 64-bit mode"
-
-config PCI_64BIT_MODE_DISABLE
- bool "Disabled"
-
-config PCI_64BIT_MODE_ENABLE
- bool "Enabled"
-
-endchoice
-
-endif
-
choice
prompt "PCI internal arbiter 1 mode"
endchoice
-if ARCH_MPC8349
-
-choice
- prompt "PCI internal arbiter 2 mode"
-
-config PCI_INT_ARBITER2_DISABLE
- bool "Disabled"
-
-config PCI_INT_ARBITER2_ENABLE
- bool "Enabled"
-
-endchoice
-
-endif
-
if ARCH_MPC8360
choice
depends on MPC83XX_PCI_SUPPORT
bool "PCI1"
-config BOOT_ROM_INTERFACE_PCI2
- depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
- bool "PCI2"
-
config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
depends on ARCH_MPC837X
bool "PCI2"
bool "Local bus GPCM - 16-bit ROM"
config BOOT_ROM_INTERFACE_GPCM_32BIT
- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360 || ARCH_MPC837X
bool "Local bus GPCM - 32-bit ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "Local bus NAND Flash- 8-bit small page ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "Local bus NAND Flash- 8-bit large page ROM"
endchoice
prompt "TSEC1 mode"
config TSEC1_MODE_MII
- depends on !ARCH_MPC8349
bool "MII"
config TSEC1_MODE_RMII
- depends on ARCH_MPC831X && !ARCH_MPC8349
+ depends on ARCH_MPC831X
bool "RMII"
config TSEC1_MODE_RGMII
depends on ARCH_MPC831X || ARCH_MPC837X
bool "RTBI"
-config TSEC1_MODE_GMII
- depends on ARCH_MPC8349
- bool "GMII"
-
-config TSEC1_MODE_TBI
- depends on ARCH_MPC8349
- bool "TBI"
-
config TSEC1_MODE_SGMII
depends on ARCH_MPC831X || ARCH_MPC837X
bool "SGMII"
prompt "TSEC2 mode"
config TSEC2_MODE_MII
- depends on !ARCH_MPC8349
bool "MII"
config TSEC2_MODE_RMII
- depends on ARCH_MPC831X && !ARCH_MPC8349
+ depends on ARCH_MPC831X
bool "RMII"
config TSEC2_MODE_RGMII
depends on ARCH_MPC831X || ARCH_MPC837X
bool "RTBI"
-config TSEC2_MODE_GMII
- depends on ARCH_MPC8349
- bool "GMII"
-
-config TSEC2_MODE_TBI
- depends on ARCH_MPC8349
- bool "TBI"
-
config TSEC2_MODE_SGMII
depends on ARCH_MPC831X || ARCH_MPC837X
bool "SGMII"
endif
-if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
+if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
choice
prompt "LALE timing"
config SYSTEM_PLL_VCO_DIV
int
- default 0 if ARCH_MPC8349 || ARCH_MPC832X
+ default 0 if ARCH_MPC832X
default 2 if ARCH_MPC8313
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
hex
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
default 0x4 if BOOT_ROM_INTERFACE_PCI1
- default 0x8 if BOOT_ROM_INTERFACE_PCI2
default 0x8 if BOOT_ROM_INTERFACE_ESDHC
default 0xc if BOOT_ROM_INTERFACE_SPI
default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
default 0x0 if !MPC83XX_TSEC1_SUPPORT
default 0x0 if TSEC1_MODE_MII
default 0x1 if TSEC1_MODE_RMII
- default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
- default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
+ default 0x3 if TSEC1_MODE_RGMII
+ default 0x5 if TSEC1_MODE_RTBI
default 0x6 if TSEC1_MODE_SGMII
- default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
- default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
- default 0x2 if TSEC1_MODE_GMII
- default 0x3 if TSEC1_MODE_TBI
config TSEC2_MODE
hex
default 0x0 if !MPC83XX_TSEC2_SUPPORT
default 0x0 if TSEC2_MODE_MII
default 0x1 if TSEC2_MODE_RMII
- default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
- default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
+ default 0x3 if TSEC2_MODE_RGMII
+ default 0x5 if TSEC2_MODE_RTBI
default 0x6 if TSEC2_MODE_SGMII
- default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
- default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
- default 0x2 if TSEC2_MODE_GMII
- default 0x3 if TSEC2_MODE_TBI
config SECONDARY_DDR_IO
int
config PCI_64BIT_MODE
int
- default 0 if !ARCH_MPC8349
- default 0 if PCI_64BIT_MODE_DISABLE
- default 1 if PCI_64BIT_MODE_ENABLE
+ default 0
config PCI_INT_ARBITER1
int
config PCI_INT_ARBITER2
int
- default 0 if !ARCH_MPC8349
- default 0 if PCI_INT_ARBITER2_DISABLE
- default 1 if PCI_INT_ARBITER2_ENABLE
+ default 0
config PCI_CLOCK_OUTPUT_DRIVE
int
-#ifdef CONFIG_ARCH_MPC8349
-#define TSEC1_MODE_SHIFT 17
-#define TSEC2_MODE_SHIFT 19
-#else
-#define TSEC1_MODE_SHIFT 18
-#define TSEC2_MODE_SHIFT 21
-#endif
-
#define CONFIG_SYS_HRCW_LOW (\
(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
- (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
- (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
+ (CONFIG_TSEC1_MODE << (31 - 18)) |\
+ (CONFIG_TSEC2_MODE << (31 - 21)) |\
(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
(CONFIG_LALE_TIMING << (31 - 29)) |\
endif
-if ARCH_MPC8349
-
-choice
- prompt "TSEC1 emergency priority"
-
-config SPCR_TSEC1EP_UNSET
- bool "Don't set value"
-
-config SPCR_TSEC1EP_0
- bool "Level 0 (lowest priority)"
-
-config SPCR_TSEC1EP_1
- bool "Level 1"
-
-config SPCR_TSEC1EP_2
- bool "Level 2"
-
-config SPCR_TSEC1EP_3
- bool "Level 3 (highest priority)"
-
-endchoice
-
-choice
- prompt "TSEC2 emergency priority"
-
-config SPCR_TSEC2EP_UNSET
- bool "Don't set value"
-
-config SPCR_TSEC2EP_0
- bool "Level 0 (lowest priority)"
-
-config SPCR_TSEC2EP_1
- bool "Level 1"
-
-config SPCR_TSEC2EP_2
- bool "Level 2"
-
-config SPCR_TSEC2EP_3
- bool "Level 3 (highest priority)"
-
-endchoice
-
-endif
-
config SPCR_OPT
hex
default 0x0 if SPCR_OPT_UNSET
#endif
};
-#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-
-/* private structure for mpc83xx pcie hose */
-static struct mpc83xx_pcie_priv {
- u8 index;
-} pcie_priv[PCIE_MAX_BUSES] = {
- {
- /* pcie controller 1 */
- .index = 0,
- },
- {
- /* pcie controller 2 */
- .index = 1,
- },
-};
-
-static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
-{
- int bus = PCI_BUS(dev) - hose->first_busno;
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
- pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
- struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
- u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
- u32 dev_base = bus << 24 | devfn << 16;
-
- if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
- return -1;
- /*
- * Workaround for the HW bug: for Type 0 configure transactions the
- * PCI-E controller does not check the device number bits and just
- * assumes that the device number bits are 0.
- */
- if (devfn & 0xf8)
- return -1;
-
- out_le32(&out_win->tarl, dev_base);
- return 0;
-}
-
-#define cfg_read(val, addr, type, op) \
- do { *val = op((type)(addr)); } while (0)
-#define cfg_write(val, addr, type, op) \
- do { op((type *)(addr), (val)); } while (0)
-
-#define cfg_read_err(val) do { *val = -1; } while (0)
-#define cfg_write_err(val) do { } while (0)
-
-#define PCIE_OP(rw, size, type, op) \
-static int pcie_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, \
- type val) \
-{ \
- int ret; \
- \
- ret = mpc83xx_pcie_remap_cfg(hose, dev); \
- if (ret) { \
- cfg_##rw##_err(val); \
- return ret; \
- } \
- cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
- return 0; \
-}
-
-PCIE_OP(read, byte, u8 *, in_8)
-PCIE_OP(read, word, u16 *, in_le16)
-PCIE_OP(read, dword, u32 *, in_le32)
-PCIE_OP(write, byte, u8, out_8)
-PCIE_OP(write, word, u16, out_le16)
-PCIE_OP(write, dword, u32, out_le32)
-
-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
- u8 link)
-{
- extern void disable_addr_trans(void); /* start.S */
- static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
- struct pci_controller *hose = &pcie_hose[bus];
- int i;
-
- /*
- * There are no spare BATs to remap all PCI-E windows for U-Boot, so
- * disable translations. In general, this is not great solution, and
- * that's why we don't register PCI-E hoses by default.
- */
- disable_addr_trans();
-
- for (i = 0; i < 2; i++, reg++) {
- if (reg->size == 0)
- break;
-
- hose->regions[i] = *reg;
- hose->region_count++;
- }
-
- i = hose->region_count++;
- hose->regions[i].bus_start = 0;
- hose->regions[i].phys_start = 0;
- hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
- i = hose->region_count++;
- hose->regions[i].bus_start = CONFIG_SYS_IMMR;
- hose->regions[i].phys_start = CONFIG_SYS_IMMR;
- hose->regions[i].size = 0x100000;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
- hose->first_busno = pci_last_busno() + 1;
- hose->last_busno = 0xff;
-
- hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
-
- hose->priv_data = &pcie_priv[bus];
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- if (!link)
- hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
-
- pci_register_hose(hose);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-}
-
-#else
-
-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
- u8 link) {}
-
-#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
-
int get_pcie_clk(int index)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
printf("link\n");
else
printf("No link\n");
-
- mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
}
/*
#endif
debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
-#if defined(CONFIG_DDR_2T_TIMING)
- /*
- * Enable 2T timing by setting sdram_cfg[16].
- */
- sdram_cfg |= SDRAM_CFG_2T_EN;
-#endif
/* Enable controller, and GO! */
ddr->sdram_cfg = sdram_cfg;
sync();
pattern[0] = 0xdeadbeef;
pattern[1] = 0xdeadbeef;
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
- dma_meminit(pattern[0], dram_size);
-#else
debug("ddr init: CPU FP write method\n");
size = dram_size;
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
sync();
-#endif
t_end = get_tbms();
icache_disable();
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
-#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
*/
.long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
-
- .align 2
-
.globl enable_addr_trans
enable_addr_trans:
/* enable address translation */
bool "Support MPC8548CDS"
select ARCH_MPC8548
select FSL_VIA
+ select SYS_CACHE_SHIFT_5
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005275
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004580
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004699
config ARCH_QEMU_E500
bool
+ select SYS_CACHE_SHIFT_5
config ARCH_T1024
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select E500MC
select E6500
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
imply CMD_NAND
imply CMD_REGINFO
imply FSL_SATA
+ imply ID_EEPROM
config ARCH_T4240
bool
select E500MC
select E6500
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
endif
obj-$(CONFIG_CPM2) += commproc.o
-obj-$(CONFIG_CPM2) += ether_fcc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_CORENET) += liodn.o
obj-$(CONFIG_MP) += mp.o
#include <config.h>
#include <common.h>
#include <cpu_func.h>
+#include <clock_legacy.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
+ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
#endif /* CONFIG_FSL_CORENET */
unsigned int i, core, nr_cores = cpu_numcores();
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * MPC8560 FCC Fast Ethernet
- * Copyright (c) 2003 Motorola,Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- */
-
-/*
- * MPC8560 FCC Fast Ethernet
- * Basic ET HW initialization and packet RX/TX routines
- *
- * This code will not perform the IO port configuration. This should be
- * done in the iop_conf_t structure specific for the board.
- *
- * TODO:
- * add a PHY driver to do the negotiation
- * reflect negotiation results in FPSMR
- * look for ways to configure the board specific stuff elsewhere, eg.
- * config_xxx.h or the board directory
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/cpm_85xx.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
-
-static struct ether_fcc_info_s
-{
- int ether_index;
- int proff_enet;
- ulong cpm_cr_enet_sblock;
- ulong cpm_cr_enet_page;
- ulong cmxfcr_mask;
- ulong cmxfcr_value;
-}
- ether_fcc_info[] =
-{
-#ifdef CONFIG_ETHER_ON_FCC1
-{
- 0,
- PROFF_FCC1,
- CPM_CR_FCC1_SBLOCK,
- CPM_CR_FCC1_PAGE,
- CONFIG_SYS_CMXFCR_MASK1,
- CONFIG_SYS_CMXFCR_VALUE1
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC2
-{
- 1,
- PROFF_FCC2,
- CPM_CR_FCC2_SBLOCK,
- CPM_CR_FCC2_PAGE,
- CONFIG_SYS_CMXFCR_MASK2,
- CONFIG_SYS_CMXFCR_VALUE2
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC3
-{
- 2,
- PROFF_FCC3,
- CPM_CR_FCC3_SBLOCK,
- CPM_CR_FCC3_PAGE,
- CONFIG_SYS_CMXFCR_MASK3,
- CONFIG_SYS_CMXFCR_VALUE3
-},
-#endif
-};
-
-/*---------------------------------------------------------------------*/
-
-/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
-#define PKT_MAXDMA_SIZE 1520
-
-/* The FCC stores dest/src/type, data, and checksum for receive packets. */
-#define PKT_MAXBUF_SIZE 1518
-#define PKT_MINBUF_SIZE 64
-
-/* Maximum input buffer size. Must be a multiple of 32. */
-#define PKT_MAXBLR_SIZE 1536
-
-#define TOUT_LOOP 1000000
-
-#define TX_BUF_CNT 2
-
-static uint rxIdx; /* index of the current RX buffer */
-static uint txIdx; /* index of the current TX buffer */
-
-/*
- * FCC Ethernet Tx and Rx buffer descriptors.
- * Provide for Double Buffering
- * Note: PKTBUFSRX is defined in net.h
- */
-
-typedef volatile struct rtxbd {
- cbd_t rxbd[PKTBUFSRX];
- cbd_t txbd[TX_BUF_CNT];
-} RTXBD;
-
-/* Good news: the FCC supports external BDs! */
-#ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
-#else
-#error "rtx must be 64-bit aligned"
-#endif
-
-#undef ET_DEBUG
-
-static int fec_send(struct eth_device *dev, void *packet, int length)
-{
- int i = 0;
- int result = 0;
-
- if (length <= 0) {
- printf("fec: bad packet size: %d\n", length);
- goto out;
- }
-
- for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
- printf("fec: tx buffer not ready\n");
- goto out;
- }
- }
-
- rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
- rtx.txbd[txIdx].cbd_datlen = length;
- rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
- BD_ENET_TX_TC | BD_ENET_TX_PAD);
-
- for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
- printf("fec: tx error\n");
- goto out;
- }
- }
-
-#ifdef ET_DEBUG
- printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
- printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
- for(i=0;i<(length/16 + 1);i++) {
- printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
- *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
- *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
- }
-#endif
-
- /* return only status bits */
- result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
- txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-out:
- return result;
-}
-
-static int fec_recv(struct eth_device* dev)
-{
- int length;
-
- for (;;)
- {
- if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
- length = rtx.rxbd[rxIdx].cbd_datlen;
-
- if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
- printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
- }
- else {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[rxIdx], length - 4);
- }
-
-
- /* Give the buffer back to the FCC. */
- rtx.rxbd[rxIdx].cbd_datlen = 0;
-
- /* wrap around buffer index when necessary */
- if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
- rxIdx = 0;
- }
- else {
- rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
- rxIdx++;
- }
- }
- return length;
-}
-
-
-static int fec_init(struct eth_device* dev, struct bd_info *bis)
-{
- struct ether_fcc_info_s * info = dev->priv;
- int i;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
- volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
- fcc_enet_t *pram_ptr;
- unsigned long mem_addr;
-
-#if 0
- mii_discover_phy();
-#endif
-
- /* 28.9 - (1-2): ioports have been set up already */
-
- /* 28.9 - (3): connect FCC's tx and rx clocks */
- cpm->im_cpm_mux.cmxuar = 0; /* ATM */
- cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
- info->cmxfcr_value;
-
- /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
- }
-
- /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
- } else if (info->ether_index == 1){
- cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
- } else if (info->ether_index == 2){
- cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
- }
-
- /* 28.9 - (6): FDSR: Ethernet Syn */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fdsr = 0xD555;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.fdsr = 0xD555;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.fdsr = 0xD555;
- }
-
- /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
- rxIdx = 0;
- txIdx = 0;
-
- /* Setup Receiver Buffer Descriptors */
- for (i = 0; i < PKTBUFSRX; i++)
- {
- rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx.rxbd[i].cbd_datlen = 0;
- rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
- }
- rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
- /* Setup Ethernet Transmitter Buffer Descriptors */
- for (i = 0; i < TX_BUF_CNT; i++)
- {
- rtx.txbd[i].cbd_sc = 0;
- rtx.txbd[i].cbd_datlen = 0;
- rtx.txbd[i].cbd_bufaddr = 0;
- }
- rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
- /* 28.9 - (7): initialize parameter ram */
- pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
-
- /* clear whole structure to make sure all reserved fields are zero */
- memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
-
- /*
- * common Parameter RAM area
- *
- * Allocate space in the reserved FCC area of DPRAM for the
- * internal buffers. No one uses this space (yet), so we
- * can do this. Later, we will add resource management for
- * this area.
- * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560
- * 0x9000 for MPC8541, MPC8555
- */
- mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
- pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
- pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
- /*
- * Set maximum bytes per receive buffer.
- * It must be a multiple of 32.
- */
- pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
- /* localbus SDRAM should be preferred */
- pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
- CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
- pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
- pram_ptr->fen_genfcc.fcc_rbdstat = 0;
- pram_ptr->fen_genfcc.fcc_rbdlen = 0;
- pram_ptr->fen_genfcc.fcc_rdptr = 0;
- /* localbus SDRAM should be preferred */
- pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
- CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
- pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
- pram_ptr->fen_genfcc.fcc_tbdstat = 0;
- pram_ptr->fen_genfcc.fcc_tbdlen = 0;
- pram_ptr->fen_genfcc.fcc_tdptr = 0;
-
- /* protocol-specific area */
- pram_ptr->fen_statbuf = 0x0;
- pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
- pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
- pram_ptr->fen_crcec = 0;
- pram_ptr->fen_alec = 0;
- pram_ptr->fen_disfc = 0;
- pram_ptr->fen_retlim = 15; /* Retry limit threshold */
- pram_ptr->fen_retcnt = 0;
- pram_ptr->fen_pper = 0;
- pram_ptr->fen_boffcnt = 0;
- pram_ptr->fen_gaddrh = 0;
- pram_ptr->fen_gaddrl = 0;
- pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
- /*
- * Set Ethernet station address.
- *
- * This is supplied in the board information structure, so we
- * copy that into the controller.
- * So far we have only been given one Ethernet address. We make
- * it unique by setting a few bits in the upper byte of the
- * non-static part of the address.
- */
-#define ea eth_get_ethaddr()
- pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
- pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
- pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
- pram_ptr->fen_ibdcount = 0;
- pram_ptr->fen_ibdstart = 0;
- pram_ptr->fen_ibdend = 0;
- pram_ptr->fen_txlen = 0;
- pram_ptr->fen_iaddrh = 0; /* disable hash */
- pram_ptr->fen_iaddrl = 0;
- pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
- /* pad pointer. use tiptr since we don't need a specific padding char */
- pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
- pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
- pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
-
-#if defined(ET_DEBUG)
- printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
- printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
- pram_ptr->fen_genfcc.fcc_rbase);
- printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
- pram_ptr->fen_genfcc.fcc_tbase);
-#endif
-
- /* 28.9 - (8)(9): clear out events in FCCE */
- /* 28.9 - (9): FCCM: mask all events */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fcce = ~0x0;
- cpm->im_cpm_fcc1.fccm = 0;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.fcce = ~0x0;
- cpm->im_cpm_fcc2.fccm = 0;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.fcce = ~0x0;
- cpm->im_cpm_fcc3.fccm = 0;
- }
-
- /* 28.9 - (10-12): we don't use ethernet interrupts */
-
- /* 28.9 - (13)
- *
- * Let's re-initialize the channel now. We have to do it later
- * than the manual describes because we have just now finished
- * the BD initialization.
- */
- cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
- info->cpm_cr_enet_sblock,
- 0x0c,
- CPM_CR_INIT_TRX) | CPM_CR_FLG;
- do {
- __asm__ __volatile__ ("eieio");
- } while (cp->cpcr & CPM_CR_FLG);
-
- /* 28.9 - (14): enable tx/rx in gfmr */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
- }
-
- return 1;
-}
-
-static void fec_halt(struct eth_device* dev)
-{
- struct ether_fcc_info_s * info = dev->priv;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
- /* write GFMR: disable tx/rx */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
- } else if(info->ether_index == 1) {
- cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
- } else if(info->ether_index == 2) {
- cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
- }
-}
-
-int fec_initialize(struct bd_info *bis)
-{
- struct eth_device* dev;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
- {
- dev = (struct eth_device*) malloc(sizeof *dev);
- memset(dev, 0, sizeof *dev);
-
- sprintf(dev->name, "FCC%d",
- ether_fcc_info[i].ether_index + 1);
- dev->priv = ðer_fcc_info[i];
- dev->init = fec_init;
- dev->halt = fec_halt;
- dev->send = fec_send;
- dev->recv = fec_recv;
-
- eth_register(dev);
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
- && defined(CONFIG_BITBANGMII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
- }
-
- return 1;
-}
-
-#endif
#include <common.h>
#include <cpu_func.h>
+#include <clock_legacy.h>
#include <ppc_asm.tmpl>
#include <asm/global_data.h>
#include <linux/compiler.h>
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
else
#endif
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
sys_info->freq_ddrbus = sys_info->freq_systembus;
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
{
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
- sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
}
#endif
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
-#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
_start_e500:
/* Enable debug exception */
li r1,MSR_DE
- mtmsr r1
+ mtmsr r1
/*
* If we got an ePAPR device tree pointer passed in as r3, we need that
.globl _start
_start:
.long 0x27051956 /* U-BOOT Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
- .align 4
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
li r0,0
-1: subi r4,r4,4
- stw r0,0(r4)
- cmplw r4,r3
+1: subi r4,r4,4
+ stw r0,0(r4)
+ cmplw r4,r3
bne 1b
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
config MPC866
bool "MPC866"
+ select SYS_CACHE_SHIFT_4
config MPC885
bool "MPC885"
+ select SYS_CACHE_SHIFT_4
endchoice
#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
-#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
*/
.text
.long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
*/
int cpu_eth_init(struct bd_info *bis)
{
-#if defined(CONFIG_ETHER_ON_FCC)
- fec_initialize(bis);
-#endif
-
#if defined(CONFIG_UEC_ETH)
uec_standard_init(bis);
#endif
*/
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-/*
- * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
- */
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
-#endif
-
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
#endif
#endif
-/* Check if boards need to enable FSL DMA engine for SDRAM init */
-#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
-#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
- ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-#define CONFIG_FSL_DMA
-#endif
-#endif
-
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_ESDHC_HC_BLK_ADDR
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
-#define LBCR_BMTPS 0x0000000F
-#define LBCR_BMTPS_SHIFT 0
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT 0
/* LCRR - Clock Ratio Register
*/
*/
typedef struct cpc_corenet {
- u32 cpccsr0; /* Config/status reg */
+ u32 cpccsr0; /* Config/status reg */
u32 res1;
u32 cpccfg0; /* Configuration register */
u32 res2;
#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
-#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
-#ifdef CONFIG_APUS_FAST_EXCEPT
-#define MSR_ MSR_ME|MSR_IP|MSR_RI
-#else
#define MSR_ MSR_ME|MSR_RI
-#endif
#ifndef CONFIG_E500
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
#else
#define MAS5 SPRN_MAS5
#define MAS6 SPRN_MAS6
#define MAS7 SPRN_MAS7
-#define MAS8 SPRN_MAS8
+#define MAS8 SPRN_MAS8
#if defined(CONFIG_MPC85xx)
#define DAR_DEAR DEAR
void arch_lmb_reserve(struct lmb *lmb)
{
phys_size_t bootm_size;
- ulong size, sp, bootmap_base;
+ ulong size, bootmap_base;
bootmap_base = env_get_bootm_low();
bootm_size = env_get_bootm_size();
lmb_reserve(lmb, base, bootm_size - size);
}
- /*
- * Booting a (Linux) kernel image
- *
- * Allocate space for command line and board info - the
- * address should be as high as possible within the reach of
- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
- * memory, which means far enough below the current stack
- * pointer.
- */
- sp = get_sp();
- debug("## Current stack ends at 0x%08lx\n", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= 4096;
- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp));
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
#ifdef CONFIG_MP
cpu_mp_lmb_reserve(lmb);
sync /* wait for dcbi's to get to ram */
#endif
blr
-
config TARGET_SIFIVE_UNMATCHED
bool "Support SiFive Unmatched Board"
+ select SYS_CACHE_SHIFT_6
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
+ select SYS_CACHE_SHIFT_6
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
config SYS_ICACHE_OFF
bool "Do not enable icache"
- default n
help
Do not enable instruction cache in U-Boot.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
- default n
help
Do not enable data cache in U-Boot.
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
+#include <asm/csr.h>
+
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID 0xf12
+
+#define V5_MCACHE_CTL_IC_EN_OFFSET 0
+#define V5_MCACHE_CTL_DC_EN_OFFSET 1
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
+#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
+
+#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+
/*
* cleanup_before_linux() is called just before we call linux
return 0;
}
+
+void harts_early_init(void)
+{
+ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+ unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+ csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
+
+ /*
+ * Check DC_COHEN_EN, if cannot write to mcache_ctl,
+ * we assume this bitmap not support L2 CM
+ */
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
+ /* Wait for DC_COHSTA bit be set */
+ while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ }
+ }
+}
#include <common.h>
#include <cpu.h>
#include <dm.h>
+#include <dm/lists.h>
#include <init.h>
#include <log.h>
#include <asm/encoding.h>
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
#include <linux/types.h>
enum sbi_ext_id {
-#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
-#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+};
+
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+ SBI_EXT_HSM_HART_SUSPEND,
+};
+
+enum sbi_hsm_hart_status {
+ SBI_HSM_HART_STATUS_STARTED = 0,
+ SBI_HSM_HART_STATUS_STOPPED,
+ SBI_HSM_HART_STATUS_START_PENDING,
+ SBI_HSM_HART_STATUS_STOP_PENDING,
+ SBI_HSM_HART_STATUS_SUSPEND_PENDING,
+ SBI_HSM_HART_STATUS_RESUME_PENDING,
+};
+
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
static void boot_prep_linux(bootm_headers_t *images)
{
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
announce_and_cleanup(fake);
if (!fake) {
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
(ulong)images->ft_addr, 0, 0);
{
return do_bootm_linux(flag, argc, argv, images);
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mv %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
fdt_addr_t addr;
fdt_size_t size;
int offset, node, err, rmem_offset;
- bool nomap = true;
char basename[32] = {0};
int bname_len;
int max_len = sizeof(basename);
log_err("failed to add reserved memory: %d\n", err);
return err;
}
- if (!fdt_getprop(src, node, "no-map", NULL))
- nomap = false;
- if (nomap) {
+ if (fdt_getprop(src, node, "no-map", NULL)) {
rmem_offset = fdt_node_offset_by_phandle(dst, phandle);
fdt_setprop_empty(dst, rmem_offset, "no-map");
}
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason: reason for reset
+ */
+void sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
return 0;
}
+int os_filesize(int fd)
+{
+ off_t size;
+
+ size = os_lseek(fd, 0, OS_SEEK_END);
+ if (size < 0)
+ return -errno;
+ if (os_lseek(fd, 0, OS_SEEK_SET) < 0)
+ return -errno;
+
+ return size;
+}
+
int os_read_file(const char *fname, void **bufp, int *sizep)
{
off_t size;
printf("Cannot open file '%s'\n", fname);
goto err;
}
- size = os_lseek(fd, 0, OS_SEEK_END);
+ size = os_filesize(fd);
if (size < 0) {
- printf("Cannot seek to end of file '%s'\n", fname);
- goto err;
- }
- if (os_lseek(fd, 0, OS_SEEK_SET) < 0) {
- printf("Cannot seek to start of file '%s'\n", fname);
+ printf("Cannot get file size of '%s'\n", fname);
goto err;
}
+
*bufp = os_malloc(size);
if (!*bufp) {
printf("Not enough memory to read file '%s'\n", fname);
return ret;
}
+int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep)
+{
+ void *ptr;
+ int size;
+ int ifd;
+
+ ifd = os_open(pathname, os_flags);
+ if (ifd < 0) {
+ printf("Cannot open file '%s'\n", pathname);
+ return -EIO;
+ }
+ size = os_filesize(ifd);
+ if (size < 0) {
+ printf("Cannot get file size of '%s'\n", pathname);
+ return -EIO;
+ }
+
+ ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0);
+ if (ptr == MAP_FAILED) {
+ printf("Can't map file '%s': %s\n", pathname, strerror(errno));
+ return -EPERM;
+ }
+
+ *bufp = ptr;
+ *sizep = size;
+
+ return 0;
+}
+
/* Restore tty state when we exit */
static struct termios orig_term;
static bool term_setup;
continue;
}
} else if (!strcmp(arg, "--rm_memory")) {
- ap++;
continue;
}
argv[argc++] = arg;
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Overlay test file
+ */
+
/dts-v1/;
/plugin/;
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Overlay test file
+ */
+
/dts-v1/;
/plugin/;
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Main sandbox devicetree
+ */
+
/dts-v1/;
#include <config.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* This is the common sandbox device-tree nodes. This is shared between sandbox
* and sandbox64 builds.
};
gpio_b: gpios@1 {
- u-boot,dm-pre-proper;
+ u-boot,dm-spl;
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <2>;
sandbox,gpio-count = <10>;
};
+ gpio-test {
+ u-boot,dm-spl;
+ compatible = "sandbox,gpio-test";
+ test-gpios = <&gpio_b 3 0>;
+ };
+
hexagon {
compatible = "demo-simple";
colour = "white";
#sound-dai-cells = <1>;
};
+ irq_sandbox: irq-sbox {
+ u-boot,dm-spl;
+ compatible = "sandbox,irq";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ irq-test {
+ u-boot,dm-spl;
+ compatible = "sandbox,irq-test";
+ interrupts-extended = <&irq_sandbox 3 0>;
+ };
+
lcd {
u-boot,dm-pre-proper;
compatible = "sandbox,lcd-sdl";
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Main sandbox64 devicetree
+ */
/dts-v1/;
#include <config.h>
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Devicetree file for running sandbox tests
+ *
+ * This includes lots of extra devices used by various tests.
+ *
+ * Note that SPL use the main sandbox.dts file
+ */
+
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
};
config {
+ testing-bool;
+ testing-int = <123>;
+ testing-str = "testing";
environment {
from_fdt = "yes";
fdt_env_path = "";
};
};
+ gpio-wdt {
+ gpios = <&gpio_a 7 0>;
+ compatible = "linux,wdt-gpio";
+ hw_margin_ms = <100>;
+ always-running;
+ };
+
mbox: mbox {
compatible = "sandbox,mbox";
#mbox-cells = <1>;
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
timebase-frequency = <2000000>;
- cpu-test1 {
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ reg = <0x1>;
timebase-frequency = <3000000>;
compatible = "sandbox,cpu_sandbox";
u-boot,dm-pre-reloc;
};
- cpu-test2 {
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ reg = <0x2>;
compatible = "sandbox,cpu_sandbox";
u-boot,dm-pre-reloc;
};
- cpu-test3 {
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ reg = <0x3>;
compatible = "sandbox,cpu_sandbox";
u-boot,dm-pre-reloc;
};
wdt0: wdt@0 {
compatible = "sandbox,wdt";
+ hw_margin_ms = <200>;
};
axi: axi@0 {
#else
#define ARCH_DMA_MINALIGN 16
#endif
-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#endif /* __SANDBOX_CACHE_H__ */
*
* @param dev device to use
* @param offset GPIO offset within bank
- * @param output 0 to set as input, 1 to set as output
+ * @param output 0 to set as input, 1 to set as output
* @return -1 on error, 0 if ok
*/
int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#ifndef __SANDBOX_IRQ_H
+#define __SANDBOX_IRQ_H
+
+/**
+ * struct sandbox_irq_priv - private data for this driver
+ *
+ * @count: Counts the number calls to the read_and_clear() method
+ * @pending: true if an interrupt is pending, else false
+ */
+struct sandbox_irq_priv {
+ int count;
+ bool pending;
+};
+
+#endif /* __SANDBOX_IRQ_H */
#include <env.h>
#include <image.h>
#include <asm/byteorder.h>
+#include <asm/global_data.h>
#include <asm/zimage.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SYS_DEBUG
static void hexdump(unsigned char *buf, int len)
{
/* does not return */
return 1;
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov r15, %0" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
config SMM_TSEG
bool
- default n
config SMM_TSEG_SIZE
hex
config X86_RESET_VECTOR
bool
- default n
select BINMAN
# The following options control where the 16-bit and 32-bit init lies
config FSP_USE_UPD
bool
depends on FSP_VERSION1
- default y
+ default y if !NORTHBRIDGE_INTEL_IVYBRIDGE
help
Most FSPs use UPD data region for some FSP customization. But there
are still some FSPs that might not even have UPD. For such FSPs,
config CACHE_MRC_BIN
bool
depends on HAVE_MRC
- default n
help
Enable caching for the memory reference code binary. This uses an
MTRR (memory type range register) to turn on caching for the section
config SMP
bool "Enable Symmetric Multiprocessing"
- default n
help
Enable use of more than one CPU in U-Boot and the Operating System
when loaded. Each CPU will be started up and information can be
config GENERATE_PIRQ_TABLE
bool "Generate a PIRQ table"
- default n
help
Generate a PIRQ routing table for this board. The PIRQ routing table
is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
config GENERATE_MP_TABLE
bool "Generate an MP (Multi-Processor) table"
- default n
help
Generate an MP (Multi-Processor) table for this board. The MP table
provides a way for the operating system to support for symmetric
config GENERATE_ACPI_TABLE
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
- default n
select QFW if QEMU
help
The Advanced Configuration and Power Interface (ACPI) specification
select INTEL_SOC
select INTEL_PMC
select TPL_X86_TSC_TIMER_NATIVE
- select SPL_PCH_SUPPORT
- select TPL_PCH_SUPPORT
+ select SPL_PCH
+ select TPL_PCH
select PCIEX_LENGTH_256MB
- select PCH_SUPPORT
+ select PCH
select P2SB
select SMP_AP_WORK
select INTEL_GMA_SWSMISCI
config APL_SPI_FLASH_BOOT
bool "Support booting with SPI-flash driver instead memory-mapped SPI"
select TPL_SPI_FLASH_SUPPORT
- select TPL_SPI_SUPPORT
+ select TPL_SPI
select TPL_DM_SPI
select TPL_DM_SPI_FLASH
help
ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
if (ret)
return log_msg_ret("no hostbridge PINCTRL", ret);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int root;
/* Get length of PCI Express Region */
#endif
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_hostbridge_ids[] = {
{ .compatible = "intel,apl-hostbridge" },
{ }
.inject_dsdt = southbridge_inject_dsdt,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_lpc_ids[] = {
{ .compatible = "intel,apl-lpc" },
{ }
.set_spi_protect = apl_set_spi_protect,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_pch_ids[] = {
{ .compatible = "intel,apl-pch" },
{ }
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
struct apl_pmc_plat *plat = dev_get_plat(dev);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
u32 base[6];
int size;
int ret;
.global_reset_set_enable = apl_global_reset_set_enable,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_pmc_ids[] = {
{ .compatible = "intel,apl-pmc" },
{ }
return 0;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_ns16550_serial_ids[] = {
{ .compatible = "intel,apl-ns16550" },
{ },
#include <asm/mtrr.h>
#include <asm/cb_sysinfo.h>
#include <asm/arch/timestamp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <dm/ofnode.h>
int arch_cpu_init(void)
{
mtrr_close(&state, true);
}
- if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
+ if (!ofnode_conf_read_bool("u-boot,no-apm-finalize")) {
/*
* Issue SMI to coreboot to lock down ME and registers
* when allowed via device tree
* MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing
*/
- movl $0x80000008, %eax /* Address sizes leaf */
+ movl $0x80000008, %eax /* Address sizes leaf */
cpuid
sub $32, %al
movzx %al, %eax
#endif
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id itss_ids[] = {
{ .compatible = "intel,itss", .data = X86_IRQT_ITSS },
{ }
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
struct p2sb_plat *plat = dev_get_plat(dev);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int ret;
u32 base[2];
static int p2sb_child_post_bind(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
- int ret;
- u32 pid;
-
- ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
- if (ret)
- return ret;
- pplat->pid = pid;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
+ int ret;
+ u32 pid;
+
+ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
+ if (ret)
+ return ret;
+ pplat->pid = pid;
+ }
return 0;
}
.set_hide = intel_p2sb_set_hide,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id p2sb_ids[] = {
{ .compatible = "intel,p2sb" },
{ }
config ENABLE_VMX
bool "Enable VMX for virtualization"
- default n
help
Virtual Machine Extensions are provided in many x86 CPUs. These
provide various facilities for allowing a host OS to provide an
hex
default 0xfff80000
-config FSP_USE_UPD
- bool
- default n
-
config FSP_BROKEN_HOB
bool
default y
*/
#include <common.h>
-#include <version.h>
#include <asm/arch/mrc.h>
#include <asm/arch/msg_port.h>
#include "mrc_util.h"
{
ENTERFN();
- DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
- U_BOOT_DATE, U_BOOT_TIME);
+ DPF(D_INFO, "MRC Version %04x\n", MRC_VERSION);
/* Set up the data structures used by mrc_mem_init() */
mrc_adjust_params(mrc_params);
#define __X86_CACHE_H__
/*
- * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
- * use 64-bytes, a safe default for x86.
+ * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment.
*/
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#endif
-
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
static inline void wbinvd(void)
#include <dm/uclass-internal.h>
#include <mapmem.h>
#include <serial.h>
-#include <version.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_table.h>
.globl __idt_handler
__idt_handler:
pushal
- movb $0, %al /* This instruction gets modified */
- ljmp $0, $__interrupt_handler_16bit
+ movb $0, %al /* This instruction gets modified */
+ ljmp $0, $__interrupt_handler_16bit
.globl __idt_handler_size
__idt_handler_size:
.long . - __idt_handler
return boot_jump_linux(images);
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+#if CONFIG_IS_ENABLED(X86_64)
+ ret = gd->start_addr_sp;
+#else
+ asm("mov %%esp, %0" : "=r"(ret) : );
+#endif
+
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
UCLASS_DRIVER(lpc) = {
.id = UCLASS_LPC,
.name = "lpc",
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
* for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
* the auto allocation (after relocation).
*/
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id tpl_fake_pci_ids[] = {
{ .compatible = "pci-x86" },
{ }
config SYS_ICACHE_OFF
bool "Do not enable icache"
- default n
help
Do not enable instruction cache in U-Boot.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
- default n
help
Do not enable data cache in U-Boot.
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
-
-
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
-
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (1 byte aligned)
.endif
.endm // xchal_ncp_load
-
-
#define XCHAL_NCP_NUM_ATMPS 2
-
#define XCHAL_SA_NUM_ATMPS 2
#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
-
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
-
-
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
-
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
-
-
/*
* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
#define XCHAL_NCP_NUM_ATMPS 1
-
-
#define XCHAL_SA_NUM_ATMPS 1
#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
-
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI 0
+#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
/*----------------------------------------------------------------------
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
-
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
-
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
#define XCHAL_SA_NUM_ATMPS 1
#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
-
.endm
-
.macro ___flush_invalidate_dcache_range ar as at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___flush_invalidate_dcache_page ar as
#if XCHAL_DCACHE_SIZE
#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
#endif /* _XTENSA_SPECREG_H */
-
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += cache.o misc.o relocate.o time.o
+obj-y += cache.o misc.o relocate.o time.o
return 1;
}
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, a1" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
+}
memset((void *)&__bss_start, 0x00, len);
return 0;
}
-
#ifdef CONFIG_SPL_RAM_SUPPORT
BOOT_DEVICE_RAM,
#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
BOOT_DEVICE_MMC1,
#endif
};
+++ /dev/null
-if TARGET_FLEA3
-
-config SYS_BOARD
- default "flea3"
-
-config SYS_VENDOR
- default "CarMediaLab"
-
-config SYS_SOC
- default "mx35"
-
-config SYS_CONFIG_NAME
- default "flea3"
-
-endif
+++ /dev/null
-FLEA3 BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/CarMediaLab/flea3/
-F: include/configs/flea3.h
-F: configs/flea3_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y := flea3.o
-obj-y += lowlevel_init.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <env.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux-mx35.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-#include <fdt_support.h>
-#include <mtd_node.h>
-#include <jffs2/load_kernel.h>
-
-#ifndef CONFIG_BOARD_EARLY_INIT_F
-#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
-#endif
-
-#define CCM_CCMR_CONFIG 0x003F4208
-
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-
-static inline void dram_wait(unsigned int count)
-{
- volatile unsigned int wait = count;
-
- while (wait--)
- ;
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-static void board_setup_sdram(void)
-{
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-
- /* Initialize with default values both CSD0/1 */
- writel(0x2000, &esdc->esdctl0);
- writel(0x2000, &esdc->esdctl1);
-
-
- mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
- 13, 10, 2, 0x8080);
-}
-
-static void setup_iomux_uart3(void)
-{
- static const iomux_v3_cfg_t uart3_pads[] = {
- MX35_PAD_RTS2__UART3_RXD_MUX,
- MX35_PAD_CTS2__UART3_TXD_MUX,
- };
-
- imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
-}
-
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
- static const iomux_v3_cfg_t i2c_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
-
- NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-
-static void setup_iomux_spi(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
- MX35_PAD_CSPI1_MISO__CSPI1_MISO,
- MX35_PAD_CSPI1_SS0__CSPI1_SS0,
- MX35_PAD_CSPI1_SS1__CSPI1_SS1,
- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* GPIO used to power off ethernet */
- MX35_PAD_STXFS4__GPIO2_31,
- };
-
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-int board_early_init_f(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- /* setup GPIO3_1 to set HighVCore signal */
- imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
- gpio_direction_output(65, 1);
-
- /* initialize PLL and clock configuration */
- writel(CCM_CCMR_CONFIG, &ccm->ccmr);
-
- writel(CCM_MPLL_532_HZ, &ccm->mpctl);
- writel(CCM_PPLL_300_HZ, &ccm->ppctl);
-
- /* Set the core to run at 532 Mhz */
- writel(0x00001000, &ccm->pdr0);
-
- /* Set-up RAM */
- board_setup_sdram();
-
- /* enable clocks */
- writel(readl(&ccm->cgr0) |
- MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDIO_MASK |
- MXC_CCM_CGR0_EPIT1_MASK,
- &ccm->cgr0);
-
- writel(readl(&ccm->cgr1) |
- MXC_CCM_CGR1_FEC_MASK |
- MXC_CCM_CGR1_GPIO1_MASK |
- MXC_CCM_CGR1_GPIO2_MASK |
- MXC_CCM_CGR1_GPIO3_MASK |
- MXC_CCM_CGR1_I2C1_MASK |
- MXC_CCM_CGR1_I2C2_MASK |
- MXC_CCM_CGR1_I2C3_MASK,
- &ccm->cgr1);
-
- /* Set-up NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
-
- /* Set pinmux for the required peripherals */
- setup_iomux_uart3();
- setup_iomux_i2c();
- setup_iomux_fec();
- setup_iomux_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* Enable power for ethernet */
- gpio_direction_output(63, 0);
-
- udelay(2000);
-
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- int rev = 0;
-
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-/*
- * called prior to booting kernel or by 'fdt boardsetup' command
- *
- */
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- static const struct node_info nodes[] = {
- { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
- { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
- };
-
- if (env_get("fdt_noauto")) {
- puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
- return 0;
- }
-
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
- */
-
-#include <config.h>
-#include <asm/arch/lowlevel_macro.S>
-
-.globl lowlevel_init
-lowlevel_init:
-
- core_init
-
- init_aips
-
- init_max
-
- init_m3if
-
- mov pc, lr
int board_init(void)
{
+#ifdef CONFIG_MACH_TYPE
/* Machine number */
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+#endif
/* Boot parameters address */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+++ /dev/null
-if TARGET_ASPENITE
-
-config SYS_BOARD
- default "aspenite"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_SOC
- default "armada100"
-
-config SYS_CONFIG_NAME
- default "aspenite"
-
-endif
+++ /dev/null
-ASPENITE BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/aspenite/
-F: include/configs/aspenite.h
-F: configs/aspenite_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Contributor: Mahavir Jain <mjain@marvell.com>
-
-obj-y := aspenite.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <mvmfp.h>
-#include <asm/global_data.h>
-#include <asm/mach-types.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- u32 mfp_cfg[] = {
- /* I2C */
- MFP105_CI2C_SDA,
- MFP106_CI2C_SCL,
-
- /* Enable Console on UART1 */
- MFP107_UART1_RXD,
- MFP108_UART1_TXD,
-
- MFP_EOC /*End of configureation*/
- };
- /* configure MFP's */
- mfp_config(mfp_cfg);
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
- return 0;
-}
MPP43_GPIO,
MPP44_GPIO,
MPP45_GPIO,
- MPP46_GPIO, /* M_RLED */
+ MPP46_GPIO, /* M_RLED */
MPP47_GPIO, /* M_GLED */
MPP48_GPIO, /* B_RLED */
MPP49_GPIO, /* B_GLED */
#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
(1 << I2C_IO_REG_0_USB_H1_CL))
-/*
- * Information specific to the iEi Puzzle-M801 board.
- */
-
-/* Internal configuration registers */
-#define CP1_CONF_REG_BASE 0xf4440000
-#define CONF_REG_MPP0 0x0
-#define CONF_REG_MPP1 0x4
-#define CONF_REG_MPP2 0x8
-#define CONF_REG_MPP3 0xC
-
static int usb_enabled = 0;
/* Board specific xHCI dis-/enable code */
int board_early_init_f(void)
{
- /* Initialize some platform specific memory locations */
- if (of_machine_is_compatible("marvell,armada8040-puzzle-m801")) {
- /* MPP setup */
- writel(0x00444444, CP1_CONF_REG_BASE + CONF_REG_MPP0);
- writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP1);
- writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP2);
- writel(0x08888000, CP1_CONF_REG_BASE + CONF_REG_MPP3);
- }
+ /* Nothing to do yet */
return 0;
}
case CVMX_QLM_MODE_XFI:
case CVMX_QLM_MODE_RGMII_XFI:
case CVMX_QLM_MODE_RGMII_XFI_1X1:
- type_str = "xfi";
+ type_str = "10gbase-r";
break;
case CVMX_QLM_MODE_10G_KR:
case CVMX_QLM_MODE_RGMII_10G_KR:
if (pmd_control.s.train_en)
type_str = "10G_KR";
else
- type_str = "xfi";
+ type_str = "10gbase-r";
break;
case 4:
if (pmd_control.s.train_en)
speed[qlm] = 103125;
}
printf("QLM %d: XLAUI\n", qlm);
- } else if (!strncmp(mode_str, "xfi", 3)) {
+ } else if (!strncmp(mode_str, "10gbase-r", 3)) {
bool rgmii = false;
speed[qlm] = 103125;
{
return fdt_get_board_model();
}
-
#
# Copyright (C) 2021 Phil Sutter <phil@nwl.cc>
-obj-y += legacy.o
+obj-$(SUPPORT_PASSING_ATAGS) += legacy.o
static unsigned int syno_board_id(void)
{
+#ifdef CONFIG_MACH_TYPE
switch (CONFIG_MACH_TYPE) {
case 527:
return SYNO_DS109_ID;
case 3036:
return SYNO_AXP_4BAY_2BAY;
- default:
- return 0;
}
+#endif
+ return 0;
}
static unsigned int usb_port_modes(void)
config SYS_CONFIG_NAME
default "imx8qm_rom7720"
+config IMX_CONFIG
+ default "board/advantech/imx8qm_rom7720_a1/imximage.cfg"
+
source "board/freescale/common/Kconfig"
endif
void spl_board_init(void)
{
-#if defined(CONFIG_SPL_SPI_SUPPORT)
+#if defined(CONFIG_SPL_SPI)
if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
puts("Warning: failed to initialize FSPI0\n");
void spl_board_prepare_for_boot(void)
{
-#if defined(CONFIG_SPL_SPI_SUPPORT)
+#if defined(CONFIG_SPL_SPI)
if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
puts("Warning: failed to turn off FSPI0\n");
+++ /dev/null
-#
-# Copyright (C) 2017 Allied Telesis Labs
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
void arch_preboot_os(void)
{
-#ifdef CONFIG_WATCHDOG
- wdt_stop(gd->watchdog_dev);
-#endif
+ if (CONFIG_IS_ENABLED(WDT))
+ wdt_stop_all();
}
static int led_7seg_init(unsigned int segments)
F: board/amlogic/beelink-s922x/
F: configs/beelink-gtking_defconfig
F: configs/beelink-gtkingpro_defconfig
+F: configs/beelink-gsking-x_defconfig
F: doc/board/amlogic/beelink-gtking.rst
F: doc/board/amlogic/beelink-gtkingpro.rst
--- /dev/null
+JetHome JetHub
+M: Vyacheslav Bocharov <adeep@lexina.in>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/jethub-j80/
+F: configs/jethub_j80_defconfig
+F: configs/jethub_j100_defconfig
+F: doc/board/amlogic/jethub-j80.rst
+F: doc/board/amlogic/jethub-j100.rst
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021 Vyacheslav Bocharov
+# Author: Vyacheslav Bocharov <adeep@lexina.in>
+
+obj-y := jethub-j80.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <adc.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET 50
+#define EFUSE_SN_SIZE 32
+#define EFUSE_MAC_OFFSET 0
+#define EFUSE_MAC_SIZE 6
+#define EFUSE_USID_OFFSET 18
+#define EFUSE_USID_SIZE 32
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ char serial[EFUSE_SN_SIZE];
+ char usid[EFUSE_USID_SIZE];
+ ssize_t len;
+ unsigned int adcval;
+ int ret;
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
+ }
+
+ if (!env_get("serial")) {
+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+ EFUSE_SN_SIZE);
+ if (len == EFUSE_SN_SIZE)
+ env_set("serial", serial);
+ }
+
+ if (!env_get("usid")) {
+ len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid,
+ EFUSE_USID_SIZE);
+ if (len == EFUSE_USID_SIZE)
+ env_set("usid", usid);
+ }
+
+ ret = adc_channel_single_shot("adc@8680", 0, &adcval);
+ if (adcval < 3000)
+ env_set("userbutton", "true");
+ else
+ env_set("userbutton", "false");
+
+ return 0;
+}
F: board/amlogic/odroid-n2/
F: configs/odroid-n2_defconfig
F: configs/odroid-c4_defconfig
+F: configs/odroid-hc4_defconfig
F: doc/board/amlogic/odroid-n2.rst
F: doc/board/amlogic/odroid-c4.rst
L: u-boot-amlogic@groups.io
F: board/amlogic/u200/
F: configs/u200_defconfig
+F: configs/bananapi-m5_defconfig
+F: configs/radxa-zero_defconfig
F: doc/board/amlogic/u200.rst
+F: doc/board/amlogic/radxa-zero.rst
config SYS_BOARD_VERSION
default 5
+config IMX_CONFIG
+ default "board/aristainetos/aristainetos2.cfg"
+
endif
if TARGET_ARISTAINETOS2CCSLB
config SYS_BOARD_VERSION
default 6
+config IMX_CONFIG
+ default "board/aristainetos/aristainetos2.cfg"
+
endif
config SYS_CONFIG_NAME
default "opos6uldev"
-config IMX_CONFIG
- default "arch/arm/mach-imx/spl_sd.cfg"
-
endif
--- /dev/null
+if TARGET_VEXPRESS_CA9X4
+
+config SYS_BOARD
+ default "vexpress"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "vexpress_ca9x4"
+
+endif
--- /dev/null
+VERSATILE EXPRESS BOARDS
+M: Kristian Amlie <kristian.amlie@northern.tech>
+S: Maintained
+F: board/armltd/vexpress/
+F: include/configs/vexpress_ca9x4.h
+F: configs/vexpress_ca9x4_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-obj-y += generic.o timer.o reset.o relocate.o
+obj-y := vexpress_common.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/systimer.h>
+#include <asm/arch/sysctrl.h>
+#include <asm/arch/wdt.h>
+
+static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
+static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
+
+static void flash__init(void);
+static void vexpress_timer_init(void);
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(ulong loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+ gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
+
+ icache_enable();
+ flash__init();
+ vexpress_timer_init();
+
+ return 0;
+}
+
+static void flash__init(void)
+{
+ /* Setup the sytem control register to allow writing to flash */
+ writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
+ &sysctrl_base->scflashctrl);
+}
+
+int dram_init(void)
+{
+ gd->ram_size =
+ get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size =
+ get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size =
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
+
+/*
+ * Start timer:
+ * Setup a 32 bit timer, running at 1KHz
+ * Versatile Express Motherboard provides 1 MHz timer
+ */
+static void vexpress_timer_init(void)
+{
+ /*
+ * Set clock frequency in system controller:
+ * VEXPRESS_REFCLK is 32KHz
+ * VEXPRESS_TIMCLK is 1MHz
+ */
+ writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
+ SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
+ readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
+
+ /*
+ * Set Timer0 to be:
+ * Enabled, free running, no interrupt, 32-bit, wrapping
+ */
+ writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+ writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+ writel(SYSTIMER_EN | SYSTIMER_32BIT |
+ readl(&systimer_base->timer0control),
+ &systimer_base->timer0control);
+}
+
+int v2m_cfg_write(u32 devfn, u32 data)
+{
+ /* Configuration interface broken? */
+ u32 val;
+
+ devfn |= SYS_CFG_START | SYS_CFG_WRITE;
+
+ val = readl(V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
+
+ writel(data, V2M_SYS_CFGDATA);
+ writel(devfn, V2M_SYS_CFGCTRL);
+
+ do {
+ val = readl(V2M_SYS_CFGSTAT);
+ } while (val == 0);
+
+ return !!(val & SYS_CFG_ERR);
+}
+
+/* Use the ARM Watchdog System to cause reset */
+void reset_cpu(void)
+{
+ if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+ printf("Unable to reboot\n");
+}
+
+void lowlevel_init(void)
+{
+}
+
+ulong get_board_rev(void){
+ return readl((u32 *)SYS_ID);
+}
+
+#ifdef CONFIG_ARMV7_NONSEC
+/* Setting the address at which secondary cores start from.
+ * Versatile Express uses one address for all cores, so ignore corenr
+ */
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* The SYSFLAGS register on VExpress needs to be cleared first
+ * by writing to the next address, since any writes to the address
+ * at offset 0 will only be ORed in
+ */
+ writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
+ writel(addr, CONFIG_SYSFLAGS_ADDR);
+}
+#endif
# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
obj-y += armadillo-800eva.o
-
#include <common.h>
#include <debug_uart.h>
+#include <fdtdec.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
#ifdef CONFIG_CMD_USB
board_usb_hw_init();
return 0;
}
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
+ return fdtdec_setup_mem_size_base();
}
#define MAC24AA_MAC_OFFSET 0xfa
F: board/atmel/sama5d2_icp/
F: include/configs/sama5d2_icp.h
F: configs/sama5d2_icp_mmc_defconfig
+F: configs/sama5d2_icp_qspiflash_defconfig
#include <i2c.h>
#include <init.h>
#include <nand.h>
-#include <version.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
#ifdef CONFIG_CMD_USB
board_usb_hw_init();
return 0;
}
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
+ return fdtdec_setup_mem_size_base();
}
#define AT24MAC_MAC_OFFSET 0x9a
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
-
config SYS_CONFIG_NAME
default "imx8mm_beacon"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+
source "board/freescale/common/Kconfig"
endif
config IMX8MN_FORCE_NOM_SOC
bool "Force to use nominal mode for SOC and ARM"
- default n
config IMX8MN_BEACON_2GB_LPDDR
bool "Enable 2GB LPDDR"
- default n
+
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
source "board/freescale/common/Kconfig"
====
Set baseboard DIP switch:
S17: 1100XXXX
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 400, 100, },
};
-
config SYS_CONFIG_NAME
default "mx53cx9020"
+config IMX_CONFIG
+ default "board/beckhoff/mx53cx9020/imximage.cfg"
+
endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
+#endif
/*
* Set CCAT mode
# Copyright (C) 2018 Robert Bosch Power Tools GmbH
#
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static const struct ddr_data ddr3_data = {
const struct dpll_params *get_dpll_ddr_params(void)
{
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return &dpll_ddr;
}
/*
* Read header information from EEPROM into global structure.
*/
+#define EEPROM_ADDR 0x50
static int read_eeprom(void)
{
/* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ if (i2c_probe(EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
return -ENODEV;
}
/* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+ if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
return -EIO;
config SYS_CONFIG_NAME
default "nitrogen6x"
+config DDR_MB
+ int "Memory size in MB"
+
endif
nitrogen6q i.MX6Q/6D 1GB
nitrogen6dl i.MX6DL 1GB
nitrogen6s i.MX6S 512MB
- nitrogen6q2g i.MX6Q/6D 2GB
+ nitrogen6q2g i.MX6Q/6D 2GB
nitrogen6dl2g i.MX6DL 2GB
nitrogen6s1g i.MX6S 1GB
5. Use one of previous descriptions to re-flash the SPI-NOR as required.
6. Ensure SW1 is returned to "00" to boot from the fuses once done.
-
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
void reset_cpu(void)
{
}
Because this problem is easy to fall into and difficult to debug
if one doesn't expect it, the linker script provides a link-time
check and fatal error message if the image size exceeds 128 KB.
-
return 0;
}
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
return 0;
}
-#endif /* CONFIG_POWER */
+#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */
/*
* cl_som_imx7_setup_wdog() - watchdog configuration.
}
}
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#ifdef CONFIG_SPL_SPI
static void cl_som_imx7_spl_spi_init(void)
{
cl_som_imx7_espi1_pads_set();
}
-#else /* !CONFIG_SPL_SPI_SUPPORT */
+#else /* !CONFIG_SPL_SPI */
static void cl_som_imx7_spl_spi_init(void) {}
-#endif /* CONFIG_SPL_SPI_SUPPORT */
+#endif /* CONFIG_SPL_SPI */
void board_init_f(ulong dummy)
{
return 0;
}
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
}
+#endif
static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART4_BASE,
enable_uart_clk(1);
}
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#ifdef CONFIG_SPL_SPI
static void cm_fx6_setup_ecspi(void)
{
cm_fx6_set_ecspi_iomux();
}
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
static struct fsl_esdhc_cfg usdhc_cfg = {
.esdhc_base = USDHC3_BASE_ADDR,
.max_bus_width = 4,
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
set_i2c_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_probe(TPS65218_CHIP_PM);
return 0;
void scale_vcores(void)
{
set_i2c_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (i2c_probe(TPS65218_CHIP_PM))
return;
hang();
}
-
# Author: Igor Grinberg <grinberg@compulab.co.il>
obj-y += common.o
-obj-$(CONFIG_SYS_I2C_LEGACY) += eeprom.o
+obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += eeprom.o
obj-$(CONFIG_LCD) += omap3_display.o
obj-$(CONFIG_SMC911X) += omap3_smc911x.o
#include <linux/kernel.h>
#include "eeprom.h"
-#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#endif
-
-#ifndef CONFIG_SYS_I2C_EEPROM_BUS
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
-#endif
-
#define EEPROM_LAYOUT_VER_OFFSET 44
#define BOARD_SERIAL_OFFSET 20
#define BOARD_SERIAL_OFFSET_LEGACY 8
#define LAYOUT_VERSION_VER2 3
#define LAYOUT_VERSION_VER3 4
-extern struct eeprom_field layout_unknown[1];
-
#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x
-#ifdef CONFIG_CM_T3X
-struct eeprom_field layout_legacy[5] = {
- { "MAC address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
- { "Board Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin) },
- { "Serial Number", 8, NULL, DEFINE_PRINT_UPDATE(bin) },
- { "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) },
- { RESERVED_FIELDS, 176, NULL, eeprom_field_print_reserved,
- eeprom_field_update_ascii },
-};
-#else
-#define layout_legacy layout_unknown
-#endif
-
-#if defined(CONFIG_CM_T3X)
-struct eeprom_field layout_v1[12] = {
- { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
- { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
- { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
- { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
- { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) },
- { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
- { RESERVED_FIELDS, 96, NULL, DEFINE_PRINT_UPDATE(reserved) },
- { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
- { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
- { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
- { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
- { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved,
- eeprom_field_update_ascii },
-};
-#else
-#define layout_v1 layout_unknown
-#endif
-
struct eeprom_field layout_v2[15] = {
{ "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
{ "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version)
{
switch (layout->layout_version) {
- case LAYOUT_VERSION_LEGACY:
- layout->fields = layout_legacy;
- layout->num_of_fields = ARRAY_SIZE(layout_legacy);
- break;
- case LAYOUT_VERSION_VER1:
- layout->fields = layout_v1;
- layout->num_of_fields = ARRAY_SIZE(layout_v1);
- break;
case LAYOUT_VERSION_VER2:
layout->fields = layout_v2;
layout->num_of_fields = ARRAY_SIZE(layout_v2);
#define _EEPROM_
#include <errno.h>
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
u32 cl_eeprom_get_board_rev(uint eeprom_bus);
int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus);
config SYS_CONFIG_NAME
default "imx8mm-cl-iot-gate"
+config IMX_CONFIG
+ default "board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
+
endif
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 2400, 400, 100, },
};
-
enable_tzc380();
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, 100000, 0x7f, &i2c_pad_info1);
power_init_board();
config SYS_CONFIG_NAME
default "cgtqmx8"
+config IMX_CONFIG
+ default "board/congatec/cgtqmx8/imximage.cfg"
+
source "board/congatec/common/Kconfig"
endif
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
- default n
help
This option enables LTC3882 voltage monitor read
functionality. It is used by common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
- default n
help
This option enables LTC3882 voltage monitor set
functionality. It is used by common VID driver.
config USB_TCPC
bool "USB Typec port controller simple driver"
- default n
help
Enable USB type-c port controller (TCPC) driver
#include <config.h>
#include <common.h>
#include <nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#define BIT_CLE ((unsigned short)0x0800)
their MAC address in SPI Flash from the factory
Enable this option to read the MAC from SPI Flash
-config MAC_ADDR_IN_EEPROM
- bool "MAC address in EEPROM"
- help
- The DA850 EVM comes with SoM are programmed with
- their MAC address in SPI Flash from the factory,
- but the kit has an optional expansion board with
- EEPROM available. Enable this option to read the
- MAC from the EEPROM
-
endif
endif
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
-obj-$(CONFIG_MACH_OMAPL138_LCDK) += omapl138_lcdk.o
+obj-$(CONFIG_TARGET_OMAPL138_LCDK) += omapl138_lcdk.o
{
dspwake();
-#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
-
- uchar env_enetaddr[6];
- int enetaddr_found;
+#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH)
+ uchar env_enetaddr[6], buff[6];
+ int enetaddr_found, spi_mac_read;
enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
-#endif
-
-#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
- int spi_mac_read;
- uchar buff[6];
-
spi_mac_read = get_mac_addr(buff);
buff[0] = 0;
"with the MAC address in the environment\n");
printf("Default using MAC address from environment\n");
}
-
-#elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
- uint8_t enetaddr[8];
- int eeprom_mac_read;
-
- /* Read Ethernet MAC address from EEPROM */
- eeprom_mac_read = dvevm_read_mac_address(enetaddr);
-
- /*
- * MAC address not present in the environment
- * try and read the MAC address from EEPROM flash
- * and set it.
- */
- if (!enetaddr_found) {
- if (eeprom_mac_read)
- /* Set Ethernet MAC address from EEPROM */
- davinci_sync_env_enetaddr(enetaddr);
- } else {
- /*
- * MAC address present in environment compare it with
- * the MAC address in EEPROM and warn on mismatch
- */
- if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
- printf("Warning: MAC address in EEPROM don't match "
- "with the MAC address in the environment\n");
- printf("Default using MAC address from environment\n");
- }
-
#endif
return 0;
}
#define REV_AM18X_EVM 0x100
+#ifdef CONFIG_REVISION_TAG
/*
* get_board_rev() - setup to pass kernel board revision information
* Returns:
rev = 1;
return rev;
}
+#endif
int board_early_init_f(void)
{
#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
#endif
-/*
- * get_board_rev() - setup to pass kernel board revision information
- * Returns:
- * bit[0-3] Maximum cpu clock rate supported by onboard SoC
- * 0000b - 300 MHz
- * 0001b - 372 MHz
- * 0010b - 408 MHz
- * 0011b - 456 MHz
- */
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_early_init_f(void)
{
/*
#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
-static int get_mac_addr(u8 *addr)
-{
- /* Need to find a way to get MAC ADDRESS */
- return 0;
-}
-
void dsp_lpsc_on(unsigned domain, unsigned int id)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
int misc_init_r(void)
{
- uint8_t tmp[20], addr[10];
-
-
- if (env_get("ethaddr") == NULL) {
- /* Read Ethernet MAC address from EEPROM */
- if (dvevm_read_mac_address(addr)) {
- /* Set Ethernet MAC address from EEPROM */
- davinci_sync_env_enetaddr(addr);
- } else {
- get_mac_addr(addr);
- }
-
- if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
- sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
- addr[0], addr[1], addr[2], addr[3], addr[4],
- addr[5]);
-
- env_set("ethaddr", (char *)tmp);
- } else {
- printf("Invalid MAC address read.\n");
- }
- }
-
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
/* Select RMII fucntion through the expander */
if (rmii_hw_init())
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <watchdog.h>
+#include <dm/ofnode.h>
#include "../../st/common/stpmic1.h"
/* SYSCFG registers */
#ifdef CONFIG_LED
static int get_led(struct udevice **dev, char *led_string)
{
- char *led_name;
+ const char *led_name;
int ret;
- led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
+ led_name = ofnode_conf_read_str(led_string);
if (!led_name) {
pr_debug("%s: could not find %s config string\n",
__func__, led_string);
config SYS_CONFIG_NAME
default "mx7ulp_com"
+config IMX_CONFIG
+ default "board/ea/mx7ulp_com/imximage.cfg"
+
endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
}
}
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
#ifdef CONFIG_DEBUG_UART
void board_debug_uart_init(void)
/* setup GP timer */
timer_init();
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
setup_iomux_uart();
preloader_console_init();
#endif
config SYS_CONFIG_NAME
default "imx8mm_icore_mx8mm"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+
source "board/freescale/common/Kconfig"
endif
#include <led.h>
#include <log.h>
#include <asm/global_data.h>
+#include <dm/ofnode.h>
#ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
char *led_name;
int ret;
- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+ led_name = ofnode_conf_read_str("u-boot,boot-led");
if (!led_name)
return 0;
ret = led_get_by_label(led_name, &dev);
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
- default n
help
This option enables the PCA9547 I2C mux on Freescale boards.
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(void);
-extern unsigned long get_board_ddr_clk(void);
extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
- u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
+ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
u32 crc; /* 0xfc - 0xff CRC32 checksum */
#endif
} e;
config SYS_CONFIG_NAME
default "imx8mm_evk"
+config IMX_CONFIG
+ default "board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg"
+
endif
config IMX8MN_LOW_DRIVE_MODE
bool "Enable the low drive mode of iMX8MN on EVK board"
- default n
+
+config IMX_CONFIG
+ default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
source "board/freescale/common/Kconfig"
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 2400, 1066, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 1600, 1066, },
};
-
config SYS_CONFIG_NAME
default "imx8mp_evk"
+config IMX_CONFIG
+ default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
+
source "board/freescale/common/Kconfig"
endif
},
};
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
config SYS_CONFIG_NAME
default "imx8mq_evk"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
endif
return 0;
}
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
config SYS_CONFIG_NAME
default "imx8qm_mek"
+config IMX_CONFIG
+ default "board/freescale/imx8qm_mek/imximage.cfg"
+
source "board/freescale/common/Kconfig"
endif
config SYS_CONFIG_NAME
default "imx8qxp_mek"
+config IMX_CONFIG
+ default "board/freescale/imx8qxp_mek/imximage.cfg"
+
source "board/freescale/common/Kconfig"
endif
}
#endif
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
}
#endif
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4020_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4020_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
bus = miiphy_get_dev_by_name(mdio_name);
pfe_set_mdio(1, bus);
pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
data8 = QIXIS_READ(brdcfg[12]);
data8 |= 0x20;
pfe_set_mdio(0, bus);
pfe_set_phy_address_mode(0,
CONFIG_PFE_SGMII_2500_PHY1_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
}
break;
ETH_1_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
- prop_val.phy_mode = "sgmii-2500";
+ prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
ETH_1_MDIO);
} else {
ETH_2_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
- prop_val.phy_mode = "sgmii-2500";
+ prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
ETH_2_MDIO);
}
#define ETH_1_2_5G_PHY_ID 0x1
#define ETH_1_2_5G_MDIO_MUX 0x2
#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
-#define ETH_2_5G_PHY_MODE "sgmii-2500"
+#define ETH_2_5G_PHY_MODE "2500base-x"
#define ETH_2_2_5G_BUS_ID 0x1
#define ETH_2_2_5G_PHY_ID 0x2
#define ETH_2_2_5G_MDIO_MUX 0x3
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4020_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4030_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4030_0000
PPA FIT image | 2MB | 0x4040_0000
PFE firmware | 20K | 0x00a0_0000
Linux ITB | ~53MB | 0x4100_0000
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC1_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
} else {
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
}
break;
default:
LS1021a rev1.0 Soc specific Options/Settings
--------------------------------------------
-If the LS1021a Soc is rev1.0, you need modify the configure file.
-Add the following define in include/configs/ls1021aqds.h:
-#define CONFIG_SKIP_LOWLEVEL_INIT
+If the LS1021a Soc is rev1.0, you need modify the configuration and enable
+CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.
return 66666666;
}
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
}
return 66666666;
}
+#endif
int dram_init(void)
{
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP Semiconductors
+/* Copyright 2016-2019 NXP
*/
#include <common.h>
#include <clock_legacy.h>
LS1021a rev1.0 Soc specific Options/Settings
--------------------------------------------
-If the LS1021a Soc is rev1.0, you need modify the configure file.
-Add the following define in include/configs/ls1021atwr.h:
-#define CONFIG_SKIP_LOWLEVEL_INIT
+If the LS1021a Soc is rev1.0, you need modify the configuration and enable
+CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.
config EMMC_BOOT
bool "Support for booting from EMMC"
- default n
config SYS_TEXT_BASE
default 0x96000000 if SD_BOOT || EMMC_BOOT
config EMMC_BOOT
bool "Support for booting from EMMC"
- default n
config SYS_TEXT_BASE
default 0x96000000 if SD_BOOT || EMMC_BOOT
u8 uart;
#endif
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
i2c_early_init_f();
#endif
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
"sgmii-riser-s4-p1");
}
} else if (fm_info_get_enet_if(port) ==
- PHY_INTERFACE_MODE_SGMII_2500) {
+ PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (mdio_mux[port]) {
case EMI1_SLOT1:
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
port == FM1_10GEC1) {
- /* XFI interface */
+ /* 10GBase-R interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
- /* no PHY for XFI */
+ /* no PHY for 10GBase-R */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
- } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ } else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
#define CFG_UART_MUX_SHIFT 1
#define CFG_LPUART_EN 0x1
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
-void i2c_early_init_f(void);
-#endif
-
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
*/
out_le32(cntcr, 0x1);
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
i2c_early_init_f();
#endif
fsl_lsch2_early_init_f();
config SYS_HAS_ARMV8_SECURE_BASE
bool "Enable secure address for PSCI image"
depends on ARMV8_PSCI
- default n
help
PSCI image can be re-located to secure RAM.
If enabled, please also define the value for ARMV8_SECURE_BASE,
- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
standard PCIe card
- QSGMII with x4 RJ45 connector
- - XFI with x1 RJ45 connector
+ - 10GBase-R with x1 RJ45 connector
- DDR Controller
- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
- /* XFI on lane A, MAC 9 */
+ /* 10GBase-R on lane A, MAC 9 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
-IFC/Local Bus
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
default:
break;
}
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
/* Backplane KR mode: skip fixups */
printf("Interface %d in backplane KR mode\n", port);
} else {
- /* XFI interface */
+ /* 10GBase-R interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
- /* no PHY for XFI */
+ /* no PHY for 10GBase-R */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
-void i2c_early_init_f(void);
-#endif
-
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
*/
out_le32(cntcr, 0x1);
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
i2c_early_init_f();
#endif
fsl_lsch2_early_init_f();
LS1046ARDB board Overview
-----------------------
- SERDES1 Connections, 4 lanes supporting:
- - Lane0: XFI with x1 RJ45 connector
- - Lane1: XFI Cage
+ - Lane0: 10GBase-R with x1 RJ45 connector
+ - Lane1: 10GBase-R Cage
- Lane2: SGMII.5
- Lane3: SGMII.6
- SERDES2 Connections, 4 lanes supporting:
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
QSPI flash map:
Start Address End Address Description Size
0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
-0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
+0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
- /* XFI on lane A, MAC 9 */
+ /* 10GBase-R on lane A, MAC 9 */
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - XFI
+ - 10GBase-R
- QSGMII
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - 2 XFI
+ - 2 10GBase-R
- QSGMII, SGMII with help for Riser card
- 2 RGMII
- 5 slot for Riser card or PCIe NIC
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
-
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
switch (srds_s1) {
case 0x1D:
/*
- * XFI does not need a PHY to work, but to avoid U-boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
+ * 10GBase-R does not need a PHY to work, but to avoid U-boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
* MAC error.
*/
wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
- QSGMII
- SATA 3.0
- XAUI
- - XFI
+ - 10GBase-R
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
DPMAC14 -> PHY4-P1
DPMAC15 -> PHY4-P2
DPMAC16 -> PHY4-P3
-
case 0x4B:
case 0x4C:
/*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
- * error.
+ * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
+ * MAC, and should not use a real XAUI PHY address, since MDIO
+ * can access it successfully, and then MDIO thinks the XAUI
+ * card is used for the 10GBase-R MAC, which will cause error.
*/
wriop_set_phy_address(i, 0, i + 4);
ls2080a_qds_enable_SFP_TX(SFP_TX);
int board_early_init_f(void)
{
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
i2c_early_init_f();
#endif
fsl_lsch3_early_init_f();
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
hugepages=16 mem=2048M'
-
int board_early_init_f(void)
{
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT)
i2c_early_init_f();
#endif
fsl_lsch3_early_init_f();
int board_early_init_f(void)
{
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
i2c_early_init_f();
#endif
/* get required clock for UART IP */
CONFIG_SYS_MBAR -- define MBAR offset
-CONFIG_MONITOR_IS_IN_RAM -- Not support
+CONFIG_MONITOR_IS_IN_RAM -- Not support
CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#define SET_CLE 0x10
#define SET_ALE 0x08
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#define SET_CLE 0x10
#define SET_ALE 0x08
+++ /dev/null
-if TARGET_MPC8349EMDS
-
-config SYS_BOARD
- default "mpc8349emds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8349EMDS"
-
-endif
-
-if TARGET_MPC8349EMDS_SDRAM
-
-config SYS_BOARD
- default "mpc8349emds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8349EMDS_SDRAM"
-
-endif
+++ /dev/null
-MPC8349EMDS BOARD
-#M: Kim Phillips <kim.phillips@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/mpc8349emds/
-F: include/configs/MPC8349EMDS.h
-F: configs/MPC8349EMDS_defconfig
-F: configs/MPC8349EMDS_SDRAM_defconfig
-F: configs/MPC8349EMDS_PCI64_defconfig
-F: configs/MPC8349EMDS_SLAVE_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8349emds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 300, 4, 4, 2, 0},
- {2, 365, 4, 6, 2, 0},
- {2, 450, 4, 7, 2, 0},
- {2, 850, 4, 31, 2, 0},
- {1, 300, 4, 4, 2, 0},
- {1, 365, 4, 6, 2, 0},
- {1, 450, 4, 7, 2, 0},
- {1, 850, 4, 31, 2, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned int i;
- ulong ddr_freq;
-
- if (ctrl_num != 0) /* we have only one controller */
- return;
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (pdimm[i].n_ranks)
- break;
- }
- if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
- return;
-
- pbsp = udimm0;
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[i].n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- popts->dqs_config = 0; /* only true DQS signal is used on board */
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/bitops.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <miiphy.h>
-#ifdef CONFIG_SYS_FSL_DDR2
-#include <fsl_ddr_sdram.h>
-#else
-#include <spd_sdram.h>
-#endif
-#include <linux/delay.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-int board_early_init_f (void)
-{
- volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[1] &= ~0x01;
-
-#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
- /* Use USB PHY on SYS board */
- bcsr[5] |= 0x02;
-#endif
-
- return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- phys_size_t msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -ENXIO;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_SYS_FSL_DDR2
- msize = spd_sdram() * 1024 * 1024;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- ddr_enable_ecc(msize);
-#endif
-#else
- msize = fsl_ddr_sdram();
-#endif
-#else
- msize = fixed_sdram() * 1024 * 1024;
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- sdram_init();
-
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize;
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE;
- u32 ddr_size = msize << 20; /* DDR size in bytes */
- u32 ddr_size_log2 = __ilog2(ddr_size);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
- im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
- /* currently we use only one CS, so disable the other banks */
- im->ddr.cs_config[0] = 0;
- im->ddr.cs_config[1] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
- im->ddr.sdram_cfg =
- SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
- | SDRAM_CFG_2T_EN
-#endif
- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
- /* for 32-bit mode burst length is 8 */
- im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
- udelay(200);
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
- /*
- * Warning: do not read the BCSR registers here
- *
- * There is a timing bug in the 8349E and 8349EA BCSR code
- * version 1.2 (read from BCSR 11) that will cause the CFI
- * flash initialization code to overwrite BCSR 0, disabling
- * the serial ports and gigabit ethernet
- */
-
- puts("Board: Freescale MPC8349EMDS\n");
- return 0;
-}
-
-/*
- * if MPC8349EMDS is soldered with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM) \
- && defined(CONFIG_SYS_OR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
- LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
- LSDMR_WRC3 | LSDMR_CL3;
- /*
- * Setup SDRAM Base and Option Registers, already done in cpu_init.c
- */
-
- /* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = 0x00000000;
- /* LB refresh timer prescal, 266MHz/32 */
- lbc->mrtpr = 0x20000000;
- /* LB sdram refresh timer, about 6us */
- lbc->lsrt = 0x32000000;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
-
- /* 0x40636733; normal operation */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-
- /* 0x68636733; precharge all the banks */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x48636733; auto refresh */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync");
- /*1 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*2 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*3 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*4 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*5 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*6 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*7 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*8 times*/
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x58636733; mode register write operation */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x40636733; normal operation */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-}
-#else
-void sdram_init(void)
-{
-}
-#endif
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK 0x80000000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat &= ~SPI_CS_MASK;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat |= SPI_CS_MASK;
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-#ifndef CONFIG_PCISLAVE
-void pib_init(void)
-{
- u8 val8, orig_i2c_bus;
- /*
- * Assign PIB PMC slot to desired PCI bus
- */
- /* Switch temporarily to I2C bus #2 */
- orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- val8 = 0;
- i2c_write(0x23, 0x6, 1, &val8, 1);
- i2c_write(0x23, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x23, 0x2, 1, &val8, 1);
- i2c_write(0x23, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x26, 0x6, 1, &val8, 1);
- val8 = 0x34;
- i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_PCI_64BIT)
- val8 = 0xf4; /* PMC2:PCI1/64-bit */
-#elif defined(CONFIG_PCI_ALL_PCI1)
- val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(CONFIG_PCI_ONE_PCI1)
- val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
-#else
- val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
-#endif
- i2c_write(0x26, 0x2, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x26, 0x3, 1, &val8, 1);
- val8 = 0;
- i2c_write(0x27, 0x6, 1, &val8, 1);
- i2c_write(0x27, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x27, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x27, 0x3, 1, &val8, 1);
- asm("eieio");
-
-#if defined(CONFIG_PCI_64BIT)
- printf("PCI1: 64-bit on PMC2\n");
-#elif defined(CONFIG_PCI_ALL_PCI1)
- printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(CONFIG_PCI_ONE_PCI1)
- printf("PCI1: 32-bit on PMC1\n");
- printf("PCI2: 32-bit on PMC2, PMC3\n");
-#else
- printf("PCI1: 32-bit on PMC1, PMC2\n");
- printf("PCI2: 32-bit on PMC3\n");
-#endif
- /* Reset to original I2C bus */
- i2c_set_bus_num(orig_i2c_bus);
-}
-
-#endif /* CONFIG_PCISLAVE */
config SYS_CONFIG_NAME
default "mx51evk"
+config IMX_CONFIG
+ default "board/freescale/mx51evk/imximage.cfg"
+
endif
return 0;
}
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
u32 rev = get_cpu_rev();
rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
return rev;
}
+#endif
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
config SYS_CONFIG_NAME
default "mx53loco"
+config IMX_CONFIG
+ default "board/freescale/mx53loco/imximage.cfg"
+
endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
+#endif
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
help
Select the type of DDR (DDR3 or LPDDR2) used on your design
-config DDR3
+config DDR3
bool "DDR3"
help
Select this if your board design uses DDR3.
-config LPDDR2
+config LPDDR2
bool "LPDDR2"
help
Select this if your board design uses LPDDR2.
details.
endmenu
-endif
+config IMX_CONFIG
+ default "arch/arm/mach-imx/spl_sd.cfg"
+
+endif
gd->ram_size = imx_ddr_size();
return 0;
}
-
}
#endif
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
int rev = nxp_board_rev();
return (get_cpu_rev() & ~(0xF << 8)) | rev;
}
+#endif
static int ar8031_phy_fixup(struct phy_device *phydev)
{
config SYS_CONFIG_NAME
default "mx6slevk"
+config IMX_CONFIG
+ default "board/freescale/mx6slevk/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "mx6sllevk"
+config IMX_CONFIG
+ default "board/freescale/mx6sllevk/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "mx6sxsabreauto"
+config IMX_CONFIG
+ default "board/freescale/mx6sxsabreauto/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "mx6sxsabresd"
+config IMX_CONFIG
+ default "board/freescale/mx6sxsabresd/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "mx6ullevk"
+config IMX_CONFIG
+ default "board/freescale/mx6ullevk/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "mx7dsabresd"
+config IMX_CONFIG
+ default "board/freescale/mx7dsabresd/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "mx7ulp_evk"
+config IMX_CONFIG
+ default "board/freescale/mx7ulp_evk/imximage.cfg"
+
endif
dm_i2c_write(dev, 2, &val, 1);
#else
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
- i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
val = 0x0; /* no polarity inversion */
i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
#endif
env_relocate();
#endif
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
i2c_init_all();
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- - 10GbE XFI or 10Base-KR interface
+ - 10GBase-R or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
- /* set 10G XFI with Aquantia AQR105 PHY */
+ /* set 10GBase-R with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
#endif
#endif
fm_info_set_mdio(i, dev);
break;
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
enum fm_port port, int offset)
{
#if defined(CONFIG_TARGET_T1024RDB)
- if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
#endif
return CONFIG_SYS_CLK_FREQ;
}
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
return CONFIG_SYS_CLK_FREQ;
}
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{
return CONFIG_SYS_CLK_FREQ;
}
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- - Four 10Gbps XFI on-board cages
+ - Four 10GBase-R on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
-XFI:
- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+10GBase-R:
+ - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
a on-board SFP+ cages, which to house optical module (fiber cable) or
direct attach cable(copper), the copper cable is used to emulate
10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
+ So, for 10GBase-R usage, there are two scenarios, one will use fiber cable,
another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
+ introduced to indicate a 10GBase-R port will use copper cable, and U-Boot
will fixup the dtb accordingly.
It's used as: fsl_10gkr_copper:<10g_mac_name>
The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
will be used by default.
for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
- hwconfig, then both four XFI ports will use copper cable.
+ hwconfig, then both four 10GBase-R ports will use copper cable.
set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
+ 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use
+ fiber cable.
1000BASE-KX(1G-KX):
- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
Software configurations and board settings
------------------------------------------
1. NOR boot:
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
switch (srds_s1) {
- case 0x66: /* XFI interface */
+ case 0x66: /* 10GBase-R interface */
case 0x6b:
case 0x6c:
case 0x6d:
case 0x71:
/*
- * if the 10G is XFI, check hwconfig to see what is the
- * media type, there are two types, fiber or copper,
- * fix the dtb accordingly.
- */
+ * Check hwconfig to see what is the media type, there
+ * are two types, fiber or copper, fix the dtb
+ * accordingly.
+ */
switch (port) {
case FM1_10GEC1:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
printf("Interface %d in backplane KR mode\n",
port);
} else {
- /* fixed-link for XFI fiber cable */
+ /* fixed-link for 10GBase-R fiber cable */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
case 0x66:
case 0x67:
/*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
+ * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
+ * the XAUI card is used for the 10GBase-R MAC, which will cause
* error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
(srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
(srds_s1 == 0x71)) {
- /* As XFI is in cage intead of a slot, so
+ /* As 10GBase-R is in cage intead of a slot, so
* ensure doesn't disable the corresponding port
*/
break;
break;
case 0x66:
case 0x67:
- /* SD1(A:D) => XFI cage
+ /* SD1(A:D) => 10GBase-R cage
* SD1(E:H) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xfe);
break;
case 0x6a:
case 0x6b:
- /* SD1(A:D) => XFI cage
+ /* SD1(A:D) => 10GBase-R cage
* SD1(E) => SLOT1 PCIe4
* SD1(F:H) => SLOT2 SGMII
*/
break;
case 0x6c:
case 0x6d:
- /* SD1(A:B) => XFI cage
+ /* SD1(A:B) => 10GBase-R cage
* SD1(C:D) => SLOT3 SGMII
* SD1(E:H) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xda);
break;
case 0x6e:
- /* SD1(A:B) => SFP Module, XFI
+ /* SD1(A:B) => SFP Module, 10GBase-R
* SD1(C:D) => SLOT3 SGMII
* SD1(E:F) => SLOT1 PCIe4 x2
* SD1(G:H) => SLOT2 SGMII
config T2080RDB_REV_D
bool "Support for T2080RDB revisions D and up"
- default n
source "board/freescale/common/Kconfig"
T2080PCIe-RDB board Overview
----------------------------
- SERDES Configuration
- - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+ - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
- Ethernet
- Two on-board 10M/100M/1G RGMII ethernet ports
- - Two on-board 10Gbps XFI fiber ports
+ - Two on-board 10GBase-R fiber ports
- Two on-board 10Gbps Base-T copper ports
- DDR Memory
- Supports 72bit 4GB DDR3-LP SODIMM
return CONFIG_SYS_CLK_FREQ;
}
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
return CONFIG_SYS_CLK_FREQ;
}
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
int misc_init_r(void)
{
u8 reg;
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value) \
cpld_write(offsetof(struct cpld_data, reg), value)
-
#if (CONFIG_SYS_NUM_FMAN == 2)
if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
- /* SGMII && XFI */
+ /* SGMII && 10GBase-R */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
return CONFIG_SYS_CLK_FREQ;
}
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
config SYS_CONFIG_NAME
default "vf610twr"
+config IMX_CONFIG
+ default "board/freescale/vf610twr/imximage.cfg"
+
endif
env_set("ethaddr", ethaddr);
}
-#ifdef CONFIG_REVISION_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
static void set_board_rev(void)
{
char info[64] = {0, };
- snprintf(info, ARRAY_SIZE(info), "%02x", get_board_rev());
+ snprintf(info, ARRAY_SIZE(info), "%02x", get_board_revision());
env_set("board_rev", info);
}
#endif
char info[64] = {0, };
snprintf(info, ARRAY_SIZE(info),
- "s5p4418-nanopi2-rev%02x.dtb", get_board_rev());
+ "s5p4418-nanopi2-rev%02x.dtb", get_board_revision());
env_set("dtb_name", info);
}
{
bd_update_env();
-#ifdef CONFIG_REVISION_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_rev();
#endif
set_dtb_name();
}
/* To override __weak symbols */
-u32 get_board_rev(void)
+u32 get_board_revision(void)
{
return (base_rev << 8) | pcb_rev;
}
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ return get_board_revision();
+}
+#endif
+
const char *get_board_name(void)
{
bd_hwrev_init();
extern void bd_hwrev_init(void);
extern void bd_base_rev_init(void);
-extern u32 get_board_rev(void);
+extern u32 get_board_revision(void);
extern const char *get_board_name(void);
#endif /* __BD_HW_REV_H__ */
obj-y := gw_ventana.o gsc.o eeprom.o common.o
obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
-
int gsc_boot_wd_disable(void);
const char *gsc_get_dtb_name(int level, char *buf, int sz);
#endif
-
config SYS_CONFIG_NAME
default "imx8mm_venice"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+
endif
return dm_gpio_request(gpio, gpio_name);
}
-
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name,
- name,
- MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
#include <panel.h>
#include <rtc.h>
#include <spi_flash.h>
-#include <version.h>
+#include <version_string.h>
#include "../common/vpd_reader.h"
#include <power/pmic.h>
#include <input.h>
#include <pwm.h>
-#include <version.h>
+#include <version_string.h>
#include <stdlib.h>
#include <dm/root.h>
#include "../common/ge_rtc.h"
else
env_set("rtc_status", "OK");
}
-
-
if TARGET_MX53PPD
config SYS_BOARD
config SYS_CONFIG_NAME
default "mx53ppd"
+config IMX_CONFIG
+ default "board/ge/mx53ppd/imximage.cfg"
+
source "board/ge/common/Kconfig"
endif
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
-#include <version.h>
+#include <version_string.h>
#include <watchdog.h>
#include "ppd_gpio.h"
#include <stdlib.h>
return 0;
}
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
return get_cpu_rev() & ~(0xF << 8);
}
+#endif
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
};
size_t display_count = ARRAY_SIZE(displays);
-
.get_str = coral_get_str,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id coral_ids[] = {
{ .compatible = "google,coral" },
{ }
config SYS_CONFIG_NAME
default "imx8mq_phanbell"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
endif
static __maybe_unused struct ctrl_dev *cdev =
(struct ctrl_dev *)CTRL_DEVICE_BASE;
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
void set_uart_mux_conf(void)
{
configure_module_pin_mux(uart0_pin_mux);
{
chilisom_spl_board_init();
}
-#endif
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
/*
* Basic board specific setup. Pinmux has been handled already.
#ifdef CONFIG_SPL_BUILD
-#if defined(CONFIG_SPL_MMC_SUPPORT)
+#if defined(CONFIG_SPL_MMC)
int board_mmc_init(struct bd_info *bd)
{
ci20_mux_mmc();
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
+#endif
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR}
config SYS_CONFIG_NAME
default "kp_imx53"
+config IMX_CONFIG
+ default "board/freescale/mx53loco/imximage.cfg"
+
endif
eth_env_set_enetaddr("ethaddr", p);
}
+#define I2C_EEPROM_BUS_NUM 1
+#define I2C_EEPROM_ADDR 0x50
+#define I2C_EEPROM_ADDR_LEN 2
+
int read_eeprom(void)
{
struct udevice *dev;
if (eeprom_has_been_read)
return 0;
- ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
- CONFIG_SYS_I2C_EEPROM_ADDR,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+ ret = i2c_get_chip_for_busnum(I2C_EEPROM_BUS_NUM, I2C_EEPROM_ADDR,
+ I2C_EEPROM_ADDR_LEN, &dev);
if (ret) {
printf("Cannot find EEPROM !\n");
return ret;
struct udevice *eedev = NULL;
ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
- CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev);
+ CONFIG_SYS_IVM_EEPROM_ADR, 1, &eedev);
if (ret) {
printf("failed to get device for EEPROM at address 0x%02x\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
+ CONFIG_SYS_IVM_EEPROM_ADR);
return 1;
}
ret = dm_i2c_read(eedev, 0, buf, len);
if (ret != 0) {
printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ CONFIG_SYS_IVM_EEPROM_ADR, 0);
return 1;
}
#else
return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
KM_I2C_DEBLOCK_SCL);
}
-
{
struct fsl_i2c_base *base;
base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_I2C_OFFSET);
+ CONFIG_SYS_FSL_I2C_OFFSET);
udelay(DELAY_ABORT_SEQ);
out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
{
struct fsl_i2c_base *base;
base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_I2C_OFFSET);
+ CONFIG_SYS_FSL_I2C_OFFSET);
uchar last;
int nbr_read = 0;
int i = 0;
config KM_FPGA_CONFIG
bool "FPGA Configuration"
- default n
help
Include capability to change FPGA configuration.
config KM_FPGA_FORCE_CONFIG
bool "FPGA reconfiguration"
- default n
help
If yes we force to reconfigure the FPGA always
config KM_FPGA_NO_RESET
bool "FPGA skip reset"
- default n
help
If yes we skip triggering a reset of the FPGA
config KM_ENV_IS_IN_SPI_NOR
bool "Environment in SPI NOR"
- default n
help
Put the U-Boot environment in the SPI NOR flash.
config KM_PIGGY4_88E6061
bool "Piggy via Switch 88E6061"
- default n
help
The Piggy4 board is connected via a Marvell 88E6061 switch.
config KM_PIGGY4_88E6352
bool "Piggy via Switch 88E6352"
- default n
help
The Piggy4 board is connected via a Marvell 88E6352 switch.
#include <netdev.h>
#include <nand.h>
#include <spi.h>
-#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
/* Sold devices are expected to be at least revision F. */
return 6;
}
+#endif
void get_board_serial(struct tag_serialnr *serialnr)
{
#endif
}
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#ifdef CONFIG_SPL_SPI
static void displ5_init_ecspi(void)
{
displ5_set_iomux_ecspi_spl();
static inline void displ5_init_ecspi(void) { }
#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
static struct fsl_esdhc_cfg usdhc_cfg = {
.esdhc_base = USDHC4_BASE_ADDR,
.max_bus_width = 8,
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
/*SYS_nRESWARM */\
- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
/* - PEN_IRQ */\
Additional Support Documentation can be found at:
https://support.logicpd.com/
-
*/
void set_muxconf_regs(void)
{
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*SDRC_CKE0*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*SDRC_CKE1*/
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)) /*GPMC_nCS6*/
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) /*ETK_D0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) /*ETK_D1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) /*ETK_D2*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) /*ETK_D3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) /*ETK_D4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) /*ETK_D5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) /*ETK_D6*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) /*ETK_D7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) /*ETK_D8*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) /*ETK_D9*/
#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/
#endif
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/
#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/
#endif
}
+++ /dev/null
-if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
-
-config SYS_BOARD
- default "mt7620"
-
-config SYS_VENDOR
- default "mediatek"
-
-config SYS_CONFIG_NAME
- default "mt7620"
-
-endif
+++ /dev/null
-if TARGET_MT7622
-
-config SYS_BOARD
- default "mt7622"
-
-config SYS_CONFIG_NAME
- default "mt7622"
-
-config MTK_BROM_HEADER_INFO
- string
- default "lk=1"
-
-config MTK_BROM_HEADER_INFO
- string
- default "media=nor"
-
-endif
# SPDX-License-Identifier: GPL-2.0
obj-y += mt7622_rfb.o
-
+++ /dev/null
-if TARGET_MT7623
-
-config SYS_BOARD
- default "mt7623"
-
-config SYS_CONFIG_NAME
- default "mt7623"
-
-config MTK_BROM_HEADER_INFO
- string
- default "lk=1"
-
-endif
+++ /dev/null
-if BOARD_MT7628_RFB
-
-config SYS_BOARD
- default "mt7628"
-
-config SYS_VENDOR
- default "mediatek"
-
-config SYS_CONFIG_NAME
- default "mt7628"
-
-endif
+++ /dev/null
-if TARGET_MT7629
-
-config SYS_BOARD
- default "mt7629"
-
-config SYS_CONFIG_NAME
- default "mt7629"
-
-config MTK_SPL_PAD_SIZE
- hex
- default 0x10000
-
-config MTK_BROM_HEADER_INFO
- string
- default "media=nor"
-
-endif
+++ /dev/null
-if TARGET_MT8183
-
-config SYS_BOARD
- default "mt8183"
-
-config SYS_CONFIG_NAME
- default "mt8183"
-
-config MTK_BROM_HEADER_INFO
- string
- default "media=emmc"
-
-endif
+++ /dev/null
-if TARGET_MT8512
-
-config SYS_BOARD
- default "mt8512"
-
-config SYS_CONFIG_NAME
- default "mt8512"
-
-
-config MTK_BROM_HEADER_INFO
- string
- default "media=nor"
-
-endif
+++ /dev/null
-if TARGET_MT8516
-
-config SYS_BOARD
- default "mt8516"
-
-config SYS_CONFIG_NAME
- default "mt8516"
-
-config MTK_BROM_HEADER_INFO
- string
- default "media=emmc"
-
-endif
+++ /dev/null
-if TARGET_MT8518
-
-config SYS_BOARD
- default "mt8518"
-
-config SYS_CONFIG_NAME
- default "mt8518"
-
-
-config MTK_BROM_HEADER_INFO
- string
- default "media=nor"
-
-endif
config SYS_CONFIG_NAME
default "m53menlo"
+config IMX_CONFIG
+ default "board/menlo/m53menlo/imximage.cfg"
+
endif
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
obj-$(CONFIG_SOC_JR2) := jr2.o
-
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
obj-$(CONFIG_SOC_OCELOT) := ocelot.o
-
return 0;
}
+#ifdef CONFIG_REVISION_TAG
/*
* Routine: get_board_revision
* Description: Return board revision.
{
return simple_strtol(hw_build_ptr, NULL, 16);
}
+#endif
/*
* Routine: setup_board_tags
config SYS_CONFIG_NAME
default "meerkat96"
+config IMX_CONFIG
+ default "board/novtech/meerkat96/imximage.cfg"
+
endif
#include <asm/gpio.h>
/* TODO: Remove this code when the SPI switch is working */
-#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
+#ifndef CONFIG_TARGET_VENTANA
void gpio_early_init_uart(void)
{
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
return ret;
return PS7_INIT_SUCCESS;
}
-
int
default 256
+config IMX_CONFIG
+ default "board/phytec/pcm052/imximage.cfg"
+
endif
if TARGET_BK4R1
int
default 512
+config IMX_CONFIG
+ default "board/phytec/pcm052/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "phycore_imx8mm"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+
endif
config SYS_CONFIG_NAME
default "phycore_imx8mp"
+config IMX_CONFIG
+ default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
+
endif
#define HNF_BASE (unsigned long)(0x3A200000)
#endif /* _FT_DURIAN_H */
-
+++ /dev/null
-if TARGET_BG0900
-
-config SYS_BOARD
- default "bg0900"
-
-config SYS_VENDOR
- default "ppcag"
-
-config SYS_SOC
- default "mxs"
-
-config SYS_CONFIG_NAME
- default "bg0900"
-
-endif
+++ /dev/null
-BG0900 BOARD
-M: Marek Vasut <marex@denx.de>
-S: Maintained
-F: board/ppcag/bg0900/
-F: include/configs/bg0900.h
-F: configs/bg0900_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifndef CONFIG_SPL_BUILD
-obj-y := bg0900.o
-else
-obj-y := spl_boot.o
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PPC-AG BG0900 board
- *
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Functions
- */
-int board_early_init_f(void)
-{
- /* IO0 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK0, 480000);
- /* IO1 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK1, 480000);
-
- /* SSP2 clock at 160MHz */
- mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- return mxs_dram_init();
-}
-
-int board_init(void)
-{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(struct bd_info *bis)
-{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- struct eth_device *dev;
- int ret;
-
- ret = cpu_eth_init(bis);
-
- /* BG0900 uses ENET_CLK PAD to drive FEC clock */
- writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
- &clkctrl_regs->hw_clkctrl_enet);
-
- /* Reset FEC PHYs */
- gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
- udelay(200);
- gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
-
- ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
- if (ret) {
- puts("FEC MXS: Unable to init FEC0\n");
- return ret;
- }
-
- dev = eth_get_dev_by_name("FEC0");
- if (!dev) {
- puts("FEC MXS: Unable to get FEC0 device entry\n");
- return -EINVAL;
- }
-
- return ret;
-}
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PPC-AG BG0900 Boot setup
- *
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-
-const iomux_cfg_t iomux_setup[] = {
- /* DUART */
- MX28_PAD_PWM0__DUART_RX,
- MX28_PAD_PWM1__DUART_TX,
-
- /* GPMI NAND */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-
- /* FEC0 */
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
-
- /* FEC0 Reset */
- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
- (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-
- /* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
-
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
-
- /* SPI2 (for SPI flash) */
- MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_SS0__SSP2_D3 |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
-};
-
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-{
- /*
- * DDR Controller Registers
- * Manufacturer: Winbond
- * Device Part Number: W972GG6JB-25I
- * Clock Freq.: 200MHz
- * Density: 2Gb
- * Chip Selects: 1
- * Number of Banks: 8
- * Row address: 14
- * Column address: 10
- */
-
- dram_vals[0x74 / 4] = 0x0102010A;
- dram_vals[0x98 / 4] = 0x04005003;
- dram_vals[0x9c / 4] = 0x090000c8;
-
- dram_vals[0xa8 / 4] = 0x0036b009;
- dram_vals[0xac / 4] = 0x03270612;
-
- dram_vals[0xb0 / 4] = 0x02020202;
- dram_vals[0xb4 / 4] = 0x00c80029;
-
- dram_vals[0xc0 / 4] = 0x00011900;
-
- dram_vals[0x12c / 4] = 0x07400300;
- dram_vals[0x130 / 4] = 0x07400300;
- dram_vals[0x2c4 / 4] = 0x02030303;
-}
-
-void board_init_ll(const uint32_t arg, const uint32_t *resptr)
-{
- mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
-}
void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE, MAP_NOCACHE);
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* CPU:775, DDR:650, AHB:258 */
qca956x_pll_init();
qca956x_ddr_init();
/* drive strength configs for sdhc pins */
const struct tlmm_cfg hdrv[] = {
-
+
{ SDC1_CLK_HDRV, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, },
{ SDC1_CMD_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, },
{ SDC1_DATA_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, },
/* pull configs for sdhc pins */
const struct tlmm_cfg pull[] = {
-
+
{ SDC1_CLK_PULL, TLMM_NO_PULL, TLMM_PULL_MASK, },
{ SDC1_CMD_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, },
{ SDC1_DATA_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, },
};
const struct tlmm_cfg rclk[] = {
-
+
{ SDC1_RCLK_PULL, TLMM_PULL_DOWN, TLMM_PULL_MASK,},
};
return 0;
}
-static void get_board_rev(void)
+static void get_board_revision(void)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1);
int ret;
hw_watchdog_init();
#endif
- get_board_rev();
+ get_board_revision();
gd->bd->bi_boot_params = 0x100;
int board_early_init_f(void)
{
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
* Copyright (C) 2017 Chris Brandt
*/
#include <config.h>
-#include <version.h>
#include <asm/macro.h>
/* Watchdog Registers */
int board_early_init_f(void)
{
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
void reset_cpu(void)
{
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
#else
/* only CA57 ? */
int board_early_init_f(void)
{
-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
#include <dm.h>
#include <asm/io.h>
#include <asm/arch-rockchip/uart.h>
-
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-
config SYS_CONFIG_NAME
default "imx8mq_cm"
+config IMX_CONFIG
+ default "board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg"
+
endif
}
#endif
-#if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC)
+#if CONFIG_IS_ENABLED(POWER_LEGACY) || CONFIG_IS_ENABLED(DM_PMIC)
int power_init_board(void)
{
set_ps_hold_ctrl();
{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
};
-static unsigned int odroid_get_rev(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
- if (odroid_info[i].board_type == gd->board_type)
- return odroid_info[i].board_rev;
- }
-
- return 0;
-}
-
/*
* Read ADC at least twice and check the resuls. If regulator providing voltage
* on to measured point was just turned on, first reads might require time
return false;
}
+#ifdef CONFIG_REVISION_TAG
+static unsigned int odroid_get_rev(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
+ if (odroid_info[i].board_type == gd->board_type)
+ return odroid_info[i].board_rev;
+ }
+
+ return 0;
+}
+
/**
* get_board_rev() - return detected board revision.
*
return odroid_get_rev();
}
+#endif
/**
* get_board_type() - returns board type string.
DECLARE_GLOBAL_DATA_PTR;
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
/* Set Initial global variables */
#include <asm/arch/pinmux.h>
#include <usb.h>
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int exynos_init(void)
{
return 0;
board_rev = modelrev << 8;
}
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
return board_rev;
}
+#endif
static inline u32 get_model_rev(void)
{
unsigned int board_rev;
static int init_pmic_lcd(void);
+#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
return board_rev;
}
+#endif
int exynos_power_init(void)
{
gd_t *gd;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-/* Add a simple GPIO device */
+/*
+ * Add a simple GPIO device (don't use with of-platdata as it interferes with
+ * the auto-generated devices)
+ */
U_BOOT_DRVINFO(gpio_sandbox) = {
.name = "sandbox_gpio",
};
config SYS_CONFIG_NAME
default "giedi"
+config IMX_CONFIG
+ default "board/siemens/capricorn/imximage.cfg"
endif
if TARGET_DENEB
config SYS_CONFIG_NAME
default "deneb"
+config IMX_CONFIG
+ default "board/siemens/capricorn/imximage.cfg"
+
endif
#endif /* #ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
+#define FACTORYSET_EEPROM_ADDR 0x50
/*
* Basic board specific setup. Pinmux has been handled already.
*/
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
- factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
+ factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR);
#endif
gpmc_init();
u8 nand_bus;
};
+#define EEPROM_ADDR 0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
static int draco_read_nand_geometry(void)
{
struct am335x_nand_geometry geo;
/* Read NAND geometry */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+ if (i2c_read(EEPROM_ADDR, 0x80, 2,
(uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
return -EIO;
static int read_eeprom(void)
{
/* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ if (i2c_probe(EEPROM_ADDR)) {
printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
return 1;
}
#ifdef CONFIG_SPL_BUILD
/* Read Siemens eeprom data (DDR3) */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
+ if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
(uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
set_default_ddr3_timings();
}
/* Read Siemens eeprom data (CHIP) */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
+ if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
(uchar *)&settings.chip, sizeof(settings.chip)))
printf("Could not read chip settings\n");
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) Siemens AG, 2018-2021
+#
+# Authors:
+# Le Jin <le.jin@siemens.com>
+# Jan Kiszka <jan.kiszka@siemens.com>
+
+config TARGET_IOT2050_A53
+ bool "IOT2050 running on A53"
+ select ARM64
+ select SOC_K3_AM6
+ select BOARD_LATE_INIT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+if TARGET_IOT2050_A53
+
+config SYS_BOARD
+ default "iot2050"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_CONFIG_NAME
+ default "iot2050"
+
+config IOT2050_BOOT_SWITCH
+ bool "Disable eMMC boot via USER button (Advanced version only)"
+ default y
+
+endif
--- /dev/null
+IOT2050 BOARD
+M: Le Jin <le.jin@siemens.com>
+M: Jan Kiszka <jan.kiszka@siemens.com>
+S: Maintained
+F: board/siemens/iot2050/
+F: include/configs/iot2050.h
+F: configs/iot2050_defconfig
+F: arch/arm/dts/iot2050-*
+F: doc/board/siemens/iot2050.rst
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile for Siemens IOT2050 board
+# Copyright (c) Siemens AG, 2018-2021
+#
+# Authors:
+# Le Jin <le.jin@siemens.com>
+#
+
+obj-y += board.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for IOT2050
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <dm.h>
+#include <i2c.h>
+#include <led.h>
+#include <malloc.h>
+#include <net.h>
+#include <phy.h>
+#include <spl.h>
+#include <version.h>
+#include <linux/delay.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define IOT2050_INFO_MAGIC 0x20502050
+
+struct iot2050_info {
+ u32 magic;
+ u16 size;
+ char name[20 + 1];
+ char serial[16 + 1];
+ char mlfb[18 + 1];
+ char uuid[32 + 1];
+ char a5e[18 + 1];
+ u8 mac_addr_cnt;
+ u8 mac_addr[8][ARP_HLEN];
+ char seboot_version[40 + 1];
+} __packed;
+
+/*
+ * Scratch SRAM (available before DDR RAM) contains extracted EEPROM data.
+ */
+#define IOT2050_INFO_DATA ((struct iot2050_info *) \
+ TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool board_is_advanced(void)
+{
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+
+ return info->magic == IOT2050_INFO_MAGIC &&
+ strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
+}
+
+static bool board_is_sr1(void)
+{
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+
+ return info->magic == IOT2050_INFO_MAGIC &&
+ !strstr((char *)info->name, "-PG2");
+}
+
+static void remove_mmc1_target(void)
+{
+ char *boot_targets = strdup(env_get("boot_targets"));
+ char *mmc1 = strstr(boot_targets, "mmc1");
+
+ if (mmc1) {
+ memmove(mmc1, mmc1 + 4, strlen(mmc1 + 4) + 1);
+ env_set("boot_targets", boot_targets);
+ }
+
+ free(boot_targets);
+}
+
+void set_board_info_env(void)
+{
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+ u8 __maybe_unused mac_cnt;
+ const char *fdtfile;
+
+ if (info->magic != IOT2050_INFO_MAGIC) {
+ pr_err("IOT2050: Board info parsing error!\n");
+ return;
+ }
+
+ if (env_get("board_uuid"))
+ return;
+
+ env_set("board_name", info->name);
+ env_set("board_serial", info->serial);
+ env_set("mlfb", info->mlfb);
+ env_set("board_uuid", info->uuid);
+ env_set("board_a5e", info->a5e);
+ env_set("fw_version", PLAIN_VERSION);
+ env_set("seboot_version", info->seboot_version);
+
+ if (IS_ENABLED(CONFIG_NET)) {
+ /* set MAC addresses to ensure forwarding to the OS */
+ for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) {
+ if (is_valid_ethaddr(info->mac_addr[mac_cnt]))
+ eth_env_set_enetaddr_by_index("eth",
+ mac_cnt + 1,
+ info->mac_addr[mac_cnt]);
+ }
+ }
+
+ if (board_is_advanced()) {
+ if (board_is_sr1())
+ fdtfile = "ti/k3-am6548-iot2050-advanced.dtb";
+ else
+ fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb";
+ } else {
+ if (board_is_sr1())
+ fdtfile = "ti/k3-am6528-iot2050-basic.dtb";
+ else
+ fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb";
+ /* remove the unavailable eMMC (mmc1) from the list */
+ remove_mmc1_target();
+ }
+ env_set("fdtfile", fdtfile);
+
+ env_save();
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (board_is_advanced())
+ gd->ram_size = SZ_2G;
+ else
+ gd->ram_size = SZ_1G;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ dram_init();
+
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = 0;
+ gd->bd->bi_dram[1].size = 0;
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+ char upper_name[32];
+
+ if (info->magic != IOT2050_INFO_MAGIC ||
+ strlen(name) >= sizeof(upper_name))
+ return -1;
+
+ str_to_upper(name, upper_name, sizeof(upper_name));
+ if (!strcmp(upper_name, (char *)info->name))
+ return 0;
+
+ return -1;
+}
+#endif
+
+int do_board_detect(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_IOT2050_BOOT_SWITCH
+static bool user_button_pressed(void)
+{
+ struct udevice *red_led = NULL;
+ unsigned long count = 0;
+ struct gpio_desc gpio;
+
+ memset(&gpio, 0, sizeof(gpio));
+
+ if (dm_gpio_lookup_name("25", &gpio) < 0 ||
+ dm_gpio_request(&gpio, "USER button") < 0 ||
+ dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN) < 0)
+ return false;
+
+ if (dm_gpio_get_value(&gpio) == 1)
+ return false;
+
+ printf("USER button pressed - booting from external media only\n");
+
+ led_get_by_label("status-led-red", &red_led);
+
+ if (red_led)
+ led_set_state(red_led, LEDST_ON);
+
+ while (dm_gpio_get_value(&gpio) == 0 && count++ < 10000)
+ mdelay(1);
+
+ if (red_led)
+ led_set_state(red_led, LEDST_OFF);
+
+ return true;
+}
+#endif
+
+#define SERDES0_LANE_SELECT 0x00104080
+
+int board_late_init(void)
+{
+ /* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */
+ writel(0x3, SERDES0_LANE_SELECT);
+
+ set_board_info_env();
+
+ /* remove the eMMC if requested via button */
+ if (IS_ENABLED(CONFIG_IOT2050_BOOT_SWITCH) && board_is_advanced() &&
+ user_button_pressed())
+ remove_mmc1_target();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+
+ ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+ if (ret < 0)
+ ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+ "sram@70000000");
+ if (ret)
+ pr_err("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+ return ret;
+}
+#endif
+
+void spl_board_init(void)
+{
+}
+
+#if CONFIG_IS_ENABLED(LED) && CONFIG_IS_ENABLED(BOOTSTAGE)
+/*
+ * Indicate any error or (accidental?) entering of CLI via the red status LED.
+ */
+void show_boot_progress(int progress)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (progress < 0 || progress == BOOTSTAGE_ID_ENTER_CLI_LOOP) {
+ ret = led_get_by_label("status-led-green", &dev);
+ if (ret == 0)
+ led_set_state(dev, LEDST_OFF);
+
+ ret = led_get_by_label("status-led-red", &dev);
+ if (ret == 0)
+ led_set_state(dev, LEDST_ON);
+ }
+}
+#endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) Siemens AG, 2020-2021
+#
+# Authors:
+# Jan Kiszka <jan.kiszka@siemens.com>
+
+flash.bin: all
--- /dev/null
+image sdcard.img {
+ size = 128M
+
+ hdimage {
+ gpt = true
+ }
+
+ partition u-boot-spl {
+ image = "u-boot-spl.bin"
+ offset = 17K
+ partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47
+ }
+
+ partition u-boot {
+ image = "u-boot.itb"
+ offset = 1041K
+ partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985
+ }
+}
--- /dev/null
+image spi-nor.img {
+ size = 32M
+
+ hdimage {
+ gpt = true
+ }
+
+ partition u-boot-spl {
+ image = "u-boot-spl.bin"
+ offset = 20K
+ partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47
+ }
+
+ partition u-boot {
+ image = "u-boot.itb"
+ offset = 1044K
+ partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985
+ }
+}
#if defined(CONFIG_SYS_NAND_BASE)
#include <nand.h>
#include <linux/errno.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
static int state;
config SYS_CONFIG_NAME
default "vining_2000"
+config IMX_CONFIG
+ default "board/softing/vining_2000/imximage.cfg"
+
endif
config SYS_CONFIG_NAME
default "somlabs_visionsom_6ull"
+config IMX_CONFIG
+ default "board/somlabs/visionsom-6ull/imximage.cfg"
+
endif
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
}
#ifdef CONFIG_STM32MP15x_STM32IMAGE
- if (!serial && CONFIG_IS_ENABLED(OPTEE) &&
- tee_find_device(NULL, NULL, NULL, NULL))
+ if (!serial && tee_find_device(NULL, NULL, NULL, NULL))
tee = true;
#endif
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
return 0;
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
return 0;
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
return 0;
{
return BOOT_DEVICE_XIP;
}
-
#endif
-u32 get_board_rev(void)
-{
- return 0;
-}
int board_late_init(void)
{
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
return 0;
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_init(void)
{
return 0;
return 0;
}
-u32 get_board_rev(void)
-{
- return 0;
-}
-
int board_late_init(void)
{
return 0;
#include <asm/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
+#include <dm/ofnode.h>
#include <jffs2/load_kernel.h>
#include <linux/bitops.h>
#include <linux/delay.h>
static int get_led(struct udevice **dev, char *led_string)
{
- char *led_name;
+ const char *led_name;
int ret;
- led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
+ led_name = ofnode_conf_read_str(led_string);
if (!led_name) {
log_debug("could not find %s config string\n", led_string);
return -ENOENT;
M: Stephan Gerhold <stephan@gerhold.net>
S: Maintained
F: board/ste/stemmy/
-F: include/configs/stemmy.h
F: configs/stemmy_defconfig
+F: doc/board/ste/stemmy.rst
+F: include/configs/stemmy.h
+++ /dev/null
-ST-Ericsson U8500 Samsung "stemmy" board
-========================================
-
-The "stemmy" board supports Samsung smartphones released with
-the ST-Ericsson NovaThor U8500 SoC, e.g.
-
- - Samsung Galaxy S III mini (GT-I8190) "golden"
- - Samsung Galaxy S Advance (GT-I9070) "janice"
- - Samsung Galaxy Xcover 2 (GT-S7710) "skomer"
- - Samsung Galaxy Ace 2 (GT-I8160) "codina"
-
-and likely others as well (untested).
-
-At the moment, U-Boot is intended to be chain-loaded from
-the original Samsung bootloader, not replacing it entirely.
-
-Installation
-------------
-
-1. Setup cross compiler, e.g. export CROSS_COMPILE=arm-none-eabi-
-2. make stemmy_defconfig
-3. make
-
-For newer devices (golden and skomer), the U-Boot binary has to be packed into
-an Android boot image. janice boots the raw U-Boot binary from the boot partition.
-
-4. Obtain mkbootimg, e.g. https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg
-5. mkbootimg \
- --kernel=u-boot.bin \
- --base=0x00000000 \
- --kernel_offset=0x00100000 \
- --ramdisk_offset=0x02000000 \
- --tags_offset=0x00000100 \
- --output=u-boot.img
-
-6. Enter Samsung download mode (press Power + Home + Volume Down)
-7. Flash U-Boot image to Android boot partition using Heimdall:
- https://gitlab.com/BenjaminDobell/Heimdall
-
- heimdall flash --Kernel u-boot.(bin|img)
-
-8. After reboot U-Boot prompt should appear via UART.
-
-UART
-----
-
-UART is available through the micro USB port, similar to the Carkit standard.
-With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-.
-
-Make sure to connect the UART cable *before* turning on the phone.
config SYS_CONFIG_NAME
default "smegw01"
+config IMX_CONFIG
+ default "board/storopack/smegw01/imximage.cfg"
+
endif
S: Maintained
F: configs/nanopi_neo_air_defconfig
+NANOPI-R1S-H5 BOARD
+M: Chukun Pan <amadeus@jmu.edu.cn>
+S: Maintained
+F: configs/nanopi_r1s_h5_defconfig
+
NANOPI-A64 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
S: Maintained
F: configs/pinephone_defconfig
+PINETAB BOARD
+M: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+S: Maintained
+F: configs/pinetab_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
#include <asm/arch/dram.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/prcm.h>
#include <asm/arch/spl.h>
#include <spl.h>
#include <sy8106a.h>
#include <asm/setup.h>
-
-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
-/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
-int soft_i2c_gpio_sda;
-int soft_i2c_gpio_scl;
-
-static int soft_i2c_board_init(void)
-{
- int ret;
-
- soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
- if (soft_i2c_gpio_sda < 0) {
- printf("Error invalid soft i2c sda pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
- return soft_i2c_gpio_sda;
- }
- ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
- if (ret) {
- printf("Error requesting soft i2c sda pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
- return ret;
- }
-
- soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
- if (soft_i2c_gpio_scl < 0) {
- printf("Error invalid soft i2c scl pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
- return soft_i2c_gpio_scl;
- }
- ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
- if (ret) {
- printf("Error requesting soft i2c scl pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
- return ret;
- }
-
- return 0;
-}
-#else
-static int soft_i2c_board_init(void) { return 0; }
-#endif
+#include <status_led.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#endif /* CONFIG_DM_MMC */
- /* Uses dm gpio code so do this here and not in i2c_init_board() */
- return soft_i2c_board_init();
+ return 0;
}
/*
static void mmc_pinmux_setup(int sdc)
{
unsigned int pin;
- __maybe_unused int pins;
switch (sdc) {
case 0:
break;
case 1:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
- if (pins == SUNXI_GPIO_H) {
+ if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
/* SDC1: PH22-PH-27 */
for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN8I)
- if (pins == SUNXI_GPIO_D) {
- /* SDC1: PD2-PD7 */
- for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC1: PG0-PG5 */
- for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
#endif
break;
case 2:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* SDC2: PC6-PC11 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN5I)
- if (pins == SUNXI_GPIO_E) {
- /* SDC2: PE4-PE9 */
- for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC2: PC6-PC15 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
+ /* SDC2: PC6-PC15 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN6I)
- if (pins == SUNXI_GPIO_A) {
- /* SDC2: PA9-PA14 */
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC2: PC6-PC15, PC24 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-
- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ /* SDC2: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#elif defined(CONFIG_MACH_SUN8I_R40)
/* SDC2: PC6-PC15, PC24 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
break;
case 3:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
/* SDC3: PI4-PI9 */
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN6I)
- if (pins == SUNXI_GPIO_A) {
- /* SDC3: PA9-PA14 */
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC3: PC6-PC15, PC24 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-
- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ /* SDC3: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#endif
break;
{
int power_failed = 0;
+#ifdef CONFIG_LED_STATUS
+ if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
+ status_led_init();
+#endif
+
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
void eth_init_board(void)
{
};
#endif /* _BOARD_SYNOPSYS_AXS10X_H */
-
if (env_common.core_mask.val == ALL_CPU_MASK)
return 0;
- if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
+ if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !images->ft_len) {
pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
return 0;
}
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
*/
-.equ PPMCR0, 0xfc04002d
+.equ PPMCR0, 0xfc04002d
.equ MSCR_SDRAMC, 0xec094060
.equ MISCCR2, 0xec09001a
.equ DDR_RCR, 0xfc0b8180
+++ /dev/null
-if TARGET_ZMX25
-
-config SYS_BOARD
- default "zmx25"
-
-config SYS_VENDOR
- default "syteco"
-
-config SYS_SOC
- default "mx25"
-
-config SYS_CONFIG_NAME
- default "zmx25"
-
-endif
+++ /dev/null
-ZMX25 BOARD
-M: Matthias Weisser <weisserm@arcor.de>
-S: Maintained
-F: board/syteco/zmx25/
-F: include/configs/zmx25.h
-F: configs/zmx25_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (c) 2010 Graf-Syteco, Matthias Weisser
-# <weisserm@arcor.de>
-
-obj-y += zmx25.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Matthias Weisser <weisserm@arcor.de>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on U-Boot and RedBoot sources for several different i.mx
- * platforms.
- */
-
-#include <asm/macro.h>
-#include <asm/arch/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-/*
- * clocks
- */
-.macro init_clocks
-
- /* disable clock output */
- write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
- write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
-
- /*
- * enable all implemented clocks in all three
- * clock control registers
- */
- write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
- write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
- write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
-
- /* Devide NAND clock by 32 */
- write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
-.endm
-
-/*
- * sdram controller init
- */
-.macro init_lpddr
- ldr r0, =IMX_ESDRAMC_BASE
- ldr r2, =IMX_SDRAM_BANK0_BASE
-
- /*
- * reset SDRAM controller
- * then wait for initialization to complete
- */
- ldr r1, =(1 << 1) | (1 << 2)
- str r1, [r0, #ESDRAMC_ESDMISC]
-1: ldr r3, [r0, #ESDRAMC_ESDMISC]
- tst r3, #(1 << 31)
- beq 1b
- ldr r1, =(1 << 2)
- str r1, [r0, #ESDRAMC_ESDMISC]
-
- ldr r1, =0x002a7420
- str r1, [r0, #ESDRAMC_ESDCFG0]
-
- /* control | precharge */
- ldr r1, =0x92216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
- /* dram command encoded in address */
- str r1, [r2, #0x400]
-
- /* auto refresh */
- ldr r1, =0xa2216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
- /* read dram twice to auto refresh */
- ldr r3, [r2]
- ldr r3, [r2]
-
- /* control | load mode */
- ldr r1, =0xb2216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
-
- /* mode register of lpddram */
- strb r1, [r2, #0x33]
-
- /* extended mode register of lpddrram */
- ldr r2, =0x81000000
- strb r1, [r2]
-
- /* control | normal */
- ldr r1, =0x82216008
- str r1, [r0, #ESDRAMC_ESDCTL0]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- init_aips
- init_max
- init_clocks
- init_lpddr
- mov pc, lr
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (c) 2011 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * Based on tx25.c:
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on imx27lite.c:
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- * And:
- * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
- */
-#include <common.h>
-#include <cpu_func.h>
-#include <env.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx25.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init()
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t dig_out_pads[] = {
- MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
- MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
- NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
- NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
- };
-
- static const iomux_v3_cfg_t led_pads[] = {
- MX25_PAD_CSI_D9__GPIO_4_21,
- MX25_PAD_CSI_D4__GPIO_1_29,
- };
-
- static const iomux_v3_cfg_t can_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t i2c3_pads[] = {
- MX25_PAD_CSPI1_SS1__I2C3_DAT,
- MX25_PAD_GPIO_E__I2C3_CLK,
- };
-
- icache_enable();
-
- /* Setup of core voltage selection pin to run at 1.4V */
- imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
- gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
-
- /* Setup of SD card pins*/
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- /* Setup of digital output for USB power and OC */
- imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
- gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
-
- imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
- gpio_direction_input(IMX_GPIO_NR(1, 18));
-
- /* Setup of digital output control pins */
- imx_iomux_v3_setup_multiple_pads(dig_out_pads,
- ARRAY_SIZE(dig_out_pads));
-
- /* Switch both output drivers off */
- gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
- gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
-
- /* Setup of key input pin */
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
- gpio_direction_input(IMX_GPIO_NR(2, 29));
-
- /* Setup of status LED outputs */
- imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
-
- /* Switch both LEDs off */
- gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
- gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
-
- /* Setup of CAN1 and CAN2 signals */
- imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
-
- /* Setup of I2C3 signals */
- imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
-
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- const char *e;
-
-#ifdef CONFIG_FEC_MXC
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define FEC_OUT_PAD_CTRL 0
-
- static const iomux_v3_cfg_t fec_pads[] = {
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX25_PAD_FEC_RX_DV__FEC_RX_DV,
- MX25_PAD_FEC_RDATA0__FEC_RDATA0,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
- MX25_PAD_FEC_MDIO__FEC_MDIO,
- MX25_PAD_FEC_RDATA1__FEC_RDATA1,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
-
- MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
- MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
- /* assert PHY reset (low) */
- gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
-
- udelay(5000);
-
- /* deassert PHY reset */
- gpio_set_value(IMX_GPIO_NR(3, 16), 1);
-
- udelay(5000);
-#endif
-
- e = env_get("gs_base_board");
- if (e != NULL) {
- if (strcmp(e, "G283") == 0) {
- int key = gpio_get_value(IMX_GPIO_NR(2, 29));
-
- if (key) {
- /* Switch on both LEDs to inidcate boot mode */
- gpio_set_value(IMX_GPIO_NR(1, 29), 0);
- gpio_set_value(IMX_GPIO_NR(4, 21), 0);
-
- env_set("preboot", "run gs_slow_boot");
- } else
- env_set("preboot", "run gs_fast_boot");
- }
- }
-
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- PHYS_SDRAM_SIZE);
- return 0;
-}
#
# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static const struct ddr_data ddr3_sl50_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
const struct dpll_params *get_dpll_ddr_params(void)
{
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return &dpll_ddr_sl50;
}
return 0;
}
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 3
int power_init_board(void)
{
}
return 0;
}
-
config SYS_CONFIG_NAME
default "pico-imx8mq"
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
endif
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* _PRELOADER_PLL_CONFIG_H_ */
-
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
{
enable_i2c0_pin_mux();
enable_i2c2_pin_mux();
-#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2);
-#endif
if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS))
printf("ti_i2c_eeprom_init failed\n");
}
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
return;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- if (i2c_probe(TPS65217_CHIP_PM))
- return;
-#else
if (power_tps65217_init(0))
return;
-#endif
/*
* 1.10V. For MPU voltage we need to switch based on
* the frequency we are running at.
*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
- if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
- return;
-#else
if (power_tps65910_init(0))
return;
-#endif
/*
* Depending on MPU clock and PG we will need a different
* VDD to drive at that speed.
if (first_time) {
enable_i2c0_pin_mux();
-#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
first_time = false;
}
}
static unsigned short detect_daughter_board_profile(void)
{
unsigned short val;
-
-#if !CONFIG_IS_ENABLED(DM_I2C)
- if (i2c_probe(I2C_CPLD_ADDR))
- return PROFILE_NONE;
-
- if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
- return PROFILE_NONE;
-#else
struct udevice *dev = NULL;
int rc;
rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
if (rc)
return PROFILE_NONE;
-#endif
return (1 << (val & PROFILE_MASK));
}
#
# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
}
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */
{
int mpu_vdd, ddr_volt;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- if (i2c_probe(TPS65218_CHIP_PM))
- return;
-#else
if (power_tps65218_init(0))
return;
-#endif
switch (m) {
case 1000:
{
int mpu_vdd;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- if (i2c_probe(TPS62362_I2C_ADDR))
- return;
-#else
if (power_tps62362_init(0))
return;
-#endif
switch (m) {
case 1000:
if (first_time) {
enable_i2c0_pin_mux();
-#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
first_time = false;
}
}
int power_init_board(void)
{
int rc;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- struct pmic *p = NULL;
-#endif
if (board_is_idk()) {
rc = power_tps62362_init(0);
if (rc)
goto done;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- p = pmic_get("TPS62362");
- if (!p || pmic_probe(p))
- goto done;
-#endif
puts("PMIC: TPS62362\n");
} else {
rc = power_tps65218_init(0);
if (rc)
goto done;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- p = pmic_get("TPS65218_PMIC");
- if (!p || pmic_probe(p))
- goto done;
-#endif
puts("PMIC: TPS65218\n");
}
done:
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
{0x0884, 0, 0}, /* CFG_UART2_RTSN_OUT */
{0x0888, 683, 0}, /* CFG_UART2_RXD_IN */
{0x088C, 0, 0}, /* CFG_UART2_RXD_OEN */
- {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */
+ {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */
{0x0894, 835, 0}, /* CFG_UART2_TXD_IN */
{0x0898, 0, 0}, /* CFG_UART2_TXD_OEN */
{0x089C, 0, 0}, /* CFG_UART2_TXD_OUT */
{0x0C48, 0, 404}, /* CFG_VOUT1_D22_IN */
{0x0C78, 0, 0}, /* CFG_VOUT1_D4_IN */
{0x0C84, 0, 365}, /* CFG_VOUT1_D5_IN */
- {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */
+ {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */
{0x0C9C, 0, 218}, /* CFG_VOUT1_D7_IN */
};
#endif
#endif
+#ifdef CONFIG_REVISION_TAG
/*
* get_board_rev() - get board revision
*/
{
return 0x20;
}
+#endif
}
#endif /* CONFIG_SPL_OS_BOOT */
+#ifdef CONFIG_REVISION_TAG
/*
* get_board_rev() - get board revision
*/
{
return 0x20;
}
+#endif
config TDX_CFG_BLOCK_OFFSET
default "-512"
+config IMX_CONFIG
+ default "board/toradex/apalis-imx8/apalis-imx8-imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
config TDX_CFG_BLOCK_OFFSET
default "-512"
+config IMX_CONFIG
+ default "board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
This option configures DCE mode unconditionally. Whithout this
option the config block stating V1.0 HW selects DCE mode,
otherwise the UARTs are configuered in DTE mode.
- default n
source "board/toradex/common/Kconfig"
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#if defined(CONFIG_REVISION_TAG) && \
- defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
char env_str[256];
u32 rev;
- rev = get_board_rev();
+ rev = get_board_revision();
snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
env_set("board_rev", env_str);
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
+config IMX_CONFIG
+ default "board/toradex/colibri-imx6ull/imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
config TDX_CFG_BLOCK_OFFSET
default "-512"
+config IMX_CONFIG
+ default "board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#if defined(CONFIG_REVISION_TAG) && \
- defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
char env_str[256];
u32 rev;
- rev = get_board_rev();
+ rev = get_board_revision();
snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
env_set("board_rev", env_str);
#endif
endif
+config IMX_CONFIG
+ default "board/toradex/colibri_imx7/imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
+config IMX_CONFIG
+ default "board/toradex/colibri_vf/imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
else
tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
}
-#ifdef CONFIG_MACH_TYPE
+#if defined(CONFIG_TARGET_APALIS_T30) || defined(CONFIG_TARGET_COLIBRI_T30)
else if (!strcmp("tegra30", soc)) {
- if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
- if (it == 'y' || it == 'Y')
- tdx_hw_tag.prodid = APALIS_T30_IT;
- else
- if (gd->ram_size == 0x40000000)
- tdx_hw_tag.prodid = APALIS_T30_1GB;
- else
- tdx_hw_tag.prodid = APALIS_T30_2GB;
- } else {
- if (it == 'y' || it == 'Y')
- tdx_hw_tag.prodid = COLIBRI_T30_IT;
+#ifdef CONFIG_TARGET_APALIS_T30
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = APALIS_T30_IT;
+ else
+ if (gd->ram_size == 0x40000000)
+ tdx_hw_tag.prodid = APALIS_T30_1GB;
else
- tdx_hw_tag.prodid = COLIBRI_T30;
- }
+ tdx_hw_tag.prodid = APALIS_T30_2GB;
+#else
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_T30_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_T30;
+#endif
}
-#endif /* CONFIG_MACH_TYPE */
+#endif /* CONFIG_TARGET_APALIS_T30 || CONFIG_TARGET_COLIBRI_T30 */
else if (!strcmp("tegra124", soc)) {
tdx_hw_tag.prodid = APALIS_TK1_2GB;
} else if (!strcmp("vf500", soc)) {
static char *tdx_carrier_board_name;
#endif
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+u32 get_board_revision(void)
{
/* Check validity */
if (!tdx_hw_tag.ver_major)
#else /* CONFIG_TDX_CFG_BLOCK */
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+u32 get_board_revision(void)
{
return 0;
}
#define TDX_USB_VID 0x1B67
int ft_common_board_setup(void *blob, struct bd_info *bd);
+u32 get_board_revision(void);
#if defined(CONFIG_DM_VIDEO)
int show_boot_logo(void);
config TDX_CFG_BLOCK_OFFSET
default "-512"
+config IMX_CONFIG
+ default "board/toradex/verdin-imx8mm/imximage.cfg"
+
source "board/toradex/common/Kconfig"
endif
wdr4300_pinmux_config();
#endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
ar934x_pll_init(560, 480, 240);
ar934x_ddr_init(560, 480, 240);
#endif
#endif
#endif
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
static struct i2c_pads_info tqma6_i2c3_pads = {
/* I2C3: on board LM75, M24C64, */
.scl = {
#ifndef CONFIG_DM_SPI
tqma6_iomuxc_spi();
#endif
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
tqma6_setup_i2c();
#endif
};
}
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
/* setup board specific PMIC */
int power_init_board(void)
{
};
#endif
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
int power_init_board(void)
{
struct pmic *p;
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-endif
-endif
+++ /dev/null
-/* EEPROM init functions for Cyrus */
-
-
-void init_eeprom(int bus_num, int addr, int addr_len);
-void mac_read_from_fixed_id(void);
-int mac_read_from_eeprom_common(void);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Based on board/freescale/common/sys_eeprom.c
- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
- *
- * This defines the API for storing board information in the
- * eeprom. It has been adapted from an earlier version of the
- * Freescale API, but has a number of key differences. Because
- * the two APIs are independent and may diverge further, the
- * Varisys version of the API is implemented separately here.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-#include <linux/delay.h>
-#include <u-boot/crc.h>
-
-#include "eeprom.h"
-
-#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
-#define MAX_NUM_PORTS CONFIG_SYS_I2C_EEPROM_NXID_MAC
-#else
-#define MAX_NUM_PORTS 8
-#endif
-#define NXID_VERSION 0
-
-/**
- * static eeprom: EEPROM layout for NXID formats
- *
- * See Freescale application note AN3638 for details.
- */
-static struct __attribute__ ((__packed__)) eeprom {
- u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
- u8 sn[12]; /* 0x04 - 0x0F Serial Number */
- u8 errata[5]; /* 0x10 - 0x14 Errata Level */
- u8 date[6]; /* 0x15 - 0x1a Build Date */
- u8 res_0; /* 0x1b Reserved */
- u32 version; /* 0x1c - 0x1f NXID Version */
- u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */
- u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
- u8 tempcalflags; /* 0x2a Temperature Calibration Flags */
- u8 res_1[21]; /* 0x2b - 0x3f Reserved */
- u8 mac_count; /* 0x40 Number of MAC addresses */
- u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
- u32 crc; /* x+1 CRC32 checksum */
-} e;
-
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
-
-/* Is this a valid NXID EEPROM? */
-#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
- (e.id[2] == 'I') || (e.id[3] == 'D'))
-
-/** Fixed ID field in EEPROM */
-static unsigned char uid[16];
-
-static int eeprom_bus_num = -1;
-static int eeprom_addr;
-static int eeprom_addr_len;
-
-/**
- * This must be called before any eeprom access.
- */
-void init_eeprom(int bus_num, int addr, int addr_len)
-{
- eeprom_bus_num = bus_num;
- eeprom_addr = addr;
- eeprom_addr_len = addr_len;
-}
-
-/**
- * show_eeprom - display the contents of the EEPROM
- */
-void show_eeprom(void)
-{
- int i;
- unsigned int crc;
-
- /* EEPROM tag ID, either CCID or NXID */
- printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
- be32_to_cpu(e.version));
-
- /* Serial number */
- printf("SN: %s\n", e.sn);
-
- printf("UID: ");
- for (i = 0; i < 16; i++)
- printf("%02x", uid[i]);
- printf("\n");
-
- /* Errata level. */
- printf("Errata: %s\n", e.errata);
-
- /* Build date, BCD date values, as YYMMDDhhmmss */
- printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
- e.date[0], e.date[1], e.date[2],
- e.date[3] & 0x7F, e.date[4], e.date[5],
- e.date[3] & 0x80 ? "PM" : "");
-
- /* Show MAC addresses */
- for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
- u8 *p = e.mac[i];
-
- printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
- p[0], p[1], p[2], p[3], p[4], p[5]);
- }
-
- crc = crc32(0, (void *)&e, sizeof(e) - 4);
-
- if (crc == be32_to_cpu(e.crc))
- printf("CRC: %08x\n", be32_to_cpu(e.crc));
- else
- printf("CRC: %08x (should be %08x)\n",
- be32_to_cpu(e.crc), crc);
-
-#ifdef DEBUG
- printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
- for (i = 0; i < sizeof(e); i++) {
- if ((i % 16) == 0)
- printf("%02X: ", i);
- printf("%02X ", ((u8 *)&e)[i]);
- if (((i % 16) == 15) || (i == sizeof(e) - 1))
- printf("\n");
- }
-#endif
-}
-
-/**
- * read_eeprom - read the EEPROM into memory
- */
-int read_eeprom(void)
-{
- int ret;
- unsigned int bus;
-
- if (eeprom_bus_num < 0) {
- printf("EEPROM not configured\n");
- return -1;
- }
-
- if (has_been_read)
- return 0;
-
- bus = i2c_get_bus_num();
- i2c_set_bus_num(eeprom_bus_num);
-
- ret = i2c_read(eeprom_addr, 0, eeprom_addr_len,
- (void *)&e, sizeof(e));
-
-
- /* Fixed address of ID field */
- i2c_read(0x5f, 0x80, 1, uid, 16);
-
- i2c_set_bus_num(bus);
-
-#ifdef DEBUG
- show_eeprom();
-#endif
-
- has_been_read = (ret == 0) ? 1 : 0;
-
- return ret;
-}
-
-/**
- * update_crc - update the CRC
- *
- * This function should be called after each update to the EEPROM structure,
- * to make sure the CRC is always correct.
- */
-static void update_crc(void)
-{
- u32 crc, crc_offset = offsetof(struct eeprom, crc);
-
- crc = crc32(0, (void *)&e, crc_offset);
- e.crc = cpu_to_be32(crc);
-}
-
-/**
- * prog_eeprom - write the EEPROM from memory
- */
-static int prog_eeprom(void)
-{
- int ret = 0;
- int i;
- void *p;
- unsigned int bus;
-
- if (eeprom_bus_num < 0) {
- printf("EEPROM not configured\n");
- return -1;
- }
-
- /* Set the reserved values to 0xFF */
- e.res_0 = 0xFF;
- memset(e.res_1, 0xFF, sizeof(e.res_1));
- update_crc();
-
- bus = i2c_get_bus_num();
- i2c_set_bus_num(eeprom_bus_num);
-
- /*
- * The AT24C02 datasheet says that data can only be written in page
- * mode, which means 8 bytes at a time, and it takes up to 5ms to
- * complete a given write.
- */
- for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
- ret = i2c_write(eeprom_addr, i, eeprom_addr_len,
- p, min((int)(sizeof(e) - i), 8));
- if (ret)
- break;
- udelay(5000); /* 5ms write cycle timing */
- }
-
- if (!ret) {
- /* Verify the write by reading back the EEPROM and comparing */
- struct eeprom e2;
-
- ret = i2c_read(eeprom_addr, 0,
- eeprom_addr_len, (void *)&e2, sizeof(e2));
- if (!ret && memcmp(&e, &e2, sizeof(e)))
- ret = -1;
- }
-
- i2c_set_bus_num(bus);
-
- if (ret) {
- printf("Programming failed.\n");
- has_been_read = 0;
- return -1;
- }
-
- printf("Programming passed.\n");
- return 0;
-}
-
-/**
- * h2i - converts hex character into a number
- *
- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
- * the integer equivalent.
- */
-static inline u8 h2i(char p)
-{
- if ((p >= '0') && (p <= '9'))
- return p - '0';
-
- if ((p >= 'A') && (p <= 'F'))
- return (p - 'A') + 10;
-
- if ((p >= 'a') && (p <= 'f'))
- return (p - 'a') + 10;
-
- return 0;
-}
-
-/**
- * set_date - stores the build date into the EEPROM
- *
- * This function takes a pointer to a string in the format "YYMMDDhhmmss"
- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
- * and stores it in the build date field of the EEPROM local copy.
- */
-static void set_date(const char *string)
-{
- unsigned int i;
-
- if (strlen(string) != 12) {
- printf("Usage: mac date YYMMDDhhmmss\n");
- return;
- }
-
- for (i = 0; i < 6; i++)
- e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
-
- update_crc();
-}
-
-/**
- * set_mac_address - stores a MAC address into the EEPROM
- *
- * This function takes a pointer to MAC address string
- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
- * stores it in one of the MAC address fields of the EEPROM local copy.
- */
-static void set_mac_address(unsigned int index, const char *string)
-{
- char *p = (char *)string;
- unsigned int i;
-
- if ((index >= MAX_NUM_PORTS) || !string) {
- printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
- return;
- }
-
- for (i = 0; *p && (i < 6); i++) {
- e.mac[index][i] = hextoul(p, &p);
- if (*p == ':')
- p++;
- }
-
- update_crc();
-}
-
-int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- char cmd;
-
- if (argc == 1) {
- show_eeprom();
- return 0;
- }
-
- cmd = argv[1][0];
-
- if (cmd == 'r') {
- read_eeprom();
- return 0;
- }
-
- if (cmd == 'i') {
- memcpy(e.id, "NXID", sizeof(e.id));
- e.version = NXID_VERSION;
- update_crc();
- return 0;
- }
-
- if (!is_valid) {
- printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
- return 0;
- }
-
- if (argc == 2) {
- switch (cmd) {
- case 's': /* save */
- prog_eeprom();
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
- }
-
- /* We know we have at least one parameter */
-
- switch (cmd) {
- case 'n': /* serial number */
- memset(e.sn, 0, sizeof(e.sn));
- strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
- update_crc();
- break;
- case 'e': /* errata */
- memset(e.errata, 0, 5);
- strncpy((char *)e.errata, argv[2], 4);
- update_crc();
- break;
- case 'd': /* date BCD format YYMMDDhhmmss */
- set_date(argv[2]);
- break;
- case 'p': /* MAC table size */
- e.mac_count = hextoul(argv[2], NULL);
- update_crc();
- break;
- case '0' ... '9': /* "mac 0" through "mac 22" */
- set_mac_address(dectoul(argv[1], NULL), argv[2]);
- break;
- case 'h': /* help */
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
-}
-
-int mac_read_from_generic_eeprom(const char *envvar, int chip,
- int address, int mac_bus)
-{
- int ret;
- unsigned int bus;
- unsigned char mac[6];
- char ethaddr[18];
-
- bus = i2c_get_bus_num();
- i2c_set_bus_num(mac_bus);
-
- ret = i2c_read(chip, address, 1, mac, 6);
-
- i2c_set_bus_num(bus);
-
- if (!ret) {
- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
- mac[0],
- mac[1],
- mac[2],
- mac[3],
- mac[4],
- mac[5]);
-
- printf("MAC: %s\n", ethaddr);
- env_set(envvar, ethaddr);
- }
-
- return ret;
-}
-
-void mac_read_from_fixed_id(void)
-{
-#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR
- mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR,
- CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS);
-#endif
-#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR
- mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR,
- CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS);
-#endif
-}
-
-/**
- * mac_read_from_eeprom - read the MAC addresses from EEPROM
- *
- * This function reads the MAC addresses from EEPROM and sets the
- * appropriate environment variables for each one read.
- *
- * The environment variables are only set if they haven't been set already.
- * This ensures that any user-saved variables are never overwritten.
- *
- * This function must be called after relocation.
- *
- * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
- * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is
- * located at a different offset.
- */
-int mac_read_from_eeprom_common(void)
-{
- unsigned int i;
- u32 crc, crc_offset = offsetof(struct eeprom, crc);
- u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
-
- puts("EEPROM: ");
-
- if (read_eeprom()) {
- printf("Read failed.\n");
- return 0;
- }
-
- if (!is_valid) {
- printf("Invalid ID (%02x %02x %02x %02x)\n",
- e.id[0], e.id[1], e.id[2], e.id[3]);
- return 0;
- }
-
- crc = crc32(0, (void *)&e, crc_offset);
- crcp = (void *)&e + crc_offset;
- if (crc != be32_to_cpu(*crcp)) {
- printf("CRC mismatch (%08x != %08x)\n", crc,
- be32_to_cpu(e.crc));
- return 0;
- }
-
- /*
- * MAC address #9 in v1 occupies the same position as the CRC in v0.
- * Erase it so that it's not mistaken for a MAC address. We'll
- * update the CRC later.
- */
- if (e.version == 0)
- memset(e.mac[8], 0xff, 6);
-
- for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
- if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
- memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
- char ethaddr[18];
- char enetvar[9];
-
- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
- e.mac[i][0],
- e.mac[i][1],
- e.mac[i][2],
- e.mac[i][3],
- e.mac[i][4],
- e.mac[i][5]);
- sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
- /* Only initialize environment variables that are blank
- * (i.e. have not yet been set)
- */
- if (!env_get(enetvar))
- env_set(enetvar, ethaddr);
- }
- }
-
- printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
- be32_to_cpu(e.version));
-
- return 0;
-}
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
*/
i2c_set_bus_num(1);
- printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
+ printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED);
if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
puts("i2c: cannot access TPS65910\n");
config SYS_CONFIG_NAME
default "warp"
+config IMX_CONFIG
+ default "board/warp/imximage.cfg"
+
endif
help
The address the FDT file should be loaded to.
+config IMX_CONFIG
+ default "board/warp7/imximage.cfg"
+
endif
This will generate the U-Boot binary called u-boot-dtb.imx.
-Put warp7 board in USB download mode:
+Put warp7 board in USB download mode:
Remove the CPU board from the base board then put switch 2 in the upper
position
int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-#ifdef CONFIG_SERIAL_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
struct tag_serialnr serialnr;
char serial_string[0x20];
#endif
env_set_ulong(HAB_ENABLED_ENVNAME, 0);
#endif
-#ifdef CONFIG_SERIAL_TAG
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Set serial# standard environment variable based on OTP settings */
get_board_serial(&serialnr);
snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
#include <env.h>
#include <spi.h>
#include <i2c.h>
+#include <timestamp.h>
#include <version.h>
#include <vsprintf.h>
#include <linux/delay.h>
#include <common.h>
#include <nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
/*
"versal sub-system",
versal_help_text
)
-
#include <fdtdec.h>
#include <fpga.h>
#include <malloc.h>
+#include <memalign.h>
#include <mmc.h>
#include <watchdog.h>
#include <wdt.h>
return ENVL_NOWHERE;
}
}
+
+#if defined(CONFIG_SET_DFU_ALT_INFO)
+
+#define DFU_ALT_BUF_LEN SZ_1K
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+ if (env_get("dfu_alt_info"))
+ return;
+
+ memset(buf, 0, sizeof(buf));
+
+ switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+ case ZYNQ_BM_SD:
+ snprintf(buf, DFU_ALT_BUF_LEN,
+ "mmc 0:1=boot.bin fat 0 1;"
+ "u-boot.img fat 0 1");
+ break;
+ case ZYNQ_BM_QSPI:
+ snprintf(buf, DFU_ALT_BUF_LEN,
+ "sf 0:0=boot.bin raw 0 0x1500000;"
+ "u-boot.img raw 0x%x 0x500000",
+ CONFIG_SYS_SPI_U_BOOT_OFFS);
+ break;
+ default:
+ return;
+ }
+
+ env_set("dfu_alt_info", buf);
+ puts("DFU alt info setting: done\n");
+}
+#endif
//
};
-
-
#include "xil_io.h"
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
ret = ps7_config (ps7_ddr_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
-
-
// Peripherals init
ret = ps7_config (ps7_peripherals_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
//
};
-
-
#include "xil_io.h"
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
ret = ps7_config (ps7_ddr_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
-
-
// Peripherals init
ret = ps7_config (ps7_peripherals_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
//
};
-
-
#include "xil_io.h"
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
ret = ps7_config (ps7_ddr_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
-
-
// Peripherals init
ret = ps7_config (ps7_peripherals_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
//
};
-
-
#include "xil_io.h"
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
ret = ps7_config (ps7_ddr_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
-
-
// Peripherals init
ret = ps7_config (ps7_peripherals_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
return ret;
return PS7_INIT_SUCCESS;
}
-
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+ u32 lane2_protocol, u32 lane2_rate,
+ u32 lane1_protocol, u32 lane1_rate,
+ u32 lane0_protocol, u32 lane0_rate);
+
+static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
+ int d_lock_cnt, int d_lfhf, int d_cp, int d_res);
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+ psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+ serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0);
+ psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U);
+ psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+ int cur_PLLCR0;
+
+ cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL0PLLCR0;
+
+ cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL1PLLCR0;
+
+ cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL2PLLCR0;
+
+ cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL3PLLCR0;
+
+ cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL4PLLCR0;
+
+ cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SLBPLLCR0;
+
+ cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+ Xil_Out32(0xFD080068, 0x02120000);
+ Xil_Out32(0xFD081404, 0x02120000);
+ Xil_Out32(0xFD081444, 0x02120000);
+ Xil_Out32(0xFD081484, 0x02120000);
+ Xil_Out32(0xFD0814C4, 0x02120000);
+ Xil_Out32(0xFD081504, 0x02120000);
+ Xil_Out32(0xFD0817C4, 0x02120000);
+ int cur_div2;
+
+ cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U;
+ int cur_fbdiv;
+
+ cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+ dpll_prog(1, 49, 63, 625, 3, 3, 2);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return 0;
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+ Xil_Out32(0xFD0800C0U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000331U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000B36U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000C56U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000E19U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00001616U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ Xil_Out32(0xFD070010U, 0x80000010U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+ prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+ prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+ prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ Xil_Out32(0xFD080068, cur_PLLCR0);
+ Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+ Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+ Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+ Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+ Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+ Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2);
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+ prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+ prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+ prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0014FE01);
+
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x8000007E)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x000091C7U);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80008FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+ prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+ prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+ Xil_Out32(0xFD070180U, 0x02160010U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+ for (int tp = 0; tp < 4000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+ prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+ prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+ prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+ prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+ prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ return 1;
+}
+
+static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate,
+ u32 lane2_protocol, u32 lane2_rate,
+ u32 lane1_protocol, u32 lane1_rate,
+ u32 lane0_protocol, u32 lane0_rate)
+{
+ Xil_Out32(0xFD410098, 0x00000000);
+ Xil_Out32(0xFD401010, 0x00000040);
+ Xil_Out32(0xFD405010, 0x00000040);
+ Xil_Out32(0xFD409010, 0x00000040);
+ Xil_Out32(0xFD40D010, 0x00000040);
+ Xil_Out32(0xFD402084, 0x00000080);
+ Xil_Out32(0xFD406084, 0x00000080);
+ Xil_Out32(0xFD40A084, 0x00000080);
+ Xil_Out32(0xFD40E084, 0x00000080);
+ Xil_Out32(0xFD410098, 0x00000004);
+ mask_delay(50);
+ if (lane0_rate == 1)
+ Xil_Out32(0xFD410098, 0x0000000E);
+ Xil_Out32(0xFD410098, 0x00000006);
+ if (lane0_rate == 1) {
+ Xil_Out32(0xFD40000C, 0x00000004);
+ Xil_Out32(0xFD40400C, 0x00000004);
+ Xil_Out32(0xFD40800C, 0x00000004);
+ Xil_Out32(0xFD40C00C, 0x00000004);
+ Xil_Out32(0xFD410098, 0x00000007);
+ mask_delay(400);
+ Xil_Out32(0xFD40000C, 0x0000000C);
+ Xil_Out32(0xFD40400C, 0x0000000C);
+ Xil_Out32(0xFD40800C, 0x0000000C);
+ Xil_Out32(0xFD40C00C, 0x0000000C);
+ mask_delay(15);
+ Xil_Out32(0xFD410098, 0x0000000F);
+ mask_delay(100);
+ }
+ if (pllsel == 0)
+ mask_poll(0xFD4023E4, 0x00000010U);
+ if (pllsel == 1)
+ mask_poll(0xFD4063E4, 0x00000010U);
+ if (pllsel == 2)
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ if (pllsel == 3)
+ mask_poll(0xFD40E3E4, 0x00000010U);
+ mask_delay(50);
+ Xil_Out32(0xFD401010, 0x000000C0);
+ Xil_Out32(0xFD405010, 0x000000C0);
+ Xil_Out32(0xFD409010, 0x000000C0);
+ Xil_Out32(0xFD40D010, 0x000000C0);
+ Xil_Out32(0xFD401010, 0x00000080);
+ Xil_Out32(0xFD405010, 0x00000080);
+ Xil_Out32(0xFD409010, 0x00000080);
+ Xil_Out32(0xFD40D010, 0x00000080);
+
+ Xil_Out32(0xFD402084, 0x000000C0);
+ Xil_Out32(0xFD406084, 0x000000C0);
+ Xil_Out32(0xFD40A084, 0x000000C0);
+ Xil_Out32(0xFD40E084, 0x000000C0);
+ mask_delay(50);
+ Xil_Out32(0xFD402084, 0x00000080);
+ Xil_Out32(0xFD406084, 0x00000080);
+ Xil_Out32(0xFD40A084, 0x00000080);
+ Xil_Out32(0xFD40E084, 0x00000080);
+ mask_delay(50);
+ Xil_Out32(0xFD401010, 0x00000000);
+ Xil_Out32(0xFD405010, 0x00000000);
+ Xil_Out32(0xFD409010, 0x00000000);
+ Xil_Out32(0xFD40D010, 0x00000000);
+ Xil_Out32(0xFD402084, 0x00000000);
+ Xil_Out32(0xFD406084, 0x00000000);
+ Xil_Out32(0xFD40A084, 0x00000000);
+ Xil_Out32(0xFD40E084, 0x00000000);
+ mask_delay(500);
+ return 1;
+}
+
+static int serdes_bist_static_settings(u32 lane_active)
+{
+ if (lane_active == 0) {
+ Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+ Xil_Out32(0xFD403068, 0x1);
+ Xil_Out32(0xFD40306C, 0x1);
+ Xil_Out32(0xFD4010AC, 0x0020);
+ Xil_Out32(0xFD403008, 0x0);
+ Xil_Out32(0xFD40300C, 0xF4);
+ Xil_Out32(0xFD403010, 0x0);
+ Xil_Out32(0xFD403014, 0x0);
+ Xil_Out32(0xFD403018, 0x00);
+ Xil_Out32(0xFD40301C, 0xFB);
+ Xil_Out32(0xFD403020, 0xFF);
+ Xil_Out32(0xFD403024, 0x0);
+ Xil_Out32(0xFD403028, 0x00);
+ Xil_Out32(0xFD40302C, 0x00);
+ Xil_Out32(0xFD403030, 0x4A);
+ Xil_Out32(0xFD403034, 0x4A);
+ Xil_Out32(0xFD403038, 0x4A);
+ Xil_Out32(0xFD40303C, 0x4A);
+ Xil_Out32(0xFD403040, 0x0);
+ Xil_Out32(0xFD403044, 0x14);
+ Xil_Out32(0xFD403048, 0x02);
+ Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+ }
+ if (lane_active == 1) {
+ Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+ Xil_Out32(0xFD407068, 0x1);
+ Xil_Out32(0xFD40706C, 0x1);
+ Xil_Out32(0xFD4050AC, 0x0020);
+ Xil_Out32(0xFD407008, 0x0);
+ Xil_Out32(0xFD40700C, 0xF4);
+ Xil_Out32(0xFD407010, 0x0);
+ Xil_Out32(0xFD407014, 0x0);
+ Xil_Out32(0xFD407018, 0x00);
+ Xil_Out32(0xFD40701C, 0xFB);
+ Xil_Out32(0xFD407020, 0xFF);
+ Xil_Out32(0xFD407024, 0x0);
+ Xil_Out32(0xFD407028, 0x00);
+ Xil_Out32(0xFD40702C, 0x00);
+ Xil_Out32(0xFD407030, 0x4A);
+ Xil_Out32(0xFD407034, 0x4A);
+ Xil_Out32(0xFD407038, 0x4A);
+ Xil_Out32(0xFD40703C, 0x4A);
+ Xil_Out32(0xFD407040, 0x0);
+ Xil_Out32(0xFD407044, 0x14);
+ Xil_Out32(0xFD407048, 0x02);
+ Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+ }
+
+ if (lane_active == 2) {
+ Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+ Xil_Out32(0xFD40B068, 0x1);
+ Xil_Out32(0xFD40B06C, 0x1);
+ Xil_Out32(0xFD4090AC, 0x0020);
+ Xil_Out32(0xFD40B008, 0x0);
+ Xil_Out32(0xFD40B00C, 0xF4);
+ Xil_Out32(0xFD40B010, 0x0);
+ Xil_Out32(0xFD40B014, 0x0);
+ Xil_Out32(0xFD40B018, 0x00);
+ Xil_Out32(0xFD40B01C, 0xFB);
+ Xil_Out32(0xFD40B020, 0xFF);
+ Xil_Out32(0xFD40B024, 0x0);
+ Xil_Out32(0xFD40B028, 0x00);
+ Xil_Out32(0xFD40B02C, 0x00);
+ Xil_Out32(0xFD40B030, 0x4A);
+ Xil_Out32(0xFD40B034, 0x4A);
+ Xil_Out32(0xFD40B038, 0x4A);
+ Xil_Out32(0xFD40B03C, 0x4A);
+ Xil_Out32(0xFD40B040, 0x0);
+ Xil_Out32(0xFD40B044, 0x14);
+ Xil_Out32(0xFD40B048, 0x02);
+ Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+ }
+
+ if (lane_active == 3) {
+ Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+ Xil_Out32(0xFD40F068, 0x1);
+ Xil_Out32(0xFD40F06C, 0x1);
+ Xil_Out32(0xFD40D0AC, 0x0020);
+ Xil_Out32(0xFD40F008, 0x0);
+ Xil_Out32(0xFD40F00C, 0xF4);
+ Xil_Out32(0xFD40F010, 0x0);
+ Xil_Out32(0xFD40F014, 0x0);
+ Xil_Out32(0xFD40F018, 0x00);
+ Xil_Out32(0xFD40F01C, 0xFB);
+ Xil_Out32(0xFD40F020, 0xFF);
+ Xil_Out32(0xFD40F024, 0x0);
+ Xil_Out32(0xFD40F028, 0x00);
+ Xil_Out32(0xFD40F02C, 0x00);
+ Xil_Out32(0xFD40F030, 0x4A);
+ Xil_Out32(0xFD40F034, 0x4A);
+ Xil_Out32(0xFD40F038, 0x4A);
+ Xil_Out32(0xFD40F03C, 0x4A);
+ Xil_Out32(0xFD40F040, 0x0);
+ Xil_Out32(0xFD40F044, 0x14);
+ Xil_Out32(0xFD40F048, 0x02);
+ Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+ }
+ return 1;
+}
+
+static int serdes_bist_run(u32 lane_active)
+{
+ if (lane_active == 0) {
+ psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
+ Xil_Out32(0xFD4010AC, 0x0020);
+ Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
+ }
+ if (lane_active == 1) {
+ psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
+ Xil_Out32(0xFD4050AC, 0x0020);
+ Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
+ }
+ if (lane_active == 2) {
+ psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
+ psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
+ psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
+ Xil_Out32(0xFD4090AC, 0x0020);
+ Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
+ }
+ if (lane_active == 3) {
+ psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
+ psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
+ psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
+ Xil_Out32(0xFD40D0AC, 0x0020);
+ Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
+ }
+ mask_delay(100);
+ return 1;
+}
+
+static int serdes_bist_result(u32 lane_active)
+{
+ u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+
+ if (lane_active == 0) {
+ pkt_cnt_l0 = Xil_In32(0xFD40304C);
+ pkt_cnt_h0 = Xil_In32(0xFD403050);
+ err_cnt_l0 = Xil_In32(0xFD403054);
+ err_cnt_h0 = Xil_In32(0xFD403058);
+ }
+ if (lane_active == 1) {
+ pkt_cnt_l0 = Xil_In32(0xFD40704C);
+ pkt_cnt_h0 = Xil_In32(0xFD407050);
+ err_cnt_l0 = Xil_In32(0xFD407054);
+ err_cnt_h0 = Xil_In32(0xFD407058);
+ }
+ if (lane_active == 2) {
+ pkt_cnt_l0 = Xil_In32(0xFD40B04C);
+ pkt_cnt_h0 = Xil_In32(0xFD40B050);
+ err_cnt_l0 = Xil_In32(0xFD40B054);
+ err_cnt_h0 = Xil_In32(0xFD40B058);
+ }
+ if (lane_active == 3) {
+ pkt_cnt_l0 = Xil_In32(0xFD40F04C);
+ pkt_cnt_h0 = Xil_In32(0xFD40F050);
+ err_cnt_l0 = Xil_In32(0xFD40F054);
+ err_cnt_h0 = Xil_In32(0xFD40F058);
+ }
+ if (lane_active == 0)
+ Xil_Out32(0xFD403004, 0x0);
+ if (lane_active == 1)
+ Xil_Out32(0xFD407004, 0x0);
+ if (lane_active == 2)
+ Xil_Out32(0xFD40B004, 0x0);
+ if (lane_active == 3)
+ Xil_Out32(0xFD40F004, 0x0);
+ if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
+ (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
+ return 0;
+ return 1;
+}
+
+static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol,
+ u32 lane3_rate, u32 lane2_protocol,
+ u32 lane2_rate, u32 lane1_protocol,
+ u32 lane1_rate, u32 lane0_protocol,
+ u32 lane0_rate, u32 gen2_calib)
+{
+ u64 tempbistresult;
+ u32 currbistresult[4];
+ u32 prevbistresult[4];
+ u32 itercount = 0;
+ u32 ill12_val[4], ill1_val[4];
+ u32 loop = 0;
+ u32 iterresult[8];
+ u32 meancount[4];
+ u32 bistpasscount[4];
+ u32 meancountalt[4];
+ u32 meancountalt_bistpasscount[4];
+ u32 lane0_active;
+ u32 lane1_active;
+ u32 lane2_active;
+ u32 lane3_active;
+
+ lane0_active = (lane0_protocol == 1);
+ lane1_active = (lane1_protocol == 1);
+ lane2_active = (lane2_protocol == 1);
+ lane3_active = (lane3_protocol == 1);
+ for (loop = 0; loop <= 3; loop++) {
+ iterresult[loop] = 0;
+ iterresult[loop + 4] = 0;
+ meancountalt[loop] = 0;
+ meancountalt_bistpasscount[loop] = 0;
+ meancount[loop] = 0;
+ prevbistresult[loop] = 0;
+ bistpasscount[loop] = 0;
+ }
+ itercount = 0;
+ if (lane0_active)
+ serdes_bist_static_settings(0);
+ if (lane1_active)
+ serdes_bist_static_settings(1);
+ if (lane2_active)
+ serdes_bist_static_settings(2);
+ if (lane3_active)
+ serdes_bist_static_settings(3);
+ do {
+ if (gen2_calib != 1) {
+ if (lane0_active == 1)
+ ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
+ if (lane0_active == 1)
+ ill12_val[0] =
+ ((0x04 + itercount * 8) >=
+ 0x100) ? 0x10 : 0x00;
+ if (lane1_active == 1)
+ ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
+ if (lane1_active == 1)
+ ill12_val[1] =
+ ((0x04 + itercount * 8) >=
+ 0x100) ? 0x10 : 0x00;
+ if (lane2_active == 1)
+ ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
+ if (lane2_active == 1)
+ ill12_val[2] =
+ ((0x04 + itercount * 8) >=
+ 0x100) ? 0x10 : 0x00;
+ if (lane3_active == 1)
+ ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
+ if (lane3_active == 1)
+ ill12_val[3] =
+ ((0x04 + itercount * 8) >=
+ 0x100) ? 0x10 : 0x00;
+
+ if (lane0_active == 1)
+ Xil_Out32(0xFD401924, ill1_val[0]);
+ if (lane0_active == 1)
+ psu_mask_write(0xFD401990, 0x000000F0U,
+ ill12_val[0]);
+ if (lane1_active == 1)
+ Xil_Out32(0xFD405924, ill1_val[1]);
+ if (lane1_active == 1)
+ psu_mask_write(0xFD405990, 0x000000F0U,
+ ill12_val[1]);
+ if (lane2_active == 1)
+ Xil_Out32(0xFD409924, ill1_val[2]);
+ if (lane2_active == 1)
+ psu_mask_write(0xFD409990, 0x000000F0U,
+ ill12_val[2]);
+ if (lane3_active == 1)
+ Xil_Out32(0xFD40D924, ill1_val[3]);
+ if (lane3_active == 1)
+ psu_mask_write(0xFD40D990, 0x000000F0U,
+ ill12_val[3]);
+ }
+ if (gen2_calib == 1) {
+ if (lane0_active == 1)
+ ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
+ if (lane0_active == 1)
+ ill12_val[0] =
+ ((0x104 + itercount * 8) >=
+ 0x200) ? 0x02 : 0x01;
+ if (lane1_active == 1)
+ ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
+ if (lane1_active == 1)
+ ill12_val[1] =
+ ((0x104 + itercount * 8) >=
+ 0x200) ? 0x02 : 0x01;
+ if (lane2_active == 1)
+ ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
+ if (lane2_active == 1)
+ ill12_val[2] =
+ ((0x104 + itercount * 8) >=
+ 0x200) ? 0x02 : 0x01;
+ if (lane3_active == 1)
+ ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
+ if (lane3_active == 1)
+ ill12_val[3] =
+ ((0x104 + itercount * 8) >=
+ 0x200) ? 0x02 : 0x01;
+
+ if (lane0_active == 1)
+ Xil_Out32(0xFD401928, ill1_val[0]);
+ if (lane0_active == 1)
+ psu_mask_write(0xFD401990, 0x0000000FU,
+ ill12_val[0]);
+ if (lane1_active == 1)
+ Xil_Out32(0xFD405928, ill1_val[1]);
+ if (lane1_active == 1)
+ psu_mask_write(0xFD405990, 0x0000000FU,
+ ill12_val[1]);
+ if (lane2_active == 1)
+ Xil_Out32(0xFD409928, ill1_val[2]);
+ if (lane2_active == 1)
+ psu_mask_write(0xFD409990, 0x0000000FU,
+ ill12_val[2]);
+ if (lane3_active == 1)
+ Xil_Out32(0xFD40D928, ill1_val[3]);
+ if (lane3_active == 1)
+ psu_mask_write(0xFD40D990, 0x0000000FU,
+ ill12_val[3]);
+ }
+
+ if (lane0_active == 1)
+ psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
+ if (lane1_active == 1)
+ psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
+ if (lane2_active == 1)
+ psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
+ if (lane3_active == 1)
+ psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
+ if (lane0_active == 1)
+ currbistresult[0] = 0;
+ if (lane1_active == 1)
+ currbistresult[1] = 0;
+ if (lane2_active == 1)
+ currbistresult[2] = 0;
+ if (lane3_active == 1)
+ currbistresult[3] = 0;
+ serdes_rst_seq(pllsel, lane3_protocol, lane3_rate,
+ lane2_protocol, lane2_rate, lane1_protocol,
+ lane1_rate, lane0_protocol, lane0_rate);
+ if (lane3_active == 1)
+ serdes_bist_run(3);
+ if (lane2_active == 1)
+ serdes_bist_run(2);
+ if (lane1_active == 1)
+ serdes_bist_run(1);
+ if (lane0_active == 1)
+ serdes_bist_run(0);
+ tempbistresult = 0;
+ if (lane3_active == 1)
+ tempbistresult = tempbistresult | serdes_bist_result(3);
+ tempbistresult = tempbistresult << 1;
+ if (lane2_active == 1)
+ tempbistresult = tempbistresult | serdes_bist_result(2);
+ tempbistresult = tempbistresult << 1;
+ if (lane1_active == 1)
+ tempbistresult = tempbistresult | serdes_bist_result(1);
+ tempbistresult = tempbistresult << 1;
+ if (lane0_active == 1)
+ tempbistresult = tempbistresult | serdes_bist_result(0);
+ Xil_Out32(0xFD410098, 0x0);
+ Xil_Out32(0xFD410098, 0x2);
+
+ if (itercount < 32) {
+ iterresult[0] =
+ ((iterresult[0] << 1) |
+ ((tempbistresult & 0x1) == 0x1));
+ iterresult[1] =
+ ((iterresult[1] << 1) |
+ ((tempbistresult & 0x2) == 0x2));
+ iterresult[2] =
+ ((iterresult[2] << 1) |
+ ((tempbistresult & 0x4) == 0x4));
+ iterresult[3] =
+ ((iterresult[3] << 1) |
+ ((tempbistresult & 0x8) == 0x8));
+ } else {
+ iterresult[4] =
+ ((iterresult[4] << 1) |
+ ((tempbistresult & 0x1) == 0x1));
+ iterresult[5] =
+ ((iterresult[5] << 1) |
+ ((tempbistresult & 0x2) == 0x2));
+ iterresult[6] =
+ ((iterresult[6] << 1) |
+ ((tempbistresult & 0x4) == 0x4));
+ iterresult[7] =
+ ((iterresult[7] << 1) |
+ ((tempbistresult & 0x8) == 0x8));
+ }
+ currbistresult[0] =
+ currbistresult[0] | ((tempbistresult & 0x1) == 1);
+ currbistresult[1] =
+ currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
+ currbistresult[2] =
+ currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
+ currbistresult[3] =
+ currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
+
+ for (loop = 0; loop <= 3; loop++) {
+ if (currbistresult[loop] == 1 &&
+ prevbistresult[loop] == 1)
+ bistpasscount[loop] = bistpasscount[loop] + 1;
+ if (bistpasscount[loop] < 4 &&
+ currbistresult[loop] == 0 && itercount > 2) {
+ if (meancountalt_bistpasscount[loop] <
+ bistpasscount[loop]) {
+ meancountalt_bistpasscount[loop] =
+ bistpasscount[loop];
+ meancountalt[loop] =
+ ((itercount - 1) -
+ ((bistpasscount[loop] + 1) / 2));
+ }
+ bistpasscount[loop] = 0;
+ }
+ if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
+ (currbistresult[loop] == 0 || itercount == 63) &&
+ prevbistresult[loop] == 1)
+ meancount[loop] =
+ itercount - 1 -
+ ((bistpasscount[loop] + 1) / 2);
+ prevbistresult[loop] = currbistresult[loop];
+ }
+ } while (++itercount < 64);
+
+ for (loop = 0; loop <= 3; loop++) {
+ if (lane0_active == 0 && loop == 0)
+ continue;
+ if (lane1_active == 0 && loop == 1)
+ continue;
+ if (lane2_active == 0 && loop == 2)
+ continue;
+ if (lane3_active == 0 && loop == 3)
+ continue;
+
+ if (meancount[loop] == 0)
+ meancount[loop] = meancountalt[loop];
+
+ if (gen2_calib != 1) {
+ ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
+ ill12_val[loop] =
+ ((0x04 + meancount[loop] * 8) >=
+ 0x100) ? 0x10 : 0x00;
+ }
+ if (gen2_calib == 1) {
+ ill1_val[loop] =
+ ((0x104 + meancount[loop] * 8) % 0x100);
+ ill12_val[loop] =
+ ((0x104 + meancount[loop] * 8) >=
+ 0x200) ? 0x02 : 0x01;
+ }
+ }
+ if (gen2_calib != 1) {
+ if (lane0_active == 1)
+ Xil_Out32(0xFD401924, ill1_val[0]);
+ if (lane0_active == 1)
+ psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
+ if (lane1_active == 1)
+ Xil_Out32(0xFD405924, ill1_val[1]);
+ if (lane1_active == 1)
+ psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
+ if (lane2_active == 1)
+ Xil_Out32(0xFD409924, ill1_val[2]);
+ if (lane2_active == 1)
+ psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
+ if (lane3_active == 1)
+ Xil_Out32(0xFD40D924, ill1_val[3]);
+ if (lane3_active == 1)
+ psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
+ }
+ if (gen2_calib == 1) {
+ if (lane0_active == 1)
+ Xil_Out32(0xFD401928, ill1_val[0]);
+ if (lane0_active == 1)
+ psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
+ if (lane1_active == 1)
+ Xil_Out32(0xFD405928, ill1_val[1]);
+ if (lane1_active == 1)
+ psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
+ if (lane2_active == 1)
+ Xil_Out32(0xFD409928, ill1_val[2]);
+ if (lane2_active == 1)
+ psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
+ if (lane3_active == 1)
+ Xil_Out32(0xFD40D928, ill1_val[3]);
+ if (lane3_active == 1)
+ psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
+ }
+
+ if (lane0_active == 1)
+ psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
+ if (lane1_active == 1)
+ psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
+ if (lane2_active == 1)
+ psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
+ if (lane3_active == 1)
+ psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
+
+ Xil_Out32(0xFD410098, 0);
+ if (lane0_active == 1) {
+ Xil_Out32(0xFD403004, 0);
+ Xil_Out32(0xFD403008, 0);
+ Xil_Out32(0xFD40300C, 0);
+ Xil_Out32(0xFD403010, 0);
+ Xil_Out32(0xFD403014, 0);
+ Xil_Out32(0xFD403018, 0);
+ Xil_Out32(0xFD40301C, 0);
+ Xil_Out32(0xFD403020, 0);
+ Xil_Out32(0xFD403024, 0);
+ Xil_Out32(0xFD403028, 0);
+ Xil_Out32(0xFD40302C, 0);
+ Xil_Out32(0xFD403030, 0);
+ Xil_Out32(0xFD403034, 0);
+ Xil_Out32(0xFD403038, 0);
+ Xil_Out32(0xFD40303C, 0);
+ Xil_Out32(0xFD403040, 0);
+ Xil_Out32(0xFD403044, 0);
+ Xil_Out32(0xFD403048, 0);
+ Xil_Out32(0xFD40304C, 0);
+ Xil_Out32(0xFD403050, 0);
+ Xil_Out32(0xFD403054, 0);
+ Xil_Out32(0xFD403058, 0);
+ Xil_Out32(0xFD403068, 1);
+ Xil_Out32(0xFD40306C, 0);
+ Xil_Out32(0xFD4010AC, 0);
+ psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
+ psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
+ psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
+ }
+ if (lane1_active == 1) {
+ Xil_Out32(0xFD407004, 0);
+ Xil_Out32(0xFD407008, 0);
+ Xil_Out32(0xFD40700C, 0);
+ Xil_Out32(0xFD407010, 0);
+ Xil_Out32(0xFD407014, 0);
+ Xil_Out32(0xFD407018, 0);
+ Xil_Out32(0xFD40701C, 0);
+ Xil_Out32(0xFD407020, 0);
+ Xil_Out32(0xFD407024, 0);
+ Xil_Out32(0xFD407028, 0);
+ Xil_Out32(0xFD40702C, 0);
+ Xil_Out32(0xFD407030, 0);
+ Xil_Out32(0xFD407034, 0);
+ Xil_Out32(0xFD407038, 0);
+ Xil_Out32(0xFD40703C, 0);
+ Xil_Out32(0xFD407040, 0);
+ Xil_Out32(0xFD407044, 0);
+ Xil_Out32(0xFD407048, 0);
+ Xil_Out32(0xFD40704C, 0);
+ Xil_Out32(0xFD407050, 0);
+ Xil_Out32(0xFD407054, 0);
+ Xil_Out32(0xFD407058, 0);
+ Xil_Out32(0xFD407068, 1);
+ Xil_Out32(0xFD40706C, 0);
+ Xil_Out32(0xFD4050AC, 0);
+ psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
+ psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
+ psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
+ }
+ if (lane2_active == 1) {
+ Xil_Out32(0xFD40B004, 0);
+ Xil_Out32(0xFD40B008, 0);
+ Xil_Out32(0xFD40B00C, 0);
+ Xil_Out32(0xFD40B010, 0);
+ Xil_Out32(0xFD40B014, 0);
+ Xil_Out32(0xFD40B018, 0);
+ Xil_Out32(0xFD40B01C, 0);
+ Xil_Out32(0xFD40B020, 0);
+ Xil_Out32(0xFD40B024, 0);
+ Xil_Out32(0xFD40B028, 0);
+ Xil_Out32(0xFD40B02C, 0);
+ Xil_Out32(0xFD40B030, 0);
+ Xil_Out32(0xFD40B034, 0);
+ Xil_Out32(0xFD40B038, 0);
+ Xil_Out32(0xFD40B03C, 0);
+ Xil_Out32(0xFD40B040, 0);
+ Xil_Out32(0xFD40B044, 0);
+ Xil_Out32(0xFD40B048, 0);
+ Xil_Out32(0xFD40B04C, 0);
+ Xil_Out32(0xFD40B050, 0);
+ Xil_Out32(0xFD40B054, 0);
+ Xil_Out32(0xFD40B058, 0);
+ Xil_Out32(0xFD40B068, 1);
+ Xil_Out32(0xFD40B06C, 0);
+ Xil_Out32(0xFD4090AC, 0);
+ psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
+ psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
+ psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
+ }
+ if (lane3_active == 1) {
+ Xil_Out32(0xFD40F004, 0);
+ Xil_Out32(0xFD40F008, 0);
+ Xil_Out32(0xFD40F00C, 0);
+ Xil_Out32(0xFD40F010, 0);
+ Xil_Out32(0xFD40F014, 0);
+ Xil_Out32(0xFD40F018, 0);
+ Xil_Out32(0xFD40F01C, 0);
+ Xil_Out32(0xFD40F020, 0);
+ Xil_Out32(0xFD40F024, 0);
+ Xil_Out32(0xFD40F028, 0);
+ Xil_Out32(0xFD40F02C, 0);
+ Xil_Out32(0xFD40F030, 0);
+ Xil_Out32(0xFD40F034, 0);
+ Xil_Out32(0xFD40F038, 0);
+ Xil_Out32(0xFD40F03C, 0);
+ Xil_Out32(0xFD40F040, 0);
+ Xil_Out32(0xFD40F044, 0);
+ Xil_Out32(0xFD40F048, 0);
+ Xil_Out32(0xFD40F04C, 0);
+ Xil_Out32(0xFD40F050, 0);
+ Xil_Out32(0xFD40F054, 0);
+ Xil_Out32(0xFD40F058, 0);
+ Xil_Out32(0xFD40F068, 1);
+ Xil_Out32(0xFD40F06C, 0);
+ Xil_Out32(0xFD40D0AC, 0);
+ psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
+ psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
+ psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
+ }
+ return 1;
+}
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+ u32 lane2_protocol, u32 lane2_rate,
+ u32 lane1_protocol, u32 lane1_rate,
+ u32 lane0_protocol, u32 lane0_rate)
+{
+ unsigned int rdata = 0;
+ unsigned int sata_gen2 = 1;
+ unsigned int temp_ill12 = 0;
+ unsigned int temp_PLL_REF_SEL_OFFSET;
+ unsigned int temp_TM_IQ_ILL1;
+ unsigned int temp_TM_E_ILL1;
+ unsigned int temp_tx_dig_tm_61;
+ unsigned int temp_tm_dig_6;
+ unsigned int temp_pll_fbdiv_frac_3_msb_offset;
+
+ if (lane0_protocol == 2 || lane0_protocol == 1) {
+ Xil_Out32(0xFD401910, 0xF3);
+ Xil_Out32(0xFD40193C, 0xF3);
+ Xil_Out32(0xFD401914, 0xF3);
+ Xil_Out32(0xFD401940, 0xF3);
+ }
+ if (lane1_protocol == 2 || lane1_protocol == 1) {
+ Xil_Out32(0xFD405910, 0xF3);
+ Xil_Out32(0xFD40593C, 0xF3);
+ Xil_Out32(0xFD405914, 0xF3);
+ Xil_Out32(0xFD405940, 0xF3);
+ }
+ if (lane2_protocol == 2 || lane2_protocol == 1) {
+ Xil_Out32(0xFD409910, 0xF3);
+ Xil_Out32(0xFD40993C, 0xF3);
+ Xil_Out32(0xFD409914, 0xF3);
+ Xil_Out32(0xFD409940, 0xF3);
+ }
+ if (lane3_protocol == 2 || lane3_protocol == 1) {
+ Xil_Out32(0xFD40D910, 0xF3);
+ Xil_Out32(0xFD40D93C, 0xF3);
+ Xil_Out32(0xFD40D914, 0xF3);
+ Xil_Out32(0xFD40D940, 0xF3);
+ }
+
+ if (sata_gen2 == 1) {
+ if (lane0_protocol == 2) {
+ temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
+ Xil_Out32(0xFD402360, 0x0);
+ temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
+ temp_TM_E_ILL1 = Xil_In32(0xFD401924);
+ Xil_Out32(0xFD4018F8, 0x78);
+ temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
+ temp_tm_dig_6 = Xil_In32(0xFD40106C);
+ psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
+ psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
+ temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
+
+ serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
+
+ Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
+ Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET);
+ Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
+ Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
+ Xil_Out32(0xFD40106C, temp_tm_dig_6);
+ Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
+ temp_ill12 =
+ temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
+ Xil_Out32(0xFD401990, temp_ill12);
+ Xil_Out32(0xFD401924, temp_TM_E_ILL1);
+ }
+ if (lane1_protocol == 2) {
+ temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
+ Xil_Out32(0xFD406360, 0x0);
+ temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+ temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
+ temp_TM_E_ILL1 = Xil_In32(0xFD405924);
+ Xil_Out32(0xFD4058F8, 0x78);
+ temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
+ temp_tm_dig_6 = Xil_In32(0xFD40506C);
+ psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
+ psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
+ temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
+
+ serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0);
+
+ Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
+ Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET);
+ Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
+ Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
+ Xil_Out32(0xFD40506C, temp_tm_dig_6);
+ Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
+ temp_ill12 =
+ temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
+ Xil_Out32(0xFD405990, temp_ill12);
+ Xil_Out32(0xFD405924, temp_TM_E_ILL1);
+ }
+ if (lane2_protocol == 2) {
+ temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
+ Xil_Out32(0xFD40A360, 0x0);
+ temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+ temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
+ temp_TM_E_ILL1 = Xil_In32(0xFD409924);
+ Xil_Out32(0xFD4098F8, 0x78);
+ temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
+ temp_tm_dig_6 = Xil_In32(0xFD40906C);
+ psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
+ psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
+ temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
+
+ serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+
+ Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
+ Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET);
+ Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
+ Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
+ Xil_Out32(0xFD40906C, temp_tm_dig_6);
+ Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
+ temp_ill12 =
+ temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
+ Xil_Out32(0xFD409990, temp_ill12);
+ Xil_Out32(0xFD409924, temp_TM_E_ILL1);
+ }
+ if (lane3_protocol == 2) {
+ temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
+ Xil_Out32(0xFD40E360, 0x0);
+ temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+ temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
+ temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
+ Xil_Out32(0xFD40D8F8, 0x78);
+ temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
+ temp_tm_dig_6 = Xil_In32(0xFD40D06C);
+ psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
+ psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
+ temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
+
+ serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0);
+
+ Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
+ Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+ Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
+ Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
+ Xil_Out32(0xFD40D06C, temp_tm_dig_6);
+ Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
+ temp_ill12 =
+ temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
+ Xil_Out32(0xFD40D990, temp_ill12);
+ Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
+ }
+ rdata = Xil_In32(0xFD410098);
+ rdata = (rdata & 0xDF);
+ Xil_Out32(0xFD410098, rdata);
+ }
+
+ if (lane0_protocol == 2 && lane0_rate == 3) {
+ psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
+ }
+ if (lane1_protocol == 2 && lane1_rate == 3) {
+ psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
+ }
+ if (lane2_protocol == 2 && lane2_rate == 3) {
+ psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
+ }
+ if (lane3_protocol == 2 && lane3_rate == 3) {
+ psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
+ }
+
+ if (lane0_protocol == 1) {
+ if (lane0_rate == 0) {
+ serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate,
+ lane2_protocol, lane2_rate,
+ lane1_protocol, lane1_rate,
+ lane0_protocol, 0, 0);
+ } else {
+ serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate,
+ lane2_protocol, lane2_rate,
+ lane1_protocol, lane1_rate,
+ lane0_protocol, 0, 0);
+ serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate,
+ lane2_protocol, lane2_rate,
+ lane1_protocol, lane1_rate,
+ lane0_protocol, lane0_rate,
+ 1);
+ }
+ }
+
+ if (lane0_protocol == 3)
+ Xil_Out32(0xFD401914, 0xF3);
+ if (lane0_protocol == 3)
+ Xil_Out32(0xFD401940, 0xF3);
+ if (lane0_protocol == 3)
+ Xil_Out32(0xFD401990, 0x20);
+ if (lane0_protocol == 3)
+ Xil_Out32(0xFD401924, 0x37);
+
+ if (lane1_protocol == 3)
+ Xil_Out32(0xFD405914, 0xF3);
+ if (lane1_protocol == 3)
+ Xil_Out32(0xFD405940, 0xF3);
+ if (lane1_protocol == 3)
+ Xil_Out32(0xFD405990, 0x20);
+ if (lane1_protocol == 3)
+ Xil_Out32(0xFD405924, 0x37);
+
+ if (lane2_protocol == 3)
+ Xil_Out32(0xFD409914, 0xF3);
+ if (lane2_protocol == 3)
+ Xil_Out32(0xFD409940, 0xF3);
+ if (lane2_protocol == 3)
+ Xil_Out32(0xFD409990, 0x20);
+ if (lane2_protocol == 3)
+ Xil_Out32(0xFD409924, 0x37);
+
+ if (lane3_protocol == 3)
+ Xil_Out32(0xFD40D914, 0xF3);
+ if (lane3_protocol == 3)
+ Xil_Out32(0xFD40D940, 0xF3);
+ if (lane3_protocol == 3)
+ Xil_Out32(0xFD40D990, 0x20);
+ if (lane3_protocol == 3)
+ Xil_Out32(0xFD40D924, 0x37);
+
+ return 1;
+}
+
+static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
+ int d_lock_cnt, int d_lfhf, int d_cp, int d_res)
+{
+ unsigned int pll_ctrl_regval;
+ unsigned int pll_status_regval;
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
+ pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
+ pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
+ pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+ pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_status_regval = 0x00000000;
+ while ((pll_status_regval & 0x00000002U) != 0x00000002U)
+ pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+ pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+ int count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ xil_printf("#SERDES initialization timed out\n\r");
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if (p_code >= 0x26 && p_code <= 0x3C)
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if (n_code >= 0x26 && n_code <= 0x3C)
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if (i_code >= 0xC && i_code <= 0x12)
+ match_ical_code[i_code - 0xc] += 1;
+
+ if (r_code >= 0x6 && r_code <= 0xC)
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
mode = "mmc";
bootseq = dev_seq(dev);
+ env_set("modeboot", "emmcboot");
break;
case SD_MODE:
puts("SD_MODE\n");
config CMD_ERASEENV
bool "eraseenv"
- default n
depends on CMD_SAVEENV
help
Erase environment variables from the compiled-in persistent
Help printed with the LAYOUT VERSIONS part of the 'eeprom'
command's help.
+config SYS_I2C_EEPROM_BUS
+ int "I2C bus of the EEPROM device."
+ depends on CMD_EEPROM
+ default 0
+
+config SYS_I2C_EEPROM_ADDR_LEN
+ int "Length in bytes of the EEPROM memory array address"
+ depends on CMD_EEPROM || ID_EEPROM
+ default 1
+ range 1 2
+ help
+ Note: This is NOT the chip address length!
+
+config SYS_EEPROM_SIZE
+ depends on CMD_EEPROM
+ int "Size in bytes of the EEPROM device"
+ default 256
+
+config SYS_EEPROM_PAGE_WRITE_BITS
+ int "Number of bits used to address bytes in a single page"
+ depends on CMD_EEPROM
+ default 8
+ help
+ The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
+ A 64 byte page, for example would require six bits.
+
+config SYS_EEPROM_PAGE_WRITE_DELAY_MS
+ int "Number of milliseconds to delay between page writes"
+ depends on CMD_EEPROM || CMD_I2C
+ default 0
+
config LOOPW
bool "loopw"
help
config CMD_MD5SUM
bool "md5sum"
- default n
select MD5
help
Compute MD5 checksum.
config MD5SUM_VERIFY
bool "md5sum -v"
- default n
depends on CMD_MD5SUM
help
Add -v option to verify data against an MD5 checksum.
config CMD_BKOPS_ENABLE
bool "mmc bkops enable"
depends on CMD_MMC
- default n
help
Enable command for setting manual background operations handshake
on a eMMC device. The feature is optionally available on eMMC devices
config CMD_SETEXPR_FMT
bool "setexpr_fmt"
- default n
depends on CMD_SETEXPR
help
Evaluate format string expression and store result in an environment
config CMD_AB_SELECT
bool "ab_select"
- default n
depends on ANDROID_AB
help
On Android devices with more than one boot slot (multiple copies of
bool "efidebug - display/configure UEFI environment"
depends on EFI_LOADER
select EFI_DEVICE_PATH_TO_TEXT
- default n
help
Enable the 'efidebug' command which provides a subset of UEFI
shell utility with simplified functionality. It will be useful
config CMD_AVB
bool "avb - Android Verified Boot 2.0 operations"
depends on AVB_VERIFY
- default n
help
Enables a "avb" command to perform verification of partitions using
Android Verified Boot 2.0 functionality. It includes such subcommands:
config CMD_UBI_RENAME
bool "Enable rename"
depends on CMD_UBI
- default n
help
Enable a "ubi" command to rename ubi volume:
ubi rename <oldname> <newname>
} /* bedbug_puts */
-
/* ======================================================================
* Initialize the bug_ctx structure used by the bedbug debugger. This is
* specific to the CPU since each has different debug registers and
} /* bedbug_init */
-
/* ======================================================================
* Entry point from the interpreter to the disassembler. Repeated calls
* will resume from the last disassembled address.
} /* do_bedbug_breakpoint */
-
/* ======================================================================
* Called from the CPU-specific breakpoint handling routine. Enter a
* mini main loop until the stopped flag is cleared from the breakpoint
} /* bedbug_main_loop */
-
/* ======================================================================
* Interpreter command to continue from a breakpoint. Just clears the
* stopped flag in the context so that the breakpoint routine will
*
* based on: cmd_jffs2.c
*
- * Add support for a CRAMFS located in RAM
+ * Add support for a CRAMFS located in RAM
*/
return CMD_RET_FAILURE;
}
}
-#elif defined(CONFIG_SYS_I2C_LEGACY)
+#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
old_bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
#else
}
/* switch back to original I2C bus */
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
i2c_set_bus_num(old_bus);
#elif !defined(CONFIG_DM_RTC)
I2C_SET_BUS(old_bus);
* degradation (typical for EEPROM) is incured for FRAM memory:
*
* #define CONFIG_SYS_I2C_FRAM
- * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+ * Set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to 0
*
*/
#include <eeprom_layout.h>
#include <linux/delay.h>
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 50000
-#endif
-
-#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0
-#endif
-
-#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8
-#endif
-
#ifndef I2C_RXTX_LEN
#define I2C_RXTX_LEN 128
#endif
#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
-/*
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
- * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
- *
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
- * 0x00000nxx for EEPROM address selectors and page number at n.
- */
-#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
-#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \
- (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \
- (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2)
-#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
-#endif
-#endif
-
#if CONFIG_IS_ENABLED(DM_I2C)
static int eeprom_i2c_bus;
#endif
/* I2C EEPROM */
#if CONFIG_IS_ENABLED(DM_I2C)
eeprom_i2c_bus = bus;
-#elif defined(CONFIG_SYS_I2C_LEGACY)
+#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
if (bus >= 0)
i2c_set_bus_num(bus);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
+/*
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ * 0x00000nxx for EEPROM address selectors and page number at n.
+ */
static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr)
{
unsigned blk_off;
buffer += len;
offset += len;
+#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0
if (!read)
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
}
return rcode;
int argc_no_bus = argc_no_bus_addr + 1;
int argc_bus_addr = argc_no_bus_addr + 2;
-#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
if (argc == argc_no_bus_addr) {
*i2c_bus = -1;
- *i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+ *i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR;
return 0;
}
fdt_strerror(err));
return CMD_RET_FAILURE;
}
-#ifdef CONFIG_SOC_KEYSTONE
+#ifdef CONFIG_ARCH_KEYSTONE
ft_board_setup_ex(working_fdt, gd->bd);
#endif
}
* pairs. The following macros take care of this */
#if defined(CONFIG_SYS_I2C_NOPROBES)
-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
static struct
{
uchar bus;
#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
-#endif /* defined(CONFIG_SYS_I2C_LEGACY) */
+#endif /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */
#endif
#define DISP_LINE_LEN 16
{
}
-/* TODO: Implement architecture-specific get/set functions */
-
-/**
- * i2c_get_bus_speed() - Return I2C bus speed
- *
- * This function is the default implementation of function for retrieveing
- * the current I2C bus speed in Hz.
- *
- * A driver implementing runtime switching of I2C bus speed must override
- * this function to report the speed correctly. Simple or legacy drivers
- * can use this fallback.
- *
- * Returns I2C bus speed in Hz.
- */
-#if !defined(CONFIG_SYS_I2C_LEGACY) && !CONFIG_IS_ENABLED(DM_I2C)
-/*
- * TODO: Implement architecture-specific get/set functions
- * Should go away, if we switched completely to new multibus support
- */
-__weak
-unsigned int i2c_get_bus_speed(void)
-{
- return CONFIG_SYS_I2C_SPEED;
-}
-
-/**
- * i2c_set_bus_speed() - Configure I2C bus speed
- * @speed: Newly set speed of the I2C bus in Hz
- *
- * This function is the default implementation of function for setting
- * the I2C bus speed in Hz.
- *
- * A driver implementing runtime switching of I2C bus speed must override
- * this function to report the speed correctly. Simple or legacy drivers
- * can use this fallback.
- *
- * Returns zero on success, negative value on error.
- */
-__weak
-int i2c_set_bus_speed(unsigned int speed)
-{
- if (speed != CONFIG_SYS_I2C_SPEED)
- return -1;
-
- return 0;
-}
-#endif
-
/**
* get_alen() - Small parser helper function to get address length
*
if (ret)
return i2c_report_err(ret,
I2C_ERR_WRITE);
-#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
if (incrflag)
*
* Returns zero always.
*/
-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \
CONFIG_IS_ENABLED(DM_I2C)
static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
printf("Current bus is %d\n", bus_no);
} else {
bus_no = dectoul(argv[1], NULL);
-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
printf("Invalid bus %d\n", bus_no);
return -1;
return ret ? CMD_RET_FAILURE : 0;
}
-#endif /* defined(CONFIG_SYS_I2C_LEGACY) */
+#endif /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */
/**
* do_i2c_bus_speed() - Handle the "i2c speed" command-line command
printf("Error: Not supported by the driver\n");
return CMD_RET_FAILURE;
}
-#elif defined(CONFIG_SYS_I2C_LEGACY)
+#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
return 0;
}
static struct cmd_tbl cmd_i2c_sub[] = {
-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
#endif
U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
-#if defined(CONFIG_SYS_I2C_LEGACY) || \
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \
defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif /* CONFIG_I2C_MULTI_BUS */
/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char i2c_help_text[] =
-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
"bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
"i2c " /* That's the prefix for the crc32 command below. */
#endif
"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
-#if defined(CONFIG_SYS_I2C_LEGACY) || \
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \
defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
"i2c dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
addr = load_serial_ymodem(offset, xyzModem_ymodem);
+ if (addr == ~0) {
+ image_load_addr = 0;
+ printf("## Binary (ymodem) download aborted\n");
+ rcode = 1;
+ } else {
+ printf("## Start Addr = 0x%08lX\n", addr);
+ image_load_addr = addr;
+ }
} else if (strcmp(argv[0],"loadx")==0) {
printf("## Ready for binary (xmodem) download "
"to 0x%08lX at %d bps...\n",
addr = load_serial_ymodem(offset, xyzModem_xmodem);
+ if (addr == ~0) {
+ image_load_addr = 0;
+ printf("## Binary (xmodem) download aborted\n");
+ rcode = 1;
+ } else {
+ printf("## Start Addr = 0x%08lX\n", addr);
+ image_load_addr = addr;
+ }
} else {
printf("## Ready for binary (kermit) download "
udelay(1000);
}
+ if (size == 0)
+ return ~0; /* Download aborted */
+
flush_cache(offset, size);
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
res = xyzModem_stream_open(&info, &err);
if (!res) {
+ err = 0;
while ((res =
xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0) {
store_addr = addr + offset;
rc = flash_write((char *) ymodemBuf,
store_addr, res);
if (rc != 0) {
+ xyzModem_stream_terminate(true, &getcxmodem);
+ xyzModem_stream_close(&err);
+ printf("\n");
flash_perror(rc);
return (~0);
}
}
}
+ if (err) {
+ xyzModem_stream_terminate((err == xyzModem_cancel) ? false : true, &getcxmodem);
+ xyzModem_stream_close(&err);
+ printf("\n%s\n", xyzModem_error(err));
+ return (~0); /* Download aborted */
+ }
+
if (IS_ENABLED(CONFIG_CMD_BOOTEFI))
efi_set_bootdev("Uart", "", "",
map_sysmem(offset, 0), size);
} else {
- printf("%s\n", xyzModem_error(err));
+ printf("\n%s\n", xyzModem_error(err));
+ return (~0); /* Download aborted */
}
- xyzModem_stream_close(&err);
xyzModem_stream_terminate(false, &getcxmodem);
+ xyzModem_stream_close(&err);
flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN));
config CMD_MVEBU_BUBT
bool "bubt"
- default n
select SHA256 if ARMADA_3700
help
bubt - Burn a u-boot image to flash
#include <image.h>
#include <asm/cache.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#include <command.h>
#include <console.h>
#include <env.h>
}
}
-int pci_bar_show(struct udevice *dev)
+static int pci_bar_show(struct udevice *dev)
{
u8 header_type;
int bar_cnt, bar_id, mem_type;
*
* @dev: Bus+Device+Function number
*/
-void pci_header_show(struct udevice *dev)
+static void pci_header_show(struct udevice *dev)
{
unsigned long class, header_type;
}
}
-void pciinfo_header(int busnum, bool short_listing)
+static void pciinfo_header(int busnum, bool short_listing)
{
printf("Scanning PCI devices on bus %d\n", busnum);
"pvblock write addr blk# cnt - read/write `cnt'"
" blocks starting at block `blk#'\n"
" to/from memory address `addr'");
-
env = env_get("loadaddr");
load_addr = env ?
(void *)hextoul(env, NULL) :
-#ifdef CONFIG_LOADADDR
- (void *)CONFIG_LOADADDR;
-#else
- NULL;
-#endif
+ (void *)CONFIG_SYS_LOAD_ADDR;
env = env_get("ramdiskaddr");
initrd_addr = env ?
};
static struct sbi_ext extensions[] = {
- { 0x00000000, "sbi_set_timer" },
- { 0x00000001, "sbi_console_putchar" },
- { 0x00000002, "sbi_console_getchar" },
- { 0x00000003, "sbi_clear_ipi" },
- { 0x00000004, "sbi_send_ipi" },
- { 0x00000005, "sbi_remote_fence_i" },
- { 0x00000006, "sbi_remote_sfence_vma" },
- { 0x00000007, "sbi_remote_sfence_vma_asid" },
- { 0x00000008, "sbi_shutdown" },
- { 0x00000010, "SBI Base Functionality" },
- { 0x54494D45, "Timer Extension" },
- { 0x00735049, "IPI Extension" },
- { 0x52464E43, "RFENCE Extension" },
- { 0x0048534D, "Hart State Management Extension" },
- { 0x53525354, "System Reset Extension" },
+ { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" },
+ { SBI_EXT_0_1_CONSOLE_PUTCHAR, "sbi_console_putchar" },
+ { SBI_EXT_0_1_CONSOLE_GETCHAR, "sbi_console_getchar" },
+ { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" },
+ { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" },
+ { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" },
+ { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" },
+ { SBI_EXT_BASE, "SBI Base Functionality" },
+ { SBI_EXT_TIME, "Timer Extension" },
+ { SBI_EXT_IPI, "IPI Extension" },
+ { SBI_EXT_RFENCE, "RFENCE Extension" },
+ { SBI_EXT_HSM, "Hart State Management Extension" },
+ { SBI_EXT_SRST, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text,
U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable),
U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision));
-
" - id Session ID, passed to W7 (defaults to zero)\n"
);
#endif
-
static unsigned int cs;
static unsigned int mode;
static unsigned int freq;
-static int bitlen;
-static uchar dout[MAX_SPI_BYTES];
-static uchar din[MAX_SPI_BYTES];
+static int bitlen;
+static uchar dout[MAX_SPI_BYTES];
+static uchar din[MAX_SPI_BYTES];
static int do_spi_xfer(int bus, int cs)
{
NULL,
},
[SPL_EXPORT_ATAGS] = (const char * []) {
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
- defined(CONFIG_CMDLINE_TAG) || \
- defined(CONFIG_INITRD_TAG) || \
- defined(CONFIG_SERIAL_TAG) || \
- defined(CONFIG_REVISION_TAG)
+#ifdef CONFIG_SUPPORT_PASSING_ATAGS
"start",
"loados",
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
#include <common.h>
#include <command.h>
#include <env.h>
-#include <lz4.h>
+#include <u-boot/lz4.h>
static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
#include <common.h>
#include <command.h>
+#include <timestamp.h>
#include <version.h>
+#include <version_string.h>
#include <linux/compiler.h>
#ifdef CONFIG_SYS_COREBOOT
#include <asm/cb_sysinfo.h>
#endif
-const char __weak version_string[] = U_BOOT_VERSION_STRING;
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+ U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
+
+const char version_string[] = U_BOOT_VERSION_STRING;
static int do_version(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
default y if CONSOLE_MUX
help
This allows multiple input/output devices to be set at boot time.
- For example, if stdout is set to "serial,video" then output will
- be sent to both the serial and video devices on boot. The
+ For example, if stdout is set to "serial,vidconsole" then output
+ will be sent to both the serial and video devices on boot. The
environment variables can be updated after boot to change the
input/output devices.
help
Enabling this option calls 'misc_init_r' function
+config ID_EEPROM
+ bool "Enable I2C connected system identifier EEPROM"
+ help
+ A number of different systems and vendors enable a vendor-specified
+ EEPROM that contains various identifying features.
+
config PCI_INIT_R
bool "Enumerate PCI buses during init"
depends on PCI
config STACKPROTECTOR
bool "Stack Protector buffer overflow detection"
- default n
help
Enable stack smash detection through compiler's stack-protector
canary logic
config SPL_STACKPROTECTOR
bool "Stack Protector buffer overflow detection for SPL"
depends on STACKPROTECTOR && SPL
- default n
config TPL_STACKPROTECTOR
bool "Stack Protector buffer overflow detection for TPL"
depends on STACKPROTECTOR && TPL
- default n
endmenu
config UPDATE_COMMON
bool
- default n
select DFU_WRITE_ALT
config UPDATE_TFTP
config ANDROID_AB
bool "Android A/B updates"
- default n
help
If enabled, adds support for the new Android A/B update model. This
allows the bootloader to select which slot to boot from based on the
config FIT_RSASSA_PSS
bool "Support rsassa-pss signature scheme of FIT image contents"
depends on FIT_SIGNATURE
- default n
help
Enable this to support the pss padding algorithm as described
in the rfc8017 (https://tools.ietf.org/html/rfc8017).
select SPL_IMAGE_SIGN_INFO
select SPL_FIT_FULL_CHECK
+config SPL_FIT_SIGNATURE_MAX_SIZE
+ hex "Max size of signed FIT structures in SPL"
+ depends on SPL_FIT_SIGNATURE
+ default 0x10000000
+ help
+ This option sets a max size in bytes for verified FIT uImages.
+ A sane value of 256MB protects corrupted DTB structures from overlapping
+ device memory. Assure this size does not extend past expected storage
+ space.
+
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
distinguishing between booting Chrome OS in a basic way (developer
mode) and a full boot.
+config RAMBOOT_PBL
+ bool "Freescale PBL(pre-boot loader) image format support"
+ help
+ Some SoCs use PBL to load RCW and/or pre-initialization instructions.
+ For more details refer to doc/README.pblimage
+
+config SYS_FSL_PBL_PBI
+ string "PBI(pre-boot instructions) commands for the PBL image"
+ depends on RAMBOOT_PBL
+ help
+ PBI commands can be used to configure SoC before it starts the execution.
+ Please refer doc/README.pblimage for more details.
+
+config SYS_FSL_PBL_RCW
+ string "Aadditional RCW (Power on reset configuration) for the PBL image"
+ depends on RAMBOOT_PBL
+ help
+ Enables addition of RCW (Power on reset configuration) in built image.
+ Please refer doc/README.pblimage for more details.
+
endmenu # Boot images
menu "Boot timing"
config NAND_BOOT
bool "Support for booting from NAND flash"
- default n
imply MTD_RAW_NAND
help
Enabling this will make a U-Boot binary that is capable of being
config ONENAND_BOOT
bool "Support for booting from ONENAND"
- default n
imply MTD_RAW_NAND
help
Enabling this will make a U-Boot binary that is capable of being
config QSPI_BOOT
bool "Support for booting from QSPI flash"
- default n
help
Enabling this will make a U-Boot binary that is capable of being
booted via QSPI flash. This is not a must, some SoCs need this,
config SATA_BOOT
bool "Support for booting from SATA"
- default n
help
Enabling this will make a U-Boot binary that is capable of being
booted via SATA. This is not a must, some SoCs need this,
config SD_BOOT
bool "Support for booting from SD/EMMC"
- default n
help
Enabling this will make a U-Boot binary that is capable of being
booted via SD/EMMC. This is not a must, some SoCs need this,
config SPI_BOOT
bool "Support for booting from SPI flash"
- default n
help
Enabling this will make a U-Boot binary that is capable of being
booted via SPI flash. This is not a must, some SoCs need this,
config AUTOBOOT_KEYED
bool "Stop autobooting via specific input key / string"
- default n
help
This option enables stopping (aborting) of the automatic
boot feature only by issuing a specific input key or
config AUTOBOOT_KEYED_CTRLC
bool "Enable Ctrl-C autoboot interruption"
depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
- default n
help
This option allows for the boot sequence to be interrupted
by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
obj-$(CONFIG_DFU_OVER_USB) += dfu.o
endif
obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
-obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+obj-$(CONFIG_SPL_NET) += miiphyutil.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
ifdef CONFIG_SPL_USB_HOST
obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_TPL_SERIAL_SUPPORT) += console.o
+obj-$(CONFIG_TPL_SERIAL) += console.o
else
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o
+obj-$(CONFIG_SPL_SERIAL) += console.o
endif
else
obj-y += console.o
endif
endif
-obj-y += image.o
+obj-y += image.o image-board.o
obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o
obj-$(CONFIG_ANDROID_AB) += android_ab.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
#include <u-boot/sha256.h>
#include <bootcount.h>
#include <crypt.h>
+#include <dm/ofnode.h>
DECLARE_GLOBAL_DATA_PTR;
ulong addr;
/* Add an env variable to point to a kernel payload, if available */
- addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0);
+ addr = ofnode_conf_read_int("kernel-offset", 0);
if (addr)
env_set_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
/* Add an env variable to point to a root disk, if available */
- addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
+ addr = ofnode_conf_read_int("rootdisk-offset", 0);
if (addr)
env_set_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
#endif /* CONFIG_SYS_TEXT_BASE */
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
if (IS_ENABLED(CONFIG_OF_CONTROL))
- bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
- bootdelay);
+ bootdelay = ofnode_conf_read_int("bootdelay", bootdelay);
debug("### main_loop entered: bootdelay=%d\n\n", bootdelay);
return 0;
}
-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
static int init_func_i2c(void)
{
puts("I2C: ");
misc_init_f,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
init_func_i2c,
#endif
#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
#endif
#include <asm/sections.h>
#include <dm/root.h>
+#include <dm/ofnode.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <efi_loader.h>
static int should_load_env(void)
{
if (IS_ENABLED(CONFIG_OF_CONTROL))
- return fdtdec_get_config_int(gd->fdt_blob,
- "load-environment", 1);
+ return ofnode_conf_read_int("load-environment", 1);
if (IS_ENABLED(CONFIG_DELAY_ENVIRONMENT))
return 0;
#endif
INIT_FUNC_WATCHDOG_RESET
cpu_secondary_init_r,
-#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
+#if defined(CONFIG_ID_EEPROM)
mac_read_from_eeprom,
#endif
INIT_FUNC_WATCHDOG_RESET
images.os.arch = image_get_arch(os_hdr);
break;
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
if (fit_image_get_type(images.fit_hdr_os,
images.fit_noffset_os,
/* Kernel entry point is the setup.bin */
} else if (images.legacy_hdr_valid) {
images.ep = image_get_ep(&images.legacy_hdr_os_copy);
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
} else if (images.fit_uname_os) {
int ret;
return 1;
}
-#if IMAGE_ENABLE_OF_LIBFDT
+#if CONFIG_IS_ENABLED(OF_LIBFDT)
/* find flattened device tree */
ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
&images.ft_addr, &images.ft_len);
set_working_fdt_addr(map_to_sysmem(images.ft_addr));
#endif
-#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA)
- /* find bitstreams */
- ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
- NULL, NULL);
- if (ret) {
- printf("FPGA image is corrupted or invalid\n");
- return 1;
+#if CONFIG_IS_ENABLED(FIT)
+ if (IS_ENABLED(CONFIG_FPGA)) {
+ /* find bitstreams */
+ ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+ NULL, NULL);
+ if (ret) {
+ printf("FPGA image is corrupted or invalid\n");
+ return 1;
+ }
}
-#endif
/* find all of the loadables */
ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
}
}
#endif
-#if IMAGE_ENABLE_OF_LIBFDT && defined(CONFIG_LMB)
+#if CONFIG_IS_ENABLED(OF_LIBFDT) && defined(CONFIG_LMB)
if (!ret && (states & BOOTM_STATE_FDT)) {
boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
const void *buf;
const char *fit_uname_config = NULL;
const char *fit_uname_kernel = NULL;
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
int os_noffset;
#endif
bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
break;
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
os_noffset = fit_image_load(images, img_addr,
&fit_uname_kernel, &fit_uname_config,
}
#endif
+static void __maybe_unused fit_unsupported_reset(const char *msg)
+{
+ if (CONFIG_IS_ENABLED(FIT_VERBOSE)) {
+ printf("! FIT images not supported for '%s' - must reset board to recover!\n",
+ msg);
+ }
+}
+
#ifdef CONFIG_BOOTM_NETBSD
static int do_bootm_netbsd(int flag, int argc, char *const argv[],
bootm_headers_t *images)
#include <hang.h>
#include <malloc.h>
#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <dm/ofnode.h>
#ifdef CONFIG_CMDLINE
/*
bool cli_process_fdt(const char **cmdp)
{
/* Allow the fdt to override the boot command */
- char *env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd");
+ const char *env = ofnode_conf_read_str("bootcmd");
if (env)
*cmdp = env;
/*
* Always use 'env' in this case, since bootsecure requres that the
* bootcmd was specified in the FDT too.
*/
- return fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0) != 0;
+ return ofnode_conf_read_int("bootsecure", 0);
}
/*
#include <u-boot/crc.h>
#else
#include "mkimage.h"
+#include <linux/compiler_attributes.h>
#include <time.h>
+#include <linux/kconfig.h>
#endif /* !USE_HOSTCC*/
#include <hash.h>
static void reloc_update(void);
-#if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha1(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha1(struct hash_algo *algo, void **ctxp)
{
sha1_context *ctx = malloc(sizeof(sha1_context));
sha1_starts(ctx);
return 0;
}
-static int hash_update_sha1(struct hash_algo *algo, void *ctx, const void *buf,
- unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha1(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size,
+ int is_last)
{
sha1_update((sha1_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf,
- int size)
+static int __maybe_unused hash_finish_sha1(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA256) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha256(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha256(struct hash_algo *algo, void **ctxp)
{
sha256_context *ctx = malloc(sizeof(sha256_context));
sha256_starts(ctx);
return 0;
}
-static int hash_update_sha256(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha256(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha256_update((sha256_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha256(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA384) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha384(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha384(struct hash_algo *algo, void **ctxp)
{
sha512_context *ctx = malloc(sizeof(sha512_context));
sha384_starts(ctx);
return 0;
}
-static int hash_update_sha384(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha384(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha384_update((sha512_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha384(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA512) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha512(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha512(struct hash_algo *algo, void **ctxp)
{
sha512_context *ctx = malloc(sizeof(sha512_context));
sha512_starts(ctx);
return 0;
}
-static int hash_update_sha512(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha512(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha512_update((sha512_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha512(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-
static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp)
{
return 0;
}
-static int hash_init_crc32(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_crc32(struct hash_algo *algo, void **ctxp)
{
uint32_t *ctx = malloc(sizeof(uint32_t));
*ctx = 0;
return 0;
}
-static int hash_update_crc32(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_crc32(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size,
+ int is_last)
{
*((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), buf, size);
return 0;
}
-static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf,
- int size)
+static int __maybe_unused hash_finish_crc32(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
return 0;
}
-#ifdef USE_HOSTCC
-# define I_WANT_MD5 1
-#else
-# define I_WANT_MD5 CONFIG_IS_ENABLED(MD5)
-#endif
/*
* These are the hash algorithms we support. If we have hardware acceleration
* is enable we will use that, otherwise a software version of the algorithm.
* Note that algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
-#if I_WANT_MD5
+#if CONFIG_IS_ENABLED(MD5)
{
.name = "md5",
.digest_size = MD5_SUM_LEN,
.hash_func_ws = md5_wd,
},
#endif
-#ifdef CONFIG_SHA1
+#if CONFIG_IS_ENABLED(SHA1)
{
- .name = "sha1",
+ .name = "sha1",
.digest_size = SHA1_SUM_LEN,
.chunk_size = CHUNKSZ_SHA1,
-#ifdef CONFIG_SHA_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_HW_ACCEL)
.hash_func_ws = hw_sha1,
#else
.hash_func_ws = sha1_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
#endif
},
#endif
-#ifdef CONFIG_SHA256
+#if CONFIG_IS_ENABLED(SHA256)
{
.name = "sha256",
.digest_size = SHA256_SUM_LEN,
.chunk_size = CHUNKSZ_SHA256,
-#ifdef CONFIG_SHA_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_HW_ACCEL)
.hash_func_ws = hw_sha256,
#else
.hash_func_ws = sha256_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
#endif
},
#endif
-#ifdef CONFIG_SHA384
+#if CONFIG_IS_ENABLED(SHA384)
{
.name = "sha384",
.digest_size = SHA384_SUM_LEN,
.chunk_size = CHUNKSZ_SHA384,
-#ifdef CONFIG_SHA512_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL)
.hash_func_ws = hw_sha384,
#else
.hash_func_ws = sha384_csum_wd,
#endif
-#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
#endif
},
#endif
-#ifdef CONFIG_SHA512
+#if CONFIG_IS_ENABLED(SHA512)
{
.name = "sha512",
.digest_size = SHA512_SUM_LEN,
.chunk_size = CHUNKSZ_SHA512,
-#ifdef CONFIG_SHA512_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL)
.hash_func_ws = hw_sha512,
#else
.hash_func_ws = sha512_csum_wd,
#endif
-#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
.hash_update = hash_update_crc16_ccitt,
.hash_finish = hash_finish_crc16_ccitt,
},
+#if CONFIG_IS_ENABLED(CRC32)
{
.name = "crc32",
.digest_size = 4,
.hash_update = hash_update_crc32,
.hash_finish = hash_finish_crc32,
},
+#endif
};
/* Try to minimize code size for boards that don't want much hashing */
-#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) || \
- defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH) || \
- defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#if CONFIG_IS_ENABLED(SHA256) || CONFIG_IS_ENABLED(CMD_SHA1SUM) || \
+ CONFIG_IS_ENABLED(CRC32_VERIFY) || CONFIG_IS_ENABLED(CMD_HASH) || \
+ CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512)
#define multi_hash() 1
#else
#define multi_hash() 0
return 0;
}
-#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
+#if !defined(CONFIG_SPL_BUILD) && (defined(CONFIG_CMD_HASH) || \
+ defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32))
/**
* store_result: Store the resulting sum to an address or variable
*
*
* This call is similar to hwconfig_f(), except that it takes additional
* argument @subopt. In this example:
- * "dr_usb:mode=peripheral"
+ * "dr_usb:mode=peripheral"
* "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its
* argument.
*/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Image code used by boards (and not host tools)
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fpga.h>
+#include <image.h>
+#include <mapmem.h>
+#include <rtc.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+
+#ifndef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE 512
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * image_get_ramdisk - get and verify ramdisk image
+ * @rd_addr: ramdisk image start address
+ * @arch: expected ramdisk architecture
+ * @verify: checksum verification flag
+ *
+ * image_get_ramdisk() returns a pointer to the verified ramdisk image
+ * header. Routine receives image start address and expected architecture
+ * flag. Verification done covers data and header integrity and os/type/arch
+ * fields checking.
+ *
+ * returns:
+ * pointer to a ramdisk image header, if image was found and valid
+ * otherwise, return NULL
+ */
+static const image_header_t *image_get_ramdisk(ulong rd_addr, u8 arch,
+ int verify)
+{
+ const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
+
+ if (!image_check_magic(rd_hdr)) {
+ puts("Bad Magic Number\n");
+ bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
+ return NULL;
+ }
+
+ if (!image_check_hcrc(rd_hdr)) {
+ puts("Bad Header Checksum\n");
+ bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+ return NULL;
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
+ image_print_contents(rd_hdr);
+
+ if (verify) {
+ puts(" Verifying Checksum ... ");
+ if (!image_check_dcrc(rd_hdr)) {
+ puts("Bad Data CRC\n");
+ bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
+ return NULL;
+ }
+ puts("OK\n");
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+
+ if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
+ !image_check_arch(rd_hdr, arch) ||
+ !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
+ printf("No Linux %s Ramdisk Image\n",
+ genimg_get_arch_name(arch));
+ bootstage_error(BOOTSTAGE_ID_RAMDISK);
+ return NULL;
+ }
+
+ return rd_hdr;
+}
+
+/*****************************************************************************/
+/* Shared dual-format routines */
+/*****************************************************************************/
+ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */
+ulong image_save_addr; /* Default Save Address */
+ulong image_save_size; /* Default Save Size (in bytes) */
+
+static int on_loadaddr(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ switch (op) {
+ case env_op_create:
+ case env_op_overwrite:
+ image_load_addr = hextoul(value, NULL);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr);
+
+ulong env_get_bootm_low(void)
+{
+ char *s = env_get("bootm_low");
+
+ if (s) {
+ ulong tmp = hextoul(s, NULL);
+ return tmp;
+ }
+
+#if defined(CONFIG_SYS_SDRAM_BASE)
+ return CONFIG_SYS_SDRAM_BASE;
+#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
+ return gd->bd->bi_dram[0].start;
+#else
+ return 0;
+#endif
+}
+
+phys_size_t env_get_bootm_size(void)
+{
+ phys_size_t tmp, size;
+ phys_addr_t start;
+ char *s = env_get("bootm_size");
+
+ if (s) {
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ return tmp;
+ }
+
+ start = gd->ram_base;
+ size = gd->ram_size;
+
+ if (start + size > gd->ram_top)
+ size = gd->ram_top - start;
+
+ s = env_get("bootm_low");
+ if (s)
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ else
+ tmp = start;
+
+ return size - (tmp - start);
+}
+
+phys_size_t env_get_bootm_mapsize(void)
+{
+ phys_size_t tmp;
+ char *s = env_get("bootm_mapsize");
+
+ if (s) {
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ return tmp;
+ }
+
+#if defined(CONFIG_SYS_BOOTMAPSZ)
+ return CONFIG_SYS_BOOTMAPSZ;
+#else
+ return env_get_bootm_size();
+#endif
+}
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ if (to == from)
+ return;
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ if (to > from) {
+ from += len;
+ to += len;
+ }
+ while (len > 0) {
+ size_t tail = (len > chunksz) ? chunksz : len;
+
+ WATCHDOG_RESET();
+ if (to > from) {
+ to -= tail;
+ from -= tail;
+ }
+ memmove(to, from, tail);
+ if (to < from) {
+ to += tail;
+ from += tail;
+ }
+ len -= tail;
+ }
+#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+ memmove(to, from, len);
+#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+}
+
+/**
+ * genimg_get_kernel_addr_fit - get the real kernel address and return 2
+ * FIT strings
+ * @img_addr: a string might contain real image address
+ * @fit_uname_config: double pointer to a char, will hold pointer to a
+ * configuration unit name
+ * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
+ * name
+ *
+ * genimg_get_kernel_addr_fit get the real kernel start address from a string
+ * which is normally the first argv of bootm/bootz
+ *
+ * returns:
+ * kernel start address
+ */
+ulong genimg_get_kernel_addr_fit(char * const img_addr,
+ const char **fit_uname_config,
+ const char **fit_uname_kernel)
+{
+ ulong kernel_addr;
+
+ /* find out kernel image address */
+ if (!img_addr) {
+ kernel_addr = image_load_addr;
+ debug("* kernel: default image load address = 0x%08lx\n",
+ image_load_addr);
+ } else if (CONFIG_IS_ENABLED(FIT) &&
+ fit_parse_conf(img_addr, image_load_addr, &kernel_addr,
+ fit_uname_config)) {
+ debug("* kernel: config '%s' from image at 0x%08lx\n",
+ *fit_uname_config, kernel_addr);
+ } else if (CONFIG_IS_ENABLED(FIT) &&
+ fit_parse_subimage(img_addr, image_load_addr, &kernel_addr,
+ fit_uname_kernel)) {
+ debug("* kernel: subimage '%s' from image at 0x%08lx\n",
+ *fit_uname_kernel, kernel_addr);
+ } else {
+ kernel_addr = hextoul(img_addr, NULL);
+ debug("* kernel: cmdline image address = 0x%08lx\n",
+ kernel_addr);
+ }
+
+ return kernel_addr;
+}
+
+/**
+ * genimg_get_kernel_addr() is the simple version of
+ * genimg_get_kernel_addr_fit(). It ignores those return FIT strings
+ */
+ulong genimg_get_kernel_addr(char * const img_addr)
+{
+ const char *fit_uname_config = NULL;
+ const char *fit_uname_kernel = NULL;
+
+ return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config,
+ &fit_uname_kernel);
+}
+
+/**
+ * genimg_get_format - get image format type
+ * @img_addr: image start address
+ *
+ * genimg_get_format() checks whether provided address points to a valid
+ * legacy or FIT image.
+ *
+ * New uImage format and FDT blob are based on a libfdt. FDT blob
+ * may be passed directly or embedded in a FIT image. In both situations
+ * genimg_get_format() must be able to dectect libfdt header.
+ *
+ * returns:
+ * image format type or IMAGE_FORMAT_INVALID if no image is present
+ */
+int genimg_get_format(const void *img_addr)
+{
+ if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ const image_header_t *hdr;
+
+ hdr = (const image_header_t *)img_addr;
+ if (image_check_magic(hdr))
+ return IMAGE_FORMAT_LEGACY;
+ }
+ if (CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ if (!fdt_check_header(img_addr))
+ return IMAGE_FORMAT_FIT;
+ }
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) &&
+ !android_image_check_header(img_addr))
+ return IMAGE_FORMAT_ANDROID;
+
+ return IMAGE_FORMAT_INVALID;
+}
+
+/**
+ * fit_has_config - check if there is a valid FIT configuration
+ * @images: pointer to the bootm command headers structure
+ *
+ * fit_has_config() checks if there is a FIT configuration in use
+ * (if FTI support is present).
+ *
+ * returns:
+ * 0, no FIT support or no configuration found
+ * 1, configuration found
+ */
+int genimg_has_config(bootm_headers_t *images)
+{
+ if (CONFIG_IS_ENABLED(FIT) && images->fit_uname_cfg)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * select_ramdisk() - Select and locate the ramdisk to use
+ *
+ * @images: pointer to the bootm images structure
+ * @select: name of ramdisk to select, or NULL for any
+ * @arch: expected ramdisk architecture
+ * @rd_datap: pointer to a ulong variable, will hold ramdisk pointer
+ * @rd_lenp: pointer to a ulong variable, will hold ramdisk length
+ * @return 0 if OK, -ENOPKG if no ramdisk (but an error should not be reported),
+ * other -ve value on other error
+ */
+static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch,
+ ulong *rd_datap, ulong *rd_lenp)
+{
+ ulong rd_addr = 0;
+ char *buf;
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_ramdisk = NULL;
+ bool processed;
+ int rd_noffset;
+
+ if (select) {
+ ulong default_addr;
+ bool done = true;
+
+ if (CONFIG_IS_ENABLED(FIT)) {
+ /*
+ * If the init ramdisk comes from the FIT image and
+ * the FIT image address is omitted in the command
+ * line argument, try to use os FIT image address or
+ * default load address.
+ */
+ if (images->fit_uname_os)
+ default_addr = (ulong)images->fit_hdr_os;
+ else
+ default_addr = image_load_addr;
+
+ if (fit_parse_conf(select, default_addr, &rd_addr,
+ &fit_uname_config)) {
+ debug("* ramdisk: config '%s' from image at 0x%08lx\n",
+ fit_uname_config, rd_addr);
+ } else if (fit_parse_subimage(select, default_addr,
+ &rd_addr,
+ &fit_uname_ramdisk)) {
+ debug("* ramdisk: subimage '%s' from image at 0x%08lx\n",
+ fit_uname_ramdisk, rd_addr);
+ } else {
+ done = false;
+ }
+ }
+ if (!done) {
+ rd_addr = hextoul(select, NULL);
+ debug("* ramdisk: cmdline image address = 0x%08lx\n",
+ rd_addr);
+ }
+ } else if (CONFIG_IS_ENABLED(FIT)) {
+ /* use FIT configuration provided in first bootm
+ * command argument. If the property is not defined,
+ * quit silently (with -ENOPKG )
+ */
+ rd_addr = map_to_sysmem(images->fit_hdr_os);
+ rd_noffset = fit_get_node_from_config(images, FIT_RAMDISK_PROP,
+ rd_addr);
+ if (rd_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (rd_noffset < 0)
+ return rd_noffset;
+ }
+
+ /*
+ * Check if there is an initrd image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get FIT node.
+ */
+ buf = map_sysmem(rd_addr, 0);
+ processed = false;
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_LEGACY:
+ if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ const image_header_t *rd_hdr;
+
+ printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n",
+ rd_addr);
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
+ rd_hdr = image_get_ramdisk(rd_addr, arch, images->verify);
+ if (!rd_hdr)
+ return -ENOENT;
+
+ *rd_datap = image_get_data(rd_hdr);
+ *rd_lenp = image_get_data_size(rd_hdr);
+ processed = true;
+ }
+ break;
+ case IMAGE_FORMAT_FIT:
+ if (CONFIG_IS_ENABLED(FIT)) {
+ rd_noffset = fit_image_load(images, rd_addr,
+ &fit_uname_ramdisk,
+ &fit_uname_config, arch,
+ IH_TYPE_RAMDISK,
+ BOOTSTAGE_ID_FIT_RD_START,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ rd_datap, rd_lenp);
+ if (rd_noffset < 0)
+ return rd_noffset;
+
+ images->fit_hdr_rd = map_sysmem(rd_addr, 0);
+ images->fit_uname_rd = fit_uname_ramdisk;
+ images->fit_noffset_rd = rd_noffset;
+ processed = true;
+ }
+ break;
+ case IMAGE_FORMAT_ANDROID:
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ android_image_get_ramdisk((void *)images->os.start,
+ rd_datap, rd_lenp);
+ processed = true;
+ }
+ break;
+ }
+
+ if (!processed) {
+ if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) {
+ char *end = NULL;
+
+ if (select)
+ end = strchr(select, ':');
+ if (end) {
+ *rd_lenp = hextoul(++end, NULL);
+ *rd_datap = rd_addr;
+ processed = true;
+ }
+ }
+
+ if (!processed) {
+ puts("Wrong Ramdisk Image Format\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * boot_get_ramdisk - main ramdisk handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @images: pointer to the bootm images structure
+ * @arch: expected ramdisk architecture
+ * @rd_start: pointer to a ulong variable, will hold ramdisk start address
+ * @rd_end: pointer to a ulong variable, will hold ramdisk end
+ *
+ * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if ramdisk image was found and valid, or skiped
+ * rd_start and rd_end are set to ramdisk start/end addresses if
+ * ramdisk image is found and valid
+ *
+ * 1, if ramdisk image is found but corrupted, or invalid
+ * rd_start and rd_end are set to 0 if no ramdisk exists
+ */
+int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, ulong *rd_start, ulong *rd_end)
+{
+ ulong rd_data, rd_len;
+ const char *select = NULL;
+
+ *rd_start = 0;
+ *rd_end = 0;
+
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ char *buf;
+
+ /* Look for an Android boot image */
+ buf = map_sysmem(images->os.start, 0);
+ if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
+ select = (argc == 0) ? env_get("loadaddr") : argv[0];
+ }
+
+ if (argc >= 2)
+ select = argv[1];
+
+ /*
+ * Look for a '-' which indicates to ignore the
+ * ramdisk argument
+ */
+ if (select && strcmp(select, "-") == 0) {
+ debug("## Skipping init Ramdisk\n");
+ rd_len = 0;
+ rd_data = 0;
+ } else if (select || genimg_has_config(images)) {
+ int ret;
+
+ ret = select_ramdisk(images, select, arch, &rd_data, &rd_len);
+ if (ret == -ENOPKG)
+ return 0;
+ else if (ret)
+ return ret;
+ } else if (images->legacy_hdr_valid &&
+ image_check_type(&images->legacy_hdr_os_copy,
+ IH_TYPE_MULTI)) {
+ /*
+ * Now check if we have a legacy mult-component image,
+ * get second entry data start address and len.
+ */
+ bootstage_mark(BOOTSTAGE_ID_RAMDISK);
+ printf("## Loading init Ramdisk from multi component Legacy Image at %08lx ...\n",
+ (ulong)images->legacy_hdr_os);
+
+ image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
+ } else {
+ /*
+ * no initrd image
+ */
+ bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
+ rd_len = 0;
+ rd_data = 0;
+ }
+
+ if (!rd_data) {
+ debug("## No init Ramdisk\n");
+ } else {
+ *rd_start = rd_data;
+ *rd_end = rd_data + rd_len;
+ }
+ debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
+ *rd_start, *rd_end);
+
+ return 0;
+}
+
+/**
+ * boot_ramdisk_high - relocate init ramdisk
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @rd_data: ramdisk data start address
+ * @rd_len: ramdisk data length
+ * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
+ * start address (after possible relocation)
+ * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
+ * end address (after possible relocation)
+ *
+ * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment
+ * variable and if requested ramdisk data is moved to a specified location.
+ *
+ * Initrd_start and initrd_end are set to final (after relocation) ramdisk
+ * start/end addresses if ramdisk image start and len were provided,
+ * otherwise set initrd_start and initrd_end set to zeros.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+ ulong *initrd_start, ulong *initrd_end)
+{
+ char *s;
+ ulong initrd_high;
+ int initrd_copy_to_ram = 1;
+
+ s = env_get("initrd_high");
+ if (s) {
+ /* a value of "no" or a similar string will act like 0,
+ * turning the "load high" feature off. This is intentional.
+ */
+ initrd_high = hextoul(s, NULL);
+ if (initrd_high == ~0)
+ initrd_copy_to_ram = 0;
+ } else {
+ initrd_high = env_get_bootm_mapsize() + env_get_bootm_low();
+ }
+
+ debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
+ initrd_high, initrd_copy_to_ram);
+
+ if (rd_data) {
+ if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
+ debug(" in-place initrd\n");
+ *initrd_start = rd_data;
+ *initrd_end = rd_data + rd_len;
+ lmb_reserve(lmb, rd_data, rd_len);
+ } else {
+ if (initrd_high)
+ *initrd_start = (ulong)lmb_alloc_base(lmb,
+ rd_len, 0x1000, initrd_high);
+ else
+ *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
+ 0x1000);
+
+ if (*initrd_start == 0) {
+ puts("ramdisk - allocation error\n");
+ goto error;
+ }
+ bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
+
+ *initrd_end = *initrd_start + rd_len;
+ printf(" Loading Ramdisk to %08lx, end %08lx ... ",
+ *initrd_start, *initrd_end);
+
+ memmove_wd((void *)*initrd_start,
+ (void *)rd_data, rd_len, CHUNKSZ);
+
+ /*
+ * Ensure the image is flushed to memory to handle
+ * AMP boot scenarios in which we might not be
+ * HW cache coherent
+ */
+ if (IS_ENABLED(CONFIG_MP)) {
+ flush_cache((unsigned long)*initrd_start,
+ ALIGN(rd_len, ARCH_DMA_MINALIGN));
+ }
+ puts("OK\n");
+ }
+ } else {
+ *initrd_start = 0;
+ *initrd_end = 0;
+ }
+ debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
+ *initrd_start, *initrd_end);
+
+ return 0;
+
+error:
+ return -1;
+}
+
+int boot_get_setup(bootm_headers_t *images, u8 arch,
+ ulong *setup_start, ulong *setup_len)
+{
+ if (!CONFIG_IS_ENABLED(FIT))
+ return -ENOENT;
+
+ return boot_get_setup_fit(images, arch, setup_start, setup_len);
+}
+
+int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, const ulong *ld_start, ulong * const ld_len)
+{
+ ulong tmp_img_addr, img_data, img_len;
+ void *buf;
+ int conf_noffset;
+ int fit_img_result;
+ const char *uname, *name;
+ int err;
+ int devnum = 0; /* TODO support multi fpga platforms */
+
+ if (!IS_ENABLED(CONFIG_FPGA))
+ return -ENOSYS;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
+ NULL);
+ if (!uname) {
+ debug("## FPGA image is not specified\n");
+ return 0;
+ }
+ fit_img_result = fit_image_load(images,
+ tmp_img_addr,
+ (const char **)&uname,
+ &images->fit_uname_cfg,
+ arch,
+ IH_TYPE_FPGA,
+ BOOTSTAGE_ID_FPGA_INIT,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+
+ debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+ uname, img_data, img_len);
+
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ if (!fpga_is_partial_data(devnum, img_len)) {
+ name = "full";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_FULL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_FULL);
+ } else {
+ name = "partial";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_PARTIAL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_PARTIAL);
+ }
+
+ if (err)
+ return err;
+
+ printf(" Programming %s bitstream... OK\n", name);
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static void fit_loadable_process(u8 img_type,
+ ulong img_data,
+ ulong img_len)
+{
+ int i;
+ const unsigned int count =
+ ll_entry_count(struct fit_loadable_tbl, fit_loadable);
+ struct fit_loadable_tbl *fit_loadable_handler =
+ ll_entry_start(struct fit_loadable_tbl, fit_loadable);
+ /* For each loadable handler */
+ for (i = 0; i < count; i++, fit_loadable_handler++)
+ /* matching this type */
+ if (fit_loadable_handler->type == img_type)
+ /* call that handler with this image data */
+ fit_loadable_handler->handler(img_data, img_len);
+}
+
+int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, const ulong *ld_start, ulong * const ld_len)
+{
+ /*
+ * These variables are used to hold the current image location
+ * in system memory.
+ */
+ ulong tmp_img_addr;
+ /*
+ * These two variables are requirements for fit_image_load, but
+ * their values are not used
+ */
+ ulong img_data, img_len;
+ void *buf;
+ int loadables_index;
+ int conf_noffset;
+ int fit_img_result;
+ const char *uname;
+ u8 img_type;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ for (loadables_index = 0;
+ uname = fdt_stringlist_get(buf, conf_noffset,
+ FIT_LOADABLE_PROP,
+ loadables_index, NULL), uname;
+ loadables_index++) {
+ fit_img_result = fit_image_load(images, tmp_img_addr,
+ &uname,
+ &images->fit_uname_cfg,
+ arch, IH_TYPE_LOADABLE,
+ BOOTSTAGE_ID_FIT_LOADABLE_START,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_img_result = fit_image_get_node(buf, uname);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+ fit_img_result = fit_image_get_type(buf,
+ fit_img_result,
+ &img_type);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_loadable_process(img_type, img_data, img_len);
+ }
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * boot_get_cmdline - allocate and initialize kernel cmdline
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @cmd_start: pointer to a ulong variable, will hold cmdline start
+ * @cmd_end: pointer to a ulong variable, will hold cmdline end
+ *
+ * boot_get_cmdline() allocates space for kernel command line below
+ * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment
+ * variable is present its contents is copied to allocated kernel
+ * command line.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
+{
+ char *cmdline;
+ char *s;
+
+ cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
+ env_get_bootm_mapsize() + env_get_bootm_low());
+ if (!cmdline)
+ return -1;
+
+ s = env_get("bootargs");
+ if (!s)
+ s = "";
+
+ strcpy(cmdline, s);
+
+ *cmd_start = (ulong)cmdline;
+ *cmd_end = *cmd_start + strlen(cmdline);
+
+ debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
+
+ return 0;
+}
+
+/**
+ * boot_get_kbd - allocate and initialize kernel copy of board info
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @kbd: double pointer to board info data
+ *
+ * boot_get_kbd() allocates space for kernel copy of board info data below
+ * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized
+ * with the current u-boot board info data.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
+{
+ *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
+ sizeof(struct bd_info),
+ 0xf,
+ env_get_bootm_mapsize() +
+ env_get_bootm_low());
+ if (!*kbd)
+ return -1;
+
+ **kbd = *gd->bd;
+
+ debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
+
+#if defined(DEBUG)
+ if (IS_ENABLED(CONFIG_CMD_BDI)
+ do_bdinfo(NULL, 0, 0, NULL);
+#endif
+
+ return 0;
+}
+
+int image_setup_linux(bootm_headers_t *images)
+{
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ struct lmb *lmb = &images->lmb;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT))
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ if (IS_ENABLED(CONFIG_SYS_BOOT_GET_CMDLINE)) {
+ ret = boot_get_cmdline(lmb, &images->cmdline_start,
+ &images->cmdline_end);
+ if (ret) {
+ puts("ERROR with allocation of cmdline\n");
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+ }
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) {
+ ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void genimg_print_size(uint32_t size)
+{
+ printf("%d Bytes = ", size);
+ print_size(size, "\n");
+}
+
+void genimg_print_time(time_t timestamp)
+{
+ struct rtc_time tm;
+
+ rtc_to_tm(timestamp, &tm);
+ printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n",
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+}
}
/**
- * boot_get_fdt - main fdt handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @arch: architecture (IH_ARCH_...)
- * @images: pointer to the bootm images structure
- * @of_flat_tree: pointer to a char* variable, will hold fdt start address
- * @of_size: pointer to a ulong variable, will hold fdt length
- *
- * boot_get_fdt() is responsible for finding a valid flat device tree image.
- * Curently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if fdt image was found and valid, or skipped
- * of_flat_tree and of_size are set to fdt start address and length if
- * fdt image is found and valid
+ * select_fdt() - Select and locate the FDT to use
*
- * 1, if fdt image is found but corrupted
- * of_flat_tree and of_size are set to 0 if no fdt exists
+ * @images: pointer to the bootm images structure
+ * @select: name of FDT to select, or NULL for any
+ * @arch: expected FDT architecture
+ * @fdt_addrp: pointer to a ulong variable, will hold FDT pointer
+ * @return 0 if OK, -ENOPKG if no FDT (but an error should not be reported),
+ * other -ve value on other error
*/
-int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
- bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
-{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *fdt_hdr;
- ulong load, load_end;
- ulong image_start, image_data, image_end;
-#endif
- ulong img_addr;
- ulong fdt_addr;
- char *fdt_blob = NULL;
- void *buf;
-#if CONFIG_IS_ENABLED(FIT)
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_fdt = NULL;
- ulong default_addr;
- int fdt_noffset;
-#endif
- const char *select = NULL;
- *of_flat_tree = NULL;
- *of_size = 0;
-
- img_addr = (argc == 0) ? image_load_addr :
- hextoul(argv[0], NULL);
- buf = map_sysmem(img_addr, 0);
+static int select_fdt(bootm_headers_t *images, const char *select, u8 arch,
+ ulong *fdt_addrp)
+{
+ const char *buf;
+ ulong fdt_addr;
- if (argc > 2)
- select = argv[2];
- if (select || genimg_has_config(images)) {
#if CONFIG_IS_ENABLED(FIT)
- if (select) {
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_fdt = NULL;
+ ulong default_addr;
+ int fdt_noffset;
+
+ if (select) {
/*
* If the FDT blob comes from the FIT image and the
* FIT image address is omitted in the command line
else
default_addr = image_load_addr;
- if (fit_parse_conf(select, default_addr,
- &fdt_addr, &fit_uname_config)) {
+ if (fit_parse_conf(select, default_addr, &fdt_addr,
+ &fit_uname_config)) {
debug("* fdt: config '%s' from image at 0x%08lx\n",
fit_uname_config, fdt_addr);
- } else if (fit_parse_subimage(select, default_addr,
- &fdt_addr, &fit_uname_fdt)) {
+ } else if (fit_parse_subimage(select, default_addr, &fdt_addr,
+ &fit_uname_fdt)) {
debug("* fdt: subimage '%s' from image at 0x%08lx\n",
fit_uname_fdt, fdt_addr);
} else
#endif
- {
- fdt_addr = hextoul(select, NULL);
- debug("* fdt: cmdline image address = 0x%08lx\n",
- fdt_addr);
- }
-#if CONFIG_IS_ENABLED(FIT)
- } else {
- /* use FIT configuration provided in first bootm
- * command argument
- */
- fdt_addr = map_to_sysmem(images->fit_hdr_os);
- fdt_noffset = fit_get_node_from_config(images,
- FIT_FDT_PROP,
- fdt_addr);
- if (fdt_noffset == -ENOENT)
- return 0;
- else if (fdt_noffset < 0)
- return 1;
+ {
+ fdt_addr = hextoul(select, NULL);
+ debug("* fdt: cmdline image address = 0x%08lx\n",
+ fdt_addr);
}
-#endif
- debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
- fdt_addr);
-
- /*
- * Check if there is an FDT image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get a FIT node.
+#if CONFIG_IS_ENABLED(FIT)
+ } else {
+ /* use FIT configuration provided in first bootm
+ * command argument
*/
- buf = map_sysmem(fdt_addr, 0);
- switch (genimg_get_format(buf)) {
+ fdt_addr = map_to_sysmem(images->fit_hdr_os);
+ fdt_noffset = fit_get_node_from_config(images, FIT_FDT_PROP,
+ fdt_addr);
+ if (fdt_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (fdt_noffset < 0)
+ return fdt_noffset;
+ }
+#endif
+ debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
+ fdt_addr);
+
+ /*
+ * Check if there is an FDT image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get a FIT node.
+ */
+ buf = map_sysmem(fdt_addr, 0);
+ switch (genimg_get_format(buf)) {
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
+ case IMAGE_FORMAT_LEGACY: {
+ const image_header_t *fdt_hdr;
+ ulong load, load_end;
+ ulong image_start, image_data, image_end;
+
/* verify fdt_addr points to a valid image header */
printf("## Flattened Device Tree from Legacy Image at %08lx\n",
fdt_addr);
fdt_hdr = image_get_fdt(fdt_addr);
if (!fdt_hdr)
- goto no_fdt;
+ return -ENOPKG;
/*
* move image data to the load address,
if ((load < image_end) && (load_end > image_start)) {
fdt_error("fdt overwritten");
- goto error;
+ return -EFAULT;
}
debug(" Loading FDT from 0x%08lx to 0x%08lx\n",
fdt_addr = load;
break;
+ }
#endif
- case IMAGE_FORMAT_FIT:
- /*
- * This case will catch both: new uImage format
- * (libfdt based) and raw FDT blob (also libfdt
- * based).
- */
+ case IMAGE_FORMAT_FIT:
+ /*
+ * This case will catch both: new uImage format
+ * (libfdt based) and raw FDT blob (also libfdt
+ * based).
+ */
#if CONFIG_IS_ENABLED(FIT)
/* check FDT blob vs FIT blob */
if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) {
ulong load, len;
- fdt_noffset = boot_get_fdt_fit(images,
- fdt_addr, &fit_uname_fdt,
- &fit_uname_config,
- arch, &load, &len);
+ fdt_noffset = boot_get_fdt_fit(images, fdt_addr,
+ &fit_uname_fdt,
+ &fit_uname_config,
+ arch, &load, &len);
if (fdt_noffset < 0)
- goto error;
+ return -ENOENT;
images->fit_hdr_fdt = map_sysmem(fdt_addr, 0);
images->fit_uname_fdt = fit_uname_fdt;
fdt_addr = load;
break;
- } else
+ } else
#endif
- {
- /*
- * FDT blob
- */
- debug("* fdt: raw FDT blob\n");
- printf("## Flattened Device Tree blob at %08lx\n",
- (long)fdt_addr);
- }
- break;
- default:
- puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
- goto error;
+ {
+ /*
+ * FDT blob
+ */
+ debug("* fdt: raw FDT blob\n");
+ printf("## Flattened Device Tree blob at %08lx\n",
+ (long)fdt_addr);
}
+ break;
+ default:
+ puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
+ return -ENOENT;
+ }
+ *fdt_addrp = fdt_addr;
+
+ return 0;
+}
+
+/**
+ * boot_get_fdt - main fdt handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @arch: architecture (IH_ARCH_...)
+ * @images: pointer to the bootm images structure
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_get_fdt() is responsible for finding a valid flat device tree image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if fdt image was found and valid, or skipped
+ * of_flat_tree and of_size are set to fdt start address and length if
+ * fdt image is found and valid
+ *
+ * 1, if fdt image is found but corrupted
+ * of_flat_tree and of_size are set to 0 if no fdt exists
+ */
+int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
+ bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
+{
+ ulong img_addr;
+ ulong fdt_addr;
+ char *fdt_blob = NULL;
+ void *buf;
+ const char *select = NULL;
+ *of_flat_tree = NULL;
+ *of_size = 0;
+
+ img_addr = (argc == 0) ? image_load_addr : hextoul(argv[0], NULL);
+ buf = map_sysmem(img_addr, 0);
+
+ if (argc > 2)
+ select = argv[2];
+ if (select || genimg_has_config(images)) {
+ int ret;
+
+ ret = select_fdt(images, select, arch, &fdt_addr);
+ if (ret == -ENOPKG)
+ goto no_fdt;
+ else if (ret)
+ return 1;
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
fdt_blob = map_sysmem(fdt_addr, 0);
} else if (images->legacy_hdr_valid &&
/* Append PStore configuration */
fdt_fixup_pstore(blob);
#endif
- if (IMAGE_OF_BOARD_SETUP) {
+ if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) {
const char *skip_board_fixup;
skip_board_fixup = env_get("skip_board_fixup");
}
}
}
- if (IMAGE_OF_SYSTEM_SETUP) {
+ if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) {
fdt_ret = ft_system_setup(blob, gd->bd);
if (fdt_ret) {
printf("ERROR: system-specific fdt fixup failed: %s\n",
if (!ft_verify_fdt(blob))
goto err;
-#if defined(CONFIG_SOC_KEYSTONE)
- if (IMAGE_OF_BOARD_SETUP)
+#if defined(CONFIG_ARCH_KEYSTONE)
+ if (IS_ENABLED(CONFIG_OF_BOARD_SETUP))
ft_board_setup_ex(blob, gd->bd);
#endif
* Use malloc() except in SPL (to save code size). In SPL the caller
* must allocate the array.
*/
-#ifndef CONFIG_SPL_BUILD
- if (!region)
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && !region)
region = calloc(sizeof(*region), count);
-#endif
if (!region)
return NULL;
for (i = 0; i < count; i++) {
char *algo_name;
const char *padding_name;
- if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) {
+ if (fdt_totalsize(fit) > CONFIG_VAL(FIT_SIGNATURE_MAX_SIZE)) {
*err_msgp = "Total size too large";
return 1;
}
-
if (fit_image_hash_get_algo(fit, noffset, &algo_name)) {
*err_msgp = "Can't get hash algo property";
return -1;
#include <asm/io.h>
#include <malloc.h>
#include <asm/global_data.h>
+#ifdef CONFIG_DM_HASH
+#include <dm.h>
+#include <u-boot/hash.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
return count;
}
-#if CONFIG_IS_ENABLED(FIT_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT)
/**
* fit_image_print_data() - prints out the hash node details
* @fit: pointer to the FIT format image header
const char *p;
time_t timestamp;
+ if (!CONFIG_IS_ENABLED(FIT_PRINT))
+ return;
+
/* Indent string is defined in header image.h */
p = IMAGE_INDENT_STRING;
int ndepth;
int ret;
+ if (!CONFIG_IS_ENABLED(FIT_PRINT))
+ return;
+
/* Mandatory properties */
ret = fit_get_desc(fit, image_noffset, &desc);
printf("%s Description: ", p);
ret = fit_image_get_data_and_size(fit, image_noffset, &data, &size);
- if (!host_build()) {
+ if (!tools_build()) {
printf("%s Data Start: ", p);
if (ret) {
printf("unavailable\n");
}
}
}
-#else
-void fit_print_contents(const void *fit) { }
-void fit_image_print(const void *fit, int image_noffset, const char *p) { }
-#endif /* CONFIG_IS_ENABLED(FIR_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT) */
/**
* fit_get_desc - get node description property
int calculate_hash(const void *data, int data_len, const char *name,
uint8_t *value, int *value_len)
{
+#if !defined(USE_HOSTCC) && defined(CONFIG_DM_HASH)
+ int rc;
+ enum HASH_ALGO hash_algo;
+ struct udevice *dev;
+
+ rc = uclass_get_device(UCLASS_HASH, 0, &dev);
+ if (rc) {
+ debug("failed to get hash device, rc=%d\n", rc);
+ return -1;
+ }
+
+ hash_algo = hash_algo_lookup_by_name(algo);
+ if (hash_algo == HASH_ALGO_INVALID) {
+ debug("Unsupported hash algorithm\n");
+ return -1;
+ };
+
+ rc = hash_digest_wd(dev, hash_algo, data, data_len, value, CHUNKSZ);
+ if (rc) {
+ debug("failed to get hash value, rc=%d\n", rc);
+ return -1;
+ }
+
+ *value_len = hash_algo_digest_size(hash_algo);
+#else
struct hash_algo *algo;
int ret;
algo->hash_func_ws(data, data_len, value, algo->chunk_size);
*value_len = algo->digest_size;
+#endif
return 0;
}
}
printf("%s", algo);
- if (IMAGE_ENABLE_IGNORE) {
+ if (!tools_build()) {
fit_image_hash_get_ignore(fit, noffset, &ignore);
if (ignore) {
printf("-skipped ");
if (conf_uname == NULL) {
/* get configuration unit name from the default property */
debug("No configuration specified, trying default...\n");
- if (!host_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) {
+ if (!tools_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) {
noffset = fit_find_config_node(fit);
if (noffset < 0)
return noffset;
int type_ok, os_ok;
ulong load, load_end, data, len;
uint8_t os, comp;
-#ifndef USE_HOSTCC
- uint8_t os_arch;
-#endif
const char *prop_name;
int ret;
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
- if (!host_build() && IS_ENABLED(CONFIG_SANDBOX)) {
+ if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX)) {
if (!fit_image_check_target_arch(fit, noffset)) {
puts("Unsupported Architecture\n");
bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
}
#ifndef USE_HOSTCC
+ {
+ uint8_t os_arch;
+
fit_image_get_arch(fit, noffset, &os_arch);
images->os.arch = os_arch;
+ }
#endif
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
}
/* perform any post-processing on the image data */
- if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
+ if (!tools_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
board_fit_image_post_process(fit, noffset, &buf, &size);
len = (ulong)size;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Image code used by host tools (and not boards)
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <time.h>
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ memmove(to, from, len);
+}
+
+void genimg_print_size(uint32_t size)
+{
+ printf("%d Bytes = %.2f KiB = %.2f MiB\n", size, (double)size / 1.024e3,
+ (double)size / 1.048576e6);
+}
+
+void genimg_print_time(time_t timestamp)
+{
+ printf("%s", ctime(×tamp));
+}
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <image.h>
+#include <relocate.h>
#include <u-boot/ecdsa.h>
#include <u-boot/rsa.h>
#include <u-boot/hash-checksum.h>
int i;
const char *name;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ static bool done;
- if (!done) {
- done = true;
- for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
- checksum_algos[i].name += gd->reloc_off;
- checksum_algos[i].calculate += gd->reloc_off;
+ if (!done) {
+ done = true;
+ for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
+ struct checksum_algo *algo = &checksum_algos[i];
+
+ MANUAL_RELOC(algo->name);
+ MANUAL_RELOC(algo->calculate);
+ }
}
}
-#endif
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
name = checksum_algos[i].name;
struct crypto_algo *crypto, *end;
const char *name;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
-
- if (!done) {
- crypto = ll_entry_start(struct crypto_algo, cryptos);
- end = ll_entry_end(struct crypto_algo, cryptos);
- for (; crypto < end; crypto++) {
- crypto->name += gd->reloc_off;
- crypto->verify += gd->reloc_off;
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ static bool done;
+
+ if (!done) {
+ done = true;
+ crypto = ll_entry_start(struct crypto_algo, cryptos);
+ end = ll_entry_end(struct crypto_algo, cryptos);
+ for (; crypto < end; crypto++) {
+ MANUAL_RELOC(crypto->name);
+ MANUAL_RELOC(crypto->verify);
+ }
}
}
-#endif
/* Move name to after the comma */
name = strchr(full_name, ',');
#ifndef USE_HOSTCC
#include <common.h>
-#include <bootstage.h>
-#include <cpu_func.h>
#include <env.h>
#include <lmb.h>
#include <log.h>
#include <malloc.h>
-#include <asm/cache.h>
#include <u-boot/crc.h>
-#include <watchdog.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
#include <status_led.h>
#endif
-#include <rtc.h>
-
-#include <gzip.h>
-#include <image.h>
-#include <lz4.h>
-#include <mapmem.h>
-
-#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
+#if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)
#include <linux/libfdt.h>
#include <fdt_support.h>
-#include <fpga.h>
-#include <xilinx.h>
#endif
#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/io.h>
-#include <bzlib.h>
-#include <linux/lzo.h>
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-#include <linux/zstd.h>
-
#ifdef CONFIG_CMD_BDI
extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
- int verify);
-#endif
+/* Set this if we have less than 4 MB of malloc() space */
+#if CONFIG_SYS_MALLOC_LEN < (4096 * 1024)
+#define CONSERVE_MEMORY true
#else
+#define CONSERVE_MEMORY false
+#endif
+
+#else /* USE_HOSTCC */
#include "mkimage.h"
#include <u-boot/md5.h>
#include <time.h>
-#include <image.h>
#ifndef __maybe_unused
# define __maybe_unused /* unimplemented */
#endif
+
+#define CONSERVE_MEMORY false
+
#endif /* !USE_HOSTCC*/
-#include <u-boot/crc.h>
+#include <abuf.h>
+#include <bzlib.h>
+#include <display_options.h>
+#include <gzip.h>
+#include <image.h>
#include <imximage.h>
-
-#ifndef CONFIG_SYS_BARGSIZE
-#define CONFIG_SYS_BARGSIZE 512
-#endif
+#include <relocate.h>
+#include <linux/lzo.h>
+#include <linux/zstd.h>
+#include <linux/kconfig.h>
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+#include <u-boot/crc.h>
+#include <u-boot/lz4.h>
static const table_entry_t uimage_arch[] = {
{ IH_ARCH_INVALID, "invalid", "Invalid ARCH", },
{ IH_COMP_GZIP, "gzip", {0x1f, 0x8b},},
{ IH_COMP_LZMA, "lzma", {0x5d, 0x00},},
{ IH_COMP_LZO, "lzo", {0x89, 0x4c},},
+ { IH_COMP_LZ4, "lz4", {0x04, 0x22},},
+ { IH_COMP_ZSTD, "zstd", {0x28, 0xb5},},
{ IH_COMP_NONE, "none", {}, },
};
void *load_buf, void *image_buf, ulong image_len,
uint unc_len, ulong *load_end)
{
- int ret = 0;
+ int ret = -ENOSYS;
*load_end = load;
print_decomp_msg(comp, type, load == image_start);
*/
switch (comp) {
case IH_COMP_NONE:
+ ret = 0;
if (load == image_start)
break;
if (image_len <= unc_len)
else
ret = -ENOSPC;
break;
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(GZIP)
- case IH_COMP_GZIP: {
- ret = gunzip(load_buf, unc_len, image_buf, &image_len);
- break;
- }
-#endif /* CONFIG_GZIP */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(BZIP2)
- case IH_COMP_BZIP2: {
- uint size = unc_len;
-
- /*
- * If we've got less than 4 MB of malloc() space,
- * use slower decompression algorithm which requires
- * at most 2300 KB of memory.
- */
- ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
- image_buf, image_len,
- CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
- image_len = size;
+ case IH_COMP_GZIP:
+ if (!tools_build() && CONFIG_IS_ENABLED(GZIP))
+ ret = gunzip(load_buf, unc_len, image_buf, &image_len);
break;
- }
-#endif /* CONFIG_BZIP2 */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZMA)
- case IH_COMP_LZMA: {
- SizeT lzma_len = unc_len;
+ case IH_COMP_BZIP2:
+ if (!tools_build() && CONFIG_IS_ENABLED(BZIP2)) {
+ uint size = unc_len;
- ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
- image_buf, image_len);
- image_len = lzma_len;
+ /*
+ * If we've got less than 4 MB of malloc() space,
+ * use slower decompression algorithm which requires
+ * at most 2300 KB of memory.
+ */
+ ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
+ image_buf, image_len, CONSERVE_MEMORY, 0);
+ image_len = size;
+ }
break;
- }
-#endif /* CONFIG_LZMA */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZO)
- case IH_COMP_LZO: {
- size_t size = unc_len;
+ case IH_COMP_LZMA:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZMA)) {
+ SizeT lzma_len = unc_len;
- ret = lzop_decompress(image_buf, image_len, load_buf, &size);
- image_len = size;
+ ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
+ image_buf, image_len);
+ image_len = lzma_len;
+ }
break;
- }
-#endif /* CONFIG_LZO */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZ4)
- case IH_COMP_LZ4: {
- size_t size = unc_len;
+ case IH_COMP_LZO:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZO)) {
+ size_t size = unc_len;
- ret = ulz4fn(image_buf, image_len, load_buf, &size);
- image_len = size;
- break;
- }
-#endif /* CONFIG_LZ4 */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(ZSTD)
- case IH_COMP_ZSTD: {
- size_t size = unc_len;
- ZSTD_DStream *dstream;
- ZSTD_inBuffer in_buf;
- ZSTD_outBuffer out_buf;
- void *workspace;
- size_t wsize;
-
- wsize = ZSTD_DStreamWorkspaceBound(image_len);
- workspace = malloc(wsize);
- if (!workspace) {
- debug("%s: cannot allocate workspace of size %zu\n", __func__,
- wsize);
- return -1;
+ ret = lzop_decompress(image_buf, image_len, load_buf, &size);
+ image_len = size;
}
+ break;
+ case IH_COMP_LZ4:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZ4)) {
+ size_t size = unc_len;
- dstream = ZSTD_initDStream(image_len, workspace, wsize);
- if (!dstream) {
- printf("%s: ZSTD_initDStream failed\n", __func__);
- return ZSTD_getErrorCode(ret);
+ ret = ulz4fn(image_buf, image_len, load_buf, &size);
+ image_len = size;
}
-
- in_buf.src = image_buf;
- in_buf.pos = 0;
- in_buf.size = image_len;
-
- out_buf.dst = load_buf;
- out_buf.pos = 0;
- out_buf.size = size;
-
- while (1) {
- size_t ret;
-
- ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
- if (ZSTD_isError(ret)) {
- printf("%s: ZSTD_decompressStream error %d\n", __func__,
- ZSTD_getErrorCode(ret));
- return ZSTD_getErrorCode(ret);
+ break;
+ case IH_COMP_ZSTD:
+ if (!tools_build() && CONFIG_IS_ENABLED(ZSTD)) {
+ struct abuf in, out;
+
+ abuf_init_set(&in, image_buf, image_len);
+ abuf_init_set(&in, load_buf, unc_len);
+ ret = zstd_decompress(&in, &out);
+ if (ret >= 0) {
+ image_len = ret;
+ ret = 0;
}
-
- if (in_buf.pos >= image_len || !ret)
- break;
}
-
- image_len = out_buf.pos;
-
break;
}
-#endif /* CONFIG_ZSTD */
-#endif
- default:
+ if (ret == -ENOSYS) {
printf("Unimplemented compression type %d\n", comp);
- return -ENOSYS;
+ return ret;
}
+ if (ret)
+ return ret;
*load_end = load + image_len;
- return ret;
-}
-
-
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-/**
- * image_get_ramdisk - get and verify ramdisk image
- * @rd_addr: ramdisk image start address
- * @arch: expected ramdisk architecture
- * @verify: checksum verification flag
- *
- * image_get_ramdisk() returns a pointer to the verified ramdisk image
- * header. Routine receives image start address and expected architecture
- * flag. Verification done covers data and header integrity and os/type/arch
- * fields checking.
- *
- * returns:
- * pointer to a ramdisk image header, if image was found and valid
- * otherwise, return NULL
- */
-static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
- int verify)
-{
- const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
-
- if (!image_check_magic(rd_hdr)) {
- puts("Bad Magic Number\n");
- bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
- return NULL;
- }
-
- if (!image_check_hcrc(rd_hdr)) {
- puts("Bad Header Checksum\n");
- bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
- return NULL;
- }
-
- bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
- image_print_contents(rd_hdr);
-
- if (verify) {
- puts(" Verifying Checksum ... ");
- if (!image_check_dcrc(rd_hdr)) {
- puts("Bad Data CRC\n");
- bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
- return NULL;
- }
- puts("OK\n");
- }
-
- bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
-
- if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
- !image_check_arch(rd_hdr, arch) ||
- !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
- printf("No Linux %s Ramdisk Image\n",
- genimg_get_arch_name(arch));
- bootstage_error(BOOTSTAGE_ID_RAMDISK);
- return NULL;
- }
-
- return rd_hdr;
-}
-#endif
-#endif /* !USE_HOSTCC */
-
-/*****************************************************************************/
-/* Shared dual-format routines */
-/*****************************************************************************/
-#ifndef USE_HOSTCC
-ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */
-ulong image_save_addr; /* Default Save Address */
-ulong image_save_size; /* Default Save Size (in bytes) */
-
-static int on_loadaddr(const char *name, const char *value, enum env_op op,
- int flags)
-{
- switch (op) {
- case env_op_create:
- case env_op_overwrite:
- image_load_addr = hextoul(value, NULL);
- break;
- default:
- break;
- }
-
- return 0;
-}
-U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr);
-
-ulong env_get_bootm_low(void)
-{
- char *s = env_get("bootm_low");
- if (s) {
- ulong tmp = hextoul(s, NULL);
- return tmp;
- }
-
-#if defined(CONFIG_SYS_SDRAM_BASE)
- return CONFIG_SYS_SDRAM_BASE;
-#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
- return gd->bd->bi_dram[0].start;
-#else
return 0;
-#endif
-}
-
-phys_size_t env_get_bootm_size(void)
-{
- phys_size_t tmp, size;
- phys_addr_t start;
- char *s = env_get("bootm_size");
- if (s) {
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- return tmp;
- }
-
- start = gd->ram_base;
- size = gd->ram_size;
-
- if (start + size > gd->ram_top)
- size = gd->ram_top - start;
-
- s = env_get("bootm_low");
- if (s)
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- else
- tmp = start;
-
- return size - (tmp - start);
-}
-
-phys_size_t env_get_bootm_mapsize(void)
-{
- phys_size_t tmp;
- char *s = env_get("bootm_mapsize");
- if (s) {
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- return tmp;
- }
-
-#if defined(CONFIG_SYS_BOOTMAPSZ)
- return CONFIG_SYS_BOOTMAPSZ;
-#else
- return env_get_bootm_size();
-#endif
-}
-
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- if (to == from)
- return;
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- if (to > from) {
- from += len;
- to += len;
- }
- while (len > 0) {
- size_t tail = (len > chunksz) ? chunksz : len;
- WATCHDOG_RESET();
- if (to > from) {
- to -= tail;
- from -= tail;
- }
- memmove(to, from, tail);
- if (to < from) {
- to += tail;
- from += tail;
- }
- len -= tail;
- }
-#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
- memmove(to, from, len);
-#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
-}
-#else /* USE_HOSTCC */
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- memmove(to, from, len);
-}
-#endif /* !USE_HOSTCC */
-
-void genimg_print_size(uint32_t size)
-{
-#ifndef USE_HOSTCC
- printf("%d Bytes = ", size);
- print_size(size, "\n");
-#else
- printf("%d Bytes = %.2f KiB = %.2f MiB\n",
- size, (double)size / 1.024e3,
- (double)size / 1.048576e6);
-#endif
-}
-
-#if IMAGE_ENABLE_TIMESTAMP
-void genimg_print_time(time_t timestamp)
-{
-#ifndef USE_HOSTCC
- struct rtc_time tm;
-
- rtc_to_tm(timestamp, &tm);
- printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tm.tm_year, tm.tm_mon, tm.tm_mday,
- tm.tm_hour, tm.tm_min, tm.tm_sec);
-#else
- printf("%s", ctime(×tamp));
-#endif
}
-#endif
const table_entry_t *get_table_entry(const table_entry_t *table, int id)
{
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return entry->lname;
-#else
- return entry->lname + gd->reloc_off;
-#endif
+ return manual_reloc(entry->lname);
}
/**
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return entry->sname;
-#else
- return entry->sname + gd->reloc_off;
-#endif
+ return manual_reloc(entry->sname);
}
int genimg_get_cat_count(enum ih_category category)
table = get_table_entry(table, id);
if (!table)
return msg;
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return table->lname;
-#else
- return table->lname + gd->reloc_off;
-#endif
+ return manual_reloc(table->lname);
}
const char *genimg_get_os_name(uint8_t os)
table = get_table_entry(table, val);
if (!table)
return "unknown";
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return table->sname;
-#else
- return table->sname + gd->reloc_off;
-#endif
+ return manual_reloc(table->sname);
}
const char *genimg_get_type_short_name(uint8_t type)
const table_entry_t *t;
for (t = table; t->id >= 0; ++t) {
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- if (t->sname && strcasecmp(t->sname + gd->reloc_off, name) == 0)
-#else
- if (t->sname && strcasecmp(t->sname, name) == 0)
-#endif
- return (t->id);
+ if (t->sname && !strcasecmp(manual_reloc(t->sname), name))
+ return t->id;
}
debug("Invalid %s Type: %s\n", table_name, name);
{
return (get_table_entry_id(uimage_comp, "Compression", name));
}
-
-#ifndef USE_HOSTCC
-/**
- * genimg_get_kernel_addr_fit - get the real kernel address and return 2
- * FIT strings
- * @img_addr: a string might contain real image address
- * @fit_uname_config: double pointer to a char, will hold pointer to a
- * configuration unit name
- * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
- * name
- *
- * genimg_get_kernel_addr_fit get the real kernel start address from a string
- * which is normally the first argv of bootm/bootz
- *
- * returns:
- * kernel start address
- */
-ulong genimg_get_kernel_addr_fit(char * const img_addr,
- const char **fit_uname_config,
- const char **fit_uname_kernel)
-{
- ulong kernel_addr;
-
- /* find out kernel image address */
- if (!img_addr) {
- kernel_addr = image_load_addr;
- debug("* kernel: default image load address = 0x%08lx\n",
- image_load_addr);
-#if CONFIG_IS_ENABLED(FIT)
- } else if (fit_parse_conf(img_addr, image_load_addr, &kernel_addr,
- fit_uname_config)) {
- debug("* kernel: config '%s' from image at 0x%08lx\n",
- *fit_uname_config, kernel_addr);
- } else if (fit_parse_subimage(img_addr, image_load_addr, &kernel_addr,
- fit_uname_kernel)) {
- debug("* kernel: subimage '%s' from image at 0x%08lx\n",
- *fit_uname_kernel, kernel_addr);
-#endif
- } else {
- kernel_addr = hextoul(img_addr, NULL);
- debug("* kernel: cmdline image address = 0x%08lx\n",
- kernel_addr);
- }
-
- return kernel_addr;
-}
-
-/**
- * genimg_get_kernel_addr() is the simple version of
- * genimg_get_kernel_addr_fit(). It ignores those return FIT strings
- */
-ulong genimg_get_kernel_addr(char * const img_addr)
-{
- const char *fit_uname_config = NULL;
- const char *fit_uname_kernel = NULL;
-
- return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config,
- &fit_uname_kernel);
-}
-
-/**
- * genimg_get_format - get image format type
- * @img_addr: image start address
- *
- * genimg_get_format() checks whether provided address points to a valid
- * legacy or FIT image.
- *
- * New uImage format and FDT blob are based on a libfdt. FDT blob
- * may be passed directly or embedded in a FIT image. In both situations
- * genimg_get_format() must be able to dectect libfdt header.
- *
- * returns:
- * image format type or IMAGE_FORMAT_INVALID if no image is present
- */
-int genimg_get_format(const void *img_addr)
-{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *hdr;
-
- hdr = (const image_header_t *)img_addr;
- if (image_check_magic(hdr))
- return IMAGE_FORMAT_LEGACY;
-#endif
-#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
- if (fdt_check_header(img_addr) == 0)
- return IMAGE_FORMAT_FIT;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- if (android_image_check_header(img_addr) == 0)
- return IMAGE_FORMAT_ANDROID;
-#endif
-
- return IMAGE_FORMAT_INVALID;
-}
-
-/**
- * fit_has_config - check if there is a valid FIT configuration
- * @images: pointer to the bootm command headers structure
- *
- * fit_has_config() checks if there is a FIT configuration in use
- * (if FTI support is present).
- *
- * returns:
- * 0, no FIT support or no configuration found
- * 1, configuration found
- */
-int genimg_has_config(bootm_headers_t *images)
-{
-#if IMAGE_ENABLE_FIT
- if (images->fit_uname_cfg)
- return 1;
-#endif
- return 0;
-}
-
-/**
- * boot_get_ramdisk - main ramdisk handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @images: pointer to the bootm images structure
- * @arch: expected ramdisk architecture
- * @rd_start: pointer to a ulong variable, will hold ramdisk start address
- * @rd_end: pointer to a ulong variable, will hold ramdisk end
- *
- * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
- * Curently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if ramdisk image was found and valid, or skiped
- * rd_start and rd_end are set to ramdisk start/end addresses if
- * ramdisk image is found and valid
- *
- * 1, if ramdisk image is found but corrupted, or invalid
- * rd_start and rd_end are set to 0 if no ramdisk exists
- */
-int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, ulong *rd_start, ulong *rd_end)
-{
- ulong rd_addr, rd_load;
- ulong rd_data, rd_len;
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *rd_hdr;
-#endif
- void *buf;
-#ifdef CONFIG_SUPPORT_RAW_INITRD
- char *end;
-#endif
-#if IMAGE_ENABLE_FIT
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_ramdisk = NULL;
- ulong default_addr;
- int rd_noffset;
-#endif
- const char *select = NULL;
-
- *rd_start = 0;
- *rd_end = 0;
-
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- /*
- * Look for an Android boot image.
- */
- buf = map_sysmem(images->os.start, 0);
- if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
- select = (argc == 0) ? env_get("loadaddr") : argv[0];
-#endif
-
- if (argc >= 2)
- select = argv[1];
-
- /*
- * Look for a '-' which indicates to ignore the
- * ramdisk argument
- */
- if (select && strcmp(select, "-") == 0) {
- debug("## Skipping init Ramdisk\n");
- rd_len = rd_data = 0;
- } else if (select || genimg_has_config(images)) {
-#if IMAGE_ENABLE_FIT
- if (select) {
- /*
- * If the init ramdisk comes from the FIT image and
- * the FIT image address is omitted in the command
- * line argument, try to use os FIT image address or
- * default load address.
- */
- if (images->fit_uname_os)
- default_addr = (ulong)images->fit_hdr_os;
- else
- default_addr = image_load_addr;
-
- if (fit_parse_conf(select, default_addr,
- &rd_addr, &fit_uname_config)) {
- debug("* ramdisk: config '%s' from image at "
- "0x%08lx\n",
- fit_uname_config, rd_addr);
- } else if (fit_parse_subimage(select, default_addr,
- &rd_addr, &fit_uname_ramdisk)) {
- debug("* ramdisk: subimage '%s' from image at "
- "0x%08lx\n",
- fit_uname_ramdisk, rd_addr);
- } else
-#endif
- {
- rd_addr = hextoul(select, NULL);
- debug("* ramdisk: cmdline image address = "
- "0x%08lx\n",
- rd_addr);
- }
-#if IMAGE_ENABLE_FIT
- } else {
- /* use FIT configuration provided in first bootm
- * command argument. If the property is not defined,
- * quit silently.
- */
- rd_addr = map_to_sysmem(images->fit_hdr_os);
- rd_noffset = fit_get_node_from_config(images,
- FIT_RAMDISK_PROP, rd_addr);
- if (rd_noffset == -ENOENT)
- return 0;
- else if (rd_noffset < 0)
- return 1;
- }
-#endif
-
- /*
- * Check if there is an initrd image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get FIT node.
- */
- buf = map_sysmem(rd_addr, 0);
- switch (genimg_get_format(buf)) {
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
- printf("## Loading init Ramdisk from Legacy "
- "Image at %08lx ...\n", rd_addr);
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
- rd_hdr = image_get_ramdisk(rd_addr, arch,
- images->verify);
-
- if (rd_hdr == NULL)
- return 1;
-
- rd_data = image_get_data(rd_hdr);
- rd_len = image_get_data_size(rd_hdr);
- rd_load = image_get_load(rd_hdr);
- break;
-#endif
-#if IMAGE_ENABLE_FIT
- case IMAGE_FORMAT_FIT:
- rd_noffset = fit_image_load(images,
- rd_addr, &fit_uname_ramdisk,
- &fit_uname_config, arch,
- IH_TYPE_RAMDISK,
- BOOTSTAGE_ID_FIT_RD_START,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &rd_data, &rd_len);
- if (rd_noffset < 0)
- return 1;
-
- images->fit_hdr_rd = map_sysmem(rd_addr, 0);
- images->fit_uname_rd = fit_uname_ramdisk;
- images->fit_noffset_rd = rd_noffset;
- break;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- case IMAGE_FORMAT_ANDROID:
- android_image_get_ramdisk((void *)images->os.start,
- &rd_data, &rd_len);
- break;
-#endif
- default:
-#ifdef CONFIG_SUPPORT_RAW_INITRD
- end = NULL;
- if (select)
- end = strchr(select, ':');
- if (end) {
- rd_len = hextoul(++end, NULL);
- rd_data = rd_addr;
- } else
-#endif
- {
- puts("Wrong Ramdisk Image Format\n");
- rd_data = rd_len = rd_load = 0;
- return 1;
- }
- }
- } else if (images->legacy_hdr_valid &&
- image_check_type(&images->legacy_hdr_os_copy,
- IH_TYPE_MULTI)) {
-
- /*
- * Now check if we have a legacy mult-component image,
- * get second entry data start address and len.
- */
- bootstage_mark(BOOTSTAGE_ID_RAMDISK);
- printf("## Loading init Ramdisk from multi component "
- "Legacy Image at %08lx ...\n",
- (ulong)images->legacy_hdr_os);
-
- image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
- } else {
- /*
- * no initrd image
- */
- bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
- rd_len = rd_data = 0;
- }
-
- if (!rd_data) {
- debug("## No init Ramdisk\n");
- } else {
- *rd_start = rd_data;
- *rd_end = rd_data + rd_len;
- }
- debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
- *rd_start, *rd_end);
-
- return 0;
-}
-
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
-/**
- * boot_ramdisk_high - relocate init ramdisk
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @rd_data: ramdisk data start address
- * @rd_len: ramdisk data length
- * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
- * start address (after possible relocation)
- * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
- * end address (after possible relocation)
- *
- * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment
- * variable and if requested ramdisk data is moved to a specified location.
- *
- * Initrd_start and initrd_end are set to final (after relocation) ramdisk
- * start/end addresses if ramdisk image start and len were provided,
- * otherwise set initrd_start and initrd_end set to zeros.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
- ulong *initrd_start, ulong *initrd_end)
-{
- char *s;
- ulong initrd_high;
- int initrd_copy_to_ram = 1;
-
- s = env_get("initrd_high");
- if (s) {
- /* a value of "no" or a similar string will act like 0,
- * turning the "load high" feature off. This is intentional.
- */
- initrd_high = hextoul(s, NULL);
- if (initrd_high == ~0)
- initrd_copy_to_ram = 0;
- } else {
- initrd_high = env_get_bootm_mapsize() + env_get_bootm_low();
- }
-
-
- debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
- initrd_high, initrd_copy_to_ram);
-
- if (rd_data) {
- if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
- debug(" in-place initrd\n");
- *initrd_start = rd_data;
- *initrd_end = rd_data + rd_len;
- lmb_reserve(lmb, rd_data, rd_len);
- } else {
- if (initrd_high)
- *initrd_start = (ulong)lmb_alloc_base(lmb,
- rd_len, 0x1000, initrd_high);
- else
- *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
- 0x1000);
-
- if (*initrd_start == 0) {
- puts("ramdisk - allocation error\n");
- goto error;
- }
- bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
-
- *initrd_end = *initrd_start + rd_len;
- printf(" Loading Ramdisk to %08lx, end %08lx ... ",
- *initrd_start, *initrd_end);
-
- memmove_wd((void *)*initrd_start,
- (void *)rd_data, rd_len, CHUNKSZ);
-
-#ifdef CONFIG_MP
- /*
- * Ensure the image is flushed to memory to handle
- * AMP boot scenarios in which we might not be
- * HW cache coherent
- */
- flush_cache((unsigned long)*initrd_start,
- ALIGN(rd_len, ARCH_DMA_MINALIGN));
-#endif
- puts("OK\n");
- }
- } else {
- *initrd_start = 0;
- *initrd_end = 0;
- }
- debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
- *initrd_start, *initrd_end);
-
- return 0;
-
-error:
- return -1;
-}
-#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
-
-int boot_get_setup(bootm_headers_t *images, uint8_t arch,
- ulong *setup_start, ulong *setup_len)
-{
-#if IMAGE_ENABLE_FIT
- return boot_get_setup_fit(images, arch, setup_start, setup_len);
-#else
- return -ENOENT;
-#endif
-}
-
-#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA)
-int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len)
-{
- ulong tmp_img_addr, img_data, img_len;
- void *buf;
- int conf_noffset;
- int fit_img_result;
- const char *uname, *name;
- int err;
- int devnum = 0; /* TODO support multi fpga platforms */
-
- /* Check to see if the images struct has a FIT configuration */
- if (!genimg_has_config(images)) {
- debug("## FIT configuration was not specified\n");
- return 0;
- }
-
- /*
- * Obtain the os FIT header from the images struct
- */
- tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
- buf = map_sysmem(tmp_img_addr, 0);
- /*
- * Check image type. For FIT images get FIT node
- * and attempt to locate a generic binary.
- */
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_FIT:
- conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
-
- uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
- NULL);
- if (!uname) {
- debug("## FPGA image is not specified\n");
- return 0;
- }
- fit_img_result = fit_image_load(images,
- tmp_img_addr,
- (const char **)&uname,
- &(images->fit_uname_cfg),
- arch,
- IH_TYPE_FPGA,
- BOOTSTAGE_ID_FPGA_INIT,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
-
- debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
- uname, img_data, img_len);
-
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- if (!fpga_is_partial_data(devnum, img_len)) {
- name = "full";
- err = fpga_loadbitstream(devnum, (char *)img_data,
- img_len, BIT_FULL);
- if (err)
- err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_FULL);
- } else {
- name = "partial";
- err = fpga_loadbitstream(devnum, (char *)img_data,
- img_len, BIT_PARTIAL);
- if (err)
- err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_PARTIAL);
- }
-
- if (err)
- return err;
-
- printf(" Programming %s bitstream... OK\n", name);
- break;
- default:
- printf("The given image format is not supported (corrupt?)\n");
- return 1;
- }
-
- return 0;
-}
-#endif
-
-static void fit_loadable_process(uint8_t img_type,
- ulong img_data,
- ulong img_len)
-{
- int i;
- const unsigned int count =
- ll_entry_count(struct fit_loadable_tbl, fit_loadable);
- struct fit_loadable_tbl *fit_loadable_handler =
- ll_entry_start(struct fit_loadable_tbl, fit_loadable);
- /* For each loadable handler */
- for (i = 0; i < count; i++, fit_loadable_handler++)
- /* matching this type */
- if (fit_loadable_handler->type == img_type)
- /* call that handler with this image data */
- fit_loadable_handler->handler(img_data, img_len);
-}
-
-int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len)
-{
- /*
- * These variables are used to hold the current image location
- * in system memory.
- */
- ulong tmp_img_addr;
- /*
- * These two variables are requirements for fit_image_load, but
- * their values are not used
- */
- ulong img_data, img_len;
- void *buf;
- int loadables_index;
- int conf_noffset;
- int fit_img_result;
- const char *uname;
- uint8_t img_type;
-
- /* Check to see if the images struct has a FIT configuration */
- if (!genimg_has_config(images)) {
- debug("## FIT configuration was not specified\n");
- return 0;
- }
-
- /*
- * Obtain the os FIT header from the images struct
- */
- tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
- buf = map_sysmem(tmp_img_addr, 0);
- /*
- * Check image type. For FIT images get FIT node
- * and attempt to locate a generic binary.
- */
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_FIT:
- conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
-
- for (loadables_index = 0;
- uname = fdt_stringlist_get(buf, conf_noffset,
- FIT_LOADABLE_PROP, loadables_index,
- NULL), uname;
- loadables_index++)
- {
- fit_img_result = fit_image_load(images,
- tmp_img_addr,
- &uname,
- &(images->fit_uname_cfg), arch,
- IH_TYPE_LOADABLE,
- BOOTSTAGE_ID_FIT_LOADABLE_START,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- fit_img_result = fit_image_get_node(buf, uname);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
- fit_img_result = fit_image_get_type(buf,
- fit_img_result,
- &img_type);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- fit_loadable_process(img_type, img_data, img_len);
- }
- break;
- default:
- printf("The given image format is not supported (corrupt?)\n");
- return 1;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-/**
- * boot_get_cmdline - allocate and initialize kernel cmdline
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @cmd_start: pointer to a ulong variable, will hold cmdline start
- * @cmd_end: pointer to a ulong variable, will hold cmdline end
- *
- * boot_get_cmdline() allocates space for kernel command line below
- * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment
- * variable is present its contents is copied to allocated kernel
- * command line.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
-{
- char *cmdline;
- char *s;
-
- cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
- env_get_bootm_mapsize() + env_get_bootm_low());
-
- if (cmdline == NULL)
- return -1;
-
- s = env_get("bootargs");
- if (!s)
- s = "";
-
- strcpy(cmdline, s);
-
- *cmd_start = (ulong) & cmdline[0];
- *cmd_end = *cmd_start + strlen(cmdline);
-
- debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
-
- return 0;
-}
-#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
-
-#ifdef CONFIG_SYS_BOOT_GET_KBD
-/**
- * boot_get_kbd - allocate and initialize kernel copy of board info
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @kbd: double pointer to board info data
- *
- * boot_get_kbd() allocates space for kernel copy of board info data below
- * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized
- * with the current u-boot board info data.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
-{
- *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
- sizeof(struct bd_info),
- 0xf,
- env_get_bootm_mapsize() + env_get_bootm_low());
- if (*kbd == NULL)
- return -1;
-
- **kbd = *(gd->bd);
-
- debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
-
-#if defined(DEBUG) && defined(CONFIG_CMD_BDI)
- do_bdinfo(NULL, 0, 0, NULL);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_SYS_BOOT_GET_KBD */
-
-#ifdef CONFIG_LMB
-int image_setup_linux(bootm_headers_t *images)
-{
- ulong of_size = images->ft_len;
- char **of_flat_tree = &images->ft_addr;
- struct lmb *lmb = &images->lmb;
- int ret;
-
- if (IMAGE_ENABLE_OF_LIBFDT)
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-
- if (IMAGE_BOOT_GET_CMDLINE) {
- ret = boot_get_cmdline(lmb, &images->cmdline_start,
- &images->cmdline_end);
- if (ret) {
- puts("ERROR with allocation of cmdline\n");
- return ret;
- }
- }
-
- if (IMAGE_ENABLE_OF_LIBFDT) {
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
- if (ret)
- return ret;
- }
-
- if (IMAGE_ENABLE_OF_LIBFDT && of_size) {
- ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif /* CONFIG_LMB */
-#endif /* !USE_HOSTCC */
"print string on lcd-framebuffer",
" <string>"
);
-
#include <env.h>
#include <init.h>
#include <net.h>
-#include <version.h>
+#include <version_string.h>
#include <efi_loader.h>
static void run_preboot_environment_command(void)
config SPL_RAW_IMAGE_SUPPORT
bool "Support SPL loading and booting of RAW images"
- default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
+ default n if (ARCH_MX6 && (SPL_MMC || SPL_SATA))
default y if !TI_SECURE_DEVICE
help
SPL will support loading and booting a RAW image when this option
config SPL_CRC32
bool "Support CRC32"
- default y if SPL_LEGACY_IMAGE_SUPPORT
+ default y if SPL_LEGACY_IMAGE_SUPPORT || SPL_EFI_PARTITION
+ default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
help
Enable this to support CRC32 in uImages or FIT images within SPL.
This is a 32-bit checksum value that can be used to verify images.
ensure this information is available to the next image
invoked).
-config SPL_CACHE_SUPPORT
+config SPL_CACHE
bool "Support CACHE drivers"
help
Enable CACHE drivers in SPL. These drivers can keep data so that
config SPL_ETH
bool "Support Ethernet"
depends on SPL_ENV_SUPPORT
+ depends on SPL_NET
help
Enable access to the network subsystem and associated Ethernet
drivers in SPL. This permits SPL to load U-Boot over an Ethernet
link rather than from an on-board peripheral. Environment support
is required since the network stack uses a number of environment
- variables. See also SPL_NET_SUPPORT.
+ variables. See also SPL_NET.
config SPL_FS_EXT4
bool "Support EXT filesystems"
this option to build the drivers in drivers/mailbox as part of
SPL build.
-config SPL_MMC_SUPPORT
+config SPL_MMC
bool "Support MMC"
depends on MMC
select HAVE_BLOCK_DEVICE
config SPL_MMC_TINY
bool "Tiny MMC framework in SPL"
- depends on SPL_MMC_SUPPORT
- default n
+ depends on SPL_MMC
help
Enable MMC framework tinification support. This option is useful if
if your SPL is extremely size constrained. Heed the warning, enable
config SPL_MMC_WRITE
bool "MMC/SD/SDIO card support for write operations in SPL"
- depends on SPL_MMC_SUPPORT
- default n
+ depends on SPL_MMC
help
Enable write access to MMC and SD Cards in SPL
-config SPL_MPC8XXX_INIT_DDR_SUPPORT
+config SPL_MPC8XXX_INIT_DDR
bool "Support MPC8XXX DDR init"
help
Enable support for DDR-SDRAM (double-data-rate synchronous dynamic
README.ubispl for more info.
if SPL_DM
-config SPL_CACHE
- depends on CACHE
- bool "Support cache drivers in SPL"
- help
- Enable support for cache drivers in SPL.
-
config SPL_DM_SPI
bool "Support SPI DM drivers in SPL"
help
config UBI_SPL_SILENCE_MSG
bool "silence UBI SPL messages"
- default n
help
Disable messages from UBI SPL. This leaves warnings
and errors enabled.
endif # if SPL_UBI
-config SPL_NET_SUPPORT
+config SPL_NET
bool "Support networking"
help
Enable support for network devices (such as Ethernet) in SPL.
the network stack uses a number of environment variables. See also
SPL_ETH.
-if SPL_NET_SUPPORT
+if SPL_NET
config SPL_NET_VCI_STRING
string "BOOTP Vendor Class Identifier string sent by SPL"
help
of a client. This is often used in practice to allow for the DHCP
server to specify different files to load depending on if the ROM,
SPL or U-Boot itself makes the request
-endif # if SPL_NET_SUPPORT
+endif # if SPL_NET
config SPL_NO_CPU_SUPPORT
bool "Drop CPU code in SPL"
config SPL_OS_BOOT
bool "Activate Falcon Mode"
depends on !TI_SECURE_DEVICE
- default n
help
Enable booting directly to an OS from SPL.
for more info read doc/README.falcon
necessary driver support. This enables the drivers in drivers/pci
as part of an SPL build.
-config SPL_PCH_SUPPORT
+config SPL_PCH
bool "Support PCH drivers"
help
Enable support for PCH (Platform Controller Hub) devices in SPL.
config SPL_POWER_DOMAIN
bool "Support power domain drivers"
+ select SPL_POWER
help
Enable support for power domain control in SPL. Many SoCs allow
power to be applied to or removed from portions of the SoC (power
Enable support for REMOTEPROCs in SPL. This permits to load
a remote processor firmware in SPL.
-config SPL_RTC_SUPPORT
+config SPL_RTC
bool "Support RTC drivers"
help
Enable RTC (Real-time Clock) support in SPL. This includes support
needed. This enables the drivers in drivers/rtc as part of an SPL
build.
-config SPL_SATA_SUPPORT
+config SPL_SATA
bool "Support loading from SATA"
help
Enable support for SATA (Serial AT attachment) in SPL. This allows
config SPL_SATA_RAW_U_BOOT_USE_SECTOR
bool "SATA raw mode: by sector"
- depends on SPL_SATA_SUPPORT
+ depends on SPL_SATA
default y if ARCH_MVEBU
help
Use sector number for specifying U-Boot location on SATA disk in
Sector on the SATA disk to load U-Boot from, when the SATA disk is being
used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes).
-config SPL_SERIAL_SUPPORT
+config SPL_SERIAL
bool "Support serial"
select SPL_PRINTF
select SPL_STRTO
unless there are space reasons not to. Even then, consider
enabling SPL_USE_TINY_PRINTF which is a small printf() version.
-config SPL_SPI_SUPPORT
+config SPL_SPI
bool "Support SPI drivers"
help
Enable support for using SPI in SPL. This is used for connecting
config SPL_SPI_FLASH_SUPPORT
bool "Support SPI flash drivers"
- depends on SPL_SPI_SUPPORT
+ depends on SPL_SPI
help
Enable support for using SPI flash in SPL, and loading U-Boot from
SPI flash. SPI flash (Serial Peripheral Bus flash) is named after
the SPI bus that is used to connect it to a system. It is a simple
but fast bidirectional 4-wire bus (clock, chip select and two data
lines). This enables the drivers in drivers/mtd/spi as part of an
- SPL build. This normally requires SPL_SPI_SUPPORT.
+ SPL build. This normally requires SPL_SPI.
if SPL_SPI_FLASH_SUPPORT
config SPL_USB_ETHER
bool "Support USB Ethernet drivers"
+ depends on SPL_NET
help
Enable access to the USB network subsystem and associated
drivers in SPL. This permits SPL to load U-Boot over a
USB-connected Ethernet link (such as a USB Ethernet dongle) rather
than from an onboard peripheral. Environment support is required
since the network stack uses a number of environment variables.
- See also SPL_NET_SUPPORT and SPL_ETH.
+ See also SPL_NET and SPL_ETH.
config SPL_DFU
bool "Support DFU (Device Firmware Upgrade)"
config SPL_USB_SDP_SUPPORT
bool "Support SDP (Serial Download Protocol)"
- depends on SPL_SERIAL_SUPPORT
+ depends on SPL_SERIAL
help
Enable Serial Download Protocol (SDP) device support in SPL. This
allows to download images into memory and execute (jump to) them
config SPL_YMODEM_SUPPORT
bool "Support loading using Ymodem"
- depends on SPL_SERIAL_SUPPORT
+ depends on SPL_SERIAL
help
While loading from serial is slow it can be a useful backup when
there is no other option. The Ymodem protocol provides a reliable
Enable access to the AM33xx RTC and select the external 32kHz clock
source.
-config SPL_OPTEE
- bool "Support OP-TEE Trusted OS"
+config SPL_OPTEE_IMAGE
+ bool "Support OP-TEE Trusted OS image in SPL"
depends on ARM
help
- OP-TEE is an open source Trusted OS which is loaded by SPL.
+ OP-TEE is an open source Trusted OS which is loaded by SPL.
More detail at: https://github.com/OP-TEE/optee_os
config SPL_OPENSBI
config TPL_NEEDS_SEPARATE_TEXT_BASE
bool "TPL needs a separate text-base"
- default n
depends on TPL
help
Enable, if the TPL stage should not inherit its text-base
config TPL_NEEDS_SEPARATE_STACK
bool "TPL needs a separate initial stack-pointer"
- default n
depends on TPL
help
Enable, if the TPL stage should not inherit its initial
stack-pointer from the settings for the SPL stage.
+config TPL_POWER
+ bool "Support power drivers"
+ help
+ Enable support for power control in TPL. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in TPL to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of an TPL build.
+
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
depends on TPL_NEEDS_SEPARATE_TEXT_BASE
BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
boot device list, if not implemented for a given board)
+config TPL_CRC32
+ bool "Support CRC32 in TPL"
+ default y if TPL_ENV_SUPPORT || TPL_BLOBLIST
+ help
+ Enable this to support CRC32 in uImages or FIT images within SPL.
+ This is a 32-bit checksum value that can be used to verify images.
+ For FIT images, this is the least secure type of checksum, suitable
+ for detected accidental image corruption. For secure applications you
+ should consider SHA1 or SHA256.
+
config TPL_DRIVERS_MISC
bool "Support misc drivers in TPL"
help
Enable support for generic U-Boot libraries within TPL. See
SPL_LIBGENERIC_SUPPORT for details.
-config TPL_MPC8XXX_INIT_DDR_SUPPORT
+config TPL_MPC8XXX_INIT_DDR
bool "Support MPC8XXX DDR init"
help
Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
- SPL_MPC8XXX_INIT_DDR_SUPPORT for details.
+ SPL_MPC8XXX_INIT_DDR for details.
-config TPL_MMC_SUPPORT
+config TPL_MMC
bool "Support MMC"
depends on MMC
help
- Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details.
+ Enable support for MMC within TPL. See SPL_MMC for details.
config TPL_NAND_SUPPORT
bool "Support NAND flash"
necessary driver support. This enables the drivers in drivers/pci
as part of a TPL build.
-config TPL_PCH_SUPPORT
+config TPL_PCH
bool "Support PCH drivers"
help
Enable support for PCH (Platform Controller Hub) devices in TPL.
be already in memory when TPL takes over, e.g. loaded by the boot
ROM.
-config TPL_RTC_SUPPORT
+config TPL_RTC
bool "Support RTC drivers"
help
Enable RTC (Real-time Clock) support in TPL. This includes support
needed. This enables the drivers in drivers/rtc as part of an TPL
build.
-config TPL_SERIAL_SUPPORT
+config TPL_SERIAL
bool "Support serial"
select TPL_PRINTF
select TPL_STRTO
help
- Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for
+ Enable support for serial in TPL. See SPL_SERIAL for
details.
config TPL_SPI_FLASH_SUPPORT
Enable support for loading next stage, U-Boot or otherwise, from
SPI NOR in U-Boot TPL.
-config TPL_SPI_SUPPORT
+config TPL_SPI
bool "Support SPI drivers"
help
- Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for
+ Enable support for using SPI in TPL. See SPL_SPI for
details.
config TPL_DM_SPI
config TPL_YMODEM_SUPPORT
bool "Support loading using Ymodem"
- depends on TPL_SERIAL_SUPPORT
+ depends on TPL_SERIAL
help
While loading from serial is slow it can be a useful backup when
there is no other option. The Ymodem protocol provides a reliable
config SPL_AT91_MCK_BYPASS
bool "Use external clock signal as a source of main clock for AT91 platforms"
depends on ARCH_AT91
- default n
help
Use external 8 to 24 Mhz clock signal as source of main clock instead
of an external crystal oscillator.
obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o
endif
obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o
-obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
-obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_$(SPL_TPL_)NET) += spl_net.o
+obj-$(CONFIG_$(SPL_TPL_)MMC) += spl_mmc.o
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
-obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPTEE_IMAGE) += spl_optee.o
obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
-obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
+obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o
obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o
obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
#include <nand.h>
#include <fat.h>
#include <u-boot/crc.h>
+#if CONFIG_IS_ENABLED(BANNER_PRINT)
+#include <timestamp.h>
+#endif
#include <version.h>
#include <image.h>
#include <malloc.h>
return ret;
}
#endif
- if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
ret = fdtdec_setup();
if (ret) {
debug("fdtdec_setup() returned error %d\n", ret);
if (CONFIG_IS_ENABLED(SHOW_ERRORS))
ret = -ENXIO;
loader = spl_ll_find_loader(bootdev);
- if (CONFIG_IS_ENABLED(SERIAL_SUPPORT) &&
+ if (CONFIG_IS_ENABLED(SERIAL) &&
CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) &&
!IS_ENABLED(CONFIG_SILENT_CONSOLE)) {
if (loader)
spl_invoke_atf(&spl_image);
break;
#endif
-#if CONFIG_IS_ENABLED(OPTEE)
+#if CONFIG_IS_ENABLED(OPTEE_IMAGE)
case IH_OS_TEE:
debug("Jumping to U-Boot via OP-TEE\n");
spl_board_prepare_for_optee(spl_image.fdt_addr);
*/
void preloader_console_init(void)
{
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_SPL_SERIAL
gd->baudrate = CONFIG_BAUDRATE;
serial_init(); /* serial communications setup */
err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
if (err)
continue;
- if (info.sys_ind ==
+ if (info.sys_ind ==
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) {
partition = type_part;
break;
#if CONFIG_IS_ENABLED(DFU)
SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
#endif
-
-
#include <errno.h>
#include <spl.h>
#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <dm/ofnode.h>
#ifdef CONFIG_SPL_OS_BOOT
/*
header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
- payload_offs = fdtdec_get_config_int(gd->fdt_blob,
- "u-boot,spl-payload-offset",
- payload_offs);
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset",
+ payload_offs);
+ }
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header))
dev->name);
}
}
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
i2c_init_all();
#endif
if (IS_ENABLED(CONFIG_DM_VIDEO)) {
int action; /* what to do */
int ip_wanted; /* needed */
int *irq_handle; /* for USB int requests */
- unsigned int irqpipe; /* pipe for release_irq */
+ unsigned int irqpipe; /* pipe for release_irq */
unsigned char irqmaxp; /* max packed for irq Pipe */
unsigned char irqinterval; /* Intervall for IRQ Pipe */
struct scsi_cmd *srb; /* current srb */
/* Values magic to the protocol */
#define SOH 0x01
#define STX 0x02
+#define ETX 0x03 /* ^C for interrupt */
#define EOT 0x04
#define ACK 0x06
#define BSP 0x08
hdr_found = true;
break;
case CAN:
+ case ETX:
xyz.total_CAN++;
ZM_DEBUG (zm_dump (__LINE__));
if (++can_total == xyzModem_CAN_COUNT)
total = 0;
stat = xyzModem_cancel;
/* Try and get 'size' bytes into the buffer */
- while (!xyz.at_eof && (size > 0))
+ while (!xyz.at_eof && xyz.len >= 0 && (size > 0))
{
if (xyz.len == 0)
{
CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
ZM_DEBUG (zm_dprintf ("FINAL ACK (%d)\n", __LINE__));
}
+ else
+ stat = 0;
xyz.at_eof = true;
break;
}
}
}
/* Don't "read" data from the EOF protocol package */
- if (!xyz.at_eof)
+ if (!xyz.at_eof && xyz.len > 0)
{
len = xyz.len;
if (size < len)
void
xyzModem_stream_close (int *err)
{
- diag_printf
+ ZM_DEBUG (zm_dprintf
("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n",
xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX,
- xyz.total_CAN, xyz.total_retries);
+ xyz.total_CAN, xyz.total_retries));
ZM_DEBUG (zm_flush ());
}
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
+CONFIG_SYS_LOAD_ADDR=0xcc000000
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
+CONFIG_SYS_LOAD_ADDR=0xd4000000
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_AXP152_POWER=y
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_SUNXI_NO_PMIC=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_REALTEK=y
CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0"
-CONFIG_MMC3_PINS="PH"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_ADDR=3
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_ADDR=3
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP152_POWER=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP152_POWER=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_RGMII=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_ENV_IS_IN_UBI=y
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot-env"
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0x100
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_VIDEO_LCD_POWER="PH27"
CONFIG_VIDEO_LCD_BL_EN="PM1"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
-CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23"
-CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_USB0_ID_DET="PH16"
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
+CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP_GPIO=y
CONFIG_AXP809_POWER=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_SCSI=y
CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_B53_SWITCH=y
CONFIG_B53_PHY_PORTS=0x1f
CONFIG_PHY_REALTEK=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
CONFIG_TARGET_M5208EVBE=y
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x2000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x58000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
CONFIG_TARGET_M5235EVB=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x300
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
CONFIG_TARGET_M5235EVB=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x300
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
CONFIG_TARGET_M5249EVB=y
+CONFIG_SYS_LOAD_ADDR=0x200000
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_DEVICE_NULLDEV=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
CONFIG_TARGET_M5253DEMO=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_MAC_PARTITION=y
CONFIG_ENV_ADDR=0xFF804000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x280
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
CONFIG_TARGET_M5272C3=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
CONFIG_TARGET_M5275EVB=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x300
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
CONFIG_TARGET_M5282EVB=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x8000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
CONFIG_TARGET_M53017EVB=y
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2"
CONFIG_CMD_DATE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x40000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x58000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
CONFIG_TARGET_M5329EVB=y
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DATE=y
CONFIG_ENV_ADDR=0x4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x58000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
CONFIG_TARGET_M5329EVB=y
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DATE=y
CONFIG_ENV_ADDR=0x4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x58000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
CONFIG_TARGET_M5373EVB=y
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DATE=y
CONFIG_ENV_ADDR=0x4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x58000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x1C000001
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
+CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_DRAM_CLK=384
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349EMDS=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_64BIT_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2400000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSEC1EP_3=y
-CONFIG_SPCR_TSEC2EP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_ENV_ADDR_REDUND=0xFE0A0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349EMDS_SDRAM=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2400000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="SDRAM"
-CONFIG_LBLAW2_LENGTH_64_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="SDRAM"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_BR2_PORTSIZE_32BIT=y
-CONFIG_BR2_MACHINE_SDRAM=y
-CONFIG_OR2_COLS_9=y
-CONFIG_OR2_ROWS_13=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_ONE_PCI1=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_ENV_ADDR_REDUND=0xFE0A0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66666666
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349EMDS=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_64BIT_MODE_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2400000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSEC1EP_3=y
-CONFIG_SPCR_TSEC2EP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_ONE_PCI1=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
-CONFIG_BOOTDELAY=6
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_ENV_ADDR_REDUND=0xFE0A0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349EMDS=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2400000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xE2400000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSEC1EP_3=y
-CONFIG_SPCR_TSEC2EP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_ONE_PCI1=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_ENV_ADDR_REDUND=0xFE0A0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_DM=y
CONFIG_FSL_SATA=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_DHCP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_DHCP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_MII=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_SUNXI_NO_PMIC=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_SCSI=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_USB0_ID_DET="PH3"
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
+CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP_GPIO=y
CONFIG_AXP809_POWER=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL_DRIVERS_MISC=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_TPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw"
CONFIG_IDENT_STRING="\nSBx81LIFKW"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat"
CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_MMC0_CD_PIN="PA4"
-CONFIG_MMC3_PINS="PC"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_OFFSET=0x180000
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_T2080RDB_REV_D=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_CONS_INDEX=2
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC1_CD_PIN="PH2"
-CONFIG_MMC1_PINS="PH"
+CONFIG_MMC1_PINS_PH=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_NDS32=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x4A000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x140000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
CONFIG_TARGET_ADP_AE3XX=y
+CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
# CONFIG_AUTO_COMPLETE is not set
CONFIG_NDS32=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
CONFIG_TARGET_ADP_AG101P=y
+CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_TEXT_BASE=0x01200000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_BOOTDELAY=3
CONFIG_SYS_TEXT_BASE=0x01200000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_BOOTDELAY=3
CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_TEXT_BASE=0x01200000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_BOOTDELAY=3
CONFIG_SYS_TEXT_BASE=0x01200000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_BOOTDELAY=3
CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Alt"
CONFIG_R8A7794=y
CONFIG_TARGET_ALT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_BALTOS=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_OMAP24_I2C_SPEED=1000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SPEED=1000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP_HS_ADMA=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x00080000
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_SMSC=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MUSB_NEW=y
# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00080000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_AM33XX=y
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_SPL=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_SPL_DM_MMC is not set
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
# CONFIG_SPL_NAND_AM33XX_BCH is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_GUARDIAN=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL"
CONFIG_SPL_POWER=y
CONFIG_SPL_USB_GADGET=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_CLK_TI_DIVIDER=y
CONFIG_CLK_TI_GATE=y
CONFIG_CLK_TI_MUX=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0x100
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x200000
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
# CONFIG_SPL_YMODEM_SUPPORT is not set
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_AM33XX=y
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_SPL=y
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_IGEP003X=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_FS_EXT4=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
CONFIG_AM33XX=y
CONFIG_TARGET_PDU001=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x9000
CONFIG_SPL_FS_FAT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SLAVE=0x1
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x9000
CONFIG_SPL_FS_FAT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SLAVE=0x1
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x9000
CONFIG_SPL_FS_FAT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SLAVE=0x1
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x9000
CONFIG_SPL_FS_FAT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SLAVE=0x1
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_SL50=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x20000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=57
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_HOST=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_GIGE=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_AM43XX=y
CONFIG_ENV_OFFSET_REDUND=0x120000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI,QSPI_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_SPL_POWER_I2C=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_GIGE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_GIGE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_GIGE=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
CONFIG_CMD_SPL=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_AM642_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_TARGET_AM642_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
CONFIG_SPL_TEXT_BASE=0x70000000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x190000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6A0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x7ec00
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6A0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="amcore"
CONFIG_TARGET_AMCORE=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="ap121"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_ARCH_ATH79=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="ap143"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP143=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="ap152"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xb8020000
CONFIG_ARCH_ATH79=y
CONFIG_TARGET_AP152=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8-imximage.cfg"
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis"
CONFIG_TARGET_APALIS_IMX8X=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x89000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg"
CONFIG_BOOTDELAY=1
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_TARGET_APALIS_TK1=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6Q=y
CONFIG_TARGET_APALIS_IMX6=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_MXC_I2C3_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA30=y
CONFIG_TARGET_APALIS_T30=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_CMD_DEKBLOB is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
CONFIG_BOOTDELAY=-2
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_ENCRYPTION=y
# CONFIG_CMD_DEKBLOB is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
CONFIG_BOOTDELAY=-2
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board"
CONFIG_R8A7740=y
CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_SYS_LOAD_ADDR=0x44000000
CONFIG_BOOTDELAY=3
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x86200
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ARNDALE"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_USE_PREBOOT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_TARGET_ASPENITE=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x20000
-CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-# CONFIG_MMC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_SECT_SIZE=0x8000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
CONFIG_TARGET_ASTRO_MCF5373L=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion"
CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x58000
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x2000
+CONFIG_SYS_MALLOC_LEN=0x23000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x2c000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x2c000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0x5000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0"
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ZYNQ_MAC_IN_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_DEBUG_UART_CLOCK=18432000
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068"
+CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flash_self"
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_ARC=y
CONFIG_TARGET_AXS101=y
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="axs101"
CONFIG_DEBUG_UART_BASE=0xe0022000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="axs103"
CONFIG_DEBUG_UART_BASE=0xe0022000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-m5"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_RGMII=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCMSTB=y
CONFIG_SYS_TEXT_BASE=0x10100000
CONFIG_TARGET_BCM7260=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x814800
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_ENV_OFFSET_REDUND=0x824800
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTDELAY=1
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCMSTB=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_BCM7445=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x1E0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_ENV_OFFSET_REDUND=0x1F0000
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTDELAY=1
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_BCM63158=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
CONFIG_TARGET_BCM963158=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_RSASSA_PSS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_63158=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCM68360=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg"
CONFIG_TARGET_BCM968360BG=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_68360=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6838=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6838=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY=y
CONFIG_BCM6368_USBH_PHY=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCM6858=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref"
CONFIG_TARGET_BCM968580XREF=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6858=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x80000
+CONFIG_SYS_MALLOC_LEN=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="ns3-board"
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_SIGNATURE_MAX_SIZE=0x20000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA30=y
CONFIG_TARGET_BEAVER=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="beelink-s922x"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX28=y
-CONFIG_SYS_TEXT_BASE=0x40002000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x4000
-CONFIG_SPL_TEXT_BASE=0x00001000
-CONFIG_TARGET_BG0900=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MXS_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
-CONFIG_SPI=y
-CONFIG_OF_LIBFDT=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ZYNQ=y
CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x200000
+CONFIG_SYS_MALLOC_LEN=0x402000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x220000
CONFIG_TARGET_BK4R1=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter passphrase to stop autoboot, booting in %d seconds\n"
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_SYS_EEPROM_SIZE=32768
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot"
CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche"
CONFIG_R8A7792=y
CONFIG_TARGET_BLANCHE=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS32_R6=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R2=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_CPU_MIPS64_R6=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="img,boston"
CONFIG_TARGET_BOSTON=y
CONFIG_SYS_LITTLE_ENDIAN=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc"
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x50000
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x60000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-nand"
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_PHY_NATSEMI=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi"
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x30000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPI_BOOT=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6QDL=y
CONFIG_TARGET_BRPPT2=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_CMD_BMODE is not set
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x10700000
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brsmarc1"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
CONFIG_TARGET_BRSMARC1=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x30000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brxre1"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=1000
CONFIG_TARGET_BRXRE1=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x50000
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_ARM=y
CONFIG_ARCH_OWL=y
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
CONFIG_MACH_S900=y
CONFIG_IDENT_STRING="\nBubblegum-96"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x7ffc0
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA30=y
CONFIG_TARGET_CARDHU=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_TARGET_CEI_TK1_SOM=y
CONFIG_ARMV7_PSCI_0_1=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8"
CONFIG_TARGET_CONGA_QMX8=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-chiliboard"
CONFIG_AM33XX=y
CONFIG_TARGET_CHILIBOARD=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x22000
CONFIG_SPL_FS_FAT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MISC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_ROCKCHIP_RK3288=y
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_TARGET_CHROMEBIT_MICKEY=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_DEBUG_UART_BASE=0xff1a0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_CPU=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_PCI=y
+CONFIG_SPL_POWER=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_TPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_PMC=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_ROCKCHIP_RK3288=y
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_PCI=y
-CONFIG_SPL_PCH_SUPPORT=y
-CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_PCH=y
+CONFIG_SPL_RTC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_ROCKCHIP_RK3288=y
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_TARGET_CHROMEBOOK_MINNIE=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_HANDOFF=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_PCI=y
-CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_SPL_PCH=y
CONFIG_TPL_PCI=y
-CONFIG_TPL_PCH_SUPPORT=y
+CONFIG_TPL_PCH=y
CONFIG_TPL_DM_SPI=y
CONFIG_TPL_DM_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_ROCKCHIP_RK3288=y
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x83800
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="ci20"
CONFIG_SPL_TEXT_BASE=0xf4000a00
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_ARCH_JZ47XX=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_TARGET_CL_SOM_IMX7=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_LATE_INIT=y
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_MII=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6QDL=y
CONFIG_TARGET_CM_FX6=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_CMD_BMODE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
# CONFIG_DWC_AHSATA_AHCI is not set
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_MXC_I2C3_SPEED=400000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_AM33XX=y
CONFIG_TARGET_CM_T335=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=64
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHY_ATHEROS=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0x40300350
CONFIG_AM43XX=y
CONFIG_TARGET_CM_T43=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_PHY_ATHEROS=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_OMAP_USB_PHY=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
CONFIG_TARGET_COBRA5272=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_ENV_OFFSET=0x380000
CONFIG_MX6ULL=y
CONFIG_TARGET_COLIBRI_IMX6ULL=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,IMX_NAND"
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_TARGET_COLIBRI_IMX8X=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg"
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y
CONFIG_TARGET_COLIBRI_IMX6=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_MXC_I2C3_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SYS_MEMTEST_END=0x8c000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x380000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
-CONFIG_FSL_CAAM=y
CONFIG_DFU_NAND=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_SYS_MEMTEST_END=0x8c000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc"
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_IMX_HAB=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
-CONFIG_FSL_CAAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0xa0000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200"
CONFIG_SYS_DEVICE_NULLDEV=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_COLIBRI_T20=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA30=y
CONFIG_TARGET_COLIBRI_T30=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x180000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,IMX_NAND"
+CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6318=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6328=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6348=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM63268=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6368=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_ETH=y
CONFIG_BCM6368_ETH=y
CONFIG_PHY=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6368=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0x04000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_TEXT_BASE=0x04000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_TEXT_BASE=0x04000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x820000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_CORTINA_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SERIAL=y
CONFIG_CORTINA_UART=y
CONFIG_WDT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x180000
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
+CONFIG_SYS_LOAD_ADDR=0x70000000
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_PHYLIB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s-bit"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s-bit"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s-bit"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_ARM=y
CONFIG_ARCH_OWL=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"
CONFIG_MACH_S700=y
CONFIG_IDENT_STRING="\ncubieboard7"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x7ffc0
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyOWL3,115200n8"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net"
CONFIG_IDENT_STRING=" D2 v2"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="d2v2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2800
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
CONFIG_DM_SPI_FLASH=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA114=y
CONFIG_TARGET_DALMORE=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
CONFIG_SPL_TEXT_BASE=0x40004030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_MVEBU=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
CONFIG_SPL_TEXT_BASE=0x40004030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_MARVELL=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_TARGET_DENEB=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xA0000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_TEXT_BASE=0x00000000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_DMA_LPC32XX=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_LPC32XX_SLC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=31
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_DEVKIT8000=y
CONFIG_SPL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_CONS_INDEX=3
CONFIG_OF_LIBFDT=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x130000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=32768
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_SYS_EEPROM_SIZE=32768
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x130000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="echo SDP Display5 recovery"
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=32768
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_SYS_EEPROM_SIZE=32768
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
CONFIG_IDENT_STRING="\nD-Link DNS-325"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar"
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_CMD_SPL=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_BOOTP_DNS2=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_DRACO=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x802000
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x804000
CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
CONFIG_TARGET_DRAGONBOARD820C=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyMSM0,115200n8"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_STATIC_MACH_TYPE=y
+CONFIG_MACH_TYPE=527
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DS109=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_STATIC_MACH_TYPE=y
+CONFIG_MACH_TYPE=3036
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DS414=y
+CONFIG_DDR_32BIT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x7E0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
CONFIG_SPL_TEXT_BASE=0x40004030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1"
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_SYS_TEXT_BASE=0x500000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
# CONFIG_PSCI_RESET is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_EA_LPC3250DEVKITV2=y
CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80100000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282"
CONFIG_TARGET_EB_CPU5282=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_MII=y
CONFIG_CMD_DATE=y
CONFIG_ENV_ADDR=0xFF040000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x300
+CONFIG_SYS_I2C_SLAVE=0
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=8
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
CONFIG_TARGET_EB_CPU5282=y
+CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_MII=y
CONFIG_CMD_DATE=y
CONFIG_ENV_ADDR=0xFF040000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x300
+CONFIG_SYS_I2C_SLAVE=0
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=8
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="edison"
CONFIG_ENV_OFFSET_REDUND=0x600000
CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_EDISON=y
CONFIG_SMP=y
CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SPL_TEXT_BASE=0xffff0000
CONFIG_TARGET_EDMINIV2=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_IDENT_STRING=" EDMiniV2"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFF84000
CONFIG_NETCONSOLE=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_TARGET_EMSDP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x10000
CONFIG_DEFAULT_DEVICE_TREE="emsdp"
CONFIG_SYS_CLK_FREQ=40000000
+CONFIG_SYS_LOAD_ADDR=0x10000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
CONFIG_IDENT_STRING=" for ESPRESSO7420"
+CONFIG_SYS_LOAD_ADDR=0x43e00000
# CONFIG_AUTOBOOT is not set
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_ETAMIN=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xB80000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x80
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x27000000
CONFIG_ENV_SIZE=0x21000
CONFIG_ENV_OFFSET=0x3DE000
CONFIG_ENV_SECT_SIZE=0x21000
+CONFIG_SYS_MALLOC_LEN=0x121000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ethernut5"
+CONFIG_SYS_LOAD_ADDR=0x020000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_MX6ULL=y
CONFIG_TARGET_O4_IMX6ULL_NANO=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_EV_IMX280_NANO_X_MB=y
CONFIG_IMX_MODULE_FUSE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
CONFIG_PRE_CON_BUF_ADDR=0x1e720000
+CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x10000
CONFIG_SPL=y
# CONFIG_ARMV7_NONSEC is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_FIT=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1c0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x60800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x60800800
CONFIG_FIT=y
CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x61000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x61800800
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SPL_OPTEE=y
+CONFIG_SPL_OPTEE_IMAGE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
-CONFIG_SPL_OPTEE=y
+CONFIG_SPL_OPTEE_IMAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_TARGET_FLEA3=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="flea3 U-Boot > "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA0090000
-CONFIG_MXC_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x22900000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x0
CONFIG_ENV_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR="x"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
CONFIG_CMD_WDT=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand"
CONFIG_MTDPARTS_DEFAULT="atmel_nand:1536k(uboot),10752k(unused),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_UBI_VOLUME="uboot_env0"
CONFIG_ENV_UBI_VOLUME_REDUND="uboot_env1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
# CONFIG_UBIFS_SILENCE_MSG is not set
+CONFIG_LZMA=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xA0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xB0000
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_MEMTEST_END=0x07e00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
CONFIG_IDENT_STRING=" gazerbeam 0.01"
# CONFIG_GE_RTC is not set
CONFIG_MX6QDL=y
CONFIG_TARGET_GE_B1X5V2=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x21ec000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ENV_SIZE=0x2000
CONFIG_MX6Q=y
CONFIG_TARGET_GE_BX50V3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3"
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_DEBUG_UART_BASE=0xFF690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_TARGET_GIEDI=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Gose"
CONFIG_R8A7793=y
CONFIG_TARGET_GOSE=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
CONFIG_RZA1=y
+CONFIG_SYS_LOAD_ADDR=0x20400000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="ignore_loglevel"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_GURNARD=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
+CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENV_OFFSET=0xB1400
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xD1400
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_POWER_I2C=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_ENV_OFFSET=0xB1400
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xD1400
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_POWER_I2C=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_ENV_OFFSET=0x1000000
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_CMD_EECONFIG=y
CONFIG_CMD_GSC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1080000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xe00000
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_POWER_I2C=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_HARMONY=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PCI=y
CONFIG_DM_PMIC=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_HIHOPE_RZG2=y
# CONFIG_SPL is not set
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x801000
CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
CONFIG_IDENT_STRING="\nHikey960"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw"
CONFIG_NR_DRAM_BANKS=6
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x801000
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
CONFIG_IDENT_STRING="hikey"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80000
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw"
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_DM_ETH=y
+CONFIG_POWER_LEGACY=y
CONFIG_CONS_INDEX=4
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_TARGET_HSDK=y
CONFIG_BOARD_HSDK_4XD=y
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="hsdk-4xd"
CONFIG_DEBUG_UART_BASE=0xf0005000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ISA_ARCV2=y
CONFIG_TARGET_HSDK=y
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="hsdk"
CONFIG_DEBUG_UART_BASE=0xf0005000
CONFIG_DEBUG_UART_CLOCK=33333333
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6358=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0"
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_SERIAL_TAG=y
+CONFIG_STATIC_MACH_TYPE=y
+CONFIG_MACH_TYPE=4283
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_CMD_UNZIP=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect"
CONFIG_IDENT_STRING=" Iomega iConnect"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_TEXT_BASE=0xFFF00000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_BOOTCOUNT_ADDR=0x9
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_I2C=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_ELBC=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SYS_MTDPARTS_RUNTIME=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SMC911X=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
CONFIG_TARGET_XILFPGA=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
+CONFIG_SYS_LOAD_ADDR=0x80500000
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
+CONFIG_IMX_CONFIG=""
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
CONFIG_SPL_TEXT_BASE=0x1000
CONFIG_TARGET_XEA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6DL_MAMOJ=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_MX6Q=y
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_MX6LOGICPD=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_FEC_MXC=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_DEBUG_UART_CLOCK=24000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_SPL=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-cm"
CONFIG_TARGET_IMX7_CM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4400
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_CL_IOT_GATE=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_DM_KEYBOARD=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_BEACON=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_EVK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0xff0000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_VENICE=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xff8000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_DDR4_EVK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_CLK_IMX8MN=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_CLK_IMX8MN=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_EVK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_CM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_PHANBELL=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_TARGET_IMX8QM_MEK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_LEN=0x2800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8qm-rom7720-a1"
CONFIG_TARGET_IMX8QM_ROM7720_A1=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/advantech/imx8qm_rom7720_a1/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_LEN=0x2400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_TARGET_IMX8QXP_MEK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_IMX_CONFIG=""
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
CONFIG_SPL_TEXT_BASE=0x22020000
CONFIG_TARGET_IMX8ULP_EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80480000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_IMX_RGPIO2P=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
CONFIG_SPL_TEXT_BASE=0x20209000
CONFIG_TARGET_IMXRT1020_EVK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x20209000
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
CONFIG_SPL_TEXT_BASE=0x20209000
CONFIG_TARGET_IMXRT1050_EVK=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x20209000
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2"
CONFIG_IDENT_STRING=" IS v2"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CM720T=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_MALLOC_LEN=0x28000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CM920T=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_MALLOC_LEN=0x28000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CM926EJ_S=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_MALLOC_LEN=0x28000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CM946ES=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
+CONFIG_SYS_MALLOC_LEN=0x28000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x22000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x22000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x22000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x22000
+CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
# CONFIG_DISPLAY_CPUINFO is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM6=y
+CONFIG_TARGET_IOT2050_A53=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ENV_OFFSET_REDUND=0x6a0000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTSTAGE=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SYS_PROMPT="IOT2050> "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_PCI=y
+CONFIG_PCI_KEYSTONE=y
+CONFIG_PHY=y
+CONFIG_AM654_PHY=y
+CONFIG_OMAP_USB2_PHY=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_K3_RTI=y
+CONFIG_WDT_K3_RTI_LOAD_FW=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_IOT_DEVKIT=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x10000
CONFIG_DEFAULT_DEVICE_TREE="iot_devkit"
CONFIG_SYS_CLK_FREQ=16000000
CONFIG_LOCALVERSION="-iotdk-1.0"
+CONFIG_SYS_LOAD_ADDR=0x30000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_PROMPT="IoTDK# "
# CONFIG_CMD_BOOTD is not set
CONFIG_TARGET_J7200_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6A0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J7200_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6A0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x700000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x700000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="jethub"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100"
+CONFIG_MESON_AXG=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" jethubj100"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPIO=y
+CONFIG_RANDOM_UUID=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD_UBI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_AXG=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="jethub-j80"
+CONFIG_SYS_CONFIG_NAME="jethub"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80"
+CONFIG_MESON_GXL=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" jethubj80"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_RANDOM_UUID=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD_UBI=y
+CONFIG_PHY_MESON_GXL=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_TARGET_JETSON_TK1=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2E_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_TI_EDMA3=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2E_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_TI_EDMA3=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2G_EVM=y
CONFIG_ENV_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_TI_EDMA3=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_K2G_EVM=y
CONFIG_ENV_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM=y
CONFIG_DFU_MMC=y
+CONFIG_TI_EDMA3=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2HK_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_TI_EDMA3=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2HK_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_TI_EDMA3=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2L_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_TI_EDMA3=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2L_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_TI_EDMA3=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim2"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x0
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x0
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0x2000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x0
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_PINMUX is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0xD0000
CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x0
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0xD0000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x0
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_ENV_OFFSET_REDUND=0xD0000
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x0
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Koelsch"
CONFIG_R8A7791=y
CONFIG_TARGET_KOELSCH=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x3e0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
CONFIG_SPL_TEXT_BASE=0x18010000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
CONFIG_CMD_ASKENV=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_TARGET_KP_IMX53=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
CONFIG_ENV_OFFSET_REDUND=0x102000
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="."
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_MX6QDL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KP_IMX6Q_TPC=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x102000
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x60800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x60000
CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT"
CONFIG_TARGET_KZM9G=y
+CONFIG_SYS_LOAD_ADDR=0x43000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x40000
CONFIG_VERSION_VARIABLE=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SH=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Lager"
CONFIG_R8A7790=y
CONFIG_TARGET_LAGER=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_TARGET_LEGOEV3=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
+CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
# CONFIG_NET is not set
CONFIG_DM=y
# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-ac"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc-v2"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-s905d-pc"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-s912-pc"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_BOARD_LINKIT_SMART_7688=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6UL=y
CONFIG_TARGET_LITEBOARD=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
CONFIG_QSPI_AHB_INIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_QSPI_AHB_INIT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_QSPI_AHB_INIT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_QSPI_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x140000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x1c000
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1002000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1020000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_SPL=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_SPL=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,EMMC_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_OS_BASE=0x40980000
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_SPL=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x102000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_QSPI_AHB_INIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_MXC_I2C1_SPEED=40000000
+CONFIG_SYS_MXC_I2C2_SPEED=40000000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_MXC_I2C1_SPEED=40000000
+CONFIG_SYS_MXC_I2C2_SPEED=40000000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_SPL_DM=y
CONFIG_SCSI_AHCI=y
# CONFIG_SPL_BLK is not set
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_MXC_I2C1_SPEED=40000000
+CONFIG_SYS_MXC_I2C2_SPEED=40000000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_MXC_I2C1_SPEED=40000000
+CONFIG_SYS_MXC_I2C2_SPEED=40000000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x200000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2"
CONFIG_IDENT_STRING=" LS-CHLv2"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_API=y
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl"
CONFIG_IDENT_STRING=" LS-XHL"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_API=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2160AQDS=y
CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2160AQDS=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2160ARDB=y
CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2160ARDB=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2160ARDB=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2162AQDS=y
CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2162AQDS=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2162AQDS=y
CONFIG_TFABOOT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
+CONFIG_ID_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_TARGET_M53MENLO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo"
CONFIG_SPL_TEXT_BASE=0x70008000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_LOAD_ADDR=0x70800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXC=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_CPU_MIPS64_R2=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R2=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_TEXT_BASE=0xBE000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_TEXT_BASE=0xBE000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
# CONFIG_AUTOBOOT is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg"
CONFIG_MX6Q=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_SPL_TEXT_BASE=0x40004030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_nor.cfg"
CONFIG_MX6QDL=y
CONFIG_TARGET_MCCMON6=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_sd.cfg"
CONFIG_MX6QDL=y
CONFIG_TARGET_MCCMON6=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_MEDCOM_WIDE=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96"
CONFIG_TARGET_MEERKAT96=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/novtech/meerkat96/imximage.cfg"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_ENV_SIZE=0x4200
CONFIG_ENV_OFFSET=0x4200
CONFIG_ENV_SECT_SIZE=0x210
+CONFIG_SYS_MALLOC_LEN=0x2d000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_SYS_LOAD_ADDR=0x20100000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_SYS_LOAD_ADDR=0x20100000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0xc0000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=-1
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SBI_V01=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP152_POWER=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_MACH_SUN4I=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SOC_JR2=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARCH_MSCC=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106"
CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_SOC_SERVAL=y
CONFIG_DDRTYPE_H5TQ1G63BFA=y
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1f0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="servalt_pcb116"
CONFIG_ENV_OFFSET_REDUND=0x140000
CONFIG_ARCH_MSCC=y
CONFIG_SOC_SERVALT=y
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xb0000c00
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_ARCH_MTMIPS=y
CONFIG_BOARD_MT7620_MT7530_RFB=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xb0000c00
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_ARCH_MTMIPS=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x4007ff28
CONFIG_FIT=y
CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
CONFIG_LOGLEVEL=7
CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc"
CONFIG_TARGET_MT7623=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2"
CONFIG_TARGET_MT7623=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_BOARD_MT7628_RFB=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
+CONFIG_SYS_LOAD_ADDR=0x80010000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb"
CONFIG_SPL_TEXT_BASE=0x201000
CONFIG_TARGET_MT7629=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x40800000
CONFIG_SPL_PAYLOAD="u-boot-lzma.img"
CONFIG_BUILD_TARGET="u-boot-mtk.bin"
CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"
+CONFIG_SYS_LOAD_ADDR=0x42007f1c
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_DEBUG_UART_CLOCK=26000000
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x4c000000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DM_ETH=y
CONFIG_PHY=y
CONFIG_PHY_MTK_TPHY=y
+# CONFIG_POWER is not set
CONFIG_BAUDRATE=921600
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc"
CONFIG_TARGET_MT8512=y
+CONFIG_SYS_LOAD_ADDR=0x41000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb"
CONFIG_DEBUG_UART_CLOCK=26000000
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x4c000000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc"
CONFIG_TARGET_MT8518=y
+CONFIG_SYS_LOAD_ADDR=0x41000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc.dtb"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_IMX_CONFIG=""
CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino"
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX23_OLINUXINO=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_IMX_CONFIG=""
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx23-evk"
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX23EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_IMX_CONFIG=""
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_IMX_CONFIG=""
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx28-evk"
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_IMX_CONFIG=""
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x380000
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
+CONFIG_IMX_CONFIG=""
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX51EVK=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x92000000
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_MX53CX9020=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x70010000
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_CMD_MMC=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX53LOCO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb"
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2800
CONFIG_TARGET_MX53PPD=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd"
CONFIG_BOOTCOUNT_BOOTLIMIT=10
+CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ENV_OFFSET=0xFE000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6CUBOXI=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_MX6QDL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_MX6MEMCAL=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL"
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg"
CONFIG_MX6Q=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabrelite"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6SABREAUTO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NXP_BOARD_REVISION=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6SABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SL=y
CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6SL=y
CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SL=y
CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6SLL=y
CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6SLL=y
CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
CONFIG_USE_IMXIMG_PLUGIN=y
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SX=y
CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_OFFSET=0xE0000
CONFIG_MX6SX=y
CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_USE_IMXIMG_PLUGIN=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CMD_BOOTD is not set
CONFIG_DFU_RAM=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CMD_BOOTD is not set
CONFIG_DFU_RAM=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MEMTEST_END=0x9e000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_MEMTEST_END=0x9e000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_ENV_SIZE=0x4000
CONFIG_MX6ULL=y
CONFIG_TARGET_MYS_6ULX=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval"
CONFIG_SPL_TEXT_BASE=0x908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" nanopi-k2"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+# CONFIG_DRAM_ODT_EN is not set
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
CONFIG_IDENT_STRING="\nNAS 220"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big"
CONFIG_IDENT_STRING=" 2Big v2"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="2big2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
CONFIG_ARCH_BMIPS=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6362=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite"
CONFIG_IDENT_STRING=" NS v2 Lite"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max"
CONFIG_IDENT_STRING=" NS Max v2"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini"
CONFIG_IDENT_STRING=" NS v2 Mini"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2"
CONFIG_IDENT_STRING=" NS v2"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl2g.cfg"
CONFIG_MX6DL=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=2048
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl.cfg"
CONFIG_MX6DL=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q2g.cfg"
CONFIG_MX6Q=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=2048
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg"
CONFIG_MX6Q=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg"
CONFIG_MX6S=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=1024
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s.cfg"
CONFIG_MX6S=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_DDR_MB=512
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x"
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,DDR_MB=512"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_REVISION_TAG=y
+CONFIG_STATIC_MACH_TYPE=y
+CONFIG_MACH_TYPE=1955
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MALLOC_LEN=0xc0000
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_OPTIMIZE_INLINING=y
CONFIG_LTO=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_KEYED=y
CONFIG_MX6Q=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KOSAGI_NOVENA=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x84000
CONFIG_SPL_FS_FAT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc1,115200 "
CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s"
CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_NSIM=y
CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=arc700 -mlock -mswape"
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_TARGET_NSIM=y
CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=arc700 -mlock -mswape"
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_TARGET_NSIM=y
CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=archs"
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_TARGET_NSIM=y
CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=archs"
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x82408000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_MX6ULL=y
CONFIG_TARGET_O4_IMX6ULL_NANO=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_MT41K256M16HA_125E=y
CONFIG_IMX_MODULE_FUSE=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=1200000000
CONFIG_ARCH_OCTEON=y
CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff80100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xe000
CONFIG_ENV_SECT_SIZE=0x100
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=800000000
CONFIG_ARCH_OCTEON=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_LOAD_ADDR=0xffffffff80100000
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX2_95XX=y
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX2_96XX=y
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX_81XX=y
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x2800000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX_83XX=y
+CONFIG_SYS_MALLOC_LEN=0x4008000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x2800000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c4/hc4"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SOUND=y
CONFIG_SYSRESET=y
-CONFIG_OPTEE=y
+CONFIG_OPTEE_LIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="odroid-n2"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" odroid-hc4"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_AHCI=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SATA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-n2/n2-plus"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x310000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DFU_MMC=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x140000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_DM=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=147
CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=1
+CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=62
CONFIG_USB_OMAP3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_CONS_INDEX=3
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=80
+CONFIG_HAS_OMAP_EHCI_PHY3_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY3_RESET_GPIO=79
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80200000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x10000000
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_ARCH_RV64I=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x87000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_PROMPT="openpiton$ "
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x10000000
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
-CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x87000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
# CONFIG_SPL_BANNER_PRINT is not set
CONFIG_SPL_CPU=y
CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_RTC=y
CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base"
CONFIG_IDENT_STRING="\nOpenRD-Base"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client"
CONFIG_IDENT_STRING="\nOpenRD-Client"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate"
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6UL=y
CONFIG_TARGET_OPOS6ULDEV=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_SY8106A_VOUT1_VOLT=1100
CONFIG_DRAM_CLK=624
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SATAPWR="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ORIGEN=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4200
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ORIGEN"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43e00000
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p200"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p201"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p212"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
CONFIG_TEGRA210=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_2180=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
CONFIG_TEGRA210=y
CONFIG_TARGET_P2571=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000"
CONFIG_TEGRA186=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500"
CONFIG_TEGRA186=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
CONFIG_TEGRA210=y
CONFIG_TARGET_P3450_0000=y
+CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_MMC0_CD_PIN="PD14"
-CONFIG_MMC2_PINS="PC"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PD10"
CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_PAZ00=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xA0000
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052"
CONFIG_ENV_OFFSET_REDUND=0xC0000
CONFIG_TARGET_PCM052=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_SYS_EEPROM_SIZE=32768
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MX6Q=y
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_PCM058=y
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-phytec-mira-rdk-nand"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pi"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x23e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pit"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x23e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_EXPU1=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_LEGACY=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_TARGET_PG_WCOM_SELI8=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x1004000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_LEGACY=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=1000
CONFIG_TARGET_PHYCORE_AM335X_R2=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=1000
CONFIG_TARGET_PHYCORE_AM335X_R2=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
-CONFIG_SYS_EEPROM_SIZE=4096
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_PHYCORE_IMX8MP=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
-CONFIG_SYS_EEPROM_SIZE=4096
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
CONFIG_ENV_SIZE=0x4000
CONFIG_MX6UL=y
CONFIG_TARGET_PCL063=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand"
CONFIG_SPL_TEXT_BASE=0x00909000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ENV_SIZE=0x4000
CONFIG_MX6ULL=y
CONFIG_TARGET_PCL063_ULL=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc"
CONFIG_SPL_TEXT_BASE=0x908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x88080000
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
CONFIG_MACH_PIC32=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x88500000
CONFIG_BOOTDELAY=5
CONFIG_SYS_PROMPT="dask # "
# CONFIG_CMD_SAVEENV is not set
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi"
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
CONFIG_SPL_I2C=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
CONFIG_SPL_I2C=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6QDL=y
CONFIG_TARGET_PICO_IMX6=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run default_boot"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPL_I2C=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_CONS_INDEX=4
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_SPL_I2C=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PICO_IMX8MQ=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
CONFIG_SPL_I2C=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6UL=y
CONFIG_TARGET_PICO_IMX6UL=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
CONFIG_SPL_I2C=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
# CONFIG_NETDEVICES is not set
CONFIG_AXP209_POWER=y
CONFIG_AXP_DCDC2_VOLT=1250
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2"
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_PINEPHONE_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2"
+CONFIG_LED_STATUS=y
+CONFIG_LED_STATUS_GPIO=y
+CONFIG_LED_STATUS0=y
+CONFIG_LED_STATUS_BIT=114
+CONFIG_LED_STATUS_STATE=2
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_PLUTUX=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x50000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_PM9G45=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
CONFIG_IDENT_STRING="\nPogo E02"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x1F0000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar"
CONFIG_IDENT_STRING="poplar"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="poplar# "
CONFIG_CMD_MMC=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Porter"
CONFIG_R8A7791=y
CONFIG_TARGET_PORTER=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=720
CONFIG_TARGET_PXM2=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SPEED=400000
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_CONS_INDEX=2
CONFIG_USB_MUSB_HOST=y
CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_SPL_CPU=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET=y
CONFIG_SPL_PCI=y
-CONFIG_SPL_PCH_SUPPORT=y
-CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_PCH=y
+CONFIG_SPL_RTC=y
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_TARGET_QEMU_ARM_32BIT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0x8FE00000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
CONFIG_TARGET_R2DPLUS=y
+CONFIG_SYS_LOAD_ADDR=0x8e000000
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP152_POWER=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_BEACON_RZG2M=y
# CONFIG_SPL is not set
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_BEACON_RZG2N=y
# CONFIG_SPL is not set
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x0
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_BEACON_RZG2H=y
# CONFIG_SPL is not set
CONFIG_LTO=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EAGLE=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_CONDOR=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EBISU=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x70
-CONFIG_SYS_I2C_EEPROM_BUS=7
-CONFIG_SYS_EEPROM_SIZE=128
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_DRAAK=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC00000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_TARGET_FALCON=y
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" radxa-zero"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_RASTABAN=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_ARCH_RMOBILE=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x70
-CONFIG_SYS_I2C_EEPROM_BUS=7
-CONFIG_SYS_EEPROM_SIZE=128
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x70
-CONFIG_SYS_I2C_EEPROM_BUS=7
-CONFIG_SYS_EEPROM_SIZE=128
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
+CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg"
CONFIG_MX6S=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x60800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
CONFIG_TARGET_RUT=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_CMD_ASKENV=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" s400"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MEMTEST_END=0xb0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x2E0200
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2"
CONFIG_TARGET_NANOPI2=y
CONFIG_ROOT_DEV=1
CONFIG_BOOT_PART=1
CONFIG_ROOT_PART=2
+CONFIG_SYS_LOAD_ADDR=0x71080000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
CONFIG_TARGET_S5P_GONI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x34000000
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x44800000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x44800000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6338=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAM9X60EK=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
CONFIG_AT91_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAM9X60EK=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=8
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
CONFIG_AT91_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAM9X60EK=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
CONFIG_AT91_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_QSPI_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_QSPI_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp"
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_TARGET_SAMA5D2_ICP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x20000000
+CONFIG_SYS_MEMTEST_END=0x40000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp"
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlycon earlyprintk=serial,ttyS0, ignore_loglevel root=/dev/mmcblk0p2 memtest=0 rootfstype=ext4 rw rootwait"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=2
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=66000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=66000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_OF_LIBFDT=y
+# CONFIG_EFI_LOADER_HII is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_NAND_BOOT=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_SD_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_SD_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_QSPI_BOOT=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
+CONFIG_SYS_NAND_OOBSIZE=0xe0
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_SPL_TEXT_BASE=0x200000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000"
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000"
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SANDBOX64=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SANDBOX_OSD=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
+CONFIG_WDT_GPIO=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_PRE_CON_BUF_ADDR=0xf0000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_RSASSA_PSS=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_BIND=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_SANDBOX=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
+CONFIG_WDT_GPIO=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_RTC=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
+# CONFIG_SPL_DM_I2C_GPIO is not set
CONFIG_SYS_I2C_SANDBOX=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_RTC=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
+# CONFIG_SPL_DM_I2C_GPIO is not set
CONFIG_SYS_I2C_SANDBOX=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_SEABOARD=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
CONFIG_TEGRA_KEYBOARD=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ENV_OFFSET=0x3c00000
CONFIG_MX6ULL=y
CONFIG_TARGET_NPI_IMX6ULL=y
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board"
CONFIG_SPL_TEXT_BASE=0x908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFFFF0000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510"
CONFIG_MESON_G12A=y
CONFIG_IDENT_STRING=" sei510"
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run load_logo"
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFFFF0000
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610"
CONFIG_MESON_G12A=y
CONFIG_IDENT_STRING=" sei610"
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run load_logo"
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6358=y
CONFIG_BOARD_SFR_NB4_SER=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1b0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_GPIO=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_TARGET_SIFIVE_UNLEASHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb"
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK=y
CONFIG_SPL_GPIO=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ID_EEPROM=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_PWM=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x54
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3F0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SILINUX_EK874=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Silk"
CONFIG_R8A7794=y
CONFIG_TARGET_SILK=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x180000
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_PHYLIB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5250"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5420"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x23e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_SYS_TEXT_BASE=0x34800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
CONFIG_TARGET_SMDKC100=y
CONFIG_IDENT_STRING=" for SMDKC100"
+CONFIG_SYS_LOAD_ADDR=0x30000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4200
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDKC210/V310"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43e00000
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="SMDKV310 # "
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
CONFIG_TARGET_SMEGW01=y
CONFIG_IMX_BOOTAUX=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/storopack/smegw01/imximage.cfg"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x7F
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
CONFIG_BOOTDELAY=3
CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SOFT=y
+CONFIG_SYS_I2C_SOFT_SLAVE=0x7F
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MALLOC_LEN=0x120000
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_SNIPER=y
CONFIG_SPL=y
# CONFIG_CMD_NFS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_OMAP24_I2C_SPEED=400000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_TWL4030_INPUT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
-# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_SOCFPGA_ARRIA5_SECU1=y
CONFIG_ENV_OFFSET_REDUND=0x120000
# CONFIG_SPL_LIBDISK_SUPPORT is not set
-# CONFIG_SPL_SPI_SUPPORT is not set
+# CONFIG_SPL_SPI is not set
CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\""
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=1024
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_EEPROM_SIZE=1024
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_DENALI=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2
# CONFIG_DM_SPI_FLASH is not set
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0xE0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_MALLOC_LEN=0x500000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_SPL_TEXT_BASE=0xFFE00000
# CONFIG_PSCI_RESET is not set
CONFIG_OPTIMIZE_INLINING=y
CONFIG_SPL_OPTIMIZE_INLINING=y
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6ULL=y
CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3FC000
CONFIG_ENV_SECT_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for spring"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_SYS_I2C_S3C24X0=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_U8500=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+# CONFIG_SETUP_MEMORY_TAGS is not set
+CONFIG_INITRD_TAG=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy"
+CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fastbootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CONFIG=y
CONFIG_CMD_GETTIME=y
CONFIG_EFI_PARTITION=y
# CONFIG_NET is not set
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x18100000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
+CONFIG_USB_GADGET_PRODUCT_NUM=0x685d
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MCDE_SIMPLE=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_STI=y
CONFIG_SYS_TEXT_BASE=0x7D600000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
+CONFIG_SYS_MALLOC_LEN=0x1800000
CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x90400000
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run bootcmd_romfs"
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_EVALUATION=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F469_DISCOVERY=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x8008000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x8008000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_DISCO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xd0400000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_EVAL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xd0400000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
CONFIG_STM32H7=y
CONFIG_TARGET_STM32H750_ART_PI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc1800000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_ENV_OFFSET=0x280000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_ICORE_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_ENV_OFFSET=0x280000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_ICORE_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_ENV_OFFSET=0x280000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_MICROGEA_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_ENV_OFFSET=0x280000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_MICROGEA_STM32MP1=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_CMD_STM32KEY=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MTDPARTS_RUNTIME=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_STM32_FMC2=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ENV_OFFSET_REDUND=0x4C0000
CONFIG_TYPEC_STUSB160X=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MTDPARTS_RUNTIME=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_STM32_FMC2=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_DH_STM32MP1_PDK2=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=3
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
CONFIG_STM32_IPCC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SYS_I2C_EEPROM_BUS=3
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_TARGET_DH_STM32MP1_PDK2=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
CONFIG_STM32_IPCC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_MTDPARTS_RUNTIME=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_STM32_FMC2=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x40000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stmark2"
CONFIG_TARGET_STMARK2=y
+CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1"
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Stout"
CONFIG_R8A7790=y
CONFIG_TARGET_STOUT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_BOARD_INIT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x14000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_ARM=y
-CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SYNQUACER=y
-CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_TEXT_BASE=0x08200000
CONFIG_ENV_SIZE=0x30000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
CONFIG_TARGET_DEVELOPERBOX=y
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_BOOTSTAGE_STASH_SIZE=4096
CONFIG_HUSH_PARSER=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x460000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_DEBUG_UART_CLOCK=18432000
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067"
+CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_TARGET_TB100=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_ENV_SIZE=0x800
+CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
CONFIG_SYS_CLK_FREQ=500000000
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6Q=y
CONFIG_TARGET_TBS2910=y
+CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA30=y
CONFIG_TARGET_TEC_NG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_TEC=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start"
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
CONFIG_SPL_TEXT_BASE=0x40004030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_FPGA_ALTERA=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x0
# CONFIG_MMC is not set
CONFIG_SF_DEFAULT_SPEED=27777777
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_THUBAN=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SYS_TEXT_BASE=0x00500000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x101000
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
CONFIG_DEBUG_UART_BASE=0x87e024000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x500000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000 debug maxcpus=48 rootwait rw root=/dev/sda2 coherent_pool=16M"
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0x40400000
CONFIG_TI816X=y
CONFIG_TARGET_TI816X_EVM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E0000
CONFIG_SPL_FS_FAT=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_COUNT=0x40
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SPL_GPIO=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_SYS_TEXT_BASE=0
CONFIG_ENV_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x2a00000
+CONFIG_SYS_MALLOC_LEN=0x3200000
CONFIG_DEFAULT_DEVICE_TREE="total_compute"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_MEMTEST_START=0x80100000
CONFIG_SYS_MEMTEST_END=0x83f00000
CONFIG_ENV_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_SYS_LOAD_ADDR=0xa1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6DL=y
CONFIG_TARGET_TQMA6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6DL=y
CONFIG_TARGET_TQMA6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6Q=y
CONFIG_TARGET_TQMA6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_TQMA6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6S=y
CONFIG_TARGET_TQMA6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6S=y
CONFIG_TARGET_TQMA6=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_TARGET_TRATS2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x63300000
CONFIG_TARGET_TRATS=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
+CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x44800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_TRIMSLICE=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x3000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
+CONFIG_SYS_I2C_SLAVE=0x7F
+CONFIG_SYS_I2C_SPEED=200000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" u200"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0x6000000
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_USE_PREBOOT=y
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6QDL=y
CONFIG_TARGET_UDOO=y
+CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SX=y
CONFIG_TARGET_UDOO_NEO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
CONFIG_SPL_TEXT_BASE=0x00040000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_LOAD_ADDR=0x85000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_CMD_CONFIG=y
# CONFIG_CMD_XIMG is not set
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SPL_NAND_DENALI=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SMC911X=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
CONFIG_SPL_TEXT_BASE=0x00100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_LOAD_ADDR=0x85000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_CMD_CONFIG=y
# CONFIG_CMD_XIMG is not set
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SPL_NAND_DENALI=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SNI_AVE=y
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
CONFIG_ARCH_UNIPHIER_V8_MULTI=y
CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_LOAD_ADDR=0x85000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=6
CONFIG_CMD_CONFIG=y
# CONFIG_CMD_XIMG is not set
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SNI_AVE=y
CONFIG_PINCONF=y
CONFIG_SPI=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x2000
CONFIG_ENV_SECT_SIZE=0x2000
+CONFIG_SYS_MALLOC_LEN=0x26000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="usb_a9263"
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_USBARMORY=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory"
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x72000000
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
CONFIG_ENV_SIZE=0x2000
CONFIG_MX6ULL=y
CONFIG_TARGET_DART_6UL=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SPL_USB_HOST=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_TARGET_VENICE2=y
+CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_TEGRA20=y
CONFIG_TARGET_VENTANA=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_VERDIN_IMX8MM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mm/imximage.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb"
CONFIG_LOG=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x810000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9"
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_SYS_MALLOC_LEN=0x840000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_VEXPRESS_CA9X4=y
+CONFIG_SYS_TEXT_BASE=0x60800000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="vexpress-v2p-ca9"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
+CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_ADDR=0x47F80000
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_SMC911X=y
+CONFIG_SMC911X_32_BIT=y
+CONFIG_BAUDRATE=38400
+CONFIG_CONS_INDEX=0
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0x202000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_VYBRID_GPIO=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x180000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0x0220000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
+CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_VYBRID_GPIO=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x20f00000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_MX6SX=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_SOFTING_VINING_2000=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-softing-vining-2000"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_PWM_IMX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x04e000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2"
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_ARCH_MTMIPS=y
CONFIG_SOC_MT7628=y
CONFIG_BOARD_VOCORE2=y
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revd1"
CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
CONFIG_TARGET_WARP7=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_OPTEE_TZDRAM_SIZE=0x02000000
-CONFIG_OPTEE_TZDRAM_BASE=0x9e000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
CONFIG_TARGET_WARP7=y
CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OPTEE_LOAD_ADDR=0x84000000
CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
-CONFIG_OPTEE_TZDRAM_BASE=0x9d000000
CONFIG_BOOTM_OPTEE=y
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6SL=y
CONFIG_TARGET_WARP=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_MALLOC_LEN=0x2300000
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_I2C=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" wetek-core2"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_CMD_MAX6957=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_TEXT_BASE=0x00000000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x120000
+CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS2,115200n8"
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
+CONFIG_SYS_I2C_SPEED=350000
+CONFIG_SYS_I2C_EEPROM_ADDR=0x56
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_LPC32XX_MLC=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
CONFIG_SPL_TEXT_BASE=0x40000030
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SILENT_CONSOLE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_TARGET_XENGUEST_ARM64=y
CONFIG_SYS_TEXT_BASE=0x40080000
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_IDENT_STRING=" xenguest"
+CONFIG_SYS_LOAD_ADDR=0x40000000
CONFIG_BOOTDELAY=10
CONFIG_SYS_PROMPT="xenguest# "
# CONFIG_CMD_BDI is not set
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFINE_TCM_OCM_MMAP=y
CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SET_DFU_ALT_INFO=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ZYNQ=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_USB_FUNCTION_THOR=y
CONFIG_DISPLAY=y
CONFIG_SPL_GZIP=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x1a00
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_MAX_CHIPS=2
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
+CONFIG_SYS_MALLOC_LEN=0x1a00
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
CONFIG_SPL=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_CMD_ZYNQMP is not set
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ZYNQMP_R5=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x1400000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
CONFIG_DEBUG_UART_BASE=0xff010000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTSTAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ZynqMP r5> "
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
+CONFIG_SYS_MALLOC_LEN=0x4040000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_ZYNQ_MAC_IN_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_CMD_FRU=y
CONFIG_ZYNQMP_USB=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_MAX_CHIPS=2
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
CONFIG_SYS_CPU="dc233c"
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_XTFPGA_KC705=y
+CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
CONFIG_AUTOBOOT_KEYED=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX25=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_ZMX25=y
-CONFIG_BOOTDELAY=5
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
-CONFIG_AUTOBOOT_DELAY_STR="delaygs"
-CONFIG_AUTOBOOT_STOP_STR="stopgs"
-CONFIG_USE_PREBOOT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="zmx25> "
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0040000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_USB=y
-CONFIG_LZO=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ZYNQ=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_ARM_DCC=y
# CONFIG_GZIP is not set
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
#ccflags-y += -DET_DEBUG -DDEBUG
-obj-$(CONFIG_PARTITIONS) += part.o
+obj-$(CONFIG_PARTITIONS) += part.o
obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o
obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o
obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o
#include <malloc.h>
#include <memalign.h>
#include <part_efi.h>
+#include <dm/ofnode.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
#include <u-boot/crc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_HAVE_BLOCK_DEVICE
/* GUID for basic data partitons */
* from the start of the device) to be specified as a property
* of the device tree '/config' node.
*/
- config_offset = fdtdec_get_config_int(gd->fdt_blob,
- "u-boot,efi-partition-entries-offset",
- -EINVAL);
+ config_offset = ofnode_conf_read_int(
+ "u-boot,efi-partition-entries-offset", -EINVAL);
if (config_offset != -EINVAL) {
offset_bytes = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
offset_blks = offset_bytes / dev_desc->blksz;
printf("Part Start Sect x Size Type\n");
i=1;
do {
- printf(" %2d " LBAFU " " LBAFU " %6ld %.32s\n",
+ printf(" %2d %8" LBAFlength "u %8" LBAFlength "u %6ld %.32s\n",
i, info.start, info.size, info.blksz, info.type);
i++;
} while (part_get_info_iso_verb(dev_desc, i, &info, 0) != -1);
CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o)
CONFIG_SPL_I2C (drivers/i2c/libi2c.o)
CONFIG_SPL_GPIO (drivers/gpio/libgpio.o)
-CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o)
-CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o)
+CONFIG_SPL_MMC (drivers/mmc/libmmc.o)
+CONFIG_SPL_SERIAL (drivers/serial/libserial.o)
CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
-CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
+CONFIG_SPL_SPI (drivers/spi/libspi.o)
CONFIG_SPL_FS_FAT (fs/fat/libfat.o)
CONFIG_SPL_FS_EXT4
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
on OMAP3:
nandecc hw
-nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
-spl export atags /* export ATAGS */
+nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
+spl export atags /* export ATAGS */
nand erase 0x680000 0x20000 /* erase - one page */
nand write 0x80000100 0x680000 0x20000 /* write the image - one page */
call with FDT:
nandecc hw
-nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
+nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
tftpboot 0x80000100 devkit8000.dtb /* Read fdt */
spl export fdt 0x82000000 - 0x80000100 /* export FDT */
nand erase 0x680000 0x20000 /* erase - one page */
possible to set large enough default buffer (8 MiB @ BBB)
-
FIT image format for download
-----------------------------
where "u-boot.bin" is the DFU entity name to be stored.
-
To do
-----
the DTB with a different DTB. fdtfile will automatically be set for you if
it matches the format ${soc}-${board}.dtb which covers most 32 bit use cases.
AArch64 generally does not match as the Linux kernel put the dtb files under
- SoC vendor directories.
+ SoC vendor directories.
ramdisk_addr_r:
CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved.
-CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
+CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
CONFIG_SPL_OS_BOOT Activate Falcon Mode.
A board may chose to look at the environment for decisions about falcon
mode. In this case the following variables may be supported:
-boot_os : Set to yes/Yes/true/True/1 to enable booting to OS,
+boot_os : Set to yes/Yes/true/True/1 to enable booting to OS,
any other value to fall back to U-Boot (including
unset)
falcon_args_file : Filename to load as the 'args' portion of falcon mode
flexibility, so that one day we can eliminate the old mechanism.
- CONFIG_SYS_NAND_ONFI_DETECTION
- Enables detection of ONFI compliant devices during probe.
- And fetching device parameters flashed on device, by parsing
- ONFI parameter page.
-
Platform specific options
=========================
CONFIG_NAND_OMAP_GPMC
so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
SPL-NAND driver with software ECC correction support.
- CONFIG_NAND_OMAP_ECCSCHEME
- On OMAP platforms, this CONFIG specifies NAND ECC scheme.
- It can take following values:
- OMAP_ECC_HAM1_CODE_SW
- 1-bit Hamming code using software lib.
- (for legacy devices only)
- OMAP_ECC_HAM1_CODE_HW
- 1-bit Hamming code using GPMC hardware.
- (for legacy devices only)
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
- 4-bit BCH code (unsupported)
- OMAP_ECC_BCH4_CODE_HW
- 4-bit BCH code (unsupported)
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
- 8-bit BCH code with
- - ecc calculation using GPMC hardware engine,
- - error detection using software library.
- - requires CONFIG_BCH to enable software BCH library
- (For legacy device which do not have ELM h/w engine)
- OMAP_ECC_BCH8_CODE_HW
- 8-bit BCH code with
- - ecc calculation using GPMC hardware engine,
- - error detection using ELM hardware engine.
- OMAP_ECC_BCH16_CODE_HW
- 16-bit BCH code with
- - ecc calculation using GPMC hardware engine,
- - error detection using ELM hardware engine.
-
- How to select ECC scheme on OMAP and AMxx platforms ?
- -----------------------------------------------------
- Though higher ECC schemes have more capability to detect and correct
- bit-flips, but still selection of ECC scheme is dependent on following
- - hardware engines present in SoC.
- Some legacy OMAP SoC do not have ELM h/w engine thus such
- SoC cannot support BCHx_HW ECC schemes.
- - size of OOB/Spare region
- With higher ECC schemes, more OOB/Spare area is required to
- store ECC. So choice of ECC scheme is limited by NAND oobsize.
-
- In general following expression can help:
- NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
- where
- NAND_OOBSIZE = number of bytes available in
- OOB/spare area per NAND page.
- NAND_PAGESIZE = bytes in main-area of NAND page.
- ECC_BYTES = number of ECC bytes generated to
- protect 512 bytes of data, which is:
- 3 for HAM1_xx ecc schemes
- 7 for BCH4_xx ecc schemes
- 14 for BCH8_xx ecc schemes
- 26 for BCH16_xx ecc schemes
-
- example to check for BCH16 on 2K page NAND
- NAND_PAGESIZE = 2048
- NAND_OOBSIZE = 64
- 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
- Thus BCH16 cannot be supported on 2K page NAND.
-
- However, for 4K pagesize NAND
- NAND_PAGESIZE = 4096
- NAND_OOBSIZE = 224
- ECC_BYTES = 26
- 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
- Thus BCH16 can be supported on 4K page NAND.
-
-
CONFIG_NAND_OMAP_GPMC_PREFETCH
On OMAP platforms that use the GPMC controller
(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
Partition Map for USB device 0 -- Partition Type: DOS
Part Start Sector Num Sectors UUID Type
- 1 3072 263168 000c4046-01 06
- 2 266240 13457408 000c4046-02 83
+ 1 3072 263168 000c4046-01 06
+ 2 266240 13457408 000c4046-02 83
Odroid # ls usb 0:2 /boot
<DIR> 4096 .
# pcap stop
# tftpput 0xffffffff80100000 $pcapsize 10.0.2.2:capture.pcap
-
I. Building the required images
1. You have to enable generic SPL configuration options (see
-doc/README.SPL) as well as CONFIG_SPL_NET_SUPPORT,
+doc/README.SPL) as well as CONFIG_SPL_NET,
CONFIG_SPL_ETH, CONFIG_SPL_LIBGENERIC_SUPPORT and
CONFIG_SPL_LIBCOMMON_SUPPORT in your board configuration file to build
SPL with support for booting over the network. Also you have to enable
CONFIG_SKIP_LOWLEVEL_INIT:
If you want to boot this system from SPI ROM and bypass e-bios (the
- other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
- in "include/configs/adp-ag101p.h".
+ other boot loader on ROM). You should enable CONFIG_SKIP_LOWLEVEL_INIT
+ when running menuconfig or similar.
Build and boot steps
--------------------
This matrix concerns the actual source code version.
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
-| | | S805X | S905D | | S905D2 | A311D | S905D3 |
-| | | | | | S905Y2 | | |
-+===============================+===========+=================+==============+============+============+=============+==============+
-| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
-| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
-| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 |
-| | P201 | LibreTech-AC v2 | | | | | |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Infrared Decoder | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SPI (CC) | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| NAND | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| CEC | No | No | No | *N/A* | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Thermal Sensor | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
+| | | S805X | S905D | | S905D2 | A311D | S905D3 |
+| | | S905W | | | S905Y2 | | |
++===============================+===========+=================+==============+=============+============+=============+==============+
+| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
+| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
+| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 |
+| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 |
+| | | JetHub J80 | | | | | BananaPi-M5 |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Infrared Decoder | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SPI (CC) | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| NAND | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| CEC | No | No | No | *N/A* | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Thermal Sensor | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
Board Documentation
-------------------
beelink-gtking
beelink-gtkingpro
+ jethub-j100
+ jethub-j80
khadas-vim2
khadas-vim3l
khadas-vim3
p201
p212
q200
+ radxa-zero
s400
sei510
sei610
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for JetHub J100
+=======================
+
+JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation
+controller manufactured by JetHome with the following specifications:
+
+ - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
+ - no video out
+ - 512Mb/1GB DDR3
+ - 8/16GB eMMC flash
+ - 1 x USB 2.0
+ - 1 x 10/100Mbps ethernet
+ - WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE
+ 802.11a/b/g/n/ac, Bluetooth 4.2.
+ - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
+ power and Zigbee 3.0 support.
+ - 2 x gpio LEDS
+ - GPIO user Button
+ - 1 x 1-Wire
+ - 2 x RS-485
+ - 4 x dry contact digital GPIO inputs
+ - 3 x relay GPIO outputs
+ - DC source with a voltage of 9 to 56 V / Passive POE
+ - DIN Rail Mounting case
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make jethub_j100_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain binaries
+from the git tree published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot
+ $ cd jethub-u-boot
+ $ export FIPDIR=$PWD
+
+Go back to mainline U-boot source tree then :
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/j100/bl2.bin fip/
+ $ cp $FIPDIR/j100/acs.bin fip/
+ $ cp $FIPDIR/j100/bl21.bin fip/
+ $ cp $FIPDIR/j100/bl30.bin fip/
+ $ cp $FIPDIR/j100/bl301.bin fip/
+ $ cp $FIPDIR/j100/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ $ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $FIPDIR/j100/aml_encrypt_axg --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc --level v3
+
+and then write the image to eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_emmc_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for JetHub J80
+======================
+
+JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation
+controller manufactured by JetHome with the following specifications:
+
+ - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
+ - No video out
+ - 1GB DDR3
+ - 8/16GB eMMC flash
+ - 2 x USB 2.0
+ - 1 x 10/100Mbps ethernet
+ - SDIO WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0.
+ - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
+ power and Zigbee 3.0 support.
+ - MicroSD 2.x/3.x/4.x DS/HS cards.
+ - 1 x gpio LED
+ - ADC user Button
+ - DC source 5V microUSB
+ - Square plastic case
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make jethub_j80_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain binaries
+from the git tree published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot
+ $ cd jethub-u-boot
+ $ export FIPDIR=$PWD
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/j80/bl2.bin fip/
+ $ cp $FIPDIR/j80/acs.bin fip/
+ $ cp $FIPDIR/j80/bl21.bin fip/
+ $ cp $FIPDIR/j80/bl30.bin fip/
+ $ cp $FIPDIR/j80/bl301.bin fip/
+ $ cp $FIPDIR/j80/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ $ $FIPDIR/j80/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD/eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
- UART serial
- Infrared receiver
+The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands
+applies for HC4.
+
Schematics are available on the manufacturer website.
U-Boot compilation
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Radxa Zero
+=====================
+
+Radxa Zero is a small form factor SBC based on the Amlogic S905Y2
+chipset that ships in a number of RAM/eMMC configurations:
+
+Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436
+wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB
+eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
+
+- Amlogic S905Y2 quad-core Cortex-A53
+- Mali G31-MP2 GPU
+- HDMI 2.1 output (micro)
+- 1x USB 2.0 port - Type C (OTG)
+- 1x USB 3.0 port - Type C (Host)
+- 1x micro SD Card slot
+- 40 Pin GPIO header
+
+Schematics are available on the manufacturer website:
+
+https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make radxa-zero_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+git trees published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git
+ $ git clone https://github.com/radxa/fip.git
+
+ $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev
+ $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools
+
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+ $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt
+
+ $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
+ $ export ARCH=arm
+ $ cd u-boot
+ $ make radxa-zero_defconfig
+ $ make
+
+ $ cp u-boot.bin ../fip/radxa-zero/bl33.bin
+ $ cd ../fip/radxa-zero
+ $ make
+
+This will generate:
+
+.. code-block:: bash
+
+ $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
+
+Then write the image to SD with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
openpiton/index
qualcomm/index
rockchip/index
+ siemens/index
sifive/index
sipeed/index
socionext/index
st/index
+ ste/index
tbs/index
ti/index
toradex/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Siemens
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ iot2050
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Jan Kiszka <jan.kiszka@siemens.com>
+
+SIMATIC IOT2050 BASIC and ADVANCED
+==================================
+
+The SIMATIC IOT2050 is an open industrial IoT gateway that is using the TI
+AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced
+variant is prepared for secure boot.
+
+The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader
+called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and
+OP-TEE, before booting U-Boot on the A53 cores. This describes how to build all
+open artifacts into a flashable image for the OSPI flash. The flash image will
+work on both variants.
+
+Dependencies
+------------
+
+ATF: Upstream release 2.4 or newer
+OP-TEE: Upstream release 3.10.0 or newer
+
+Binary dependencies can be found in
+https://github.com/siemens/meta-iot2050/tree/master/recipes-bsp/u-boot/files/prebuild.
+The following binaries from that source need to be present in the build folder:
+
+ - tiboot3.bin
+ - sysfw.itb
+ - sysfw.itb_HS
+ - sysfw_sr2.itb
+ - sysfw_sr2.itb_HS
+
+Building
+--------
+
+Make sure that CROSS_COMPILE is set appropriately:
+
+.. code-block:: text
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+
+ATF:
+
+.. code-block:: text
+
+ $ make PLAT=k3 SPD=opteed K3_USART=1
+
+OP-TEE:
+
+.. code-block:: text
+
+ $ make PLATFORM=k3-am65x CFG_ARM64_core=y CFG_TEE_CORE_LOG_LEVEL=2 CFG_CONSOLE_UART=1
+
+U-Boot:
+
+.. code-block:: text
+
+ $ export ATF=/path/to/bl31.bin
+ $ export TEE=/path/to/tee-pager_v2.bin
+ $ make iot2050_defconfig
+ $ make
+
+Flashing
+--------
+
+Via U-Boot:
+
+.. code-block:: text
+
+ IOT2050> sf probe
+ IOT2050> load mmc 0:1 $loadaddr /path/to/flash.bin
+ IOT2050> sf update $loadaddr 0x0 $filesize
+
+Via external programmer Dediprog SF100 or SF600:
+
+.. code-block:: text
+
+ $ dpcmd --vcc 2 -v -u flash.bin
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+ST-Ericsson
+===========
+
+.. toctree::
+ :maxdepth: 2
+
+ stemmy
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Stephan Gerhold <stephan@gerhold.net>
+
+ST-Ericsson U8500 Samsung "stemmy" board
+========================================
+
+The "stemmy" board supports Samsung smartphones released with
+the ST-Ericsson NovaThor U8500 SoC, e.g.
+
+ +---------------------------+----------+--------------+----------------+
+ | Device | Model | Codename | U-Boot |
+ +===========================+==========+==============+================+
+ | Samsung Galaxy Ace 2 | GT-I8160 | codina | ``u-boot.bin`` |
+ +---------------------------+----------+--------------+----------------+
+ | Samsung Galaxy Amp | SGH-I407 | kyle | ``u-boot.img`` |
+ +---------------------------+----------+--------------+----------------+
+ | Samsung Galaxy Beam | GT-I8530 | gavini | ``u-boot.bin`` |
+ +---------------------------+----------+--------------+----------------+
+ | Samsung Galaxy Exhibit | SGH-T599 | codina (TMO) | ``u-boot.bin`` |
+ +---------------------------+----------+--------------+----------------+
+ | Samsung Galaxy S Advance | GT-I9070 | janice | ``u-boot.bin`` |
+ +---------------------------+----------+--------------+----------------+
+ | Samsung Galaxy S III mini | GT-I8190 | golden | ``u-boot.img`` |
+ +---------------------------+----------+--------------+----------------+
+ | Samsung Galaxy Xcover 2 | GT-S7710 | skomer | ``u-boot.img`` |
+ +---------------------------+----------+--------------+----------------+
+
+At the moment, U-Boot is intended to be chain-loaded from
+the original Samsung bootloader, not replacing it entirely.
+
+Installation
+------------
+First, setup ``CROSS_COMPILE`` for ARMv7. Then, build U-Boot for ``stemmy``::
+
+ $ export CROSS_COMPILE=arm-none-eabi-
+ $ make stemmy_defconfig
+ $ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+For newer devices (check ``u-boot.img`` in the table above), the U-Boot binary
+has to be packed into an Android boot image. Devices with ``u-boot.bin`` boot
+the raw U-Boot binary from the boot partition. You can build the Android boot
+image with ``mkbootimg``, e.g. from from android-7.1.2_r37_::
+
+ $ mkbootimg \
+ --kernel=u-boot.bin \
+ --base=0x00000000 \
+ --kernel_offset=0x00100000 \
+ --ramdisk_offset=0x02000000 \
+ --tags_offset=0x00000100 \
+ --output=u-boot.img
+
+.. _android-7.1.2_r37: https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg
+
+To flash the U-Boot binary, enter the Samsung download mode
+(press Power + Home + Volume Down). Use Heimdall_ to flash the U-Boot image to
+the Android boot partition::
+
+ $ heimdall flash --Kernel u-boot.(bin|img)
+
+If this is not working but there are messages like ``Android recovery image`` in
+the UART console, you can try flashing to the recovery partition instead::
+
+ $ heimdall flash --Kernel2 u-boot.(bin|img)
+
+.. _Heimdall: https://gitlab.com/BenjaminDobell/Heimdall
+
+After a reboot the U-Boot prompt should appear via UART. Unless interrupted it
+automatically boots to USB Fastboot mode where Android boot images can be booted
+via ``fastboot boot boot.img``. It is mainly intended to boot mainline Linux,
+but booting original Samsung Android boot images is also supported (e.g. for
+charging).
+
+UART
+----
+UART is available through the micro USB port, similar to the Carkit standard.
+With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-.
+
+.. note::
+ Make sure to connect the UART cable **before** turning on the phone.
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Tom Rini <trini@konsulko.com>
+
Summary
=======
-This document covers various features of the 'am335x_evm' build, and some of
-the related build targets (am335x_evm_uartN, etc).
+This document covers various features of the `am335x_evm` default
+configuration, some of the related defconfigs, and how to enable hardware
+features not present by default in the defconfigs.
Hardware
-========
+--------
The binary produced by this board supports, based on parsing of the EEPROM
documented in TI's reference designs:
-- AM335x GP EVM
-- AM335x EVM SK
-- Beaglebone White
-- Beaglebone Black
+* AM335x GP EVM
+* AM335x EVM SK
+* The Beaglebone family of designs
Customization
-=============
+-------------
Given that all of the above boards are reference platforms (and the
Beaglebone platforms are OSHA), it is likely that this platform code and
required if a custom platform makes use of these blocks, the following
are required, depending on design:
-- GPIO is only required if DDR3 power is controlled in a way similar to
- EVM SK
-- SPI is only required for SPI flash, or exposing the SPI bus.
+* GPIO is only required if DDR3 power is controlled in a way similar to EVM SK
+* SPI is only required for SPI flash, or exposing the SPI bus.
The following blocks are required:
-- I2C, to talk with the PMIC and ensure that we do not run afoul of
+
+* I2C, to talk with the PMIC and ensure that we do not run afoul of
errata 1.0.24.
-When removing options as part of customization,
-CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
-needs and to remove no longer relevant options as in some cases we
-define additional text blocks (such as for NAND or DFU strings). Also
-note that all of the SPL options are grouped together, rather than with
-the IP blocks, so both areas will need their choices updated to reflect
-the custom design.
+When removing options as part of customization, note that you will likely need
+to look at both `include/configs/am335x_evm.h`,
+`include/configs/ti_am335x_common.h` and `include/configs/am335x_evm.h` as the
+migration to Kconfig is not yet complete.
NAND
-====
+----
The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
this example to program the NAND we assume that an SD card has been
CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
Step-2: Flashing NAND via MMC/SD
+
+.. code-block:: text
+
# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
U-Boot # mmc rescan
# erase flash
Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
The device should boot from images flashed on NAND device.
-NOR
-===
-
-The Beaglebone White can be equipped with a "memory cape" that in turn can
-have a NOR module plugged into it. In this case it is then possible to
-program and boot from NOR. Note that due to how U-Boot is designed we
-must build a specific version of U-Boot that knows we have NOR flash. This
-build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
-build that will assume that the environment is on NOR rather than NAND. In
-the following example we assume that and SD card has been populated with
-MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
-'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a
-binary must be written to the start of NOR, with no header or similar
-prepended. In the following example we use a size of 512KiB (0x80000)
-as that is how much space we set aside before the environment, as per
-the config file.
-
-U-Boot # mmc rescan
-U-Boot # load mmc 0 ${loadaddr} u-boot.bin
-U-Boot # protect off 08000000 +80000
-U-Boot # erase 08000000 +80000
-U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
Falcon Mode
-===========
+-----------
The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is
worst-case however.
Falcon Mode: eMMC
-=================
+-----------------
The recommended layout in this case is:
-MMC BLOCKS |--------------------------------| LOCATION IN BYTES
-0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
-0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
-0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
-0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
-0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
-0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
-0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
+.. code-block:: text
+
+ MMC BLOCKS |--------------------------------| LOCATION IN BYTES
+ 0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
+ 0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
+ 0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
+ 0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
+ 0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
+ 0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
+ 0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
Note that when we run 'spl export' it will prepare to boot the kernel.
This includes relocation of the uImage from where we loaded it to the entry
write garbage into the area, you must delete it from the partition table
first.
-# Ensure we are able to talk with this mmc device
-U-Boot # mmc rescan
-U-Boot # tftp 81000000 am335x/MLO
-# Write to two of the backup locations ROM uses
-U-Boot # mmc write 81000000 100 100
-U-Boot # mmc write 81000000 200 100
-# Write U-Boot to the location set in the config
-U-Boot # tftp 81000000 am335x/u-boot.img
-U-Boot # mmc write 81000000 300 400
-# Load kernel and device tree into memory, perform export
-U-Boot # tftp 81000000 am335x/uImage
-U-Boot # run findfdt
-U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt 81000000 - ${fdtaddr}
-# Write the updated device tree to MMC
-U-Boot # mmc write ${fdtaddr} 80 80
-# Write the uImage to MMC
-U-Boot # mmc write 81000000 900 2000
+.. code-block:: text
+
+ # Ensure we are able to talk with this mmc device
+ U-Boot # mmc rescan
+ U-Boot # tftp 81000000 am335x/MLO
+ # Write to two of the backup locations ROM uses
+ U-Boot # mmc write 81000000 100 100
+ U-Boot # mmc write 81000000 200 100
+ # Write U-Boot to the location set in the config
+ U-Boot # tftp 81000000 am335x/u-boot.img
+ U-Boot # mmc write 81000000 300 400
+ # Load kernel and device tree into memory, perform export
+ U-Boot # tftp 81000000 am335x/uImage
+ U-Boot # run findfdt
+ U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
+ U-Boot # run mmcargs
+ U-Boot # spl export fdt 81000000 - ${fdtaddr}
+ # Write the updated device tree to MMC
+ U-Boot # mmc write ${fdtaddr} 80 80
+ # Write the uImage to MMC
+ U-Boot # mmc write 81000000 900 2000
Falcon Mode: FAT SD cards
-=========================
+-------------------------
In this case the additional file is written to the filesystem. In this
example we assume that the uImage and device tree to be used are already on
afterwards) along with a Falcon Mode aware MLO and the FAT partition has
already been created and marked bootable:
-U-Boot # mmc rescan
-# Load kernel and device tree into memory, perform export
-U-Boot # load mmc 0:1 ${loadaddr} uImage
-U-Boot # run findfdt
-U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+.. code-block:: text
+
+ U-Boot # mmc rescan
+ # Load kernel and device tree into memory, perform export
+ U-Boot # load mmc 0:1 ${loadaddr} uImage
+ U-Boot # run findfdt
+ U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
+ U-Boot # run mmcargs
+ U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
This will print a number of lines and then end with something like:
- Using Device Tree in place at 80f80000, end 80f85928
- Using Device Tree in place at 80f80000, end 80f88928
+
+.. code-block:: text
+
+ Using Device Tree in place at 80f80000, end 80f85928
+ Using Device Tree in place at 80f80000, end 80f88928
+
So then you:
-U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
+.. code-block:: text
+
+ U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
Falcon Mode: NAND
-=================
+-----------------
In this case the additional data is written to another partition of the
NAND. In this example we assume that the uImage and device tree to be are
along with a Falcon Mode aware MLO written to the correct locations for
booting and mtdparts have been configured correctly for the board:
-U-Boot # nand read ${loadaddr} kernel
-U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
-U-Boot # run nandargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-U-Boot # nand erase.part u-boot-spl-os
-U-Boot # nand write ${fdtaddr} u-boot-spl-os
+.. code-block:: text
+
+ U-Boot # nand read ${loadaddr} kernel
+ U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+ U-Boot # run nandargs
+ U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+ U-Boot # nand erase.part u-boot-spl-os
+ U-Boot # nand write ${fdtaddr} u-boot-spl-os
.. toctree::
:maxdepth: 2
+ am335x_evm
j721e_evm
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0-only
+
+==========
+Checkpatch
+==========
+
+Checkpatch (scripts/checkpatch.pl) is a perl script which checks for trivial
+style violations in patches and optionally corrects them. Checkpatch can
+also be run on file contexts and without the kernel tree.
+
+Checkpatch is not always right. Your judgement takes precedence over checkpatch
+messages. If your code looks better with the violations, then its probably
+best left alone.
+
+
+Options
+=======
+
+This section will describe the options checkpatch can be run with.
+
+Usage::
+
+ ./scripts/checkpatch.pl [OPTION]... [FILE]...
+
+Available options:
+
+ - -q, --quiet
+
+ Enable quiet mode.
+
+ - -v, --verbose
+ Enable verbose mode. Additional verbose test descriptions are output
+ so as to provide information on why that particular message is shown.
+
+ - --no-tree
+
+ Run checkpatch without the kernel tree.
+
+ - --no-signoff
+
+ Disable the 'Signed-off-by' line check. The sign-off is a simple line at
+ the end of the explanation for the patch, which certifies that you wrote it
+ or otherwise have the right to pass it on as an open-source patch.
+
+ Example::
+
+ Signed-off-by: Random J Developer <random@developer.example.org>
+
+ Setting this flag effectively stops a message for a missing signed-off-by
+ line in a patch context.
+
+ - --patch
+
+ Treat FILE as a patch. This is the default option and need not be
+ explicitly specified.
+
+ - --emacs
+
+ Set output to emacs compile window format. This allows emacs users to jump
+ from the error in the compile window directly to the offending line in the
+ patch.
+
+ - --terse
+
+ Output only one line per report.
+
+ - --showfile
+
+ Show the diffed file position instead of the input file position.
+
+ - -g, --git
+
+ Treat FILE as a single commit or a git revision range.
+
+ Single commit with:
+
+ - <rev>
+ - <rev>^
+ - <rev>~n
+
+ Multiple commits with:
+
+ - <rev1>..<rev2>
+ - <rev1>...<rev2>
+ - <rev>-<count>
+
+ - -f, --file
+
+ Treat FILE as a regular source file. This option must be used when running
+ checkpatch on source files in the kernel.
+
+ - --subjective, --strict
+
+ Enable stricter tests in checkpatch. By default the tests emitted as CHECK
+ do not activate by default. Use this flag to activate the CHECK tests.
+
+ - --list-types
+
+ Every message emitted by checkpatch has an associated TYPE. Add this flag
+ to display all the types in checkpatch.
+
+ Note that when this flag is active, checkpatch does not read the input FILE,
+ and no message is emitted. Only a list of types in checkpatch is output.
+
+ - --types TYPE(,TYPE2...)
+
+ Only display messages with the given types.
+
+ Example::
+
+ ./scripts/checkpatch.pl mypatch.patch --types EMAIL_SUBJECT,BRACES
+
+ - --ignore TYPE(,TYPE2...)
+
+ Checkpatch will not emit messages for the specified types.
+
+ Example::
+
+ ./scripts/checkpatch.pl mypatch.patch --ignore EMAIL_SUBJECT,BRACES
+
+ - --show-types
+
+ By default checkpatch doesn't display the type associated with the messages.
+ Set this flag to show the message type in the output.
+
+ - --max-line-length=n
+
+ Set the max line length (default 100). If a line exceeds the specified
+ length, a LONG_LINE message is emitted.
+
+
+ The message level is different for patch and file contexts. For patches,
+ a WARNING is emitted. While a milder CHECK is emitted for files. So for
+ file contexts, the --strict flag must also be enabled.
+
+ - --min-conf-desc-length=n
+
+ Set the Kconfig entry minimum description length, if shorter, warn.
+
+ - --tab-size=n
+
+ Set the number of spaces for tab (default 8).
+
+ - --root=PATH
+
+ PATH to the kernel tree root.
+
+ This option must be specified when invoking checkpatch from outside
+ the kernel root.
+
+ - --no-summary
+
+ Suppress the per file summary.
+
+ - --mailback
+
+ Only produce a report in case of Warnings or Errors. Milder Checks are
+ excluded from this.
+
+ - --summary-file
+
+ Include the filename in summary.
+
+ - --debug KEY=[0|1]
+
+ Turn on/off debugging of KEY, where KEY is one of 'values', 'possible',
+ 'type', and 'attr' (default is all off).
+
+ - --fix
+
+ This is an EXPERIMENTAL feature. If correctable errors exists, a file
+ <inputfile>.EXPERIMENTAL-checkpatch-fixes is created which has the
+ automatically fixable errors corrected.
+
+ - --fix-inplace
+
+ EXPERIMENTAL - Similar to --fix but input file is overwritten with fixes.
+
+ DO NOT USE this flag unless you are absolutely sure and you have a backup
+ in place.
+
+ - --ignore-perl-version
+
+ Override checking of perl version. Runtime errors maybe encountered after
+ enabling this flag if the perl version does not meet the minimum specified.
+
+ - --codespell
+
+ Use the codespell dictionary for checking spelling errors.
+
+ - --codespellfile
+
+ Use the specified codespell file.
+ Default is '/usr/share/codespell/dictionary.txt'.
+
+ - --typedefsfile
+
+ Read additional types from this file.
+
+ - --color[=WHEN]
+
+ Use colors 'always', 'never', or only when output is a terminal ('auto').
+ Default is 'auto'.
+
+ - --kconfig-prefix=WORD
+
+ Use WORD as a prefix for Kconfig symbols (default is `CONFIG_`).
+
+ - -h, --help, --version
+
+ Display the help text.
+
+Message Levels
+==============
+
+Messages in checkpatch are divided into three levels. The levels of messages
+in checkpatch denote the severity of the error. They are:
+
+ - ERROR
+
+ This is the most strict level. Messages of type ERROR must be taken
+ seriously as they denote things that are very likely to be wrong.
+
+ - WARNING
+
+ This is the next stricter level. Messages of type WARNING requires a
+ more careful review. But it is milder than an ERROR.
+
+ - CHECK
+
+ This is the mildest level. These are things which may require some thought.
+
+Type Descriptions
+=================
+
+This section contains a description of all the message types in checkpatch.
+
+.. Types in this section are also parsed by checkpatch.
+.. The types are grouped into subsections based on use.
+
+
+Allocation style
+----------------
+
+ **ALLOC_ARRAY_ARGS**
+ The first argument for kcalloc or kmalloc_array should be the
+ number of elements. sizeof() as the first argument is generally
+ wrong.
+ See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html
+
+ **ALLOC_SIZEOF_STRUCT**
+ The allocation style is bad. In general for family of
+ allocation functions using sizeof() to get memory size,
+ constructs like::
+
+ p = alloc(sizeof(struct foo), ...)
+
+ should be::
+
+ p = alloc(sizeof(*p), ...)
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#allocating-memory
+
+ **ALLOC_WITH_MULTIPLY**
+ Prefer kmalloc_array/kcalloc over kmalloc/kzalloc with a
+ sizeof multiply.
+ See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html
+
+
+API usage
+---------
+
+ **ARCH_DEFINES**
+ Architecture specific defines should be avoided wherever
+ possible.
+
+ **ARCH_INCLUDE_LINUX**
+ Whenever asm/file.h is included and linux/file.h exists, a
+ conversion can be made when linux/file.h includes asm/file.h.
+ However this is not always the case (See signal.h).
+ This message type is emitted only for includes from arch/.
+
+ **AVOID_BUG**
+ BUG() or BUG_ON() should be avoided totally.
+ Use WARN() and WARN_ON() instead, and handle the "impossible"
+ error condition as gracefully as possible.
+ See: https://www.kernel.org/doc/html/latest/process/deprecated.html#bug-and-bug-on
+
+ **CONSIDER_KSTRTO**
+ The simple_strtol(), simple_strtoll(), simple_strtoul(), and
+ simple_strtoull() functions explicitly ignore overflows, which
+ may lead to unexpected results in callers. The respective kstrtol(),
+ kstrtoll(), kstrtoul(), and kstrtoull() functions tend to be the
+ correct replacements.
+ See: https://www.kernel.org/doc/html/latest/process/deprecated.html#simple-strtol-simple-strtoll-simple-strtoul-simple-strtoull
+
+ **LOCKDEP**
+ The lockdep_no_validate class was added as a temporary measure to
+ prevent warnings on conversion of device->sem to device->mutex.
+ It should not be used for any other purpose.
+ See: https://lore.kernel.org/lkml/1268959062.9440.467.camel@laptop/
+
+ **MALFORMED_INCLUDE**
+ The #include statement has a malformed path. This has happened
+ because the author has included a double slash "//" in the pathname
+ accidentally.
+
+ **USE_LOCKDEP**
+ lockdep_assert_held() annotations should be preferred over
+ assertions based on spin_is_locked()
+ See: https://www.kernel.org/doc/html/latest/locking/lockdep-design.html#annotations
+
+ **UAPI_INCLUDE**
+ No #include statements in include/uapi should use a uapi/ path.
+
+
+Comment style
+-------------
+
+ **BLOCK_COMMENT_STYLE**
+ The comment style is incorrect. The preferred style for multi-
+ line comments is::
+
+ /*
+ * This is the preferred style
+ * for multi line comments.
+ */
+
+ The networking comment style is a bit different, with the first line
+ not empty like the former::
+
+ /* This is the preferred comment style
+ * for files in net/ and drivers/net/
+ */
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting
+
+ **C99_COMMENTS**
+ C99 style single line comments (//) should not be used.
+ Prefer the block comment style instead.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting
+
+
+Commit message
+--------------
+
+ **BAD_SIGN_OFF**
+ The signed-off-by line does not fall in line with the standards
+ specified by the community.
+ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1
+
+ **BAD_STABLE_ADDRESS_STYLE**
+ The email format for stable is incorrect.
+ Some valid options for stable address are::
+
+ 1. stable@vger.kernel.org
+ 2. stable@kernel.org
+
+ For adding version info, the following comment style should be used::
+
+ stable@vger.kernel.org # version info
+
+ **COMMIT_COMMENT_SYMBOL**
+ Commit log lines starting with a '#' are ignored by git as
+ comments. To solve this problem addition of a single space
+ infront of the log line is enough.
+
+ **COMMIT_MESSAGE**
+ The patch is missing a commit description. A brief
+ description of the changes made by the patch should be added.
+ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes
+
+ **MISSING_SIGN_OFF**
+ The patch is missing a Signed-off-by line. A signed-off-by
+ line should be added according to Developer's certificate of
+ Origin.
+ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
+
+ **NO_AUTHOR_SIGN_OFF**
+ The author of the patch has not signed off the patch. It is
+ required that a simple sign off line should be present at the
+ end of explanation of the patch to denote that the author has
+ written it or otherwise has the rights to pass it on as an open
+ source patch.
+ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
+
+ **DIFF_IN_COMMIT_MSG**
+ Avoid having diff content in commit message.
+ This causes problems when one tries to apply a file containing both
+ the changelog and the diff because patch(1) tries to apply the diff
+ which it found in the changelog.
+ See: https://lore.kernel.org/lkml/20150611134006.9df79a893e3636019ad2759e@linux-foundation.org/
+
+ **GERRIT_CHANGE_ID**
+ To be picked up by gerrit, the footer of the commit message might
+ have a Change-Id like::
+
+ Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b
+ Signed-off-by: A. U. Thor <author@example.com>
+
+ The Change-Id line must be removed before submitting.
+
+ **GIT_COMMIT_ID**
+ The proper way to reference a commit id is:
+ commit <12+ chars of sha1> ("<title line>")
+
+ An example may be::
+
+ Commit e21d2170f36602ae2708 ("video: remove unnecessary
+ platform_set_drvdata()") removed the unnecessary
+ platform_set_drvdata(), but left the variable "dev" unused,
+ delete it.
+
+ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes
+
+
+Comparison style
+----------------
+
+ **ASSIGN_IN_IF**
+ Do not use assignments in if condition.
+ Example::
+
+ if ((foo = bar(...)) < BAZ) {
+
+ should be written as::
+
+ foo = bar(...);
+ if (foo < BAZ) {
+
+ **BOOL_COMPARISON**
+ Comparisons of A to true and false are better written
+ as A and !A.
+ See: https://lore.kernel.org/lkml/1365563834.27174.12.camel@joe-AO722/
+
+ **COMPARISON_TO_NULL**
+ Comparisons to NULL in the form (foo == NULL) or (foo != NULL)
+ are better written as (!foo) and (foo).
+
+ **CONSTANT_COMPARISON**
+ Comparisons with a constant or upper case identifier on the left
+ side of the test should be avoided.
+
+
+Macros, Attributes and Symbols
+------------------------------
+
+ **ARRAY_SIZE**
+ The ARRAY_SIZE(foo) macro should be preferred over
+ sizeof(foo)/sizeof(foo[0]) for finding number of elements in an
+ array.
+
+ The macro is defined in include/linux/kernel.h::
+
+ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+ **AVOID_EXTERNS**
+ Function prototypes don't need to be declared extern in .h
+ files. It's assumed by the compiler and is unnecessary.
+
+ **AVOID_L_PREFIX**
+ Local symbol names that are prefixed with `.L` should be avoided,
+ as this has special meaning for the assembler; a symbol entry will
+ not be emitted into the symbol table. This can prevent `objtool`
+ from generating correct unwind info.
+
+ Symbols with STB_LOCAL binding may still be used, and `.L` prefixed
+ local symbol names are still generally usable within a function,
+ but `.L` prefixed local symbol names should not be used to denote
+ the beginning or end of code regions via
+ `SYM_CODE_START_LOCAL`/`SYM_CODE_END`
+
+ **BIT_MACRO**
+ Defines like: 1 << <digit> could be BIT(digit).
+ The BIT() macro is defined in include/linux/bitops.h::
+
+ #define BIT(nr) (1UL << (nr))
+
+ **CONST_READ_MOSTLY**
+ When a variable is tagged with the __read_mostly annotation, it is a
+ signal to the compiler that accesses to the variable will be mostly
+ reads and rarely(but NOT never) a write.
+
+ const __read_mostly does not make any sense as const data is already
+ read-only. The __read_mostly annotation thus should be removed.
+
+ **DATE_TIME**
+ It is generally desirable that building the same source code with
+ the same set of tools is reproducible, i.e. the output is always
+ exactly the same.
+
+ The kernel does *not* use the ``__DATE__`` and ``__TIME__`` macros,
+ and enables warnings if they are used as they can lead to
+ non-deterministic builds.
+ See: https://www.kernel.org/doc/html/latest/kbuild/reproducible-builds.html#timestamps
+
+ **DEFINE_ARCH_HAS**
+ The ARCH_HAS_xyz and ARCH_HAVE_xyz patterns are wrong.
+
+ For big conceptual features use Kconfig symbols instead. And for
+ smaller things where we have compatibility fallback functions but
+ want architectures able to override them with optimized ones, we
+ should either use weak functions (appropriate for some cases), or
+ the symbol that protects them should be the same symbol we use.
+ See: https://lore.kernel.org/lkml/CA+55aFycQ9XJvEOsiM3txHL5bjUc8CeKWJNR_H+MiicaddB42Q@mail.gmail.com/
+
+ **INIT_ATTRIBUTE**
+ Const init definitions should use __initconst instead of
+ __initdata.
+
+ Similarly init definitions without const require a separate
+ use of const.
+
+ **INLINE_LOCATION**
+ The inline keyword should sit between storage class and type.
+
+ For example, the following segment::
+
+ inline static int example_function(void)
+ {
+ ...
+ }
+
+ should be::
+
+ static inline int example_function(void)
+ {
+ ...
+ }
+
+ **MULTISTATEMENT_MACRO_USE_DO_WHILE**
+ Macros with multiple statements should be enclosed in a
+ do - while block. Same should also be the case for macros
+ starting with `if` to avoid logic defects::
+
+ #define macrofun(a, b, c) \
+ do { \
+ if (a == 5) \
+ do_this(b, c); \
+ } while (0)
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#macros-enums-and-rtl
+
+ **WEAK_DECLARATION**
+ Using weak declarations like __attribute__((weak)) or __weak
+ can have unintended link defects. Avoid using them.
+
+
+Functions and Variables
+-----------------------
+
+ **CAMELCASE**
+ Avoid CamelCase Identifiers.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#naming
+
+ **FUNCTION_WITHOUT_ARGS**
+ Function declarations without arguments like::
+
+ int foo()
+
+ should be::
+
+ int foo(void)
+
+ **GLOBAL_INITIALISERS**
+ Global variables should not be initialized explicitly to
+ 0 (or NULL, false, etc.). Your compiler (or rather your
+ loader, which is responsible for zeroing out the relevant
+ sections) automatically does it for you.
+
+ **INITIALISED_STATIC**
+ Static variables should not be initialized explicitly to zero.
+ Your compiler (or rather your loader) automatically does
+ it for you.
+
+ **RETURN_PARENTHESES**
+ return is not a function and as such doesn't need parentheses::
+
+ return (bar);
+
+ can simply be::
+
+ return bar;
+
+
+Spacing and Brackets
+--------------------
+
+ **ASSIGNMENT_CONTINUATIONS**
+ Assignment operators should not be written at the start of a
+ line but should follow the operand at the previous line.
+
+ **BRACES**
+ The placement of braces is stylistically incorrect.
+ The preferred way is to put the opening brace last on the line,
+ and put the closing brace first::
+
+ if (x is true) {
+ we do y
+ }
+
+ This applies for all non-functional blocks.
+ However, there is one special case, namely functions: they have the
+ opening brace at the beginning of the next line, thus::
+
+ int function(int x)
+ {
+ body of function
+ }
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces
+
+ **BRACKET_SPACE**
+ Whitespace before opening bracket '[' is prohibited.
+ There are some exceptions:
+
+ 1. With a type on the left::
+
+ ;int [] a;
+
+ 2. At the beginning of a line for slice initialisers::
+
+ [0...10] = 5,
+
+ 3. Inside a curly brace::
+
+ = { [0...10] = 5 }
+
+ **CODE_INDENT**
+ Code indent should use tabs instead of spaces.
+ Outside of comments, documentation and Kconfig,
+ spaces are never used for indentation.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation
+
+ **CONCATENATED_STRING**
+ Concatenated elements should have a space in between.
+ Example::
+
+ printk(KERN_INFO"bar");
+
+ should be::
+
+ printk(KERN_INFO "bar");
+
+ **ELSE_AFTER_BRACE**
+ `else {` should follow the closing block `}` on the same line.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces
+
+ **LINE_SPACING**
+ Vertical space is wasted given the limited number of lines an
+ editor window can display when multiple blank lines are used.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
+
+ **OPEN_BRACE**
+ The opening brace should be following the function definitions on the
+ next line. For any non-functional block it should be on the same line
+ as the last construct.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces
+
+ **POINTER_LOCATION**
+ When using pointer data or a function that returns a pointer type,
+ the preferred use of * is adjacent to the data name or function name
+ and not adjacent to the type name.
+ Examples::
+
+ char *linux_banner;
+ unsigned long long memparse(char *ptr, char **retptr);
+ char *match_strdup(substring_t *s);
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
+
+ **SPACING**
+ Whitespace style used in the kernel sources is described in kernel docs.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
+
+ **SWITCH_CASE_INDENT_LEVEL**
+ switch should be at the same indent as case.
+ Example::
+
+ switch (suffix) {
+ case 'G':
+ case 'g':
+ mem <<= 30;
+ break;
+ case 'M':
+ case 'm':
+ mem <<= 20;
+ break;
+ case 'K':
+ case 'k':
+ mem <<= 10;
+ /* fall through */
+ default:
+ break;
+ }
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation
+
+ **TRAILING_WHITESPACE**
+ Trailing whitespace should always be removed.
+ Some editors highlight the trailing whitespace and cause visual
+ distractions when editing files.
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
+
+ **WHILE_AFTER_BRACE**
+ while should follow the closing bracket on the same line::
+
+ do {
+ ...
+ } while(something);
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces
+
+
+Others
+------
+
+ **CONFIG_DESCRIPTION**
+ Kconfig symbols should have a help text which fully describes
+ it.
+
+ **CORRUPTED_PATCH**
+ The patch seems to be corrupted or lines are wrapped.
+ Please regenerate the patch file before sending it to the maintainer.
+
+ **DOS_LINE_ENDINGS**
+ For DOS-formatted patches, there are extra ^M symbols at the end of
+ the line. These should be removed.
+
+ **EXECUTE_PERMISSIONS**
+ There is no reason for source files to be executable. The executable
+ bit can be removed safely.
+
+ **NON_OCTAL_PERMISSIONS**
+ Permission bits should use 4 digit octal permissions (like 0700 or 0444).
+ Avoid using any other base like decimal.
+
+ **NOT_UNIFIED_DIFF**
+ The patch file does not appear to be in unified-diff format. Please
+ regenerate the patch file before sending it to the maintainer.
+
+ **PRINTF_0XDECIMAL**
+ Prefixing 0x with decimal output is defective and should be corrected.
+
+ **TRAILING_STATEMENTS**
+ Trailing statements (for example after any conditional) should be
+ on the next line.
+ Like::
+
+ if (x == y) break;
+
+ should be::
+
+ if (x == y)
+ break;
static int mmc_of_to_plat(struct udevice *dev)
{
- #if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
/* Decode the devicetree data */
struct mmc_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
- #endif
+ }
- return 0;
+ return 0;
}
static int mmc_probe(struct udevice *dev)
Problems
--------
+This section shows some common problems and how to fix them.
+
+Driver not found
+~~~~~~~~~~~~~~~~
+
In some cases you will you see something like this::
WARNING: the driver rockchip_rk3188_grf was not found in the driver list
then dtoc looks at the first compatible string ("rockchip,rk3188-grf"),
converts that to a C identifier (rockchip_rk3188_grf) and then looks for that.
+Missing .compatible or Missing .id
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
Various things can cause dtoc to fail to find the driver and it tries to
-warn about these. For example:
+warn about these. For example::
rockchip_rk3188_uart: Missing .compatible in drivers/serial/serial_rockchip.c
: WARNING: the driver rockchip_rk3188_uart was not found in the driver list
member and a .id member. The first provides the array of compatible strings and
the second provides the uclass ID.
+Missing parent
+~~~~~~~~~~~~~~
+
+When a device is used, its parent must be present as well. If you see an error
+like::
+
+ Node '/i2c@0/emul/emul0' requires parent node '/i2c@0/emul' but it is not in
+ the valid list
+
+it indicates that you are using a node whose parent is not present in the
+devicetree. In this example, if you look at the device tree output
+(e.g. fdtdump tpl/u-boot-tpl.dtb in your build directory), you may see something
+like this::
+
+ emul {
+ emul0 {
+ compatible = "sandbox,i2c-rtc-emul";
+ #emul-cells = <0x00000000>;
+ phandle = <0x00000003>;
+ };
+ };
+
+In this example, 'emul0' exists but its parent 'emul' has no properties. These
+have been dropped by fdtgrep in an effort to reduce the devicetree size. This
+indicates that the two nodes have different phase settings. Looking at the
+source .dts::
+
+ i2c_emul: emul {
+ u-boot,dm-spl;
+ reg = <0xff>;
+ compatible = "sandbox,i2c-emul-parent";
+ emul0: emul0 {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,i2c-rtc-emul";
+ #emul-cells = <0>;
+ };
+ };
+
+you can see that the child node 'emul0' usees 'u-boot,dm-pre-reloc', indicating
+that the node is present in all SPL builds, but its parent uses 'u-boot,dm-spl'
+indicating it is only present in SPL, not TPL. For a TPL build, this will fail
+with the above message. The fix is to change 'emul0' to use the same
+'u-boot,dm-spl' condition, so that it is not present in TPL, like its parent.
+
+Link errors / undefined reference
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Sometimes dtoc does not find the problem for you, but something is wrong and
+you get a link error, e.g.::
+
+ :(.u_boot_list_2_udevice_2_spl_test5+0x0): undefined reference to
+ `_u_boot_list_2_driver_2_sandbox_spl_test'
+ /usr/bin/ld: dts/dt-uclass.o:(.u_boot_list_2_uclass_2_misc+0x8):
+ undefined reference to `_u_boot_list_2_uclass_driver_2_misc'
+
+The first one indicates that the device cannot find its driver. This means that
+there is a driver 'sandbox_spl_test' but it is not compiled into the build.
+Check your Kconfig settings to make sure it is. If you don't want that in the
+build, adjust your phase settings, e.g. by using 'u-boot,dm-spl' in the node
+to exclude it from the TPL build::
+
+ spl-test5 {
+ u-boot,dm-tpl;
+ compatible = "sandbox,spl-test";
+ stringarray = "tpl";
+ };
+
+We can drop the 'u-boot,dm-tpl' line so this node won't appear in the TPL
+devicetree and thus the driver won't be needed.
+
+The second error above indicates that the MISC uclass is needed by the driver
+(since it is in the MISC uclass) but that uclass is not compiled in the build.
+The fix above would fix this error too. But if you do want this uclass in the
+build, check your Kconfig settings to make sure the uclass is being built
+(CONFIG_MISC in this case).
+
+Another error that can crop up is something like::
+
+ spl/dts/dt-device.c:257:38: error: invalid application of ‘sizeof’ to
+ incomplete type ‘struct sandbox_irq_priv’
+ 257 | u8 _sandbox_irq_priv_irq_sbox[sizeof(struct sandbox_irq_priv)]
+ | ^~~~~~
+
+This indicates that `struct sandbox_irq_priv` is not defined anywhere. The
+solution is to add a DM_HEADER() line, as below, so this is included in the
+dt-device.c file::
+
+ U_BOOT_DRIVER(sandbox_irq) = {
+ .name = "sandbox_irq",
+ .id = UCLASS_IRQ,
+ .of_match = sandbox_irq_ids,
+ .ops = &sandbox_irq_ops,
+ .priv_auto = sizeof(struct sandbox_irq_priv),
+ DM_HEADER(<asm/irq.h>)
+ };
+
+Note that there is no dependency checking on the above, so U-Boot will not
+regenerate the dt-device.c file when you update the source file (here,
+`irq_sandbox.c`). You need to run `make mrproper` first to get a fresh build.
+
+Another error that can crop up is something like::
+
+ spl/dts/dt-device.c:257:38: error: invalid application of ‘sizeof’ to
+ incomplete type ‘struct sandbox_irq_priv’
+ 257 | u8 _sandbox_irq_priv_irq_sbox[sizeof(struct sandbox_irq_priv)]
+ | ^~~~~~
+
+This indicates that `struct sandbox_irq_priv` is not defined anywhere. The
+solution is to add a DM_HEADER() line, as below, so this is included in the
+dt-device.c file::
+
+ U_BOOT_DRIVER(sandbox_irq) = {
+ .name = "sandbox_irq",
+ .id = UCLASS_IRQ,
+ .of_match = sandbox_irq_ids,
+ .ops = &sandbox_irq_ops,
+ .priv_auto = sizeof(struct sandbox_irq_priv),
+ DM_HEADER(<asm/irq.h>)
+ };
+
+Note that there is no dependency checking on the above, so U-Boot will not
+regenerate the dt-device.c file when you update the source file (here,
+`irq_sandbox.c`). You need to run `make mrproper` first to get a fresh build.
+
Caveats
-------
---------
Generated files
-```````````````
+~~~~~~~~~~~~~~~
When enabled, dtoc generates the following five files:
CONFIG options
-``````````````
+~~~~~~~~~~~~~~
Several CONFIG options are used to control the behaviour of of-platdata, all
available for both SPL and TPL:
the nodes cannot be updated, OF_PLATDATA_NO_BIND is enabled.
Data structures
-```````````````
+~~~~~~~~~~~~~~~
A few extra data structures are used with of-platdata:
`device_get_by_ofplat_idx()`.
Other changes
-`````````````
+~~~~~~~~~~~~~
Some other changes are made with of-platdata:
.. toctree::
:maxdepth: 1
+ checkpatch
coccinelle
moveconfig
browser, but may be read directly as plain text, perhaps with the aid of the
`html2text` utility.
+Running tests in parallel
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Note: This does not fully work yet and is documented only so you can try to
+fix the problems.
+
+First install support for parallel tests::
+
+ pip3 install pytest-xdist
+
+Then build sandbox in a suitable build directory. It is not possible to use
+the --build flag with xdist.
+
+Finally, run the tests in parallel using the -n flag::
+
+ # build sandbox first, in a suitable build directory. It is not possible
+ # to use the --build flag with -n
+ test/py/test.py -B sandbox --build-dir /tmp/b/sandbox -q -k 'not slow' -n32
+
+At least the following non-slow tests are known to fail:
+
+- test_fit_ecdsa
+- test_bind_unbind_with_uclass
+- ut_dm_spi_flash
+- test_gpt_rename_partition
+- test_gpt_swap_partitions
+- test_pinmux_status
+- test_sqfs_load
+
+
Testing under a debugger
~~~~~~~~~~~~~~~~~~~~~~~~
This is used as part of the banner string when U-Boot starts.
- U_BOOT_VERSION_STRING (string #define)
- U_BOOT_VERSION followed by build-time information
- and CONFIG_IDENT_STRING.
-
- Examples::
-
- U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700)
- U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring
-
U_BOOT_VERSION_NUM (integer #define)
Release year, e.g. 2021 for release 2021.01. Note
this is an integer, not a string.
Patch number, e.g. 1 for release 2020.01. Note
this is an integer, not a string.
+Human readable U-Boot version string is available in header file
+include/version_string.h in following variable:
+
+ version_string (const char[])
+ U_BOOT_VERSION followed by build-time information
+ and CONFIG_IDENT_STRING.
+
+ Examples::
+
+ U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700)
+ U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring
+
Build date/time is also included. See the generated file
include/generated/timestamp_autogenerated.h for the available
fields. For example::
#define U_BOOT_DATE "Jan 06 2021" (US format only)
#define U_BOOT_TIME "08:50:36" (24-hour clock)
#define U_BOOT_TZ "-0700" (Time zone in hours)
- #define U_BOOT_BUILD_DATE 0x20210106 (hex yyyymmdd format)
#define U_BOOT_EPOCH 1609948236
The Epoch is the number of seconds since midnight on 1/1/70. You can convert
----------------------------------------
A number of run-time configuration options are provided in the /config node
-of the control device tree. You can access these using fdtdec_get_config_int(),
-fdtdec_get_config_bool() and fdtdec_get_config_string().
+of the control device tree. You can access these using ofnode_conf_read_int(),
+ofnode_conf_read_bool() and ofnode_conf_read_str().
These options are designed to affect the operation of U-Boot at runtime.
Runtime-configuration items can help avoid proliferation of different builds
in drivers/tee/optee/optee_smc.h
-
Example:
firmware {
optee {
Required properties:
--------------------
- compatible: Shall be: "ti,am654-secure-proxy"
-- reg-names data - Map the data region
+- reg-names data - Map the data region
scfg - Map the secure configuration region
rt - Map the Realtime region.
- reg: Contains the register map per reg-names.
--------------------
- compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200
"ti,am64-ddrss" for am642
-- reg-names cfg - Map the controller configuration region
+- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
- reg: Contains the register map per reg-names.
- power-domains: Should contain two entries:
Required properties:
--------------------
- compatible: Shall be: "ti,am654-ddrss"
-- reg-names ss - Map the sub system wrapper logic region
+- reg-names ss - Map the sub system wrapper logic region
ctl - Map the controller region
phy - Map the PHY region
- reg: Contains the register map per reg-names.
clock-names = "biu", "ciu";
max-frequency = <25000000>;
};
-
tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
compatible = "altr,tse-msgdma-1.0";
- reg = <0x00000001 0x00001000 0x00000400>,
+ reg = <0x00000001 0x00001000 0x00000400>,
<0x00000001 0x00001460 0x00000020>,
<0x00000001 0x00001480 0x00000020>,
<0x00000001 0x000014A0 0x00000008>,
* "2500base-x",
* "rxaui"
* "xaui"
- * "10gbase-kr" (10GBASE-KR, XFI, SFI)
+ * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol
+ used with various different mediums. Please refer to the IEEE standard for
+ a definition of this. Note: 10GBASE-R is just one protocol that can be used
+ with XFI and SFI. XFI and SFI permit multiple protocols over a single
+ SERDES lane, and also defines the electrical characteristics of the signals
+ with a host compliance board plugged into the host XFP/SFP connector.
+ Therefore, XFI and SFI are not PHY interface types in their own right.)
+ * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with
+ Clause 73 autonegotiation. Please refer to the IEEE standard for further
+ information. Note: due to legacy usage, some 10GBASE-R usage incorrectly
+ makes use of this definition).
- phy-connection-type: the same as "phy-mode" property but described in the
Devicetree Specification;
- phy-handle: phandle, specifies a reference to a node representing a PHY
fec0: ethernet@9000 {
compatible = "fsl,mcf-dma-fec";
- reg = <0x9000 0x800>;
+ reg = <0x9000 0x800>;
mii-base = <0>;
phy-addr = <0>;
timeout-loop = <5000>;
fec0: ethernet@fc030000 {
compatible = "fsl,mcf-fec";
- reg = <0xfc030000 0x400>;
+ reg = <0xfc030000 0x400>;
mii-base = <0>;
phy-addr = <0>;
timeout-loop = <5000>;
Required properties for the pinctrl driver:
- compatible: "brcm,bcm6838-pinctrl"
-- regmap: specify the gpio test port syscon
+- regmap: specify the gpio test port syscon
- brcm,pins-count: the number of pin
- brcm,functions-count: the number of function
----------------------------------------------------------------------
MPP# 0x1 0x2 0x3 0x4
----------------------------------------------------------------------
-0 SDIO_CLK - SPI0_CLK -
+0 SDIO_CLK - SPI0_CLK -
1 SDIO_CMD - SPI0_MISO -
-2 SDIO_D[0] - SPI0_MOSI -
-3 SDIO_D[1] - SPI0_CS0n -
+2 SDIO_D[0] - SPI0_MOSI -
+3 SDIO_D[1] - SPI0_CS0n -
4 SDIO_D[2] - I2C0_SDA SPI0_CS1n
5 SDIO_D[3] - I2C0_SCK -
6 SDIO_DS - - -
7 SDIO_D[4] - UART1_RXD -
-8 SDIO_D[5] - UART1_TXD -
-9 SDIO_D[6] - SPI0_CS1n -
+8 SDIO_D[5] - UART1_TXD -
+9 SDIO_D[6] - SPI0_CS1n -
10 SDIO_D[7] - - -
-11 - - UART0_TXD -
-12 SDIO_CARD_PW_OFF SDIO_HW_RST - -
+11 - - UART0_TXD -
+12 SDIO_CARD_PW_OFF SDIO_HW_RST - -
13 - - - -
14 - - - -
15 - - - -
"marvell,armada-8k-cpm-pinctrl",
"marvell,armada-8k-cps-pinctrl"
- bank-name: A string defining the pinc controller bank name
-- reg: A pair of values defining the pin controller base address
+- reg: A pair of values defining the pin controller base address
and the address space
- pin-count: Numeric value defining the amount of multi purpose pins
included in this bank
--- /dev/null
+Microchip AT91 PWM controller for SAMA5D2
+
+Required properties:
+ - compatible: Should be "atmel,sama5d2-pwm"
+ - reg: Physical base address and length of the controller's registers.
+ - clocks: Should contain a clock identifier for the PWM's parent clock.
+ - #pwm-cells: Should be 3.
+
+Example:
+
+pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+};
- anatop-reg-offset: u32 value representing the anatop MFD register offset.
- anatop-vol-bit-shift: u32 value representing the bit shift for the register.
- anatop-vol-bit-width: u32 value representing the number of bits used in the
- register.
+ register.
- anatop-min-bit-val: u32 value representing the minimum value of this
- register.
+ register.
- anatop-min-voltage: u32 value representing the minimum voltage of this
- regulator.
+ regulator.
- anatop-max-voltage: u32 value representing the maximum voltage of this
- regulator.
+ regulator.
Optional properties:
- anatop-delay-reg-offset: u32 value representing the anatop MFD step time
- register offset.
+ register offset.
- anatop-delay-bit-shift: u32 value representing the bit shift for the step
- time register.
+ time register.
- anatop-delay-bit-width: u32 value representing the number of bits used in
- the step time register.
+ the step time register.
- anatop-enable-bit: u32 value representing regulator enable bit offset.
- vin-supply: input supply phandle.
The SPI master node requires the following properties:
- #address-cells - number of cells required to define a chip select
- address on the SPI bus.
+ address on the SPI bus.
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
- recommended practice.
+ recommended practice.
- cs-gpios - (optional) gpios chip select.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
contain the following properties.
- reg - (required) chip select address of device.
- compatible - (required) name of SPI device following generic names
- recommended practice
+ recommended practice
- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
- spi-cpol - (optional) Empty property indicating device requires
- inverse clock polarity (CPOL) mode
+ inverse clock polarity (CPOL) mode
- spi-cpha - (optional) Empty property indicating device requires
- shifted clock phase (CPHA) mode
+ shifted clock phase (CPHA) mode
- spi-cs-high - (optional) Empty property indicating device requires
- chip select active high
+ chip select active high
- spi-3wire - (optional) Empty property indicating device requires
- 3-wire mode.
+ 3-wire mode.
- spi-tx-bus-width - (optional) The bus width(number of data wires) that
used for MOSI. Defaults to 1 if not present.
- spi-rx-bus-width - (optional) The bus width(number of data wires) that
- reg : Physical base address and size of SPI registers map.
- clock : Clock phandle (see clock bindings for details).
- #address-cells : Number of cells required to define a chip select
- address on the SPI bus. Should be set to 1.
+ address on the SPI bus. Should be set to 1.
- #size-cells : Should be zero.
- pinctrl-names : Must be "default"
- pinctrl-n : At least one pinctrl phandle
Example:
tpm {
- compatible = "sandbox,tpm2";
+ compatible = "sandbox,tpm2";
};
- reg : SPI Chip select
Optional properties:
-- gpio-reset : Reset GPIO (if not connected to the SoC reset line)
+- reset-gpios : Reset GPIO (if not connected to the SoC reset line)
+- gpio-reset : Reset GPIO (deprecated, use reset-gpios instead)
- spi-max-frequency : See spi-bus.txt
Example:
compatible = "maxim,ds24xxx";
}
};
-
compatible = "maxim,ds2502";
};
};
-
compatible = "sandbox,w1-eeprom";
}
};
-
compatible = "maxim,ds24xxx";
}
};
-
--- /dev/null
+GPIO watchdog timer
+
+Describes a simple watchdog timer which is reset by toggling a gpio.
+
+Required properties:
+
+- compatible: Must be "linux,wdt-gpio".
+- gpios: gpio to toggle when wdt driver reset method is called.
+- always-running: Boolean property indicating that the watchdog cannot
+ be disabled. At present, U-Boot only supports this kind of GPIO
+ watchdog.
+
+Example:
+
+ gpio-wdt {
+ gpios = <&gpio0 1 0>;
+ compatible = "linux,wdt-gpio";
+ always-running;
+ };
+++ /dev/null
-U-Boot for Freescale i.MX25
-
-This file contains information for the port of U-Boot to the Freescale i.MX25
-SoC.
-
-1. CONVENTIONS FOR FUSE ASSIGNMENTS
------------------------------------
-
-1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the
- natural MAC byte order (i.e. MSB first).
1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
16 msbs in word 3[15:0].
For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address
- is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in
+ is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in
word 4.
Example:
-.TH KWBOOT 1 "2012-05-19"
+.TH KWBOOT 1 "2021-08-25"
.SH NAME
-kwboot \- Boot Marvell Kirkwood SoCs over a serial link.
+kwboot \- Boot Marvell Kirkwood (and others 32-bit) SoCs over a serial link.
.SH SYNOPSIS
.B kwboot
.RB [ "-b \fIimage\fP" ]
-.RB [ "-p" ]
.RB [ "-t" ]
.RB [ "-B \fIbaudrate\fP" ]
.RB \fITTY\fP
.SH "DESCRIPTION"
-The \fBmkimage\fP program boots boards based on Marvell's Kirkwood
-platform over their integrated UART. Boot image files will typically
+The \fBkwboot\fP program boots boards based on Marvell's 32-bit
+platforms including Kirkwood, Dove, A370, AXP, A375, A38x
+and A39x over their integrated UART. Boot image files will typically
contain a second stage boot loader, such as U-Boot. The image file
must conform to Marvell's BootROM firmware image format
-(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP.
+(\fIkwbimage v0\fP or \fIv1\fP), created using a tool such as
+\fBmkimage\fP.
Following power-up or a system reset, system BootROM code polls the
UART for a brief period of time, sensing a handshake message which
Handshake; then upload file \fIimage\fP over \fITTY\fP.
Note that for the encapsulated boot code to be executed, \fIimage\fP
-must be of type "UART boot" (0x69). Boot images of different types,
-such as backup images of vendor firmware downloaded from flash memory
-(type 0x8B), will not work (or not as expected). See \fB-p\fP for a
-workaround.
+must be of type "UART boot" (0x69). The \fBkwboot\fP program changes
+this type automatically, unless the \fIimage\fP is signed, in which
+case it cannot be changed.
This mode writes handshake status and upload progress indication to
-stdout.
+stdout. It is possible that \fIimage\fP contains an optional binary
+code in it's header which may also print some output via UART (for
+example U-Boot SPL does this). In such a case, this output is also
+written to stdout after the header is sent.
.TP
.BI "\-p"
-In combination with \fB-b\fP, patches the header in \fIimage\fP prior
-to upload, to "UART boot" type.
+Obsolete. Does nothing.
-This option attempts on-the-fly conversion of some none-UART image
-types, such as images which were originally formatted to be stored in
-flash memory.
-
-Conversion is performed in memory. The contents of \fIimage\fP will
-not be altered.
+In the past, when this option was used, the program patched the header
+in the image prior upload, to "UART boot" type. This is now done by
+default.
.TP
.BI "\-t"
immediately following a successful image upload.
If standard I/O streams connect to a console, this mode will terminate
-after receiving 'ctrl-\\' followed by 'c' from console input.
+after receiving \fBctrl-\e\fP followed by \fBc\fP from console input.
.TP
.BI "\-B \fIbaudrate\fP"
-Adjust the baud rate on \fITTY\fP. Default rate is 115200.
+If used in combination with \fB-b\fP, inject into the image header
+code that changes baud rate to \fIbaudrate\fP after uploading image
+header, and code that changes the baud rate back to the default
+(115200 Bd) before executing payload, and also adjust the baud rate
+on \fITTY\fP correspondingly. This can make the upload significantly
+faster.
+
+If used in combination with \fB-t\fP, adjust the baud rate to
+\fIbaudrate\fP on \fITTY\fP before starting terminal.
+
+If both \fB-b\fP and \fB-t\fP are used, the baud rate is changed
+back to 115200 after the upload.
+
+Tested values for \fIbaudrate\fP for Armada 38x include: 115200,
+230400, 460800, 500000, 576000, 921600, 1000000, 1152000, 1500000,
+2000000, 2500000, 3125000, 4000000 and 5200000.
.SH "SEE ALSO"
.PP
Luka Perkov <luka@openwrt.org>
.br
David Purdy <david.c.purdy@gmail.com>
+.br
+Pali Rohár <pali@kernel.org>
+.br
+Marek Behún <marek.behun@nic.cz>
0xFFF00000 0xFFFFFFFF Bootrom
0x100000000 <DRAM Size>-1 DRAM
-
- NAND: # nand write <load_address> 0 <ATF Size>
- SPI: # sf write <load_address> 0 <ATF Size>
- SD/eMMC: # mmc write <load_address> [0|1] <ATF Size>/<block_size>
-
kernel_addr
address to which the file specified by the -kernel parameter of QEMU shall
be loaded. Defaults to environment variable *loadaddr* and further to
- the value of *CONFIG_LOADADDR*.
+ the value of *CONFIG_SYS_LOAD_ADDR*.
initrd_addr
address to which the file specified by the -initrd parameter of QEMU shall
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
obj-$(CONFIG_$(SPL_TPL_)DM) += core/
+obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/
+obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/
obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/
obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/
obj-$(CONFIG_$(SPL_TPL_)I2C) += i2c/
obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/
obj-$(CONFIG_$(SPL_TPL_)LED) += led/
-obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/
+obj-$(CONFIG_$(SPL_TPL_)MMC) += mmc/
obj-y += mtd/
obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux/
-obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/
+obj-$(CONFIG_$(SPL_TPL_)ETH) += net/
+obj-$(CONFIG_$(SPL_TPL_)PCH) += pch/
obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/
obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/
obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/
+obj-$(CONFIG_$(SPL_TPL_)POWER) += power/
obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/
-obj-$(CONFIG_$(SPL_TPL_)RTC_SUPPORT) += rtc/
-obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
+obj-$(CONFIG_$(SPL_TPL_)RTC) += rtc/
+obj-$(CONFIG_$(SPL_TPL_)SERIAL) += serial/
+obj-$(CONFIG_$(SPL_TPL_)SPI) += spi/
obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/
obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/
obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
-obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/
obj-$(CONFIG_XEN) += xen/
obj-$(CONFIG_$(SPL_)FPGA) += fpga/
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
-obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/
obj-$(CONFIG_SPL_CPU) += cpu/
obj-$(CONFIG_SPL_CRYPTO) += crypto/
-obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
+obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
-obj-$(CONFIG_SPL_POWER) += power/ power/pmic/
-obj-$(CONFIG_SPL_POWER) += power/regulator/
-obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
obj-$(CONFIG_SPL_DM_RESET) += reset/
-obj-$(CONFIG_SPL_DMA) += dma/
-obj-$(CONFIG_SPL_ETH) += net/
-obj-$(CONFIG_SPL_ETH) += net/phy/
-obj-$(CONFIG_SPL_USB_ETHER) += net/phy/
obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
obj-$(CONFIG_SPL_USB_HOST) += usb/host/
obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
-obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
+obj-$(CONFIG_SPL_SATA) += ata/ scsi/
obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/
obj-$(CONFIG_SPL_THERMAL) += thermal/
ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_TPL_BOOTCOUNT_LIMIT) += bootcount/
-obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
+obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/
endif
obj-$(CONFIG_DM_DEMO) += demo/
obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
-obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
config AHCI_PCI
bool "Support for PCI-based AHCI controller"
+ depends on PCI
depends on DM_SCSI
help
Enables support for the PCI-based AHCI controller.
+config SPL_AHCI_PCI
+ bool "Support for PCI-based AHCI controller for SPL"
+ depends on SPL
+ depends on SPL_PCI
+ depends on SPL_SATA_SUPPORT && DM_SCSI
+
config SATA_CEVA
bool "Ceva Sata controller"
depends on AHCI
obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
obj-$(CONFIG_AHCI) += ahci-uclass.o
-obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
+obj-$(CONFIG_$(SPL_)AHCI_PCI) += ahci-pci.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
.post_bind = dm_scan_fdt_dev,
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
-
config SPL_BLOCK_CACHE
bool "Use block device cache in SPL"
depends on SPL_BLK
- default n
help
This option enables the disk-block cache in SPL
config TPL_BLOCK_CACHE
bool "Use block device cache in TPL"
depends on TPL_BLK
- default n
help
This option enables the disk-block cache in TPL
struct l2cache *regs;
u32 iprefetch;
u32 dprefetch;
- u32 tram_ctl[2];
- u32 dram_ctl[2];
+ u32 tram_ctl[2];
+ u32 dram_ctl[2];
};
static int v5l2_enable(struct udevice *dev)
static const struct cache_ops sandbox_cache_ops = {
.get_info = sandbox_get_info,
- .enable = sandbox_enable,
+ .enable = sandbox_enable,
.disable = snadbox_disable,
};
#include <asm/processor.h>
#include <clk-uclass.h>
#include <common.h>
+#include <div64.h>
#include <dm.h>
#include <linux/clk-provider.h>
#include <linux/clk/at91_pmc.h>
#include "pmc.h"
-#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk"
+#define UBOOT_DM_CLK_AT91_MASTER_PRES "at91-master-clk-pres"
+#define UBOOT_DM_CLK_AT91_MASTER_DIV "at91-master-clk-div"
#define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk"
#define MASTER_PRES_MASK 0x7
return 0;
}
-static ulong clk_master_get_rate(struct clk *clk)
+static ulong clk_master_pres_get_rate(struct clk *clk)
{
struct clk_master *master = to_clk_master(clk);
const struct clk_master_layout *layout = master->layout;
master->characteristics;
ulong rate = clk_get_parent_rate(clk);
unsigned int mckr;
- u8 pres, div;
+ u8 pres;
if (!rate)
return 0;
mckr &= layout->mask;
pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
- div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
- rate /= 3;
+ pres = 3;
else
- rate >>= pres;
-
- rate /= characteristics->divisors[div];
-
- if (rate < characteristics->output.min)
- pr_warn("master clk is underclocked");
- else if (rate > characteristics->output.max)
- pr_warn("master clk is overclocked");
+ pres = (1 << pres);
- return rate;
+ return DIV_ROUND_CLOSEST_ULL(rate, pres);
}
-static const struct clk_ops master_ops = {
+static const struct clk_ops master_pres_ops = {
.enable = clk_master_enable,
- .get_rate = clk_master_get_rate,
+ .get_rate = clk_master_pres_get_rate,
};
-struct clk *at91_clk_register_master(void __iomem *base,
+struct clk *at91_clk_register_master_pres(void __iomem *base,
const char *name, const char * const *parent_names,
int num_parents, const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics,
pmc_read(master->base, master->layout->offset, &val);
clk = &master->clk;
clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
- ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name,
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_PRES, name,
parent_names[val & AT91_PMC_CSS]);
if (ret) {
kfree(master);
return clk;
}
-U_BOOT_DRIVER(at91_master_clk) = {
- .name = UBOOT_DM_CLK_AT91_MASTER,
+U_BOOT_DRIVER(at91_master_pres_clk) = {
+ .name = UBOOT_DM_CLK_AT91_MASTER_PRES,
+ .id = UCLASS_CLK,
+ .ops = &master_pres_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static ulong clk_master_div_get_rate(struct clk *clk)
+{
+ struct clk_master *master = to_clk_master(clk);
+ const struct clk_master_layout *layout = master->layout;
+ const struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ ulong rate = clk_get_parent_rate(clk);
+ unsigned int mckr;
+ u8 div;
+
+ if (!rate)
+ return 0;
+
+ pmc_read(master->base, master->layout->offset, &mckr);
+ mckr &= layout->mask;
+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
+
+ rate = DIV_ROUND_CLOSEST_ULL(rate, characteristics->divisors[div]);
+ if (rate < characteristics->output.min)
+ pr_warn("master clk is underclocked");
+ else if (rate > characteristics->output.max)
+ pr_warn("master clk is overclocked");
+
+ return rate;
+}
+
+static const struct clk_ops master_div_ops = {
+ .enable = clk_master_enable,
+ .get_rate = clk_master_div_get_rate,
+};
+
+struct clk *at91_clk_register_master_div(void __iomem *base,
+ const char *name, const char *parent_name,
+ const struct clk_master_layout *layout,
+ const struct clk_master_characteristics *characteristics)
+{
+ struct clk_master *master;
+ struct clk *clk;
+ int ret;
+
+ if (!base || !name || !parent_name || !layout || !characteristics)
+ return ERR_PTR(-EINVAL);
+
+ master = kzalloc(sizeof(*master), GFP_KERNEL);
+ if (!master)
+ return ERR_PTR(-ENOMEM);
+
+ master->layout = layout;
+ master->characteristics = characteristics;
+ master->base = base;
+ master->num_parents = 1;
+
+ clk = &master->clk;
+ clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_DIV, name,
+ parent_name);
+ if (ret) {
+ kfree(master);
+ clk = ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(at91_master_div_clk) = {
+ .name = UBOOT_DM_CLK_AT91_MASTER_DIV,
.id = UCLASS_CLK,
- .ops = &master_ops,
+ .ops = &master_div_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.ops = &sam9x60_frac_pll_ops,
.flags = DM_FLAG_PRE_RELOC,
};
-
const struct clk_pll_characteristics *characteristics,
const struct clk_pll_layout *layout, bool critical);
struct clk *
-at91_clk_register_master(void __iomem *base, const char *name,
+at91_clk_register_master_pres(void __iomem *base, const char *name,
const char * const *parent_names, int num_parents,
const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics,
const u32 *mux_table);
struct clk *
+at91_clk_register_master_div(void __iomem *base,
+ const char *name, const char *parent_name,
+ const struct clk_master_layout *layout,
+ const struct clk_master_characteristics *characteristics);
+struct clk *
at91_clk_sama7g5_register_master(void __iomem *base, const char *name,
const char * const *parent_names, int num_parents,
const u32 *mux_table, const u32 *clk_mux_table,
* @ID_PLL_A_FRAC: APLL fractional clock identifier
* @ID_PLL_A_DIV: APLL divider clock identifier
- * @ID_MCK: MCK clock identifier
+ * @ID_MCK_DIV: MCK DIV clock identifier
* @ID_UTMI: UTMI clock identifier
* @ID_DDR: DDR system clock identifier
* @ID_QSPI: QSPI system clock identifier
*
+ * @ID_MCK_PRES: MCK PRES clock identifier
+ *
* Note: if changing the values of this enums please sync them with
* device tree
*/
ID_PLL_A_FRAC = 9,
ID_PLL_A_DIV = 10,
- ID_MCK = 11,
+ ID_MCK_DIV = 11,
ID_UTMI = 12,
ID_DDR = 17,
ID_QSPI = 18,
+ ID_MCK_PRES = 19,
+
ID_MAX,
};
[ID_MAINCK] = "mainck",
[ID_PLL_U_DIV] = "upll_divpmcck",
[ID_PLL_A_DIV] = "plla_divpmcck",
- [ID_MCK] = "mck",
+ [ID_MCK_PRES] = "mck_pres",
+ [ID_MCK_DIV] = "mck_div",
};
/* Fractional PLL output range. */
u8 id;
u8 cid;
} sam9x60_systemck[] = {
- { .n = "ddrck", .p = "mck", .id = 2, .cid = ID_DDR, },
+ { .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, },
{ .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, },
{ .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, },
- { .n = "qspick", .p = "mck", .id = 19, .cid = ID_QSPI, },
+ { .n = "qspick", .p = "mck_pres", .id = 19, .cid = ID_QSPI, },
};
/**
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c);
}
- /* Register MCK clock. */
+ /* Register MCK pres clock. */
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_MAINCK];
p[2] = clk_names[ID_PLL_A_DIV];
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4,
fail);
- c = at91_clk_register_master(base, clk_names[ID_MCK], p, 4, &mck_layout,
- &mck_characteristics, tmpclkmux);
+ c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4,
+ &mck_layout, &mck_characteristics,
+ tmpclkmux);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c);
+
+ /* Register MCK div clock. */
+ c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV],
+ clk_names[ID_MCK_PRES],
+ &mck_layout, &mck_characteristics);
if (IS_ERR(c)) {
ret = PTR_ERR(c);
goto fail;
}
- clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK), c);
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c);
/* Register programmable clocks. */
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_TD_SLCK];
p[2] = clk_names[ID_MAINCK];
- p[3] = clk_names[ID_MCK];
+ p[3] = clk_names[ID_MCK_DIV];
p[4] = clk_names[ID_PLL_A_DIV];
p[5] = clk_names[ID_PLL_U_DIV];
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) {
for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout,
sam9x60_periphck[i].n,
- clk_names[ID_MCK],
+ clk_names[ID_MCK_DIV],
sam9x60_periphck[i].id,
&r);
if (IS_ERR(c)) {
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_TD_SLCK];
p[2] = clk_names[ID_MAINCK];
- p[3] = clk_names[ID_MCK];
+ p[3] = clk_names[ID_MCK_DIV];
p[4] = clk_names[ID_PLL_A_DIV];
p[5] = clk_names[ID_PLL_U_DIV];
m[0] = 0;
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
* @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier
* @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier
- * @ID_MCK0: MCK0 clock identifier
+ * @ID_MCK0_PRES: MCK0 PRES clock identifier
+ * @ID_MCK0_DIV: MCK0 DIV clock identifier
* @ID_MCK1: MCK1 clock identifier
* @ID_MCK2: MCK2 clock identifier
* @ID_MCK3: MCK3 clock identifier
ID_PLL_ETH_FRAC = 20,
ID_PLL_ETH_DIV = 21,
- ID_MCK0 = 22,
+ ID_MCK0_DIV = 22,
ID_MCK1 = 23,
ID_MCK2 = 24,
ID_MCK3 = 25,
ID_PCK6 = 42,
ID_PCK7 = 43,
+ ID_MCK0_PRES = 44,
+
ID_MAX,
};
[ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck",
[ID_PLL_AUDIO_DIVIO] = "audiopll_diviock",
[ID_PLL_ETH_DIV] = "ethpll_divpmcck",
- [ID_MCK0] = "mck0",
+ [ID_MCK0_DIV] = "mck0_div",
+ [ID_MCK0_PRES] = "mck0_pres",
};
/* Fractional PLL output range. */
struct clk_range r;
u8 id;
} sama7g5_periphck[] = {
- { .n = "pioA_clk", .p = "mck0", .id = 11, },
+ { .n = "pioA_clk", .p = "mck0_div", .id = 11, },
{ .n = "sfr_clk", .p = "mck1", .id = 19, },
{ .n = "hsmc_clk", .p = "mck1", .id = 21, },
{ .n = "xdmac0_clk", .p = "mck1", .id = 22, },
{ .n = "aes_clk", .p = "mck1", .id = 27, },
{ .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
{ .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
- { .n = "cpkcc_clk", .p = "mck0", .id = 32, },
+ { .n = "cpkcc_clk", .p = "mck0_div", .id = 32, },
{ .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, },
{ .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, },
{ .n = "eic_clk", .p = "mck1", .id = 37, },
sama7g5_plls[i].c));
}
- /* Register MCK0 clock. */
+ /* Register MCK0_PRES clock. */
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_MAINCK];
p[2] = clk_names[ID_PLL_CPU_DIV];
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV);
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
fail);
- clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0),
- at91_clk_register_master(base, clk_names[ID_MCK0], p,
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES),
+ at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], p,
4, &mck0_layout, &mck0_characteristics, tmpclkmux));
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV),
+ at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV],
+ clk_names[ID_MCK0_PRES], &mck0_layout, &mck0_characteristics));
+
/* Register MCK1-4 clocks. */
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_TD_SLCK];
p[2] = clk_names[ID_MAINCK];
- p[3] = clk_names[ID_MCK0];
+ p[3] = clk_names[ID_MCK0_DIV];
m[0] = 0;
m[1] = 1;
m[2] = 2;
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
p[4 + j] = sama7g5_mckx[i].ep[j];
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_TD_SLCK];
p[2] = clk_names[ID_MAINCK];
- p[3] = clk_names[ID_MCK0];
+ p[3] = clk_names[ID_MCK0_DIV];
p[4] = clk_names[ID_PLL_SYS_DIV];
p[5] = clk_names[ID_PLL_DDR_DIV];
p[6] = clk_names[ID_PLL_IMG_DIV];
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV);
cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_DDR_DIV);
cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_IMG_DIV);
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_TD_SLCK];
p[2] = clk_names[ID_MAINCK];
- p[3] = clk_names[ID_MCK0];
+ p[3] = clk_names[ID_MCK0_DIV];
m[0] = 0;
m[1] = 1;
m[2] = 2;
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
for (j = 0; j < sama7g5_gck[i].ep_count; j++) {
p[4 + j] = sama7g5_gck[i].ep[j];
return (struct clk *)dev_get_uclass_priv(dev);
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-# if CONFIG_IS_ENABLED(OF_PLATDATA)
-int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells,
- struct clk *clk)
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells,
+ struct clk *clk)
{
int ret;
return 0;
}
-# else
+#endif
+
+#if CONFIG_IS_ENABLED(OF_REAL)
static int clk_of_xlate_default(struct clk *clk,
struct ofnode_phandle_args *args)
{
return clk_get_by_index(dev, index, clk);
}
-# endif /* OF_PLATDATA */
+#endif /* OF_REAL */
int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
{
return 0;
}
-#endif /* OF_CONTROL */
-
int clk_request(struct udevice *dev, struct clk *clk)
{
const struct clk_ops *ops;
static int clk_fixed_factor_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- int err;
- struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ int err;
+ struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
- err = clk_get_by_index(dev, 0, &ff->parent);
- if (err)
- return err;
+ err = clk_get_by_index(dev, 0, &ff->parent);
+ if (err)
+ return err;
- ff->div = dev_read_u32_default(dev, "clock-div", 1);
- ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
-#endif
+ ff->div = dev_read_u32_default(dev, "clock-div", 1);
+ ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+ }
return 0;
}
struct clk_fixed_rate *plat)
{
struct clk *clk = &plat->clk;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0);
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL))
+ plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency",
+ 0);
+
/* Make fixed rate clock accessible from higher level struct clk */
/* FIXME: This is not allowed */
dev_set_uclass_priv(dev, clk);
* Whether we swapped r and od while enforcing frequency limits
*/
bool swapped = false;
+ /*
+ * Whether the intermediate frequencies are out-of-spec
+ */
+ bool out_of_spec;
u64 last_od = od;
u64 last_r = r;
* aren't in spec, try swapping r and od. If everything is
* in-spec, calculate the relative error.
*/
- while (true) {
+again:
+ out_of_spec = false;
+ if (r > max_r) {
+ out_of_spec = true;
+ } else {
/*
- * Whether the intermediate frequencies are out-of-spec
+ * There is no way to only divide once; we need
+ * to examine the frequency with and without the
+ * effect of od.
*/
- bool out_of_spec = false;
+ u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
- if (r > max_r) {
+ if (vco > 1750000000 || vco < 340000000)
out_of_spec = true;
- } else {
- /*
- * There is no way to only divide once; we need
- * to examine the frequency with and without the
- * effect of od.
- */
- u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+ }
+
+ if (out_of_spec) {
+ u64 new_r, new_od;
+
+ if (!swapped) {
+ u64 tmp = r;
- if (vco > 1750000000 || vco < 340000000)
- out_of_spec = true;
+ r = od;
+ od = tmp;
+ swapped = true;
+ goto again;
}
- if (out_of_spec) {
- if (!swapped) {
- u64 tmp = r;
-
- r = od;
- od = tmp;
- swapped = true;
- continue;
- } else {
- /*
- * Try looking ahead to see if there are
- * additional factors for the same
- * product.
- */
- if (i + 1 < ARRAY_SIZE(factors)) {
- u64 new_r, new_od;
-
- i++;
- new_r = UNPACK_R(factors[i]);
- new_od = UNPACK_OD(factors[i]);
- if (r * od == new_r * new_od) {
- r = new_r;
- od = new_od;
- swapped = false;
- continue;
- }
- i--;
+ /*
+ * Try looking ahead to see if there are additional
+ * factors for the same product.
+ */
+ if (i + 1 < ARRAY_SIZE(factors)) {
+ i++;
+ new_r = UNPACK_R(factors[i]);
+ new_od = UNPACK_OD(factors[i]);
+ if (r * od == new_r * new_od) {
+ r = new_r;
+ od = new_od;
+ swapped = false;
+ goto again;
+ }
+ i--;
+ }
+
+ /*
+ * Try looking back to see if there is a worse ratio
+ * that we could try anyway
+ */
+ while (i > 0) {
+ i--;
+ new_r = UNPACK_R(factors[i]);
+ new_od = UNPACK_OD(factors[i]);
+ /*
+ * Don't loop over factors for the same product
+ * to avoid getting stuck because of the above
+ * clause
+ */
+ if (r * od != new_r * new_od) {
+ if (new_r * new_od > last_r * last_od) {
+ r = new_r;
+ od = new_od;
+ swapped = false;
+ goto again;
}
break;
}
}
- error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
- /* The lower 16 bits are spurious */
- error = abs((error - BIT(32))) >> 16;
+ /* We ran out of things to try */
+ continue;
+ }
- if (error < best_error) {
- best->r = r;
- best->f = f;
- best->od = od;
- best_error = error;
- }
- break;
+ error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
+ /* The lower 16 bits are spurious */
+ error = abs((error - BIT(32))) >> 16;
+
+ if (error < best_error) {
+ best->r = r;
+ best->f = f;
+ best->od = od;
+ best_error = error;
}
} while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
+ log_debug("best error %lld\n", best_error);
if (best_error == S64_MAX)
return -EINVAL;
- log_debug("best error %lld\n", best_error);
return 0;
}
u32 reg;
ulong calc_rate;
- if (rate_in < 0)
- return rate_in;
-
err = k210_pll_calc_config(rate, rate_in, &config);
if (err)
return err;
u64 r, f, od;
u32 reg = readl(priv->base + k210_plls[id].off);
- if (rate_in < 0 || (reg & K210_PLL_BYPASS))
+ if (reg & K210_PLL_BYPASS)
return rate_in;
if (!(reg & K210_PLL_PWRD))
parent = k210_clk_get_parent(priv, id);
parent_rate = do_k210_clk_get_rate(priv, parent);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
if (k210_clks[id].flags & K210_CLKF_PLL)
return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate);
parent = k210_clk_get_parent(priv, clk->id);
rate_in = do_k210_clk_get_rate(priv, parent);
+ if (IS_ERR_VALUE(rate_in))
+ return rate_in;
log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in);
clk_id = priv->clk[clk->id].clk_id;
- return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+ if (versal_clock_gate(clk_id))
+ return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+
+ return 0;
}
static struct clk_ops versal_clk_ops = {
}
static const struct clk_ops clk_pllv3_sys_ops = {
- .enable = clk_pllv3_generic_enable,
+ .enable = clk_pllv3_generic_enable,
.disable = clk_pllv3_generic_disable,
.get_rate = clk_pllv3_sys_get_rate,
.set_rate = clk_pllv3_sys_set_rate,
obj-$(CONFIG_CLK_MESON_AXG) += axg.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o
-
return ret;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int px30_gmac_set_parent(struct clk *clk, struct clk *parent)
{
struct px30_clk_priv *priv = dev_get_priv(clk->dev);
static struct clk_ops px30_clk_ops = {
.get_rate = px30_clk_get_rate,
.set_rate = px30_clk_set_rate,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.set_parent = px30_clk_set_parent,
#endif
.enable = px30_clk_enable,
static int rk3188_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3188_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3188_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
-#endif
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
static struct clk_ops rk3288_clk_ops = {
.get_rate = rk3288_clk_get_rate,
.set_rate = rk3288_clk_set_rate,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.set_parent = rk3288_clk_set_parent,
#endif
};
static int rk3288_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3288_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3288_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
-#endif
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
return ret;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent)
{
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
static struct clk_ops rk3308_clk_ops = {
.get_rate = rk3308_clk_get_rate,
.set_rate = rk3308_clk_set_rate,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.set_parent = rk3308_clk_set_parent,
#endif
};
}
#endif
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
u32 div, con, con_id, rate;
case SCLK_SPI0 ... SCLK_SPI2:
rate = rk3368_spi_get_clk(priv->cru, clk->id);
break;
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
#endif
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
ret = rk3368_mmc_set_clk(clk, rate);
static struct clk_ops rk3368_clk_ops = {
.get_rate = rk3368_clk_get_rate,
.set_rate = rk3368_clk_set_rate,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.set_parent = rk3368_clk_set_parent,
#endif
};
static int rk3368_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3368_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3368_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
-#endif
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.set_parent = rk3399_clk_set_parent,
#endif
.enable = rk3399_clk_enable,
static int rk3399_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3399_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3399_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+ }
- priv->cru = dev_read_addr_ptr(dev);
-#endif
return 0;
}
static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+
+ priv->pmucru = dev_read_addr_ptr(dev);
+ }
- priv->pmucru = dev_read_addr_ptr(dev);
-#endif
return 0;
}
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
+config CLK_SUN6I_A31_R
+ bool "Clock driver for Allwinner A31 generation PRCM"
+ default SUNXI_GEN_SUN6I
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
+
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
default MACH_SUN8I_A23 || MACH_SUN8I_A33
This enables common clock driver support for platforms based
on Allwinner H6 SoC.
+config CLK_SUN50I_H6_R
+ bool "Clock driver for Allwinner H6 generation PRCM"
+ default SUN50I_GEN_H6
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner H6/H616 SoCs.
+
config CLK_SUN50I_H616
bool "Clock driver for Allwinner H616"
default MACH_SUN50I_H616
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun4i-a10-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
#include <linux/bitops.h>
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/reset/sun5i-ccu.h>
#include <linux/bitops.h>
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
#include <linux/bitops.h>
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
[CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+ [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
[RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
[RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
[RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a31_r_gates[] = {
+ [CLK_APB0_PIO] = GATE(0x028, BIT(0)),
+ [CLK_APB0_IR] = GATE(0x028, BIT(1)),
+ [CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
+ [CLK_APB0_RSB] = GATE(0x028, BIT(3)),
+ [CLK_APB0_UART] = GATE(0x028, BIT(4)),
+ [CLK_APB0_I2C] = GATE(0x028, BIT(6)),
+ [CLK_APB0_TWD] = GATE(0x028, BIT(7)),
+};
+
+static struct ccu_reset a31_r_resets[] = {
+ [RST_APB0_IR] = RESET(0x0b0, BIT(1)),
+ [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
+ [RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
+ [RST_APB0_UART] = RESET(0x0b0, BIT(4)),
+ [RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
+};
+
+static const struct ccu_desc a31_r_ccu_desc = {
+ .gates = a31_r_gates,
+ .resets = a31_r_resets,
+};
+
+static int a31_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
+}
+
+static const struct udevice_id a31_r_clk_ids[] = {
+ { .compatible = "allwinner,sun8i-a83t-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun8i-h3-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-a64-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31_r) = {
+ .name = "sun6i_a31_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = a31_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = a31_r_clk_bind,
+};
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
+ [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h616-ccu.h>
#include <dt-bindings/reset/sun50i-h616-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h6_r_gates[] = {
+ [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
+ [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
+ [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
+ [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
+ [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
+ [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
+ [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
+ [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
+};
+
+static struct ccu_reset h6_r_resets[] = {
+ [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
+ [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
+ [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
+ [RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
+ [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
+ [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
+ [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
+ [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
+};
+
+static const struct ccu_desc h6_r_ccu_desc = {
+ .gates = h6_r_gates,
+ .resets = h6_r_resets,
+};
+
+static int h6_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
+}
+
+static const struct udevice_id h6_r_clk_ids[] = {
+ { .compatible = "allwinner,sun50i-h6-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-h616-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_h6_r) = {
+ .name = "sun6i_h6_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = h6_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = h6_r_clk_bind,
+};
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <log.h>
#include <reset.h>
#include <asm/io.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <linux/bitops.h>
#include <linux/log2.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
struct clk_ti_reg clkmode_reg;
struct clk_ti_reg idlest_reg;
struct clk_ti_reg clksel_reg;
+ struct clk_ti_reg ssc_deltam_reg;
+ struct clk_ti_reg ssc_modfreq_reg;
struct clk clk_bypass;
struct clk clk_ref;
u16 last_rounded_mult;
u8 last_rounded_div;
+ u8 min_div;
ulong max_rate;
+ u32 ssc_modfreq;
+ u32 ssc_deltam;
+ bool ssc_downspread;
};
static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
err = rate;
err_min = rate;
ref_rate = clk_get_rate(&priv->clk_ref);
- for (d = 1; err_min && d <= 128; d++) {
+ for (d = priv->min_div; err_min && d <= 128; d++) {
for (m = 2; m <= 2047; m++) {
r = (ref_rate * m) / d;
err = abs(r - rate);
priv->last_rounded_mult = mult;
priv->last_rounded_div = div;
- dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
- ret, mult, div);
+ dev_dbg(clk->dev, "rate=%ld, min-div: %d, best_rate=%ld, mult=%d, div=%d\n",
+ rate, priv->min_div, ret, mult, div);
return ret;
}
return 0;
}
+/**
+ * clk_ti_am3_dpll_ssc_program - set spread-spectrum clocking registers
+ * @clk: struct clk * of DPLL to set
+ *
+ * Enable the DPLL spread spectrum clocking if frequency modulation and
+ * frequency spreading have been set, otherwise disable it.
+ */
+static void clk_ti_am3_dpll_ssc_program(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ unsigned long ref_rate;
+ u32 v, ctrl, mod_freq_divider, exponent, mantissa;
+ u32 deltam_step, deltam_ceil;
+
+ ctrl = clk_ti_readl(&priv->clkmode_reg);
+
+ if (priv->ssc_modfreq && priv->ssc_deltam) {
+ ctrl |= CM_CLKMODE_DPLL_SSC_EN_MASK;
+
+ if (priv->ssc_downspread)
+ ctrl |= CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+ else
+ ctrl &= ~CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+
+ ref_rate = clk_get_rate(&priv->clk_ref);
+ mod_freq_divider =
+ (ref_rate / priv->last_rounded_div) / (4 * priv->ssc_modfreq);
+ if (priv->ssc_modfreq > (ref_rate / 70))
+ dev_warn(clk->dev,
+ "clock: SSC modulation frequency of DPLL %s greater than %ld\n",
+ clk->dev->name, ref_rate / 70);
+
+ exponent = 0;
+ mantissa = mod_freq_divider;
+ while ((mantissa > 127) && (exponent < 7)) {
+ exponent++;
+ mantissa /= 2;
+ }
+ if (mantissa > 127)
+ mantissa = 127;
+
+ v = clk_ti_readl(&priv->ssc_modfreq_reg);
+ v &= ~(CM_SSC_MODFREQ_DPLL_MANT_MASK | CM_SSC_MODFREQ_DPLL_EXP_MASK);
+ v |= mantissa << __ffs(CM_SSC_MODFREQ_DPLL_MANT_MASK);
+ v |= exponent << __ffs(CM_SSC_MODFREQ_DPLL_EXP_MASK);
+ clk_ti_writel(v, &priv->ssc_modfreq_reg);
+ dev_dbg(clk->dev,
+ "mod_freq_divider: %u, exponent: %u, mantissa: %u, modfreq_reg: 0x%x\n",
+ mod_freq_divider, exponent, mantissa, v);
+
+ deltam_step = priv->last_rounded_mult * priv->ssc_deltam;
+ deltam_step /= 10;
+ if (priv->ssc_downspread)
+ deltam_step /= 2;
+
+ deltam_step <<= __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+ deltam_step /= 100;
+ deltam_step /= mod_freq_divider;
+ if (deltam_step > 0xFFFFF)
+ deltam_step = 0xFFFFF;
+
+ deltam_ceil = (deltam_step & CM_SSC_DELTAM_DPLL_INT_MASK) >>
+ __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+ if (deltam_step & CM_SSC_DELTAM_DPLL_FRAC_MASK)
+ deltam_ceil++;
+
+ if ((priv->ssc_downspread &&
+ ((priv->last_rounded_mult - (2 * deltam_ceil)) < 20 ||
+ priv->last_rounded_mult > 2045)) ||
+ ((priv->last_rounded_mult - deltam_ceil) < 20 ||
+ (priv->last_rounded_mult + deltam_ceil) > 2045))
+ dev_warn(clk->dev,
+ "clock: SSC multiplier of DPLL %s is out of range\n",
+ clk->dev->name);
+
+ v = clk_ti_readl(&priv->ssc_deltam_reg);
+ v &= ~(CM_SSC_DELTAM_DPLL_INT_MASK | CM_SSC_DELTAM_DPLL_FRAC_MASK);
+ v |= deltam_step << __ffs(CM_SSC_DELTAM_DPLL_INT_MASK |
+ CM_SSC_DELTAM_DPLL_FRAC_MASK);
+ clk_ti_writel(v, &priv->ssc_deltam_reg);
+ dev_dbg(clk->dev,
+ "deltam_step: %u, deltam_ceil: %u, deltam_reg: 0x%x\n",
+ deltam_step, deltam_ceil, v);
+ } else {
+ ctrl &= ~CM_CLKMODE_DPLL_SSC_EN_MASK;
+ }
+
+ clk_ti_writel(ctrl, &priv->clkmode_reg);
+}
+
static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
{
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
clk_ti_writel(v, &priv->clksel_reg);
+ clk_ti_am3_dpll_ssc_program(clk);
+
/* lock dpll */
clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
struct clk_ti_am3_dpll_drv_data *data =
(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+ u32 min_div;
int err;
priv->max_rate = data->max_rate;
return err;
}
+ err = clk_ti_get_reg_addr(dev, 3, &priv->ssc_deltam_reg);
+ if (err) {
+ dev_err(dev, "failed to get SSC deltam register\n");
+ return err;
+ }
+
+ err = clk_ti_get_reg_addr(dev, 4, &priv->ssc_modfreq_reg);
+ if (err) {
+ dev_err(dev, "failed to get SSC modfreq register\n");
+ return err;
+ }
+
+ if (dev_read_u32(dev, "ti,ssc-modfreq-hz", &priv->ssc_modfreq))
+ priv->ssc_modfreq = 0;
+
+ if (dev_read_u32(dev, "ti,ssc-deltam", &priv->ssc_deltam))
+ priv->ssc_deltam = 0;
+
+ priv->ssc_downspread = dev_read_bool(dev, "ti,ssc-downspread");
+
+ if (dev_read_u32(dev, "ti,min-div", &min_div) || min_div == 0 ||
+ min_div > 128)
+ priv->min_div = 1;
+ else
+ priv->min_div = min_div;
+
return 0;
}
config SPL_DM_DEVICE_REMOVE
bool "Support device removal in SPL"
depends on SPL_DM
- default n
help
We can save some code space by dropping support for removing a
device. This is not normally required in SPL, so by default this
config SPL_DM_SEQ_ALIAS
bool "Support numbered aliases in device tree in SPL"
depends on SPL_DM
- default n
help
Most boards will have a '/aliases' node containing the path to
numbered devices (e.g. serial0 = &serial0). This feature can be
config DM_DMA
bool "Support per-device DMA constraints"
depends on DM
- default n
help
Enable this to extract per-device DMA constraints, only supported on
device-tree systems for now. This is needed in order translate
config SPL_OF_TRANSLATE
bool "Translate addresses using fdt_translate_address in SPL"
depends on SPL_DM && SPL_OF_CONTROL
- default n
help
If this option is enabled, the reg property will be translated
using the fdt_translate_address() function. This is necessary
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/**
* device_find_by_ofnode() - Return device associated with given ofnode
*
dev->uclass_plat_ = uclass_plat;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
bool device_is_compatible(const struct udevice *dev, const char *compat)
{
return ofnode_device_is_compatible(dev_ofnode(dev), compat);
fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
fdt_addr_t addr;
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
return ret;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/**
* driver_check_compatible() - Check if a driver matches a compatible string
*
else
return ofnode_write_string(node, "status", "disabled");
}
+
+bool ofnode_conf_read_bool(const char *prop_name)
+{
+ ofnode node;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node))
+ return false;
+
+ return ofnode_read_bool(node, prop_name);
+}
+
+int ofnode_conf_read_int(const char *prop_name, int default_val)
+{
+ ofnode node;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node))
+ return default_val;
+
+ return ofnode_read_u32_default(node, prop_name, default_val);
+}
+
+const char *ofnode_conf_read_str(const char *prop_name)
+{
+ ofnode node;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node))
+ return NULL;
+
+ return ofnode_read_string(node, prop_name);
+}
return ret;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/**
* dm_scan_fdt_node() - Scan the device tree and bind drivers for a node
*
return ret;
}
- if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
ret = dm_extended_scan(pre_reloc_only);
if (ret) {
debug("dm_extended_scan() failed: %d\n", ret);
.per_device_plat_auto = sizeof(struct simple_bus_plat),
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id generic_simple_bus_ids[] = {
{ .compatible = "simple-bus" },
{ .compatible = "simple-mfd" },
U_BOOT_DRIVER(generic_syscon) = {
.name = "syscon",
.id = UCLASS_SYSCON,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_match = generic_syscon_ids,
return ret;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
const char *name, struct udevice **devp)
{
return count;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int pci_get_devfn(struct udevice *dev)
{
struct fdt_pci_addr addr;
static const struct udevice_id at91_cpu_ids[] = {
{ .compatible = "arm,cortex-a7" },
+ { .compatible = "arm,arm926ej-s" },
{ /* Sentinel. */ }
};
return 0;
}
-static const char *cpu_current = "cpu-test1";
+static const char *cpu_current = "cpu@1";
void cpu_sandbox_set_current(const char *name)
{
menu "Hardware crypto devices"
+source drivers/crypto/hash/Kconfig
+
source drivers/crypto/fsl/Kconfig
endmenu
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2013 Samsung Electronics Co., Ltd.
-# http://www.samsung.com
+# http://www.samsung.com
obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
obj-y += rsa_mod_exp/
obj-y += fsl/
+obj-y += hash/
--- /dev/null
+config DM_HASH
+ bool "Enable Driver Model for Hash"
+ depends on DM
+ help
+ If you want to use driver model for Hash, say Y.
+
+config HASH_SOFTWARE
+ bool "Enable driver for Hash in software"
+ depends on DM_HASH
+ depends on MD5
+ depends on SHA1
+ depends on SHA256
+ depends on SHA512_ALGO
+ help
+ Enable driver for hashing operations in software. Currently
+ it support multiple hash algorithm including CRC/MD5/SHA.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021 ASPEED Technology Inc.
+
+obj-$(CONFIG_DM_HASH) += hash-uclass.o
+obj-$(CONFIG_HASH_SOFTWARE) += hash_sw.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 ASPEED Technology Inc.
+ * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com>
+ */
+
+#define LOG_CATEGORY UCLASS_HASH
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <u-boot/hash.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+struct hash_info {
+ char *name;
+ uint32_t digest_size;
+};
+
+static const struct hash_info hash_info[HASH_ALGO_NUM] = {
+ [HASH_ALGO_CRC16_CCITT] = { "crc16-ccitt", 2 },
+ [HASH_ALGO_CRC32] = { "crc32", 4 },
+ [HASH_ALGO_MD5] = { "md5", 16 },
+ [HASH_ALGO_SHA1] = { "sha1", 20 },
+ [HASH_ALGO_SHA256] = { "sha256", 32 },
+ [HASH_ALGO_SHA384] = { "sha384", 48 },
+ [HASH_ALGO_SHA512] = { "sha512", 64},
+};
+
+enum HASH_ALGO hash_algo_lookup_by_name(const char *name)
+{
+ int i;
+
+ if (!name)
+ return HASH_ALGO_INVALID;
+
+ for (i = 0; i < HASH_ALGO_NUM; ++i)
+ if (!strcmp(name, hash_info[i].name))
+ return i;
+
+ return HASH_ALGO_INVALID;
+}
+
+ssize_t hash_algo_digest_size(enum HASH_ALGO algo)
+{
+ if (algo >= HASH_ALGO_NUM)
+ return -EINVAL;
+
+ return hash_info[algo].digest_size;
+}
+
+const char *hash_algo_name(enum HASH_ALGO algo)
+{
+ if (algo >= HASH_ALGO_NUM)
+ return NULL;
+
+ return hash_info[algo].name;
+}
+
+int hash_digest(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf)
+{
+ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev);
+
+ if (!ops->hash_digest)
+ return -ENOSYS;
+
+ return ops->hash_digest(dev, algo, ibuf, ilen, obuf);
+}
+
+int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf, uint32_t chunk_sz)
+{
+ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev);
+
+ if (!ops->hash_digest_wd)
+ return -ENOSYS;
+
+ return ops->hash_digest_wd(dev, algo, ibuf, ilen, obuf, chunk_sz);
+}
+
+int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp)
+{
+ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev);
+
+ if (!ops->hash_init)
+ return -ENOSYS;
+
+ return ops->hash_init(dev, algo, ctxp);
+}
+
+int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen)
+{
+ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev);
+
+ if (!ops->hash_update)
+ return -ENOSYS;
+
+ return ops->hash_update(dev, ctx, ibuf, ilen);
+}
+
+int hash_finish(struct udevice *dev, void *ctx, void *obuf)
+{
+ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev);
+
+ if (!ops->hash_finish)
+ return -ENOSYS;
+
+ return ops->hash_finish(dev, ctx, obuf);
+}
+
+UCLASS_DRIVER(hash) = {
+ .id = UCLASS_HASH,
+ .name = "hash",
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 ASPEED Technology Inc.
+ * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com>
+ */
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <watchdog.h>
+#include <u-boot/hash.h>
+#include <u-boot/crc.h>
+#include <u-boot/md5.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
+
+/* CRC16-CCITT */
+static void hash_init_crc16_ccitt(void *ctx)
+{
+ *((uint16_t *)ctx) = 0;
+}
+
+static void hash_update_crc16_ccitt(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), ibuf, ilen);
+}
+
+static void hash_finish_crc16_ccitt(void *ctx, void *obuf)
+{
+ *((uint16_t *)obuf) = *((uint16_t *)ctx);
+}
+
+/* CRC32 */
+static void hash_init_crc32(void *ctx)
+{
+ *((uint32_t *)ctx) = 0;
+}
+
+static void hash_update_crc32(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ *((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), ibuf, ilen);
+}
+
+static void hash_finish_crc32(void *ctx, void *obuf)
+{
+ *((uint32_t *)obuf) = *((uint32_t *)ctx);
+}
+
+/* MD5 */
+static void hash_init_md5(void *ctx)
+{
+ MD5Init((struct MD5Context *)ctx);
+}
+
+static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ MD5Update((struct MD5Context *)ctx, ibuf, ilen);
+}
+
+static void hash_finish_md5(void *ctx, void *obuf)
+{
+ MD5Final(obuf, (struct MD5Context *)ctx);
+}
+
+/* SHA1 */
+static void hash_init_sha1(void *ctx)
+{
+ sha1_starts((sha1_context *)ctx);
+}
+
+static void hash_update_sha1(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ sha1_update((sha1_context *)ctx, ibuf, ilen);
+}
+
+static void hash_finish_sha1(void *ctx, void *obuf)
+{
+ sha1_finish((sha1_context *)ctx, obuf);
+}
+
+/* SHA256 */
+static void hash_init_sha256(void *ctx)
+{
+ sha256_starts((sha256_context *)ctx);
+}
+
+static void hash_update_sha256(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ sha256_update((sha256_context *)ctx, ibuf, ilen);
+}
+
+static void hash_finish_sha256(void *ctx, void *obuf)
+{
+ sha256_finish((sha256_context *)ctx, obuf);
+}
+
+/* SHA384 */
+static void hash_init_sha384(void *ctx)
+{
+ sha384_starts((sha512_context *)ctx);
+}
+
+static void hash_update_sha384(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ sha384_update((sha512_context *)ctx, ibuf, ilen);
+}
+
+static void hash_finish_sha384(void *ctx, void *obuf)
+{
+ sha384_finish((sha512_context *)ctx, obuf);
+}
+
+/* SHA512 */
+static void hash_init_sha512(void *ctx)
+{
+ sha512_starts((sha512_context *)ctx);
+}
+
+static void hash_update_sha512(void *ctx, const void *ibuf, uint32_t ilen)
+{
+ sha512_update((sha512_context *)ctx, ibuf, ilen);
+}
+
+static void hash_finish_sha512(void *ctx, void *obuf)
+{
+ sha512_finish((sha512_context *)ctx, obuf);
+}
+
+struct sw_hash_ctx {
+ enum HASH_ALGO algo;
+ uint8_t algo_ctx[];
+};
+
+struct sw_hash_impl {
+ void (*init)(void *ctx);
+ void (*update)(void *ctx, const void *ibuf, uint32_t ilen);
+ void (*finish)(void *ctx, void *obuf);
+ uint32_t ctx_alloc_sz;
+};
+
+static struct sw_hash_impl sw_hash_impl[HASH_ALGO_NUM] = {
+ [HASH_ALGO_CRC16_CCITT] = {
+ .init = hash_init_crc16_ccitt,
+ .update = hash_update_crc16_ccitt,
+ .finish = hash_finish_crc16_ccitt,
+ .ctx_alloc_sz = sizeof(uint16_t),
+ },
+
+ [HASH_ALGO_CRC32] = {
+ .init = hash_init_crc32,
+ .update = hash_update_crc32,
+ .finish = hash_finish_crc32,
+ .ctx_alloc_sz = sizeof(uint32_t),
+ },
+
+ [HASH_ALGO_MD5] = {
+ .init = hash_init_md5,
+ .update = hash_update_md5,
+ .finish = hash_finish_md5,
+ .ctx_alloc_sz = sizeof(struct MD5Context),
+ },
+
+ [HASH_ALGO_SHA1] = {
+ .init = hash_init_sha1,
+ .update = hash_update_sha1,
+ .finish = hash_finish_sha1,
+ .ctx_alloc_sz = sizeof(sha1_context),
+ },
+
+ [HASH_ALGO_SHA256] = {
+ .init = hash_init_sha256,
+ .update = hash_update_sha256,
+ .finish = hash_finish_sha256,
+ .ctx_alloc_sz = sizeof(sha256_context),
+ },
+
+ [HASH_ALGO_SHA384] = {
+ .init = hash_init_sha384,
+ .update = hash_update_sha384,
+ .finish = hash_finish_sha384,
+ .ctx_alloc_sz = sizeof(sha512_context),
+ },
+
+ [HASH_ALGO_SHA512] = {
+ .init = hash_init_sha512,
+ .update = hash_update_sha512,
+ .finish = hash_finish_sha512,
+ .ctx_alloc_sz = sizeof(sha512_context),
+ },
+};
+
+static int sw_hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp)
+{
+ struct sw_hash_ctx *hash_ctx;
+ struct sw_hash_impl *hash_impl = &sw_hash_impl[algo];
+
+ hash_ctx = malloc(sizeof(hash_ctx->algo) + hash_impl->ctx_alloc_sz);
+ if (!hash_ctx)
+ return -ENOMEM;
+
+ hash_ctx->algo = algo;
+
+ hash_impl->init(hash_ctx->algo_ctx);
+
+ *ctxp = hash_ctx;
+
+ return 0;
+}
+
+static int sw_hash_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen)
+{
+ struct sw_hash_ctx *hash_ctx = ctx;
+ struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo];
+
+ hash_impl->update(hash_ctx->algo_ctx, ibuf, ilen);
+
+ return 0;
+}
+
+static int sw_hash_finish(struct udevice *dev, void *ctx, void *obuf)
+{
+ struct sw_hash_ctx *hash_ctx = ctx;
+ struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo];
+
+ hash_impl->finish(hash_ctx->algo_ctx, obuf);
+
+ free(ctx);
+
+ return 0;
+}
+
+static int sw_hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf, uint32_t chunk_sz)
+{
+ int rc;
+ void *ctx;
+ const void *cur, *end;
+ uint32_t chunk;
+
+ rc = sw_hash_init(dev, algo, &ctx);
+ if (rc)
+ return rc;
+
+ if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) {
+ cur = ibuf;
+ end = ibuf + ilen;
+
+ while (cur < end) {
+ chunk = end - cur;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+
+ rc = sw_hash_update(dev, ctx, cur, chunk);
+ if (rc)
+ return rc;
+
+ cur += chunk;
+ WATCHDOG_RESET();
+ }
+ } else {
+ rc = sw_hash_update(dev, ctx, ibuf, ilen);
+ if (rc)
+ return rc;
+ }
+
+ rc = sw_hash_finish(dev, ctx, obuf);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static int sw_hash_digest(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf)
+{
+ /* re-use the watchdog version with input length as the chunk_sz */
+ return sw_hash_digest_wd(dev, algo, ibuf, ilen, obuf, ilen);
+}
+
+static const struct hash_ops hash_ops_sw = {
+ .hash_init = sw_hash_init,
+ .hash_update = sw_hash_update,
+ .hash_finish = sw_hash_finish,
+ .hash_digest_wd = sw_hash_digest_wd,
+ .hash_digest = sw_hash_digest,
+};
+
+U_BOOT_DRIVER(hash_sw) = {
+ .name = "hash_sw",
+ .id = UCLASS_HASH,
+ .ops = &hash_ops_sw,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRVINFO(hash_sw) = {
+ .name = "hash_sw",
+};
+choice
+ prompt "Method to determine DDR clock frequency"
+ default STATIC_DDR_CLK_FREQ
+ depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \
+ || ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \
+ || FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2
+ help
+ The DDR clock frequency can either be defined statically now at
+ build time, or can be determined at run-time via the
+ get_board_ddr_clk function.
+
+config DYNAMIC_DDR_CLK_FREQ
+ bool "Run-time DDR clock frequency"
+
+config STATIC_DDR_CLK_FREQ
+ bool "Build-time static DDR clock frequency"
+
+endchoice
+
+config DDR_CLK_FREQ
+ int "DDR clock frequency in Hz"
+ depends on STATIC_DDR_CLK_FREQ
+ default 100000000
+ help
+ The DDR clock frequency, specified in Hz.
+
+config DDR_SPD
+ bool "JEDEC Serial Presence Detect (SPD) support"
+ help
+ For memory controllers that can utilize it, add enable support for
+ using the JEDEC SDP standard.
+
source "drivers/ddr/altera/Kconfig"
source "drivers/ddr/imx/Kconfig"
debug("DDR: HMC init success\n");
return 0;
}
-
help
Select Freescale Multi Mode DDR controller (MMDC).
+if SYS_FSL_DDR || SYS_FSL_MMDC
+
config SYS_FSL_DDR_BE
bool
help
config SYS_FSL_DDR4
bool "Freescale DDR4 controller"
depends on SYS_FSL_HAS_DDR4
+ imply DDR_SPD
select SYS_FSL_DDRC_GEN4
config SYS_FSL_DDR3
bool "Freescale DDR3 controller"
depends on SYS_FSL_HAS_DDR3
+ imply DDR_SPD
select SYS_FSL_DDRC_GEN3 if PPC
select SYS_FSL_DDRC_ARM_GEN3 if ARM
config SYS_FSL_DDR2
bool "Freescale DDR2 controller"
depends on SYS_FSL_HAS_DDR2
+ imply DDR_SPD
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
config SYS_FSL_DDR1
bool "Freescale DDR1 controller"
depends on SYS_FSL_HAS_DDR1
+ imply DDR_SPD
select SYS_FSL_DDRC_GEN1
endchoice
endmenu
+config FSL_DMA
+ def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
+
+config DDR_ECC
+ bool "ECC DDR memory support"
+
+config DDR_ECC_CMD
+ bool "Access the ECC features of the memory controller"
+ depends on DDR_ECC && MPC83xx
+ default y
+
+config ECC_INIT_VIA_DDRCONTROLLER
+ bool "DDR Memory controller initializes memory."
+ help
+ Use the DDR controller to auto initialize memory. If not enabled,
+ the DMA controller is responsible for doing this.
+
+endif
+
config SYS_FSL_ERRATUM_A008378
bool
* 0110 16Gb 2GB
*
* SPD byte8 - module memory bus width
- * bit[2:0] primary bus width
+ * bit[2:0] primary bus width
* 000 8bits
- * 001 16bits
- * 010 32bits
- * 011 64bits
+ * 001 16bits
+ * 010 32bits
+ * 011 64bits
*
* SPD byte7 - module organiztion
- * bit[2:0] sdram device width
- * 000 4bits
- * 001 8bits
- * 010 16bits
- * 011 32bits
+ * bit[2:0] sdram device width
+ * 000 4bits
+ * 001 8bits
+ * 010 16bits
+ * 011 32bits
*
*/
static unsigned long long
#define FAR_END_DIMM_ADDR 0x50
#define MAX_DIMM_ADDR 0x60
-#ifndef CONFIG_DDR_FIXED_SIZE
+#ifndef CONFIG_SYS_SDRAM_SIZE
#define SDRAM_CS_SIZE 0xFFFFFFF
#else
-#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1)
+#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1)
#endif
#define SDRAM_CS_BASE 0x0
#define SDRAM_DIMM_SIZE 0x80000000
* Level 3: Provides the windows margin of each DQ as a results of DQS
* centeralization
*/
-#ifdef CONFIG_DDR_LOG_LEVEL
#define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
-#else
-#define DDR3_LOG_LEVEL 0
-#endif
#define DDR3_PBS 1
#define SPD_COL_NUM_MASK (7 << SPD_COL_NUM_OFF)
#define SPD_MODULE_ORG_BYTE 7
-#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
+#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
#define SPD_MODULE_SDRAM_DEV_WIDTH_MASK (7 << SPD_MODULE_SDRAM_DEV_WIDTH_OFF)
#define SPD_MODULE_BANK_NUM_MIN 1
#define SPD_MODULE_BANK_NUM_OFF 3
#include <dm.h>
#include <dm-demo.h>
#include <errno.h>
-#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/list.h>
-DECLARE_GLOBAL_DATA_PTR;
-
UCLASS_DRIVER(demo) = {
.name = "demo",
.id = UCLASS_DEMO,
int demo_parse_dt(struct udevice *dev)
{
struct dm_demo_pdata *pdata = dev_get_plat(dev);
- int dn = dev_of_offset(dev);
- pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0);
- pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL);
+ pdata->sides = dev_read_s32_default(dev, "sides", 0);
+ pdata->colour = dev_read_string(dev, "colour");
if (!pdata->sides || !pdata->colour) {
debug("%s: Invalid device tree data\n", __func__);
return -EINVAL;
if DFU
config DFU_WRITE_ALT
bool
- default n
config DFU_TFTP
bool "DFU via TFTP"
This driver support data transfer from devices to
memory and from memory to devices.
+config DMA_LPC32XX
+ bool "LPC32XX DMA driver"
+ select DMA_LEGACY
+ help
+ Enable some legacy DMA code for lpc32xx. It provides some direct
+ functions likes lpc32xx_dma_wait_status() which can be called from
+ other code.
+
+ This should be converted to use driver model and UCLASS_DMA.
+
config TI_EDMA3
bool "TI EDMA3 driver"
+ select DMA_LEGACY
help
Enable the TI EDMA3 driver for DRA7xx and AM43xx evms.
This driver support data transfer between memory
regions.
+config TI_KSNAV
+ bool "TI Keystone Navigator DMA driver"
+ depends on ARCH_KEYSTONE
+ default y
+ select DMA_LEGACY
+ help
+ Enable the Keystone Navigator driver for Keystone 2 platforms.
+
config APBH_DMA
bool "Support APBH DMA"
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
+ select DMA_LEGACY
help
Enable APBH DMA driver.
+
if APBH_DMA
config APBH_DMA_BURST
bool "Enable DMA BURST"
endif
+config DMA_LEGACY
+ bool "Legacy DMA support"
+ default y if FSLDMAFEC
+ help
+ Enable legacy DMA support. This does not use driver model and should
+ be migrated to the new API.
+
+ It is required for some PowerPC boards.
+
source "drivers/dma/ti/Kconfig"
endmenu # menu "DMA Support"
/*
* 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
- * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
*/
#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
- (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
void dma_meminit(uint val, uint size)
{
uint *p = 0;
#include <linux/delay.h>
struct qm_config qm_memmap = {
- .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE,
- .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE,
- .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS,
- .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE,
- .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE,
- .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE,
- .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE,
- .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE,
- .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
- .region_num = CONFIG_KSNAV_QM_REGION_NUM,
- .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE,
- .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE,
- .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE,
- .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM,
+ .stat_cfg = KS2_QM_QUEUE_STATUS_BASE,
+ .queue = (void *)KS2_QM_MANAGER_QUEUES_BASE,
+ .mngr_vbusm = KS2_QM_BASE_ADDRESS,
+ .i_lram = KS2_QM_LINK_RAM_BASE,
+ .proxy = (void *)KS2_QM_MANAGER_Q_PROXY_BASE,
+ .status_ram = KS2_QM_STATUS_RAM_BASE,
+ .mngr_cfg = (void *)KS2_QM_CONF_BASE,
+ .intd_cfg = KS2_QM_INTD_CONF_BASE,
+ .desc_mem = (void *)KS2_QM_DESC_SETUP_BASE,
+ .region_num = KS2_QM_REGION_NUM,
+ .pdsp_cmd = KS2_QM_PDSP1_CMD_BASE,
+ .pdsp_ctl = KS2_QM_PDSP1_CTRL_BASE,
+ .pdsp_iram = KS2_QM_PDSP1_IRAM_BASE,
+ .qpool_num = KS2_QM_QPOOL_NUM,
};
/*
writel(0, &pktdma->global->emulation_control);
/* Set QM base address, only for K2x devices */
- writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
+ writel(KS2_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
/* Enable all channels. The current state isn't important */
for (j = 0; j < pktdma->tx_ch_num; j++) {
#include <asm/ti-common/keystone_nav.h>
-#ifdef CONFIG_KSNAV_PKTDMA_NETCP
/* NETCP Pktdma */
struct pktdma_cfg netcp_pktdma = {
- .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE,
- .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE,
- .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM,
- .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE,
- .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM,
- .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE,
- .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE,
- .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM,
- .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE,
- .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE,
- .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE,
+ .global = (void *)KS2_NETCP_PDMA_CTRL_BASE,
+ .tx_ch = (void *)KS2_NETCP_PDMA_TX_BASE,
+ .tx_ch_num = KS2_NETCP_PDMA_TX_CH_NUM,
+ .rx_ch = (void *)KS2_NETCP_PDMA_RX_BASE,
+ .rx_ch_num = KS2_NETCP_PDMA_RX_CH_NUM,
+ .tx_sched = (u32 *)KS2_NETCP_PDMA_SCHED_BASE,
+ .rx_flows = (void *)KS2_NETCP_PDMA_RX_FLOW_BASE,
+ .rx_flow_num = KS2_NETCP_PDMA_RX_FLOW_NUM,
+ .rx_free_q = KS2_NETCP_PDMA_RX_FREE_QUEUE,
+ .rx_rcv_q = KS2_NETCP_PDMA_RX_RCV_QUEUE,
+ .tx_snd_q = KS2_NETCP_PDMA_TX_SND_QUEUE,
};
-#endif
select TI_K3_NAVSS_RINGACC
select TI_K3_NAVSS_PSILCFG
select TI_K3_PSIL
- default n
help
Support for UDMA used in K3 devices.
endif
config FASTBOOT_UUU_SUPPORT
bool "Enable FASTBOOT i.MX UUU special command"
- default n
help
The fastboot protocol includes "UCmd" and "ACmd" command.
Be aware that you provide full access to any U-Boot command,
UCLASS_DRIVER(firmware) = {
.id = UCLASS_FIRMWARE,
.name = "firmware",
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
obj-y += scmi_agent-uclass.o
obj-y += smt.o
-obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o
+obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o
obj-$(CONFIG_DM_MAILBOX) += mailbox_agent.o
obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
-
# GPIO infrastructure and drivers
#
-menu "GPIO Support"
+menuconfig GPIO
+ bool "GPIO support"
+ default y
+ help
+ Enable support for GPIOs (General-purpose Input/Output) in U-Boot.
+ GPIOs allow U-Boot to read the state of an input line (high or
+ low) and set the state of an output line. This can be used to
+ drive LEDs, control power to various system parts and read user
+ input. GPIOs can be useful to enable a 'sign-of-life' LED,
+ for example. Enable this option to build the drivers in
+ drivers/gpio as part of an U-Boot build.
+
+if GPIO
config DM_GPIO
bool "Enable Driver Model for GPIO drivers"
config GPIO_HOG
bool "Enable GPIO hog support"
depends on DM_GPIO
- default n
help
Enable gpio hog support
The GPIO chip may contain GPIO hog definitions. GPIO hogging
config DWAPB_GPIO
bool "DWAPB GPIO driver"
depends on DM && DM_GPIO
- default n
help
Support for the Designware APB GPIO driver.
config AT91_GPIO
bool "AT91 PIO GPIO driver"
- default n
help
Say yes here to select AT91 PIO GPIO driver. AT91 PIO
controller manages up to 32 fully programmable input/output
config ATMEL_PIO4
bool "ATMEL PIO4 driver"
depends on DM_GPIO
- default n
help
Say yes here to support the Atmel PIO4 driver.
The PIO4 is new version of Atmel PIO controller, which manages
config IMX_RGPIO2P
bool "i.MX7ULP RGPIO2P driver"
depends on DM
- default n
help
This driver supports i.MX7ULP Rapid GPIO2P controller.
config IPROC_GPIO
bool "Broadcom iProc GPIO driver(without pinconf)"
- default n
help
The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray,
use the same GPIO Controller IP hence this driver could be used
config HSDK_CREG_GPIO
bool "HSDK CREG GPIO griver"
depends on DM_GPIO
- default n
help
This driver supports CREG GPIOs on Synopsys HSDK SOC.
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
- default n
help
Support for the LPC32XX GPIO driver.
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
- default n
help
Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
This controller have single bank (default name "soc"), every
config VYBRID_GPIO
bool "Vybrid GPIO driver"
depends on DM
- default n
help
Say yes here to support Vybrid vf610 GPIOs.
into a number of banks each with 32 GPIOs. The GPIOs for a device are
defined in the device tree with one node for each bank.
-endmenu
+endif
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
-obj-$(CONFIG_MARVELL_MFP) += mvmfp.o
obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o
obj-$(CONFIG_S5P) += s5p_gpio.o
-obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
+obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o
obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
-obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
+obj-$(CONFIG_$(SPL_TPL_)PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
*/
#include <common.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <asm/gpio.h>
#include <axp_pmic.h>
#include <common.h>
#include <dm.h>
+#include <dt-structs.h>
#include <log.h>
#include <dm/devres.h>
#include <dm/device_compat.h>
if (!strncasecmp(name, uc_priv->bank_name, len)) {
if (!strict_strtoul(name + len, 10, &offset))
- break;
+ if (offset < uc_priv->gpio_count)
+ break;
}
/*
return 0;
}
-int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
- struct ofnode_phandle_args *args)
+unsigned long gpio_flags_xlate(uint32_t arg)
{
- if (args->args_count < 1)
- return -EINVAL;
+ unsigned long flags = 0;
- desc->offset = args->args[0];
-
- if (args->args_count < 2)
- return 0;
-
- desc->flags = 0;
- if (args->args[1] & GPIO_ACTIVE_LOW)
- desc->flags |= GPIOD_ACTIVE_LOW;
+ if (arg & GPIO_ACTIVE_LOW)
+ flags |= GPIOD_ACTIVE_LOW;
/*
* need to test 2 bits for gpio output binding:
* OPEN_DRAIN (0x6) = SINGLE_ENDED (0x2) | LINE_OPEN_DRAIN (0x4)
* OPEN_SOURCE (0x2) = SINGLE_ENDED (0x2) | LINE_OPEN_SOURCE (0x0)
*/
- if (args->args[1] & GPIO_SINGLE_ENDED) {
- if (args->args[1] & GPIO_LINE_OPEN_DRAIN)
- desc->flags |= GPIOD_OPEN_DRAIN;
+ if (arg & GPIO_SINGLE_ENDED) {
+ if (arg & GPIO_LINE_OPEN_DRAIN)
+ flags |= GPIOD_OPEN_DRAIN;
else
- desc->flags |= GPIOD_OPEN_SOURCE;
+ flags |= GPIOD_OPEN_SOURCE;
}
- if (args->args[1] & GPIO_PULL_UP)
- desc->flags |= GPIOD_PULL_UP;
+ if (arg & GPIO_PULL_UP)
+ flags |= GPIOD_PULL_UP;
+
+ if (arg & GPIO_PULL_DOWN)
+ flags |= GPIOD_PULL_DOWN;
+
+ return flags;
+}
+
+int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ if (args->args_count < 1)
+ return -EINVAL;
+
+ desc->offset = args->args[0];
+ if (desc->offset >= uc_priv->gpio_count)
+ return -EINVAL;
+
+ if (args->args_count < 2)
+ return 0;
- if (args->args[1] & GPIO_PULL_DOWN)
- desc->flags |= GPIOD_PULL_DOWN;
+ desc->flags = gpio_flags_xlate(args->args[1]);
return 0;
}
return gpio_xlate_offs_flags(desc->dev, desc, args);
}
-#if defined(CONFIG_GPIO_HOG)
+#if CONFIG_IS_ENABLED(GPIO_HOG)
struct gpio_hog_priv {
struct gpio_desc gpiod;
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int _gpio_request_by_name_nodev(ofnode node, const char *list_name,
int index, struct gpio_desc *desc,
int flags, bool add_index)
}
#endif /* OF_PLATDATA */
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+int gpio_request_by_phandle(struct udevice *dev,
+ const struct phandle_2_arg *cells,
+ struct gpio_desc *desc, int flags)
+{
+ struct ofnode_phandle_args args;
+ struct udevice *gpio_dev;
+ const int index = 0;
+ int ret;
+
+ ret = device_get_by_ofplat_idx(cells->idx, &gpio_dev);
+ if (ret)
+ return ret;
+ args.args[0] = cells->arg[0];
+ args.args[1] = cells->arg[1];
+
+ return gpio_request_tail(ret, NULL, &args, NULL, index, desc, flags,
+ index > 0, gpio_dev);
+}
+#endif
+
int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc)
{
/* For now, we don't do any checking of dev */
}
#endif
- if (IS_ENABLED(CONFIG_GPIO_HOG)) {
+ if (CONFIG_IS_ENABLED(OF_REAL) && IS_ENABLED(CONFIG_GPIO_HOG)) {
dev_for_each_subnode(node, dev) {
if (ofnode_read_bool(node, "gpio-hog")) {
const char *name = ofnode_get_name(node);
return !!readb(bank->base + (BIT(gpio + 2)));
}
-
-
static const struct dm_gpio_ops gpio_hi6220_ops = {
.direction_input = hi6220_gpio_direction_input,
.direction_output = hi6220_gpio_direction_output,
.probe = hi6220_gpio_probe,
.priv_auto = sizeof(struct gpio_bank),
};
-
-
#endif
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id intel_intel_gpio_ids[] = {
{ .compatible = "intel,gpio" },
{ }
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <mvmfp.h>
-#include <asm/arch/mfp.h>
-
-/*
- * mfp_config
- *
- * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
- * configuration registers to configure each GPIO/Function pin on the
- * SoC.
- *
- * This function reads the array of values for
- * MFPR_X registers and programms them into respective
- * Multi-Function Pin registers.
- * It supports - Alternate Function Selection programming.
- *
- * Whereas,
- * The Configureation value is constructed using MFP()
- * array consists of 32bit values as defined in MFP(xx,xx..) macro
- */
-void mfp_config(u32 *mfp_cfgs)
-{
- u32 *p_mfpr = NULL;
- u32 cfg_val, val;
-
- do {
- cfg_val = *mfp_cfgs++;
- /* exit if End of configuration table detected */
- if (cfg_val == MFP_EOC)
- break;
-
- p_mfpr = (u32 *)(MV_MFPR_BASE
- + MFP_REG_GET_OFFSET(cfg_val));
-
- /* Write a mfg register as per configuration */
- val = 0;
- if (cfg_val & MFP_VALUE_MASK)
- val |= cfg_val & MFP_VALUE_MASK;
-
- writel(val, p_mfpr);
- } while (1);
- /*
- * perform a read-back of any MFPR register to make sure the
- * previous writings are finished
- */
- readl(p_mfpr);
-}
[0] = GPIO1_BASE_ADDR,
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
{ "gpio_mxc", &mxc_plat[0] },
{ "gpio_mxc", &mxc_plat[1] },
{ "gpio_mxc", &mxc_plat[2] },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[3] },
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int mxs_of_to_plat(struct udevice *dev)
{
struct mxs_gpio_plat *plat = dev_get_plat(dev);
.probe = mxs_gpio_probe,
.priv_auto = sizeof(struct mxs_gpio_priv),
.plat_auto = sizeof(struct mxs_gpio_plat),
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = mxs_gpio_ids,
.of_to_plat = mxs_of_to_plat,
#endif
}
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id omap_gpio_ids[] = {
{ .compatible = "ti,omap3-gpio" },
{ .compatible = "ti,omap4-gpio" },
.name = "gpio_omap",
.id = UCLASS_GPIO,
#if CONFIG_IS_ENABLED(OF_CONTROL)
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap_gpio_ids,
.of_to_plat = of_match_ptr(omap_gpio_of_to_plat),
.plat_auto = sizeof(struct omap_gpio_plat),
static int sandbox_gpio_of_to_plat(struct udevice *dev)
{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = dev_read_u32_default(dev, "sandbox,gpio-count",
- 0);
- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+ uc_priv->gpio_count =
+ dev_read_u32_default(dev, "sandbox,gpio-count", 0);
+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+ }
return 0;
}
DM_DRIVER_ALIAS(sandbox_gpio, sandbox_gpio_alias)
+#if CONFIG_IS_ENABLED(PINCTRL)
+
/* pincontrol: used only to check GPIO pin configuration (pinmux command) */
struct sb_pinctrl_priv {
.priv_auto = sizeof(struct sb_pinctrl_priv),
ACPI_OPS_PTR(&pinctrl_sandbox_acpi_ops)
};
+
+#endif /* PINCTRL */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sandbox driver for testing GPIOs with of-platdata
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+
+static const struct udevice_id sandbox_gpio_test_ids[] = {
+ { .compatible = "sandbox,gpio-test" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_gpio_test) = {
+ .name = "sandbox_gpio_test",
+ .id = UCLASS_MISC,
+ .of_match = sandbox_gpio_test_ids,
+};
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
-#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
-
struct sunxi_gpio_plat {
struct sunxi_gpio *regs;
const char *bank_name; /* Name of bank, e.g. "B" */
}
#endif /* DM_GPIO */
-int sunxi_name_to_gpio_bank(const char *name)
-{
- int group = 0;
-
- if (*name == 'P' || *name == 'p')
- name++;
- if (*name >= 'A') {
- group = *name - (*name > 'a' ? 'a' : 'A');
- return group;
- }
-
- return -1;
-}
-
#if CONFIG_IS_ENABLED(DM_GPIO)
/* TODO(sjg@chromium.org): Remove this function and use device tree */
int sunxi_name_to_gpio(const char *name)
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-static const int CONFIG_SFIO = 0;
-static const int CONFIG_GPIO = 1;
+static const int CFG_SFIO = 0;
+static const int CFG_GPIO = 1;
static const int DIRECTION_INPUT = 0;
static const int DIRECTION_OUTPUT = 1;
debug("get_config: port = %d, bit = %d is %s\n",
GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
- return type ? CONFIG_GPIO : CONFIG_SFIO;
+ return type ? CFG_GPIO : CFG_SFIO;
}
/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
- if (type != CONFIG_SFIO)
+ if (type != CFG_SFIO)
u |= 1 << GPIO_BIT(gpio);
else
u &= ~(1 << GPIO_BIT(gpio));
set_direction(config[i].gpio, DIRECTION_OUTPUT);
break;
}
- set_config(config[i].gpio, CONFIG_GPIO);
+ set_config(config[i].gpio, CFG_GPIO);
}
}
device (bus child) info is kept as parent platdata. The interface
is defined in include/i2c.h.
+config SYS_I2C_LEGACY
+ bool "Enable legacy I2C subsystem and drivers"
+ depends on !DM_I2C
+ help
+ Enable the legacy I2C subsystem and drivers. While this is
+ deprecated in U-Boot itself, this can be useful in some situations
+ in SPL or TPL.
+
+config SPL_SYS_I2C_LEGACY
+ bool "Enable legacy I2C subsystem and drivers in SPL"
+ depends on SUPPORT_SPL && !SPL_DM_I2C
+ help
+ Enable the legacy I2C subsystem and drivers in SPL. This is useful
+ in some size constrained situations.
+
+config TPL_SYS_I2C_LEGACY
+ bool "Enable legacy I2C subsystem and drivers in TPL"
+ depends on SUPPORT_TPL && !SPL_DM_I2C
+ help
+ Enable the legacy I2C subsystem and drivers in TPL. This is useful
+ in some size constrained situations.
+
+config SYS_I2C_EARLY_INIT
+ bool "Enable legacy I2C subsystem early in boot"
+ depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
+ help
+ Add the function prototype for i2c_early_init_f which is called in
+ board_early_init_f.
+
config I2C_CROS_EC_TUNNEL
tristate "Chrome OS EC tunnel I2C bus"
depends on CROS_EC
config SYS_I2C_FSL
bool "Freescale I2C bus driver"
- depends on DM_I2C
help
Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
MPC85xx processors.
+if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
+config SYS_FSL_I2C_OFFSET
+ hex "Offset from the IMMR of the address of the first I2C controller"
+
+config SYS_FSL_HAS_I2C2_OFFSET
+ bool "Support a second I2C controller"
+
+config SYS_FSL_I2C2_OFFSET
+ hex "Offset from the IMMR of the address of the second I2C controller"
+ depends on SYS_FSL_HAS_I2C2_OFFSET
+
+config SYS_FSL_HAS_I2C3_OFFSET
+ bool "Support a third I2C controller"
+
+config SYS_FSL_I2C3_OFFSET
+ hex "Offset from the IMMR of the address of the third I2C controller"
+ depends on SYS_FSL_HAS_I2C3_OFFSET
+
+config SYS_FSL_HAS_I2C4_OFFSET
+ bool "Support a fourth I2C controller"
+
+config SYS_FSL_I2C4_OFFSET
+ hex "Offset from the IMMR of the address of the fourth I2C controller"
+ depends on SYS_FSL_HAS_I2C4_OFFSET
+endif
+
config SYS_I2C_CADENCE
tristate "Cadence I2C Controller"
depends on DM_I2C
config SYS_I2C_CA
tristate "Cortina-Access I2C Controller"
depends on DM_I2C && CORTINA_PLATFORM
- default n
help
Add support for the Cortina Access I2C host controller.
Say yes here to select Cortina-Access I2C Host Controller.
config SYS_I2C_DW
bool "Designware I2C Controller"
- default n
help
Say yes here to select the Designware I2C Host Controller. This
controller is used in various SoCs, e.g. the ST SPEAr, Altera
channels and operating on standard mode up to 100 kbits/s and fast
mode up to 400 kbits/s.
-# These settings are not used with DM_I2C, however SPL doesn't use
-# DM_I2C even if DM_I2C is enabled, and so might use these settings even
-# when main u-boot does not!
-if SYS_I2C_MXC && (!DM_I2C || SPL)
+if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
config SYS_I2C_MXC_I2C1
bool "NXP MXC I2C1"
help
MXC I2C Channel 1 speed
config SYS_MXC_I2C1_SLAVE
- int "I2C1 Slave"
+ hex "I2C1 Slave"
default 0
help
MXC I2C1 Slave
MXC I2C Channel 2 speed
config SYS_MXC_I2C2_SLAVE
- int "I2C2 Slave"
+ hex "I2C2 Slave"
default 0
help
MXC I2C2 Slave
MXC I2C Channel 3 speed
config SYS_MXC_I2C3_SLAVE
- int "I2C3 Slave"
+ hex "I2C3 Slave"
default 0
help
MXC I2C3 Slave
MXC I2C Channel 4 speed
config SYS_MXC_I2C4_SLAVE
- int "I2C4 Slave"
+ hex "I2C4 Slave"
default 0
help
MXC I2C4 Slave
MXC I2C Channel 5 speed
config SYS_MXC_I2C5_SLAVE
- int "I2C5 Slave"
+ hex "I2C5 Slave"
default 0
help
MXC I2C5 Slave
MXC I2C Channel 6 speed
config SYS_MXC_I2C6_SLAVE
- int "I2C6 Slave"
+ hex "I2C6 Slave"
default 0
help
MXC I2C6 Slave
MXC I2C Channel 7 speed
config SYS_MXC_I2C7_SLAVE
- int "I2C7 Slave"
+ hex "I2C7 Slave"
default 0
help
MXC I2C7 Slave
MXC I2C Channel 8 speed
config SYS_MXC_I2C8_SLAVE
- int "I2C8 Slave"
+ hex "I2C8 Slave"
default 0
help
MXC I2C8 Slave
help
Add support for the OMAP2+ I2C driver.
-if SYS_I2C_OMAP24XX
-config SYS_OMAP24_I2C_SLAVE
- int "I2C Slave addr channel 0"
- default 1
- help
- OMAP24xx I2C Slave address channel 0
-
-config SYS_OMAP24_I2C_SPEED
- int "I2C Slave channel 0 speed"
- default 100000
- help
- OMAP24xx Slave speed channel 0
-endif
-
config SYS_I2C_RCAR_I2C
bool "Renesas RCar I2C driver"
depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
bus. Devices can be attached to the bus using the device tree
which specifies the driver to use. See sandbox.dts as an example.
+config SYS_I2C_SH
+ bool "Legacy SuperH I2C interface"
+ depends on ARCH_RMOBILE && SYS_I2C_LEGACY
+ help
+ Enable the legacy SuperH I2C interface.
+
+if SYS_I2C_SH
+config SYS_I2C_SH_NUM_CONTROLLERS
+ int
+ default 5
+
+config SYS_I2C_SH_BASE0
+ hex
+ default 0xE6820000
+
+config SYS_I2C_SH_BASE1
+ hex
+ default 0xE6822000
+
+config SYS_I2C_SH_BASE2
+ hex
+ default 0xE6824000
+
+config SYS_I2C_SH_BASE3
+ hex
+ default 0xE6826000
+
+config SYS_I2C_SH_BASE4
+ hex
+ default 0xE6828000
+
+config SH_I2C_8BIT
+ bool
+ default y
+
+config SH_I2C_DATA_HIGH
+ int
+ default 4
+
+config SH_I2C_DATA_LOW
+ int
+ default 5
+
+config SH_I2C_CLOCK
+ int
+ default 104000000
+endif
+
+config SYS_I2C_SOFT
+ bool "Legacy software I2C interface"
+ help
+ Enable the legacy software defined I2C interface
+
+config SYS_I2C_SOFT_SPEED
+ int "Software I2C bus speed"
+ depends on SYS_I2C_SOFT
+ default 100000
+ help
+ Speed of the software I2C bus
+
+config SYS_I2C_SOFT_SLAVE
+ hex "Software I2C slave address"
+ depends on SYS_I2C_SOFT
+ default 0xfe
+ help
+ Slave address of the software I2C bus
+
config SYS_I2C_OCTEON
bool "Octeon II/III/TX/TX2 I2C driver"
depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
- depends on ARCH_EXYNOS4 && DM_I2C
+ depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
help
Support for Samsung I2C controller as Samsung SoCs.
_ Optional clock stretching
_ Software reset
+config SYS_I2C_SUN6I_P2WI
+ bool "Allwinner sun6i P2WI controller"
+ depends on ARCH_SUNXI
+ help
+ Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
+ in the Allwinner A31 and A31s SOCs. This interface is used to connect
+ to specific devices like the X-Powers AXP221 PMIC.
+
+config SYS_I2C_SUN8I_RSB
+ bool "Allwinner sun8i Reduced Serial Bus controller"
+ depends on ARCH_SUNXI
+ help
+ Support for Allwinner's Reduced Serial Bus (RSB) controller. This
+ controller is responsible for communicating with various RSB based
+ devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
+
config SYS_I2C_SYNQUACER
bool "Socionext SynQuacer I2C controller"
depends on ARCH_SYNQUACER && DM_I2C
config SYS_I2C_MVTWSI
bool "Marvell I2C driver"
- depends on DM_I2C
help
Support for Marvell I2C controllers as used on the orion5x and
kirkwood SoC families.
by the BPMP, and can only be accessed by the main CPU via IPC
requests to the BPMP. This driver covers the latter case.
+config SYS_I2C_SLAVE
+ hex "I2C Slave address channel (all buses)"
+ depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
+ default 0xfe
+ help
+ I2C Slave address channel 0 for all buses in the legacy drivers.
+ Many boards/controllers/drivers don't support an I2C slave
+ interface so provide a default slave address for them for use in
+ common code. A real value for CONFIG_SYS_I2C_SLAVE should be
+ defined for any board which does support a slave interface and
+ this default used otherwise.
+
+config SYS_I2C_SPEED
+ int "I2C Slave channel 0 speed (all buses)"
+ depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
+ default 100000
+ help
+ I2C Slave speed channel 0 for all buses in the legacy drivers.
+
config SYS_I2C_BUS_MAX
int "Max I2C busses"
depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_SYS_I2C_LEGACY) += i2c_core.o
+obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
+obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o
+obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o
obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
dw_i2c_write, dw_i2c_set_bus_speed,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
-#if CONFIG_SYS_I2C_BUS_MAX >= 2
-U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
- dw_i2c_write, dw_i2c_set_bus_speed,
- CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
-#endif
-
-#if CONFIG_SYS_I2C_BUS_MAX >= 3
-U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
- dw_i2c_write, dw_i2c_set_bus_speed,
- CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
-#endif
-
-#if CONFIG_SYS_I2C_BUS_MAX >= 4
-U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
- dw_i2c_write, dw_i2c_set_bus_speed,
- CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
-#endif
-
#else /* CONFIG_DM_I2C */
/* The DM I2C functions */
#define IC_TX_EMPTY 0x0010
#define IC_TX_OVER 0x0008
#define IC_RX_FULL 0x0004
-#define IC_RX_OVER 0x0002
+#define IC_RX_OVER 0x0002
#define IC_RX_UNDER 0x0001
/* fifo threshold register definitions */
*/
U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
- CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
0)
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
- CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
1)
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
- CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
2)
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
- CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
3)
#endif
#else /* CONFIG_DM_I2C */
UCLASS_DRIVER(i2c_emul_parent) = {
.id = UCLASS_I2C_EMUL_PARENT,
.name = "i2c_emul_parent",
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
return ops->deblock(bus);
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip)
{
int addr;
static int i2c_pre_probe(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
unsigned int max = 0;
ofnode node;
static int i2c_post_probe(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
i2c->speed_hz = dev_read_u32_default(dev, "clock-frequency",
static int i2c_child_post_bind(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct dm_i2c_chip *plat = dev_get_parent_plat(dev);
if (!dev_has_ofnode(dev))
debug("%s: %s, seq=%d\n", __func__, dev->name, dev_seq(dev));
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
ret = dm_scan_fdt_dev(dev);
#endif
return ret;
{
}
-/* implement possible for i2c specific early i2c init */
-__weak void i2c_early_init_f(void)
-{
-}
-
/*
* i2c_init_all():
*
#include <common.h>
#include <i2c.h>
-#if CONFIG_IS_ENABLED(DM_I2C)
#include <dm.h>
#include <regmap.h>
-#else
-#include <gdsys_fpga.h>
-#endif
#include <log.h>
#include <asm/global_data.h>
#include <asm/unaligned.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-#if CONFIG_IS_ENABLED(DM_I2C)
struct ihs_i2c_priv {
uint speed;
struct regmap *map;
#define ihs_i2c_get(map, member, valp) \
regmap_get(map, struct ihs_i2c_regs, member, valp)
-#else /* !CONFIG_DM_I2C */
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-
-#define I2C_SET_REG(fld, val) \
- do { \
- if (I2C_ADAP_HWNR & 0x10) \
- FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
- else \
- FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
- } while (0)
-#else
-#define I2C_SET_REG(fld, val) \
- FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
-#endif
-
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-#define I2C_GET_REG(fld, val) \
- do { \
- if (I2C_ADAP_HWNR & 0x10) \
- FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
- else \
- FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
- } while (0)
-#else
-#define I2C_GET_REG(fld, val) \
- FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
-#endif
-#endif /* CONFIG_DM_I2C */
-
enum {
I2CINT_ERROR_EV = BIT(13),
I2CINT_TRANSMIT_EV = BIT(14),
I2COP_READ = 1,
};
-#if CONFIG_IS_ENABLED(DM_I2C)
static int wait_for_int(struct udevice *dev, int read)
-#else
-static int wait_for_int(bool read)
-#endif
{
u16 val;
uint ctr = 0;
-#if CONFIG_IS_ENABLED(DM_I2C)
struct ihs_i2c_priv *priv = dev_get_priv(dev);
-#endif
-#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_get(priv->map, interrupt_status, &val);
-#else
- I2C_GET_REG(interrupt_status, &val);
-#endif
/* Wait until error or receive/transmit interrupt was raised */
while (!(val & (I2CINT_ERROR_EV
| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
debug("%s: timed out\n", __func__);
return -ETIMEDOUT;
}
-#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_get(priv->map, interrupt_status, &val);
-#else
- I2C_GET_REG(interrupt_status, &val);
-#endif
}
return (val & I2CINT_ERROR_EV) ? -EIO : 0;
}
-#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
uchar *buffer, int len, int read, bool is_last)
-#else
-static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
- bool is_last)
-#endif
{
u16 val;
u16 data;
int res;
-#if CONFIG_IS_ENABLED(DM_I2C)
struct ihs_i2c_priv *priv = dev_get_priv(dev);
-#endif
/* Clear interrupt status */
data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
-#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_set(priv->map, interrupt_status, data);
ihs_i2c_get(priv->map, interrupt_status, &val);
-#else
- I2C_SET_REG(interrupt_status, data);
- I2C_GET_REG(interrupt_status, &val);
-#endif
/* If we want to write and have data, write the bytes to the mailbox */
if (!read && len) {
if (len > 1)
val |= buffer[1] << 8;
-#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_set(priv->map, write_mailbox_ext, val);
-#else
- I2C_SET_REG(write_mailbox_ext, val);
-#endif
}
data = I2CMB_NATIVE
| ((len > 1) ? I2CMB_2BYTE : 0)
| (is_last ? 0 : I2CMB_HOLD_BUS);
-#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_set(priv->map, write_mailbox, data);
-#else
- I2C_SET_REG(write_mailbox, data);
-#endif
-#if CONFIG_IS_ENABLED(DM_I2C)
res = wait_for_int(dev, read);
-#else
- res = wait_for_int(read);
-#endif
if (res) {
if (res == -ETIMEDOUT)
debug("%s: time out while waiting for event\n", __func__);
/* If we want to read, get the bytes from the mailbox */
if (read) {
-#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_get(priv->map, read_mailbox_ext, &val);
-#else
- I2C_GET_REG(read_mailbox_ext, &val);
-#endif
buffer[0] = val & 0xff;
if (len > 1)
buffer[1] = val >> 8;
return 0;
}
-#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
-#else
-static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
- int read)
-#endif
{
int res;
int transfer = min(len, 2);
bool is_last = len <= transfer;
-#if CONFIG_IS_ENABLED(DM_I2C)
res = ihs_i2c_transfer(dev, chip, data, transfer, read,
hold_bus ? false : is_last);
-#else
- res = ihs_i2c_transfer(chip, data, transfer, read,
- hold_bus ? false : is_last);
-#endif
if (res)
return res;
return 0;
}
-#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
bool hold_bus)
-#else
-static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
-#endif
{
-#if CONFIG_IS_ENABLED(DM_I2C)
return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
-#else
- return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
-#endif
}
-#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
int alen, uchar *buffer, int len, int read)
-#else
-static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
- int alen, uchar *buffer, int len, int read)
-#endif
{
int res;
if (len <= 0)
return -EINVAL;
-#if CONFIG_IS_ENABLED(DM_I2C)
res = ihs_i2c_address(dev, chip, addr, alen, len);
-#else
- res = ihs_i2c_address(chip, addr, alen, len);
-#endif
if (res)
return res;
-#if CONFIG_IS_ENABLED(DM_I2C)
return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
-#else
- return ihs_i2c_send_buffer(chip, buffer, len, false, read);
-#endif
}
-#if CONFIG_IS_ENABLED(DM_I2C)
-
int ihs_i2c_probe(struct udevice *bus)
{
struct ihs_i2c_priv *priv = dev_get_priv(bus);
.priv_auto = sizeof(struct ihs_i2c_priv),
.ops = &ihs_i2c_ops,
};
-
-#else /* CONFIG_DM_I2C */
-
-static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /*
- * Call board specific i2c bus reset routine before accessing the
- * environment, which might be in a chip on that bus. For details
- * about this problem see doc/I2C_Edge_Conditions.
- */
- i2c_init_board();
-#endif
-}
-
-static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
-{
- uchar buffer[2];
- int res;
-
- res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
- if (res)
- return res;
-
- return 0;
-}
-
-static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
-{
- u8 addr_bytes[4];
-
- put_unaligned_le32(addr, addr_bytes);
-
- return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
- I2COP_READ);
-}
-
-static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
-{
- u8 addr_bytes[4];
-
- put_unaligned_le32(addr, addr_bytes);
-
- return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
- I2COP_WRITE);
-}
-
-static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- if (speed != adap->speed)
- return -EINVAL;
- return speed;
-}
-
-/*
- * Register IHS i2c adapters
- */
-#ifdef CONFIG_SYS_I2C_IHS_CH0
-U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_0,
- CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_0_1,
- CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
-#endif
-#endif
-#ifdef CONFIG_SYS_I2C_IHS_CH1
-U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_1,
- CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_1_1,
- CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
-#endif
-#endif
-#ifdef CONFIG_SYS_I2C_IHS_CH2
-U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_2,
- CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_2_1,
- CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
-#endif
-#endif
-#ifdef CONFIG_SYS_I2C_IHS_CH3
-U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_3,
- CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
- ihs_i2c_read, ihs_i2c_write,
- ihs_i2c_set_bus_speed,
- CONFIG_SYS_I2C_IHS_SPEED_3_1,
- CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
-#endif
-#endif
-#endif /* CONFIG_DM_I2C */
i2c_clk_enable();
- writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
+ writel(0x0, &base->isar); /* set our slave address */
/* set control reg values */
writel(I2C_ICR_INIT | icr_mode, &base->icr);
writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
#include <linux/bitops.h>
#include <linux/compat.h>
#if CONFIG_IS_ENABLED(DM_I2C)
+#include <clk.h>
#include <dm.h>
+#include <reset.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
static int mvtwsi_i2c_probe(struct udevice *bus)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
+ struct reset_ctl reset;
+ struct clk clk;
uint actual_speed;
+ int ret;
+
+ ret = reset_get_by_index(bus, 0, &reset);
+ if (!ret)
+ reset_deassert(&reset);
+
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (!ret)
+ clk_enable(&clk);
__twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
dev->speed = actual_speed;
};
#endif
-#ifndef CONFIG_SYS_MXC_I2C1_SPEED
-#define CONFIG_SYS_MXC_I2C1_SPEED 100000
-#endif
-#ifndef CONFIG_SYS_MXC_I2C2_SPEED
-#define CONFIG_SYS_MXC_I2C2_SPEED 100000
-#endif
-#ifndef CONFIG_SYS_MXC_I2C3_SPEED
-#define CONFIG_SYS_MXC_I2C3_SPEED 100000
-#endif
-#ifndef CONFIG_SYS_MXC_I2C4_SPEED
-#define CONFIG_SYS_MXC_I2C4_SPEED 100000
-#endif
-
-#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
-#define CONFIG_SYS_MXC_I2C1_SLAVE 0
-#endif
-#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
-#define CONFIG_SYS_MXC_I2C2_SLAVE 0
-#endif
-#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
-#define CONFIG_SYS_MXC_I2C3_SLAVE 0
-#endif
-#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
-#define CONFIG_SYS_MXC_I2C4_SLAVE 0
-#endif
-
/*
* Calculate and set proper clock divider
*/
bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
}
-
-
/*
* Init I2C Bus
*/
return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
}
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
-#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
- CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE,
+ CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE,
0)
U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
- CONFIG_SYS_OMAP24_I2C_SPEED1,
- CONFIG_SYS_OMAP24_I2C_SLAVE1,
+ CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE,
1)
#if (CONFIG_SYS_I2C_BUS_MAX > 2)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
-#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
omap24_i2c_read, omap24_i2c_write, NULL,
- CONFIG_SYS_OMAP24_I2C_SPEED2,
- CONFIG_SYS_OMAP24_I2C_SLAVE2,
+ CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE,
2)
#if (CONFIG_SYS_I2C_BUS_MAX > 3)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
-#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
omap24_i2c_read, omap24_i2c_write, NULL,
- CONFIG_SYS_OMAP24_I2C_SPEED3,
- CONFIG_SYS_OMAP24_I2C_SLAVE3,
+ CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE,
3)
#if (CONFIG_SYS_I2C_BUS_MAX > 4)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
-#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
omap24_i2c_read, omap24_i2c_write, NULL,
- CONFIG_SYS_OMAP24_I2C_SPEED4,
- CONFIG_SYS_OMAP24_I2C_SLAVE4,
+ CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE,
4)
#endif
#endif
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int omap_i2c_of_to_plat(struct udevice *bus)
{
struct omap_i2c_plat *plat = dev_get_plat(bus);
U_BOOT_DRIVER(i2c_omap) = {
.name = "i2c_omap",
.id = UCLASS_I2C,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap_i2c_ids,
.of_to_plat = omap_i2c_of_to_plat,
.plat_auto = sizeof(struct omap_i2c_plat),
struct rcar_i2c_priv {
void __iomem *base;
struct clk clk;
+ u32 fall_ns;
+ u32 rise_ns;
u32 intdelay;
u32 icccr;
enum rcar_i2c_type type;
* = F[sum * ick / 1000000000]
* = F[(ick / 1000000) * sum / 1000]
*/
- sum = 35 + 200 + priv->intdelay;
+ sum = priv->fall_ns + priv->rise_ns + priv->intdelay;
round = (ick + 500000) / 1000000 * sum;
round = (round + 500) / 1000;
int ret;
priv->base = dev_read_addr_ptr(dev);
+ priv->rise_ns = dev_read_u32_default(dev,
+ "i2c-scl-rising-time-ns", 200);
+ priv->fall_ns = dev_read_u32_default(dev,
+ "i2c-scl-falling-time-ns", 35);
priv->intdelay = dev_read_u32_default(dev,
"i2c-scl-internal-delay-ns", 5);
priv->type = dev_get_driver_data(dev);
#include <i2c.h>
#include "s3c24x0_i2c.h"
-#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
-#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
-#else
-#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/*
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
+#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
+
static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
* Register RCAR i2c adapters
*/
U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0)
#ifdef CONFIG_SYS_I2C_SH_BASE1
U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE2
U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE3
U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE4
U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
+ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4)
#endif
soft_i2c_read, soft_i2c_write, NULL,
CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
0)
-#if defined(I2C_SOFT_DECLARATIONS2)
-U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_2,
- CONFIG_SYS_I2C_SOFT_SLAVE_2,
- 1)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS3)
-U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_3,
- CONFIG_SYS_I2C_SOFT_SLAVE_3,
- 2)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS4)
-U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_4,
- CONFIG_SYS_I2C_SOFT_SLAVE_4,
- 3)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS5)
-U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_5,
- CONFIG_SYS_I2C_SOFT_SLAVE_5,
- 4)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS6)
-U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_6,
- CONFIG_SYS_I2C_SOFT_SLAVE_6,
- 5)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS7)
-U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_7,
- CONFIG_SYS_I2C_SOFT_SLAVE_7,
- 6)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS8)
-U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_8,
- CONFIG_SYS_I2C_SOFT_SLAVE_8,
- 7)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS9)
-U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_9,
- CONFIG_SYS_I2C_SOFT_SLAVE_9,
- 8)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS10)
-U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_10,
- CONFIG_SYS_I2C_SOFT_SLAVE_10,
- 9)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS11)
-U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_11,
- CONFIG_SYS_I2C_SOFT_SLAVE_11,
- 10)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS12)
-U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
- soft_i2c_read, soft_i2c_write, NULL,
- CONFIG_SYS_I2C_SOFT_SPEED_12,
- CONFIG_SYS_I2C_SOFT_SLAVE_12,
- 11)
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#include <axp_pmic.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <time.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+static int sun6i_p2wi_await_trans(struct sunxi_p2wi_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(&base->status);
+ if (reg & P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg & P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, &base->status); /* Clear status bits */
+
+ return ret;
+}
+
+static int sun6i_p2wi_read(struct sunxi_p2wi_reg *base, const u8 addr, u8 *data)
+{
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
+ writel(P2WI_DATA_NUM_BYTES(1) |
+ P2WI_DATA_NUM_BYTES_READ, &base->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &base->status);
+ writel(P2WI_CTRL_TRANS_START, &base->ctrl);
+
+ ret = sun6i_p2wi_await_trans(base);
+
+ *data = readl(&base->data0) & P2WI_DATA_BYTE_1_MASK;
+
+ return ret;
+}
+
+static int sun6i_p2wi_write(struct sunxi_p2wi_reg *base, const u8 addr, u8 data)
+{
+ writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
+ writel(P2WI_DATA_BYTE_1(data), &base->data0);
+ writel(P2WI_DATA_NUM_BYTES(1), &base->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &base->status);
+ writel(P2WI_CTRL_TRANS_START, &base->ctrl);
+
+ return sun6i_p2wi_await_trans(base);
+}
+
+static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
+ u8 slave_addr, u8 ctrl_reg,
+ u8 init_data)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ &base->pm);
+
+ while ((readl(&base->pm) & P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
+{
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, &base->ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ &base->cc);
+}
+
+#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_read(base, addr, data);
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_write(base, addr, data);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg,
+ init_data);
+}
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ sun6i_p2wi_init(base);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct sun6i_p2wi_priv {
+ struct sunxi_p2wi_reg *base;
+};
+
+static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ /* The hardware only supports SMBus-style transfers. */
+ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
+ return sun6i_p2wi_read(priv->base,
+ msg[0].buf[0], &msg[1].buf[0]);
+
+ if (nmsgs == 1 && msg[0].len == 2)
+ return sun6i_p2wi_write(priv->base,
+ msg[0].buf[0], msg[0].buf[1]);
+
+ return -EINVAL;
+}
+
+static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ return sun6i_p2wi_change_to_p2wi_mode(priv->base, chip_addr,
+ AXP_PMIC_MODE_REG,
+ AXP_PMIC_MODE_P2WI);
+}
+
+static int sun6i_p2wi_probe(struct udevice *bus)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ priv->base = dev_read_addr_ptr(bus);
+
+ sun6i_p2wi_init(priv->base);
+
+ return 0;
+}
+
+static int sun6i_p2wi_child_pre_probe(struct udevice *child)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+
+ /* Ensure each transfer is for a single register. */
+ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sun6i_p2wi_ops = {
+ .xfer = sun6i_p2wi_xfer,
+ .probe_chip = sun6i_p2wi_probe_chip,
+};
+
+static const struct udevice_id sun6i_p2wi_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-p2wi" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sun6i_p2wi) = {
+ .name = "sun6i_p2wi",
+ .id = UCLASS_I2C,
+ .of_match = sun6i_p2wi_ids,
+ .probe = sun6i_p2wi_probe,
+ .child_pre_probe = sun6i_p2wi_child_pre_probe,
+ .priv_auto = sizeof(struct sun6i_p2wi_priv),
+ .ops = &sun6i_p2wi_ops,
+};
+#endif /* CONFIG_IS_ENABLED(DM_I2C) */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ */
+
+#include <axp_pmic.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <time.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/rsb.h>
+
+static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(&base->stat);
+ if (stat & RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat & RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat & RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, &base->stat); /* Clear status bits */
+
+ return ret;
+}
+
+static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
+{
+ setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
+
+ return sun8i_rsb_await_trans(base);
+}
+
+static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
+ u8 reg_addr, u8 *data)
+{
+ int ret;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
+ writel(reg_addr, &base->addr);
+ writel(RSB_CMD_BYTE_READ, &base->cmd);
+
+ ret = sun8i_rsb_do_trans(base);
+ if (ret)
+ return ret;
+
+ *data = readl(&base->data) & 0xff;
+
+ return 0;
+}
+
+static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
+ u8 reg_addr, u8 data)
+{
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
+ writel(reg_addr, &base->addr);
+ writel(data, &base->data);
+ writel(RSB_CMD_BYTE_WRITE, &base->cmd);
+
+ return sun8i_rsb_do_trans(base);
+}
+
+static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
+ u16 device_addr, u16 runtime_addr)
+{
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
+ RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
+ writel(RSB_CMD_SET_RTSADDR, &base->cmd);
+
+ return sun8i_rsb_do_trans(base);
+}
+
+static void sun8i_rsb_cfg_io(void)
+{
+#ifdef CONFIG_MACH_SUN8I
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
+}
+
+static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
+{
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 24000000 / 3000000 / 2 - 1;
+ cd_odly = div >> 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly << 8) | div, &base->ccr);
+}
+
+static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &base->dmcr);
+
+ while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return sun8i_rsb_await_trans(base);
+}
+
+static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
+{
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ /* Setup external pins */
+ sun8i_rsb_cfg_io();
+
+ writel(RSB_CTRL_SOFT_RST, &base->ctrl);
+ sun8i_rsb_set_clk(base);
+
+ return sun8i_rsb_set_device_mode(base);
+}
+
+#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
+int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
+}
+
+int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
+}
+
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
+}
+
+int rsb_init(void)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_init(base);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct sun8i_rsb_priv {
+ struct sunxi_rsb_reg *base;
+};
+
+/*
+ * The mapping from hardware address to runtime address is fixed, and shared
+ * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
+ */
+static int sun8i_rsb_get_runtime_address(u16 device_addr)
+{
+ if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
+ return AXP_PMIC_PRI_RUNTIME_ADDR;
+ if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
+ return AXP_PMIC_SEC_RUNTIME_ADDR;
+
+ return -ENXIO;
+}
+
+static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ if (runtime_addr < 0)
+ return runtime_addr;
+
+ /* The hardware only supports SMBus-style transfers. */
+ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
+ return sun8i_rsb_read(priv->base, runtime_addr,
+ msg[0].buf[0], &msg[1].buf[0]);
+
+ if (nmsgs == 1 && msg[0].len == 2)
+ return sun8i_rsb_write(priv->base, runtime_addr,
+ msg[0].buf[0], msg[0].buf[1]);
+
+ return -EINVAL;
+}
+
+static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ if (runtime_addr < 0)
+ return runtime_addr;
+
+ return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
+}
+
+static int sun8i_rsb_probe(struct udevice *bus)
+{
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ priv->base = dev_read_addr_ptr(bus);
+
+ return sun8i_rsb_init(priv->base);
+}
+
+static int sun8i_rsb_child_pre_probe(struct udevice *child)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+
+ /* Ensure each transfer is for a single register. */
+ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sun8i_rsb_ops = {
+ .xfer = sun8i_rsb_xfer,
+ .probe_chip = sun8i_rsb_probe_chip,
+};
+
+static const struct udevice_id sun8i_rsb_ids[] = {
+ { .compatible = "allwinner,sun8i-a23-rsb" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sun8i_rsb) = {
+ .name = "sun8i_rsb",
+ .id = UCLASS_I2C,
+ .of_match = sun8i_rsb_ids,
+ .probe = sun8i_rsb_probe,
+ .child_pre_probe = sun8i_rsb_child_pre_probe,
+ .priv_auto = sizeof(struct sun8i_rsb_priv),
+ .ops = &sun8i_rsb_ops,
+};
+#endif /* CONFIG_IS_ENABLED(DM_I2C) */
else if ((quirk & QUIRK_DUP_POR) && config == KBD_POR)
config = kbd_cmd_read(CMD_RD_CONFIG);
- config |= CONFIG_AT_TRANS;
- config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN);
+ config |= CFG_AT_TRANS;
+ config &= ~(CFG_KIRQ_EN | CFG_MIRQ_EN);
if (kbd_cmd_write(CMD_WR_CONFIG, config))
goto err;
#include <common.h>
#include <asm/ti-common/ti-aemif.h>
-#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4)
-#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60)
-#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c)
-#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \
- + (cs * 4))
+#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4)
+#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60)
+#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c)
+#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4))
#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
This option is an SPL-variant of the I2C_EEPROM option.
See the help of I2C_EEPROM for details.
-if I2C_EEPROM
-
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
+ depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
default 0
-config SYS_I2C_EEPROM_BUS
- int "I2C bus of the EEPROM device."
- default 0
-
-config SYS_EEPROM_SIZE
- int "Size in bytes of the EEPROM device"
- default 256
-
-config SYS_EEPROM_PAGE_WRITE_BITS
- int "Number of bits used to address bytes in a single page"
- default 0
- help
- The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
- A 64 byte page, for example would require six bits.
-
-config SYS_EEPROM_PAGE_WRITE_DELAY_MS
- int "Number of milliseconds to delay between page writes"
- default 0
-
-config SYS_I2C_EEPROM_ADDR_LEN
- int "Length in bytes of the EEPROM memory array address"
- default 1
- help
- Note: This is NOT the chip address length!
+if I2C_EEPROM
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
obj-$(CONFIG_IRQ) += irq-uclass.o
-obj-$(CONFIG_SANDBOX) += irq_sandbox.o
+obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
* I2C Driver for Atmel ATSHA204 over I2C
*
* Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
- * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
*
* int i, j;
* for (i = 0; i < 256; ++i) {
- * u8 c = 0;
- * for (j = 0; j < 8; ++j) {
- * c = (c << 1) | ((i >> j) & 1);
- * }
- * bitreverse_table[i] = c;
+ * u8 c = 0;
+ * for (j = 0; j < 8; ++j) {
+ * c = (c << 1) | ((i >> j) & 1);
+ * }
+ * bitreverse_table[i] = c;
* }
*/
*
* int i, j;
* for (i = 0; i < 256; ++i) {
- * u16 c = i << 8;
- * for (j = 0; j < 8; ++j) {
- * int b = c >> 15;
- * c <<= 1;
- * if (b)
- * c ^= 0x8005;
- * }
- * crc16_table[i] = c;
+ * u16 c = i << 8;
+ * for (j = 0; j < 8; ++j) {
+ * int b = c >> 15;
+ * c <<= 1;
+ * if (b)
+ * c ^= 0x8005;
+ * }
+ * crc16_table[i] = c;
* }
*/
static u16 const crc16_table[256] = {
retry--;
atsha204a_wakeup(dev);
} while (retry >= 0);
-
+
if (res) {
debug("ATSHA204A read failed\n");
return res;
int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan)
{
- if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
+ if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
sizeof(scan->data)) != sizeof(scan->data))
return -1;
.id = UCLASS_CROS_EC,
.name = "cros-ec",
.per_device_auto = sizeof(struct cros_ec_dev),
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-int irq_get_by_driver_info(struct udevice *dev,
- struct phandle_1_arg *cells, struct irq *irq)
+int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells,
+ struct irq *irq)
{
int ret;
return ret;
irq->id = cells->arg[0];
+ /*
+ * Note: we could call irq_of_xlate_default() here to do this properly.
+ * For now, this is good enough for existing cases.
+ */
+ irq->flags = cells->arg[1];
+
return 0;
}
#else
#include <dm.h>
#include <irq.h>
#include <acpi/acpi_device.h>
+#include <asm/irq.h>
#include <asm/test.h>
-/**
- * struct sandbox_irq_priv - private data for this driver
- *
- * @count: Counts the number calls to the read_and_clear() method
- * @pending: true if an interrupt is pending, else false
- */
-struct sandbox_irq_priv {
- int count;
- bool pending;
-};
-
static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low)
{
if (irq > 10)
{ }
};
-U_BOOT_DRIVER(sandbox_irq_drv) = {
+U_BOOT_DRIVER(sandbox_irq) = {
.name = "sandbox_irq",
.id = UCLASS_IRQ,
.of_match = sandbox_irq_ids,
.ops = &sandbox_irq_ops,
.priv_auto = sizeof(struct sandbox_irq_priv),
+ DM_HEADER(<asm/irq.h>)
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sandbox driver for testing interrupts with of-platdata
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <irq.h>
+#include <asm/irq.h>
+
+static const struct udevice_id sandbox_irq_test_ids[] = {
+ { .compatible = "sandbox,irq-test" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_irq_test) = {
+ .name = "sandbox_irq_test",
+ .id = UCLASS_MISC,
+ .of_match = sandbox_irq_test_ids,
+};
UCLASS_DRIVER(misc) = {
.id = UCLASS_MISC,
.name = "misc",
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
static int p2sb_child_post_bind(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
- int ret;
- u32 pid;
-
- ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
- if (ret)
- return ret;
- pplat->pid = pid;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
+ int ret;
+ u32 pid;
+
+ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
+ if (ret)
+ return ret;
+ pplat->pid = pid;
+ }
return 0;
}
config SPL_MMC_IO_VOLTAGE
bool "Support IO voltage configuration in SPL"
- default n
help
IO voltage configuration allows selecting the voltage level of the IO
lines (not the level of main supply). This is required for UHS
config MMC_TRACE
bool "MMC debugging"
- default n
help
This is an option for use by developer. Enable MMC core debugging.
depends on DM_MMC
depends on MMC_DW
depends on BLK
- default n
help
This selects support for Cortina SoC specific extensions to the
Synopsys DesignWare Memory Card Interface driver. Select this option
config FTSDC010_SDIO
bool "Support ftsdc010 sdio"
- default n
depends on FTSDC010
help
This can enable ftsdc010 sdio function.
config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
bool "enable eSDHC workaround for 3.3v IO reliability issue"
depends on FSL_ESDHC && DM_MMC
- default n
help
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
-obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
static int fsl_esdhc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
#endif
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
-
fdt_addr_t addr;
unsigned int val;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->vs18_enable = 1;
}
#endif
-#endif
+
return 0;
}
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = mmc_of_parse(dev, &plat->cfg);
- if (ret)
- return ret;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+ }
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
#include <syscon.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
- chip->name = dev->name;
- chip->ioaddr = dev_read_addr_ptr(dev);
- chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 4);
- chip->priv = dev;
- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "fifo-depth", 0);
- priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
- "fifo-mode");
- if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
- "clock-freq-min-max", priv->minmax, 2)) {
- int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "max-frequency", -EINVAL);
- if (val < 0)
- return val;
-
- priv->minmax[0] = 400000; /* 400 kHz */
- priv->minmax[1] = val;
- } else {
- debug("%s: 'clock-freq-min-max' property was deprecated.\n",
- __func__);
+
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ chip->name = dev->name;
+ chip->ioaddr = dev_read_addr_ptr(dev);
+ chip->buswidth = dev_read_u32_default(dev, "bus-width", 4);
+ chip->priv = dev;
+ priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
+ priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
+ if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
+ if (dev_read_u32(dev, "max-frequency", &priv->minmax[1]))
+ return -EINVAL;
+
+ priv->minmax[0] = 400000; /* 400 kHz */
+ } else {
+ debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
+ }
}
-#endif
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
+
return 0;
}
chip->priv = dev;
chip->dev_index = 1;
memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
+ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
if (ret < 0)
return ret;
#endif
mmc_go_idle(mmc);
start = get_timer(0);
- /* Asking to the card its capabilities */
+ /* Asking to the card its capabilities */
for (i = 0; ; i++) {
err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
static struct sdhci_ops mv_ops;
-
-#if defined(CONFIG_SHEEVA_88SV331xV5)
-#define SD_CE_ATA_2 0xEA
-#define MMC_CARD 0x1000
-#define MMC_WIDTH 0x0100
-static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
-{
- struct mmc *mmc = host->mmc;
- u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
-
- if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
- if (mmc->bus_width == 8)
- writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
- else
- writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
- }
-
- writeb(val, host->ioaddr + reg);
-}
-
-#else
-#define mv_sdhci_writeb NULL
-#endif /* CONFIG_SHEEVA_88SV331xV5 */
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
host->max_clk = max_clk;
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
memset(&mv_ops, 0, sizeof(struct sdhci_ops));
- mv_ops.write_b = mv_sdhci_writeb;
host->ops = &mv_ops;
#endif
.set_ios = mxsmmc_set_ios,
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int mxsmmc_of_to_plat(struct udevice *bus)
{
struct mxsmmc_plat *plat = dev_get_plat(bus);
U_BOOT_DRIVER(fsl_imx23_mmc) = {
.name = "fsl_imx23_mmc",
.id = UCLASS_MMC,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = mxsmmc_ids,
.of_to_plat = mxsmmc_of_to_plat,
#endif
#include <asm/arch/mux_dra7xx.h>
#include <asm/arch/dra7xx_iodelay.h>
#endif
-#if !defined(CONFIG_SOC_KEYSTONE)
+#if !defined(CONFIG_ARCH_KEYSTONE)
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#endif
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
+ defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
}
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
#ifdef CONFIG_OMAP54XX
__weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
{
return omap_hsmmc_init_setup(mmc);
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct omap_mmc_of_data dra7_mmc_of_data = {
.controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
U_BOOT_DRIVER(omap_hsmmc) = {
.name = "omap_hsmmc",
.id = UCLASS_MMC,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap_hsmmc_ids,
.of_to_plat = omap_hsmmc_of_to_plat,
.plat_auto = sizeof(struct omap_hsmmc_plat),
static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
-#endif
+
return 0;
}
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = dtplat->max_frequency;
- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
+ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
if (ret < 0)
return ret;
#else
#include <mmc.h>
#include <clk.h>
#include <reset.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
-#include <asm-generic/gpio.h>
#include <linux/delay.h>
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
source "drivers/mtd/nand/Kconfig"
+config SYS_NAND_MAX_CHIPS
+ int "NAND max chips"
+ depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
+ SPL_OMAP3_ID_NAND
+ default 1
+ help
+ The maximum number of NAND chips per device to be supported.
+
source "drivers/mtd/spi/Kconfig"
source "drivers/mtd/ubi/Kconfig"
* drivers and users.
*
* Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
- * Copyright © 2006 Red Hat UK Limited
+ * Copyright © 2006 Red Hat UK Limited
*
*/
} else {
*next = 0;
}
-
+
return ret;
}
* device name
* @name: MTD device name to open
*
- * This function returns MTD device description structure in case of
- * success and an error code in case of failure.
+ * This function returns MTD device description structure in case of
+ * success and an error code in case of failure.
*/
struct mtd_info *get_mtd_device_nm(const char *name)
{
config ATMEL_NAND_HWECC
bool "Atmel Hardware ECC"
- default n
config ATMEL_NAND_HW_PMECC
bool "Atmel Programmable Multibit ECC (PMECC)"
select ATMEL_NAND_HWECC
- default n
help
The Programmable Multibit ECC (PMECC) controller is a programmable
binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
bool "Atmel PMECC Header Generation"
select ATMEL_NAND_HWECC
select ATMEL_NAND_HW_PMECC
- default n
help
Generate Programmable Multibit ECC (PMECC) header for SPL image.
Enable this driver for NAND flash controllers available in TI Davinci
and Keystone2 platforms
+config KEYSTONE_RBL_NAND
+ depends on ARCH_KEYSTONE
+ def_bool y
+
+config SPL_NAND_LOAD
+ def_bool y
+ depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
+
config NAND_DENALI
bool
select SYS_NAND_SELF_INIT
Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device.
+config NAND_FSL_ELBC
+ bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
+ depends on FSL_ELBC
+ help
+ Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
+
+config NAND_FSL_IFC
+ bool "Support Freescale Integrated Flash Controller NAND driver"
+ help
+ Enable the Freescale Integrated Flash Controller NAND driver.
+
+config NAND_LPC32XX_MLC
+ bool "Support LPC32XX_MLC controller"
+ help
+ Enable the LPC32XX MLC NAND controller.
+
config NAND_LPC32XX_SLC
bool "Support LPC32XX_SLC controller"
help
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
and BCH16 ECC algorithms.
+if NAND_OMAP_GPMC
+
config NAND_OMAP_GPMC_PREFETCH
bool "Enable GPMC Prefetch"
- depends on NAND_OMAP_GPMC
default y
help
On OMAP platforms that use the GPMC controller
config NAND_OMAP_ELM
bool "Enable ELM driver for OMAPxx and AMxx platforms."
- depends on NAND_OMAP_GPMC && !OMAP34XX
+ depends on !OMAP34XX
help
ELM controller is used for ECC error detection (not ECC calculation)
of BCH4, BCH8 and BCH16 ECC algorithms.
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
+choice
+ prompt "ECC scheme"
+ default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ help
+ On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+ It can take following values:
+ OMAP_ECC_HAM1_CODE_SW
+ 1-bit Hamming code using software lib.
+ (for legacy devices only)
+ OMAP_ECC_HAM1_CODE_HW
+ 1-bit Hamming code using GPMC hardware.
+ (for legacy devices only)
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH4_CODE_HW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using software library.
+ - requires CONFIG_BCH to enable software BCH library
+ (For legacy device which do not have ELM h/w engine)
+ OMAP_ECC_BCH8_CODE_HW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+ OMAP_ECC_BCH16_CODE_HW
+ 16-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
+ How to select ECC scheme on OMAP and AMxx platforms ?
+ -----------------------------------------------------
+ Though higher ECC schemes have more capability to detect and correct
+ bit-flips, but still selection of ECC scheme is dependent on following
+ - hardware engines present in SoC.
+ Some legacy OMAP SoC do not have ELM h/w engine thus such
+ SoC cannot support BCHx_HW ECC schemes.
+ - size of OOB/Spare region
+ With higher ECC schemes, more OOB/Spare area is required to
+ store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+ In general following expression can help:
+ NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+ where
+ NAND_OOBSIZE = number of bytes available in
+ OOB/spare area per NAND page.
+ NAND_PAGESIZE = bytes in main-area of NAND page.
+ ECC_BYTES = number of ECC bytes generated to
+ protect 512 bytes of data, which is:
+ 3 for HAM1_xx ecc schemes
+ 7 for BCH4_xx ecc schemes
+ 14 for BCH8_xx ecc schemes
+ 26 for BCH16_xx ecc schemes
+
+ example to check for BCH16 on 2K page NAND
+ NAND_PAGESIZE = 2048
+ NAND_OOBSIZE = 64
+ 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+ Thus BCH16 cannot be supported on 2K page NAND.
+
+ However, for 4K pagesize NAND
+ NAND_PAGESIZE = 4096
+ NAND_OOBSIZE = 224
+ ECC_BYTES = 26
+ 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+ Thus BCH16 can be supported on 4K page NAND.
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+ bool "1-bit Hamming code using software lib"
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+ bool "1-bit Hamming code using GPMC hardware"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+ bool "8-bit BCH code with HW calculation SW error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ bool "8-bit BCH code with HW calculation and error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+ bool "16-bit BCH code with HW calculation and error detection"
+
+endchoice
+
+config NAND_OMAP_ECCSCHEME
+ int
+ default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+ default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+ default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+ default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+ help
+ This must be kept in sync with the enum in
+ include/linux/mtd/omap_gpmc.h
+
+endif
+
config NAND_VF610_NFC
bool "Support for Freescale NFC for VF610"
select SYS_NAND_SELF_INIT
config SYS_NAND_BLOCK_SIZE
hex "NAND chip eraseblock size"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
+ depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of data bytes in one eraseblock for the NAND chip on the
board. This is the multiple of NAND_PAGE_SIZE and the number of
pages.
+config SYS_NAND_ONFI_DETECTION
+ bool "Enable detection of ONFI compliant devices during probe"
+ help
+ Enables detection of ONFI compliant devices during probe.
+ And fetching device parameters flashed on device, by parsing
+ ONFI parameter page.
+
+config SYS_NAND_PAGE_COUNT
+ hex "NAND chip page count"
+ depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
+ SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
+ help
+ Number of pages in the NAND chip.
+
config SYS_NAND_PAGE_SIZE
hex "NAND chip page size"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
+ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
+ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
+ depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of data bytes in one page for the NAND chip on the
board, not including the OOB area.
config SYS_NAND_OOBSIZE
hex "NAND chip OOB size"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
+ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
+ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
+ depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of bytes in the Out-Of-Band area for the NAND chip on
the board.
not available while configuring controller. So a static CONFIG_NAND_xx
is needed to know the device's bus-width in advance.
-config SYS_NAND_MAX_CHIPS
- int "NAND max chips"
- default 1
- depends on NAND_ARASAN
+if SPL
+
+config SYS_NAND_5_ADDR_CYCLE
+ bool "Wait 5 address cycles during NAND commands"
+ depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
+ (SPL_NAND_SUPPORT && NAND_ATMEL)
+ default y
+ help
+ Some controllers require waiting for 5 address cycles when issuing
+ some commands, on NAND chips larger than 128MiB.
+
+choice
+ prompt "NAND bad block marker/indicator position in the OOB"
+ depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
+ SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
+ default HAS_NAND_LARGE_BADBLOCK_POS
help
- The maximum number of NAND chips per device to be supported.
+ In the OOB, which position contains the badblock information.
-if SPL
+config HAS_NAND_LARGE_BADBLOCK_POS
+ bool "Set the bad block marker/indicator to the 'large' position"
+
+config HAS_NAND_SMALL_BADBLOCK_POS
+ bool "Set the bad block marker/indicator to the 'small' position"
+
+endchoice
+
+config SYS_NAND_BAD_BLOCK_POS
+ int
+ default 0 if HAS_NAND_LARGE_BADBLOCK_POS
+ default 5 if HAS_NAND_SMALL_BADBLOCK_POS
config SYS_NAND_U_BOOT_LOCATIONS
bool "Define U-boot binaries locations in NAND"
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
#include <nand.h>
#include <watchdog.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
#ifdef CONFIG_ATMEL_NAND_HWECC
#include <linux/completion.h>
#include <linux/errno.h>
#include <linux/log2.h>
+#include <linux/mtd/rawnand.h>
#include <asm/processor.h>
#include <dm.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/errno.h>
+#include <linux/mtd/rawnand.h>
#include <asm/gpio.h>
#include <fdtdec.h>
#include <bouncebuf.h>
#include <common.h>
#include <log.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <nand.h>
#include <dm/uclass.h>
#define NAND_TIMEOUT 10240
#define NAND_ECC_BUSY 0xC
#define NAND_4BITECC_MASK 0x03FF03FF
-#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
+#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
#define ECC_STATE_NO_ERR 0x0
#define ECC_STATE_TOO_MANY_ERRS 0x1
#define ECC_STATE_ERR_CORR_COMP_P 0x2
};
#ifdef CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
+#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11)
#elif defined(CONFIG_SYS_NAND_PAGE_4K)
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
+#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12)
#endif
/**
struct nand_ecclayout *saved_ecc_layout;
/* save current ECC layout and assign Keystone RBL ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
saved_ecc_layout = chip->ecc.layout;
chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
mtd->oobavail = chip->ecc.layout->oobavail;
err:
/* restore ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = saved_ecc_layout;
mtd->oobavail = saved_ecc_layout->oobavail;
}
struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
/* save current ECC layout and assign Keystone RBL ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
mtd->oobavail = chip->ecc.layout->oobavail;
}
}
/* restore ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = saved_ecc_layout;
mtd->oobavail = saved_ecc_layout->oobavail;
}
nand->bbt_td = &bbt_main_descr;
nand->bbt_md = &bbt_mirror_descr;
- /* set up nand options */
+ /* set up nand options */
nand->options = NAND_NO_SUBPAGE_WRITE;
nand->bbt_options = NAND_BBT_USE_FLASH;
#include <common.h>
#include <cpu_func.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/fsl_lbc.h>
#include <nand.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/fsl_upm.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
*/
#include <common.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/arch/hardware.h>
*/
#include <common.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <nand.h>
#include <asm/io.h>
#include <linux/delay.h>
+#include <linux/mtd/rawnand.h>
#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
#include <nand.h>
#include <linux/delay.h>
#include <linux/errno.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/clk.h>
#include <nand.h>
#include <linux/bug.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/config.h>
#include <nand.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+#if defined(CONFIG_MX27) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
#define is_mxc_nfc_1() 1
#define is_mxc_nfc_21() 0
#define is_mxc_nfc_32() 0
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V2_1
-#define is_mxc_nfc_1() 0
-#define is_mxc_nfc_21() 1
-#define is_mxc_nfc_32() 0
#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
#define MXC_NFC_V3
#define MXC_NFC_V3_2
#include <common.h>
#include <hang.h>
#include <nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include "mxc_nand.h"
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/mtd/rawnand.h>
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
void nand_deselect(void)
{
}
-
#include <nand.h>
#include <errno.h>
#include <linux/mtd/concat.h>
+#include <linux/mtd/rawnand.h>
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
static void ioread16_rep(void *addr, void *buf, int len)
{
int i;
- u16 *p = (u16 *) buf;
+ u16 *p = (u16 *) buf;
for (i = 0; i < len; i++)
p[i] = readw(addr);
if (ret)
return ret;
- u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
- u32 time_start;
-
- time_start = get_timer(0);
- while (get_timer(time_start) < timer) {
+ u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
+ u32 time_start;
+
+ time_start = get_timer(0);
+ while (get_timer(time_start) < timer) {
if (chip->dev_ready) {
if (chip->dev_ready(mtd))
break;
LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
- LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
+ LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
#endif
*/
#include <common.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#ifdef NAND_PLAT_GPIO_DEV_READY
# include <asm/gpio.h>
#include <nand.h>
#include <asm/io.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
NAND_CTRL_ALE); /* A[24:17] */
-#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
- /* One more address cycle for devices > 32MiB */
- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
- NAND_CTRL_ALE); /* A[28:25] */
-#endif
/* Latch in address */
this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
#include <linux/errno.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#include <nand.h>
#include <jffs2/jffs2.h>
#define NAND_CMD_LOCK_TIGHT 0x2c
#define NAND_CMD_LOCK_STATUS 0x7a
-
+
/******************************************************************************
* Support for locking / unlocking operations of some NAND devices
*****************************************************************************/
return rval ? -EIO : 0;
}
-
-
/**
* nand_write_skip_bad:
*
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand_bch.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/mem.h>
#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
#include <linux/bch.h>
#include <linux/compiler.h>
#include <nand.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/rawnand.h>
#include <memalign.h>
#include <nand.h>
#include <linux/err.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
+#include <linux/mtd/rawnand.h>
/* Bad block marker length */
#define FMC2_BBM_LEN 2
#include <linux/bitops.h>
#include <linux/ctype.h>
#include <linux/delay.h>
+#include <linux/mtd/rawnand.h>
/* registers */
#define NFC_CTL 0x00000000
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/errno.h>
+#include <linux/mtd/rawnand.h>
#include <asm/gpio.h>
#include <fdtdec.h>
#include <bouncebuf.h>
#define STATUS_BYTE1_MASK 0x000000FF
/* NFC_FLASH_CONFIG Field */
-#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
-#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
-#define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
-#define CONFIG_DMA_REQ_BIT (1<<20)
-#define CONFIG_ECC_MODE_MASK 0x000E0000
-#define CONFIG_ECC_MODE_SHIFT 17
-#define CONFIG_FAST_FLASH_BIT (1<<16)
-#define CONFIG_16BIT (1<<7)
-#define CONFIG_BOOT_MODE_BIT (1<<6)
-#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
-#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
-#define CONFIG_PAGE_CNT_MASK 0xF
-#define CONFIG_PAGE_CNT_SHIFT 0
+#define CFG_ECC_SRAM_ADDR_MASK 0x7FC00000
+#define CFG_ECC_SRAM_ADDR_SHIFT 22
+#define CFG_ECC_SRAM_REQ_BIT (1<<21)
+#define CFG_DMA_REQ_BIT (1<<20)
+#define CFG_ECC_MODE_MASK 0x000E0000
+#define CFG_ECC_MODE_SHIFT 17
+#define CFG_FAST_FLASH_BIT (1<<16)
+#define CFG_16BIT (1<<7)
+#define CFG_BOOT_MODE_BIT (1<<6)
+#define CFG_ADDR_AUTO_INCR_BIT (1<<5)
+#define CFG_BUFNO_AUTO_INCR_BIT (1<<4)
+#define CFG_PAGE_CNT_MASK 0xF
+#define CFG_PAGE_CNT_SHIFT 0
/* NFC_IRQ_STATUS Field */
#define IDLE_IRQ_BIT (1<<29)
static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
{
vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
- CONFIG_ECC_MODE_MASK,
- CONFIG_ECC_MODE_SHIFT, ecc_mode);
+ CFG_ECC_MODE_MASK,
+ CFG_ECC_MODE_SHIFT, ecc_mode);
}
static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
chip->ecc.size = PAGE_2K;
/* Set configuration register. */
- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
- vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
+ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_16BIT);
+ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_ADDR_AUTO_INCR_BIT);
+ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BUFNO_AUTO_INCR_BIT);
+ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BOOT_MODE_BIT);
+ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_DMA_REQ_BIT);
+ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_FAST_FLASH_BIT);
/* Disable virtual pages, only one elementary transfer unit */
- vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
- CONFIG_PAGE_CNT_SHIFT, 1);
+ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CFG_PAGE_CNT_MASK,
+ CFG_PAGE_CNT_SHIFT, 1);
/* first scan to find the device and get the page size */
if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
}
if (cfg.width == 16)
- vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
+ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_16BIT);
/* Bad block options. */
if (cfg.flash_bbt)
/* Set ECC_STATUS offset */
vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
- CONFIG_ECC_SRAM_ADDR_MASK,
- CONFIG_ECC_SRAM_ADDR_SHIFT,
+ CFG_ECC_SRAM_ADDR_MASK,
+ CFG_ECC_SRAM_ADDR_SHIFT,
ECC_SRAM_ADDR >> 3);
/* Enable ECC status in SRAM */
- vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
+ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_ECC_SRAM_REQ_BIT);
}
/* second phase scan */
/**
* flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
- * boundary[], diesize[], mtd->size, mtd->erasesize,
- * mtd->eraseregions
+ * boundary[], diesize[], mtd->size, mtd->erasesize,
+ * mtd->eraseregions
* @param mtd - MTD device structure
*/
static void flexonenand_get_size(struct mtd_info *mtd)
config SPI_FLASH_SOFT_RESET
bool "Software Reset support for SPI NOR flashes"
- default n
help
Enable support for xSPI Software Reset. It will be used to switch from
Octal DTR mode to legacy mode on shutdown and boot (if enabled).
config SPI_FLASH_SOFT_RESET_ON_BOOT
bool "Perform a Software Reset on boot on flashes that boot in stateful mode"
depends on SPI_FLASH_SOFT_RESET
- default n
help
Perform a Software Reset on boot to allow detecting flashes that are
handed to us in Octal DTR mode. Do not enable this config on flashes
{ INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
- { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
+ { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
/* EON -- en25xxx */
config MTD_UBI_FASTMAP
bool "UBI Fastmap (Experimental feature)"
- default n
help
Important: this feature is experimental so far and the on-flash
format for fastmap may change in the next kernel versions
#else
struct ubi_device *ubi_devices[UBI_MAX_DEVICES];
#endif
-
+
#ifndef __UBOOT__
/* Serializes UBI devices creations and removals */
DEFINE_MUTEX(ubi_devices_mutex);
*
* A big-endian CRC written this way would be coded like:
* for (i = 0; i < input_bits; i++) {
- * multiple = remainder & 0x80000000 ? CRCPOLY : 0;
- * remainder = (remainder << 1 | next_input_bit()) ^ multiple;
+ * multiple = remainder & 0x80000000 ? CRCPOLY : 0;
+ * remainder = (remainder << 1 | next_input_bit()) ^ multiple;
* }
* Notice how, to get at bit 32 of the shifted remainder, we look
* at bit 31 of the remainder *before* shifting it.
* This changes the code to:
* for (i = 0; i < input_bits; i++) {
* remainder ^= next_input_bit() << 31;
- * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
- * remainder = (remainder << 1) ^ multiple;
+ * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
+ * remainder = (remainder << 1) ^ multiple;
* }
* With this optimization, the little-endian code is simpler:
* for (i = 0; i < input_bits; i++) {
* remainder ^= next_input_bit();
- * multiple = (remainder & 1) ? CRCPOLY : 0;
- * remainder = (remainder >> 1) ^ multiple;
+ * multiple = (remainder & 1) ? CRCPOLY : 0;
+ * remainder = (remainder >> 1) ^ multiple;
* }
*
* Note that the other details of endianness have been hidden in CRCPOLY
* order, we can actually do the merging 8 or more bits at a time rather
* than one bit at a time:
* for (i = 0; i < input_bytes; i++) {
- * remainder ^= next_input_byte() << 24;
- * for (j = 0; j < 8; j++) {
- * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
- * remainder = (remainder << 1) ^ multiple;
- * }
+ * remainder ^= next_input_byte() << 24;
+ * for (j = 0; j < 8; j++) {
+ * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
+ * remainder = (remainder << 1) ^ multiple;
+ * }
* }
* Or in little-endian:
* for (i = 0; i < input_bytes; i++) {
- * remainder ^= next_input_byte();
- * for (j = 0; j < 8; j++) {
- * multiple = (remainder & 1) ? CRCPOLY : 0;
- * remainder = (remainder << 1) ^ multiple;
- * }
+ * remainder ^= next_input_byte();
+ * for (j = 0; j < 8; j++) {
+ * multiple = (remainder & 1) ? CRCPOLY : 0;
+ * remainder = (remainder << 1) ^ multiple;
+ * }
* }
* If the input is a multiple of 32 bits, you can even XOR in a 32-bit
* word at a time and increase the inner loop count to 32.
source "drivers/net/pfe_eth/Kconfig"
source "drivers/net/fsl-mc/Kconfig"
+config ETH
+ def_bool y
+
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
depends on DM
config SMC911X_32_BIT
bool "Enable SMC911X 32-bit interface"
- default n
help
Define this if data bus is 32 bits. If your processor use a
narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit
config PHY_NORXERR
bool "PHY_NORXERR"
depends on ETHER_ON_FEC1
- default n
help
The PHY does not have a RXERR line (RMII only).
(so program the FEC to ignore it).
config FEC2_PHY_NORXERR
bool "PHY_NORXERR"
depends on ETHER_ON_FEC2
- default n
help
The PHY does not have a RXERR line (RMII only).
(so program the FEC to ignore it).
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+obj-y += phy/
+
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
obj-$(CONFIG_BCMGENET) += bcmgenet.o
-obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
+obj-$(CONFIG_FMAN_ENET) += fm/
obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC110) += ftmac110.o
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smi_reg_read;
mdiodev->write = smi_reg_write;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
- * Jens Scharsig (esw@bus-elektronik.de)
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_emac.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/at91_pio.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
-#error AT91 EMAC supports max 1024 RX buffers. \
- Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
-#endif
-
-#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
-#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
-#endif
-
-/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
-#if (AT91C_MASTER_CLOCK > 80000000)
- #define HCLK_DIV AT91_EMAC_CFG_MCLK_64
-#elif (AT91C_MASTER_CLOCK > 40000000)
- #define HCLK_DIV AT91_EMAC_CFG_MCLK_32
-#elif (AT91C_MASTER_CLOCK > 20000000)
- #define HCLK_DIV AT91_EMAC_CFG_MCLK_16
-#else
- #define HCLK_DIV AT91_EMAC_CFG_MCLK_8
-#endif
-
-#ifdef ET_DEBUG
-#define DEBUG_AT91EMAC 1
-#else
-#define DEBUG_AT91EMAC 0
-#endif
-
-#ifdef MII_DEBUG
-#define DEBUG_AT91PHY 1
-#else
-#define DEBUG_AT91PHY 0
-#endif
-
-#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
-#define VERBOSEP 1
-#else
-#define VERBOSEP 0
-#endif
-
-#define RBF_ADDR 0xfffffffc
-#define RBF_OWNER (1<<0)
-#define RBF_WRAP (1<<1)
-#define RBF_BROADCAST (1<<31)
-#define RBF_MULTICAST (1<<30)
-#define RBF_UNICAST (1<<29)
-#define RBF_EXTERNAL (1<<28)
-#define RBF_UNKNOWN (1<<27)
-#define RBF_SIZE 0x07ff
-#define RBF_LOCAL4 (1<<26)
-#define RBF_LOCAL3 (1<<25)
-#define RBF_LOCAL2 (1<<24)
-#define RBF_LOCAL1 (1<<23)
-
-#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
-#define RBF_FRAMELEN 0x600
-
-typedef struct {
- unsigned long addr, size;
-} rbf_t;
-
-typedef struct {
- rbf_t rbfdt[RBF_FRAMEMAX];
- unsigned long rbindex;
-} emac_device;
-
-void at91emac_EnableMDIO(at91_emac_t *at91mac)
-{
- /* Mac CTRL reg set for MDIO enable */
- writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
-}
-
-void at91emac_DisableMDIO(at91_emac_t *at91mac)
-{
- /* Mac CTRL reg set for MDIO disable */
- writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
-}
-
-int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
- unsigned char reg, unsigned short *value)
-{
- unsigned long netstat;
- at91emac_EnableMDIO(at91mac);
-
- writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
- AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
- AT91_EMAC_MAN_PHYA(addr),
- &at91mac->man);
-
- do {
- netstat = readl(&at91mac->sr);
- debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
- } while (!(netstat & AT91_EMAC_SR_IDLE));
-
- *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
-
- at91emac_DisableMDIO(at91mac);
-
- debug_cond(DEBUG_AT91PHY,
- "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
-
- return 0;
-}
-
-int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- unsigned long netstat;
- debug_cond(DEBUG_AT91PHY,
- "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
-
- at91emac_EnableMDIO(at91mac);
-
- writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
- AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
- AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
- &at91mac->man);
-
- do {
- netstat = readl(&at91mac->sr);
- debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
- } while (!(netstat & AT91_EMAC_SR_IDLE));
-
- at91emac_DisableMDIO(at91mac);
-
- return 0;
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-
-at91_emac_t *get_emacbase_by_name(const char *devname)
-{
- struct eth_device *netdev;
-
- netdev = eth_get_dev_by_name(devname);
- return (at91_emac_t *) netdev->iobase;
-}
-
-int at91emac_mii_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- unsigned short value = 0;
- at91_emac_t *emac;
-
- emac = get_emacbase_by_name(bus->name);
- at91emac_read(emac , addr, reg, &value);
- return value;
-}
-
-
-int at91emac_mii_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 value)
-{
- at91_emac_t *emac;
-
- emac = get_emacbase_by_name(bus->name);
- at91emac_write(emac, addr, reg, value);
- return 0;
-}
-
-#endif
-
-static int at91emac_phy_reset(struct eth_device *netdev)
-{
- int i;
- u16 status, adv;
- at91_emac_t *emac;
-
- emac = (at91_emac_t *) netdev->iobase;
-
- adv = ADVERTISE_CSMA | ADVERTISE_ALL;
- at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_ADVERTISE, adv);
- debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
- at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
- (BMCR_ANENABLE | BMCR_ANRESTART));
-
- for (i = 0; i < 30000; i++) {
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_BMSR, &status);
- if (status & BMSR_ANEGCOMPLETE)
- break;
- udelay(100);
- }
-
- if (status & BMSR_ANEGCOMPLETE) {
- debug_cond(VERBOSEP,
- "%s: Autonegotiation complete\n", netdev->name);
- } else {
- printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- netdev->name, status);
- return -1;
- }
- return 0;
-}
-
-static int at91emac_phy_init(struct eth_device *netdev)
-{
- u16 phy_id, status, adv, lpa;
- int media, speed, duplex;
- int i;
- at91_emac_t *emac;
-
- emac = (at91_emac_t *) netdev->iobase;
-
- /* Check if the PHY is up to snuff... */
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_PHYSID1, &phy_id);
- if (phy_id == 0xffff) {
- printf("%s: No PHY present\n", netdev->name);
- return -1;
- }
-
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_BMSR, &status);
-
- if (!(status & BMSR_LSTATUS)) {
- /* Try to re-negotiate if we don't have link already. */
- if (at91emac_phy_reset(netdev))
- return -2;
-
- for (i = 0; i < 100000 / 100; i++) {
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_BMSR, &status);
- if (status & BMSR_LSTATUS)
- break;
- udelay(100);
- }
- }
- if (!(status & BMSR_LSTATUS)) {
- debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
- return -3;
- } else {
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_ADVERTISE, &adv);
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
- MII_LPA, &lpa);
- media = mii_nway_result(lpa & adv);
- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
- ? 1 : 0);
- duplex = (media & ADVERTISE_FULL) ? 1 : 0;
- debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
- netdev->name,
- speed ? "100" : "10",
- duplex ? "full" : "half");
- }
- return 0;
-}
-
-int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
-{
- unsigned short stat1;
-
- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
-
- if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
- return -1;
-
- if (stat1 & BMSR_100FULL) {
- /*set Emac for 100BaseTX and Full Duplex */
- writel(readl(&emac->cfg) |
- AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
- &emac->cfg);
- return 0;
- }
-
- if (stat1 & BMSR_10FULL) {
- /*set MII for 10BaseT and Full Duplex */
- writel((readl(&emac->cfg) &
- ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
- ) | AT91_EMAC_CFG_FD,
- &emac->cfg);
- return 0;
- }
-
- if (stat1 & BMSR_100HALF) {
- /*set MII for 100BaseTX and Half Duplex */
- writel((readl(&emac->cfg) &
- ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
- ) | AT91_EMAC_CFG_SPD,
- &emac->cfg);
- return 0;
- }
-
- if (stat1 & BMSR_10HALF) {
- /*set MII for 10BaseT and Half Duplex */
- writel((readl(&emac->cfg) &
- ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
- &emac->cfg);
- return 0;
- }
- return 0;
-}
-
-static int at91emac_init(struct eth_device *netdev, struct bd_info *bd)
-{
- int i;
- u32 value;
- emac_device *dev;
- at91_emac_t *emac;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- emac = (at91_emac_t *) netdev->iobase;
- dev = (emac_device *) netdev->priv;
-
- /* PIO Disable Register */
- value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC |
- ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 |
- ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS |
- ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 |
- ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
-
- writel(value, &pio->pioa.pdr);
- writel(value, &pio->pioa.mux.pio2.asr);
-
-#ifdef CONFIG_RMII
- value = ATMEL_PMX_BA_ERXCK;
-#else
- value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL |
- ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 |
- ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER |
- ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
-#endif
- writel(value, &pio->piob.pdr);
- writel(value, &pio->piob.mux.pio2.bsr);
-
- at91_periph_clk_enable(ATMEL_ID_EMAC);
-
- writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
-
- /* Init Ethernet buffers */
- for (i = 0; i < RBF_FRAMEMAX; i++) {
- dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i];
- dev->rbfdt[i].size = 0;
- }
- dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
- dev->rbindex = 0;
- writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
-
- writel(readl(&emac->rsr) &
- ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
- &emac->rsr);
-
- value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
- HCLK_DIV;
-#ifdef CONFIG_RMII
- value |= AT91_EMAC_CFG_RMII;
-#endif
- writel(value, &emac->cfg);
-
- writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
- &emac->ctl);
-
- if (!at91emac_phy_init(netdev)) {
- at91emac_UpdateLinkSpeed(emac);
- return 0;
- }
- return -1;
-}
-
-static void at91emac_halt(struct eth_device *netdev)
-{
- at91_emac_t *emac;
-
- emac = (at91_emac_t *) netdev->iobase;
- writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
- &emac->ctl);
- debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
-}
-
-static int at91emac_send(struct eth_device *netdev, void *packet, int length)
-{
- at91_emac_t *emac;
-
- emac = (at91_emac_t *) netdev->iobase;
-
- while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
- ;
- writel((u32) packet, &emac->tar);
- writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
- while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
- ;
- debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
- writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
- return 0;
-}
-
-static int at91emac_recv(struct eth_device *netdev)
-{
- emac_device *dev;
- at91_emac_t *emac;
- rbf_t *rbfp;
- int size;
-
- emac = (at91_emac_t *) netdev->iobase;
- dev = (emac_device *) netdev->priv;
-
- rbfp = &dev->rbfdt[dev->rbindex];
- while (rbfp->addr & RBF_OWNER) {
- size = rbfp->size & RBF_SIZE;
- net_process_received_packet(net_rx_packets[dev->rbindex], size);
-
- debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
- dev->rbindex, size, rbfp->addr);
-
- rbfp->addr &= ~RBF_OWNER;
- rbfp->size = 0;
- if (dev->rbindex < (RBF_FRAMEMAX-1))
- dev->rbindex++;
- else
- dev->rbindex = 0;
-
- rbfp = &(dev->rbfdt[dev->rbindex]);
- if (!(rbfp->addr & RBF_OWNER))
- writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
- &emac->rsr);
- }
-
- if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
- /* EMAC silicon bug 41.3.1 workaround 1 */
- writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
- writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
- dev->rbindex = 0;
- printf("%s: reset receiver (EMAC dead lock bug)\n",
- netdev->name);
- }
- return 0;
-}
-
-static int at91emac_write_hwaddr(struct eth_device *netdev)
-{
- at91_emac_t *emac;
- emac = (at91_emac_t *) netdev->iobase;
-
- at91_periph_clk_enable(ATMEL_ID_EMAC);
-
- debug_cond(DEBUG_AT91EMAC,
- "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
- netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
- netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
- writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
- netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
- &emac->sa2l);
- writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
- debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
- readl(&emac->sa2h), readl(&emac->sa2l));
- return 0;
-}
-
-int at91emac_register(struct bd_info *bis, unsigned long iobase)
-{
- emac_device *emac;
- emac_device *emacfix;
- struct eth_device *dev;
-
- if (iobase == 0)
- iobase = ATMEL_BASE_EMAC;
- emac = malloc(sizeof(*emac)+512);
- if (emac == NULL)
- return -1;
- dev = malloc(sizeof(*dev));
- if (dev == NULL) {
- free(emac);
- return -1;
- }
- /* alignment as per Errata (64 bytes) is insufficient! */
- emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
- memset(emacfix, 0, sizeof(emac_device));
-
- memset(dev, 0, sizeof(*dev));
- strcpy(dev->name, "emac");
- dev->iobase = iobase;
- dev->priv = emacfix;
- dev->init = at91emac_init;
- dev->halt = at91emac_halt;
- dev->send = at91emac_send;
- dev->recv = at91emac_recv;
- dev->write_hwaddr = at91emac_write_hwaddr;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = at91emac_mii_read;
- mdiodev->write = at91emac_mii_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
- return 1;
-}
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = eth->miiphy_read;
mdiodev->write = eth->miiphy_write;
.start = xgmac_eth_start,
.send = xgmac_tx,
.recv = xgmac_rx,
- .free_pkt = xgmac_free_pkt,
+ .free_pkt = xgmac_free_pkt,
.stop = xgmac_eth_stop,
.write_hwaddr = xgmac_eth_write_hwaddr,
.read_rom_hwaddr = xgmac_eth_read_rom_hwaddr,
--------------------------------------
12/15/2003 Initial port to u-boot by
- Sascha Hauer <saschahauer@web.de>
+ Sascha Hauer <saschahauer@web.de>
06/03/2008 Remy Bohmer <linux@bohmer.net>
- Fixed the driver to work with DM9000A.
#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
#define DM9000_DMP_PACKET(func,packet,length) \
do { \
- int i; \
+ int i; \
printf("%s: length: %d\n", func, length); \
for (i = 0; i < length; i++) { \
if (i % 8 == 0) \
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
#include <asm/eth.h>
mdelay(20);
}
-
-
E1000_WRITE_REG(hw, TCTL, tctl);
-
-
}
/**
#define E1000_ERR_MASTER_REQUESTS_PENDING 10
#define E1000_ERR_HOST_INTERFACE_COMMAND 11
#define E1000_BLK_PHY_RESET 12
-#define E1000_ERR_SWFW_SYNC 13
+#define E1000_ERR_SWFW_SYNC 13
/* PCI Device IDs */
#define E1000_DEV_ID_82542 0x1000
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
mdiodev->read = eepro100_miiphy_read;
mdiodev->write = eepro100_miiphy_write;
mdiodev->priv = priv;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
mdiodev->read = ep93xx_miiphy_read;
mdiodev->write = ep93xx_miiphy_write;
&fec->eth->ecntrl);
#endif
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100);
/* setup the MII gasket for RMII mode */
uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
#define FEC_X_DES_ACTIVE_TDAR 0x01000000
#define FEC_R_DES_ACTIVE_RDAR 0x01000000
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
/* defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */
#define MIIGSK_CFGR_FRCONT (1 << 6)
env_get_f("hwconfig", buffer, sizeof(buffer));
buf = buffer;
- /* check if XFI interface enable in hwconfig for 10g */
+ /* check if 10GBase-R interface enable in hwconfig for 10g */
if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
"sfp_amc", "sfp", buf)) {
if ((port == FM1_10GEC1 ||
u32 value;
struct mii_dev bus;
bool sgmii_2500 = (priv->enet_if ==
- PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+ PHY_INTERFACE_MODE_2500BASEX) ? true : false;
int i = 0, j;
#ifndef CONFIG_DM_ETH
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
- fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+ fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
dtsec_configure_serdes(fm_eth);
}
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
- (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
+ (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
if (fm_eth->type == FM_ETH_10G_E)
supported = PHY_10G_FEATURES;
- if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+ if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
supported |= SUPPORTED_2500baseX_Full;
#endif
if (fm_eth->num != 0)
break;
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
break;
default:
case FM1_DTSEC2:
if ((port == FM1_DTSEC2) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC2))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
return PHY_INTERFACE_MODE_SGMII;
else if ((port == FM1_DTSEC9) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC9))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
port - FM1_DTSEC5))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= IF_MODE_XGMII;
break;
}
/* Enable automatic speed selection for Non-XGMII */
- if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI)
+ if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER)
if_mode |= IF_MODE_EN_AUTO;
if (type == PHY_INTERFACE_MODE_RGMII ||
return PHY_INTERFACE_MODE_SGMII;
else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+ port - FM1_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
-
if (!enetc_has_imdio(dev))
return 0;
- if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
+ if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX)
is2500 = true;
/*
case PHY_INTERFACE_MODE_RGMII_TXID:
enetc_init_rgmii(dev, phydev);
break;
- case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_USXGMII:
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
/* set ifmode to (US)XGMII */
if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
priv->imdio.read = enetc_mdio_read;
priv->imdio.write = enetc_mdio_write;
priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
- strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+ strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
if (!miiphy_get_dev_by_name(priv->imdio.name))
mdio_register(&priv->imdio);
}
switch (priv->if_type) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
enetc_init_sgmii(dev);
break;
- case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_USXGMII:
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
enetc_init_sxgmii(dev);
break;
};
info->bus = mdio_alloc();
if (!info->bus)
return -ENOMEM;
- strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
info->bus->read = mcffec_miiphy_read;
info->bus->write = mcffec_miiphy_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = ftmac110_mdio_read;
mdiodev->write = ftmac110_mdio_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = mii_reg_read;
mdiodev->write = mii_reg_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
mdiodev->read = macb_miiphy_read;
mdiodev->write = macb_miiphy_write;
macb->bus = mdio_alloc();
if (!macb->bus)
return -ENOMEM;
- strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
macb->bus->read = macb_miiphy_read;
macb->bus->write = macb_miiphy_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = fec8xx_miiphy_read;
mdiodev->write = fec8xx_miiphy_write;
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Felix (VSC9959) Ethernet switch driver
- * Copyright 2018-2021 NXP Semiconductors
+ * Copyright 2018-2021 NXP
*/
/*
bool autoneg = true;
if (phy->phy_id == PHY_FIXED_ID ||
- phy->interface == PHY_INTERFACE_MODE_SGMII_2500)
+ phy->interface == PHY_INTERFACE_MODE_2500BASEX)
autoneg = false;
switch (phy->interface) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
felix_init_sgmii(imdio, port, autoneg);
break;
- case PHY_INTERFACE_MODE_XGMII:
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
if (felix_init_sxgmii(imdio, port))
dev_err(dev, "PCS reset timeout on port %d\n", port);
}
}
-void felix_init(struct udevice *dev)
+static void felix_init(struct udevice *dev)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct felix_priv *priv = dev_get_priv(dev);
priv->imdio.read = felix_mdio_read;
priv->imdio.write = felix_mdio_write;
priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
- strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+ strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
/* set up CPU port */
out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG,
static int felix_probe(struct udevice *dev)
{
struct felix_priv *priv = dev_get_priv(dev);
+ int err;
if (ofnode_valid(dev_ofnode(dev)) &&
!ofnode_is_available(dev_ofnode(dev))) {
struct mii_dev *mii_bus;
mii_bus = mdio_alloc();
+ if (!mii_bus)
+ return -ENOMEM;
+
mii_bus->read = felix_mdio_read;
mii_bus->write = felix_mdio_write;
mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
- strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
- mdio_register(mii_bus);
+ strlcpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
+ err = mdio_register(mii_bus);
+ if (err) {
+ mdio_free(mii_bus);
+ return err;
+ }
}
dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
return 0;
}
+static int felix_port_probe(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
+ struct felix_priv *priv = dev_get_priv(dev);
+
+ phy->supported &= supported;
+ phy->advertising &= supported;
+
+ felix_start_pcs(dev, port, phy, &priv->imdio);
+
+ return phy_config(phy);
+}
+
static int felix_port_enable(struct udevice *dev, int port,
struct phy_device *phy)
{
- int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
struct felix_priv *priv = dev_get_priv(dev);
void *base = priv->regs_base;
FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
- felix_start_pcs(dev, port, phy, &priv->imdio);
-
- phy->supported &= supported;
- phy->advertising &= supported;
- phy_config(phy);
-
- phy_startup(phy);
-
- return 0;
+ return phy_startup(phy);
}
static void felix_port_disable(struct udevice *dev, int pidx,
}
static const struct dsa_ops felix_dsa_ops = {
+ .port_probe = felix_port_probe,
.port_enable = felix_port_enable,
.port_disable = felix_port_disable,
.xmit = felix_xmit,
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smi_reg_read;
mdiodev->write = smi_reg_write;
.ops = &mvmdio_ops,
.priv_auto = sizeof(struct mvmdio_priv),
};
-
};
U_BOOT_PCI_DEVICE(octeontx_nic, octeontx_nic_supported);
-
obj-$(CONFIG_NET_OCTEONTX2) += cgx.o nix_af.o nix.o rvu_pf.o \
rvu_af.o rvu_common.o
-
printf(" CGX%d LMAC%d [%s]", lmac->cgx->cgx_id, lmac->lmac_id,
lmac_type_to_str[lmac->lmac_type]);
}
-
}
#endif /* __NPC_H__ */
-
void rvu_get_lfid_for_pf(int pf, int *nixid, int *npaid);
#endif /* __RVU_H__ */
-
int value, sgmii_2500 = 0;
struct gemac_s *gem = priv->gem;
- if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
+ if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX)
sgmii_2500 = 1;
/* Configure SGMII PCS */
if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
- gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
+ gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
out_be32(&scfg->mdioselcr, 0x00000000);
pfe_configure_serdes(priv);
}
config PHY_AQUANTIA_UPLOAD_FW
bool "Aquantia firmware loading support"
- default n
depends on PHY_AQUANTIA
help
Aquantia PHYs use firmware which can be either loaded automatically
config SYS_CORTINA_NO_FW_UPLOAD
bool "Cortina firmware loading support"
- default n
depends on PHY_CORTINA
help
Cortina phy has provision to store phy firmware in attached dedicated
config RTL8211F_PHY_FORCE_EEE_RXC_ON
bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
depends on PHY_REALTEK
- default n
help
The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
transitions to/from a lower power consumption level (Low Power Idle
} aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
[PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
AQUANTIA_VND1_GSTART_RATE_1G},
- [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
+ [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
AQUANTIA_VND1_GSTART_RATE_2_5G},
- [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
+ [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
[PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
return ret;
}
/*
- * for backward compatibility convert XGMII into either XFI or USX based
- * on FW config
+ * for backward compatibility convert XGMII into either 10GBase-R or
+ * USXGMII based on FW config
*/
if (interface == PHY_INTERFACE_MODE_XGMII) {
- debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
+ debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n");
reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
AQUANTIA_SYSTEM_INTERFACE_SR);
if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
interface = PHY_INTERFACE_MODE_USXGMII;
else
- interface = PHY_INTERFACE_MODE_XFI;
+ interface = PHY_INTERFACE_MODE_10GBASER;
}
/*
case PHY_INTERFACE_MODE_USXGMII:
usx_an = 1;
/* FALLTHROUGH */
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
/* 10GBASE-T mode */
phydev->advertising = SUPPORTED_10000baseT_Full;
phydev->supported = phydev->advertising;
phydev->dev->name);
} else {
reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
- debug("%s: system interface XFI\n",
+ debug("%s: system interface 10GBase-R\n",
phydev->dev->name);
}
phy_write(phydev, MDIO_MMD_PHYXS,
AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
break;
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;
if (!(wol & BIT(12)) ||
((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
-
+
/* Looks like aneg failed after all */
if (!retries) {
printf("%s LPA corruption max attempts\n",
.shutdown = genphy_shutdown,
};
-int genphy_init(void)
+static int genphy_init(void)
{
return phy_register(&genphy_driver);
}
mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
* We have only 16 Bit PCMCIA access on Socket 0
*/
-#ifdef CONFIG_ADNPESC1
-#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
-#elif CONFIG_ARM64
+#if CONFIG_ARM64
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
#else
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
#endif
#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
-#ifdef CONFIG_ADNPESC1
-#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
-#elif CONFIG_ARM64
+#if CONFIG_ARM64
#define SMC_outw(a, d, r) \
(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
#else
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
| (RPC_LED_100_10 << RPC_LSXB_SHFT) )
-#elif defined(CONFIG_ADNPESC1)
-/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
-#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
- | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
- | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
#else
/* SMSC reference design: LEDa --> green, LEDb --> yellow */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
mdiodev->read = smc911x_miiphy_read;
mdiodev->write = smc911x_miiphy_write;
/* Below are the register offsets and bit definitions
* of the Lan911x memory space
*/
-#define RX_DATA_FIFO 0x00
+#define RX_DATA_FIFO 0x00
-#define TX_DATA_FIFO 0x20
+#define TX_DATA_FIFO 0x20
#define TX_CMD_A_INT_ON_COMP 0x80000000
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <wait_bit.h>
-#if CONFIG_IS_ENABLED(DM_GPIO)
-#include <asm-generic/gpio.h>
-#endif
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
}
#define cache_clean_descriptor(desc) \
- flush_dcache_range((uintptr_t)(desc), \
+ flush_dcache_range((uintptr_t)(desc), \
(uintptr_t)(desc) + sizeof(struct emac_dma_desc))
#define cache_inv_descriptor(desc) \
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
mdiodev->read = davinci_mii_phy_read;
mdiodev->write = davinci_mii_phy_write;
return priv->phydev->link ? 0 : -1;
}
-static phy_interface_t tsec_get_interface(struct tsec_private *priv)
+static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
{
struct tsec __iomem *regs = priv->regs;
u32 ecntrl;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, priv->tbiaddr);
- priv->interface = tsec_get_interface(priv);
-
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
priv->tbiaddr = tbiaddr;
phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
+ if (!phy_mode)
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- printf("Invalid PHY interface '%s'\n", phy_mode);
- return -EINVAL;
- }
+ if (pdata->phy_interface == -1)
+ pdata->phy_interface = tsec_get_interface(priv);
+
priv->interface = pdata->phy_interface;
/* Check for speed limit, default is 1000Mbps */
UCLASS_DRIVER(pch) = {
.id = UCLASS_PCH,
.name = "pch",
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
config PCI_AARDVARK
bool "Enable Aardvark PCIe driver"
- default n
depends on DM_GPIO
depends on ARMADA_3700
help
config PCI_REGION_MULTI_ENTRY
bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
- default n
help
Enable PCI memory regions to be of multiple entry. Multiple entry
here refers to allow more than one count of address ranges for MEMORY
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
depends on MIPS
- default n
help
Say Y if base address of system memory is being used as a virtual address
instead of a physical address (e.g. on MIPS). The PCI core will then remap
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
- default n
help
Say Y here if you want to enable PCI Single Root I/O Virtualization
capability support. This helps to enumerate Virtual Function devices
config PCI_ARID
bool "Enable Alternate Routing-ID support for PCI"
- default n
help
Say Y here if you want to enable Alternate Routing-ID capability
support on PCI devices. This helps to skip some devices in BDF
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
- default n
help
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
config PCIE_ECAM_SYNQUACER
bool "SynQuacer ECAM-based PCI host controller support"
- default n
select PCI_INIT_R
select PCI_REGION_MULTI_ENTRY
help
config PCIE_LAYERSCAPE
bool
- default n
config PCIE_LAYERSCAPE_RC
bool "Layerscape PCIe Root Complex mode support"
setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
#endif
- return busno;
+ return busno;
}
#else
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
+#define PCIE_CORE_DEV_REV_REG 0x8
+#define PCIE_CORE_EXP_ROM_BAR_REG 0x30
+#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define LTSSM_SHIFT 24
#define LTSSM_MASK 0x3f
#define LTSSM_L0 0x10
+#define LTSSM_DISABLED 0x20
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
/* PCIe core controller registers */
#define PCIE_CONFIG_WR_TYPE1 0xb
/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev) (dev << 4)
+#define PCIE_BDF(b, d, f) (PCI_BDF(b, d, f) << 4)
#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
/**
* struct pcie_advk - Advk PCIe controller state
*
- * @reg_base: The base address of the register space.
- * @first_busno: This driver supports multiple PCIe controllers.
- * first_busno stores the bus number of the PCIe root-port
- * number which may vary depending on the PCIe setup
- * (PEX switches etc).
- * @device: The pointer to PCI uclass device.
+ * @base: The base address of the register space.
+ * @first_busno: Bus number of the PCIe root-port.
+ * This may vary depending on the PCIe setup.
+ * @sec_busno: Bus number for the device behind the PCIe root-port.
+ * @dev: The pointer to PCI uclass device.
+ * @reset_gpio: GPIO descriptor for PERST.
+ * @cfgcache: Buffer for emulation of PCIe Root Port's PCI Bridge registers
+ * that are not available on Aardvark.
+ * @cfgcrssve: For CRSSVE emulation.
*/
struct pcie_advk {
- void *base;
- int first_busno;
- struct udevice *dev;
- struct gpio_desc reset_gpio;
+ void *base;
+ int first_busno;
+ int sec_busno;
+ struct udevice *dev;
+ struct gpio_desc reset_gpio;
+ u32 cfgcache[0x34 - 0x10];
+ bool cfgcrssve;
};
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
/**
* pcie_advk_addr_valid() - Check for valid bus address
*
+ * @pcie: Pointer to the PCI bus
+ * @busno: Bus number of PCI device
+ * @dev: Device number of PCI device
+ * @func: Function number of PCI device
* @bdf: The PCI device to access
- * @first_busno: Bus number of the PCIe controller root complex
*
- * Return: 1 on valid, 0 on invalid
+ * Return: true on valid, false on invalid
*/
-static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
+static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
+ int busno, u8 dev, u8 func)
{
+ /* On the primary (local) bus there is only one PCI Bridge */
+ if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ return false;
+
/*
- * In PCIE-E only a single device (0) can exist
- * on the local bus. Beyound the local bus, there might be
- * a Switch and everything is possible.
+ * In PCI-E only a single device (0) can exist on the secondary bus.
+ * Beyond the secondary bus, there might be a Switch and anything is
+ * possible.
*/
- if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
- return 0;
+ if (busno == pcie->sec_busno && dev != 0)
+ return false;
- return 1;
+ return true;
}
/**
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
int retry_count;
bool allow_crs;
+ ulong data;
uint reg;
int ret;
dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
dev_dbg(pcie->dev, "- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
/*
+ * The configuration space of the PCI Bridge on primary (local) bus is
+ * not accessible via PIO transfers like all other PCIe devices. PCI
+ * Bridge config registers are available directly in Aardvark memory
+ * space starting at offset zero. Moreover PCI Bridge registers in the
+ * range 0x10 - 0x34 are not available and register 0x38 (Expansion ROM
+ * Base Address) is at offset 0x30.
+ * We therefore read configuration space content of the primary PCI
+ * Bridge from our virtual cache.
+ */
+ if (busno == pcie->first_busno) {
+ if (offset >= 0x10 && offset < 0x34)
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ else if ((offset & ~3) == PCI_ROM_ADDRESS1)
+ data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
+ else
+ data = advk_readl(pcie, offset & ~3);
+
+ if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+ /*
+ * Change Header Type of PCI Bridge device to Type 1
+ * (0x01, used by PCI Bridges) because hardwired value
+ * is Type 0 (0x00, used by Endpoint devices).
+ */
+ data &= ~0x007f0000;
+ data |= PCI_HEADER_TYPE_BRIDGE << 16;
+ }
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
+ /* CRSSVE bit is stored only in cache */
+ if (pcie->cfgcrssve)
+ data |= PCI_EXP_RTCTL_CRSSVE;
+ }
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
+ (PCI_EXP_RTCAP & ~3)) {
+ /* CRS is emulated below, so set CRSVIS capability */
+ data |= PCI_EXP_RTCAP_CRSVIS << 16;
+ }
+
+ *valuep = pci_conv_32_to_size(data, offset, size);
+
+ return 0;
+ }
+
+ /*
* Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
* OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
* only when CRSSVE bit in Root Port PCIe device is enabled. In all
* other error PCIe Root Complex must return all-ones.
- * Aardvark HW does not have Root Port PCIe device and U-Boot does not
- * implement emulation of this device.
+ *
* U-Boot currently does not support handling of CRS return value for
* PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
- * Therefore disable returning CRS response for now.
+ * So it means that pcie->cfgcrssve is false. But the code is prepared
+ * for returning CRS, so that if U-Boot does support CRS in the future,
+ * it will work for Aardvark.
*/
- allow_crs = false;
+ allow_crs = pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
- if (PCI_BUS(bdf) == pcie->first_busno)
+ if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_RD_TYPE0;
else
reg |= PCIE_CONFIG_RD_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
int retry_count;
+ ulong data;
uint reg;
int ret;
dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
offset, size, value);
- if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
dev_dbg(pcie->dev, "- out of range\n");
return 0;
}
+ /*
+ * As explained in pcie_advk_read_config(), for the configuration
+ * space of the primary PCI Bridge, we write the content into virtual
+ * cache.
+ */
+ if (busno == pcie->first_busno) {
+ if (offset >= 0x10 && offset < 0x34) {
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ data = pci_conv_size_to_32(data, value, offset, size);
+ pcie->cfgcache[(offset - 0x10) / 4] = data;
+ } else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
+ data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
+ data = pci_conv_size_to_32(data, value, offset, size);
+ advk_writel(pcie, data, PCIE_CORE_EXP_ROM_BAR_REG);
+ } else {
+ data = advk_readl(pcie, offset & ~3);
+ data = pci_conv_size_to_32(data, value, offset, size);
+ advk_writel(pcie, data, offset & ~3);
+ }
+
+ if (offset == PCI_PRIMARY_BUS)
+ pcie->first_busno = data & 0xff;
+
+ if (offset == PCI_SECONDARY_BUS ||
+ (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
+ pcie->sec_busno = (data >> 8) & 0xff;
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
+ pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
+
+ return 0;
+ }
+
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
- if (PCI_BUS(bdf) == pcie->first_busno)
+ if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_WR_TYPE0;
else
reg |= PCIE_CONFIG_WR_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
val = advk_readl(pcie, CFG_REG);
ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
- return ltssm_state >= LTSSM_L0;
+ return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
}
/**
/* check if the link is up or not */
for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
- printf("PCIE-%d: Link up\n", pcie->first_busno);
+ printf("PCIe: Link up\n");
return 0;
}
udelay(LINK_WAIT_TIMEOUT);
}
- printf("PCIE-%d: Link down\n", pcie->first_busno);
+ printf("PCIe: Link down\n");
return -ETIMEDOUT;
}
*/
advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
+ * because default value is Mass Storage Controller (0x010400), causing
+ * U-Boot to fail to recognize it as P2P Bridge.
+ *
+ * Note that this Aardvark PCI Bridge does not have a compliant Type 1
+ * Configuration Space and it even cannot be accessed via Aardvark's
+ * PCI config space access method. Something like config space is
+ * available in internal Aardvark registers starting at offset 0x0
+ * and is reported as Type 0. In range 0x10 - 0x34 it has totally
+ * different registers. So our driver reports Header Type as Type 1 and
+ * for the above mentioned range redirects access to the virtual
+ * cfgcache[] buffer, which avoids changing internal Aardvark registers.
+ */
+ reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
+ reg &= ~0xffffff00;
+ reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
+
/* Set Advanced Error Capabilities and Control PF0 register */
reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
- reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
- reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
- PCIE_CORE_CMD_IO_ACCESS_EN |
- PCIE_CORE_CMD_MEM_IO_REQ_EN;
- advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
-
return 0;
}
dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
}
- pcie->first_busno = dev_seq(dev);
pcie->dev = pci_get_controller(dev);
+ /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
+ pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
+ PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
+ pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
+ PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
+
return pcie_advk_setup_hw(pcie);
}
return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
}
-int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
- enum pci_size_t size)
+static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
+ enum pci_size_t size)
{
struct udevice *bus;
int ret;
return ops->read_config(bus, bdf, offset, valuep, size);
}
-int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
- enum pci_size_t size)
+static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
+ enum pci_size_t size)
{
struct udevice *bus;
int ret;
/* Check only the first access, we don't expect problems */
ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
PCI_SIZE_16);
- if (ret)
- goto error;
-
- if (vendor == 0xffff || vendor == 0x0000)
+ if (ret || vendor == 0xffff || vendor == 0x0000)
continue;
pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
}
return 0;
-error:
- printf("Cannot read bus configuration: %d\n", ret);
-
- return ret;
}
static void decode_regions(struct pci_controller *hose, ofnode parent_node,
return phys_addr;
}
-int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
- unsigned long flags, unsigned long skip_mask,
- pci_addr_t *ba)
+static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags, unsigned long skip_mask,
+ pci_addr_t *ba)
{
struct pci_region *res;
struct udevice *ctlr;
#include <errno.h>
#include <log.h>
#include <pci.h>
+#include "pci_internal.h"
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
+ u8 io_32;
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+ dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
+ io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Configure bus number registers */
dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
* I/O space
*/
dm_pci_write_config16(dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
+ ((pci_mem->bus_lower & 0xfff00000) >> 16) &
+ PCI_MEMORY_RANGE_MASK);
cmdstat |= PCI_COMMAND_MEMORY;
}
* I/O space
*/
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
+ PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
- dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
- dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
+ prefechable_64);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
+ prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+ (((pci_io->bus_lower & 0x0000f000) >> 8) &
+ PCI_IO_RANGE_MASK) | io_32);
+ if (io_32 == PCI_IO_RANGE_TYPE_32)
+ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
pciauto_region_align(pci_mem, 0x100000);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
+ ((pci_mem->bus_lower - 1) >> 16) &
+ PCI_MEMORY_RANGE_MASK);
}
if (pci_prefetch) {
pciauto_region_align(pci_prefetch, 0x100000);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
+ (((pci_prefetch->bus_lower - 1) >> 16) &
+ PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
}
if (pci_io) {
+ u8 io_32;
+
+ dm_pci_read_config8(dev, PCI_IO_LIMIT,
+ &io_32);
+ io_32 &= PCI_IO_RANGE_TYPE_MASK;
+
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+ ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
+ PCI_IO_RANGE_MASK) | io_32);
+ if (io_32 == PCI_IO_RANGE_TYPE_32)
+ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}
pcie_dw_setup_host(&priv->dw);
- ret = meson_pcie_link_up(priv, LINK_SPEED_GEN_2);
- if (ret < 0)
- goto err_link_up;
+ meson_pcie_link_up(priv, LINK_SPEED_GEN_2);
return 0;
-err_link_up:
- clk_disable(&priv->clk_port);
- clk_disable(&priv->clk_general);
- clk_disable(&priv->clk_pclk);
err_deassert_bulk:
reset_assert_bulk(&priv->rsts);
err_power_off_phy:
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Broadcom
+ * Copyright (C) 2020-2021 Broadcom
*
*/
#include <malloc.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <linux/delay.h>
#include <linux/log2.h>
#define EP_PERST_SOURCE_SELECT_SHIFT 2
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_MEM ||
hose->regions[i].flags == PCI_REGION_PREFETCH) {
- debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n",
+ debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n",
i, &hose->regions[i].bus_start,
&hose->regions[i].phys_start,
hose->regions[i].size);
while (!pci_get_dma_regions(pcie->dev, ®ions, i)) {
dev_dbg(pcie->dev,
- "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n",
+ "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n",
i, regions.bus_start, regions.phys_start, regions.size);
/* Each range entry corresponds to an inbound mapping region */
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include <linux/libfdt.h>
+#include <fdt_support.h>
#include "pcie_layerscape_fixup_common.h"
void ft_pci_setup(void *blob, struct bd_info *bd)
}
#if defined(CONFIG_FSL_LAYERSCAPE)
-int lx2_board_fix_fdt(void *fdt)
+static int lx2_board_fix_fdt(void *fdt)
{
char *reg_name, *old_str, *new_str;
const char *reg_names;
return 0;
}
-int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
- uint offset, void **paddress)
+static int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, void **paddress)
{
struct ls_pcie_rc *pcie_rc = dev_get_priv(bus);
struct ls_pcie *pcie = pcie_rc->pcie;
config MVEBU_COMPHY_SUPPORT
bool "ComPhy SerDes driver"
- default n
help
Choose this option to add support
for Comphy driver.
* 6. Enable the output of 100M/125M/500M clock
*/
reg_set16(phy_addr(PCIE, MISC_REG0),
- 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
+ 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
/*
* 7. Enable TX
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
+ else
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
+ else
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
/*
* 11. Release SW reset
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
+ else
+ usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane);
if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
+ else
+ usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane);
/*
* 10. Set max speed generation to USB3.0 5Gbps
rb_usb2phy_pllcal_done, /* value */
rb_usb2phy_pllcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 PLL calibration\n");
+ goto out;
+ }
/* Assert impedance calibration done */
ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
rb_usb2phy_impcal_done, /* value */
rb_usb2phy_impcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 impedance calibration\n");
+ goto out;
+ }
/* Assert squetch calibration done */
ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
rb_usb2phy_sqcal_done, /* value */
rb_usb2phy_sqcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 unknown calibration\n");
+ goto out;
+ }
/* Assert PLL is ready */
ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
rb_usb2phy_pll_ready, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock USB2 PLL\n");
+ goto out;
+ }
+out:
debug_exit();
return ret;
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
+ else
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv);
if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
+ else
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv);
/*
* 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
rb_pll_ready_tx | rb_pll_ready_rx, /* value */
rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock PLL for SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* 21. Set COMPHY input port PIN_TX_IDLE=0
rb_rx_init_done, /* value */
rb_rx_init_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to init RX of SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* Restore saved selector.
*/
reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
+out:
debug_exit();
return ret;
#define MISC_REG0 0x4f
#define rb_clk100m_125m_en BIT(4)
+#define rb_txdclk_2x_sel BIT(6)
#define rb_clk500m_en BIT(7)
#define rb_ref_clk_sel BIT(10)
void comphy_pcie_unit_general_config(u32 pex_index);
#endif /* _COMPHY_CORE_H_ */
-
(0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
#endif /* _UTMI_PHY_H_ */
-
return intel_pinctrl_of_to_plat(dev, comm, 2);
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_gpio_ids[] = {
{ .compatible = "intel,apl-pinctrl"},
{ }
.of_match = of_match_ptr(apl_gpio_ids),
.probe = intel_pinctrl_probe,
.ops = &intel_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_to_plat = apl_pinctrl_of_to_plat,
.probe = mtk_pinctrl_mt7622_probe,
.priv_auto = sizeof(struct mtk_pinctrl_priv),
};
-
-
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
- /* name first last reg offset */
+ /* name first last reg offset */
BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0),
BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0),
BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0),
};
static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
- /* name first last reg offset */
+ /* name first last reg offset */
BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 0x6, 0),
BANK_PMX("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 0xb, 0),
BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0x0, 0),
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(mxs_pinctrl_match),
.probe = mxs_pinctrl_probe,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.priv_auto = sizeof(struct mxs_pinctrl_priv),
.of_to_plat = qe_io_of_to_plat,
.plat_auto = sizeof(struct qe_io_plat),
.ops = &par_io_pinctrl_ops,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.flags = DM_FLAG_PRE_RELOC,
#endif
};
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
+#include <dm/of_access.h>
#include <dm/pinctrl.h>
#include <linux/libfdt.h>
#include <linux/list.h>
};
/**
+ * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun
+ * @offset: offset base of pins
+ * @npins: number pins with the same mux value of gpio function
+ * @gpiofunc: mux value of gpio function
+ * @node: list node
+ */
+struct single_gpiofunc_range {
+ u32 offset;
+ u32 npins;
+ u32 gpiofunc;
+ struct list_head node;
+};
+
+/**
* struct single_priv - private data
* @bits_per_pin: number of bits per pin
* @npins: number of selectable pins
* @pin_name: temporary buffer to store the pin name
+ * @functions: list pin functions
+ * @gpiofuncs: list gpio functions
*/
struct single_priv {
#if (IS_ENABLED(CONFIG_SANDBOX))
unsigned int npins;
char pin_name[PINNAME_SIZE];
struct list_head functions;
+ struct list_head gpiofuncs;
};
/**
return 0;
}
+static int single_request(struct udevice *dev, int pin, int flags)
+{
+ struct single_priv *priv = dev_get_priv(dev);
+ struct single_pdata *pdata = dev_get_plat(dev);
+ struct single_gpiofunc_range *frange = NULL;
+ struct list_head *pos, *tmp;
+ phys_addr_t reg;
+ int mux_bytes = 0;
+ u32 data;
+
+ /* If function mask is null, needn't enable it. */
+ if (!pdata->mask)
+ return -ENOTSUPP;
+
+ list_for_each_safe(pos, tmp, &priv->gpiofuncs) {
+ frange = list_entry(pos, struct single_gpiofunc_range, node);
+ if ((pin >= frange->offset + frange->npins) ||
+ pin < frange->offset)
+ continue;
+
+ mux_bytes = pdata->width / BITS_PER_BYTE;
+ reg = pdata->base + pin * mux_bytes;
+
+ data = single_read(dev, reg);
+ data &= ~pdata->mask;
+ data |= frange->gpiofunc;
+ single_write(dev, data, reg);
+ break;
+ }
+
+ return 0;
+}
+
static struct single_func *single_allocate_function(struct udevice *dev,
unsigned int group_pins)
{
return priv->npins;
}
+static int single_add_gpio_func(struct udevice *dev)
+{
+ struct single_priv *priv = dev_get_priv(dev);
+ const char *propname = "pinctrl-single,gpio-range";
+ const char *cellname = "#pinctrl-single,gpio-range-cells";
+ struct single_gpiofunc_range *range;
+ struct ofnode_phandle_args gpiospec;
+ int ret, i;
+
+ for (i = 0; ; i++) {
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), propname,
+ cellname, 0, i, &gpiospec);
+ /* Do not treat it as error. Only treat it as end condition. */
+ if (ret) {
+ ret = 0;
+ break;
+ }
+ range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ ret = -ENOMEM;
+ break;
+ }
+ range->offset = gpiospec.args[0];
+ range->npins = gpiospec.args[1];
+ range->gpiofunc = gpiospec.args[2];
+ list_add_tail(&range->node, &priv->gpiofuncs);
+ }
+ return ret;
+}
+
static int single_probe(struct udevice *dev)
{
struct single_pdata *pdata = dev_get_plat(dev);
u32 size;
INIT_LIST_HEAD(&priv->functions);
+ INIT_LIST_HEAD(&priv->gpiofuncs);
size = pdata->offset + pdata->width / BITS_PER_BYTE;
#if (CONFIG_IS_ENABLED(SANDBOX))
priv->npins *= (pdata->width / priv->bits_per_pin);
}
+ if (single_add_gpio_func(dev))
+ dev_dbg(dev, "gpio functions are not added\n");
+
dev_dbg(dev, "%d pins\n", priv->npins);
return 0;
}
.get_pin_name = single_get_pin_name,
.set_state = single_set_state,
.get_pin_muxing = single_get_pin_muxing,
+ .request = single_request,
};
static const struct udevice_id single_pinctrl_match[] = {
UCLASS_DRIVER(pinctrl) = {
.id = UCLASS_PINCTRL,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = pinctrl_post_bind,
#endif
.flags = DM_UC_FLAG_SEQ_ALIAS,
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR1_0 F_(IRQ0, IP2_27_24)
/* GPSR2 */
-#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
+#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
#define GPSR2_26 F_(SDA3, IP10_7_4)
#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
.of_match = px30_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3036_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3128_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3188_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3228_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3288_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3308_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3328_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3368_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3399_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rv1108_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
-menu "Power"
+menuconfig POWER
+ bool "Power"
+ default y
+ help
+ Enable support for power control in U-Boot. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in U-Boot to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of a build.
+
+if POWER
+
+config POWER_LEGACY
+ bool "Legacy power support"
+ help
+ Note: This is a legacy option. Use DM_PMIC instead.
+
+ Enable support for power control in U-Boot. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in U-Boot to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of a build.
+
+config SPL_POWER_LEGACY
+ bool "Legacy power support in SPL"
+ default y if POWER_LEGACY
+ help
+ Note: This is a legacy option. Use SPL_DM_PMIC instead.
+
+ Enable support for power control in SPL. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in SPL to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of a build.
source "drivers/power/acpi_pmc/Kconfig"
config AXP_ALDO3_INRUSH_QUIRK
bool "axp pmic (a)ldo3 inrush quirk"
depends on AXP209_POWER
- default n
---help---
The reference design denotes a value of 4.7 uF for the output capacitor
of LDO3. Some boards have too high capacitance causing an inrush current
config AXP_SW_ON
bool "axp pmic sw on"
depends on AXP809_POWER || AXP818_POWER
- default n
---help---
Enable to turn on axp pmic sw.
This adds poweroff driver for mt6323
this pmic is used on mt7623 / Bananapi R2
-endmenu
+config POWER_I2C
+ bool "I2C-based power control for legacy power"
+ depends on POWER_LEGACY
+ help
+ Enable this to use the I2C driver designed for the legacy PMIC
+ interface.
+
+ Not to be used for new designs and existing ones should be moved to
+ the new PMIC interface based on driver model.
+
+config SPL_POWER_I2C
+ bool "I2C-based power control for legacy power"
+ depends on SPL_POWER_LEGACY
+ default y if POWER_I2C
+ help
+ Enable this to use the I2C driver designed for the legacy PMIC
+ interface.
+
+ Not to be used for new designs and existing ones should be moved to
+ the new PMIC interface based on driver model.
+
+endif
# Copyright (c) 2009 Wind River Systems, Inc.
# Tom Rix <Tom.Rix at windriver.com>
+obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/
+obj-y += battery/
+obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/
+obj-y += fuel_gauge/
+obj-y += mfd/
+obj-y += pmic/
+obj-y += regulator/
+
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_TWL4030_POWER) += twl4030.o
obj-$(CONFIG_TWL6030_POWER) += twl6030.o
obj-$(CONFIG_PALMAS_POWER) += palmas.o
-obj-$(CONFIG_POWER) += power_core.o
+obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o
obj-$(CONFIG_DIALOG_POWER) += power_dialog.o
obj-$(CONFIG_POWER_FSL) += power_fsl.o
-obj-$(CONFIG_POWER_I2C) += power_i2c.o
+obj-$(CONFIG_$(SPL_TPL_)POWER_I2C) += power_i2c.o
obj-$(CONFIG_POWER_SPI) += power_spi.o
obj-$(CONFIG_POWER_MT6323) += mt6323.o
#
# Copyright 2019 Google LLC
-obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o
+obj-y += acpi-pmc-uclass.o
obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o
#include <common.h>
#include <command.h>
#include <errno.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <axp_pmic.h>
#include <common.h>
#include <command.h>
#include <errno.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <axp_pmic.h>
return ops->off(power_domain);
}
-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA))
+#if CONFIG_IS_ENABLED(OF_REAL)
static int dev_power_domain_ctrl(struct udevice *dev, bool on)
{
struct power_domain pd;
{
return dev_power_domain_ctrl(dev, false);
}
-#endif
+#endif /* OF_REAL */
UCLASS_DRIVER(power_domain) = {
.id = UCLASS_POWER_DOMAIN,
- 'drivers/power/pmic/pmic-uclass.c'
- 'include/power/pmic.h'
+if DM_PMIC
+
+config SPL_DM_PMIC
+ bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL"
+ depends on SPL_DM
+ default y
+ ---help---
+ This config enables the driver-model PMIC support in SPL.
+ UCLASS_PMIC - designed to provide an I/O interface for PMIC devices.
+ For the multi-function PMIC devices, this can be used as parent I/O
+ device for each IC's interface. Then, each children uses its parent
+ for read/write. For detailed description, please refer to the files:
+ - 'drivers/power/pmic/pmic-uclass.c'
+ - 'include/power/pmic.h'
+
config PMIC_CHILDREN
bool "Allow child devices for PMICs"
- depends on DM_PMIC
default y
---help---
This allows PMICs to support child devices (such as regulators) in
config SPL_PMIC_CHILDREN
bool "Allow child devices for PMICs in SPL"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
default y
---help---
This allows PMICs to support child devices (such as regulators) in
config PMIC_AB8500
bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU"
- depends on DM_PMIC
select REGMAP
select SYSCON
help
config PMIC_ACT8846
bool "Enable support for the active-semi 8846 PMIC"
- depends on DM_PMIC && DM_I2C
+ depends on DM_I2C
---help---
This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout
regulators (LDOs). It also provides some GPIO, reset and battery
functions. It uses an I2C interface and is designed for use with
tablets and smartphones.
+config PMIC_AXP
+ bool "Enable Driver Model for X-Powers AXP PMICs"
+ depends on DM_I2C
+ help
+ This config enables driver-model PMIC uclass features for
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
+config SPL_PMIC_AXP
+ bool "Enable Driver Model for X-Powers AXP PMICs in SPL"
+ depends on SPL_DM_I2C && SPL_DM_PMIC
+ help
+ This config enables driver-model PMIC uclass features in the SPL for
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
config DM_PMIC_DA9063
bool "Enable Driver Model for the Dialog DA9063 PMIC"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC DA9063. The driver implements read/write operations.
config SPL_DM_PMIC_DA9063
bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL"
- depends on DM_PMIC && SPL
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC DA9063. The driver implements read/write operations.
config DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC BD71837. The driver implements read/write operations.
config SPL_DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837 in SPL stage"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass
features for PMIC BD71837. The driver implements read/write
config DM_PMIC_FAN53555
bool "Enable support for OnSemi FAN53555"
- depends on DM_PMIC && DM_REGULATOR && DM_I2C
+ depends on DM_REGULATOR && DM_I2C
select DM_REGULATOR_FAN53555
help
This config enables implementation of driver-model PMIC
config DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC MP5416. The driver implements read/write operations.
config SPL_DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416 in SPL stage"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass
features for PMIC MP5416. The driver implements read/write
config DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450. The driver implements read/write operations.
config SPL_DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450 in SPL. The driver implements read/write operations.
config DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100. The driver implements read/write operations.
config SPL_DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100 in SPL"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100 in SPL. The driver implements read/write operations.
config DM_PMIC_MAX77686
bool "Enable Driver Model for PMIC MAX77686"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
config DM_PMIC_MAX8998
bool "Enable Driver Model for PMIC MAX8998"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8998. The driver implements read/write operations.
config DM_PMIC_MC34708
bool "Enable Driver Model for PMIC MC34708"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC MC34708. The driver implements read/write operations.
config PMIC_MAX8997
bool "Enable Driver Model for PMIC MAX8997"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8997. The driver implements read/write operations.
config PMIC_PM8916
bool "Enable Driver Model for Qualcomm PM8916 PMIC"
- depends on DM_PMIC
---help---
The PM8916 is a PMIC connected to one (or several) processors
with SPMI bus. It has 2 slaves with several peripherals:
config PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
- depends on DM_PMIC
+ ---help---
+ The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
+ an RTC and two low Rds (resistance (drain to source)) switches. It is
+ accessed via an I2C interface. The device is used with Rockchip SoCs.
+ This driver implements register read/write operations.
+
+config SPL_PMIC_RK8XX
+ bool "Enable support for Rockchip PMIC RK8XX"
+ depends on SPL_DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
config PMIC_S2MPS11
bool "Enable Driver Model for PMIC Samsung S2MPS11"
- depends on DM_PMIC
---help---
The Samsung S2MPS11 PMIC provides:
- 38 adjustable LDO regulators
config DM_PMIC_SANDBOX
bool "Enable Driver Model for emulated Sandbox PMIC"
- depends on DM_PMIC
---help---
Enable the driver for Sandbox PMIC emulation. The emulated PMIC device
depends on two drivers:
config PMIC_S5M8767
bool "Enable Driver Model for the Samsung S5M8767 PMIC"
- depends on DM_PMIC
---help---
The S5M8767 PMIC provides a large array of LDOs and BUCKs for use
as a SoC power controller. It also provides 32KHz clock outputs. This
config PMIC_RN5T567
bool "Enable driver for Ricoh RN5T567 PMIC"
- depends on DM_PMIC
---help---
The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
regulators Real-Time Clock and 4 GPIOs. This driver provides
config PMIC_TPS65090
bool "Enable driver for Texas Instruments TPS65090 PMIC"
- depends on DM_PMIC
---help---
The TPS65090 is a PMIC containing several LDOs, DC to DC convertors,
FETs and a battery charger. This driver provides register access
config PMIC_PALMAS
bool "Enable driver for Texas Instruments PALMAS PMIC"
- depends on DM_PMIC
---help---
The PALMAS is a PMIC containing several LDOs, SMPS.
This driver binds the pmic children.
config PMIC_LP873X
bool "Enable driver for Texas Instruments LP873X PMIC"
- depends on DM_PMIC
---help---
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children.
config PMIC_LP87565
bool "Enable driver for Texas Instruments LP87565 PMIC"
- depends on DM_PMIC
---help---
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children.
-config POWER_MC34VR500
- bool "Enable driver for Freescale MC34VR500 PMIC"
- ---help---
- The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
- SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
- via an I2C interface.
-
config DM_PMIC_TPS65910
bool "Enable driver for Texas Instruments TPS65910 PMIC"
- depends on DM_PMIC
---help---
The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
config PMIC_STPMIC1
bool "Enable support for STMicroelectronics STPMIC1 PMIC"
- depends on DM_PMIC && DM_I2C
+ depends on DM_I2C
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW
---help---
The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
config SPL_PMIC_PALMAS
bool "Enable driver for Texas Instruments PALMAS PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The PALMAS is a PMIC containing several LDOs, SMPS.
This driver binds the pmic children in SPL.
config SPL_PMIC_LP873X
bool "Enable driver for Texas Instruments LP873X PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children in SPL.
config SPL_PMIC_LP87565
bool "Enable driver for Texas Instruments LP87565 PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children in SPL.
config PMIC_TPS65941
bool "Enable driver for Texas Instruments TPS65941 PMIC"
- depends on DM_PMIC
help
The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+endif
+
+config POWER_MC34VR500
+ bool "Enable driver for Freescale MC34VR500 PMIC"
+ depends on !DM_PMIC
+ ---help---
+ The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
+ SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
+ via an I2C interface.
# Copyright (C) 2012 Samsung Electronics
# Lukasz Majewski <l.majewski@samsung.com>
-obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_PMIC_AB8500) += ab8500.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
+obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
-obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o
+obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o
obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+
+static int axp_pmic_reg_count(struct udevice *dev)
+{
+ /* TODO: Get the specific value from driver data. */
+ return 0x100;
+}
+
+static struct dm_pmic_ops axp_pmic_ops = {
+ .reg_count = axp_pmic_reg_count,
+ .read = dm_i2c_read,
+ .write = dm_i2c_write,
+};
+
+static const struct udevice_id axp_pmic_ids[] = {
+ { .compatible = "x-powers,axp152" },
+ { .compatible = "x-powers,axp202" },
+ { .compatible = "x-powers,axp209" },
+ { .compatible = "x-powers,axp221" },
+ { .compatible = "x-powers,axp223" },
+ { .compatible = "x-powers,axp803" },
+ { .compatible = "x-powers,axp806" },
+ { .compatible = "x-powers,axp809" },
+ { .compatible = "x-powers,axp813" },
+ { }
+};
+
+U_BOOT_DRIVER(axp_pmic) = {
+ .name = "axp_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = axp_pmic_ids,
+ .bind = dm_scan_fdt_dev,
+ .ops = &axp_pmic_ops,
+};
/*
* tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
- * interface.
+ * interface.
* @return: 0 on success, not 0 on failure
*/
int tps65910_set_i2c_control(void)
obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
-obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o
+obj-$(CONFIG_$(SPL_TPL_)REGULATOR_RK8XX) += rk8xx.o
obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
frequency/period can be controlled along with the proportion of that
time that the signal is high.
+config PWM_AT91
+ bool "Enable support for PWM found on AT91 SoC's"
+ depends on DM_PWM && ARCH_AT91
+ help
+ Support for PWM hardware on AT91 based SoC.
+
config PWM_CROS_EC
bool "Enable support for the Chrome OS EC PWM"
depends on DM_PWM
obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+obj-$(CONFIG_PWM_AT91) += pwm-at91.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PWM support for Microchip AT91 architectures.
+ *
+ * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Dan Sneddon <daniel.sneddon@microchip.com>
+ *
+ * Based on drivers/pwm/pwm-atmel.c from Linux.
+ */
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <pwm.h>
+
+#define PERIOD_BITS 16
+#define PWM_MAX_PRES 10
+#define NSEC_PER_SEC 1000000000L
+
+#define PWM_ENA 0x04
+#define PWM_CHANNEL_OFFSET 0x20
+#define PWM_CMR 0x200
+#define PWM_CMR_CPRE_MSK GENMASK(3, 0)
+#define PWM_CMR_CPOL BIT(9)
+#define PWM_CDTY 0x204
+#define PWM_CPRD 0x20C
+
+struct at91_pwm_priv {
+ void __iomem *base;
+ struct clk pclk;
+ u32 clkrate;
+};
+
+static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev,
+ unsigned long clkrate,
+ uint period_ns, uint duty_ns,
+ unsigned long *cprd, u32 *pres)
+{
+ u64 cycles = period_ns;
+ int shift;
+
+ /* Calculate the period cycles and prescale value */
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+
+ /*
+ * The register for the period length is period_bits bits wide.
+ * So for each bit the number of clock cycles is wider divide the input
+ * clock frequency by two using pres and shift cprd accordingly.
+ */
+ shift = fls(cycles) - PERIOD_BITS;
+
+ if (shift > PWM_MAX_PRES) {
+ return -EINVAL;
+ } else if (shift > 0) {
+ *pres = shift;
+ cycles >>= *pres;
+ } else {
+ *pres = 0;
+ }
+
+ *cprd = cycles;
+
+ return 0;
+}
+
+static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns,
+ unsigned long clkrate, unsigned long cprd,
+ u32 pres, unsigned long *cdty)
+{
+ u64 cycles = duty_ns;
+
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+ cycles >>= pres;
+ *cdty = cprd - cycles;
+}
+
+/**
+ * Returns: channel status after set operation
+ */
+static bool at91_pwm_set(void __iomem *base, uint channel, bool enable)
+{
+ u32 val, cur_status;
+
+ val = ioread32(base + PWM_ENA);
+ cur_status = !!(val & BIT(channel));
+
+ /* if channel is already in that state, do nothing */
+ if (!(enable ^ cur_status))
+ return cur_status;
+
+ if (enable)
+ val |= BIT(channel);
+ else
+ val &= ~(BIT(channel));
+
+ iowrite32(val, base + PWM_ENA);
+
+ return cur_status;
+}
+
+static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+
+ at91_pwm_set(priv->base, channel, enable);
+
+ return 0;
+}
+
+static int at91_pwm_set_config(struct udevice *dev, uint channel,
+ uint period_ns, uint duty_ns)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ unsigned long cprd, cdty;
+ u32 pres, val;
+ int channel_enabled;
+ int ret;
+
+ ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns,
+ duty_ns, &cprd, &pres);
+ if (ret)
+ return ret;
+
+ at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty);
+
+ /* disable the channel */
+ channel_enabled = at91_pwm_set(priv->base, channel, false);
+
+ /* It is necessary to preserve CPOL, inside CMR */
+ val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+ val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
+ iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+
+ iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD);
+
+ iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY);
+
+ /* renable the channel if needed */
+ if (channel_enabled)
+ at91_pwm_set(priv->base, channel, true);
+
+ return 0;
+}
+
+static int at91_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+ if (polarity)
+ val |= PWM_CMR_CPOL;
+ else
+ val &= ~PWM_CMR_CPOL;
+ iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+
+ return 0;
+}
+
+static int at91_pwm_probe(struct udevice *dev)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &priv->pclk);
+ if (ret)
+ return ret;
+
+ /* clocks aren't ref-counted so just enabled them once here */
+ ret = clk_enable(&priv->pclk);
+ if (ret)
+ return ret;
+
+ priv->clkrate = clk_get_rate(&priv->pclk);
+
+ return ret;
+}
+
+static const struct pwm_ops at91_pwm_ops = {
+ .set_config = at91_pwm_set_config,
+ .set_enable = at91_pwm_set_enable,
+ .set_invert = at91_pwm_set_invert,
+};
+
+static const struct udevice_id at91_pwm_of_match[] = {
+ { .compatible = "atmel,sama5d2-pwm" },
+ { }
+};
+
+U_BOOT_DRIVER(at91_pwm) = {
+ .name = "at91_pwm",
+ .id = UCLASS_PWM,
+ .of_match = at91_pwm_of_match,
+ .probe = at91_pwm_probe,
+ .priv_auto = sizeof(struct at91_pwm_priv),
+ .ops = &at91_pwm_ops,
+};
.set_invert = meson_pwm_set_invert,
};
-#define XTAL -1
+#define XTAL -1
/* Local clock ids aliases to avoid define conflicts */
#define GXBB_CLKID_HDMI_PLL 2
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = uec_miiphy_read;
mdiodev->write = uec_miiphy_write;
config ASPEED_DDR4_DUALX8
bool "Enable Dual X8 DDR4 die"
depends on DM && OF_CONTROL && ARCH_ASPEED
- default n
help
Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram
controller needs to know if the memory chip mounted on the board is dual
config ASPEED_BYPASS_SELFTEST
bool "bypass self test during DRAM initialization"
- default n
help
Say Y here to bypass DRAM self test to speed up the boot time
config ASPEED_ECC
bool "aspeed SDRAM error correcting code"
depends on DM && OF_CONTROL && ARCH_ASPEED
- default n
help
enable SDRAM ECC function
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
-#define DDRSS_V2A_R1_MAT_REG 0x0020
-#define DDRSS_ECC_CTRL_REG 0x0120
+#define DDRSS_V2A_R1_MAT_REG 0x0020
+#define DDRSS_ECC_CTRL_REG 0x0120
struct k3_ddrss_desc {
struct udevice *dev;
config RAM_OCTEON
bool "Ram drivers for Octeon SoCs"
depends on RAM && ARCH_OCTEON
- default n
help
This enables support for RAM drivers for Octeon SoCs.
config RAM_OCTEON_DDR4
bool "Octeon III DDR4 RAM support"
- default n
help
This enables support for DDR4 RAM suppoort for Octeon III. This does
not include support for Octeon CN70XX.
{
int ret = 0;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3368_sdram_params *plat = dev_get_plat(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3368_sdram_params *plat = dev_get_plat(dev);
- ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
- if (ret)
- return ret;
-#endif
+ ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
+ if (ret)
+ return ret;
+ }
return ret;
}
static int rk3188_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_sdram_params *params = dev_get_plat(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
/* rk3188 supports only one-channel */
params->num_channels = 1;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
static int rk322x_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk322x_sdram_params *params = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
params->num_channels = 1;
ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
.plat_auto = sizeof(struct rk322x_sdram_params),
#endif
};
-
static int rk3288_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_sdram_params *params = dev_get_plat(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
/* Rk3288 supports dual-channel, set default channel num to 2 */
params->num_channels = 2;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3328_sdram_params *params = &plat->sdram_params;
#else
struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
static int rk3328_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
(u32 *)&plat->sdram_params,
sizeof(plat->sdram_params) / sizeof(u32));
if (ret)
printf("%s: regmap failed %d\n", __func__, ret);
-#endif
return 0;
}
struct dram_info *priv = dev_get_priv(dev);
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3399_sdram_params *params = &plat->sdram_params;
#else
struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk);
+ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->ddr_clk);
#else
ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
#endif
} else {
dev_dbg(dev, "cannot find st,mem_remap property\n");
}
-
+
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
if (swp_fmc != NOT_FOUND) {
/* set fmc swapping selection */
config STM32MP1_DDR_INTERACTIVE_FORCE
bool "STM32MP1 DDR driver : force interactive mode"
depends on STM32MP1_DDR_INTERACTIVE
- default n
help
force interactive mode in STM32MP1 DDR controller driver
skip the polling of character 'd' in console
config DM_REBOOT_MODE
bool "Enable reboot mode using Driver Model"
depends on DM
- default n
help
Enable support for reboot mode control. This will allow users to
adjust the boot process based on reboot mode parameter
config DM_REBOOT_MODE_GPIO
bool "Use GPIOs as reboot mode backend"
depends on DM_REBOOT_MODE
- default n
help
Use GPIOs to control the reboot mode. This will allow users to boot
a device in a specific mode by using a GPIO that can be controlled
config DM_REBOOT_MODE_RTC
bool "Use RTC as reboot mode backend"
depends on DM_REBOOT_MODE
- default n
help
Use RTC non volatile memory to control the reboot mode. This will allow users to boot
a device in a specific mode by using a register(s) that can be controlled
#include <exports.h>
#include <reboot-mode/reboot-mode.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int dm_reboot_mode_update(struct udevice *dev)
{
struct reboot_mode_ops *ops = reboot_mode_get_ops(dev);
return -EINVAL;
#if CONFIG_IS_ENABLED(OF_CONTROL)
- const int node = dev_of_offset(dev);
const char *mode_prefix = "mode-";
const int mode_prefix_len = strlen(mode_prefix);
- int property;
+ struct ofprop property;
const u32 *propvalue;
const char *propname;
- plat_data->env_variable = fdt_getprop(gd->fdt_blob,
- node,
- "u-boot,env-variable",
- NULL);
+ plat_data->env_variable = dev_read_string(dev, "u-boot,env-variable");
if (!plat_data->env_variable)
plat_data->env_variable = "reboot-mode";
plat_data->count = 0;
- fdt_for_each_property_offset(property, gd->fdt_blob, node) {
- propvalue = fdt_getprop_by_offset(gd->fdt_blob,
- property, &propname, NULL);
+ dev_for_each_property(property, dev) {
+ propvalue = dev_read_prop_by_prop(&property, &propname, NULL);
if (!propvalue) {
dev_err(dev, "Could not get the value for property %s\n",
propname);
struct reboot_mode_mode *next = plat_data->modes;
- fdt_for_each_property_offset(property, gd->fdt_blob, node) {
- propvalue = fdt_getprop_by_offset(gd->fdt_blob,
- property, &propname, NULL);
+ dev_for_each_property(property, dev) {
+ propvalue = dev_read_prop_by_prop(&property, &propname, NULL);
if (!propvalue) {
dev_err(dev, "Could not get the value for property %s\n",
propname);
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
#include <errno.h>
-#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
#include <remoteproc.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm.h>
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* for_each_remoteproc_device() - iterate through the list of rproc devices
* @fn: check function to call per match, if this function returns fail,
if (!dev_get_plat(dev)) {
#if CONFIG_IS_ENABLED(OF_CONTROL)
- int node = dev_of_offset(dev);
- const void *blob = gd->fdt_blob;
bool tmp;
- if (!blob) {
- debug("'%s' no dt?\n", dev->name);
- return -EINVAL;
- }
debug("'%s': using fdt\n", dev->name);
- uc_pdata->name = fdt_getprop(blob, node,
- "remoteproc-name", NULL);
+ uc_pdata->name = dev_read_string(dev, "remoteproc-name");
/* Default is internal memory mapped */
uc_pdata->mem_type = RPROC_INTERNAL_MEMORY_MAPPED;
- tmp = fdtdec_get_bool(blob, node,
- "remoteproc-internal-memory-mapped");
+ tmp = dev_read_bool(dev, "remoteproc-internal-memory-mapped");
if (tmp)
uc_pdata->mem_type = RPROC_INTERNAL_MEMORY_MAPPED;
#else
.rst_deassert = meson_reset_deassert,
};
-static const struct udevice_id meson_reset_ids[] = {
- { .compatible = "amlogic,meson-gxbb-reset" },
+static const struct udevice_id meson_reset_ids[] = {
+ { .compatible = "amlogic,meson-gxbb-reset" },
{ .compatible = "amlogic,meson-axg-reset" },
- { }
-};
+ { }
+};
static int meson_reset_probe(struct udevice *dev)
{
struct meson_reset_priv *priv = dev_get_priv(dev);
-
+
return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
}
.of_match = raspberrypi_reset_ids,
.ops = &raspberrypi_reset_ops,
};
-
#include <malloc.h>
#include <reset-uclass.h>
#include <asm/io.h>
+#include <clk/sunxi.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
#include <linux/log2.h>
-#include <asm/arch/ccu.h>
struct sunxi_reset_priv {
void *base;
config RNG_STM32MP1
bool "Enable random number generator for STM32MP1"
depends on ARCH_STM32MP
- default n
help
Enable STM32MP1 rng driver.
config RNG_ROCKCHIP
bool "Enable random number generator for rockchip crypto rng"
depends on ARCH_ROCKCHIP && DM_RNG
- default n
help
Enable random number generator for rockchip.This driver is
support rng module of crypto v1 and crypto v2.
config RNG_IPROC200
bool "Broadcom iProc RNG200 random number generator"
depends on DM_RNG
- default n
help
Enable random number generator for RPI4.
endif
config RTC_RX8025
bool "Enable RX8025 driver"
+ depends on DM_RTC
help
Support for Epson RX8025 Real Time Clock devices.
#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
+/* DS1307-specific bits */
#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
+/* DS1337-specific bits */
+#define DS1337_CTL_BIT_RS1 0x08 /* Rate select 1 */
+#define DS1337_CTL_BIT_RS2 0x10 /* Rate select 2 */
+#define DS1337_CTL_BIT_EOSC 0x80 /* Enable Oscillator */
+
+/* DS1340-specific bits */
+#define DS1340_SEC_BIT_EOSC 0x80 /* Enable Oscillator */
+#define DS1340_CTL_BIT_OUT 0x80 /* Output Control */
+
/* MCP7941X-specific bits */
#define MCP7941X_BIT_ST 0x80
#define MCP7941X_BIT_VBATEN 0x08
buf[RTC_SEC_REG_ADDR]);
return -1;
}
- }
-
- if (type == m41t11) {
+ } else if (type == ds_1337) {
+ if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the not oscillator enable (~EOSC) flag */
+ buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC;
+ dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
+ buf[RTC_CTL_REG_ADDR]);
+ return -1;
+ }
+ } else if (type == ds_1340) {
+ if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the not oscillator enable (~EOSC) flag */
+ buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC;
+ dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
+ buf[RTC_SEC_REG_ADDR]);
+ return -1;
+ }
+ } else if (type == m41t11) {
/* clock halted? turn it on, so clock can tick. */
if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
buf[RTC_SEC_REG_ADDR]);
goto read_rtc;
}
- }
-
- if (type == mcp794xx) {
+ } else if (type == mcp794xx) {
/* make sure that the backup battery is enabled */
if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
static int ds1307_rtc_reset(struct udevice *dev)
{
int ret;
+ enum ds_type type = dev_get_driver_data(dev);
- /* clear Clock Halt */
+ /*
+ * reset clock/oscillator in the seconds register:
+ * on DS1307 bit 7 enables Clock Halt (CH),
+ * on DS1340 bit 7 disables the oscillator (not EOSC)
+ * on MCP794xx bit 7 enables Start Oscillator (ST)
+ */
ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
if (ret < 0)
return ret;
- ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
- RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
- RTC_CTL_BIT_RS0);
- if (ret < 0)
- return ret;
- return 0;
+ if (type == ds_1307) {
+ /* Write control register in order to enable square-wave
+ * output (SQWE) and set a default rate of 32.768kHz (RS1|RS0).
+ */
+ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
+ RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
+ RTC_CTL_BIT_RS0);
+ } else if (type == ds_1337) {
+ /* Write control register in order to enable oscillator output
+ * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1).
+ */
+ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
+ DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1);
+ } else if (type == ds_1340 || type == mcp794xx || type == m41t11) {
+ /* Reset clock calibration, frequency test and output level. */
+ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0x00);
+ }
+
+ return ret;
}
static int ds1307_probe(struct udevice *dev)
#include <div64.h>
#include <dm.h>
#include <env.h>
-#include <generated/timestamp_autogenerated.h>
#include <rtc.h>
+#include <timestamp.h>
/**
* struct emul_rtc - private data for emulated RTC driver
.name = "rtc",
.id = UCLASS_RTC,
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x32
-#endif
-
-#ifdef CONFIG_DM_RTC
-#define DEV_TYPE struct udevice
-#else
-/* Local udevice */
-struct ludevice {
- u8 chip;
+enum rx_model {
+ model_rx_8025,
+ model_rx_8035,
};
-#define DEV_TYPE struct ludevice
-
-#endif
-
/*
* RTC register addresses
*/
#define RTC_DATE_REG_ADDR 0x04
#define RTC_MON_REG_ADDR 0x05
#define RTC_YR_REG_ADDR 0x06
+#define RTC_OFFSET_REG_ADDR 0x07
#define RTC_CTL1_REG_ADDR 0x0e
#define RTC_CTL2_REG_ADDR 0x0f
* address in a first cycle that is terminated by
* a STOP condition. The chips needs a 'restart'
* sequence (start sequence without a prior stop).
- * This driver has been written for a 4xx board.
- * U-Boot's 4xx i2c driver is currently not capable
- * to generate such cycles to some work arounds
- * are used.
*/
-/* static uchar rtc_read (uchar reg); */
-#ifdef CONFIG_DM_RTC
-/*
- * on mpc85xx based board with DM and offset len 1
- * accessing rtc works fine. May we can drop this ?
- */
#define rtc_read(reg) buf[(reg) & 0xf]
-#else
-#define rtc_read(reg) buf[((reg) + 1) & 0xf]
-#endif
-static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val);
+static int rtc_write(struct udevice *dev, uchar reg, uchar val);
+
+static int rx8025_is_osc_stopped(enum rx_model model, int ctrl2)
+{
+ int xstp = ctrl2 & RTC_CTL2_BIT_XST;
+ /* XSTP bit has different polarity on RX-8025 vs RX-8035.
+ * RX-8025: 0 == oscillator stopped
+ * RX-8035: 1 == oscillator stopped
+ */
+
+ if (model == model_rx_8025)
+ xstp = !xstp;
+
+ return xstp;
+}
/*
* Get the current time from the RTC
*/
-static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
+static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, ctl2;
uchar buf[16];
-#ifdef CONFIG_DM_RTC
if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
-#else
- if (i2c_read(dev->chip, 0, 0, buf, 16)) {
-#endif
printf("Error reading from RTC\n");
return -EIO;
}
printf("RTC: voltage drop detected\n");
rel = -1;
}
-
- if (!(ctl2 & RTC_CTL2_BIT_XST)) {
+ if (rx8025_is_osc_stopped(dev->driver_data, ctl2)) {
printf("RTC: oscillator stop detected\n");
rel = -1;
}
/*
* Set the RTC
*/
-static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp)
+static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
{
+ /* To work around the read/write cycle issue mentioned
+ * at the top of this file, write all the time registers
+ * in one I2C transaction
+ */
+ u8 write_op[8];
+
+ /* 2412 flag must be set before doing a RTC write,
+ * otherwise the seconds and minute register
+ * will be cleared when the flag is set
+ */
+ if (rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412))
+ return -EIO;
+
DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
- if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)))
- return -EIO;
-
- if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)))
- return -EIO;
-
- if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday)))
- return -EIO;
-
- if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)))
- return -EIO;
+ write_op[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec);
+ write_op[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min);
+ write_op[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour);
+ write_op[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday);
+ write_op[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday);
+ write_op[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon);
+ write_op[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100);
+ write_op[RTC_OFFSET_REG_ADDR] = 0;
- if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)))
- return -EIO;
-
- if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)))
- return -EIO;
-
- if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)))
- return -EIO;
-
- return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
+ return dm_i2c_write(dev, 0, &write_op[0], 8);
}
/*
* Reset the RTC
*/
-static int rx8025_rtc_reset(DEV_TYPE *dev)
+static int rx8025_rtc_reset(struct udevice *dev)
{
uchar buf[16];
uchar ctl2;
-#ifdef CONFIG_DM_RTC
if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
-#else
- if (i2c_read(dev->chip, 0, 0, buf, 16)) {
-#endif
printf("Error reading from RTC\n");
return -EIO;
}
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
- ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
+
+ if (dev->driver_data == model_rx_8035)
+ ctl2 &= ~(RTC_CTL2_BIT_XST);
+ else
+ ctl2 |= RTC_CTL2_BIT_XST;
return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2);
}
/*
* Helper functions
*/
-static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val)
+static int rtc_write(struct udevice *dev, uchar reg, uchar val)
{
- uchar buf[2];
- buf[0] = reg << 4;
- buf[1] = val;
-
-#ifdef CONFIG_DM_RTC
- if (dm_i2c_write(dev, 0, buf, 2)) {
-#else
- if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) {
-#endif
+ /* The RX8025/RX8035 uses the top 4 bits of the
+ * 'offset' byte as the start register address,
+ * and the bottom 4 bits as a 'transfer' mode setting
+ * (only applicable for reads)
+ */
+ u8 offset = (reg << 4);
+
+ if (dm_i2c_reg_write(dev, offset, val)) {
printf("Error writing to RTC\n");
return -EIO;
}
return 0;
}
-#ifdef CONFIG_DM_RTC
static int rx8025_probe(struct udevice *dev)
{
uchar buf[16];
};
static const struct udevice_id rx8025_rtc_ids[] = {
- { .compatible = "epson,rx8025" },
+ { .compatible = "epson,rx8025", .data = model_rx_8025 },
+ { .compatible = "epson,rx8035", .data = model_rx_8035 },
{ }
};
-U_BOOT_DRIVER(rx8010sj_rtc) = {
+U_BOOT_DRIVER(rx8025_rtc) = {
.name = "rx8025_rtc",
.id = UCLASS_RTC,
.probe = rx8025_probe,
.of_match = rx8025_rtc_ids,
.ops = &rx8025_rtc_ops,
};
-#else
-int rtc_get(struct rtc_time *tm)
-{
- struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
- };
-
- return rx8025_rtc_get(&dev, tm);
-}
-
-int rtc_set(struct rtc_time *tm)
-{
- struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
- };
-
- return rx8025_rtc_set(&dev, tm);
-}
-
-void rtc_reset(void)
-{
- struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
- };
-
- rx8025_rtc_reset(&dev);
-}
-#endif
endif
ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_SATA_SUPPORT
+ifdef CONFIG_SPL_SATA
obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
obj-$(CONFIG_SCSI) += scsi.o
endif
# Serial device configuration
#
-menu "Serial drivers"
+menuconfig SERIAL
+ bool "Serial"
+ default y
+ help
+ Enable support for serial drivers. This allows use of a serial UART
+ for displaying messages while U-Boot is running. It also brings in
+ printf() and panic() functions. This should normally be enabled
+ unless there are space reasons not to. If you just need to disable
+ the console you can adjust the stdout environment variable or use
+ SILENT_CONSOLE.
+
+if SERIAL
config BAUDRATE
int "Default baudrate"
config SERIAL_PROBE_ALL
bool "Probe all available serial devices"
depends on DM_SERIAL
- default n
help
The serial subsystem only probes for a single serial device,
but does not probe for other remaining serial devices.
U-Boot when running on top of EFI (Extensive Firmware Interface).
This is a type of BIOS used by PCs.
+config DEBUG_SBI_CONSOLE
+ bool "SBI"
+ depends on SBI_V01
+ help
+ Select this to enable a debug console which calls back to SBI to
+ output to the console. This can be useful for early debugging of
+ U-Boot when running on top of SBI (Supervisor Binary Interface).
+
config DEBUG_UART_S5P
bool "Samsung S5P"
depends on ARCH_EXYNOS || ARCH_S5PC1XX
config DEBUG_UART_BASE
hex "Base address of UART"
depends on DEBUG_UART
+ default 0 if DEBUG_SBI_CONSOLE
default 0 if DEBUG_UART_SANDBOX
help
This is the base address of your UART for memory-mapped UARTs.
config DEBUG_UART_CLOCK
int "UART input clock"
depends on DEBUG_UART
+ default 0 if DEBUG_SBI_CONSOLE
default 0 if DEBUG_UART_SANDBOX
default 0 if DEBUG_MVEBU_A3700_UART
help
config MVEBU_A3700_UART
bool "UART support for Armada 3700"
- default n
help
Choose this option to add support for UART driver on the Marvell
Armada 3700 SoC. The base address is configured via DT.
config MXC_UART
bool "IMX serial port support"
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
- || MX5 || MX6 || MX7 || IMX8M
+ depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
help
If you have a machine based on a Motorola IMX CPU you
can enable its onboard serial port by enabling this option.
depends on MPC8XX_CONS
default 0
-endmenu
+endif
obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
obj-$(CONFIG_CORTINA_UART) += serial_cortina.o
+obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += serial_mcf.o
#endif
#endif /* !CONFIG_DM_SERIAL */
-#if defined(CONFIG_SOC_KEYSTONE)
+#if defined(CONFIG_ARCH_KEYSTONE)
#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
#undef UART_MCRVAL
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
#endif
-#if defined(CONFIG_SOC_KEYSTONE)
+#if defined(CONFIG_ARCH_KEYSTONE)
serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
#endif
}
};
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int ns16550_serial_of_to_plat(struct udevice *dev)
{
struct ns16550_plat *plat = dev_get_plat(dev);
.getinfo = ns16550_serial_getinfo,
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/*
* Please consider existing compatible strings before adding a new
* one to keep this table compact. Or you may add a generic "ns16550"
{ .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
{}
};
-#endif /* OF_CONTROL && !OF_PLATDATA */
+#endif /* OF_REAL */
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
U_BOOT_DRIVER(ns16550_serial) = {
.name = "ns16550_serial",
.id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = ns16550_serial_ids,
.of_to_plat = ns16550_serial_of_to_plat,
.plat_auto = sizeof(struct ns16550_plat),
.flags = DM_FLAG_PRE_RELOC,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct sandbox_serial_plat platdata_non_fdt = {
.colour = -1,
};
*/
static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
-#if !CONFIG_VAL(SYS_MALLOC_F_LEN)
-#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work"
-#endif
-
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_check_stdout(const void *blob, struct udevice **devp)
{
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
- priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bit-rate", UART_DM_CLK_RX_TX_BIT_RATE);
return 0;
return 0;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int mt7620_serial_of_to_plat(struct udevice *dev)
{
struct mt7620_serial_plat *plat = dev_get_plat(dev);
U_BOOT_DRIVER(serial_mt7620) = {
.name = "serial_mt7620",
.id = UCLASS_SERIAL,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = mt7620_serial_ids,
.of_to_plat = mt7620_serial_of_to_plat,
#endif
#if CONFIG_IS_ENABLED(DM_SERIAL)
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int omap_serial_of_to_plat(struct udevice *dev)
{
struct ns16550_plat *plat = dev_get_plat(dev);
{ .compatible = "ti,am654-uart", },
{}
};
-#endif /* OF_CONTROL && !OF_PLATDATA */
+#endif /* OF_REAL */
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
U_BOOT_DRIVER(omap_serial) = {
.name = "omap_serial",
.id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap_serial_ids,
.of_to_plat = omap_serial_of_to_plat,
.plat_auto = sizeof(struct ns16550_plat),
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <debug_uart.h>
+#include <asm/sbi.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ if (CONFIG_IS_ENABLED(RISCV_SMODE))
+ sbi_console_putchar(c);
+}
+
+DEBUG_UART_FUNCS
.probe = sti_asc_serial_probe,
.priv_auto = sizeof(struct sti_asc_serial),
};
-
.flags = DM_FLAG_PRE_RELOC,
#endif
};
-
#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
-#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
-#endif
+#define ALTERA_SPI_IDLE_VAL 0xff
struct altera_spi_regs {
u32 rxdata;
if (txp)
data = *txp++;
else
- data = CONFIG_ALTERA_SPI_IDLE_VAL;
+ data = ALTERA_SPI_IDLE_VAL;
debug("%s: tx:%x ", __func__, data);
writel(data, ®s->txdata);
unsigned int freq;
ulong clock;
unsigned int mode;
- u8 num_cs;
+ u8 num_cs;
unsigned int mtiming;
size_t cmd_len;
u8 cmd_buf[16];
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
U_BOOT_DRIVER(coldfire_spi) = {
.name = "spi_coldfire",
.id = UCLASS_SPI,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = coldfire_spi_ids,
.of_to_plat = coldfire_dspi_of_to_plat,
.plat_auto = sizeof(struct coldfire_spi_plat),
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int davinci_ofdata_to_platadata(struct udevice *bus)
{
struct davinci_spi_plat *plat = dev_get_plat(bus);
U_BOOT_DRIVER(davinci_spi) = {
.name = "davinci_spi",
.id = UCLASS_SPI,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = davinci_spi_ids,
.of_to_plat = davinci_ofdata_to_platadata,
.plat_auto = sizeof(struct davinci_spi_plat),
.set_mode = fsl_espi_set_mode,
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int fsl_espi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
U_BOOT_DRIVER(fsl_espi) = {
.name = "fsl_espi",
.id = UCLASS_SPI,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = fsl_espi_ids,
.of_to_plat = fsl_espi_of_to_plat,
#endif
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/**
* ich_spi_get_basics() - Get basic information about the ICH device
*
uint *map_sizep, uint *offsetp)
{
pci_dev_t spi_bdf;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
if (device_is_on_pci_bus(bus)) {
struct pci_child_plat *pplat;
{
struct ich_spi_plat *plat = dev_get_plat(dev);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct ich_spi_priv *priv = dev_get_priv(dev);
int ret;
DECLARE_GLOBAL_DATA_PTR;
/* MX35 and older is CSPI */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX31)
#define MXC_CSPI
struct cspi_regs {
u32 rxdata;
#define MXC_CSPICTRL_RXOVF BIT(6)
#define MXC_CSPIPERIOD_32KHZ BIT(15)
#define MAX_SPI_BYTES 4
-#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_TC BIT(7)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#else /* MX31 */
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
#define MXC_CSPICTRL_TC BIT(8)
#define MXC_CSPICTRL_MAXBITS 0x1f
-#endif
#else /* MX51 and newer is ECSPI */
#define MXC_ECSPI
MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
MXC_CSPICTRL_DATARATE(div) |
MXC_CSPICTRL_EN |
-#ifdef CONFIG_MX35
- MXC_CSPICTRL_SSCTL |
-#endif
MXC_CSPICTRL_MODE;
if (mode & SPI_CPHA)
*/
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int mxs_of_to_plat(struct udevice *bus)
{
struct mxs_spi_plat *plat = dev_get_plat(bus);
U_BOOT_DRIVER(fsl_imx23_spi) = {
.name = "fsl_imx23_spi",
.id = UCLASS_SPI,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = mxs_spi_ids,
.of_to_plat = mxs_of_to_plat,
#endif
*/
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static struct omap2_mcspi_platform_config omap2_pdata = {
.regs_offset = 0,
};
.name = "omap3_spi",
.id = UCLASS_SPI,
.flags = DM_FLAG_PRE_RELOC,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap3_spi_ids,
.of_to_plat = omap3_spi_of_to_plat,
.plat_auto = sizeof(struct omap3_spi_plat),
.cs_info = pl022_cs_info,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int pl022_spi_of_to_plat(struct udevice *bus)
{
struct pl022_spi_pdata *plat = dev_get_plat(bus);
U_BOOT_DRIVER(pl022_spi) = {
.name = "pl022_spi",
.id = UCLASS_SPI,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = pl022_spi_ids,
.of_to_plat = pl022_spi_of_to_plat,
#endif
plat->base = dtplat->reg[0];
plat->frequency = 20000000;
- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
+ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
if (ret < 0)
return ret;
static int rockchip_spi_of_to_plat(struct udevice *bus)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
- plat->base = dev_read_addr(bus);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ plat->base = dev_read_addr(bus);
- ret = clk_get_by_index(bus, 0, &priv->clk);
- if (ret < 0) {
- debug("%s: Could not get clock for %s: %d\n", __func__,
- bus->name, ret);
- return ret;
- }
+ ret = clk_get_by_index(bus, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Could not get clock for %s: %d\n", __func__,
+ bus->name, ret);
+ return ret;
+ }
- plat->frequency =
- dev_read_u32_default(bus, "spi-max-frequency", 50000000);
- plat->deactivate_delay_us =
- dev_read_u32_default(bus, "spi-deactivate-delay", 0);
- plat->activate_delay_us =
- dev_read_u32_default(bus, "spi-activate-delay", 0);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 50000000);
+ plat->deactivate_delay_us =
+ dev_read_u32_default(bus, "spi-deactivate-delay", 0);
+ plat->activate_delay_us =
+ dev_read_u32_default(bus, "spi-activate-delay", 0);
- debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
- __func__, (uint)plat->base, plat->frequency,
- plat->deactivate_delay_us);
-#endif
+ debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, (uint)plat->base, plat->frequency,
+ plat->deactivate_delay_us);
+ }
return 0;
}
break;
}
- pin = name_to_gpio(pin_name);
+ pin = sunxi_name_to_gpio(pin_name);
if (pin < 0)
break;
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int spi_child_post_bind(struct udevice *dev)
{
struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
static int spi_post_probe(struct udevice *bus)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
- spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
-#endif
+ spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
+ }
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
static int reloc_done;
.id = UCLASS_SPI,
.name = "spi",
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
.post_probe = spi_post_probe,
.per_device_auto = sizeof(struct dm_spi_bus),
.per_child_auto = sizeof(struct spi_slave),
.per_child_plat_auto = sizeof(struct dm_spi_slave_plat),
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.child_post_bind = spi_child_post_bind,
#endif
};
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ The extension was introduced in version 0.3 of the SBI specification.
+
+ If the SBI implementation provides the extension, is board specific.
+ The RISC-V platform specification mandates the extension for rich
+ operating system platforms.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10)
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
.ops = &sandbox_warm_sysreset_ops,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/* This is here in case we don't have a device tree */
U_BOOT_DRVINFO(sysreset_sandbox_non_fdt) = {
.name = "sysreset_sandbox",
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <sysreset.h>
+#include <asm/sbi.h>
+
+static enum sbi_srst_reset_type reset_type_map[SYSRESET_COUNT] = {
+ [SYSRESET_WARM] = SBI_SRST_RESET_TYPE_WARM_REBOOT,
+ [SYSRESET_COLD] = SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ [SYSRESET_POWER] = SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ [SYSRESET_POWER_OFF] = SBI_SRST_RESET_TYPE_SHUTDOWN,
+};
+
+static int sbi_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ enum sbi_srst_reset_type reset_type;
+
+ reset_type = reset_type_map[type];
+ sbi_srst_reset(reset_type, SBI_SRST_RESET_REASON_NONE);
+
+ return -EINPROGRESS;
+}
+
+static int sbi_sysreset_probe(struct udevice *dev)
+{
+ long have_reset;
+
+ have_reset = sbi_probe_extension(SBI_EXT_SRST);
+ if (have_reset)
+ return 0;
+
+ log_warning("SBI has no system reset extension\n");
+ return -ENOENT;
+}
+
+static struct sysreset_ops sbi_sysreset_ops = {
+ .request = sbi_sysreset_request,
+};
+
+U_BOOT_DRIVER(sbi_sysreset) = {
+ .name = "sbi-sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &sbi_sysreset_ops,
+ .probe = sbi_sysreset_probe,
+};
DECLARE_GLOBAL_DATA_PTR;
#define SITES_MAX 16
-#define FLAGS_VER2 0x1
-#define FLAGS_VER3 0x2
+#define FLAGS_VER2 0x1
+#define FLAGS_VER3 0x2
#define TMR_DISABLE 0x0
#define TMR_ME 0x80000000
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Microchip Corporation
- * Wenyou.Yang <wenyou.yang@microchip.com>
+ * Wenyou.Yang <wenyou.yang@microchip.com>
*/
#include <common.h>
/* The timer is available */
rate = timer_get_rate(gd->timer);
timer_get_count(gd->timer, &ticks);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- } else if (ret == -EAGAIN) {
+ } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
/* We have been called so early that the DM is not ready,... */
ofnode node = offset_to_ofnode(-1);
struct rk_timer *timer = NULL;
debug("%s: could not read clock-frequency\n", __func__);
return 0;
}
-#endif
} else {
return 0;
}
static int rockchip_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rockchip_timer_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
- priv->timer = dev_read_addr_ptr(dev);
- if (!priv->timer)
- return -ENOENT;
-#endif
+ priv->timer = dev_read_addr_ptr(dev);
+ if (!priv->timer)
+ return -ENOENT;
+ }
return 0;
}
.probe = stm32_timer_probe,
.ops = &stm32_timer_ops,
};
-
static int timer_pre_probe(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct clk timer_clk;
- int err;
- ulong ret;
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk timer_clk;
+ int err;
+ ulong ret;
- /* It is possible that a timer device has a null ofnode */
- if (!dev_has_ofnode(dev))
- return 0;
+ /*
+ * It is possible that a timer device has a null ofnode
+ */
+ if (!dev_has_ofnode(dev))
+ return 0;
- err = clk_get_by_index(dev, 0, &timer_clk);
- if (!err) {
- ret = clk_get_rate(&timer_clk);
- if (IS_ERR_VALUE(ret))
- return ret;
- uc_priv->clock_rate = ret;
- } else {
- uc_priv->clock_rate =
- dev_read_u32_default(dev, "clock-frequency", 0);
+ err = clk_get_by_index(dev, 0, &timer_clk);
+ if (!err) {
+ ret = clk_get_rate(&timer_clk);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ uc_priv->clock_rate = ret;
+ } else {
+ uc_priv->clock_rate =
+ dev_read_u32_default(dev, "clock-frequency", 0);
+ }
}
-#endif
return 0;
}
if (gd->dm_root == NULL)
return -EAGAIN;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- /* Check for a chosen timer to be used for tick */
- node = ofnode_get_chosen_node("tick-timer");
-
- if (ofnode_valid(node) &&
- uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) {
- /*
- * If the timer is not marked to be bound before
- * relocation, bind it anyway.
- */
- if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) {
- ret = device_probe(dev);
- if (ret)
- return ret;
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ /* Check for a chosen timer to be used for tick */
+ node = ofnode_get_chosen_node("tick-timer");
+
+ if (ofnode_valid(node) &&
+ uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) {
+ /*
+ * If the timer is not marked to be bound before
+ * relocation, bind it anyway.
+ */
+ if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) {
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ }
}
}
-#endif
if (!dev) {
/* Fall back to the first available timer */
.get_count = tsc_timer_get_count,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id tsc_timer_ids[] = {
{ .compatible = "x86,tsc-timer", },
{ }
.id = UCLASS_TPM,
.name = "tpm",
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
.per_device_auto = sizeof(struct tpm_chip_priv),
if (CONFIG_IS_ENABLED(DM_GPIO)) {
struct gpio_desc reset_gpio;
- ret = gpio_request_by_name(dev, "gpio-reset", 0,
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
&reset_gpio, GPIOD_IS_OUT);
if (ret) {
- log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
- __func__);
- } else {
- dm_gpio_set_value(&reset_gpio, 1);
- mdelay(1);
- dm_gpio_set_value(&reset_gpio, 0);
+ /* legacy reset */
+ ret = gpio_request_by_name(dev, "gpio-reset", 0,
+ &reset_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log(LOGC_NONE, LOGL_NOTICE,
+ "%s: missing reset GPIO\n", __func__);
+ goto init;
+ }
+ log(LOGC_NONE, LOGL_NOTICE,
+ "%s: gpio-reset is deprecated\n", __func__);
}
+ dm_gpio_set_value(&reset_gpio, 1);
+ mdelay(1);
+ dm_gpio_set_value(&reset_gpio, 0);
}
-
+init:
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);
* @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
* there's now way for software to detect this in runtime.
* @is_utmi_l1_suspend: the core asserts output signal
- * 0 - utmi_sleep_n
- * 1 - utmi_l1_suspend_n
+ * 0 - utmi_sleep_n
+ * 1 - utmi_l1_suspend_n
* @is_selfpowered: true when we are selfpowered
* @is_fpga: true when we are using the FPGA board
* @needs_fifo_resize: not all users might want fifo resizing, flag it
* @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
- * 0 - -6dB de-emphasis
- * 1 - -3.5dB de-emphasis
- * 2 - No de-emphasis
- * 3 - Reserved
+ * 0 - -6dB de-emphasis
+ * 1 - -3.5dB de-emphasis
+ * 2 - No de-emphasis
+ * 3 - Reserved
* @index: index of _this_ controller
* @list: to maintain the list of dwc3 controllers
*/
static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv)
{
int ret;
-
+
ret = dwc3_meson_gxl_usb2_init(priv);
if (ret)
return ret;
}
static const struct udevice_id dwc3_meson_gxl_ids[] = {
+ { .compatible = "amlogic,meson-axg-usb-ctrl" },
{ .compatible = "amlogic,meson-gxl-usb-ctrl" },
{ .compatible = "amlogic,meson-gxm-usb-ctrl" },
{ }
* BESL value in the LPM token is less than or equal to LPM
* NYET threshold.
*/
- if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
+ if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
#endif /* CONFIG_DM_ETH */
-
#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
-#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
+#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */
#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
#define DBG(stuff...) debug("udc: " stuff)
#endif
-
#include <linux/usb/gadget.h>
#include <linux/usb/composite.h>
#include <linux/compiler.h>
-#include <version.h>
#include <g_dnl.h>
#include <asm/arch-rockchip/f_rockusb.h>
* so using '|=' isn't safe as it may ack an interrupt.
*/
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
-#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE)
+#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE)
static inline void udc_set_mask_UDCCR(int mask)
{
family SoCs. This is a driver for the dwc3 to provide the glue logic
to configure the controller.
+config USB_XHCI_OMAP
+ bool "Support for TI OMAP family xHCI USB controller"
+ depends on ARCH_OMAP2PLUS
+ help
+ Enables support for the on-chip xHCI controller found on some TI SoC
+ families. Note that some families have multiple contollers while
+ others only have something such as DesignWare-based controllers.
+ Consult the SoC documentation to determine if this option applies
+ to your hardware.
+
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
depends on DM_USB
config USB_EHCI_MX5
bool "Support for i.MX5 on-chip EHCI USB controller"
depends on ARCH_MX5
- default n
help
Enables support for the on-chip EHCI controller on i.MX5 SoCs.
Enables support for the on-chip EHCI controller on OMAP3 and later
SoCs.
+if USB_EHCI_OMAP
+
+config HAS_OMAP_EHCI_PHY1_RESET_GPIO
+ bool "PHY #1 requires a GPIO hold to it in RESET while PHY settles"
+ help
+ Enable this to be able to configure the GPIO number used to hold the
+ PHY in RESET for enough time until the PHY is settled and ready.
+
+config OMAP_EHCI_PHY1_RESET_GPIO
+ int "GPIO number to hold PHY #1 in RESET"
+ depends on HAS_OMAP_EHCI_PHY1_RESET_GPIO
+
+config HAS_OMAP_EHCI_PHY2_RESET_GPIO
+ bool "PHY #2 requires a GPIO hold to it in RESET while PHY settles"
+ help
+ Enable this to be able to configure the GPIO number used to hold the
+ PHY in RESET for enough time until the PHY is settled and ready.
+
+config OMAP_EHCI_PHY2_RESET_GPIO
+ int "GPIO number to hold PHY #2 in RESET"
+ depends on HAS_OMAP_EHCI_PHY2_RESET_GPIO
+
+config HAS_OMAP_EHCI_PHY3_RESET_GPIO
+ bool "PHY #3 requires a GPIO hold to it in RESET while PHY settles"
+ help
+ Enable this to be able to configure the GPIO number used to hold the
+ PHY in RESET for enough time until the PHY is settled and ready.
+
+config OMAP_EHCI_PHY3_RESET_GPIO
+ int "GPIO number to hold PHY #3 in RESET"
+ depends on HAS_OMAP_EHCI_PHY3_RESET_GPIO
+
+endif
+
config USB_EHCI_VF
bool "Support for Vybrid on-chip EHCI USB controller"
depends on ARCH_VF610
depends on DM_USB
select USB_ULPI_VIEWPORT
select MSM8916_USB_PHY
- default n
---help---
Enables support for the on-chip EHCI controller on Qualcomm
Snapdragon SoCs.
bool "Support for generic EHCI USB controller"
depends on DM_USB
default ARCH_SUNXI
- default n
---help---
Enables support for generic EHCI controller.
config USB_EHCI_FSL
bool "Support for FSL on-chip EHCI USB controller"
- default n
select CONFIG_EHCI_HCD_INIT_AFTER_RESET
---help---
Enables support for the on-chip EHCI controller on FSL chips.
{
uint32_t phyclk;
-#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
#else
/* High speed PHY running at full speed or high speed */
phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
#endif
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(®s->ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
/* Initialize Host Configuration Register */
init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
+#ifdef DWC2_DFLT_SPEED_FULL
setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
#endif
/* Configure data FIFO sizes */
-#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#ifdef DWC2_ENABLE_DYNAMIC_FIFO
if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
/* Rx FIFO */
- writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
+ writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
/* Non-periodic Tx FIFO */
- nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+ nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
DWC2_FIFOSIZE_DEPTH_OFFSET;
- nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+ nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(nptxfifosize, ®s->gnptxfsiz);
/* Periodic Tx FIFO */
- ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+ ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
DWC2_FIFOSIZE_DEPTH_OFFSET;
- ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
- CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+ ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
+ DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(ptxfifosize, ®s->hptxfsiz);
}
struct dwc2_core_regs *regs = priv->regs;
uint32_t ahbcfg = 0;
uint32_t usbcfg = 0;
- uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
+ uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
/* Common Initialization */
usbcfg = readl(®s->gusbcfg);
}
/* Set external TS Dline pulsing */
-#ifdef CONFIG_DWC2_TS_DLINE
+#ifdef DWC2_TS_DLINE
usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
#else
usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
* This programming sequence needs to happen in FS mode before
* any other programming occurs
*/
-#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
- (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if defined(DWC2_DFLT_SPEED_FULL) && \
+ (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
/* If FS mode with FS PHY */
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_I2C_ENABLE
+#ifdef DWC2_I2C_ENABLE
/* Program GUSBCFG.OtgUtmifsSel to I2C */
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
* immediately after setting phyif.
*/
usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
- usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+ usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
-#ifdef CONFIG_DWC2_PHY_ULPI_DDR
+#ifdef DWC2_PHY_ULPI_DDR
usbcfg |= DWC2_GUSBCFG_DDRSEL;
#else
usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
#endif
} else { /* UTMI+ interface */
-#if (CONFIG_DWC2_UTMI_WIDTH == 16)
+#if (DWC2_UTMI_WIDTH == 16)
usbcfg |= DWC2_GUSBCFG_PHYIF;
#endif
}
usbcfg = readl(®s->gusbcfg);
usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(®s->ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
brst_sz >>= 1;
}
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
#endif
break;
case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
#endif
break;
if (!priv->hnp_srp_disable)
usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
-#ifdef CONFIG_DWC2_IC_USB_CAP
+#ifdef DWC2_IC_USB_CAP
usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
#endif
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
in, len);
- max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
- if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
- max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+ max_xfer_len = DWC2_MAX_PACKET_COUNT * max;
+ if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE)
+ max_xfer_len = DWC2_MAX_TRANSFER_SIZE;
if (max_xfer_len > DWC2_DATA_BUF_SIZE)
max_xfer_len = DWC2_DATA_BUF_SIZE;
return -ENODEV;
}
-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+#ifdef DWC2_PHY_ULPI_EXT_VBUS
priv->ext_vbus = 1;
#else
priv->ext_vbus = 0;
#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* Default driver configuration */
-#define CONFIG_DWC2_DMA_ENABLE
-#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
-#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
-#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */
-#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS)
-#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
-#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
-#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535
-#define CONFIG_DWC2_MAX_PACKET_COUNT 511
+#define DWC2_DMA_ENABLE
+#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
+#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
+#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
+#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */
+#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS)
+#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
+#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
+#define DWC2_MAX_TRANSFER_SIZE 65535
+#define DWC2_MAX_PACKET_COUNT 511
#define DWC2_PHY_TYPE_FS 0
#define DWC2_PHY_TYPE_UTMI 1
#define DWC2_PHY_TYPE_ULPI 2
-#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
-#ifndef CONFIG_DWC2_UTMI_WIDTH
-#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
+#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
+#ifndef DWC2_UTMI_WIDTH
+#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
#endif
-#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
-#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
-#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */
-#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */
-#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */
-#undef CONFIG_DWC2_THR_CTL /* Threshold control */
-#define CONFIG_DWC2_TX_THR_LENGTH 64
-#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */
+#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
+#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
+#undef DWC2_I2C_ENABLE /* Enable I2C */
+#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */
+#undef DWC2_TS_DLINE /* External DLine pulsing */
+#undef DWC2_THR_CTL /* Threshold control */
+#define DWC2_TX_THR_LENGTH 64
+#undef DWC2_IC_USB_CAP /* IC Cap */
#endif /* __DWC2_H__ */
unsigned int v;
v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#if defined(CONFIG_MX25)
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
- MX25_OTG_OCPOL_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX25_OTG_PM_BIT;
-
- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
- v |= MX25_OTG_PP_BIT;
-
- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
- v |= MX25_OTG_OCPOL_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
- MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
- MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
- MX25_H1_IPPUE_UP_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX25_H1_PM_BIT;
-
- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
- v |= MX25_H1_PP_BIT;
-
- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
- v |= MX25_H1_OCPOL_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX25_H1_TLL_BIT;
-
- if (flags & MXC_EHCI_INTERNAL_PHY)
- v |= MX25_H1_USBTE_BIT;
-
- if (flags & MXC_EHCI_IPPUE_DOWN)
- v |= MX25_H1_IPPUE_DOWN_BIT;
-
- if (flags & MXC_EHCI_IPPUE_UP)
- v |= MX25_H1_IPPUE_UP_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-#elif defined(CONFIG_MX31)
+#if defined(CONFIG_MX31)
switch (port) {
case 0: /* OTG port */
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
default:
return -EINVAL;
}
-#elif defined(CONFIG_MX35)
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
- MX35_OTG_OCPOL_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX35_OTG_PM_BIT;
-
- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
- v |= MX35_OTG_PP_BIT;
-
- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
- v |= MX35_OTG_OCPOL_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
- MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
- MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
- MX35_H1_IPPUE_UP_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX35_H1_PM_BIT;
-
- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
- v |= MX35_H1_PP_BIT;
-
- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
- v |= MX35_H1_OCPOL_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX35_H1_TLL_BIT;
-
- if (flags & MXC_EHCI_INTERNAL_PHY)
- v |= MX35_H1_USBTE_BIT;
-
- if (flags & MXC_EHCI_IPPUE_DOWN)
- v |= MX35_H1_IPPUE_DOWN_BIT;
-
- if (flags & MXC_EHCI_IPPUE_UP)
- v |= MX35_H1_IPPUE_UP_BIT;
-
- break;
- default:
- return -EINVAL;
- }
#else
#error MXC EHCI USB driver not supported on this platform
#endif
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
-#ifdef CONFIG_MX35
- /* Workaround for ENGcm11601 */
- __raw_writel(0, &ehci->sbuscfg);
-#endif
udelay(10000);
* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
* See there for additional Copyrights.
*/
-#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)
-
-int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
- *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
-#else
int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata)
{
-#endif
int ret;
unsigned int i, reg = 0, rev = 0;
return 0;
}
-#if CONFIG_IS_ENABLED(DM_USB)
-
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.ops = &ehci_usb_ops,
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-
-#endif
*
* To generate the content of the array below, use ie. the following command:
* $ hexdump -v -e '/4 "0x%08x, "' r8a779x_usb3_v3.dlmem | \
- * sed "s@\(.\{47\}\) @\1\n@g"
+ * sed "s@\(.\{47\}\) @\1\n@g"
*
* [1] git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
*/
bool "Enable TI OTG USB controller"
depends on AM33XX
select USB_MUSB_DSPS
- default n
help
Say y here to enable support for the dual role high
speed USB controller based on the Mentor Graphics
config USB_MUSB_MT85XX
bool "Enable Mediatek MT85XX DRC USB controller"
depends on ARCH_MEDIATEK
- default n
help
Say y to enable Mediatek MT85XX USB DRC controller support
if it is available on your Mediatek MUSB IP based platform.
&& (musb_ep->dma->actual_len
== musb_ep->packet_sz)) {
/* In double buffer case, continue to unload fifo if
- * there is Rx packet in FIFO.
- **/
+ * there is Rx packet in FIFO.
+ **/
csr = musb_readw(epio, MUSB_RXCSR);
if ((csr & MUSB_RXCSR_RXPKTRDY) &&
hw_ep->rx_double_buffered)
/* SUNXI has different reg addresses, but identical r/w functions */
-#ifndef CONFIG_ARCH_SUNXI
+#ifndef CONFIG_ARCH_SUNXI
/*
* Common USB registers
static int _musb_destroy_int_queue(struct musb_host_data *host,
struct usb_device *dev, struct int_queue *queue)
{
- int index = usb_pipein(queue->urb.pipe) * 16 +
+ int index = usb_pipein(queue->urb.pipe) * 16 +
usb_pipeendpoint(queue->urb.pipe);
if (queue->urb.status == -EINPROGRESS)
#include <reset.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/root.h>
/* TxType/RxType */
#define MUSB_TYPE_SPEED 0xc0
#define MUSB_TYPE_SPEED_SHIFT 6
-#define MUSB_TYPE_SPEED_HIGH 1
-#define MUSB_TYPE_SPEED_FULL 2
+#define MUSB_TYPE_SPEED_HIGH 1
+#define MUSB_TYPE_SPEED_FULL 2
#define MUSB_TYPE_SPEED_LOW 3
#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
#define MUSB_TYPE_PROTO_SHIFT 4
#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
-#define MUSB_TYPE_PROTO_BULK 2
-#define MUSB_TYPE_PROTO_INTR 3
+#define MUSB_TYPE_PROTO_BULK 2
+#define MUSB_TYPE_PROTO_INTR 3
/* CONFIGDATA */
#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
* values are not supported
*/
struct musb_epinfo {
- u8 epnum; /* endpoint number */
+ u8 epnum; /* endpoint number */
u8 epdir; /* endpoint direction */
u16 epsize; /* endpoint FIFO size */
};
#include "musb_hcd.h"
/* MSC control transfers */
-#define USB_MSC_BBB_RESET 0xFF
+#define USB_MSC_BBB_RESET 0xFF
#define USB_MSC_BBB_GET_MAX_LUN 0xFE
/* Endpoint configuration information */
/* Set TXPKTRDY bit */
csr = readw(&musbr->txcsr);
-
+
csr |= MUSB_CSR0_TXPKTRDY;
csr |= MUSB_CSR0_H_DIS_PING;
writew(csr, &musbr->txcsr);
config TWL4030_USB
bool "TWL4030 PHY"
-config OMAP_USB_PHY
- bool "OMAP PHY"
-
config ROCKCHIP_USB2_PHY
bool "Rockchip USB2 PHY"
# Tom Rix <Tom.Rix@windriver.com>
obj-$(CONFIG_TWL4030_USB) += twl4030.o
-obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * OMAP USB PHY Support
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Author: Dan Murphy <dmurphy@ti.com>
- */
-
-#include <common.h>
-#include <usb.h>
-#include <dm/device_compat.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/omap_common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-
-#include <linux/compat.h>
-#include <linux/usb/dwc3.h>
-#include <linux/usb/xhci-omap.h>
-
-#include <usb/xhci.h>
-
-#ifdef CONFIG_OMAP_USB3PHY1_HOST
-struct usb3_dpll_params {
- u16 m;
- u8 n;
- u8 freq:3;
- u8 sd;
- u32 mf;
-};
-
-struct usb3_dpll_map {
- unsigned long rate;
- struct usb3_dpll_params params;
- struct usb3_dpll_map *dpll_map;
-};
-
-static struct usb3_dpll_map dpll_map_usb[] = {
- {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
- {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
- {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
- {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
- {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
- {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
- { }, /* Terminator */
-};
-
-static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
-{
- unsigned long rate;
- struct usb3_dpll_map *dpll_map = dpll_map_usb;
-
- rate = get_sys_clk_freq();
-
- for (; dpll_map->rate; dpll_map++) {
- if (rate == dpll_map->rate)
- return &dpll_map->params;
- }
-
- dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
-
- return NULL;
-}
-
-static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
-{
- u32 val;
-
- writel(SET_PLL_GO, &phy_regs->pll_go);
- do {
- val = readl(&phy_regs->pll_status);
- if (val & PLL_LOCK)
- break;
- } while (1);
-}
-
-static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
-{
- struct usb3_dpll_params *dpll_params;
- u32 val;
-
- dpll_params = omap_usb3_get_dpll_params();
- if (!dpll_params)
- return;
-
- val = readl(&phy_regs->pll_config_1);
- val &= ~PLL_REGN_MASK;
- val |= dpll_params->n << PLL_REGN_SHIFT;
- writel(val, &phy_regs->pll_config_1);
-
- val = readl(&phy_regs->pll_config_2);
- val &= ~PLL_SELFREQDCO_MASK;
- val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
- writel(val, &phy_regs->pll_config_2);
-
- val = readl(&phy_regs->pll_config_1);
- val &= ~PLL_REGM_MASK;
- val |= dpll_params->m << PLL_REGM_SHIFT;
- writel(val, &phy_regs->pll_config_1);
-
- val = readl(&phy_regs->pll_config_4);
- val &= ~PLL_REGM_F_MASK;
- val |= dpll_params->mf << PLL_REGM_F_SHIFT;
- writel(val, &phy_regs->pll_config_4);
-
- val = readl(&phy_regs->pll_config_3);
- val &= ~PLL_SD_MASK;
- val |= dpll_params->sd << PLL_SD_SHIFT;
- writel(val, &phy_regs->pll_config_3);
-
- omap_usb_dpll_relock(phy_regs);
-}
-
-static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
-{
- u32 rate = get_sys_clk_freq()/1000000;
- u32 val;
-
- val = readl((*ctrl)->control_phy_power_usb);
- val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
- val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
- val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
-
- writel(val, (*ctrl)->control_phy_power_usb);
-}
-
-void usb_phy_power(int on)
-{
- u32 val;
-
- val = readl((*ctrl)->control_phy_power_usb);
- if (on) {
- val &= ~USB3_PWRCTL_CLK_CMD_MASK;
- val |= USB3_PHY_TX_RX_POWERON;
- } else {
- val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
- }
-
- writel(val, (*ctrl)->control_phy_power_usb);
-}
-
-void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
-{
- omap_usb_dpll_lock(phy_regs);
- usb3_phy_partial_powerup(phy_regs);
- /*
- * Give enough time for the PHY to partially power-up before
- * powering it up completely. delay value suggested by the HW
- * team.
- */
- mdelay(100);
-}
-
-static void omap_enable_usb3_phy(struct omap_xhci *omap)
-{
- u32 val;
-
- val = (USBOTGSS_DMADISABLE |
- USBOTGSS_STANDBYMODE_SMRT_WKUP |
- USBOTGSS_IDLEMODE_NOIDLE);
- writel(val, &omap->otg_wrapper->sysconfig);
-
- /* Clear the utmi OTG status */
- val = readl(&omap->otg_wrapper->utmi_otg_status);
- writel(val, &omap->otg_wrapper->utmi_otg_status);
-
- /* Enable interrupts */
- writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
- val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
- USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
- USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
- USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
- USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
- USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
- USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
- USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
- USBOTGSS_IRQ_SET_1_OEVT_EN);
- writel(val, &omap->otg_wrapper->irqenable_set_1);
-
- /* Clear the IRQ status */
- val = readl(&omap->otg_wrapper->irqstatus_1);
- writel(val, &omap->otg_wrapper->irqstatus_1);
- val = readl(&omap->otg_wrapper->irqstatus_0);
- writel(val, &omap->otg_wrapper->irqstatus_0);
-};
-#endif /* CONFIG_OMAP_USB3PHY1_HOST */
-
-#ifdef CONFIG_OMAP_USB2PHY2_HOST
-static void omap_enable_usb2_phy2(struct omap_xhci *omap)
-{
- u32 reg, val;
-
- val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
- writel(val, (*ctrl)->control_srcomp_north_side);
-
- setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
- (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
- OTG_SS_CLKCTRL_MODULEMODE_HW));
-
- /* This is an undocumented Reserved register */
- reg = 0x4a0086c0;
- val = readl(reg);
- val |= 0x100;
- setbits_le32(reg, val);
-}
-
-void usb_phy_power(int on)
-{
- return;
-}
-#endif /* CONFIG_OMAP_USB2PHY2_HOST */
-
-#ifdef CONFIG_AM437X_USB2PHY2_HOST
-static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
-{
- const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
- USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
-
- writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
- writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
-
- writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
- writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
-}
-
-void usb_phy_power(int on)
-{
- u32 val;
-
- /* USB1_CTRL */
- val = readl(USB1_CTRL);
- if (on) {
- /*
- * these bits are re-used on AM437x to power up/down the USB
- * CM and OTG PHYs, if we don't toggle them, USB will not be
- * functional on newer silicon revisions
- */
- val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
- } else {
- val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
- }
-
- writel(val, USB1_CTRL);
-}
-#endif /* CONFIG_AM437X_USB2PHY2_HOST */
-
-void omap_enable_phy(struct omap_xhci *omap)
-{
-#ifdef CONFIG_OMAP_USB2PHY2_HOST
- omap_enable_usb2_phy2(omap);
-#endif
-
-#ifdef CONFIG_AM437X_USB2PHY2_HOST
- am437x_enable_usb2_phy2(omap);
-#endif
-
-#ifdef CONFIG_OMAP_USB3PHY1_HOST
- omap_enable_usb3_phy(omap);
- omap_usb3_phy_init(omap->usb3_phy);
-#endif
-}
config VIDEO_VESA
bool "Enable VESA video driver support"
- default n
help
Turn on this option to enable a very simple driver which uses vesa
to discover the video mode and then provides a frame buffer for use
config VIDEO_LCD_ANX9804
bool "ANX9804 bridge chip"
- default n
---help---
Support for the ANX9804 bridge chip, which can take pixel data coming
from a parallel LCD interface and translate it on the fy into a DP
bool "OTM8009A DSI LCD panel support"
depends on DM_VIDEO
select VIDEO_MIPI_DSI
- default n
help
Say Y here if you want to enable support for Orise Technology
otm8009a 480x800 dsi 2dl panel.
bool "RM68200 DSI LCD panel support"
depends on DM_VIDEO
select VIDEO_MIPI_DSI
- default n
help
Say Y here if you want to enable support for Raydium RM68200
720x1280 DSI video mode panel.
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
- default n
---help---
Support for the SSD2828 bridge chip, which can take pixel data coming
from a parallel LCD interface and translate it on the fly into MIPI DSI
default ""
---help---
The reset pin of SSD2828 chip. This takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_TDO_TL070WSH30
bool "TDO TL070WSH30 DSI LCD panel support"
depends on DM_VIDEO
select VIDEO_MIPI_DSI
- default n
help
Say Y here if you want to enable support for TDO TL070WSH30
1024x600 DSI video mode panel.
config VIDEO_LCD_HITACHI_TX18D42VM
bool "Hitachi tx18d42vm LVDS LCD panel support"
- default n
---help---
Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_SCLK
string "SPI SCLK pin for LCD related config job"
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_MOSI
string "SPI MOSI pin for LCD related config job"
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_MISO
string "SPI MISO pin for LCD related config job (optional)"
different hardware setups. If wired up, this pin may provide additional
useful functionality. Such as bi-directional communication with the
hardware and LCD panel id retrieval (if the panel can report it). The
- option takes a string in the format understood by 'name_to_gpio'
+ option takes a string in the format understood by 'sunxi_name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
source "drivers/video/meson/Kconfig"
config VIDEO_MVEBU
bool "Armada XP LCD controller"
- default n
---help---
Support for the LCD controller integrated in the Marvell
Armada XP SoC.
config I2C_EDID
bool "Enable EDID library"
- default n
help
This enables library for accessing EDID data from an LCD panel.
config DISPLAY
bool "Enable Display support"
depends on DM
- default n
select I2C_EDID
help
This supports drivers that provide a display, such as eDP (Embedded
config NXP_TDA19988
bool "Enable NXP TDA19988 support"
depends on DISPLAY
- default n
help
This enables support for the NXP TDA19988 HDMI encoder. This encoder
will convert RGB data streams into HDMI-encoded signals.
source "drivers/video/imx/Kconfig"
+config VIDEO_MXS
+ bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs"
+ depends on DM_VIDEO
+ help
+ Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors
+
config VIDEO_NX
bool "Enable video support on Nexell SoC"
depends on ARCH_S5P6818 || ARCH_S5P4418
config OSD
bool "Enable OSD support"
depends on DM
- default n
help
This supports drivers that provide a OSD (on-screen display), which
is a (usually text-oriented) graphics buffer to show information on
config VIDEO_VCXK
bool "Enable VCXK video controller driver support"
- default n
help
This enables VCXK driver which can be used with VC2K, VC4K
and VC8K devices on various boards from BuS Elektronik GmbH.
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
obj-y += ti/
-obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
-obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
* This function will init an anx9804 parallel lcd to dp bridge chip
* using the passed in parameters.
*
- * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
+ * @i2c_bus: Device of the i2c bus to which the anx9804 is connected.
* @lanes: Number of displayport lanes to use
* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
* @bpp: Bits per pixel, must be 18 or 24
*/
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
{
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- u8 c, colordepth;
- int i;
+ struct udevice *chip0, *chip1;
+ int c, colordepth, i, ret;
- i2c_set_bus_num(i2c_bus);
+ ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
+ if (ret)
+ return;
+
+ ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
+ if (ret)
+ return;
if (bpp == 18)
colordepth = 0x00; /* 6 bit */
colordepth = 0x10; /* 8 bit */
/* Reset */
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
mdelay(100);
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
/* Write 0 to the powerdown reg (powerup everything) */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
- c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
+ c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
if (c != 0x98) {
printf("Error anx9804 chipid mismatch\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
- i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
break;
if (i == 100)
printf("Error anx9804 clock is not stable\n");
- i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
-
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
+
/* Set a bunch of analog related register values */
- i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
- i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
- i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
+ dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
/* Force HPD */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
/* Power up and configure lanes */
- i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
/* Reset AUX CH */
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE);
/* Powerdown audio and some other unused bits */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
- i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
- i2c_reg_write(0x38, 0xa7, 0x00);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
+ dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
+ dm_i2c_reg_write(chip0, 0xa7, 0x00);
/* Set data-rate / lanes */
- i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
- i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
+ dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
- /* Link training */
- i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
- ANX9804_LINK_TRAINING_CTRL_EN);
+ /* Link training */
+ dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
+ ANX9804_LINK_TRAINING_CTRL_EN);
mdelay(5);
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
if ((c & 0x01) == 0)
break;
}
if(i == 100) {
printf("Error anx9804 link training timeout\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
/* Enable */
- i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
- ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
+ ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
/* Force stream valid */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
- ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
-
- i2c_set_bus_num(orig_i2c_bus);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
+ ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
}
#define ANX9804_DATA_RATE_2700M 0x0a
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp);
#else
-static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate,
+static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate,
int bpp) {}
#endif
+
#endif
+++ /dev/null
-/*
- * ATI PCI IDs from XFree86, kept here to make sync'ing with
- * XFree much simpler. Currently, this list is only used by
- * radeonfb
- */
-
-#define PCI_CHIP_RV380_3150 0x3150
-#define PCI_CHIP_RV380_3151 0x3151
-#define PCI_CHIP_RV380_3152 0x3152
-#define PCI_CHIP_RV380_3153 0x3153
-#define PCI_CHIP_RV380_3154 0x3154
-#define PCI_CHIP_RV380_3156 0x3156
-#define PCI_CHIP_RV380_3E50 0x3E50
-#define PCI_CHIP_RV380_3E51 0x3E51
-#define PCI_CHIP_RV380_3E52 0x3E52
-#define PCI_CHIP_RV380_3E53 0x3E53
-#define PCI_CHIP_RV380_3E54 0x3E54
-#define PCI_CHIP_RV380_3E56 0x3E56
-#define PCI_CHIP_RS100_4136 0x4136
-#define PCI_CHIP_RS200_4137 0x4137
-#define PCI_CHIP_R300_AD 0x4144
-#define PCI_CHIP_R300_AE 0x4145
-#define PCI_CHIP_R300_AF 0x4146
-#define PCI_CHIP_R300_AG 0x4147
-#define PCI_CHIP_R350_AH 0x4148
-#define PCI_CHIP_R350_AI 0x4149
-#define PCI_CHIP_R350_AJ 0x414A
-#define PCI_CHIP_R350_AK 0x414B
-#define PCI_CHIP_RV350_AP 0x4150
-#define PCI_CHIP_RV350_AQ 0x4151
-#define PCI_CHIP_RV360_AR 0x4152
-#define PCI_CHIP_RV350_AS 0x4153
-#define PCI_CHIP_RV350_AT 0x4154
-#define PCI_CHIP_RV350_AV 0x4156
-#define PCI_CHIP_MACH32 0x4158
-#define PCI_CHIP_RS250_4237 0x4237
-#define PCI_CHIP_R200_BB 0x4242
-#define PCI_CHIP_R200_BC 0x4243
-#define PCI_CHIP_RS100_4336 0x4336
-#define PCI_CHIP_RS200_4337 0x4337
-#define PCI_CHIP_MACH64CT 0x4354
-#define PCI_CHIP_MACH64CX 0x4358
-#define PCI_CHIP_RS250_4437 0x4437
-#define PCI_CHIP_MACH64ET 0x4554
-#define PCI_CHIP_MACH64GB 0x4742
-#define PCI_CHIP_MACH64GD 0x4744
-#define PCI_CHIP_MACH64GI 0x4749
-#define PCI_CHIP_MACH64GL 0x474C
-#define PCI_CHIP_MACH64GM 0x474D
-#define PCI_CHIP_MACH64GN 0x474E
-#define PCI_CHIP_MACH64GO 0x474F
-#define PCI_CHIP_MACH64GP 0x4750
-#define PCI_CHIP_MACH64GQ 0x4751
-#define PCI_CHIP_MACH64GR 0x4752
-#define PCI_CHIP_MACH64GS 0x4753
-#define PCI_CHIP_MACH64GT 0x4754
-#define PCI_CHIP_MACH64GU 0x4755
-#define PCI_CHIP_MACH64GV 0x4756
-#define PCI_CHIP_MACH64GW 0x4757
-#define PCI_CHIP_MACH64GX 0x4758
-#define PCI_CHIP_MACH64GY 0x4759
-#define PCI_CHIP_MACH64GZ 0x475A
-#define PCI_CHIP_RV250_Id 0x4964
-#define PCI_CHIP_RV250_Ie 0x4965
-#define PCI_CHIP_RV250_If 0x4966
-#define PCI_CHIP_RV250_Ig 0x4967
-#define PCI_CHIP_R420_JH 0x4A48
-#define PCI_CHIP_R420_JI 0x4A49
-#define PCI_CHIP_R420_JJ 0x4A4A
-#define PCI_CHIP_R420_JK 0x4A4B
-#define PCI_CHIP_R420_JL 0x4A4C
-#define PCI_CHIP_R420_JM 0x4A4D
-#define PCI_CHIP_R420_JN 0x4A4E
-#define PCI_CHIP_R420_JP 0x4A50
-#define PCI_CHIP_MACH64LB 0x4C42
-#define PCI_CHIP_MACH64LD 0x4C44
-#define PCI_CHIP_RAGE128LE 0x4C45
-#define PCI_CHIP_RAGE128LF 0x4C46
-#define PCI_CHIP_MACH64LG 0x4C47
-#define PCI_CHIP_MACH64LI 0x4C49
-#define PCI_CHIP_MACH64LM 0x4C4D
-#define PCI_CHIP_MACH64LN 0x4C4E
-#define PCI_CHIP_MACH64LP 0x4C50
-#define PCI_CHIP_MACH64LQ 0x4C51
-#define PCI_CHIP_MACH64LR 0x4C52
-#define PCI_CHIP_MACH64LS 0x4C53
-#define PCI_CHIP_MACH64LT 0x4C54
-#define PCI_CHIP_RADEON_LW 0x4C57
-#define PCI_CHIP_RADEON_LX 0x4C58
-#define PCI_CHIP_RADEON_LY 0x4C59
-#define PCI_CHIP_RADEON_LZ 0x4C5A
-#define PCI_CHIP_RV250_Ld 0x4C64
-#define PCI_CHIP_RV250_Le 0x4C65
-#define PCI_CHIP_RV250_Lf 0x4C66
-#define PCI_CHIP_RV250_Lg 0x4C67
-#define PCI_CHIP_RV250_Ln 0x4C6E
-#define PCI_CHIP_RAGE128MF 0x4D46
-#define PCI_CHIP_RAGE128ML 0x4D4C
-#define PCI_CHIP_R300_ND 0x4E44
-#define PCI_CHIP_R300_NE 0x4E45
-#define PCI_CHIP_R300_NF 0x4E46
-#define PCI_CHIP_R300_NG 0x4E47
-#define PCI_CHIP_R350_NH 0x4E48
-#define PCI_CHIP_R350_NI 0x4E49
-#define PCI_CHIP_R360_NJ 0x4E4A
-#define PCI_CHIP_R350_NK 0x4E4B
-#define PCI_CHIP_RV350_NP 0x4E50
-#define PCI_CHIP_RV350_NQ 0x4E51
-#define PCI_CHIP_RV350_NR 0x4E52
-#define PCI_CHIP_RV350_NS 0x4E53
-#define PCI_CHIP_RV350_NT 0x4E54
-#define PCI_CHIP_RV350_NV 0x4E56
-#define PCI_CHIP_RAGE128PA 0x5041
-#define PCI_CHIP_RAGE128PB 0x5042
-#define PCI_CHIP_RAGE128PC 0x5043
-#define PCI_CHIP_RAGE128PD 0x5044
-#define PCI_CHIP_RAGE128PE 0x5045
-#define PCI_CHIP_RAGE128PF 0x5046
-#define PCI_CHIP_RAGE128PG 0x5047
-#define PCI_CHIP_RAGE128PH 0x5048
-#define PCI_CHIP_RAGE128PI 0x5049
-#define PCI_CHIP_RAGE128PJ 0x504A
-#define PCI_CHIP_RAGE128PK 0x504B
-#define PCI_CHIP_RAGE128PL 0x504C
-#define PCI_CHIP_RAGE128PM 0x504D
-#define PCI_CHIP_RAGE128PN 0x504E
-#define PCI_CHIP_RAGE128PO 0x504F
-#define PCI_CHIP_RAGE128PP 0x5050
-#define PCI_CHIP_RAGE128PQ 0x5051
-#define PCI_CHIP_RAGE128PR 0x5052
-#define PCI_CHIP_RAGE128PS 0x5053
-#define PCI_CHIP_RAGE128PT 0x5054
-#define PCI_CHIP_RAGE128PU 0x5055
-#define PCI_CHIP_RAGE128PV 0x5056
-#define PCI_CHIP_RAGE128PW 0x5057
-#define PCI_CHIP_RAGE128PX 0x5058
-#define PCI_CHIP_RADEON_QD 0x5144
-#define PCI_CHIP_RADEON_QE 0x5145
-#define PCI_CHIP_RADEON_QF 0x5146
-#define PCI_CHIP_RADEON_QG 0x5147
-#define PCI_CHIP_R200_QH 0x5148
-#define PCI_CHIP_R200_QI 0x5149
-#define PCI_CHIP_R200_QJ 0x514A
-#define PCI_CHIP_R200_QK 0x514B
-#define PCI_CHIP_R200_QL 0x514C
-#define PCI_CHIP_R200_QM 0x514D
-#define PCI_CHIP_R200_QN 0x514E
-#define PCI_CHIP_R200_QO 0x514F
-#define PCI_CHIP_RV200_QW 0x5157
-#define PCI_CHIP_RV200_QX 0x5158
-#define PCI_CHIP_RV100_QY 0x5159
-#define PCI_CHIP_RV100_QZ 0x515A
-#define PCI_CHIP_RN50 0x515E
-#define PCI_CHIP_RAGE128RE 0x5245
-#define PCI_CHIP_RAGE128RF 0x5246
-#define PCI_CHIP_RAGE128RG 0x5247
-#define PCI_CHIP_RAGE128RK 0x524B
-#define PCI_CHIP_RAGE128RL 0x524C
-#define PCI_CHIP_RAGE128SE 0x5345
-#define PCI_CHIP_RAGE128SF 0x5346
-#define PCI_CHIP_RAGE128SG 0x5347
-#define PCI_CHIP_RAGE128SH 0x5348
-#define PCI_CHIP_RAGE128SK 0x534B
-#define PCI_CHIP_RAGE128SL 0x534C
-#define PCI_CHIP_RAGE128SM 0x534D
-#define PCI_CHIP_RAGE128SN 0x534E
-#define PCI_CHIP_RAGE128TF 0x5446
-#define PCI_CHIP_RAGE128TL 0x544C
-#define PCI_CHIP_RAGE128TR 0x5452
-#define PCI_CHIP_RAGE128TS 0x5453
-#define PCI_CHIP_RAGE128TT 0x5454
-#define PCI_CHIP_RAGE128TU 0x5455
-#define PCI_CHIP_RV370_5460 0x5460
-#define PCI_CHIP_RV370_5461 0x5461
-#define PCI_CHIP_RV370_5462 0x5462
-#define PCI_CHIP_RV370_5463 0x5463
-#define PCI_CHIP_RV370_5464 0x5464
-#define PCI_CHIP_RV370_5465 0x5465
-#define PCI_CHIP_RV370_5466 0x5466
-#define PCI_CHIP_RV370_5467 0x5467
-#define PCI_CHIP_R423_UH 0x5548
-#define PCI_CHIP_R423_UI 0x5549
-#define PCI_CHIP_R423_UJ 0x554A
-#define PCI_CHIP_R423_UK 0x554B
-#define PCI_CHIP_R423_UQ 0x5551
-#define PCI_CHIP_R423_UR 0x5552
-#define PCI_CHIP_R423_UT 0x5554
-#define PCI_CHIP_MACH64VT 0x5654
-#define PCI_CHIP_MACH64VU 0x5655
-#define PCI_CHIP_MACH64VV 0x5656
-#define PCI_CHIP_RS300_5834 0x5834
-#define PCI_CHIP_RS300_5835 0x5835
-#define PCI_CHIP_RS300_5836 0x5836
-#define PCI_CHIP_RS300_5837 0x5837
-#define PCI_CHIP_RV370_5B60 0x5B60
-#define PCI_CHIP_RV370_5B61 0x5B61
-#define PCI_CHIP_RV370_5B62 0x5B62
-#define PCI_CHIP_RV370_5B63 0x5B63
-#define PCI_CHIP_RV370_5B64 0x5B64
-#define PCI_CHIP_RV370_5B65 0x5B65
-#define PCI_CHIP_RV370_5B66 0x5B66
-#define PCI_CHIP_RV370_5B67 0x5B67
-#define PCI_CHIP_RV280_5960 0x5960
-#define PCI_CHIP_RV280_5961 0x5961
-#define PCI_CHIP_RV280_5962 0x5962
-#define PCI_CHIP_RV280_5964 0x5964
-#define PCI_CHIP_RV280_5C61 0x5C61
-#define PCI_CHIP_RV280_5C63 0x5C63
-#define PCI_CHIP_R423_5D57 0x5D57
-#define PCI_CHIP_RS350_7834 0x7834
-#define PCI_CHIP_RS350_7835 0x7835
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * ATI Radeon Video card Framebuffer driver.
- *
- * Copyright 2007 Freescale Semiconductor, Inc.
- * Zhang Wei <wei.zhang@freescale.com>
- * Jason Jin <jason.jin@freescale.com>
- *
- * Some codes of this file is partly ported from Linux kernel
- * ATI video framebuffer driver.
- *
- * Now the driver is tested on below ATI chips:
- * 9200
- * X300
- * X700
- */
-
-#include <common.h>
-#include <linux/delay.h>
-
-#include <command.h>
-#include <bios_emul.h>
-#include <env.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-#include <radeon.h>
-#include "ati_ids.h"
-#include "ati_radeon_fb.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DPRINT(x...) printf(x)
-#else
-#define DPRINT(x...) do{}while(0)
-#endif
-
-#define MAX_MAPPED_VRAM (2048*2048*4)
-#define MIN_MAPPED_VRAM (1024*768*1)
-
-#define RADEON_BUFFER_ALIGN 0x00000fff
-#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
- & ~RADEON_BUFFER_ALIGN) - 1)
-#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
- ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
-
-#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
- (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
-#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
- (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
-#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
- ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
-#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
- ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
-
-/*#define PCI_VENDOR_ID_ATI*/
-#define PCI_CHIP_RV280_5960 0x5960
-#define PCI_CHIP_RV280_5961 0x5961
-#define PCI_CHIP_RV280_5962 0x5962
-#define PCI_CHIP_RV280_5964 0x5964
-#define PCI_CHIP_RV280_5C63 0x5C63
-#define PCI_CHIP_RV370_5B60 0x5B60
-#define PCI_CHIP_RV380_5657 0x5657
-#define PCI_CHIP_R420_554d 0x554d
-
-static struct pci_device_id ati_radeon_pci_ids[] = {
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657},
- {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d},
- {0, 0}
-};
-
-static u16 ati_radeon_id_family_table[][2] = {
- {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280},
- {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280},
- {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280},
- {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280},
- {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280},
- {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380},
- {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380},
- {PCI_CHIP_R420_554d, CHIP_FAMILY_R420},
- {0, 0}
-};
-
-u16 get_radeon_id_family(u16 device)
-{
- int i;
- for (i=0; ati_radeon_id_family_table[0][i]; i+=2)
- if (ati_radeon_id_family_table[0][i] == device)
- return ati_radeon_id_family_table[0][i + 1];
- return 0;
-}
-
-struct radeonfb_info *rinfo;
-
-static void radeon_identify_vram(struct radeonfb_info *rinfo)
-{
- u32 tmp;
-
- /* framebuffer size */
- if ((rinfo->family == CHIP_FAMILY_RS100) ||
- (rinfo->family == CHIP_FAMILY_RS200) ||
- (rinfo->family == CHIP_FAMILY_RS300)) {
- u32 tom = INREG(NB_TOM);
- tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
-
- radeon_fifo_wait(6);
- OUTREG(MC_FB_LOCATION, tom);
- OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
- OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
- OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
-
- /* This is supposed to fix the crtc2 noise problem. */
- OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
-
- if ((rinfo->family == CHIP_FAMILY_RS100) ||
- (rinfo->family == CHIP_FAMILY_RS200)) {
- /* This is to workaround the asic bug for RMX, some versions
- of BIOS dosen't have this register initialized correctly.
- */
- OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
- ~CRTC_H_CUTOFF_ACTIVE_EN);
- }
- } else {
- tmp = INREG(CONFIG_MEMSIZE);
- }
-
- /* mem size is bits [28:0], mask off the rest */
- rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
-
- /*
- * Hack to get around some busted production M6's
- * reporting no ram
- */
- if (rinfo->video_ram == 0) {
- switch (rinfo->pdev.device) {
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- rinfo->video_ram = 8192 * 1024;
- break;
- default:
- break;
- }
- }
-
- /*
- * Now try to identify VRAM type
- */
- if ((rinfo->family >= CHIP_FAMILY_R300) ||
- (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
- rinfo->vram_ddr = 1;
- else
- rinfo->vram_ddr = 0;
-
- tmp = INREG(MEM_CNTL);
- if (IS_R300_VARIANT(rinfo)) {
- tmp &= R300_MEM_NUM_CHANNELS_MASK;
- switch (tmp) {
- case 0: rinfo->vram_width = 64; break;
- case 1: rinfo->vram_width = 128; break;
- case 2: rinfo->vram_width = 256; break;
- default: rinfo->vram_width = 128; break;
- }
- } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
- (rinfo->family == CHIP_FAMILY_RS100) ||
- (rinfo->family == CHIP_FAMILY_RS200)){
- if (tmp & RV100_MEM_HALF_MODE)
- rinfo->vram_width = 32;
- else
- rinfo->vram_width = 64;
- } else {
- if (tmp & MEM_NUM_CHANNELS_MASK)
- rinfo->vram_width = 128;
- else
- rinfo->vram_width = 64;
- }
-
- /* This may not be correct, as some cards can have half of channel disabled
- * ToDo: identify these cases
- */
-
- DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n",
- rinfo->video_ram / 1024,
- rinfo->vram_ddr ? "DDR" : "SDRAM",
- rinfo->vram_width);
-
-}
-
-static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
-{
- int i;
-
- radeon_fifo_wait(20);
-
-#if 0
- /* Workaround from XFree */
- if (rinfo->is_mobility) {
- /* A temporal workaround for the occational blanking on certain laptop
- * panels. This appears to related to the PLL divider registers
- * (fail to lock?). It occurs even when all dividers are the same
- * with their old settings. In this case we really don't need to
- * fiddle with PLL registers. By doing this we can avoid the blanking
- * problem with some panels.
- */
- if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
- (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
- (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
- /* We still have to force a switch to selected PPLL div thanks to
- * an XFree86 driver bug which will switch it away in some cases
- * even when using UseFDev */
- OUTREGP(CLOCK_CNTL_INDEX,
- mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
- ~PPLL_DIV_SEL_MASK);
- radeon_pll_errata_after_index(rinfo);
- radeon_pll_errata_after_data(rinfo);
- return;
- }
- }
-#endif
- if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return;
-
- /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
- OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
-
- /* Reset PPLL & enable atomic update */
- OUTPLLP(PPLL_CNTL,
- PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
- ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
-
- /* Switch to selected PPLL divider */
- OUTREGP(CLOCK_CNTL_INDEX,
- mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
- ~PPLL_DIV_SEL_MASK);
-
- /* Set PPLL ref. div */
- if (rinfo->family == CHIP_FAMILY_R300 ||
- rinfo->family == CHIP_FAMILY_RS300 ||
- rinfo->family == CHIP_FAMILY_R350 ||
- rinfo->family == CHIP_FAMILY_RV350) {
- if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
- /* When restoring console mode, use saved PPLL_REF_DIV
- * setting.
- */
- OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
- } else {
- /* R300 uses ref_div_acc field as real ref divider */
- OUTPLLP(PPLL_REF_DIV,
- (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
- ~R300_PPLL_REF_DIV_ACC_MASK);
- }
- } else
- OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
-
- /* Set PPLL divider 3 & post divider*/
- OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
- OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
-
- /* Write update */
- while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
- ;
- OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
-
- /* Wait read update complete */
- /* FIXME: Certain revisions of R300 can't recover here. Not sure of
- the cause yet, but this workaround will mask the problem for now.
- Other chips usually will pass at the very first test, so the
- workaround shouldn't have any effect on them. */
- for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
- ;
-
- OUTPLL(HTOTAL_CNTL, 0);
-
- /* Clear reset & atomic update */
- OUTPLLP(PPLL_CNTL, 0,
- ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
-
- /* We may want some locking ... oh well */
- udelay(5000);
-
- /* Switch back VCLK source to PPLL */
- OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
-}
-
-typedef struct {
- u16 reg;
- u32 val;
-} reg_val;
-
-#if 0 /* unused ? -> scheduled for removal */
-/* these common regs are cleared before mode setting so they do not
- * interfere with anything
- */
-static reg_val common_regs[] = {
- { OVR_CLR, 0 },
- { OVR_WID_LEFT_RIGHT, 0 },
- { OVR_WID_TOP_BOTTOM, 0 },
- { OV0_SCALE_CNTL, 0 },
- { SUBPIC_CNTL, 0 },
- { VIPH_CONTROL, 0 },
- { I2C_CNTL_1, 0 },
- { GEN_INT_CNTL, 0 },
- { CAP0_TRIG_CNTL, 0 },
- { CAP1_TRIG_CNTL, 0 },
-};
-#endif /* 0 */
-
-void radeon_setmode(void)
-{
- struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
-
- mode->crtc_gen_cntl = 0x03000200;
- mode->crtc_ext_cntl = 0x00008048;
- mode->dac_cntl = 0xff002100;
- mode->crtc_h_total_disp = 0x4f0063;
- mode->crtc_h_sync_strt_wid = 0x8c02a2;
- mode->crtc_v_total_disp = 0x01df020c;
- mode->crtc_v_sync_strt_wid = 0x8201ea;
- mode->crtc_pitch = 0x00500050;
-
- OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
- OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
- ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
- OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
- OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
- OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
- OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
- OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
- OUTREG(CRTC_OFFSET, 0);
- OUTREG(CRTC_OFFSET_CNTL, 0);
- OUTREG(CRTC_PITCH, mode->crtc_pitch);
-
- mode->clk_cntl_index = 0x300;
- mode->ppll_ref_div = 0xc;
- mode->ppll_div_3 = 0x00030059;
-
- radeon_write_pll_regs(rinfo, mode);
-}
-
-static void set_pal(void)
-{
- int idx, val = 0;
-
- for (idx = 0; idx < 256; idx++) {
- OUTREG8(PALETTE_INDEX, idx);
- OUTREG(PALETTE_DATA, val);
- val += 0x00010101;
- }
-}
-
-void radeon_setmode_9200(int vesa_idx, int bpp)
-{
- struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
-
- mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
- mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
- mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
- mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
-
- switch (bpp) {
- case 24:
- mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
-#if defined(__BIG_ENDIAN)
- mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
- mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
-#endif
- break;
- case 16:
- mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
-#if defined(__BIG_ENDIAN)
- mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
- mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
-#endif
- break;
- default:
- mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
- mode->surface_cntl = 0x00000000;
- break;
- }
-
- switch (vesa_idx) {
- case RES_MODE_1280x1024:
- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
- mode->ppll_div_3 = 0x00010078;
-#else /* default @ 60 Hz */
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
- mode->ppll_div_3 = 0x00010060;
-#endif
- /*
- * for this mode pitch expands to the same value for 32, 16 and 8 bpp,
- * so we set it here once only.
- */
- mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
- switch (bpp) {
- case 24:
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
- break;
- case 16:
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
- break;
- default: /* 8 bpp */
- mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
- break;
- }
- break;
- case RES_MODE_1024x768:
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
- mode->ppll_div_3 = 0x0002008c;
-#else /* @ 60 Hz */
- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
- mode->ppll_div_3 = 0x00020074;
-#endif
- /* also same pitch value for 32, 16 and 8 bpp */
- mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
- switch (bpp) {
- case 24:
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
- break;
- case 16:
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
- break;
- default: /* 8 bpp */
- mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
- break;
- }
- break;
- case RES_MODE_800x600:
- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
- mode->ppll_div_3 = 0x000300b0;
-#else /* @ 60 Hz */
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
- mode->ppll_div_3 = 0x0003008e;
-#endif
- switch (bpp) {
- case 24:
- mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
- break;
- case 16:
- mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
- break;
- default: /* 8 bpp */
- mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
- mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
- break;
- }
- break;
- default: /* RES_MODE_640x480 */
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
- mode->ppll_div_3 = 0x00030070;
-#else /* @ 60 Hz */
- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
- mode->ppll_div_3 = 0x00030059;
-#endif
- /* also same pitch value for 32, 16 and 8 bpp */
- mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
- switch (bpp) {
- case 24:
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
- break;
- case 16:
- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
- break;
- default: /* 8 bpp */
- mode->crtc_offset_cntl = 0x00000000;
- break;
- }
- break;
- }
-
- OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
- OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
- (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
- OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
- OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
- OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
- OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
- OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
- OUTREG(CRTC_OFFSET, 0);
- OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
- OUTREG(CRTC_PITCH, mode->crtc_pitch);
- OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
-
- mode->clk_cntl_index = 0x300;
- mode->ppll_ref_div = 0xc;
-
- radeon_write_pll_regs(rinfo, mode);
-
- OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
- ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
- OUTREG(SURFACE0_INFO, mode->surf_info[0]);
- OUTREG(SURFACE0_LOWER_BOUND, 0);
- OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
- OUTREG(SURFACE_CNTL, mode->surface_cntl);
-
- if (bpp > 8)
- set_pal();
-
- free(mode);
-}
-
-#include "../bios_emulator/include/biosemu.h"
-
-int radeon_probe(struct radeonfb_info *rinfo)
-{
- pci_dev_t pdev;
- u16 did;
-
- pdev = pci_find_devices(ati_radeon_pci_ids, 0);
-
- if (pdev != -1) {
- pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
- printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
- PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
- (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
-
- strcpy(rinfo->name, "ATI Radeon");
- rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
- rinfo->pdev.device = did;
- rinfo->family = get_radeon_id_family(rinfo->pdev.device);
- pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
- &rinfo->fb_base_bus);
- pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
- &rinfo->mmio_base_bus);
- rinfo->fb_base_bus &= 0xfffff000;
- rinfo->mmio_base_bus &= ~0x04;
-
- rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus,
- PCI_REGION_MEM, 0, MAP_NOCACHE);
- DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n",
- rinfo->mmio_base, rinfo->mmio_base_bus);
- rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
- DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
- /* PostBIOS with x86 emulater */
- if (!BootVideoCardBIOS(pdev, NULL, 0))
- return -1;
-
- /*
- * Check for errata
- * (These will be added in the future for the chipfamily
- * R300, RV200, RS200, RV100, RS100.)
- */
-
- /* Get VRAM size and type */
- radeon_identify_vram(rinfo);
-
- rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
- rinfo->video_ram);
- rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus,
- PCI_REGION_MEM, 0, MAP_NOCACHE);
- DPRINT("Radeon: framebuffer base address 0x%08x, "
- "bus address 0x%08x\n"
- "MMIO base address 0x%08x, bus address 0x%08x, "
- "framebuffer local base 0x%08x.\n ",
- (u32)rinfo->fb_base, rinfo->fb_base_bus,
- (u32)rinfo->mmio_base, rinfo->mmio_base_bus,
- rinfo->fb_local_base);
- return 0;
- }
- return -1;
-}
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
-#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
-#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
-#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
-
-void *video_hw_init(void)
-{
- GraphicDevice *pGD = (GraphicDevice *) & ctfb;
- u32 *vm;
- char *penv;
- unsigned long t1, hsynch, vsynch;
- int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
- struct ctfb_res_modes *res_mode;
- struct ctfb_res_modes var_mode;
-
- rinfo = malloc(sizeof(struct radeonfb_info));
-
- printf("Video: ");
- if(radeon_probe(rinfo)) {
- printf("No radeon video card found!\n");
- return NULL;
- }
-
- tmp = 0;
-
- videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
- /* get video mode via environment */
- penv = env_get("videomode");
- if (penv) {
- /* deceide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int)hextoul(penv, NULL);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
- if (tmp) {
- /* parameter are vesa modes */
- /* search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);
- i = 0;
- }
- res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
- bits_per_pixel = vesa_modes[i].bits_per_pixel;
- vesa_idx = vesa_modes[i].resindex;
- } else {
- res_mode = (struct ctfb_res_modes *) &var_mode;
- bits_per_pixel = video_get_params (res_mode, penv);
- }
-
- /* calculate hsynch and vsynch freq (info only) */
- t1 = (res_mode->left_margin + res_mode->xres +
- res_mode->right_margin + res_mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= res_mode->pixclock;
- t1 /= 1000;
- hsynch = 1000000000L / t1;
- t1 *= (res_mode->upper_margin + res_mode->yres +
- res_mode->lower_margin + res_mode->vsync_len);
- t1 /= 1000;
- vsynch = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
- res_mode->yres, bits_per_pixel, (hsynch / 1000),
- (vsynch / 1000));
- printf ("%s\n", pGD->modeIdent);
- pGD->winSizeX = res_mode->xres;
- pGD->winSizeY = res_mode->yres;
- pGD->plnSizeX = res_mode->xres;
- pGD->plnSizeY = res_mode->yres;
-
- switch (bits_per_pixel) {
- case 24:
- pGD->gdfBytesPP = 4;
- pGD->gdfIndex = GDF_32BIT_X888RGB;
- if (res_mode->xres == 800) {
- pGD->winSizeX = 832;
- pGD->plnSizeX = 832;
- }
- break;
- case 16:
- pGD->gdfBytesPP = 2;
- pGD->gdfIndex = GDF_16BIT_565RGB;
- if (res_mode->xres == 800) {
- pGD->winSizeX = 896;
- pGD->plnSizeX = 896;
- }
- break;
- default:
- if (res_mode->xres == 800) {
- pGD->winSizeX = 1024;
- pGD->plnSizeX = 1024;
- }
- pGD->gdfBytesPP = 1;
- pGD->gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- pGD->pciBase = (unsigned int)rinfo->fb_base;
- pGD->frameAdrs = (unsigned int)rinfo->fb_base;
- pGD->memSize = 64 * 1024 * 1024;
-
- /* Cursor Start Address */
- pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) +
- (unsigned int)rinfo->fb_base;
- if ((pGD->dprBase & 0x0fff) != 0) {
- /* allign it */
- pGD->dprBase &= 0xfffff000;
- pGD->dprBase += 0x00001000;
- }
- DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
- PATTERN_ADR);
- pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */
- pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */
- /* set up Hardware */
-
- /* Clear video memory (only visible screen area) */
- i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
- vm = (unsigned int *) pGD->pciBase;
- while (i--)
- *vm++ = 0;
- /*SetDrawingEngine (bits_per_pixel);*/
-
- if (rinfo->family == CHIP_FAMILY_RV280)
- radeon_setmode_9200(vesa_idx, bits_per_pixel);
- else
- radeon_setmode();
-
- return ((void *) pGD);
-}
-
-void video_set_lut (unsigned int index, /* color number */
- unsigned char r, /* red */
- unsigned char g, /* green */
- unsigned char b /* blue */
- )
-{
- OUTREG(PALETTE_INDEX, index);
- OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b);
-}
+++ /dev/null
-#ifndef __ATI_RADEON_FB_H
-#define __ATI_RADEON_FB_H
-
-/***************************************************************
- * Most of the definitions here are adapted right from XFree86 *
- ***************************************************************/
-
-/*
- * Chip families. Must fit in the low 16 bits of a long word
- */
-enum radeon_family {
- CHIP_FAMILY_UNKNOW,
- CHIP_FAMILY_LEGACY,
- CHIP_FAMILY_RADEON,
- CHIP_FAMILY_RV100,
- CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
- CHIP_FAMILY_RV200,
- CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
- RS250 (IGP 7000) */
- CHIP_FAMILY_R200,
- CHIP_FAMILY_RV250,
- CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
- CHIP_FAMILY_RV280,
- CHIP_FAMILY_R300,
- CHIP_FAMILY_R350,
- CHIP_FAMILY_RV350,
- CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
- CHIP_FAMILY_R420, /* R420/R423/M18 */
- CHIP_FAMILY_LAST,
-};
-
-#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
- ((rinfo)->family == CHIP_FAMILY_RV200) || \
- ((rinfo)->family == CHIP_FAMILY_RS100) || \
- ((rinfo)->family == CHIP_FAMILY_RS200) || \
- ((rinfo)->family == CHIP_FAMILY_RV250) || \
- ((rinfo)->family == CHIP_FAMILY_RV280) || \
- ((rinfo)->family == CHIP_FAMILY_RS300))
-
-#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
- ((rinfo)->family == CHIP_FAMILY_RV350) || \
- ((rinfo)->family == CHIP_FAMILY_R350) || \
- ((rinfo)->family == CHIP_FAMILY_RV380) || \
- ((rinfo)->family == CHIP_FAMILY_R420))
-
-struct radeonfb_info {
- char name[20];
-
- struct pci_device_id pdev;
- u16 family;
-
- u32 fb_base_bus;
- u32 mmio_base_bus;
-
- void *mmio_base;
- void *fb_base;
-
- u32 video_ram;
- u32 mapped_vram;
- int vram_width;
- int vram_ddr;
-
- u32 fb_local_base;
-};
-
-#define INREG8(addr) readb((rinfo->mmio_base)+addr)
-#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
-#define INREG16(addr) readw((rinfo->mmio_base)+addr)
-#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
-#define INREG(addr) readl((rinfo->mmio_base)+addr)
-#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
-
-static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
- u32 val, u32 mask)
-{
- unsigned int tmp;
-
- tmp = INREG(addr);
- tmp &= (mask);
- tmp |= (val);
- OUTREG(addr, tmp);
-}
-
-#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
-
-/*
- * 2D Engine helper routines
- */
-static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
-{
- int i;
-
- /* initiate flush */
- OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
- ~RB2D_DC_FLUSH_ALL);
-
- for (i=0; i < 2000000; i++) {
- if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
- return;
- udelay(1);
- }
- printf("radeonfb: Flush Timeout !\n");
-}
-
-static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
-{
- int i;
-
- for (i=0; i<2000000; i++) {
- if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
- return;
- udelay(1);
- }
- printf("radeonfb: FIFO Timeout !\n");
-}
-
-static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
-{
- int i;
-
- /* ensure FIFO is empty before waiting for idle */
- _radeon_fifo_wait (rinfo, 64);
-
- for (i=0; i<2000000; i++) {
- if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
- radeon_engine_flush (rinfo);
- return;
- }
- udelay(1);
- }
- printf("radeonfb: Idle Timeout !\n");
-}
-
-#define radeon_engine_idle() _radeon_engine_idle(rinfo)
-#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
-#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
-
-/*
- * This structure contains the various registers manipulated by this
- * driver for setting or restoring a mode. It's mostly copied from
- * XFree's RADEONSaveRec structure. A few chip settings might still be
- * tweaked without beeing reflected or saved in these registers though
- */
-struct radeon_regs {
- /* Common registers */
- u32 ovr_clr;
- u32 ovr_wid_left_right;
- u32 ovr_wid_top_bottom;
- u32 ov0_scale_cntl;
- u32 mpp_tb_config;
- u32 mpp_gp_config;
- u32 subpic_cntl;
- u32 viph_control;
- u32 i2c_cntl_1;
- u32 gen_int_cntl;
- u32 cap0_trig_cntl;
- u32 cap1_trig_cntl;
- u32 bus_cntl;
- u32 surface_cntl;
- u32 bios_5_scratch;
-
- /* Other registers to save for VT switches or driver load/unload */
- u32 dp_datatype;
- u32 rbbm_soft_reset;
- u32 clock_cntl_index;
- u32 amcgpio_en_reg;
- u32 amcgpio_mask;
-
- /* Surface/tiling registers */
- u32 surf_lower_bound[8];
- u32 surf_upper_bound[8];
- u32 surf_info[8];
-
- /* CRTC registers */
- u32 crtc_gen_cntl;
- u32 crtc_ext_cntl;
- u32 dac_cntl;
- u32 crtc_h_total_disp;
- u32 crtc_h_sync_strt_wid;
- u32 crtc_v_total_disp;
- u32 crtc_v_sync_strt_wid;
- u32 crtc_offset;
- u32 crtc_offset_cntl;
- u32 crtc_pitch;
- u32 disp_merge_cntl;
- u32 grph_buffer_cntl;
- u32 crtc_more_cntl;
-
- /* CRTC2 registers */
- u32 crtc2_gen_cntl;
- u32 dac2_cntl;
- u32 disp_output_cntl;
- u32 disp_hw_debug;
- u32 disp2_merge_cntl;
- u32 grph2_buffer_cntl;
- u32 crtc2_h_total_disp;
- u32 crtc2_h_sync_strt_wid;
- u32 crtc2_v_total_disp;
- u32 crtc2_v_sync_strt_wid;
- u32 crtc2_offset;
- u32 crtc2_offset_cntl;
- u32 crtc2_pitch;
-
- /* Flat panel regs */
- u32 fp_crtc_h_total_disp;
- u32 fp_crtc_v_total_disp;
- u32 fp_gen_cntl;
- u32 fp2_gen_cntl;
- u32 fp_h_sync_strt_wid;
- u32 fp2_h_sync_strt_wid;
- u32 fp_horz_stretch;
- u32 fp_panel_cntl;
- u32 fp_v_sync_strt_wid;
- u32 fp2_v_sync_strt_wid;
- u32 fp_vert_stretch;
- u32 lvds_gen_cntl;
- u32 lvds_pll_cntl;
- u32 tmds_crc;
- u32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- u32 dot_clock_freq;
- int feedback_div;
- int post_div;
-
- /* PLL registers */
- u32 ppll_div_3;
- u32 ppll_ref_div;
- u32 vclk_ecp_cntl;
- u32 clk_cntl_index;
-
- /* Computed values for PLL2 */
- u32 dot_clock_freq_2;
- int feedback_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- u32 p2pll_ref_div;
- u32 p2pll_div_0;
- u32 htotal_cntl2;
-
- /* Palette */
- int palette_valid;
-};
-
-static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
-{
- u32 data;
-
- OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
- /* radeon_pll_errata_after_index(rinfo); */
- data = INREG(CLOCK_CNTL_DATA);
- /* radeon_pll_errata_after_data(rinfo); */
- return data;
-}
-
-static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
- u32 val)
-{
-
- OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
- /* radeon_pll_errata_after_index(rinfo); */
- OUTREG(CLOCK_CNTL_DATA, val);
- /* radeon_pll_errata_after_data(rinfo); */
-}
-
-static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
- u32 val, u32 mask)
-{
- unsigned int tmp;
-
- tmp = __INPLL(rinfo, index);
- tmp &= (mask);
- tmp |= (val);
- __OUTPLL(rinfo, index, tmp);
-}
-
-#define INPLL(addr) __INPLL(rinfo, addr)
-#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
-#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
-
-#endif
#ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED
#define VCXK_BWS(x, data) vcxk_bws[x] = data;
- #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask;
- #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask;
+ #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask;
+ #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask;
#define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data;
#else
u_char double_bws[16384];
#endif
#define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2]
-#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2]
+#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2]
#define VC2K_Bright vcxk_bws[0x8000]
#define VC8K_BrightH vcxk_bws[0xC000]
#define VC8K_BrightL vcxk_bws[0xC001]
* set the display brightness
* PARAMETER
* side 1 set front side brightness
- * 2 set back side brightness
+ * 2 set back side brightness
* 3 set brightness for both sides
* brightness 0..1000
***
VC4K16_Bright1 = brightness + 23;
if ((side == 0) || (side & 0x2))
VC4K16_Bright2 = brightness + 23;
- } else {
+ } else {
VC2K_Bright = (brightness >> 4) + 2;
VC8K_BrightH = (brightness + 23) >> 8;
VC8K_BrightL = (brightness + 23) & 0xFF;
#include <fdtdec.h>
#include <gzip.h>
#include <log.h>
-#include <version.h>
+#include <version_string.h>
#include <malloc.h>
#include <video.h>
#include <asm/global_data.h>
+#include <dm/ofnode.h>
#include <linux/compiler.h>
-#if defined(CONFIG_VIDEO_MXS)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#endif
-
-/*
- * Defines for the i.MX31 driver (mx3fb.c)
- */
-#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#endif
-
/*
* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
*/
* Console device
*/
-#include <version.h>
#include <linux/types.h>
#include <stdio_dev.h>
#include <video_font.h>
#if defined(CONFIG_VGA_AS_SINGLE_DEVICE)
have_keyboard = false;
#elif defined(CONFIG_OF_CONTROL)
- have_keyboard = !fdtdec_get_config_bool(gd->fdt_blob,
- "u-boot,no-keyboard");
+ have_keyboard = !ofnode_conf_read_bool("u-boot,no-keyboard");
#else
have_keyboard = true;
#endif
dt->rx_timeout = fdtdec_get_int(blob, node,
"samsung,dsim-config-rx-timeout", 0);
- lcd_dt->name = fdtdec_get_config_string(blob,
- "samsung,dsim-device-name");
+ lcd_dt->name = fdt_getprop(blob, node, "samsung,dsim-device-name",
+ NULL);
lcd_dt->id = fdtdec_get_int(blob, node,
"samsung,dsim-device-id", 0);
};
int i, cs, clk, mosi, ret = 0;
- cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
- clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
- mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
+ cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
+ clk = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
+ mosi = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
if (cs == -1 || clk == -1 || mosi == 1) {
printf("Error tx18d42vm spi gpio config is invalid\n");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- * Copyright (C) 2011
- * HALE electronic GmbH, <helmut.raiger@hale.at>
- */
-#include <common.h>
-#include <env.h>
-#include <log.h>
-#include <malloc.h>
-#include <video_fb.h>
-#include <linux/delay.h>
-
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-
-#include "videomodes.h"
-
-/* this might need panel specific set-up as-well */
-#define IF_CONF 0
-
-/* -------------- controller specific stuff -------------- */
-
-/* IPU DMA Controller channel definitions. */
-enum ipu_channel {
- IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
- IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
- IDMAC_ADC_0 = 1,
- IDMAC_IC_2 = 2,
- IDMAC_ADC_1 = 2,
- IDMAC_IC_3 = 3,
- IDMAC_IC_4 = 4,
- IDMAC_IC_5 = 5,
- IDMAC_IC_6 = 6,
- IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
- IDMAC_IC_8 = 8,
- IDMAC_IC_9 = 9,
- IDMAC_IC_10 = 10,
- IDMAC_IC_11 = 11,
- IDMAC_IC_12 = 12,
- IDMAC_IC_13 = 13,
- IDMAC_SDC_0 = 14, /* Background synchronous display data */
- IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
- IDMAC_SDC_2 = 16,
- IDMAC_SDC_3 = 17,
- IDMAC_ADC_2 = 18,
- IDMAC_ADC_3 = 19,
- IDMAC_ADC_4 = 20,
- IDMAC_ADC_5 = 21,
- IDMAC_ADC_6 = 22,
- IDMAC_ADC_7 = 23,
- IDMAC_PF_0 = 24,
- IDMAC_PF_1 = 25,
- IDMAC_PF_2 = 26,
- IDMAC_PF_3 = 27,
- IDMAC_PF_4 = 28,
- IDMAC_PF_5 = 29,
- IDMAC_PF_6 = 30,
- IDMAC_PF_7 = 31,
-};
-
-/* More formats can be copied from the Linux driver if needed */
-enum pixel_fmt {
- /* 2 bytes */
- IPU_PIX_FMT_RGB565,
- IPU_PIX_FMT_RGB666,
- IPU_PIX_FMT_BGR666,
- /* 3 bytes */
- IPU_PIX_FMT_RGB24,
-};
-
-struct pixel_fmt_cfg {
- u32 b0;
- u32 b1;
- u32 b2;
- u32 acc;
-};
-
-static struct pixel_fmt_cfg fmt_cfg[] = {
- [IPU_PIX_FMT_RGB24] = {
- 0x1600AAAA, 0x00E05555, 0x00070000, 3,
- },
- [IPU_PIX_FMT_RGB666] = {
- 0x0005000F, 0x000B000F, 0x0011000F, 1,
- },
- [IPU_PIX_FMT_BGR666] = {
- 0x0011000F, 0x000B000F, 0x0005000F, 1,
- },
- [IPU_PIX_FMT_RGB565] = {
- 0x0004003F, 0x000A000F, 0x000F003F, 1,
- }
-};
-
-enum ipu_panel {
- IPU_PANEL_SHARP_TFT,
- IPU_PANEL_TFT,
-};
-
-/* IPU Common registers */
-/* IPU_CONF and its bits already defined in imx-regs.h */
-#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
-#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
-#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
-#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
-#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
-#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
-#define IPU_TASKS_STAT (0x1C + IPU_BASE)
-#define IPU_IMA_ADDR (0x20 + IPU_BASE)
-#define IPU_IMA_DATA (0x24 + IPU_BASE)
-#define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
-#define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
-#define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
-#define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
-#define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
-#define IPU_INT_STAT_1 (0x3C + IPU_BASE)
-#define IPU_INT_STAT_2 (0x40 + IPU_BASE)
-#define IPU_INT_STAT_3 (0x44 + IPU_BASE)
-#define IPU_INT_STAT_4 (0x48 + IPU_BASE)
-#define IPU_INT_STAT_5 (0x4C + IPU_BASE)
-#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
-#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
-#define IPU_BRK_STAT (0x58 + IPU_BASE)
-#define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
-
-/* Image Converter Registers */
-#define IC_CONF (0x88 + IPU_BASE)
-#define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
-#define IC_PRP_VF_RSC (0x90 + IPU_BASE)
-#define IC_PP_RSC (0x94 + IPU_BASE)
-#define IC_CMBP_1 (0x98 + IPU_BASE)
-#define IC_CMBP_2 (0x9C + IPU_BASE)
-#define PF_CONF (0xA0 + IPU_BASE)
-#define IDMAC_CONF (0xA4 + IPU_BASE)
-#define IDMAC_CHA_EN (0xA8 + IPU_BASE)
-#define IDMAC_CHA_PRI (0xAC + IPU_BASE)
-#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
-
-/* Image Converter Register bits */
-#define IC_CONF_PRPENC_EN 0x00000001
-#define IC_CONF_PRPENC_CSC1 0x00000002
-#define IC_CONF_PRPENC_ROT_EN 0x00000004
-#define IC_CONF_PRPVF_EN 0x00000100
-#define IC_CONF_PRPVF_CSC1 0x00000200
-#define IC_CONF_PRPVF_CSC2 0x00000400
-#define IC_CONF_PRPVF_CMB 0x00000800
-#define IC_CONF_PRPVF_ROT_EN 0x00001000
-#define IC_CONF_PP_EN 0x00010000
-#define IC_CONF_PP_CSC1 0x00020000
-#define IC_CONF_PP_CSC2 0x00040000
-#define IC_CONF_PP_CMB 0x00080000
-#define IC_CONF_PP_ROT_EN 0x00100000
-#define IC_CONF_IC_GLB_LOC_A 0x10000000
-#define IC_CONF_KEY_COLOR_EN 0x20000000
-#define IC_CONF_RWS_EN 0x40000000
-#define IC_CONF_CSI_MEM_WR_EN 0x80000000
-
-/* SDC Registers */
-#define SDC_COM_CONF (0xB4 + IPU_BASE)
-#define SDC_GW_CTRL (0xB8 + IPU_BASE)
-#define SDC_FG_POS (0xBC + IPU_BASE)
-#define SDC_BG_POS (0xC0 + IPU_BASE)
-#define SDC_CUR_POS (0xC4 + IPU_BASE)
-#define SDC_PWM_CTRL (0xC8 + IPU_BASE)
-#define SDC_CUR_MAP (0xCC + IPU_BASE)
-#define SDC_HOR_CONF (0xD0 + IPU_BASE)
-#define SDC_VER_CONF (0xD4 + IPU_BASE)
-#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
-#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
-
-/* Register bits */
-#define SDC_COM_TFT_COLOR 0x00000001UL
-#define SDC_COM_FG_EN 0x00000010UL
-#define SDC_COM_GWSEL 0x00000020UL
-#define SDC_COM_GLB_A 0x00000040UL
-#define SDC_COM_KEY_COLOR_G 0x00000080UL
-#define SDC_COM_BG_EN 0x00000200UL
-#define SDC_COM_SHARP 0x00001000UL
-
-#define SDC_V_SYNC_WIDTH_L 0x00000001UL
-
-/* Display Interface registers */
-#define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
-#define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
-#define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
-#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
-#define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
-#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
-#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
-#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
-#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
-#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
-#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
-#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
-#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
-#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
-#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
-#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
-#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
-#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
-#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
-#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
-#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
-#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
-#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
-#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
-#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
-#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
-#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
-#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
-#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
-#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
-#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
-#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
-#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
-#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
-#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
-#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
-
-/* DI_DISP_SIG_POL bits */
-#define DI_D3_VSYNC_POL (1 << 28)
-#define DI_D3_HSYNC_POL (1 << 27)
-#define DI_D3_DRDY_SHARP_POL (1 << 26)
-#define DI_D3_CLK_POL (1 << 25)
-#define DI_D3_DATA_POL (1 << 24)
-
-/* DI_DISP_IF_CONF bits */
-#define DI_D3_CLK_IDLE (1 << 26)
-#define DI_D3_CLK_SEL (1 << 25)
-#define DI_D3_DATAMSK (1 << 24)
-
-#define IOMUX_PADNUM_MASK 0x1ff
-#define IOMUX_GPIONUM_SHIFT 9
-#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
-
-#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
-
-#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
-
-struct chan_param_mem_planar {
- /* Word 0 */
- u32 xv:10;
- u32 yv:10;
- u32 xb:12;
-
- u32 yb:12;
- u32 res1:2;
- u32 nsb:1;
- u32 lnpb:6;
- u32 ubo_l:11;
-
- u32 ubo_h:15;
- u32 vbo_l:17;
-
- u32 vbo_h:9;
- u32 res2:3;
- u32 fw:12;
- u32 fh_l:8;
-
- u32 fh_h:4;
- u32 res3:28;
-
- /* Word 1 */
- u32 eba0;
-
- u32 eba1;
-
- u32 bpp:3;
- u32 sl:14;
- u32 pfs:3;
- u32 bam:3;
- u32 res4:2;
- u32 npb:6;
- u32 res5:1;
-
- u32 sat:2;
- u32 res6:30;
-} __attribute__ ((packed));
-
-struct chan_param_mem_interleaved {
- /* Word 0 */
- u32 xv:10;
- u32 yv:10;
- u32 xb:12;
-
- u32 yb:12;
- u32 sce:1;
- u32 res1:1;
- u32 nsb:1;
- u32 lnpb:6;
- u32 sx:10;
- u32 sy_l:1;
-
- u32 sy_h:9;
- u32 ns:10;
- u32 sm:10;
- u32 sdx_l:3;
-
- u32 sdx_h:2;
- u32 sdy:5;
- u32 sdrx:1;
- u32 sdry:1;
- u32 sdr1:1;
- u32 res2:2;
- u32 fw:12;
- u32 fh_l:8;
-
- u32 fh_h:4;
- u32 res3:28;
-
- /* Word 1 */
- u32 eba0;
-
- u32 eba1;
-
- u32 bpp:3;
- u32 sl:14;
- u32 pfs:3;
- u32 bam:3;
- u32 res4:2;
- u32 npb:6;
- u32 res5:1;
-
- u32 sat:2;
- u32 scc:1;
- u32 ofs0:5;
- u32 ofs1:5;
- u32 ofs2:5;
- u32 ofs3:5;
- u32 wid0:3;
- u32 wid1:3;
- u32 wid2:3;
-
- u32 wid3:3;
- u32 dec_sel:1;
- u32 res6:28;
-} __attribute__ ((packed));
-
-union chan_param_mem {
- struct chan_param_mem_planar pp;
- struct chan_param_mem_interleaved ip;
-};
-
-/* graphics setup */
-static GraphicDevice panel;
-static struct ctfb_res_modes *mode;
-static struct ctfb_res_modes var_mode;
-
-/*
- * sdc_init_panel() - initialize a synchronous LCD panel.
- * @width: width of panel in pixels.
- * @height: height of panel in pixels.
- * @di_setup: pixel format of the frame buffer
- * @di_panel: either SHARP or normal TFT
- * @return: 0 on success or negative error code on failure.
- */
-static int sdc_init_panel(u16 width, u16 height,
- enum pixel_fmt di_setup, enum ipu_panel di_panel)
-{
- u32 reg, div;
- uint32_t old_conf;
- int clock;
-
- debug("%s(width=%d, height=%d)\n", __func__, width, height);
-
- /* Init clocking, the IPU receives its clock from the hsp divder */
- clock = mxc_get_clock(MXC_IPU_CLK);
- if (clock < 0)
- return -EACCES;
-
- /* Init panel size and blanking periods */
- reg = width + mode->left_margin + mode->right_margin - 1;
- if (reg > 1023) {
- printf("mx3fb: Display width too large, coerced to 1023!");
- reg = 1023;
- }
- reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
- writel(reg, SDC_HOR_CONF);
-
- reg = height + mode->upper_margin + mode->lower_margin - 1;
- if (reg > 1023) {
- printf("mx3fb: Display height too large, coerced to 1023!");
- reg = 1023;
- }
- reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
- writel(reg, SDC_VER_CONF);
-
- switch (di_panel) {
- case IPU_PANEL_SHARP_TFT:
- writel(0x00FD0102L, SDC_SHARP_CONF_1);
- writel(0x00F500F4L, SDC_SHARP_CONF_2);
- writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
- /* TODO: probably IF_CONF must be adapted (see below)! */
- break;
- case IPU_PANEL_TFT:
- writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * Calculate divider: The fractional part is 4 bits so simply
- * multiple by 2^4 to get it.
- *
- * Opposed to the kernel driver mode->pixclock is the time of one
- * pixel in pico seconds, so:
- * pixel_clk = 1e12 / mode->pixclock
- * div = ipu_clk * 16 / pixel_clk
- * leads to:
- * div = ipu_clk * 16 / (1e12 / mode->pixclock)
- * or:
- * div = ipu_clk * 16 * mode->pixclock / 1e12
- *
- * To avoid integer overflows this is split into 2 shifts and
- * one divide with sufficient accuracy:
- * 16*1024*128*476837 = 0.9999996682e12
- */
- div = ((clock/1024) * (mode->pixclock/128)) / 476837;
- debug("hsp_clk is %d, div=%d\n", clock, div);
- /* coerce to not less than 4.0, not more than 255.9375 */
- if (div < 0x40)
- div = 0x40;
- else if (div > 0xFFF)
- div = 0xFFF;
- /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
- * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
- * based on timing debug DISP3_IF_CLK_UP_WR is 0
- */
- writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
-
- /* DI settings for display 3: clock idle (bit 26) during vsync */
- old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
- writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
-
- /* only set display 3 polarity bits */
- old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
- writel(old_conf | mode->sync, DI_DISP_SIG_POL);
-
- writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
- writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
- writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
- writel(readl(DI_DISP_ACC_CC) |
- ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
-
- debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
- debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
- debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
- debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
- debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
-
- return 0;
-}
-
-static void ipu_ch_param_set_size(union chan_param_mem *params,
- uint pixelfmt, uint16_t width,
- uint16_t height, uint16_t stride)
-{
- debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
- __func__, pixelfmt, width, height, stride);
-
- params->pp.fw = width - 1;
- params->pp.fh_l = height - 1;
- params->pp.fh_h = (height - 1) >> 8;
- params->pp.sl = stride - 1;
-
- /* See above, for further formats see the Linux driver */
- switch (pixelfmt) {
- case GDF_16BIT_565RGB:
- params->ip.bpp = 2;
- params->ip.pfs = 4;
- params->ip.npb = 7;
- params->ip.sat = 2; /* SAT = 32-bit access */
- params->ip.ofs0 = 0; /* Red bit offset */
- params->ip.ofs1 = 5; /* Green bit offset */
- params->ip.ofs2 = 11; /* Blue bit offset */
- params->ip.ofs3 = 16; /* Alpha bit offset */
- params->ip.wid0 = 4; /* Red bit width - 1 */
- params->ip.wid1 = 5; /* Green bit width - 1 */
- params->ip.wid2 = 4; /* Blue bit width - 1 */
- break;
- case GDF_32BIT_X888RGB:
- params->ip.bpp = 1; /* 24 BPP & RGB PFS */
- params->ip.pfs = 4;
- params->ip.npb = 7;
- params->ip.sat = 2; /* SAT = 32-bit access */
- params->ip.ofs0 = 16; /* Red bit offset */
- params->ip.ofs1 = 8; /* Green bit offset */
- params->ip.ofs2 = 0; /* Blue bit offset */
- params->ip.ofs3 = 24; /* Alpha bit offset */
- params->ip.wid0 = 7; /* Red bit width - 1 */
- params->ip.wid1 = 7; /* Green bit width - 1 */
- params->ip.wid2 = 7; /* Blue bit width - 1 */
- break;
- default:
- printf("mx3fb: Pixel format not supported!\n");
- break;
- }
-
- params->pp.nsb = 1;
-}
-
-static void ipu_ch_param_set_buffer(union chan_param_mem *params,
- void *buf0, void *buf1)
-{
- params->pp.eba0 = (u32)buf0;
- params->pp.eba1 = (u32)buf1;
-}
-
-static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
- uint32_t num_words)
-{
- for (; num_words > 0; num_words--) {
- writel(addr, IPU_IMA_ADDR);
- writel(*data++, IPU_IMA_DATA);
- addr++;
- if ((addr & 0x7) == 5) {
- addr &= ~0x7; /* set to word 0 */
- addr += 8; /* increment to next row */
- }
- }
-}
-
-static uint32_t dma_param_addr(enum ipu_channel channel)
-{
- /* Channel Parameter Memory */
- return 0x10000 | (channel << 4);
-}
-
-static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
-{
- union chan_param_mem params = {};
- uint32_t reg;
- uint32_t stride_bytes;
-
- stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
-
- debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
-
- /* Build parameter memory data for DMA channel */
- ipu_ch_param_set_size(¶ms, panel.gdfIndex,
- panel.plnSizeX, panel.plnSizeY, stride_bytes);
- ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
- params.pp.bam = 0;
- /* Some channels (rotation) have restriction on burst length */
-
- switch (channel) {
- case IDMAC_SDC_0:
- /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
- params.pp.npb = 16 - 1;
- break;
- default:
- break;
- }
-
- ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
-
- /* Disable double-buffering */
- reg = readl(IPU_CHA_DB_MODE_SEL);
- reg &= ~(1UL << channel);
- writel(reg, IPU_CHA_DB_MODE_SEL);
-}
-
-static void ipu_channel_set_priority(enum ipu_channel channel,
- int prio)
-{
- u32 reg = readl(IDMAC_CHA_PRI);
-
- if (prio)
- reg |= 1UL << channel;
- else
- reg &= ~(1UL << channel);
-
- writel(reg, IDMAC_CHA_PRI);
-}
-
-/*
- * ipu_enable_channel() - enable an IPU channel.
- * @channel: channel ID.
- * @return: 0 on success or negative error code on failure.
- */
-static int ipu_enable_channel(enum ipu_channel channel)
-{
- uint32_t reg;
-
- /* Reset to buffer 0 */
- writel(1UL << channel, IPU_CHA_CUR_BUF);
-
- switch (channel) {
- case IDMAC_SDC_0:
- ipu_channel_set_priority(channel, 1);
- break;
- default:
- break;
- }
-
- reg = readl(IDMAC_CHA_EN);
- writel(reg | (1UL << channel), IDMAC_CHA_EN);
-
- return 0;
-}
-
-static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
-{
- uint32_t reg;
-
- reg = readl(IPU_CHA_BUF0_RDY);
- if (reg & (1UL << channel))
- return -EACCES;
-
- /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
- writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
- writel((u32)buf, IPU_IMA_DATA);
-
- return 0;
-}
-
-static int idmac_tx_submit(enum ipu_channel channel, void *buf)
-{
- int ret;
-
- ipu_init_channel_buffer(channel, buf);
-
-
- /* ipu_idmac.c::ipu_submit_channel_buffers() */
- ret = ipu_update_channel_buffer(channel, buf);
- if (ret < 0)
- return ret;
-
- /* ipu_idmac.c::ipu_select_buffer() */
- /* Mark buffer 0 as ready. */
- writel(1UL << channel, IPU_CHA_BUF0_RDY);
-
-
- ret = ipu_enable_channel(channel);
- return ret;
-}
-
-static void sdc_enable_channel(void *fbmem)
-{
- int ret;
- u32 reg;
-
- ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
-
- /* mx3fb.c::sdc_fb_init() */
- if (ret >= 0) {
- reg = readl(SDC_COM_CONF);
- writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
- }
-
- /*
- * Attention! Without this msleep the channel keeps generating
- * interrupts. Next sdc_set_brightness() is going to be called
- * from mx3fb_blank().
- */
- udelay(2000);
-}
-
-/*
- * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
- * @return: 0 on success or negative error code on failure.
- * TODO: currently only 666 and TFT as DI setup supported
- */
-static int mx3fb_set_par(void)
-{
- int ret;
-
- ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
- IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
- if (ret < 0)
- return ret;
-
- writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
-
- return 0;
-}
-
-static void ll_disp3_enable(void *base)
-{
- u32 reg;
-
- debug("%s(base=0x%x)\n", __func__, (u32) base);
- /* pcm037.c::mxc_board_init() */
-
- /* Display Interface #3 */
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
-
-
- /* ipu_idmac.c::ipu_probe() */
-
- /* Start the clock */
- __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
-
-
- /* ipu_idmac.c::ipu_idmac_init() */
-
- /* Service request counter to maximum - shouldn't be needed */
- writel(0x00000070, IDMAC_CONF);
-
-
- /* ipu_idmac.c::ipu_init_channel() */
-
- /* Enable IPU sub modules */
- reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
- writel(reg, IPU_CONF);
-
-
- /* mx3fb.c::init_fb_chan() */
-
- /* set Display Interface clock period */
- writel(0x00100010L, DI_HSP_CLK_PER);
- /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
-
-
- /* mx3fb.c::sdc_set_brightness() */
-
- /* This might be board-specific */
- writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
-
-
- /* mx3fb.c::sdc_set_global_alpha() */
-
- /* Use global - not per-pixel - Alpha-blending */
- reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
- writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
-
- reg = readl(SDC_COM_CONF);
- writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
-
-
- /* mx3fb.c::sdc_set_color_key() */
-
- /* Disable colour-keying for background */
- reg = readl(SDC_COM_CONF) &
- ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
- writel(reg, SDC_COM_CONF);
-
-
- mx3fb_set_par();
-
- sdc_enable_channel(base);
-
- /*
- * Linux driver calls sdc_set_brightness() here again,
- * once is enough for us
- */
- debug("%s() done\n", __func__);
-}
-
-/* ------------------------ public part ------------------- */
-ulong calc_fbsize(void)
-{
- return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
-}
-
-/*
- * The current implementation is only tested for GDF_16BIT_565RGB!
- * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
- * because the lcd code seemed loaded with color table stuff, that
- * does not relate to most modern TFTs. cfb_console.c looks more
- * straight forward.
- * This is the environment setting for the original setup
- * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
- * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
- * "videomode=unknown"
- *
- * Settings for VBEST VGG322403 display:
- * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
- * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
- *
- * Settings for COM57H5M10XRC display:
- * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
- * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
- */
-void *video_hw_init(void)
-{
- char *penv;
- u32 memsize;
- unsigned long t1, hsynch, vsynch;
- int bits_per_pixel, i, tmp, videomode;
-
- tmp = 0;
-
- puts("Video: ");
-
- videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
- /* get video mode via environment */
- penv = env_get("videomode");
- if (penv) {
- /* decide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int)hextoul(penv, NULL);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
- if (tmp) {
- /* parameter are vesa modes */
- /* search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf("No VESA Mode found, switching to mode 0x%x ",
- CONFIG_SYS_DEFAULT_VIDEO_MODE);
- i = 0;
- }
- mode = (struct ctfb_res_modes *)
- &res_mode_init[vesa_modes[i].resindex];
- bits_per_pixel = vesa_modes[i].bits_per_pixel;
- } else {
- mode = (struct ctfb_res_modes *) &var_mode;
- bits_per_pixel = video_get_params(mode, penv);
- }
-
- /* calculate hsynch and vsynch freq (info only) */
- t1 = (mode->left_margin + mode->xres +
- mode->right_margin + mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= mode->pixclock;
- t1 /= 1000;
- hsynch = 1000000000L / t1;
- t1 *= (mode->upper_margin + mode->yres +
- mode->lower_margin + mode->vsync_len);
- t1 /= 1000;
- vsynch = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
- mode->xres, mode->yres,
- bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
- printf("%s\n", panel.modeIdent);
- panel.winSizeX = mode->xres;
- panel.winSizeY = mode->yres;
- panel.plnSizeX = mode->xres;
- panel.plnSizeY = mode->yres;
-
- switch (bits_per_pixel) {
- case 24:
- panel.gdfBytesPP = 4;
- panel.gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- panel.gdfBytesPP = 1;
- panel.gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- /* set up Hardware */
- memsize = calc_fbsize();
-
- debug("%s() allocating %d bytes\n", __func__, memsize);
-
- /* fill in missing Graphic device struct */
- panel.frameAdrs = (u32) malloc(memsize);
- if (panel.frameAdrs == 0) {
- printf("%s() malloc(%d) failed\n", __func__, memsize);
- return 0;
- }
- panel.memSize = memsize;
-
- ll_disp3_enable((void *) panel.frameAdrs);
- memset((void *) panel.frameAdrs, 0, memsize);
-
- debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
- __func__, panel.frameAdrs, memsize);
-
- return (void *) &panel;
-}
* Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
* setenv videomode
* video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
- * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
+ * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
/*----------------------------------------------------------------------*/
-#ifdef CONFIG_ACX517AKN
-
-# define LCD_BPP LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0 0x003008f9
-# define REG_LCCR3 0x03700006
-
-vidinfo_t panel_info = {
- .vl_col = 320,
- .vl_row = 320,
- .vl_width = 320,
- .vl_height = 320,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_oep = CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_HIGH,
- .vl_bpix = LCD_BPP,
- .vl_lbw = 0,
- .vl_splt = 1,
- .vl_clor = 1,
- .vl_tft = 1,
- .vl_hpw = 0x04,
- .vl_blw = 0x1c,
- .vl_elw = 0x08,
- .vl_vpw = 0x01,
- .vl_bfw = 0x07,
- .vl_efw = 0x08,
-};
-#endif /* CONFIG_ACX517AKN */
-
-#ifdef CONFIG_ACX544AKN
-
-# define LCD_BPP LCD_COLOR16
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0 0x003008f9
-# define REG_LCCR3 0x04700007 /* 16bpp */
-
-vidinfo_t panel_info = {
- .vl_col = 320,
- .vl_row = 320,
- .vl_width = 320,
- .vl_height = 320,
- .vl_clkp = CONFIG_SYS_LOW,
- .vl_oep = CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = LCD_BPP,
- .vl_lbw = 0,
- .vl_splt = 0,
- .vl_clor = 1,
- .vl_tft = 1,
- .vl_hpw = 0x05,
- .vl_blw = 0x13,
- .vl_elw = 0x08,
- .vl_vpw = 0x02,
- .vl_bfw = 0x07,
- .vl_efw = 0x05,
-};
-#endif /* CONFIG_ACX544AKN */
-
-/*----------------------------------------------------------------------*/
-
#ifdef CONFIG_LQ038J7DH53
# define LCD_BPP LCD_COLOR8
.vl_bfw = 0x04,
.vl_efw = 0x01,
};
-#endif /* CONFIG_ACX517AKN */
+#endif /* CONFIG_LQ038J7DH53 */
/*----------------------------------------------------------------------*/
if (strcmp(format, "r5g6b5") == 0) {
uc_priv->bpix = VIDEO_BPP16;
- } else if (strcmp(format, "a8b8g8r8") == 0) {
+ } else if (strcmp(format, "a8b8g8r8") == 0 ||
+ strcmp(format, "x8b8g8r8") == 0) {
uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X8B8G8R8;
+ } else if (strcmp(format, "a8r8g8b8") == 0 ||
+ strcmp(format, "x8r8g8b8") == 0) {
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X8R8G8B8;
+ } else if (strcmp(format, "a2r10g10b10") == 0 ||
+ strcmp(format, "x2r10g10b10") == 0) {
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X2R10G10B10;
} else {
printf("%s: invalid format: %s\n", __func__, format);
return -EINVAL;
// It's inefficient; you might want to c&p it and optimize it.
-
//////////////////////////////////////////////////////////////////////////////
//
// NEW TEXTURE BAKING API
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/lcdc.h>
#include <asm/arch/pwm.h>
#include <asm/arch/tve.h>
static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
{
struct ssd2828_config cfg = {
- .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
- .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
- .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
- .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
- .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
+ .csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
+ .sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
+ .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
+ .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
+ .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
.ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
.ssd2828_color_depth = 24,
#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
}
#endif /* CONFIG_VIDEO_LCD_SSD2828 */
+#ifdef CONFIG_VIDEO_LCD_PANEL_I2C
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display)
+{
+ const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME;
+ struct udevice *i2c_bus;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus);
+ if (ret)
+ return;
+
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
+ /*
+ * The anx9804 needs 1.8V from eldo3, we do this here
+ * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
+ * to avoid turning this on when using hdmi output.
+ */
+ axp_set_eldo(3, 1800);
+ anx9804_init(i2c_bus, 4,
+ ANX9804_DATA_RATE_1620M,
+ sunxi_display->depth);
+ }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
+ struct udevice *chip;
+
+ ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip);
+ if (ret)
+ return;
+
+ dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */
+ }
+}
+#else
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {}
+#endif
+
static void sunxi_engines_init(void)
{
sunxi_composer_init();
break;
case sunxi_monitor_lcd:
sunxi_lcdc_panel_enable();
- if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
- /*
- * The anx9804 needs 1.8V from eldo3, we do this here
- * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
- * to avoid turning this on when using hdmi output.
- */
- axp_set_eldo(3, 1800);
- anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
- ANX9804_DATA_RATE_1620M,
- sunxi_display->depth);
- }
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
- if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
- i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
- i2c_set_bus_num(orig_i2c_bus);
- }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C))
+ sunxi_panel_i2c_init(sunxi_display);
sunxi_composer_mode_set(mode, address, monitor);
sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false);
sunxi_composer_enable();
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
-#include <asm/arch/gpio.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
/* reset panel */
dm_gpio_set_value(&priv->reset, true);
-
+
mdelay(10);
dm_gpio_set_value(&priv->reset, false);
break;
case VIDEO_BPP32:
if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
- return (colors[idx].r << 16) |
- (colors[idx].g << 8) |
- (colors[idx].b << 0);
+ if (priv->format == VIDEO_X2R10G10B10)
+ return (colors[idx].r << 22) |
+ (colors[idx].g << 12) |
+ (colors[idx].b << 2);
+ else
+ return (colors[idx].r << 16) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 0);
}
break;
default:
config W1
bool "Enable 1-wire controllers support"
- default no
depends on DM
help
Support for the Dallas 1-Wire bus.
config W1_GPIO
bool "Enable 1-wire GPIO bitbanging"
- default no
depends on DM_GPIO
help
Emulate a 1-wire bus using a GPIO.
config W1_MXC
bool "Enable 1-wire controller on i.MX processors"
- default no
- depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
+ depends on ARCH_MX31 || ARCH_MX5
help
Support the one wire controller found in some members of the NXP
i.MX SoC family.
config WATCHDOG_TIMEOUT_MSECS
int "Watchdog timeout in msec"
- default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6
+ default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
default 128000 if ARCH_MX7 || ARCH_VF610
default 30000 if ARCH_SOCFPGA
default 60000
This driver support all CPU ISAs supported by Cortina
Access CAxxxx SoCs.
+config WDT_GPIO
+ bool "External gpio watchdog support"
+ depends on WDT
+ depends on DM_GPIO
+ help
+ Support for external watchdog fed by toggling a gpio. See
+ doc/device-tree-bindings/watchdog/gpio-wdt.txt for
+ information on how to describe the watchdog in device tree.
+
config WDT_MPC8xx
bool "MPC8xx watchdog timer support"
depends on WDT && MPC8xx
Say Y here if you want to include support for the K3 watchdog
timer (RTI module) available in the K3 generation of processors.
+if WDT_K3_RTI
+
+config WDT_K3_RTI_LOAD_FW
+ bool "Load watchdog firmware"
+ depends on REMOTEPROC
+ help
+ Automatically load the specified firmware image into the MCU R5F
+ core 0. On the AM65x, this firmware is supposed to handle the expiry
+ of the watchdog timer, typically by resetting the system.
+
+config WDT_K3_RTI_FW_FILE
+ string "Watchdog firmware image file"
+ default "k3-rti-wdt.fw"
+ depends on WDT_K3_RTI_LOAD_FW
+ help
+ Firmware image to be embedded into U-Boot and loaded on watchdog
+ start.
+
+endif
+
config WDT_SANDBOX
bool "Enable Watchdog Timer support for Sandbox"
depends on SANDBOX && WDT
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <wdt.h>
+#include <asm/gpio.h>
+
+struct gpio_wdt_priv {
+ struct gpio_desc gpio;
+ bool always_running;
+ int state;
+};
+
+static int gpio_wdt_reset(struct udevice *dev)
+{
+ struct gpio_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->state = !priv->state;
+
+ return dm_gpio_set_value(&priv->gpio, priv->state);
+}
+
+static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct gpio_wdt_priv *priv = dev_get_priv(dev);
+
+ if (priv->always_running)
+ return 0;
+
+ return -ENOSYS;
+}
+
+static int dm_probe(struct udevice *dev)
+{
+ struct gpio_wdt_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->always_running = dev_read_bool(dev, "always-running");
+ ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT);
+ if (ret < 0) {
+ dev_err(dev, "Request for wdt gpio failed: %d\n", ret);
+ return ret;
+ }
+
+ if (priv->always_running)
+ ret = gpio_wdt_reset(dev);
+
+ return ret;
+}
+
+static const struct wdt_ops gpio_wdt_ops = {
+ .start = gpio_wdt_start,
+ .reset = gpio_wdt_reset,
+};
+
+static const struct udevice_id gpio_wdt_ids[] = {
+ { .compatible = "linux,wdt-gpio" },
+ {}
+};
+
+U_BOOT_DRIVER(wdt_gpio) = {
+ .name = "wdt_gpio",
+ .id = UCLASS_WDT,
+ .of_match = gpio_wdt_ids,
+ .ops = &gpio_wdt_ops,
+ .probe = dm_probe,
+ .priv_auto = sizeof(struct gpio_wdt_priv),
+};
* Watchdog driver for Orion/Kirkwood processors
*
* Authors: Tomas Hlavacek <tmshlvck@gmail.com>
- * Sylver Bruneau <sylver.bruneau@googlemail.com>
- * Marek Behun <marek.behun@nic.cz>
+ * Sylver Bruneau <sylver.bruneau@googlemail.com>
+ * Marek Behun <marek.behun@nic.cz>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <power-domain.h>
#include <wdt.h>
#include <asm/io.h>
+#include <remoteproc.h>
/* Timer register set definition */
#define RTIDWDCTRL 0x90
unsigned int clk_khz;
};
+#ifdef CONFIG_WDT_K3_RTI_LOAD_FW
+#define RTI_WDT_FIT_PATH "/fit-images/k3-rti-wdt-firmware"
+
+static int rti_wdt_load_fw(struct udevice *dev)
+{
+ struct udevice *rproc_dev;
+ int primary_core, ret;
+ u32 cluster_mode;
+ ofnode node;
+ u64 rti_wdt_fw;
+ u32 rti_wdt_fw_size;
+
+ node = ofnode_path(RTI_WDT_FIT_PATH);
+ if (!ofnode_valid(node))
+ goto fit_error;
+
+ ret = ofnode_read_u64(node, "load", &rti_wdt_fw);
+ if (ret)
+ goto fit_error;
+ ret = ofnode_read_u32(node, "size", &rti_wdt_fw_size);
+ if (ret)
+ goto fit_error;
+
+ node = ofnode_by_compatible(ofnode_null(), "ti,am654-r5fss");
+ if (!ofnode_valid(node))
+ goto dt_error;
+
+ ret = ofnode_read_u32(node, "ti,cluster-mode", &cluster_mode);
+ if (ret)
+ cluster_mode = 1;
+
+ node = ofnode_by_compatible(node, "ti,am654-r5f");
+ if (!ofnode_valid(node))
+ goto dt_error;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_REMOTEPROC, node, &rproc_dev);
+ if (ret)
+ return ret;
+
+ primary_core = dev_seq(rproc_dev);
+
+ ret = rproc_dev_init(primary_core);
+ if (ret)
+ goto fw_error;
+
+ if (cluster_mode == 1) {
+ ret = rproc_dev_init(primary_core + 1);
+ if (ret)
+ goto fw_error;
+ }
+
+ ret = rproc_load(primary_core, (ulong)rti_wdt_fw,
+ rti_wdt_fw_size);
+ if (ret)
+ goto fw_error;
+
+ ret = rproc_start(primary_core);
+ if (ret)
+ goto fw_error;
+
+ return 0;
+
+fit_error:
+ dev_err(dev, "No loadable firmware found under %s\n", RTI_WDT_FIT_PATH);
+ return -ENOENT;
+
+dt_error:
+ dev_err(dev, "No compatible firmware target processor found\n");
+ return -ENODEV;
+
+fw_error:
+ dev_err(dev, "Failed to load watchdog firmware into remote processor %d\n",
+ primary_core);
+ return ret;
+}
+#else
+static inline int rti_wdt_load_fw(struct udevice *dev)
+{
+ return 0;
+}
+#endif
+
static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct rti_wdt_priv *priv = dev_get_priv(dev);
if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY)
return -EBUSY;
+ ret = rti_wdt_load_fw(dev);
+ if (ret < 0)
+ return ret;
+
timer_margin = timeout_ms * priv->clk_khz / 1000;
timer_margin >>= WDT_PRELOAD_SHIFT;
if (timer_margin > WDT_PRELOAD_MAX)
#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
-/*
- * Reset every 1000ms, or however often is required as indicated by a
- * hw_margin_ms property.
- */
-static ulong reset_period = 1000;
+struct wdt_priv {
+ /* Timeout, in seconds, to configure this device to. */
+ u32 timeout;
+ /*
+ * Time, in milliseconds, between calling the device's ->reset()
+ * method from watchdog_reset().
+ */
+ ulong reset_period;
+ /*
+ * Next time (as returned by get_timer(0)) to call
+ * ->reset().
+ */
+ ulong next_reset;
+ /* Whether watchdog_start() has been called on the device. */
+ bool running;
+};
-int initr_watchdog(void)
+static void init_watchdog_dev(struct udevice *dev)
{
- u32 timeout = WATCHDOG_TIMEOUT_SECS;
+ struct wdt_priv *priv;
int ret;
- /*
- * Init watchdog: This will call the probe function of the
- * watchdog driver, enabling the use of the device
- */
- if (uclass_get_device_by_seq(UCLASS_WDT, 0,
- (struct udevice **)&gd->watchdog_dev)) {
- debug("WDT: Not found by seq!\n");
- if (uclass_get_device(UCLASS_WDT, 0,
- (struct udevice **)&gd->watchdog_dev)) {
- printf("WDT: Not found!\n");
- return 0;
- }
- }
-
- if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
- timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
- WATCHDOG_TIMEOUT_SECS);
- reset_period = dev_read_u32_default(gd->watchdog_dev,
- "hw_margin_ms",
- 4 * reset_period) / 4;
- }
+ priv = dev_get_uclass_priv(dev);
if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) {
- printf("WDT: Not starting\n");
- return 0;
+ printf("WDT: Not starting %s\n", dev->name);
+ return;
}
- ret = wdt_start(gd->watchdog_dev, timeout * 1000, 0);
+ ret = wdt_start(dev, priv->timeout * 1000, 0);
if (ret != 0) {
- printf("WDT: Failed to start\n");
+ printf("WDT: Failed to start %s\n", dev->name);
+ return;
+ }
+
+ printf("WDT: Started %s with%s servicing (%ds timeout)\n", dev->name,
+ IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", priv->timeout);
+}
+
+int initr_watchdog(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_WDT, &uc);
+ if (ret) {
+ log_debug("Error getting UCLASS_WDT: %d\n", ret);
return 0;
}
- printf("WDT: Started with%s servicing (%ds timeout)\n",
- IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
+ uclass_foreach_dev(dev, uc) {
+ ret = device_probe(dev);
+ if (ret) {
+ log_debug("Error probing %s: %d\n", dev->name, ret);
+ continue;
+ }
+ init_watchdog_dev(dev);
+ }
+ gd->flags |= GD_FLG_WDT_READY;
return 0;
}
return -ENOSYS;
ret = ops->start(dev, timeout_ms, flags);
- if (ret == 0)
- gd->flags |= GD_FLG_WDT_READY;
+ if (ret == 0) {
+ struct wdt_priv *priv = dev_get_uclass_priv(dev);
+
+ priv->running = true;
+ }
return ret;
}
return -ENOSYS;
ret = ops->stop(dev);
- if (ret == 0)
- gd->flags &= ~GD_FLG_WDT_READY;
+ if (ret == 0) {
+ struct wdt_priv *priv = dev_get_uclass_priv(dev);
+
+ priv->running = false;
+ }
+
+ return ret;
+}
+
+int wdt_stop_all(void)
+{
+ struct wdt_priv *priv;
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret, err;
+
+ ret = uclass_get(UCLASS_WDT, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ if (!device_active(dev))
+ continue;
+ priv = dev_get_uclass_priv(dev);
+ if (!priv->running)
+ continue;
+ err = wdt_stop(dev);
+ if (!ret)
+ ret = err;
+ }
return ret;
}
if (ops->expire_now) {
return ops->expire_now(dev, flags);
} else {
- if (!ops->start)
- return -ENOSYS;
+ ret = wdt_start(dev, 1, flags);
- ret = ops->start(dev, 1, flags);
if (ret < 0)
return ret;
*/
void watchdog_reset(void)
{
- static ulong next_reset;
+ struct wdt_priv *priv;
+ struct udevice *dev;
+ struct uclass *uc;
ulong now;
/* Exit if GD is not ready or watchdog is not initialized yet */
if (!gd || !(gd->flags & GD_FLG_WDT_READY))
return;
- /* Do not reset the watchdog too often */
- now = get_timer(0);
- if (time_after_eq(now, next_reset)) {
- next_reset = now + reset_period;
- wdt_reset(gd->watchdog_dev);
+ if (uclass_get(UCLASS_WDT, &uc))
+ return;
+
+ /*
+ * All devices bound to the wdt uclass should have been probed
+ * in initr_watchdog(). But just in case something went wrong,
+ * check device_active() before accessing the uclass private
+ * data.
+ */
+ uclass_foreach_dev(dev, uc) {
+ if (!device_active(dev))
+ continue;
+ priv = dev_get_uclass_priv(dev);
+ if (!priv->running)
+ continue;
+ /* Do not reset the watchdog too often */
+ now = get_timer(0);
+ if (time_after_eq(now, priv->next_reset)) {
+ priv->next_reset = now + priv->reset_period;
+ wdt_reset(dev);
+ }
}
}
#endif
return 0;
}
+static int wdt_pre_probe(struct udevice *dev)
+{
+ u32 timeout = WATCHDOG_TIMEOUT_SECS;
+ /*
+ * Reset every 1000ms, or however often is required as
+ * indicated by a hw_margin_ms property.
+ */
+ ulong reset_period = 1000;
+ struct wdt_priv *priv;
+
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ timeout = dev_read_u32_default(dev, "timeout-sec", timeout);
+ reset_period = dev_read_u32_default(dev, "hw_margin_ms",
+ 4 * reset_period) / 4;
+ }
+ priv = dev_get_uclass_priv(dev);
+ priv->timeout = timeout;
+ priv->reset_period = reset_period;
+ /*
+ * Pretend this device was last reset "long" ago so the first
+ * watchdog_reset will actually call its ->reset method.
+ */
+ priv->next_reset = get_timer(0);
+
+ return 0;
+}
+
UCLASS_DRIVER(wdt) = {
- .id = UCLASS_WDT,
- .name = "watchdog",
- .flags = DM_UC_FLAG_SEQ_ALIAS,
- .post_bind = wdt_post_bind,
+ .id = UCLASS_WDT,
+ .name = "watchdog",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .post_bind = wdt_post_bind,
+ .pre_probe = wdt_pre_probe,
+ .per_device_auto = sizeof(struct wdt_priv),
};
* Xilinx window watchdog timer driver.
*
* Author(s): Michal Simek <michal.simek@xilinx.com>
- * Ashok Reddy Soma <ashokred@xilinx.com>
+ * Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
*
* Copyright (c) 2020, Xilinx Inc.
*/
/* Generic Control/Status Register Masks */
#define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */
-/* Register offsets for the Wdt device */
-#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */
-#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */
-#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */
-#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */
-#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */
-#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */
+/* Register offsets for the WWDT device */
+#define XWT_WWDT_MWR_OFFSET 0x00
+#define XWT_WWDT_ESR_OFFSET 0x04
+#define XWT_WWDT_FCR_OFFSET 0x08
+#define XWT_WWDT_FWR_OFFSET 0x0c
+#define XWT_WWDT_SWR_OFFSET 0x10
+#define XWT_WWDT_CNT_MIN 1
+#define XWT_WWDT_CNT_MAX 0xffffffff
+
+/* Master Write Control Register Masks */
+#define XWT_WWDT_MWR_MASK BIT(0)
+
+/* Enable and Status Register Masks */
+#define XWT_WWDT_ESR_WINT_MASK BIT(16)
+#define XWT_WWDT_ESR_WSW_MASK BIT(8)
+#define XWT_WWDT_ESR_WEN_MASK BIT(0)
struct xlnx_wwdt_priv {
bool enable_once;
static int xlnx_wwdt_reset(struct udevice *dev)
{
+ u32 esr;
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
- regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK);
+ regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
+ regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
+ esr |= XWT_WWDT_ESR_WINT_MASK;
+ esr &= ~XWT_WWDT_ESR_WSW_MASK;
+ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
+ regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
+ esr |= XWT_WWDT_ESR_WSW_MASK;
+ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
return 0;
}
static int xlnx_wwdt_stop(struct udevice *dev)
{
- u32 csr;
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
if (wdt->enable_once) {
return -EBUSY;
}
- /* Disable the generic watchdog timer */
- regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
- csr &= ~(XWT_WWCSR_GWEN_MASK);
- regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
+ /* Disable the window watchdog timer */
+ regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
+ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
clk_disable(&wdt->clk);
return 0;
}
-static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
+static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
int ret;
- u32 csr;
- u64 count;
+ u32 esr;
+ u64 count, timeout;
unsigned long clock_f;
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
+ /* Convert timeout from msec to sec */
+ timeout = timeout_ms / 1000;
+
/* Calculate timeout count */
count = timeout * clock_f;
+ /* Count should be at least 1 */
+ if (count < XWT_WWDT_CNT_MIN) {
+ debug("%s: watchdog won't fire with 0 ticks\n", __func__);
+ count = XWT_WWDT_CNT_MIN;
+ }
+
+ /* Limit the count to maximum possible value */
+ if (count > XWT_WWDT_CNT_MAX) {
+ debug("%s: maximum watchdog timeout exceeded\n", __func__);
+ count = XWT_WWDT_CNT_MAX;
+ }
+
ret = clk_enable(&wdt->clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
- /*
- * Timeout count is half as there are two windows
- * first window overflow is ignored (interrupt),
- * reset is only generated at second window overflow
- */
- count = count >> 1;
-
- /* Disable the generic watchdog timer */
- regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
- csr &= ~(XWT_WWCSR_GWEN_MASK);
- regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
+ /* Disable the window watchdog timer */
+ regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
+ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
- /* Set compare and offset registers for generic watchdog timeout */
- regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count);
- regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0);
- regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count);
+ /* Set first window and second window registers with timeout */
+ regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */
+ regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count);
+ regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0);
- /* Enable the generic watchdog timer */
- regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
- csr |= (XWT_WWCSR_GWEN_MASK);
- regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
+ /* Enable the window watchdog timer */
+ regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
+ esr |= XWT_WWDT_ESR_WEN_MASK;
+ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
return 0;
}
+static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags)
+{
+ return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags);
+}
+
static int xlnx_wwdt_probe(struct udevice *dev)
{
int ret;
.start = xlnx_wwdt_start,
.reset = xlnx_wwdt_reset,
.stop = xlnx_wwdt_stop,
+ .expire_now = xlnx_wwdt_expire_now,
};
static const struct udevice_id xlnx_wwdt_ids[] = {
/* Dealloc all events */
unbind_all_ports();
}
-
setup.dom = DOMID_SELF;
setup.nr_frames = 0;
}
-
bool "Run-time configuration via Device Tree"
select DTC
select OF_LIBFDT if !OF_PLATDATA
+ select OF_REAL if !OF_PLATDATA
help
This feature provides for run-time configuration of U-Boot
via a flattened device tree.
+config OF_REAL
+ bool
+ help
+ Indicates that a real devicetree is available which can be accessed
+ at runtime. This means that dev_read_...() functions can be used to
+ read data from the devicetree for each device. This is true if
+ OF_CONTROL is enabled in U-Boot proper.
+
config OF_BOARD_FIXUP
bool "Board-specific manipulation of Device Tree"
help
bool "Enable run-time configuration via Device Tree in SPL"
depends on SPL && OF_CONTROL
select SPL_OF_LIBFDT if !SPL_OF_PLATDATA
+ select SPL_OF_REAL if !SPL_OF_PLATDATA
help
Some boards use device tree in U-Boot but only have 4KB of SRAM
which is not enough to support device tree. Disable this option to
bool "Enable run-time configuration via Device Tree in TPL"
depends on TPL && OF_CONTROL
select TPL_OF_LIBFDT if !TPL_OF_PLATDATA
+ select TPL_OF_REAL if !TPL_OF_PLATDATA
help
Some boards use device tree in U-Boot but only have 4KB of SRAM
which is not enough to support device tree. Enable this option to
config SPL_MULTI_DTB_FIT
- depends on SPL_LOAD_FIT && SPL_OF_CONTROL && !SPL_OF_PLATDATA
+ depends on SPL_LOAD_FIT && SPL_OF_REAL
bool "Support embedding several DTBs in a FIT image for the SPL"
help
This option provides the SPL with the ability to select its own
compatible string, then adding platform data and U_BOOT_DRVINFO
declarations for each node. See of-plat.txt for more information.
+config SPL_OF_REAL
+ bool
+ help
+ Indicates that a real devicetree is available which can be accessed
+ at runtime. This means that dev_read_...() functions can be used to
+ read data from the devicetree for each device. This is true if
+ SPL_OF_CONTROL is enabled and not SPL_OF_PLATDATA
+
if SPL_OF_PLATDATA
config SPL_OF_PLATDATA_PARENT
endif
+config TPL_OF_REAL
+ bool
+ help
+ Indicates that a real devicetree is available which can be accessed
+ at runtime. This means that dev_read_...() functions can be used to
+ read data from the devicetree for each device. This is true if
+ TPL_OF_CONTROL is enabled and not TPL_OF_PLATDATA
+
config TPL_OF_PLATDATA
bool "Generate platform data for use in TPL"
depends on TPL_OF_CONTROL
still be one byte because the extra address bits are hidden
in the chip address.
- - CONFIG_ENV_EEPROM_IS_ON_I2C
- define this, if you have I2C and SPI activated, and your
- EEPROM, which holds the environment, is on the I2C bus.
-
- CONFIG_I2C_ENV_EEPROM_BUS
if you have an Environment on an EEPROM reached over
I2C muxes, you can define here, how to reach this
config ENV_APPEND
bool "Always append the environment with new data"
- default n
help
If defined, the environment hash table is only ever appended with new
data, but the existing hash table can never be dropped and reloaded
config ENV_WRITEABLE_LIST
bool "Permit write access only to listed variables"
- default n
help
If defined, only environment variables which explicitly set the 'w'
writeable flag can be written and modified at runtime. No variables
config ENV_ACCESS_IGNORE_FORCE
bool "Block forced environment operations"
- default n
help
If defined, don't allow the -f switch to env set override variable
access flags.
if (gd->env_valid == ENV_REDUND)
off = CONFIG_ENV_OFFSET_REDUND;
#endif
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
off + index + offsetof(env_t, data), &c, 1);
return c;
for (i = 0; i < 2; i++) {
/* read CRC */
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
off_env[i] + offsetof(env_t, crc),
(uchar *)&crc[i], sizeof(ulong));
/* read FLAGS */
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
off_env[i] + offsetof(env_t, flags),
(uchar *)&flags[i], sizeof(uchar));
while (len > 0) {
int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len;
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
rdbuf, n);
crc_tmp = crc32(crc_tmp, rdbuf, n);
eeprom_init(-1); /* prepare for EEPROM read/write */
/* read old CRC */
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_ENV_OFFSET + offsetof(env_t, crc),
(uchar *)&crc, sizeof(ulong));
while (len > 0) {
int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len;
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_ENV_OFFSET + off, rdbuf, n);
new = crc32(new, rdbuf, n);
len -= n;
off = CONFIG_ENV_OFFSET_REDUND;
#endif
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
off, (uchar *)buf_env, CONFIG_ENV_SIZE);
return env_import(buf_env, 1, H_EXTERNAL);
env_new.flags = ENV_REDUND_ACTIVE;
#endif
- rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
+ rc = eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR,
off, (uchar *)&env_new, CONFIG_ENV_SIZE);
#ifdef CONFIG_ENV_OFFSET_REDUND
if (rc == 0) {
- eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
+ eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR,
off_red + offsetof(env_t, flags),
(uchar *)&flag_obsolete, 1);
#include <part.h>
#include <search.h>
#include <errno.h>
+#include <dm/ofnode.h>
#define __STR(X) #X
#define STR(X) __STR(X)
int err;
/* look for the partition in mmc CONFIG_SYS_MMC_ENV_DEV */
- str = fdtdec_get_config_string(gd->fdt_blob, dt_prop.partition);
+ str = ofnode_conf_read_str(dt_prop.partition);
if (str) {
/* try to place the environment at end of the partition */
err = mmc_offset_try_partition(str, copy, &val);
propname = dt_prop.offset_redund;
}
#endif
- return fdtdec_get_config_int(gd->fdt_blob, propname, defvalue);
+ return ofnode_conf_read_int(propname, defvalue);
}
#else
static inline s64 mmc_offset(int copy)
struct btrfs_key key;
static const char* dir_item_str[] = {
[BTRFS_FT_REG_FILE] = " ",
- [BTRFS_FT_DIR] = "DIR",
+ [BTRFS_FT_DIR] = "DIR",
[BTRFS_FT_CHRDEV] = "CHR",
[BTRFS_FT_BLKDEV] = "BLK",
[BTRFS_FT_FIFO] = "FIF",
*/
#include "btrfs.h"
+#include <abuf.h>
#include <log.h>
#include <malloc.h>
#include <linux/lzo.h>
static u32 decompress_zstd(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
{
- ZSTD_DStream *dstream;
- ZSTD_inBuffer in_buf;
- ZSTD_outBuffer out_buf;
- void *workspace;
- size_t wsize;
- u32 res = -1;
-
- wsize = ZSTD_DStreamWorkspaceBound(ZSTD_BTRFS_MAX_INPUT);
- workspace = malloc(wsize);
- if (!workspace) {
- debug("%s: cannot allocate workspace of size %zu\n", __func__,
- wsize);
- return -1;
- }
-
- dstream = ZSTD_initDStream(ZSTD_BTRFS_MAX_INPUT, workspace, wsize);
- if (!dstream) {
- printf("%s: ZSTD_initDStream failed\n", __func__);
- goto err_free;
- }
+ struct abuf in, out;
- in_buf.src = cbuf;
- in_buf.pos = 0;
- in_buf.size = clen;
+ abuf_init_set(&in, (u8 *)cbuf, clen);
+ abuf_init_set(&out, dbuf, dlen);
- out_buf.dst = dbuf;
- out_buf.pos = 0;
- out_buf.size = dlen;
-
- while (1) {
- size_t ret;
-
- ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
- if (ZSTD_isError(ret)) {
- printf("%s: ZSTD_decompressStream error %d\n", __func__,
- ZSTD_getErrorCode(ret));
- goto err_free;
- }
-
- if (in_buf.pos >= clen || !ret)
- break;
- }
-
- res = out_buf.pos;
-
-err_free:
- free(workspace);
- return res;
+ return zstd_decompress(&in, &out);
}
u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen)
ret = btrfs_scan_one_device(desc, part, fs_devices, &total_devs);
if (ret) {
- fprintf(stderr, "No valid Btrfs found\n");
+ /*
+ * Avoid showing this when probing for a possible Btrfs
+ *
+ * fprintf(stderr, "No valid Btrfs found\n");
+ */
return ret;
}
return 0;
disk_super = fs_info->super_copy;
ret = btrfs_read_dev_super(desc, part, disk_super);
if (ret) {
- printk("No valid btrfs found\n");
+ debug("No valid btrfs found\n");
goto out_devices;
}
#define BTRFS_STRING_ITEM_KEY 253
-
/* 32 bytes in various csum fields */
#define BTRFS_CSUM_SIZE 32
__u32 inode; /* inode number */
__u32 version; /* inode version */
__u32 offset; /* offset on jeb */
- __u32 totlen; /* record length */
+ __u32 totlen; /* record length */
} __attribute__((packed));
struct jffs2_sum_dirent_flash
__u32 offset; /* offset on jeb */
__u32 pino; /* parent inode */
__u32 version; /* dirent version */
- __u32 ino; /* == zero for unlink */
+ __u32 ino; /* == zero for unlink */
uint8_t nsize; /* dirent name size */
uint8_t type; /* dirent type */
uint8_t name[0]; /* dirent name */
__u32 inode; /* inode number */
__u32 version; /* inode version */
__u32 offset; /* offset on jeb */
- __u32 totlen; /* record length */
+ __u32 totlen; /* record length */
} __attribute__((packed));
struct jffs2_sum_dirent_mem
__u32 offset; /* ofset on jeb */
__u32 pino; /* parent inode */
__u32 version; /* dirent version */
- __u32 ino; /* == zero for unlink */
+ __u32 ino; /* == zero for unlink */
uint8_t nsize; /* dirent name size */
uint8_t type; /* dirent type */
uint8_t name[0]; /* dirent name */
struct jffs2_sum_marker
{
__u32 offset; /* offset of the summary node in the jeb */
- __u32 magic; /* == JFFS2_SUM_MAGIC */
+ __u32 magic; /* == JFFS2_SUM_MAGIC */
};
#define JFFS2_SUMMARY_FRAME_SIZE (sizeof(struct jffs2_raw_summary) + sizeof(struct jffs2_sum_marker))
/* Make sure it has a valid SquashFS magic number*/
if (get_unaligned_le32(&sblk->s_magic) != SQFS_MAGIC_NUMBER) {
- printf("Bad magic number for SquashFS image.\n");
+ debug("Bad magic number for SquashFS image.\n");
ret = -EINVAL;
goto error;
}
};
struct super_operations {
- struct inode *(*alloc_inode)(struct super_block *sb);
+ struct inode *(*alloc_inode)(struct super_block *sb);
void (*destroy_inode)(struct inode *);
- void (*dirty_inode) (struct inode *, int flags);
+ void (*dirty_inode) (struct inode *, int flags);
int (*write_inode) (struct inode *, struct writeback_control *wbc);
int (*drop_inode) (struct inode *);
void (*evict_inode) (struct inode *);
char s_id[32]; /* Informational name */
u8 s_uuid[16]; /* UUID */
- void *s_fs_info; /* Filesystem private info */
+ void *s_fs_info; /* Filesystem private info */
unsigned int s_max_links;
#ifndef __UBOOT__
fmode_t s_mode;
#define f_dentry f_path.dentry
#define f_vfsmnt f_path.mnt
const struct file_operations *f_op;
- unsigned int f_flags;
+ unsigned int f_flags;
loff_t f_pos;
unsigned int f_uid, f_gid;
#if BITS_PER_LONG==32
#define MAX_LFS_FILESIZE (((u64)PAGE_CACHE_SIZE << (BITS_PER_LONG-1))-1)
#elif BITS_PER_LONG==64
-#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL
+#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL
#endif
/*
#else
#include "malloc.h"
#endif
+#include <linux/mtd/rawnand.h>
unsigned yaffs_trace_mask = 0x0; /* Disable logging */
static int yaffs_errno;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __ABUF_H
+#define __ABUF_H
+
+#include <linux/types.h>
+
+/**
+ * struct abuf - buffer that can be allocated and freed
+ *
+ * This is useful for a block of data which may be allocated with malloc(), or
+ * not, so that it needs to be freed correctly when finished with.
+ *
+ * For now it has a very simple purpose.
+ *
+ * Using memset() to zero all fields is guaranteed to be equivalent to
+ * abuf_init().
+ *
+ * @data: Pointer to data
+ * @size: Size of data in bytes
+ * @alloced: true if allocated with malloc(), so must be freed after use
+ */
+struct abuf {
+ void *data;
+ size_t size;
+ bool alloced;
+};
+
+static inline void *abuf_data(const struct abuf *abuf)
+{
+ return abuf->data;
+}
+
+static inline size_t abuf_size(const struct abuf *abuf)
+{
+ return abuf->size;
+}
+
+/**
+ * abuf_set() - set the (unallocated) data in a buffer
+ *
+ * This simply makes the abuf point to the supplied data, which must be live
+ * for the lifetime of the abuf. It is not alloced.
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_map_sysmem() - calls map_sysmem() to set up an abuf
+ *
+ * This is equivalent to abuf_set(abuf, map_sysmem(addr, size), size)
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @addr: Address to set the abuf to
+ * @size: New size of abuf
+ */
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size);
+
+/**
+ * abuf_realloc() - Change the size of a buffer
+ *
+ * This uses realloc() to change the size of the buffer, with the same semantics
+ * as that function. If the abuf is not currently alloced, then it will alloc
+ * it if the size needs to increase (i.e. set the alloced member to true)
+ *
+ * @abuf: abuf to adjust
+ * @new_size: new size in bytes.
+ * if 0, the abuf is freed
+ * if greater than the current size, the abuf is extended and the new
+ * space is not inited. The alloced member is set to true
+ * if less than the current size, the abuf is contracted and the data at
+ * the end is lost. If @new_size is 0, this sets the alloced member to
+ * false
+ * @return true if OK, false if out of memory
+ */
+bool abuf_realloc(struct abuf *abuf, size_t new_size);
+
+/**
+ * abuf_uninit_move() - Return the allocated contents and uninit the abuf
+ *
+ * This returns the abuf data to the caller, allocating it if necessary, so that
+ * the caller receives data that it can be sure will hang around. The caller is
+ * responsible for freeing the data.
+ *
+ * If the abuf has allocated data, it is returned. If the abuf has data but it
+ * is not allocated, then it is first allocated, then returned.
+ *
+ * If the abuf size is 0, this returns NULL
+ *
+ * The abuf is uninited as part of this, except if the allocation fails, in
+ * which NULL is returned and the abuf remains untouched.
+ *
+ * The abuf must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ * @sizep: if non-NULL, returns the size of the returned data
+ * @return data contents, allocated with malloc(), or NULL if the data could not
+ * be allocated, or the data size is 0
+ */
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep);
+
+/**
+ * abuf_init_move() - Make abuf take over the management of an allocated region
+ *
+ * After this, @data must not be used. All access must be via the abuf.
+ *
+ * @abuf: abuf to init
+ * @data: Existing allocated buffer to place in the abuf
+ * @size: Size of allocated buffer
+ */
+void abuf_init_move(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_init_set() - Set up a new abuf
+ *
+ * Inits a new abuf and sets up its (unallocated) data
+ *
+ * @abuf: abuf to set up
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_init_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_uninit() - Free any memory used by an abuf
+ *
+ * The buffer must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ */
+void abuf_uninit(struct abuf *abuf);
+
+/**
+ * abuf_init() - Set up a new abuf
+ *
+ * This initially has no data and alloced is set to false. This is equivalent to
+ * setting all fields to 0, e.g. with memset(), so callers can do that instead
+ * if desired.
+ *
+ * @abuf: abuf to set up
+ */
+void abuf_init(struct abuf *abuf);
+
+#endif
*/
void *trace_buff;
#endif
-#if defined(CONFIG_SYS_I2C_LEGACY)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/**
* @cur_i2c_bus: currently used I2C bus
*/
*/
fdt_addr_t translation_offset;
#endif
-#if CONFIG_IS_ENABLED(WDT)
- /**
- * @watchdog_dev: watchdog device
- */
- struct udevice *watchdog_dev;
-#endif
#ifdef CONFIG_GENERATE_ACPI_TABLE
/**
* @acpi_ctx: ACPI context pointer
struct fdtdec_phandle_args;
/**
+ * gpio_flags_xlate() - convert DT flags to internal flags
+ *
+ * This routine converts the GPIO_* flags from the generic DT binding to the
+ * GPIOD_* flags used internally. It can be called from driver xlate functions.
+ */
+unsigned long gpio_flags_xlate(uint32_t arg);
+
+/**
* gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate
*
* This routine sets the offset field to args[0] and the flags field to
*/
int dm_gpio_request(struct gpio_desc *desc, const char *label);
+struct phandle_2_arg;
+int gpio_request_by_phandle(struct udevice *dev,
+ const struct phandle_2_arg *cells,
+ struct gpio_desc *desc, int flags);
+
/**
* gpio_get_list_count() - Returns the number of GPIOs in a list
*
* I2C Driver for Atmel ATSHA204 over I2C
*
* Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
- * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
*/
#ifndef _AXP_PMIC_H_
+#include <stdbool.h>
+
#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
#endif
#include <axp818.h>
#endif
+#define AXP_PMIC_MODE_REG 0x3e
+#define AXP_PMIC_MODE_I2C 0x00
+#define AXP_PMIC_MODE_P2WI 0x3e
+#define AXP_PMIC_MODE_RSB 0x7c
+
+#define AXP_PMIC_PRI_DEVICE_ADDR 0x3a3
+#define AXP_PMIC_PRI_RUNTIME_ADDR 0x2d
+#define AXP_PMIC_SEC_DEVICE_ADDR 0x745
+#define AXP_PMIC_SEC_RUNTIME_ADDR 0x3a
+
int axp_set_dcdc1(unsigned int mvolt);
int axp_set_dcdc2(unsigned int mvolt);
int axp_set_dcdc3(unsigned int mvolt);
#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
struct phandle_1_arg;
-int clk_get_by_driver_info(struct udevice *dev,
- struct phandle_1_arg *cells, struct clk *clk);
+/**
+ * clk_get_by_phandle() - Get a clock by its phandle information (of-platadata)
+ *
+ * This function is used when of-platdata is enabled.
+ *
+ * This looks up a clock using the phandle info. With dtoc, each phandle in the
+ * 'clocks' property is transformed into an idx representing the device. For
+ * example:
+ *
+ * clocks = <&dpll_mpu_ck 23>;
+ *
+ * might result in:
+ *
+ * .clocks = {1, {23}},},
+ *
+ * indicating that the clock is udevice idx 1 in dt-plat.c with an argument of
+ * 23. This function can return a valid clock given the above information. In
+ * this example it would return a clock containing the 'dpll_mpu_ck' device and
+ * the clock ID 23.
+ *
+ * @dev: Device containing the phandle
+ * @cells: Phandle info
+ * @clock: A pointer to a clock struct to initialise
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells,
+ struct clk *clk);
/**
- * clk_get_by_index - Get/request a clock by integer index.
+ * clk_get_by_index() - Get/request a clock by integer index.
*
* This looks up and requests a clock. The index is relative to the client
* device; each device is assumed to have n clocks associated with it somehow,
CLK_DEFAULTS_POST_FORCE,
};
-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
- CONFIG_IS_ENABLED(CLK)
-
+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(CLK)
/**
* clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}'
* properties to configure clocks
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
-#ifndef _ASM_ARCH_CCU_H
-#define _ASM_ARCH_CCU_H
+#ifndef _CLK_SUNXI_H
+#define _CLK_SUNXI_H
-#ifndef __ASSEMBLY__
#include <linux/bitops.h>
-#endif
/**
* enum ccu_flags - ccu clock/reset flags
*/
int sunxi_reset_bind(struct udevice *dev, ulong count);
-#endif /* _ASM_ARCH_CCU_H */
+#endif /* _CLK_SUNXI_H */
unsigned long get_bus_freq(unsigned long dummy);
int get_serial_clock(void);
+/*
+ * If we have CONFIG_DYNAMIC_DDR_CLK_FREQ then there will be an
+ * implentation of get_board_ddr_clk() somewhere. Otherwise we have
+ * a static value to use now.
+ */
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
+unsigned long get_board_ddr_clk(void);
+#else
+#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ
+#endif
+
#endif
typedef unsigned int uint;
typedef unsigned long ulong;
+/* Define these on the host so we can build some target code */
+typedef __u32 u32;
+
#define uswap_16(x) \
((((x) & 0xff00) >> 8) | \
(((x) & 0x00ff) << 8))
#define MEM_SUPPORT_64BIT_DATA 0
#endif
-static inline bool host_build(void) {
+/**
+ * tools_build() - check if we are building host tools
+ *
+ * @return true if building for the host, false if for a target
+ */
+static inline bool tools_build(void)
+{
#ifdef USE_HOSTCC
return true;
#else
"fi\0" \
\
"scsi_boot=" \
+ BOOTENV_RUN_PCI_ENUM \
BOOTENV_RUN_SCSI_INIT \
BOOTENV_SHARED_BLKDEV_BODY(scsi)
#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV
#define CONFIG_SYS_MAXARGS 16
#endif
-#if CONFIG_IS_ENABLED(DM_I2C)
-# ifdef CONFIG_SYS_I2C_LEGACY
-# error "Cannot define CONFIG_SYS_I2C_LEGACY when CONFIG_DM_I2C is used"
-# endif
-#endif
-
#endif /* __CONFIG_FALLBACKS_H */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MALLOC_LEN 0x20000
/*
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
* (which is common practice).
*/
-/*
- * MISC
- */
-#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MALLOC_LEN 0x20000
/*
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
* (which is common practice).
*/
-/*
- * MISC
- */
-#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#endif /* __CONFIG_H */
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_LOAD_ADDR 0x40010000
-
#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR 0x36
#define CONFIG_SYS_PLL_FDR 0x7D
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
env/embedded.o(.text*);
/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_i2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
-
#define CONFIG_SYS_CLK 75000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-
/*
* Clock configuration: enable only one of the following options
*/
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET (0)
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#endif
#define CONFIG_SYS_MONITOR_LEN 0x40000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
/*
#endif
/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
"save\0" \
""
-#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_SYS_CLK 66000000
/*
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#endif
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
-#define CONFIG_SYS_LOAD_ADDR 0x800000
-
#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#ifdef CONFIG_MCFFEC
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
"save\0" \
""
-#define CONFIG_SYS_LOAD_ADDR 0x20000
-
#define CONFIG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_LOAD_ADDR 0x40010000
-
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_LOAD_ADDR 0x40010000
-
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_LOAD_ADDR 0x40010000
-
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR 0x200000
-
#define CONFIG_SYS_HZ 1000
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CONFIG_SYS_MONITOR_LEN (320 << 10)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
/* Environment Configuration */
/* NAND configuration part */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * mpc8349emds board configuration file
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
-
-/*
- * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
- * unselect it to use old spd_sdram.c
- */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x52
-#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef CONFIG_DDR_2T_TIMING
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
-
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-#else
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
-#define CONFIG_SYS_DDR_MODE 0x47d00432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#else
-#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_1 0x36332321
-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
-
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
- /* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000023
-#else
-/* the default burst length is 4 - for 64-bit data path */
- /* DLL,normal,seq,4/2.5, 4 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000022
-#endif
-#endif
-#endif
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
- */
-#define CONFIG_SYS_BCSR 0xE2400000
- /* Access window base at BCSR base */
-
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* SPI */
-#undef CONFIG_SOFT_SPI /* SPI bit-banged */
-
-/* GPIOs. Used as SPI chip selects */
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
-#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/* USB */
-#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_83XX_PCI_STREAMING
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/*
- * System performance
- */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_HOSTNAME "mpc8349emds"
-#define CONFIG_ROOTPATH "/nfsroot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=mpc8349emds\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
- "update=protect off fe000000 fe03ffff; " \
- "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc834x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * mpc8349emds board configuration file
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
-
-/*
- * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
- * unselect it to use old spd_sdram.c
- */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x52
-#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef CONFIG_DDR_2T_TIMING
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
-
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-#else
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
-#define CONFIG_SYS_DDR_MODE 0x47d00432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#else
-#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_1 0x36332321
-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
-
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
- /* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000023
-#else
-/* the default burst length is 4 - for 64-bit data path */
- /* DLL,normal,seq,4/2.5, 4 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000022
-#endif
-#endif
-#endif
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
- */
-#define CONFIG_SYS_BCSR 0xE2400000
- /* Access window base at BCSR base */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- */
-
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* SPI */
-#undef CONFIG_SOFT_SPI /* SPI bit-banged */
-
-/* GPIOs. Used as SPI chip selects */
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
-#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/* USB */
-#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_83XX_PCI_STREAMING
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/*
- * System performance
- */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_HOSTNAME "mpc8349emds"
-#define CONFIG_ROOTPATH "/nfsroot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=mpc8349emds\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
- "update=protect off fe000000 fe03ffff; " \
- "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc834x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
-#undef CONFIG_DDR_ECC /* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
/*
| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x06090100 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2)
/* 0x43000000 */
-#endif
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT))
#endif
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
#define CONFIG_FSL_SERDES2 0xe3100
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
"run setbootargs;" \
"run setipargs;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv rootdev /dev/ram;" \
"run setbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
/*
* I2C
*/
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* RapidIO MMU */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND
#endif /* __CONFIG_H */
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
* I2C
*/
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#else
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
-#define CONFIG_SYS_I2C_FSL
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_CCID
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* General PCI
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=off\0" \
"netdev=eth0\0" \
"fdtaddr=1e00000\0" \
"fdtfile=mpc8548cds.dtb\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND
#endif /* __CONFIG_H */
*/
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/*
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
/*
* I2C
*/
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* RapidIO MMU */
#endif /* CONFIG_TSEC_ENET */
-#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
-
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
-#if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
- #define FETH2_RST 0x01
-#elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
-
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
-#define MIIDELAY udelay(1)
-
-#endif
-
/*
* Environment
*/
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyCPM\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8560ads.dtb\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND
#endif /* __CONFIG_H */
#include <linux/stringify.h>
#include <asm/config_mpc85xx.h>
-#define CONFIG_NAND_FSL_IFC
#ifdef CONFIG_SDCARD
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
#define CONFIG_HWCONFIG
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
| CSOR_NAND_PGS_512 /* Page Size = 512b */ \
| CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/*
* Config the L2 Cache as L2 SRAM
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
#define I2C_PCA9557_ADDR1 0x18
#define I2C_PCA9557_ADDR2 0x19
#define I2C_PCA9557_BUS_NUM 0
-#define CONFIG_SYS_I2C_FSL
/* I2C EEPROM */
#if defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
#endif
/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* RTC */
#define CONFIG_RTC_PT7C4338
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \
"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
#endif
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND RAMBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* DDR Setup
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_NAND_FSL_ELBC
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BASE 0xffa00000
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_FSL
/*
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
"bdev=sda3\0"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+#define CONFIG_BOOTCOMMAND HDBOOT
#include <asm/fsl_secure_boot.h>
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_NAND_FSL_ELBC
#define CONFIG_PCIE3
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_FSL_RAID_ENGINE
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
/* additions for new ARM relocation support */
* for your console driver.
*/
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
#define MTDPARTS_MTDOOPS "errlog"
#define CONFIG_DOS_PARTITION
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-
#endif /* _CONFIG_SBX81LIFKW_H */
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
/* additions for new ARM relocation support */
* for your console driver.
*/
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
#define MTDPARTS_MTDOOPS "errlog"
#define CONFIG_DOS_PARTITION
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
/*
* For booting Linux, the board info and command line data
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-
#endif /* _CONFIG_SBX81LIFXCAT_H */
#endif
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
-#endif
#endif
#ifdef CONFIG_SPIFLASH
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
-#endif
#endif
#ifdef CONFIG_SDCARD
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
-#endif
#endif
#endif /* CONFIG_RAMBOOT_PBL */
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* DDR Setup
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#endif
/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define I2C_PCA6408_BUS_NUM 1
#define I2C_PCA6408_ADDR 0x20
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
#define __USB_PHY_TYPE utmi
#ifdef CONFIG_ARCH_T1024
"fdtaddr=1e00000\0" \
"bdev=sda3\0"
-#define CONFIG_LINUX \
+#define LINUXBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"setenv ramdiskaddr 0x02000000;" \
"setenv loadaddr 0x1000000;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_RAMBOOT_PBL
-
-#ifndef CONFIG_NXP_ESBC
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_PBI \
- $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
-#endif
-
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
-#endif
#endif
#ifdef CONFIG_SPIFLASH
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
-#endif
#endif
#ifdef CONFIG_SDCARD
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
-#endif
#endif
#endif
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 66666666
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C3_SPEED 400000
-#define CONFIG_SYS_FSL_I2C4_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x8
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
#endif
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#define __USB_PHY_TYPE utmi
#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
"fdtfile=" __stringify(FDTFILE) "\0" \
"bdev=sda3\0"
-#define CONFIG_LINUX \
+#define LINUXBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"setenv ramdiskaddr 0x02000000;" \
"setenv loadaddr 0x1000000;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
-
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
-#endif
#endif
#ifdef CONFIG_SPIFLASH
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
-#endif
#endif
#ifdef CONFIG_SDCARD
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
-#endif
#endif
#endif /* CONFIG_RAMBOOT_PBL */
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
/*
* Config the L3 Cache as L3 SRAM
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/*
* DDR Setup
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define CONFIG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/*
* Serial Port
/*
* I2C
*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
-#define CONFIG_SYS_FSL_I2C3_SPEED 100000
-#define CONFIG_SYS_FSL_I2C4_SPEED 100000
-#endif
-
-#define CONFIG_SYS_I2C_FSL
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
* For emulation this causes u-boot to jump to the start of the
* proof point app code automatically
*/
-#define CONFIG_PROOF_POINTS \
+#define PROOF_POINTS \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"cpu 1 release 0x29000000 - - -;" \
"cpu 7 release 0x29000000 - - -;" \
"go 0x29000000"
-#define CONFIG_HVBOOT \
+#define HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_ALU \
+#define ALU \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"cpu 1 release 0x01000000 - - -;" \
"cpu 7 release 0x01000000 - - -;" \
"go 0x01000000"
-#define CONFIG_LINUX \
+#define LINUXBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"setenv ramdiskaddr 0x02000000;" \
"setenv loadaddr 0x1000000;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
-
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
#endif
#ifdef CONFIG_SPIFLASH
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
#endif
#ifdef CONFIG_SDCARD
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
#endif
#endif /* CONFIG_RAMBOOT_PBL */
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 66660000
-#define CONFIG_DDR_CLK_FREQ 133330000
/*
* Config the L3 Cache as L3 SRAM
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* DDR Setup
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/*
* Serial Port
/*
* I2C
*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
-#define CONFIG_SYS_FSL_I2C3_SPEED 100000
-#define CONFIG_SYS_FSL_I2C4_SPEED 100000
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
* For emulation this causes u-boot to jump to the start of the
* proof point app code automatically
*/
-#define CONFIG_PROOF_POINTS \
+#define PROOF_POINTS \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"cpu 1 release 0x29000000 - - -;" \
"cpu 7 release 0x29000000 - - -;" \
"go 0x29000000"
-#define CONFIG_HVBOOT \
+#define HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_ALU \
+#define ALU \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"cpu 1 release 0x01000000 - - -;" \
"cpu 7 release 0x01000000 - - -;" \
"go 0x01000000"
-#define CONFIG_LINUX \
+#define LINUXBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"setenv ramdiskaddr 0x02000000;" \
"setenv loadaddr 0x1000000;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
#ifndef CONFIG_SDCARD
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
#endif
#ifdef CONFIG_SPL_BUILD
#endif
#endif /* CONFIG_RAMBOOT_PBL */
-#define CONFIG_DDR_ECC
-
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
-
/*
* IFC Definitions
*/
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL
/*
* General PCI
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_HVBOOT \
+#define HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ 133333333
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
/*
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE 0xff800000
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(128)) /*Page Per Block = 128*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#endif
/* I2C */
-#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
"fdtfile=t4240rdb/t4240rdb.dtb\0" \
"bdev=sda3\0"
-#define CONFIG_HVBOOT \
+#define HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_LINUX \
+#define LINUXBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"setenv ramdiskaddr 0x02000000;" \
"setenv loadaddr 0x1000000;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
*/
#define CONFIG_USE_INTERRUPT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_SKIP_TRUNOFF_WATCHDOG
#define CONFIG_ARCH_MAP_SYSMEM
* Size of malloc() pool
*/
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* Physical Memory Map
GENERATED_GBL_DATA_SIZE)
/*
- * Load address and memory test area should agree with
- * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x300000
-
-/* memtest works on 63 MB in DRAM */
-
-/*
* Static memory controller configuration
*/
#define CONFIG_FTSMC020
*/
#define CONFIG_USE_INTERRUPT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_ARCH_MAP_SYSMEM
#define CONFIG_BOOTP_SERVERIP
*/
/*
- * Size of malloc() pool
- */
-/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-
-/*
* AHB Controller configuration
*/
#define CONFIG_FTAHBC020S
#endif /* CONFIG_MEM_REMAP */
/*
- * Load address and memory test area should agree with
- * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x300000
-
-/* memtest works on 63 MB in DRAM */
-
-/*
* Static memory controller configuration
*/
#define CONFIG_FTSMC020
#define CONFIG_SYS_BOOTM_LEN SZ_16M
-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
/* PMIC support */
#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
/* SPL related */
#elif defined(CONFIG_EMMC_BOOT)
#define CONFIG_SYS_MMC_MAX_DEVICE 2
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
/* Network. */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifndef CONFIG_SPL_BUILD
#define MEM_LAYOUT_ENV_SETTINGS \
#define CONFIG_SYS_BOOTCOUNT_LE
#ifdef CONFIG_MTD_RAW_NAND
-
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 4096
-#define CONFIG_SYS_NAND_OOBSIZE 256
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
-
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define MTDIDS_DEFAULT "nand0=nand.0"
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-
#endif /* CONFIG_MTD_RAW_NAND */
#define CONFIG_AM335X_USB0
/* Ethernet support */
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION 1
/* NAND config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#endif /* ! __CONFIG_IGEP003X_H */
#endif
#define CONFIG_NET_RETRY_COUNT 10
-
-/* I2C configuration */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 1
#endif /* ! __CONFIG_AM335X_SHC_H */
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-/*#define CONFIG_MACH_TYPE 3589 Until the next sync */
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
/* PMIC support */
#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
#include <configs/ti_omap3_common.h>
-#define CONFIG_REVISION_TAG
-
-/* Hardware drivers */
-
-/*
- * USB configuration
- * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
- * Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_USB_EHCI_OMAP
-#else
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
-#endif
-
-/* I2C */
-
/* Ethernet */
#define CONFIG_NET_RETRY_COUNT 10
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 16, 17, 18, 19, 20, \
21, 22, 23, 24, 25, 26, 27, 28, 30, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
#endif
/* I2C Configuration */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* Power */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#endif
#define CONFIG_POWER_TPS65218
#define CONFIG_POWER_TPS62362
#define CONFIG_SYS_PL310_BASE 0x48242000
/*
- * Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
* When building U-Boot such that there is no previous loader
* we need to call board_early_init_f. This is taken care of in
* s_init when we have SPL used.
#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_AM437X_USB2PHY2_HOST
#endif
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER)
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_GADGET)
#undef CONFIG_USB_DWC3_PHY_OMAP
#undef CONFIG_USB_DWC3_OMAP
#undef CONFIG_USB_DWC3
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_PAGE_SIZE 4096
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
/* NAND: SPL related configs */
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
#define CONFIG_SYS_OMAP_ABE_SYSCK
#ifndef CONFIG_SPL_BUILD
#define CONFIG_NET_RETRY_COUNT 10
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-/* USB xHCI HOST */
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_OMAP_USB3PHY1_HOST
-
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
#endif
-#ifndef CONFIG_CPU_V7R
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#if defined(CONFIG_TARGET_AM642_A53_EVM)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
#endif
-#ifndef CONFIG_CPU_V7R
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BOOTCOMMAND "bootm ffc20000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
-/* undef to save memory */
-
-#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
-
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 45000000
/* reserve 128-4KB */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
#define LDS_BOARD_TEXT \
* This is a single unified instruction/data cache.
* sdram - single region - no masks
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_SYS_CS1_CTRL 0x0100
#endif /* __AMCORE_CONFIG_H */
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {9600, 19200, 38400, 57600, 115200}
-
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
"bootm 0x9f650000"
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
* Serial Port
*/
#define CONFIG_SYS_NS16550_CLK 25000000
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {9600, 19200, 38400, 57600, 115200}
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
* Serial Port
*/
#define CONFIG_SYS_NS16550_CLK 25000000
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {9600, 19200, 38400, 57600, 115200}
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
#define USDHC2_BASE_ADDR 0x5b020000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Networking */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
"${blkcnt}; fi\0"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80280000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define USDHC2_BASE_ADDR 0x5b020000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x89000000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#undef CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MACH_TYPE 4886
-
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
#include "imx6_spl.h"
#endif
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* I2C Configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_MXC_I2C3_SPEED 400000
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
-#define CONFIG_LOADADDR 0x12000000
-
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0"
/* Miscellaneous configurable options */
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 48
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30
-
/* PCI networking support */
#define CONFIG_E1000_NO_NVM
#include "mx6_common.h"
-#define CONFIG_MACH_TYPE 4501
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
/* MMC Configs */
#endif
#if (CONFIG_SYS_BOARD_VERSION == 5)
-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+#define EXTRA_ENV_BOARD_SETTINGS \
"dead=while true; do; " \
"led led_red on; sleep 1;" \
"led led_red off; sleep 1;" \
"done\0"
#elif (CONFIG_SYS_BOARD_VERSION == 6)
-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+#define EXTRA_ENV_BOARD_SETTINGS \
"dead=while true; do; " \
"led led_red on; led led_red2 on; sleep 1;" \
"led led_red off; led led_red2 off;; sleep 1;" \
"run main_rescue_boot;" \
"fi; \0"\
HAB_EXTRA_SETTINGS \
- CONFIG_EXTRA_ENV_BOARD_SETTINGS
+ EXTRA_ENV_BOARD_SETTINGS
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- 64 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#include <asm/arch/platform.h>
/* Misc CPU related */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
-
/*
* NS16550 Configuration
*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef __CONFIG_ASPENITE_H
-#define __CONFIG_ASPENITE_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
-#define CONFIG_ARMADA100 1 /* SOC Family Name */
-#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * There is no internal RAM in ARMADA100, using DRAM
- * TBD: dcache to be used for this
- */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-
-#endif /* __CONFIG_ASPENITE_H */
* set the card type to actually compile for; either of
* the possibilities listed below has to be used!
*/
-#define CONFIG_ASTRO_V532 1
+#define ASTRO_V532 1
-#if CONFIG_ASTRO_V532
+#if ASTRO_V532
#define ASTRO_ID 0xF8
-#elif CONFIG_ASTRO_V512
+#elif ASTRO_V512
#define ASTRO_ID 0xFA
-#elif CONFIG_ASTRO_TWIN7S2
+#elif ASTRO_TWIN7S2
#define ASTRO_ID 0xF9
-#elif CONFIG_ASTRO_V912
+#elif ASTRO_V912
#define ASTRO_ID 0xFC
-#elif CONFIG_ASTRO_COFDMDUOS2
+#elif ASTRO_COFDMDUOS2
#define ASTRO_ID 0xFB
#else
#error No card type defined!
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/*
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */
#else
-#if CONFIG_ASTRO_V532
+#if ASTRO_V532
#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
"run xilinxload&&run alteraload&&bootm 0x80000;"\
"update;reset"
#endif
#endif
-/* default RAM address for user programs */
-#define CONFIG_SYS_LOAD_ADDR 0x20000
-
#define CONFIG_FPGA_COUNT 1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
-/* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10)
/*
* For booting Linux, the board info and command line data
#endif
/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
/*
* BOOTP options
*/
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
#endif
#endif
/* Misc CPU related */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-/*
- * The (arm)linux board id set by generic code depending on configured board
- * (see boards.cfg for different boards)
- */
-#ifdef CONFIG_AT91SAM9G20
- /* the sam9g20 variants have two different board ids */
-# ifdef CONFIG_AT91SAM9G20EK_2MMC
- /* we may be setup for the 2MMC variant of at91sam9g20ek */
-# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC
-# else
- /* or the normal at91sam9g20ek */
-# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK
-# endif
-#else
- /* otherwise default to good old at91sam9260ek */
-# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK
-#endif
-
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
"fatload mmc 0:1 0x22000000 uImage; bootm"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
#endif
#include <asm/hardware.h>
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_ATMEL_LEGACY
/*
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
#endif
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
-#define CONFIG_SKIP_LOWLEVEL_INIT
#else
#define CONFIG_SYS_USE_NORFLASH
#endif
(AT91_PMC_PLLAR_29 | \
AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
AT91_PMC_PLLXR_PLLCOUNT(63) | \
- AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
+ AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
+ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
#endif
#define CONFIG_AT91SAM9M10G45EK
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
"bootz 0x72000000 - 0x71000000"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
/* LCD */
#define LCD_BPP LCD_COLOR16
"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
-/* Ethernet */
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* USB host */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x6000
#define CONFIG_SPL_STACK 0x308000
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
#define CONFIG_ATMEL_LEGACY
/*
/* Ethernet - not present */
-/* USB - not supported */
-
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
"fatload mmc 0:1 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
#endif
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
#endif
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#endif
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_BOOTCOMMAND "nand read " \
"bootm 0x22000000"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x6000
#define CONFIG_SPL_STACK 0x308000
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif
#define CONFIG_SPL_BSS_START_ADDR 0x04000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
#endif
#endif
*/
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * Size of malloc() pool
- * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
- */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-
/* DT blob (fdt) address */
#define CONFIG_SYS_FDT_BASE 0x800f0000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
GENERATED_GBL_DATA_SIZE)
-/*
- * Load address and memory test area should agree with
- * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
-
-/*
- * memtest works on 512 MB in DRAM
- */
-
-/*
- * FLASH and environment organization
- */
-
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
#define CONFIG_SYS_BOOTM_LEN SZ_128M
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* UART configuration
* Environment configuration
*/
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
#include <linux/sizes.h>
#include <configs/ti_am335x_common.h>
-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
/* PMIC support */
#define CONFIG_POWER_TPS65910
#ifndef CONFIG_NOR_BOOT
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#endif
#endif
#define CONFIG_SYS_TEXT_BASE 0x10100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
-#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */
-
#include "bcmstb.h"
#define BCMSTB_TIMER_LOW 0xf0412008
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
-#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */
-
#include "bcmstb.h"
#define BCMSTB_TIMER_LOW 0xf0412008
#define PHYS_SDRAM_1 V2M_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000)
/*
* Initial SP before reloaction is placed at end of first DRAM bank,
*/
#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000)
/* 12MB Malloc size */
-#define CONFIG_SYS_MALLOC_LEN (SZ_8M + SZ_4M)
/* console configuration */
#define CONFIG_SYS_NS16550_CLK 25000000
#ifndef __BCMSTB_H
#define __BCMSTB_H
-#include "version.h"
#include <linux/sizes.h>
#ifndef __ASSEMBLY__
/*
* CPU configuration.
*/
-#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory configuration.
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_LOAD_ADDR 0x2000000
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.
/*
* Informational display configuration.
*/
-#define CONFIG_REVISION_TAG
/*
* Command configuration.
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER
-
/* SPI */
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIGS_BG0900_H__
-#define __CONFIGS_BG0900_H__
-
-/* Memory configuration */
-#define PHYS_SDRAM_1 0x40000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-/* Environment */
-
-/* FEC Ethernet on SoC */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#endif
-
-/* Boot Linux */
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTCOMMAND "bootm"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "update_spi_firmware_filename=u-boot.sb\0" \
- "update_spi_firmware_maxsz=0x80000\0" \
- "update_spi_firmware=" /* Update the SPI flash firmware */ \
- "if sf probe 2:0 ; then " \
- "if tftp ${update_spi_firmware_filename} ; then " \
- "sf erase 0x0 +${filesize} ; " \
- "sf write ${loadaddr} 0x0 ${filesize} ; " \
- "fi ; " \
- "fi\0"
-
-/* The rest of the configuration is shared */
-#include <configs/mxs.h>
-
-#endif /* __CONFIGS_BG0900_H__ */
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* Enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M)
-
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define IMX_FEC1_BASE ENET1_BASE_ADDR
#define CONFIG_SYS_FSL_QSPI_LE
#endif
-#define CONFIG_LOADADDR 0x82000000
-
/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_BOARD_SIZE_LIMIT 520192
"source to NAND\0" \
"active_workset=1\0"
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical memory map */
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (SZ_512M)
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#endif
/* Memory usage */
#define CONFIG_SYS_MAXARGS 24
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K
#define CONFIG_SYS_CBSIZE SZ_512
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
-
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
/*
* Console
*/
230400, 500000, 1500000 }
/* Memory usage */
#define CONFIG_SYS_MAXARGS 24
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024)
/*
/* U-Boot */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif /* CONFIG_MTD_RAW_NAND */
/*
* bcm963158
*/
-
230400, 500000, 1500000 }
/* Memory usage */
#define CONFIG_SYS_MAXARGS 24
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/*
* 6858
/* U-Boot */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif /* CONFIG_MTD_RAW_NAND */
/*
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif /* CONFIG_MTD_RAW_NAND */
230400, 500000, 1500000 }
/* Memory usage */
#define CONFIG_SYS_MAXARGS 24
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/*
* 6858
/* U-Boot */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif /* CONFIG_MTD_RAW_NAND */
/*
* 968580xref
*/
-
#include <linux/stringify.h>
/* ------------------------------------------------------------------------- */
/* memory */
-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN SZ_32M
/* Clock Defines */
#define CONFIG_POWER_TPS65217
-/* Support both device trees and ATAGs. */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-/*#define CONFIG_MACH_TYPE 3589*/
-#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
-
/*
* When we have NAND flash we expect to be making use of mtdparts,
* both for ease of use in U-Boot and for passing information on to
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif /* CONFIG_MTD_RAW_NAND */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x8000000
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_MXC_GPT_HCLK
-#define CONFIG_LOADADDR 0x10700000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* MMC */
#define CONFIG_FSL_USDHC
/* Boot */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_MACH_TYPE 0xFFFFFFFF
/* misc */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Environment */
/* ------------------------------------------------------------------------- */
/* memory */
-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_MACH_TYPE 3589
-
#ifndef CONFIG_SPL_BUILD
/* Default environment */
" bootm ${loadaddr} - ${dtbaddr}\0"
#endif /* !CONFIG_SPL_BUILD*/
-/* Support both device trees and ATAGs. */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
/* SPI Flash */
/* Environment */
#define LCD_BPP LCD_COLOR32
/* memory */
-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_MACH_TYPE 3589
-
#ifndef CONFIG_SPL_BUILD
/* Default environment */
#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default"
-/* Support both device trees and ATAGs. */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
/* Environment */
#endif /* __CONFIG_BRXRE1_H__ */
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000
-#define CONFIG_SYS_I2C_LEGACY
-
#endif /* CONFIG_DM */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif /* !CONFIG_SPL_BUILD, ... */
-/*
- * Our DDR memory always starts at 0x80000000 and U-Boot shall have
- * relocated itself to higher in memory by the time this value is used.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
/*
* ----------------------------------------------------------------------------
* DDR information. We say (for simplicity) that we have 1 bank,
/* I2C Configuration */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_I2C_SPEED 400000
/* EEPROM */
#define EEPROM_I2C_BUS 0 /* I2C0 */
#define EEPROM_I2C_ADDR 0x50
"reset;"
/* Default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x80280000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
/* On CCP board, USDHC1 is for eMMC */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
-
/* SPI */
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80280000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
-/* Serial */
-#define CONFIG_BAUDRATE 115200
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#define CONFIG_SYS_BOOTCOUNT_BE
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
/* NAND: SPL related configs */
/* USB configuration */
#ifndef __CONFIG_CI20_H__
#define __CONFIG_CI20_H__
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* Ingenic JZ4780 clock configuration. */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 1200
/* Memory configuration */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-/* I2C configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define SYS_I2C_BUS_SOM 0
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM
-
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
"echo USB boot attempt ...; run usbbootscript; "
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
/* Machine config */
#define CONFIG_SYS_LITTLE_ENDIAN
-#define CONFIG_MACH_TYPE 4273
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Serial console */
#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* Environment */
"initrd_high=0xffffffff\0" \
"fdt_addr_r=0x18000000\0" \
"ramdisk_addr_r=0x13000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=undefined\0" \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
/* NAND */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* APBH DMA is required for NAND support */
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_MXC_I2C3_SPEED 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 2
-
/* SATA */
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
/* Boot */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-#define CONFIG_SERIAL_TAG
/* misc */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* SPL */
#include "imx6_spl.h"
#define CONFIG_VIDEO_BMP_LOGO
/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
#endif /* __CONFIG_CM_FX6_H */
#ifndef __CONFIG_CM_T335_H
#define __CONFIG_CM_T335_H
-#define CONFIG_CM_T335
-
#include <configs/ti_am335x_common.h>
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
-#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
-
/* Clock Defines */
#define V_OSCK 25000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
/* I2C Configuration */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* SPL */
/* Network. */
/* NAND support */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#undef CONFIG_SYS_NAND_U_BOOT_OFFS
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
#endif
/* Status LED polarity is inversed, so init it in the "off" state */
/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
#ifndef CONFIG_SPL_BUILD
/*
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_CM_T335_H */
-
#ifndef __CONFIG_CM_T43_H
#define __CONFIG_CM_T43_H
-#define CONFIG_CM_T43
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#endif
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
/* CPSW Ethernet support */
#define CONFIG_SYS_RX_ETH_BUFFER 64
-/* USB support */
-#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_AM437X_USB2PHY2_HOST
-
/* Power */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#define CONFIG_HSMMC2_8BIT
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
#endif /* __CONFIG_CM_T43_H */
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
-from which user programs will be started */
-
/*---*/
/*
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define PHYS_SDRAM_SIZE SZ_512M
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
/* ENET1 */
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
-/* I2C configs */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
"fatload ${interface} 0:1 ${loadaddr} " \
"${board}/flash_blk.img && source ${loadaddr}\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
"vidargs=video=mxsfb:640x480M-16@60"
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
#define CONFIG_SYS_NAND_BASE -1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* USB Device Firmware Update support */
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
+#if defined(CONFIG_DM_VIDEO)
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define USDHC2_BASE_ADDR 0x5b020000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80280000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#include "imx6_spl.h"
#endif
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* I2C Configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_MXC_I2C3_SPEED 400000
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
-#define CONFIG_LOADADDR 0x12000000
-
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"vidargs=fbmem=8M\0"
/* Miscellaneous configurable options */
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 48
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#include "mx7_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
-/* I2C configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
"fatload ${interface} 0:1 ${loadaddr} " \
"${board}/flash_blk.img && source ${loadaddr}\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
"updlevel=2\0"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#endif
#define CONFIG_USBD_HS
-#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
+#if defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
/*
* Environment settings
*/
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_BOOTCOMMAND \
"if fatload mmc 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
"bootm 0xc0000;"
#define CONFIG_TIMESTAMP
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
/*
* Serial Console Configuration
*/
/* I2C support */
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
#define CONFIG_SYS_I2C_PXA
#define CONFIG_PXA_STD_I2C
#define CONFIG_PXA_PWR_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
#endif
/* LCD support */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
#define CONFIG_TEGRA_UARTA_SDIO1
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2
-
/* LCD support */
#define CONFIG_LCD_LOGO
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
-
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define DCU_LAYER_MAX_NUM 64
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M)
-
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
-#define CONFIG_LOADADDR 0x80008000
#define CONFIG_FDTADDR 0x84000000
/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical memory map */
#include <configs/bmips_bcm6318.h>
#define CONFIG_REMAKE_ELF
-
#include <configs/bmips_bcm6328.h>
#define CONFIG_REMAKE_ELF
-
#include <configs/bmips_bcm6348.h>
#define CONFIG_REMAKE_ELF
-
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif /* CONFIG_MTD_RAW_NAND */
#include <configs/bmips_bcm6368.h>
#define CONFIG_REMAKE_ELF
-
*/
#define CONFIG_CUSTOMER_BOARD_SUPPORT
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
-#define CONFIG_LOADADDR 1000000
-
/*
* SATA/SCSI/AHCI configuration
*/
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
" gpio clear ${gpio1}; gpio set ${gpio2};" \
" fi; sleep 0.12; done\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
"tftpboot ${bootfile_addr} ${bootfile}; " \
"bootm ${bootfile_addr}"
-#define CONFIG_MMCBOOTCOMMAND \
+#define MMCBOOTCOMMAND \
"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
"console=${consoledev},${baudrate} ${othbootargs}; " \
"ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
#else
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
-#if defined(CONFIG_TARGET_P3041DS)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
-#elif defined(CONFIG_TARGET_P4080DS)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
-#elif defined(CONFIG_TARGET_P5020DS)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
-#elif defined(CONFIG_TARGET_P5040DS)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
-#endif
#endif
#endif
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/*
* DDR Setup
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define PIXIS_LBMAP_ALTBANK 0x40
#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port - controlled on board with jumper J8
* open - index 2
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_FSL
/*
* RapidIO
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#ifdef CONFIG_TARGET_P4080DS
#define __USB_PHY_TYPE ulpi
#else
"fdtfile=p4080ds/p4080ds.dtb\0" \
"bdev=sda3\0"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+#define CONFIG_BOOTCOMMAND HDBOOT
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* DFU class support */
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
-
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_BOOTCOMMAND \
"nand read 0x70000000 0x200000 0x300000;" \
"bootm 0x70000000"
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
- SZ_4M, 0x1000)
-
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
#define CONFIG_SPL_STACK (SZ_16K)
#define CONFIG_SPL_NAND_RAW_ONLY
#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
-#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
/*
* Memory Info
*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SPL_NAND_LOAD
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTCOMMAND \
"run envboot; " \
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
/* SPI */
#endif
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
/* Environment settings */
/* Environment in SD */
#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
*/
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#endif
/* NAND */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
*/
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
/*
* SATA/SCSI/AHCI configuration
*/
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#endif
/* NAND */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/*
* mv-common.h should be defined after CMD configs since it used them
/* Environment in SPI NOR flash */
/* NAND */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
#include <linux/sizes.h>
#include <asm/arch/cpu.h>
-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
-
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
/*
* Memory configurations
*/
-#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
- GENERATED_GBL_DATA_SIZE)
/*
* DMA
*/
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DMA_LPC32XX
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SPEED 100000
/*
* GPIO
#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
-
/*
* USB
*/
* U-Boot Commands
*/
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x80008000
/*
* SPL specific defines
#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
#include <configs/ti_omap3_common.h>
-#define CONFIG_REVISION_TAG 1
-
-/* Size of malloc() pool */
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
/* Hardware drivers */
/* DM9000 */
#define CONFIG_NET_RETRY_COUNT 20
/* Defines for SPL */
/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
/* SPL OS boot options */
/* Miscellaneous configurable options */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
-
/* Bootcounter */
#define CONFIG_SYS_BOOTCOUNT_BE
#define CONFIG_HW_WATCHDOG
#endif
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \
#include "imx6_spl.h"
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
-
#define CONFIG_MXC_UART_BASE UART5_BASE
/* I2C Configs */
#define _CONFIG_DNS325_H
/*
- * Machine number definition
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_DNS325
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#include "mv-common.h"
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
#define CONFIG_SYS_OMAP_ABE_SYSCK
#ifndef CONFIG_SPL_BUILD
/* SPI SPL */
-/* USB xHCI HOST */
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_OMAP_USB2PHY2_HOST
-
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000
/* NAND: SPL related configs */
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#ifndef __CONFIG_DRACO_H
#define __CONFIG_DRACO_H
-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO
-
#include "siemens-am33x-common.h"
#define DDR_PLL_FREQ 303
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define EEPROM_ADDR_DDR3 0x90
-#define EEPROM_ADDR_CHIP 0x120
-
#define CONFIG_FACTORYSET
/* Define own nand partitions */
#define PHYS_SDRAM_1_SIZE SZ_1G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* UART */
"pxefile_addr_r=0x90100000\0"\
BOOTENV
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* Generic Timer Definitions */
"pxefile_addr_r=0x90100000\0"\
BOOTENV
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 64
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
#include "mv-plug-common.h"
#ifndef _CONFIG_DS109_H
#define _CONFIG_DS109_H
-/* Provide the MACH_TYPE value that the vendor kernel requires. */
-#define CONFIG_MACH_TYPE 527
-
/*
* High Level Configuration Options (easy to change)
*/
#ifndef _CONFIG_SYNOLOGY_DS414_H
#define _CONFIG_SYNOLOGY_DS414_H
-/* Vendor kernel expects this MACH_TYPE */
-#define CONFIG_MACH_TYPE 3036
-
/*
* High Level Configuration Options (easy to change)
*/
*/
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-/* DS414 bus width is 32bits */
-#define CONFIG_DDR_32BIT
-
/* Default Environment */
-#define CONFIG_LOADADDR 0x80000
#define CONFIG_BOOTCOMMAND \
"sf probe; " \
"sf read ${loadaddr} 0xd0000 0x2d0000; " \
#define PHYS_SDRAM_1_SIZE 0x7B000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-/* Size of Malloc Pool */
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE)
-
#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000)
/* PCI CONFIG */
/*
* SoC and board defines
*/
-#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */
/*
* RAM
*/
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
/*
* cmd
*/
-#define CONFIG_SYS_LOAD_ADDR 0x80100000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
/*
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR 0x20000
-
/*#define CONFIG_SYS_DRAM_TEST 1 */
#undef CONFIG_SYS_DRAM_TEST
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
* I2C
*/
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0
-
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Memory */
-#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_PHYSMEM
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
/* auto boot */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
/*
* I2C related stuff
*/
#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
#endif
/*
*/
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
-
-/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
/* Enable command line editing */
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* I2C config */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
"fdt_addr_r=0x18000000\0" \
"fdt_addr=0x18000000\0" \
"findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M)
-#define CONFIG_SYS_MALLOC_LEN SZ_64K
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-
/*
* Environment
*/
#define CONFIG_BOOTFILE "app.bin"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_EXTRA_ENV_SETTINGS \
"upgrade_image=u-boot.bin\0" \
"emsdp rom lock\0"
#endif /* _CONFIG_EMSDP_H_ */
-
#include "siemens-am33x-common.h"
/* NAND specific changes for etamin due to different page size */
-#undef CONFIG_SYS_NAND_PAGE_SIZE
-#undef CONFIG_SYS_NAND_OOBSIZE
-#undef CONFIG_SYS_NAND_BLOCK_SIZE
#undef CONFIG_SYS_NAND_ECCPOS
-#undef CONFIG_SYS_NAND_U_BOOT_OFFS
#undef CONFIG_SYS_ENV_SECT_SIZE
-#undef CONFIG_NAND_OMAP_ECCSCHEME
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
-#define CONFIG_SYS_NAND_PAGE_SIZE 4096
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-
#undef CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_MAX_NAND_DEVICE 3
#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define DDR_PLL_FREQ 303
/* FWD Button = 27
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
-
#undef COMMON_ENV_DFU_ARGS
#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \
"setenv bootargs ${bootargs};" \
/* The first stage boot loader expects u-boot running at this address. */
/* The first stage boot loader takes care of low level initialization. */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* Set our official architecture number. */
-#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
/* CPU information */
/* 128MB SDRAM in 1 bank */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* 512kB on-chip NOR flash */
# define CONFIG_SYS_MAX_FLASH_BANKS 1
/* I2C */
#define CONFIG_SYS_MAX_I2C_BUS 1
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-
#define I2C_SOFT_DECLARATIONS
#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
/* File systems */
/* Boot command */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
"sf read 0x22000000 0xc6000 0x294000; " \
"bootm 0x22000000"
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* Memory Info */
-#define CONFIG_SYS_LOAD_ADDR 0x83000000
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* Memory Info */
-#define CONFIG_SYS_LOAD_ADDR 0x83000000
-
#endif /* __CONFIG_H */
#include <linux/sizes.h>
#include <linux/stringify.h>
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-/* Size of malloc() pool before and after relocation */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
-
/* select serial console configuration */
/* PWM */
#define CONFIG_BOARD_COMMON
-#define CONFIG_REVISION_TAG
-
/* SD/MMC configuration */
#define CONFIG_MMC_DEFAULT_DEV 0
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
/* Common environment variables */
-#define CONFIG_EXTRA_ENV_ITB \
+#define ENV_ITB \
"loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
"${kernelname}\0" \
"loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
-/* specific .lds file */
-
-/* Boot Argument Buffer Size */
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
#define CONFIG_RD_LVL
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-/* I2C */
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
-
/* SPI */
/* Ethernet Controllor Driver */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
-
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
#define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_EXYNOS5_DT
-/* Provide the MACH_TYPE value that the vendor kernel requires. */
-#define CONFIG_MACH_TYPE 8002
-
#define CONFIG_VAR_SIZE_SPL
#define CONFIG_IRAM_TOP 0x02074000
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
-/* Size of malloc() pool before and after relocation */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
/* select serial console configuration */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#include "rcar-gen3-common.h"
-/* Generic Interrupt Controller Definitions */
-#ifdef CONFIG_GICV2
-#undef CONFIG_GICV2
+/*
+ * Generic Interrupt Controller Definitions. Undefine v2 locations and define
+ * v3 locations.
+ */
#undef GICD_BASE
#undef GICC_BASE
#undef GICR_BASE
-#endif
-#define CONFIG_GICV3
#define GICD_BASE 0xF1000000
#define GICR_BASE 0xF1060000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration for the flea3 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-
-#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
-
-/* Set TEXT at the beginning of the NOR flash */
-
-/* This is required to setup the ESDC controller */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */
-#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART_BASE UART3_BASE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT 100
-
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "flea3"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc2,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "net_self=if run net_self_load;then " \
- "run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
- "else echo Images not loades;fi\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
- "erase ${uboot_addr} +80000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
-
/* NAND flash */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x7000
#define CONFIG_SPL_STACK 0x308000
#define CONFIG_SYS_MCKR_CSS 0x1302
#define CONFIG_SPL_NAND_RAW_ONLY
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
-
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
#define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
/* Memory usage */
#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
/* TODO: Turn into string option and migrate to Kconfig */
#define CONFIG_HOSTNAME "gazerbeam"
#define CONFIG_ROOTPATH "/opt/nfsroot"
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp ${fdt_addr} $fdtfile;" \
"bootm ${kernel_addr} - ${fdt_addr}"
-#define CONFIG_MMCBOOTCOMMAND \
+#define MMCBOOTCOMMAND \
"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
"console=$consoledev,$baudrate $othbootargs;" \
"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
"bootm ${kernel_addr} - ${fdt_addr}"
-#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
#endif /* __CONFIG_H */
#include "imx6_spl.h"
#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
/* PWM */
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#include "mx6_common.h"
#include <linux/sizes.h>
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#endif
-/* Serial Flash */
-
-#define CONFIG_LOADADDR 0x12000000
-
#ifdef CONFIG_CMD_NFS
#define NETWORKBOOT \
"setnetworkboot=" \
"nfs ${loadaddr} /srv/nfs/fitImage; " \
"bootm ${loadaddr}\0" \
-#define CONFIG_NETWORKBOOTCOMMAND \
+#define NETWORKBOOTCOMMAND \
"run networkboot; " \
#else
"run doboot; " \
"run failbootcmd\0" \
-#define CONFIG_MMCBOOTCOMMAND \
+#define MMCBOOTCOMMAND \
"run doquiet; " \
"run tryboot; " \
#ifdef CONFIG_CMD_NFS
-#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND NETWORKBOOTCOMMAND
#else
-#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
#endif
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Default GPIO configuration and LED status
/* Miscellaneous */
#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_CMDLINE_TAG
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
-#define CONFIG_SYS_LOAD_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-/* Malloc */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* Network interface */
/* SPL */
/* Location in NAND to read U-Boot from */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M)
/* Falcon Mode */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
-#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
-
-/* Serial ATAG */
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
/* Serial */
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_GSC 0
#define CONFIG_I2C_EDID
/*
* PMIC
*/
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#define CONFIG_POWER_LTC3676
#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
-
/* NAND support */
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4)
#define CONFIG_SYS_TIMER_COUNTS_DOWN
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
#define CONFIG_PL011_CLOCK 150000000
#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_SYS_64BIT_LBA
/* Environment data setup
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_INIT_SP_ADDR 0x01000000
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x20000000\0" \
#include <linux/sizes.h>
-#define CONFIG_POWER
#define CONFIG_POWER_HI6553
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 19000000
#define GICD_BASE 0xf6801000
#define GICC_BASE 0xf6802000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-
-#ifdef CONFIG_USB_DWC2
-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
-#endif
-
#define CONFIG_HIKEY_GPIO
/* BOOTP options */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 19000000
#define GICD_BASE 0xe82b1000
#define GICC_BASE 0xe82b2000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#include <config_distro_bootcmd.h>
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
#define CONFIG_SYS_BOOTM_LEN SZ_128M
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* UART configuration
* Environment configuration
*/
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/* Cli configuration */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
#define CONFIG_SYS_BOOTM_LEN SZ_128M
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* UART configuration
* Environment configuration
*/
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/* Cli configuration */
#define CONFIG_SYS_CBSIZE SZ_2K
#include <configs/bmips_bcm6358.h>
#define CONFIG_REMAKE_ELF
-
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#include "mv-common.h"
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Machine type
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
#include "mv-common.h"
*/
#define CONFIG_SYS_NAND_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64
/*
* I2C setup
*/
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
/*
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
/*
* Environment Configuration
#define CONFIG_BOOTFILE "ids8313/uImage"
#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
-#define CONFIG_LOADADDR 0x400000
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
/* Initial Memory map for Linux*/
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_LOADS_ECHO
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTCOMMAND "run boot_cramfs"
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
"run setipargs;run addmtd;" \
"tftp ${loadaddr} ${bootfile};" \
#define __XILFPGA_CONFIG_H
/* BootROM + MIG is pretty smart. DDR and Cache initialized */
-#define CONFIG_SKIP_LOWLEVEL_INIT
/*--------------------------------------------
* CPU configuration
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
/*----------------------------------------------------------------------
* Commands
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
/*
* Lowlevel configuration
*/
/*
* Memory Info
*/
-/* malloc() len */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
/* memtest start address */
#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
#include <linux/stringify.h>
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
/* Total Size of Environment Sector */
/* Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=uImage\0" \
"fit_image=fit.itb\0" \
"fdt_high=0xffffffff\0" \
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#ifdef CONFIG_MX6UL
# define DRAM_OFFSET(x) 0x87##x
# define FDT_ADDR __stringify(DRAM_OFFSET(800000))
-#else
+#else
# define DRAM_OFFSET(x) 0x1##x
# define FDT_ADDR __stringify(DRAM_OFFSET(8000000))
#endif
#ifdef CONFIG_NAND_MXS
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE 0x40000000
-# define CONFIG_SYS_NAND_5_ADDR_CYCLE
-# define CONFIG_SYS_NAND_ONFI_DETECTION
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
/* MTD device */
#endif
# ifdef CONFIG_ENV_IS_IN_NAND
# define CONFIG_SPL_NAND_SUPPORT
# else
-# define CONFIG_SPL_MMC_SUPPORT
+# define CONFIG_SPL_MMC
# endif
# include "imx6_spl.h"
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x14000000\0" \
"ramdisk_addr_r=0x14080000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
/* MTD device */
#endif
/* MMC support */
-#if defined(CONFIG_SPL_MMC_SUPPORT)
+#if defined(CONFIG_SPL_MMC)
#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */
#endif
/* SATA support */
-#if defined(CONFIG_SPL_SATA_SUPPORT)
+#if defined(CONFIG_SPL_SATA)
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
#endif
#include <linux/sizes.h>
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
-
/* Total Size of Environment Sector */
/* Environment */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
#define CONFIG_ETHPRIME "FEC"
#undef CONFIG_SYS_AUTOLOAD
/*
* Use:
- * boot-mode=mix
- * boot-mode=sd
- * boot-mode=net
+ * boot-mode=mix
+ * boot-mode=sd
+ * boot-mode=net
*/
#define MY_CONFIG_BOOT_MODE "boot-mode=sd\0"
#define CONFIG_BOOTCOMMAND "run boot${boot-mode}"
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_SPL_PAD_TO 0x11000
/* MMC support */
-#if defined(CONFIG_SPL_MMC_SUPPORT)
+#if defined(CONFIG_SPL_MMC)
#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */
#endif
#endif
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
"fi;"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* I2C */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* FEC*/
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
"fdt_addr_r=0x43000000\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
BOOTENV
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* I2C */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#endif /* __IMX8MM_ICORE_MX8MM_H */
"scriptaddr=0x46000000\0"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* I2C */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* FEC */
#define CONFIG_ETHPRIME "eth0"
#define CONFIG_FEC_XCV_TYPE RGMII
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_ENV_OVERWRITE
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=Image\0" \
BOOTENV \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"console=ttymxc1,115200\0" \
"fdt_addr_r=0x43000000\0" \
"boot_fit=no\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_SYS_I2C_SPEED 100000
-
#endif
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
-#undef CONFIG_DM_PMIC
-#undef CONFIG_DM_PMIC_PFUZE100
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PCA9450
-#define CONFIG_SYS_I2C_LEGACY
-
#endif
#if defined(CONFIG_CMD_NET)
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
"fdt_addr_r=0x43000000\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
/* Totally 6GB DDR */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_SYS_I2C_SPEED 100000
-
#endif
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
-#undef CONFIG_DM_PMIC
-#undef CONFIG_DM_PMIC_PFUZE100
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#endif
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_MXC_GPIO
-/* I2C Configs */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_OF_SYSTEM_SETUP
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_PMIC
-#endif
-
#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
-#undef CONFIG_DM_PMIC
-#undef CONFIG_DM_PMIC_PFUZE100
-
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#endif
#define CONFIG_REMAKE_ELF
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#define CONFIG_MXC_GPIO
-/* I2C Configs */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_OF_SYSTEM_SETUP
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_PMIC
-#endif
-
#endif
#define USDHC2_BASE_ADDR 0x5B020000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80280000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* FUSE command */
/* Boot M4 */
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80280000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80280000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#endif
-#define CONFIG_SERIAL_TAG
-
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttyLP1,115200 earlycon\0" \
"fdt_addr_r=0x83000000\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x80480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MMCROOT "/dev/mmcblk2p2"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M)
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
-#ifdef CONFIG_SUPPORT_SPL
-#define CONFIG_SYS_LOAD_ADDR 0x20209000
-#else
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-#define CONFIG_LOADADDR 0x80000000
-#endif
-
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
-#ifdef CONFIG_SUPPORT_SPL
-#define CONFIG_SYS_LOAD_ADDR 0x20209000
-#else
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-#define CONFIG_LOADADDR 0x80000000
-#endif
-
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
DMAMEM_SZ_ALL)
#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
*/
#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
/*
* There are various dependencies on the core module (CM) fitted
* image to run at reset/power up
* e.g. whether the ARM Boot Monitor runs before U-Boot
*/
-/* #define CONFIG_SKIP_LOWLEVEL_INIT */
/*
* The ARM boot monitor does not relocate U-Boot.
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for IOT2050
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+#ifndef __CONFIG_IOT2050_H
+#define __CONFIG_IOT2050_H
+
+#include <linux/sizes.h>
+
+/* SPL Loader Configuration */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_IOT2050_BOARD_SETTINGS \
+ "usb_pgood_delay=900\0"
+
+#ifndef CONFIG_SPL_BUILD
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+# define BOOT_TARGET_USB(func) \
+ func(USB, usb, 0) \
+ func(USB, usb, 1) \
+ func(USB, usb, 2)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
+/*
+ * This defines all MMC devices, even if the basic variant has no mmc1.
+ * The non-supported device will be removed from the boot targets during
+ * runtime, when that board was detected.
+ */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ BOOT_TARGET_USB(func)
+
+#include <config_distro_bootcmd.h>
+
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ BOOTENV \
+ EXTRA_ENV_IOT2050_BOARD_SETTINGS
+
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_IOT2050_H */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-#define CONFIG_SYS_MALLOC_LEN SZ_64K
#define CONFIG_SYS_BOOTM_LEN SZ_128K
-#define CONFIG_SYS_LOAD_ADDR SRAM_BASE
#define ROM_BASE CONFIG_SYS_MONITOR_BASE
#define ROM_SIZE SZ_256K
* Environment
*/
#define CONFIG_BOOTFILE "app.bin"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#endif /* _CONFIG_IOT_DEVKIT_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for JetHome devices
+ * Copyright (C) 2021 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef __JETHUB_CONFIG_H
+#define __JETHUB_CONFIG_H
+
+#if defined(CONFIG_MESON_AXG)
+#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \
+ "bootcmd_rescue=" \
+ "if gpio input 10; then " \
+ "run bootcmd_usb0;" \
+ "fi;\0"
+#else
+#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \
+ "bootcmd_rescue=" \
+ "if test \"${userbutton}\" = \"true\"; then " \
+ "run bootcmd_mmc0; " \
+ "fi;\0"
+#endif
+
+#define BOOTENV_DEV_NAME_RESCUE(devtypeu, devtypel, instance) \
+ "rescue "
+
+#ifndef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+ func(RESCUE, rescue, na) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ BOOT_TARGET_DEVICES_USB(func) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#endif
+
+#include <configs/meson64.h>
+
+#endif /* __JETHUB_CONFIG_H */
#include <environment/ti/spi.h>
-/* Platform type */
-#define CONFIG_SOC_K2E
-
#ifdef CONFIG_TI_SECURE_DEVICE
#define DEFAULT_SEC_BOOT_ENV \
DEFAULT_FIT_TI_ARGS \
#endif
/* U-Boot general configuration */
-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+#define ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
-#define CONFIG_DDR_SPD
-
#endif /* __CONFIG_K2E_EVM_H */
#include <environment/ti/mmc.h>
#include <environment/ti/spi.h>
-/* Platform type */
-#define CONFIG_SOC_K2G
-
/* U-Boot general configuration */
-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+#define ENV_KS2_BOARD_SETTINGS \
DEFAULT_MMC_TI_ARGS \
DEFAULT_PMMC_BOOT_ENV \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
#include <environment/ti/spi.h>
-/* Platform type */
-#define CONFIG_SOC_K2HK
-
#ifdef CONFIG_TI_SECURE_DEVICE
#define DEFAULT_SEC_BOOT_ENV \
DEFAULT_FIT_TI_ARGS \
#endif
/* U-Boot general configuration */
-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+#define ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
#define CONFIG_KSNET_NETCP_V1_0
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
-#define CONFIG_DDR_SPD
-
#endif /* __CONFIG_K2HK_EVM_H */
#include <environment/ti/spi.h>
-/* Platform type */
-#define CONFIG_SOC_K2L
-
#ifdef CONFIG_TI_SECURE_DEVICE
#define DEFAULT_SEC_BOOT_ENV \
DEFAULT_FIT_TI_ARGS \
#endif
/* U-Boot general configuration */
-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+#define ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
/*
* System Clock Setup
*/
-#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* ethernet port connected to piggy (UEC2) */
#define CONFIG_HAS_ETH1
/*
* System Clock Setup
*/
-#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* PAXE on the local bus CS3
/*
* Manually set up DDR parameters
*/
-#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
/*
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_NUM_I2C_BUSES 4
#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 200000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 200000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
/* EEprom support 24C08, 24C16, 24C64 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/* Reserve 4 MB for malloc */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Increase max size of compressed kernel */
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
-
#define CONFIG_NAND_ECC_BCH
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-/* Reserve 4 MB for malloc */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
/* Increase max size of compressed kernel */
#define CONFIG_SYS_BOOTM_LEN (32 << 20)
#include "asm/arch/config.h"
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
"bootcountaddr=${bootcountaddr} ${mtdparts}" \
"appended one; fi\0" \
""
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
-
/*
* NAND Flash configuration
*/
* I2C related stuff
*/
#undef CONFIG_I2C_MVTWSI
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
#define I2C_DELAY udelay(1)
#define I2C_SOFT_DECLARATIONS
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-
/* EEprom support 24C128, 24C256 valid for environment eeprom */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* Environment variables configurations
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
#else
-#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_EEPROM_WREN
#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
#endif
"newenv=setenv addr 0x100000 && " \
"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \
"mw.b ${addr} 0 4 && " \
- "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \
" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
- "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \
" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
CONFIG_KM_RESERVED_PRAM) >> 10)
#define CONFIG_SYS_CLK_FREQ 66666666
-/*
- * Take into account default implementation where DDR_FDBK_MULTI is consider as
- * configured for DDR_PLL = 2*MEM_PLL_RAT.
- * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
- */
-#define CONFIG_DDR_CLK_FREQ (100000000 >> 1)
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0x68000000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
| CSOR_NAND_TRHZ_40 \
| CSOR_NAND_BCTLD)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000
/*
* I2C
*/
-#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_MAX_HOPS 1
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DDR_CLK_FREQ 66666666
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
/******************************************************************************
* (PRAM usage)
* ... -------------------------------------------------------
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0xfa000000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
CSOR_NAND_TRHZ_40 | /**/ \
CSOR_NAND_BCTLD) /**/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
/*
* Serial Port - controlled on board with jumper J8
* open - index 2
/*
* System Clock Setup
*/
-#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
#endif
/* DDR */
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM
/* generic timer */
#define COUNTER_FREQUENCY 25000000
-/* size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-
/* early heap for SPL DM */
#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
/* ethernet */
/* environment */
/* see include/configs/ti_armv7_common.h */
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define ENV_MEM_LAYOUT_SETTINGS \
"loadaddr=0x82000000\0" \
"kernel_addr_r=0x82000000\0" \
#define CONFIG_SYS_FSL_CLK
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
/* Command definition */
-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc1,115200\0" \
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#include "imx6_spl.h" /* common IMX6 SPL configuration */
/* Miscellaneous configurable options */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
/* FEC ethernet */
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
#endif
-/* Watchdog */
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \
#define __KZM9G_H
#define CONFIG_SH73A0
-#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
#include <asm/arch/rmobile.h>
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
/* MEMORY */
#define KZM_SDRAM_BASE (0x40000000)
#define PHYS_SDRAM KZM_SDRAM_BASE
#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
#define CONFIG_NFS_TIMEOUT 10000UL
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
-#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
-#define CONFIG_SYS_I2C_SH_SPEED0 100000
-#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
-#define CONFIG_SYS_I2C_SH_SPEED1 100000
-#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
-#define CONFIG_SYS_I2C_SH_SPEED2 100000
-#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
-#define CONFIG_SYS_I2C_SH_SPEED3 100000
-#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
-#define CONFIG_SYS_I2C_SH_SPEED4 100000
-#define CONFIG_SH_I2C_8BIT
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
-
#endif /* __KZM9G_H */
#define _CONFIG_LACIE_KW_H
/*
- * Machine number definition
- */
-#if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2
-#elif defined(CONFIG_NETSPACE_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
-#elif defined(CONFIG_NETSPACE_LITE_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
-#elif defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
-#elif defined(CONFIG_NETSPACE_MAX_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
-#elif defined(CONFIG_D2NET_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
-#elif defined(CONFIG_NET2BIG_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
-#else
-#error "Unknown board"
-#endif
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#else
#define CONFIG_KW88F6281
#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* SDRAM configuration
*/
#ifdef CONFIG_CMD_I2C
/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
#if defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_I2C_G762_ADDR 0x3e
#endif
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory Info
*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/*
* I2C Configuration
*/
-#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SETUP_INITRD_TAG
#define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
-
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
#define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
/* Memory usage */
#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_CBSIZE 512
/* SPL options */
#include "imx6_spl.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
"else run netboot; fi"
/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H
-#define CONFIG_GICV2
-
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h>
#define CONFIG_SYS_CLK_FREQ 125000000
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M)
-
/* PFE */
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000
CONFIG_SYS_SCSI_MAX_LUN)
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
/* GPIO */
#ifdef CONFIG_DM_GPIO
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
#define CONFIG_SYS_HZ 1000
#define CONFIG_HWCONFIG
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* Voltage monitor on channel 2*/
#define CONFIG_SYS_FSL_CLK
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
/*
* DDR: 800 MHz ( 1600 MT/s data rate )
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI \
- board/freescale/ls1021aiot/ls102xa_pbi.cfg
-#endif
-
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_I2C
#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#define CONFIG_SPL_MAX_SIZE 0x1a000
* I2C
*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* MMC
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_CMDLINE_TAG
-
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_DEEP_SLEEP
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_QIXIS_I2C_ACCESS
#else
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-#endif
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
#endif
#ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_SD_BOOT_QSPI
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
-#endif
-
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_SPL_PAD_TO 0x1c000
#endif
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
-
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_SPL_PAD_TO 0x1c000
#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* NAND Flash Definitions
*/
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
/*
/*
* I2C
*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* GPIO */
#ifdef CONFIG_DM_GPIO
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* I2C bus multiplexer
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_CMDLINE_TAG
-
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
/* SPDX-License-Identifier: GPL-2.0
- * Copyright 2016-2019 NXP Semiconductors
+ * Copyright 2016-2019 NXP
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/
#define CONFIG_DEEP_SLEEP
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI \
- "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
-#endif
-
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
-
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
#endif /* ifdef CONFIG_NXP_ESBC */
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* QSPI */
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DEEP_SLEEP
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
-#endif
-
#ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_SD_BOOT_QSPI
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
-#endif
-
#ifdef CONFIG_NXP_ESBC
/*
* HDR would be appended at end of image and copied to DDR along
/*
* I2C
*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* GPIO */
#ifdef CONFIG_DM_GPIO
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* MMC
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_CMDLINE_TAG
-
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-
/* GPIO */
#ifdef CONFIG_DM_GPIO
#ifndef CONFIG_MPC8XXX_GPIO
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#endif
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define I2C_MUX_CH_DEFAULT 0x8
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* DisplayPort */
#define DP_PWD_EN_DEFAULT_MASK 0x8
#include "ls1028a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
/* DDR */
#include "ls1028a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_SYS_RTC_BUS_NUM 0
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV2
#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
/* PCIe */
#ifndef SPL_NO_PCIE
#else
-#ifdef CONFIG_NAND_BOOT
-/* Store Fman ucode at offeset 0x900000(72 blocks). */
-#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SD_BOOT)
+#if defined(CONFIG_SD_BOOT)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 1MB (2040 blocks), Env is stored after the image, and the env size is
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
- "fdt_addr=0x64f00000\0" \
+ "fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_LAYERSCAPE_NS_ACCESS
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
#endif
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
-#endif
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_SD_BOOT_QSPI
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
-#endif
-#endif
-
/* LPUART */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#define CONFIG_SCSI_AHCI_PLAT
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
/*
* NAND Flash Definitions
*/
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
#endif
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_I2C_EARLY_INIT
#endif
/*
* Environment
*/
-#define CONFIG_CMDLINE_TAG
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043AQDS_H__ */
#include "ls1043a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS
#ifndef CONFIG_SPL
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
-#endif
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
-#endif
-
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
/*
* NAND Flash Definitions
*/
-#ifndef SPL_NO_IFC
-#define CONFIG_NAND_FSL_IFC
-#endif
#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
#endif
/* EEPROM */
#ifndef SPL_NO_EEPROM
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#endif
/*
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV2
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_WATCHDOG
#define CONFIG_SPL_I2C
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (36 * (256 * 1024))
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#endif
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#include "ls1046a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS
/*
* NAND Flash Definitions
*/
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
/* IFC Timing Params */
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define I2C_RETIMER_ADDR 0x18
/* I2C bus multiplexer */
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_LAYERSCAPE_NS_ACCESS
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
#endif
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI \
- board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
-#endif
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_SD_BOOT_QSPI
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
-#endif
-#endif
-
/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* IFC Definitions
/*
* NAND Flash Definitions
*/
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#endif
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_I2C_EARLY_INIT
#endif
/*
* Environment
*/
-#define CONFIG_CMDLINE_TAG
-
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
#include "ls1046a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
-#ifdef CONFIG_EMMC_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
-#endif
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
-#define CONFIG_SYS_FSL_PBL_PBI \
- board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_UBOOT_BASE 0x40100000
#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#endif
/*
* NAND Flash Definitions
*/
-#define CONFIG_NAND_FSL_IFC
#endif
#define CONFIG_SYS_NAND_BASE 0x7e800000
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
/*
* CPLD
*/
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define I2C_RETIMER_ADDR 0x18
/* PMIC */
-#define CONFIG_POWER
-#ifdef CONFIG_POWER
-#define CONFIG_POWER_I2C
-#endif
/*
* Environment
/* Link Definitions */
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
*/
#define CPU_RELEASE_ADDR secondary_boot_addr
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-
/* GPIO */
#ifdef CONFIG_DM_GPIO
#ifndef CONFIG_MPC8XXX_GPIO
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#endif
/* Serial Port */
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
/* IFC */
#define CONFIG_FSL_IFC
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* SATA */
#ifdef CONFIG_SCSI
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_TFABOOT
#define SYS_NO_FLASH
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_EARLY_INIT
-#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
#endif
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
#define CONFIG_FSL_QIXIS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-#define CONFIG_DDR_SPD
#ifdef CONFIG_EMU
#define CONFIG_SYS_FSL_DDR_EMU
-#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
-#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
#else
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define SPD_EEPROM_ADDRESS 0x51
#endif
#endif
-#ifndef SPL_NO_IFC
-#define CONFIG_NAND_FSL_IFC
-#endif
-
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
#ifndef SPL_NO_QIXIS
#define CONFIG_FSL_QIXIS
#endif
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#define __LS2_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV3
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
/* Link Definitions */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
*/
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-
/* GPIO */
#ifdef CONFIG_DM_GPIO
#ifndef CONFIG_MPC8XXX_GPIO
#endif
/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#endif
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/* IFC */
#define CONFIG_FSL_IFC
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_EARLY_INIT
-#endif
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#endif
#else
#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
#endif
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_EARLY_INIT
-#endif
#endif
#define I2C_MUX_CH_VOL_MONITOR 0xa
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ 133333333
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(128)) /* Pages Per Block 128*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
FTIM0_NAND_TWP(0x30) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SPL_PAD_TO 0x80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
*/
#if defined(CONFIG_LSCHLV2)
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
-#define CONFIG_MACH_TYPE 3006
#elif defined(CONFIG_LSXHL)
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
-#define CONFIG_MACH_TYPE 2663
#else
#error "unknown board"
#endif
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
#define CONFIG_KIRKWOOD_GPIO
#include "mv-common.h"
/*
* Default environment variables
*/
-#define CONFIG_LOADADDR 0x00800000
#if defined(CONFIG_LSXHL)
#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb"
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_MEMAC
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* DDR */
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* SMP Definitinos */
#define CPU_RELEASE_ADDR secondary_boot_addr
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-
/* Serial Port */
#define CONFIG_PL01X_SERIAL
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
(void *)CONFIG_SYS_SERIAL1, \
(void *)CONFIG_SYS_SERIAL2, \
(void *)CONFIG_SYS_SERIAL3 }
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* MC firmware */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* Qixis */
#define CONFIG_FSL_QIXIS
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_HWCONFIG
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define I2C_EMC2305_PWM 0x80
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
#endif
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
#include <asm/arch/imx-regs.h>
-#define CONFIG_REVISION_TAG
#define CONFIG_SYS_FSL_CLK
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_ETHPRIME "FEC0"
#endif
-/*
- * I2C
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
-#endif
/*
* RTC
/*
* Boot Linux
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTFILE "boot/fitImage"
-#define CONFIG_LOADADDR 0x70800000
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*
* NAND SPL
#define CONFIG_SPL_PAD_TO 0x8000
#define CONFIG_SPL_STACK 0x70004000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/*
* Extra Environments
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
-
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H
+#include <linux/sizes.h>
+
/*
* High Level Configuration Options (easy to change)
*/
*/
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
/* SPI NOR flash default params, used by sf commands */
/* SPL related SPI defines */
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
+#define CONFIG_SYS_SDRAM_SIZE SZ_1G
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
#define PHYS_SDRAM_SIZE SZ_512M
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
/* Misc CPU related */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/*
* Hardware drivers
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
* leaving the correct space for initial global data structure above
#define CONFIG_SYS_CBSIZE 512
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
- 128*1024, 0x1000)
-
#endif
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_MAXARGS 32
-#ifndef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
-#endif
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_INIT_SP_ADDR 0x20000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */
/* ROM USB boot support, auto-execute boot.scr at scriptaddr */
#define BOOT_TARGET_NVME(func)
#endif
+#ifdef CONFIG_CMD_SCSI
+ #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
+#else
+ #define BOOT_TARGET_SCSI(func)
+#endif
+
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
func(MMC, mmc, 2) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_NVME(func) \
+ BOOT_TARGET_SCSI(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#endif
#include <linux/sizes.h>
-#define CONFIG_SYS_MALLOC_LEN SZ_128M
-
#ifndef BOOT_PARTITION
#define BOOT_PARTITION "boot"
#endif
/* setting reset address */
/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
-#define CONFIG_SYS_MALLOC_LEN 0xC0000
-
/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_F_LEN)
#define CONFIG_SYS_CBSIZE 512
/* max number of command args */
#define CONFIG_SYS_MAXARGS 15
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0
#define CONFIG_HOSTNAME "microblaze-generic"
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-
-#define CONFIG_SYS_MALLOC_LEN SZ_8M
-
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x100000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x80010000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_CBSIZE 1024
-/* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/* SPL */
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
#define CONFIG_SYS_CBSIZE SZ_1K
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
/* Uboot definition */
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
GENERATED_GBL_DATA_SIZE)
-/* UBoot -> Kernel */
-#define CONFIG_LOADADDR 0x4007ff28
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#include <linux/sizes.h>
/* Miscellaneous configurable options */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
#define CONFIG_SYS_MAXARGS 8
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
/* Environment */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
GENERATED_GBL_DATA_SIZE)
-/* UBoot -> Kernel */
-#define CONFIG_LOADADDR 0x84000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* MMC */
#define MMC_SUPPORTS_TUNING
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x100000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x80010000
#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
#define CONFIG_SYS_CBSIZE 1024
/* Serial SPL */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
230400, 460800, 921600 }
/* SPL */
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
#include <linux/sizes.h>
/* Miscellaneous configurable options */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
#define CONFIG_SYS_MAXARGS 8
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
/* Environment */
/* UBoot -> Kernel */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000
-#define CONFIG_LOADADDR 0x42007f1c
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#include <linux/sizes.h>
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
-
#define CONFIG_CPU_ARMV8
#define COUNTER_FREQUENCY 13000000
#define COUNTER_FREQUENCY 13000000
-#define CONFIG_SYS_LOAD_ADDR 0x41000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* Uboot definition */
#include <linux/sizes.h>
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
-
#define CONFIG_CPU_ARMV8
#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
-#define CONFIG_SYS_LOAD_ADDR 0x41000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* Uboot definition */
/* auto boot */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */
-
-/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
* High Level Configuration Options (easy to change)
*/
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* mv-common.h should be defined after CMD configs since it used them
4000000, 4500000, 5000000, 5500000, \
6000000 }
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
-
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */
-
-/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LOAD_ADDR 0x06000000 /* default load adr */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
* I2C
*/
#define CONFIG_I2C_MV
-#define CONFIG_SYS_I2C_SLAVE 0x0
/*
* Environment
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
-
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */
-
-/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* When runtime detection fails this is the default */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/*
* Ethernet Driver configuration
#ifndef __CONFIGS_MX23_OLINUXINO_H__
#define __CONFIGS_MX23_OLINUXINO_H__
-/* System configurations */
-#define CONFIG_MACH_TYPE 4105
-
/* U-Boot Commands */
/* Memory configuration */
/* Booting Linux */
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
#ifndef __CONFIGS_MX23EVK_H__
#define __CONFIGS_MX23EVK_H__
-/* System configurations */
-#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK
-
/* U-Boot Commands */
/* Memory configuration */
#endif
/* Framebuffer support */
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
/* Boot Linux */
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Extra Environments */
#define CONFIG_EXTRA_ENV_SETTINGS \
#ifndef __CONFIGS_MX28EVK_H__
#define __CONFIGS_MX28EVK_H__
-/* System configurations */
-#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
-
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
#endif
/* Framebuffer support */
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
/* Boot Linux */
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART_BASE UART1_BASE
/* PMIC Controller */
-#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
#define CONFIG_SYS_FSL_CLK
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
-#define CONFIG_REVISION_TAG
-
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_FPGA_COUNT 1
/* Command definition */
-#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
-
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
#define CONFIG_SYS_FSL_CLK
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-#define CONFIG_REVISION_TAG
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
#define CONFIG_SYS_FSL_CLK
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-#define CONFIG_REVISION_TAG
-
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/* Command definition */
-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
-
#define PPD_CONFIG_NFS \
"nfsserver=192.168.252.95\0" \
"gatewayip=192.168.252.95\0" \
"video-mode=" \
"lcd:800x480-24@60,monitor=lcd\0" \
-#define CONFIG_MMCBOOTCOMMAND \
+#define MMCBOOTCOMMAND \
"run doquiet; " \
"run tryboot; " \
-#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_MAXARGS 48 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
/* Physical Memory Map */
#define CONFIG_SYS_FSL_CLK
-/* ATAGs */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Boot options */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
- defined(CONFIG_MX6SX) || \
- defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
-#define CONFIG_LOADADDR 0x82000000
-#else
-#define CONFIG_LOADADDR 0x12000000
-#endif
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
#include "imx6_spl.h"
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
"fdtfile=undefined\0" \
"fdt_addr_r=0x18000000\0" \
"fdt_addr=0x18000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
"initrd_high=0xffffffff\0" \
#include "mx6_common.h"
#include "imx6_spl.h"
-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
-
#ifdef CONFIG_SERIAL_CONSOLE_UART1
#if defined(CONFIG_MX6SL)
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
"dfu_alt_info=spl raw 0x400\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
#include "imx6_spl.h"
#endif
-#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONSOLE_DEV "ttymxc3"
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#include "imx6_spl.h"
#endif
-#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
#endif
-/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#include "imx6_spl.h"
#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-/* I2C Configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* I2C Configs */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"epdc_waveform=epdc_splash.bin\0" \
"script=boot.scr\0" \
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_EXTRA_ENV_SETTINGS \
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-/* I2C Configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
#include "imx6_spl.h"
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
#ifdef CONFIG_IMX_BOOTAUX
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
-/* I2C Configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* Network */
#define CONFIG_FEC_MXC
#endif
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
/* SPL options */
#include "imx6_spl.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#endif
-/* I2C configs */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_addr=0x83000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#endif
#endif
-/* I2C configs */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
-#define CONFIG_LOADADDR 0x80800000
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
* launched by OPTEE, because of that we shall skip all the low level
* initialization since it was already done by ATF or OPTEE
*/
-#if (CONFIG_OPTEE_TZDRAM_SIZE != 0)
-#ifndef CONFIG_OPTEE
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#endif
#endif
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-/* I2C configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#ifdef CONFIG_IMX_BOOTAUX
"fdtfile=imx7d-sdb.dtb\0" \
"fdt_addr=0x83000000\0" \
"fdt_addr_r=0x83000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x83100000\0" \
"ramdiskaddr=0x83100000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
BOOTENV
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
#endif
#define CONFIG_USBD_HS
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
/* UART */
#define LPUART_BASE LPUART4_RBASE
#define PHYS_SDRAM 0x60000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_LOADADDR 0x60800000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
"console=ttyLP0\0" \
"run mmcboot; " \
"fi; " \
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-/*#define CONFIG_REVISION_TAG*/
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
/* UART */
#define LPUART_BASE LPUART4_RBASE
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 512
#define PHYS_SDRAM_SIZE SZ_1G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_LOADADDR 0x60800000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"fi"
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
#endif
/* Memory sizes */
-#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-/* Booting Linux */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
/*
* Drivers
*/
#endif
#endif
-/* LCD */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
-#endif
-
/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#endif
/* OCOTP */
#define CONFIG_SYS_FSL_USDHC_NUM 1
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define _CONFIG_NAS220_H
/*
- * Machine type ID
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
#define CONFIG_KW88F6192 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/* power-on led, regulator, sata0, sata1 */
#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))
#define CONFIG_KIRKWOOD_GPIO
#endif /* _CONFIG_NAS220_H */
-
#include <configs/bmips_common.h>
#include <configs/bmips_bcm3380.h>
-
#include <configs/bmips_bcm6362.h>
#define CONFIG_REMAKE_ELF
-
#include "mx6_common.h"
-#define CONFIG_MACH_TYPE 3769
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
#define CONFIG_USBD_HS
#define CONFIG_MXC_UART_BASE UART2_BASE
/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_EDID
/* MMC Configs */
#define DISTRO_BOOT_DEV_DHCP(func)
#endif
-
-#if defined(CONFIG_SABRELITE)
-#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
-#else
-/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */
-#define FDTFILE
-#endif
-
#define BOOT_TARGET_DEVICES(func) \
DISTRO_BOOT_DEV_MMC(func) \
DISTRO_BOOT_DEV_SATA(func) \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr_r=0x18000000\0" \
- FDTFILE \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
"ip_dyn=yes\0" \
*/
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
-#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#include <asm/arch/mem.h>
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */
-
-#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */
-#define CONFIG_INITRD_TAG /* enable passing initrd */
-#define CONFIG_REVISION_TAG /* enable passing revision tag*/
-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
-
-/*
- * Size of malloc() pool
- */
#define CONFIG_UBI_SIZE (512 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
- (128 << 10))
/*
* Hardware drivers
"run attachboot;" \
"echo"
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
-
/* SPL */
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#endif
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_SPD_BUS_NUM 0
/* I2C EEPROM */
-#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_BUS 2
-#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
"bootdev=/dev/mmcblk0p1\0" \
"rootdev=/dev/mmcblk0p2\0" \
"netdev=eth0\0" \
- "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
- "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
- "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \
- "ramdisk_addr_r=0x28000000\0" \
+ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+ "pxefile_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+ "scriptaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+ "ramdisk_addr_r=0x28000000\0" \
"fdt_addr_r=0x18000000\0" \
"fdtfile=imx6q-novena.dtb\0" \
"stdout=serial,vidconsole\0" \
#define CONFIG_SYS_FSL_USDHC_NUM 1
-/* Size of malloc() poll */
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
-
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6192 1 /* SOC Name */
#define CONFIG_KW88F6702 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#include "mv-common.h"
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
#define CONFIG_SYS_BOOTM_LEN SZ_32M
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* Environment configuration
*/
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#undef CONFIG_LOADADDR
-#define CONFIG_LOADADDR 0x82408000
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#include "mx6_common.h"
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define __OCTEON_COMMON_H__
#if defined(CONFIG_RAM_OCTEON)
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
#define CONFIG_SYS_INIT_SP_OFFSET 0x20100000
#else
/* No DDR init -> run in L2 cache with limited resources */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
#endif
#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
-
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#endif /* __OCTEON_COMMON_H__ */
/** Stack starting address */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
-/** Heap size for U-Boot */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-
#define CONFIG_LAST_STAGE_INIT
/* Allow environment variable to be overwritten */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
/** Heap size for U-Boot */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
/* Allow environment variable to be overwritten */
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_NAND_OCTEONTX)
/*#define CONFIG_MTD_CONCAT */
#define CONFIG_SYS_MAX_NAND_DEVICE 8
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
#endif /* __OCTEONTX_COMMON_H__ */
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
-#define CONFIG_MACH_TYPE 4289
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL)
#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
#include <linux/sizes.h>
#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot"
*/
#define CONFIG_MISC_COMMON
-#undef CONFIG_REVISION_TAG
-
#endif /* __CONFIG_H */
/* Set soc_rev, soc_id, board_rev, board_name, fdtfile */
#define CONFIG_ODROID_REV_AIN 9
-#define CONFIG_REVISION_TAG
/*
* Need to override existing one (smdk5420) with odroid so set_board_info will
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_MTD_RAW_NAND */
-/* USB EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-
/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS
"${defargs} " \
"${optargs} " \
"root=${ramroot} ramdisk_size=${ramdisk_size} " \
- "rootfstype=${ramrootfstype}\0" \
+ "rootfstype=${ramrootfstype}\0" \
"ramboot=run mmcbootenv; " \
"if run loadimage && run loaddtb && run loadramdisk; then " \
"echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
-#define CONFIG_REVISION_TAG 1
-
/* TPS65950 */
#define PBIASLITEVMODE1 (1 << 8)
#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#endif /* __IGEP00X0_H */
#include <configs/ti_omap3_common.h>
-/*
- * We are only ever GP parts and will utilize all of the "downloaded image"
- * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
- * order to allow for BCH8 to fit in.
- */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Hardware drivers */
-
-/* I2C */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
-
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_USB_EHCI_OMAP
-#endif
-#ifdef CONFIG_USB_EHCI_OMAP
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4
-#endif
-
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \
23, 24, 25, 26, 27, 28, 30, 31, 32, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#endif
#ifndef __CONFIG_PANDA_H
#define __CONFIG_PANDA_H
-/*
- * High Level Configuration Options
- */
-
-/* USB UHH support options */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
-
-/* USB Networking options */
-
-#define CONFIG_UBOOT_ENABLE_PADS_ALL
-
#include <configs/ti_omap4_common.h>
-/* GPIO */
-
-/* ENV related config options */
-
#endif /* __CONFIG_PANDA_H */
/*
* High Level Configuration Options
*/
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP
#include <configs/ti_omap4_common.h>
/* USB UHH support options */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
-#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
-
/* Enabled commands */
/* USB Networking options */
/*
* SoC Configuration
*/
-#define CONFIG_MACH_OMAPL138_LCDK
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Memory Info
*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SPL_NAND_LOAD
#endif
/*
#define CONFIG_BOOTFILE "zImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
/*
* USB Configs
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTCOMMAND \
"run envboot; " \
"run mmcboot; "
/* Environment options */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M)
-#define CONFIG_SYS_LOAD_ADDR 0x87000000
-#define CONFIG_SYS_MALLOC_LEN SZ_256M
#define CONFIG_SYS_BOOTM_LEN SZ_256M
#ifdef CONFIG_SPL
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#include "mv-common.h"
#endif
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
-
/* Miscellaneous configurable options */
#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VIDEO_MXS
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
#endif
"mmcrootfstype=ext4 rootwait\0" \
"kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \
"splashpos=0,0\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \
"check_env=if test -n ${flash_env_version}; " \
"then env default env_version; " \
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
-
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY (24000000) /* 24MHz */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
/* Some commands use this as the default load address */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)
/*
* This is the initial SP which is used only briefly for relocating the u-boot
#if defined(CONFIG_TARGET_P1020RDB_PC)
#define CONFIG_BOARDNAME "P1020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
*/
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_BOARDNAME "P1020RDB-PD"
-#define CONFIG_NAND_FSL_ELBC
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_BOARDNAME "P2020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
#define CONFIG_VSC7385_ENET
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
+#elif defined(CONFIG_SPIFLASH)
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
+#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_NAND_INIT
#else
#define CONFIG_SYS_CLK_FREQ 66666666
#endif
-#define CONFIG_DDR_CLK_FREQ 66666666
#define CONFIG_HWCONFIG
/*
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#else
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-#endif
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
#define CONFIG_SYS_CPLD_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
/* I2C */
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
/*
* I2C2 EEPROM
*/
-#undef CONFIG_ID_EEPROM
#define CONFIG_RTC_PT7C4338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#if defined(CONFIG_PCI)
/*
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#ifdef __SW_BOOT_NOR
#define __NOR_RST_CMD \
norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
__stringify(__NAND_RST_CMD)"\0" \
__stringify(__PCIE_RST_CMD)"\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;" \
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
"bootm $norbootaddr - $norfdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+#define CONFIG_BOOTCOMMAND HDBOOT
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#include "tegra-common-post.h"
#define CONFIG_SYS_FSL_USDHC_NUM 1
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
/* Environment settings */
/* Environment in SD */
#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#include <linux/sizes.h>
#include <linux/stringify.h>
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* Enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M)
-
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_LOADADDR 0x82000000
-
/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_BOARD_SIZE_LIMIT 520192
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Physical memory map */
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
/* Enable NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/* Using 32K of volatile storage for environment */
-#define MACH_TYPE_PDU001 5075
-#define CONFIG_MACH_TYPE MACH_TYPE_PDU001
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#include <configs/ti_am335x_common.h>
-#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X
-
#ifdef CONFIG_MTD_RAW_NAND
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_OS_BOOT
#ifdef CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
#endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */
"fi;"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM SZ_1G
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* I2C */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* ENET1 */
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PCA9450
-#define CONFIG_SYS_I2C_LEGACY
-
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"fi;"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* I2C */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#endif /* __PHYCORE_IMX8MP_H */
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CONFIG_SYS_SDRAM_BASE 0x88000000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */
#define CONFIG_SYS_ENV_ADDR 0x88300000
#define CONFIG_SYS_FDT_ADDR 0x89d00000
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
"run base_boot;" \
"fi; \0" \
"base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
-
#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
/* MMC Configs */
BOOTMENU_ENV \
"fdt_addr=0x83000000\0" \
"fdt_addr_r=0x83000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x83000000\0" \
"ramdiskaddr=0x83000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"mmcautodetect=yes\0" \
CONFIG_DFU_ENV_SETTINGS \
"findfdt=" \
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* I2C configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* environment organization */
/* Environment starts at 768k = 768 * 1024 = 786432 */
/*
*/
#define CONFIG_BOARD_SIZE_LIMIT 715776
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* MMC Config */
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"console=ttymxc4\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \
"fdt_addr=0x83000000\0" \
"fdt_addr_r=0x83000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x83000000\0" \
"ramdiskaddr=0x83000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
CONFIG_DFU_ENV_SETTINGS \
"findfdt=" \
"if test $fdtfile = ask ; then " \
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* I2C configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
-#define CONFIG_SYS_I2C_MXC_I2C2
-#define CONFIG_SYS_I2C_MXC_I2C3
-#define CONFIG_SYS_I2C_MXC_I2C4
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
-#undef CONFIG_DM_PMIC
-
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#endif
#define CONFIG_REMAKE_ELF
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
#define CONFIG_MXC_GPIO
-/* I2C Configs */
-#define CONFIG_SYS_I2C_SPEED 100000
-
#define CONFIG_OF_SYSTEM_SETUP
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_PMIC
-#endif
-
#define CONFIG_SYS_BOOTM_LEN SZ_128M
#endif
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
-
-#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
-
/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL \
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-
/*
* Hardware drivers
*/
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_LOAD_ADDR 0x22000000
-
#undef CONFIG_SYS_USE_DATAFLASH_CS0
#undef CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SYS_USE_FLASH 1
#error "Undefined memory device"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
-
-#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
-
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | \
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-
/*
* Hardware drivers
*/
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#define CONFIG_SYS_USE_FLASH 1
#undef CONFIG_SYS_USE_DATAFLASH
#undef CONFIG_SYS_USE_NANDFLASH
#error "Undefined memory device"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
"bootz 0x72000000 - 0x71000000"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
- 128 * 1024, 0x1000)
-
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#define _CONFIG_POGO_E02_H
/*
- * Machine type definition and ID
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#include "mv-common.h"
/* SYS */
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_INIT_SP_ADDR 0x200000
-#define CONFIG_SYS_LOAD_ADDR 0x800000
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
/* ATF bl33.bin load address (must match) */
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
* does not yet support DT. Thus define it here.
*/
-#define CONFIG_GICV2
#define GICD_BASE 0xf7011000
#define GICC_BASE 0xf7012000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-
#define CONFIG_SYS_TIMER_BASE 0xf4321000
/* Use external clock source */
#define CONFIG_BOOTP_BOOTFILESIZE
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000)
#define CONFIG_LAST_STAGE_INIT
/* SDRAM Bank #1 */
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
- #define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
- #define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
#define SDRAM_BANK_SIZE (2UL << 30)
-#define CONFIG_SERIAL_TAG
-
#endif
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_IRAM_BASE 0xff020000
#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
-#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x4000000
#define __CONFIG_PXA_COMMON_H__
/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400
-#endif
-
-/*
* OHCI USB
*/
#ifdef CONFIG_CMD_USB
#ifndef __CONFIG_PXM2_H
#define __CONFIG_PXM2_H
-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2
-
#include "siemens-am33x-common.h"
#define DDR_IOCTRL_VAL 0x18b
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
#define CONFIG_FACTORYSET
#ifndef CONFIG_SPL_BUILD
/* The DTB generated by QEMU is placed at start of RAM, stay away from there */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-#define CONFIG_SYS_MALLOC_LEN SZ_16M
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_LBA48
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#define CONFIG_BOOTCOMMAND \
"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0"
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-
-#define CONFIG_SYS_MALLOC_LEN SZ_8M
-
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#include <asm/arch/rmobile.h>
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
#ifdef CONFIG_SPL
#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec"
#endif
#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR 0x50000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
/* ENV setting */
/* boot option */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
/* Generic Interrupt Controller Definitions */
-#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
#define DRAM_RSV_SIZE 0x08000000
#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
-#define CONFIG_SYS_LOAD_ADDR 0x58000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* The HF/QSPI layout permits up to 1 MiB large bootloader blob */
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
-#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10081fff
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
#define CONFIG_IRAM_BASE 0x10080000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
-#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#ifndef __CONFIG_RK3188_COMMON_H
#define __CONFIG_RK3188_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_SYS_CBSIZE 1024
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
#endif
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
-#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
-#define CONFIG_SYS_LOAD_ADDR 0x61800800
#define CONFIG_SPL_MAX_SIZE 0x100000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#endif
#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
-#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0xff718000
#define CONFIG_IRAM_BASE 0xff700000
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
#define CONFIG_IRAM_BASE 0xfff80000
#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
-#define CONFIG_SYS_LOAD_ADDR 0x00C00800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
-#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x2000000
#include "rockchip-common.h"
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h>
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
-#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define COUNTER_FREQUENCY 24000000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
-#define CONFIG_SYS_LOAD_ADDR 0x00800800
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
#define CONFIG_SPL_STACK 0x00400000
#include "rockchip-common.h"
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define COUNTER_FREQUENCY 24000000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
#define CONFIG_IRAM_BASE 0xfdcc0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
-#define CONFIG_SYS_LOAD_ADDR 0x00c00800
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SDRAM_BASE 0
#include <asm/arch/base.h>
#endif
-#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
/* Architecture, CPU, etc.*/
/* Use SoC timer for AArch32, but architected timer for AArch64 */
(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
#endif
-/*
- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
- * so 2708 has historically been used rather than a dedicated 2835 ID.
- *
- * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
- * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
- * rather than obtaining a valid ID:-/
- *
- * For the bcm2837, hopefully a machine type is not needed, since everything
- * is DT.
- */
-#ifdef CONFIG_BCM2835
-#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
-#endif
-
/* Memory layout */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
-#define CONFIG_LOADADDR 0x00200000
#ifdef CONFIG_ARM64
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SYS_CBSIZE 1024
/* Environment */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000
/* Shell */
-/* ATAGs support for bootm/bootz */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
/* Environment */
#define ENV_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
#ifndef __CONFIG_RUT_H
#define __CONFIG_RUT_H
-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
-
#include "siemens-am33x-common.h"
#define RUT_IOCTRL_VAL 0x18b
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
-
#define CONFIG_FACTORYSET
/* Watchdog */
#define CONFIG_IRAM_BASE 0x10080000
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
/* TIMER1,initialized by ddr initialize code */
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
/* rockchip ohci host driver */
#define CONFIG_USB_OHCI_NEW
*/
#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
#define BMP_LOAD_ADDR 0x78000000
/* kernel load address */
-#define CONFIG_SYS_LOAD_ADDR 0x71080000
#define INITRD_START 0x79000000
#define KERNEL_DTB_ADDR 0x7A000000
(void *)PHY_BASEADDR_UART1, \
(void *)PHY_BASEADDR_UART2, \
(void *)PHY_BASEADDR_UART3}
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* PLL
/* Text Base */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_INITRD_TAG
-
-/* Size of malloc() pool before and after relocation */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
-
/* MMC */
#define SDHCI_MAX_HOSTS 4
"dfu_alt_info=" CONFIG_DFU_ALT "\0"
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
/* Goni has 3 banks of DRAM, but swap the bank */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
#define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT
",100M(swap)"\
",-(UMS)\0"
-#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
-#define CONFIG_BOOTBLOCK "10"
-#define CONFIG_UBIBLOCK "9"
-
-#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc "
-#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
- "${mtdparts}"
-
-#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"updateb=" \
"onenand erase 0x0 0x100000;" \
"lpj=lpj=3981312\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \
- CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
- CONFIG_ENV_COMMON_BOOT "; run bootk\0" \
+ "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \
+ "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \
+ "${lcdinfo} ${console} ${meminfo}; run bootk\0" \
"tftpboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
- CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
- CONFIG_ENV_COMMON_BOOT \
+ "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \
+ "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \
+ "${lcdinfo} ${console} ${meminfo}" \
"; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \
"nfsboot=" \
"set bootargs root=/dev/nfs rw " \
"nfsroot=${nfsroot},nolock,tcp " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+ "${netmask}:generic:usb0:off ${console} ${meminfo}" \
"; run bootk\0" \
"ramfsboot=" \
"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
"mbrparts=" MBRPARTS_DEFAULT \
"meminfo=crashkernel=32M@0x50000000\0" \
"nfsroot=/nfsroot/arm\0" \
- "bootblock=" CONFIG_BOOTBLOCK "\0" \
- "ubiblock=" CONFIG_UBIBLOCK" \0" \
+ "bootblock=10\0" \
+ "ubiblock=9\0" \
"ubi=enabled\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
"mmcdev=0\0" \
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6338.h>
-
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in sd card */
#define CONFIG_BOOTCOMMAND \
"bootz 0x22000000 - 0x21000000"
#endif
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
-
#endif
#undef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x8000000
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+ (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \
+#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 " \
CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \
- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
- "bootz 0x22000000 - 0x21000000"
+ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \
+ "bootz 0x23000000 - 0x22000000"
#endif
/* SPL */
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* NAND flash */
/* SPI flash */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
#endif /* __CONFIG_H */
#include "at91-sama5_common.h"
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+ (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* SerialFlash */
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \
- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
- "bootz 0x22000000 - 0x21000000"
+#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 at91-sama5d2_xplained.dtb; " \
+ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \
+ "bootz 0x23000000 - 0x22000000"
#elif CONFIG_SPI_BOOT
/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \
- "ext4load mmc 0:1 0x22000000 /boot/zImage; " \
- "bootz 0x22000000 - 0x21000000"
+#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; " \
+ "ext4load mmc 0:1 0x23000000 /boot/zImage; " \
+ "bootz 0x23000000 - 0x22000000"
#endif
#undef CONFIG_BOOTCOMMAND
#define CONFIG_ENV_SPI_BUS 1
#define CONFIG_BOOTCOMMAND "sf probe 1:0; " \
- "sf read 0x21000000 0x180000 0x80000; " \
- "sf read 0x22000000 0x200000 0x600000; "\
- "bootz 0x22000000 - 0x21000000"
+ "sf read 0x22000000 0x180000 0x80000; " \
+ "sf read 0x23000000 0x200000 0x600000; "\
+ "bootz 0x23000000 - 0x22000000"
#endif
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
/* USB */
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
/* Falcon boot support on raw MMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
/* USB */
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
/* SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
/* SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif
GENERATED_GBL_DATA_SIZE)
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x62000000 /* load address */
-
-#undef CONFIG_BOOTCOMMAND
+#ifndef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \
"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \
"bootz 0x62000000 - 0x61000000"
+#else
+#define CONFIG_BOOTCOMMAND "Place your bootcommand here"
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#endif
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50
#define CONFIG_HOST_MAX_DEVICES 4
-/*
- * Size of malloc() pool, before and after relocation
- */
#define CONFIG_MALLOC_F_ADDR 0x0010000
-#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_I2C_EDID
-/* Memory things - we don't really want a memory test */
-#define CONFIG_SYS_LOAD_ADDR 0x00000000
#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
#define CONFIG_PHYSMEM
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
/* NAND support */
#include <configs/bmips_bcm6358.h>
#define CONFIG_REMAKE_ELF
-
#define CONFIG_DMA_COHERENT
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
-#ifdef CONFIG_SIEMENS_MACH_TYPE
-#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE
-#endif
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
/* commands to include */
#ifndef CONFIG_SPL_BUILD
* start addr of ram disk
*/
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-
/* Physical Memory Map */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
/* I2C Configuration */
-#define CONFIG_SYS_I2C_LEGACY
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCSTEPS 4
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#ifndef CONFIG_SPL_BUILD
/*
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-
-#define CONFIG_SYS_MALLOC_LEN SZ_8M
-
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
-
-#define CONFIG_SYS_MALLOC_LEN SZ_8M
-
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
/* Environment options */
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1
-
-#define CONFIG_ID_EEPROM
#endif /* __SIFIVE_UNMATCHED_H */
#include <linux/sizes.h>
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
/* Start just below the second bank so we don't clobber it during reloc */
#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
-#define CONFIG_SYS_MALLOC_LEN SZ_128K
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_SIZE SZ_8M
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
/* misc settings */
-#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
-#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 32
/* setting board specific options */
-#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
#define CONFIG_SYS_AUTOLOAD "yes"
#define CONFIG_RESET_TO_RETRY
* till the beginning of the U-Boot position in RAM.
*/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000)
-
/* NAND flash settings */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
/* BOOTP and DHCP options */
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv autoload yes; setenv autoboot yes; " \
"setenv bootargs ${basicargs} ${mtdparts} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
#define CONFIG_SYS_CBSIZE 512
/*
- * RAM Memory address where to put the
- * Linux Kernel befor starting.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x22000000
-
-/*
* The NAND Flash partitions:
*/
#define CONFIG_ENV_RANGE (SZ_512K)
#define CONFIG_SYS_USE_NANDFLASH 1
#define CONFIG_SPL_NAND_RAW_ONLY
#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_SIZE (SZ_256M)
-#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
-#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
/* Text Base */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- * 1MB = 0x100000, 0x100000 = 1024 * 1024
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
-
/*
* select serial console configuration
*/
* Miscellaneous configurable options
*/
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
#undef CONFIG_BOARD_COMMON
#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
-#undef CONFIG_REVISION_TAG
/* High Level Configuration Options */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
-/* Mach Type */
-#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
-
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* Handling Sleep Mode*/
#define S5P_CHECK_LPA 0xABAD0000
/* MMC SPL */
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define COPY_BL2_FNPTR_ADDR 0x00002488
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
/* SMDKV310 has 4 bank of DRAM */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_SIZE SZ_512M
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
-
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
"run mmcboot; " \
"fi; " \
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
/* CPU */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
#endif
/* I2C - Bit-bashed */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define I2C_INIT do { \
at91_set_gpio_output(AT91_PIN_PA23, 1); \
#define I2C_DELAY udelay(2)
/* Boot options */
-#define CONFIG_SYS_LOAD_ADDR 0x23000000
#define CONFIG_BOOTP_BOOTFILESIZE
/* Console settings */
-/* U-Boot memory settings */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* CPU */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
/* UARTs/Serial console */
/* Boot options */
-#define CONFIG_SYS_LOAD_ADDR 0x23000000
#define CONFIG_BOOTP_BOOTFILESIZE
/* Console settings */
-/* U-Boot memory settings */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-
#endif /* __CONFIG_H */
#include <asm/arch/omap.h>
/*
- * CPU
- */
-
-#define CONFIG_ARM_ARCH_CP15_ERRATA
-
-/*
- * Board
- */
-
-/*
* Clocks
*/
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
-
/*
* I2C
*/
-#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_I2C_MULTI_BUS
/*
"bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
/*
- * ATAGs
- */
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/*
* Boot
*/
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_BOOTCOMMAND \
"setenv boot_mmc_part ${kernel_mmc_part}; " \
"if test reboot-${reboot-mode} = reboot-r; then " \
#include <asm/arch/base_addr_a10.h>
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/*
* U-Boot general configurations
*/
"setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
"saveenv && saveenv && boot;"
-#define CONFIG_CMDLINE_TAG
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* Environment settings */
#define CONFIG_BOOT_RETRY_TIME 45
#define CONFIG_RESET_TO_RETRY
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR
-
/*
* FPGA Remote Update related environment
*
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
-#ifdef CONFIG_SPL_NAND_SUPPORT
-#undef CONFIG_SYS_NAND_U_BOOT_OFFS
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#endif
-
#undef CONFIG_WATCHDOG_TIMEOUT_MSECS
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
* Memory configurations
*/
#define PHYS_SDRAM_1 0x0
-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
#endif
/* SPL SDMMC boot support */
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
/* SPL QSPI boot support */
/* SPL NAND boot support */
-#ifdef CONFIG_SPL_NAND_SUPPORT
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
-#endif
-#endif
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Environment is in MMC */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Booting Linux */
#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Environment is in MMC */
* U-Boot general configurations
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_LOADADDR 0x2000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_REMAKE_ELF
/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
#define CPU_RELEASE_ADDR 0xFFD12210
+ 0x100000)
#endif
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
/*
* U-Boot environment configurations
"socfpga_legacy_reset_compat=1\0"
/*
- * Generic Interrupt Controller Definitions
- */
-#define CONFIG_GICV2
-
-/*
* External memory configurations
*/
#define PHYS_SDRAM_1 0x0
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Ethernet on SoC (EMAC) */
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
/* The PHY is autodetected, so no MII PHY address is needed here */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTCOMMAND "run selboot"
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Extra Environment */
#define CONFIG_HOSTNAME "socfpga_vining_fpga"
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
-#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
/* Hardcoded values, to use instead of SPD */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
/* FPGA and NAND */
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
+#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-
/*
* General PCI
* Memory space is mapped 1-1.
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
-#endif
-
-#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"era fe000000 fe1dffff;" \
"cp.b 100000 fe000000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "update_fdt=tftp 100000 ${fdt_file};" \
+ "update_fdt=tftp 100000 ${fdt_file};" \
"era fe1e0000 fe1fffff;" \
"cp.b 100000 fe1e0000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "update_initrd=tftp 100000 ${initrd_file};" \
+ "update_initrd=tftp 100000 ${initrd_file};" \
"era fe200000 fe9fffff;" \
"cp.b 100000 fe200000 ${filesize};" \
"setenv filesize;saveenv\0" \
"clean_data=era fea00000 fff5ffff\0" \
- "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
- "load_usb=usb start;" \
+ "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
+ "load_usb=usb start;" \
"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
"boot_usb=run load_usb usbargs addcons;" \
"bootm ${kernel_addr_r} - ${fdt_addr};" \
/* SPL options */
#include "imx6_spl.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
* low-level initialization and rely on configuration provided by the Samsung
* bootloader. New images are loaded at the same address for compatibility.
*/
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MALLOC_LEN SZ_2M
/* FIXME: This should be loaded from device tree... */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0xa0412000
-/* Generate initrd atag for downstream kernel (others are copied in stemmy.c) */
-#define CONFIG_INITRD_TAG
+/* Linux does not boot if FDT / initrd is loaded to end of RAM */
+#define BOOT_ENV \
+ "fdt_high=0x6000000\0" \
+ "initrd_high=0x6000000\0"
+
+#define CONSOLE_ENV \
+ "stdin=serial\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#define FASTBOOT_ENV \
+ "fastboot_partition_alias_boot=Kernel\0" \
+ "fastboot_partition_alias_recovery=Kernel2\0" \
+ "fastboot_partition_alias_system=SYSTEM\0" \
+ "fastboot_partition_alias_cache=CACHEFS\0" \
+ "fastboot_partition_alias_hidden=HIDDEN\0" \
+ "fastboot_partition_alias_userdata=DATAFS\0"
+
+#define BOOTCMD_ENV \
+ "fastbootcmd=echo '*** FASTBOOT MODE ***'; fastboot usb 0\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOT_ENV \
+ CONSOLE_ENV \
+ FASTBOOT_ENV \
+ BOOTCMD_ENV
#endif
#define PHYS_SDRAM_1 0x40000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x3E000000
-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */
#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */
*/
#define CONFIG_SYS_BOOTMAPSZ SZ_256M
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_BOOTM_LEN SZ_16M
#define BOOT_TARGET_DEVICES(func) \
/* Extra Commands */
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN 0x1800000
#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN - \
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/* USB Configs */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_LOAD_ADDR 0x90400000
-#define CONFIG_LOADADDR 0x90400000
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MALLOC_LEN (2 << 20)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00400000
-#define CONFIG_LOADADDR 0x00400000
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00400000
-#define CONFIG_LOADADDR 0x00400000
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
-#ifdef CONFIG_SUPPORT_SPL
-#define CONFIG_SYS_LOAD_ADDR 0x08008000
-#else
-#define CONFIG_SYS_LOAD_ADDR 0xC0400000
-#define CONFIG_LOADADDR 0xC0400000
-#endif
-
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
-/*
- * Configuration of the external SDRAM memory
- */
-#define CONFIG_SYS_LOAD_ADDR 0xD0400000
-#define CONFIG_LOADADDR 0xD0400000
-
#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
-/*
- * Configuration of the external SDRAM memory
- */
-#define CONFIG_SYS_LOAD_ADDR 0xD0400000
-#define CONFIG_LOADADDR 0xD0400000
-
#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#define CONFIG_SYS_FLASH_BASE 0x90000000
#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
-/*
- * Configuration of the external SDRAM memory
- */
-#define CONFIG_SYS_LOAD_ADDR 0xC1800000
-#define CONFIG_LOADADDR 0xC1800000
-
#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#define CONFIG_SYS_CBSIZE SZ_1K
/*
- * default load address used for command tftp, bootm , loadb, ...
- */
-#define CONFIG_LOADADDR 0xc2000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_MMC_MAX_DEVICE 3
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Ethernet need */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define LDS_BOARD_TEXT \
board/sysam/stmark2/sbf_dram_init.o (.text*)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
#define CONFIG_SYS_MBAR 0xFC000000
/*
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
#endif
/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x00198000
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
-
/* user interface */
#define CONFIG_SYS_CBSIZE 1024
/* MISC */
-#define CONFIG_SYS_LOAD_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
#define CONFIG_SYS_INIT_SP_OFFSET \
*/
#include <configs/sunxi-common.h>
-#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
-
#endif /* __CONFIG_H */
*/
#include <configs/sunxi-common.h>
-#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
-
#endif /* __CONFIG_H */
*/
#include <configs/sunxi-common.h>
-#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
-
#endif /* __CONFIG_H */
#include <asm/arch/cpu.h>
#include <linux/stringify.h>
-#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
-/*
- * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
- * expense of restricting some features, so the regular machine id values can
- * be used.
- */
-# define CONFIG_MACH_TYPE_COMPAT_REV 0
-#else
-/*
- * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
- * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
- * beyond the machine id check.
- */
-# define CONFIG_MACH_TYPE_COMPAT_REV 1
-#endif
-
#ifdef CONFIG_ARM64
#define CONFIG_SYS_BOOTM_LEN (32 << 20)
#endif
#ifdef CONFIG_MACH_SUN9I
#define SDRAM_OFFSET(x) 0x2##x
#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
#else
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
/* V3s do not have enough memory to place code at 0x4a000000 */
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
#define CONFIG_SYS_64BIT_LBA
#endif
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_SERIAL_TAG
-
#ifdef CONFIG_NAND_SUNXI
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif
#define CONFIG_SYS_MMC_MAX_DEVICE 4
#endif
-#ifndef CONFIG_MACH_SUN8I_V3S
-/* 64MB of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
-#else
-/* 2MB of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
-#endif
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#endif
-
-/* I2C */
-#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
- defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
- defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
-#define CONFIG_SYS_I2C_MVTWSI
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-#endif
-#endif
-
-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
-#define CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
-/* We use pin names in Kconfig and sunxi_name_to_gpio() */
-#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda
-#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl
-#ifndef __ASSEMBLY__
-extern int soft_i2c_gpio_sda;
-extern int soft_i2c_gpio_scl;
-#endif
-#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
-#else
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
-#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
-#endif
-
/* Ethernet support */
#ifdef CONFIG_USB_EHCI_HCD
* Boot info
*/
#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
-#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
/*
* Hardware drivers support
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
-
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 128
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
- 2 * 1024 * 1024)
/*
* DDR related
*/
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-/* EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*
#define CONFIG_SYS_MAXARGS 32 /* max number of command */
/* args */
-/* memtest works on */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
/*
* AM3517 has 12 GP timers, they can be driven by the system clock
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
/* NAND boot config */
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
48, 49, 50, 51, 52, 53, 54, 55,\
56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
/* Setup MTD for NAND on the SOM */
#define TAM3517_READ_EEPROM(info, ret) \
do { \
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
(void *)info, sizeof(*info))) \
ret = 1; \
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
/* SPL related */
#endif
-/* load address */
-#define CONFIG_SYS_LOAD_ADDR 0x22000000
-
/* bootstrap in spi flash , u-boot + env + linux in nandflash */
#ifndef CONFIG_SPL_BUILD
"upgrade_available=0\0"
#endif
#endif /* #ifndef CONFIG_SPL_BUILD */
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE (31 * SZ_512)
#define CONFIG_SYS_USE_NANDFLASH 1
#define CONFIG_SPL_NAND_RAW_ONLY
#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
-#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
-#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_128K
#define CONFIG_SYS_BOOTM_LEN SZ_32M
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* UART configuration
* Environment configuration
*/
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
/* General configuration */
-#define CONFIG_MACH_TYPE 3980
-
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
-
#define CONFIG_SYS_BOOTMAPSZ 0x10000000
/* Serial console */
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* Tag support */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#ifndef __TEGRA_COMMON_POST_H
#define __TEGRA_COMMON_POST_H
-/*
- * Size of malloc() pool
- */
-#ifdef CONFIG_DFU_OVER_USB
-#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \
- CONFIG_SYS_DFU_DATA_BUF_SIZE + \
- CONFIG_SYS_DFU_MAX_FILE_SIZE)
-#else
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-#endif
-
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#ifndef CONFIG_SPL_BUILD
#define BOARD_EXTRA_ENV_SETTINGS
#endif
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
#endif
/* overrides for SPL build here */
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-
-/* remove I2C support */
-#ifdef CONFIG_SYS_I2C_TEGRA
-#undef CONFIG_SYS_I2C_TEGRA
-#endif
-
/* remove USB */
#ifdef CONFIG_USB_EHCI_TEGRA
#undef CONFIG_USB_EHCI_TEGRA
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
#endif
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-
/* Environment */
/*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"
* Physical Memory Map
*/
-/* Generic Interrupt Controller */
-#define CONFIG_GICV2
-
#undef FDTFILE
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_LOADADDR 0x80080000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_LOADADDR 0x01000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x10000000\0" \
"pxefile_addr_r=0x10100000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x03000000\0" \
"ramdisk_addr_r=0x03100000\0"
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif /* _TEGRA20_COMMON_H_ */
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/* Generic Interrupt Controller */
-#define CONFIG_GICV2
-
/*
* Memory layout for where various images get loaded by boot scripts:
*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_LOADADDR 0x80080000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83200000\0"
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"
#ifndef _CONFIG_THEADORABLE_H
#define _CONFIG_THEADORABLE_H
+#include <linux/sizes.h>
+
/*
* High Level Configuration Options (easy to change)
*/
*/
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
+#define CONFIG_SYS_SDRAM_SIZE SZ_2G
#endif /* _CONFIG_THEADORABLE_H */
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_BOOTP_BOOTFILESIZE
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
/* Physical Memory Map */
#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
#include <asm/arch/omap.h>
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
-#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG /* for ramdisk support */
-
/* commands to include */
#define CONFIG_EXTRA_ENV_SETTINGS \
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
-
/**
* Physical Memory Map
*/
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
/* Ethernet */
#define CONFIG_NET_RETRY_COUNT 10
#include <configs/ti_armv7_omap.h>
#include <asm/arch/omap.h>
-#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
-
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
/* NAND: SPL related configs */
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* SPL */
/* Defines for SPL */
/* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
/*
* Disable MMC DM for SPL build and can be re-enabled after adding
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
/*
* When building U-Boot such that there is no previous loader
#ifndef __CONFIG_TI_ARMV7_COMMON_H__
#define __CONFIG_TI_ARMV7_COMMON_H__
-/* Support both device trees and ATAGs. */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Our DDR memory always starts at 0x80000000 and U-Boot shall have
- * relocated itself to higher in memory by the time this value is used.
- * However, set this to a 32MB offset to allow for easier Linux kernel
- * booting as the default is often used as the kernel load address.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
/*
* We setup defaults based on constraints from the Linux kernel, which should
* also be safe elsewhere. We have the default load at 32MB into DDR (for
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* If DM_I2C, enable non-DM I2C support */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#endif
/*
* The following are general good-enough settings for U-Boot. We set a
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
/* As stated above, the following choices are optional. */
#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H
-#define CONFIG_SOC_KEYSTONE
-
/* U-Boot Build Configuration */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
/* SoC Configuration */
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_SGMII_RATESCALE 2
-/* Keyston Navigator Configuration */
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
-#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
-#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
-#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
-#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
-#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
-#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
-#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
-#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
-#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
-#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
-#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
-#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
-#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
-
-/* NETCP pktdma */
-#define CONFIG_KSNAV_PKTDMA_NETCP
-#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
-#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
-#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
-#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
-#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
-#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
-#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
-#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
-#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
-#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
-#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
-
/* Keystone net */
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
-#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
-
/* I2C Configuration */
#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
/* EEPROM definitions */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
/* NAND Configuration */
-#define CONFIG_KEYSTONE_RBL_NAND
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define DFU_ALT_INFO_MMC \
#define CONFIG_TIMESTAMP
/* EDMA3 */
-#define CONFIG_TI_EDMA3
#define KERNEL_MTD_PARTS \
"mtdparts=" \
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
- CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ ENV_KS2_BOARD_SETTINGS \
DFUARGS \
"bootdir=/boot\0" \
"tftp_root=/\0" \
#ifdef CONFIG_SPL_BUILD
/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
-#undef CONFIG_SYS_I2C_LEGACY
#endif
#endif /* __CONFIG_TI_OMAP4_COMMON_H */
#define UART0_BASE 0x7ff80000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 7372800
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR 0x90000000
/* Physical Memory Map */
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_ARM_PL180_MMCI_BASE 0x001c050000
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 12000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0xa0000000
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
* Serial Port
*/
#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {9600, 19200, 38400, 57600, 115200}
#define CONFIG_BOOTCOMMAND \
"dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
/* I2C Configs */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 100000
/* I2C EEPROM (M24C64) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20
#if !defined(CONFIG_DM_PMIC)
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#define TQMA6_PFUZE100_I2C_BUS 2
#define CONFIG_ARP_TIMEOUT 200UL
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M)
-
#if defined(CONFIG_TQMA6X_MMC_BOOT)
#define TQMA6_UBOOT_OFFSET SZ_1K
#define CONFIG_SYS_BOOTCOUNT_BE
/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
#endif /* __CONFIG_TQMA6_WRU4_H */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
-
#define CONFIG_BOOTCOMMAND "run autoboot"
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_BOOTBLOCK "10"
-#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
-
/* Tizen - partitions definitions */
#define PARTS_CSA "csa-mmc"
#define PARTS_BOOT "boot"
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=${nfsroot},nolock,tcp " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+ "${netmask}:generic:usb0:off ${console} ${meminfo}" \
"; run bootk\0" \
"ramfsboot=" \
"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
"console=console=ttySAC2,115200n8\0" \
"meminfo=crashkernel=32M@0x50000000\0" \
"nfsroot=/nfsroot/arm\0" \
- "bootblock=" CONFIG_BOOTBLOCK "\0" \
+ "bootblock=10\0" \
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
"${fdtfile}\0" \
"setenv spl_imgsize;" \
"setenv spl_imgaddr;" \
"setenv spl_addr_tmp;\0" \
- CONFIG_EXTRA_ENV_ITB \
+ ENV_ITB \
"fdtaddr=40800000\0" \
/* Falcon mode definitions */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
#define CONFIG_BOOTCOMMAND "run autoboot"
"setenv spl_imgsize;" \
"setenv spl_imgaddr;" \
"setenv spl_addr_tmp;\0" \
- CONFIG_EXTRA_ENV_ITB \
+ ENV_ITB \
"fdtaddr=40800000\0" \
/* GPT */
#define CONFIG_TEGRA_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
-
/* SPI */
/* Environment in SPI */
4000000, 4500000, 5000000, 5500000, \
6000000 }
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
-
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */
-
-/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
* I2C
*/
#define CONFIG_I2C_MV
-#define CONFIG_SYS_I2C_SLAVE 0x0
/* Environment in SPI NOR flash */
#include "imx6_spl.h"
-/* Provide the MACH_TYPE value that the vendor kernel requires. */
-#define CONFIG_MACH_TYPE 4800
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART2_BASE
/* SATA Configs */
"setenv fdtfile imx6dl-udoo.dtb; fi; " \
"if test ${fdtfile} = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x13000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
#include "imx6_spl.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
"setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
"if test $fdtfile = UNDEFINED; then " \
"echo WARNING: Could not determine dtb to use; fi\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x84000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* I2C configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#define PFUZE3000_I2C_BUS 0
#define BOOTENV
#endif
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_MONITOR_BASE 0
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/*
* Network Configuration
#define CONFIG_GATEWAYIP 192.168.11.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SYS_LOAD_ADDR 0x85000000
#define CONFIG_SYS_BOOTM_LEN (32 << 20)
#if defined(CONFIG_ARM64)
#endif
#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs $bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
/* only for SPL */
#define CONFIG_SPL_STACK (0x00100000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
-
/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40)
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
/*
* Hardware drivers
*/
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif
-#define CONFIG_SYS_LOAD_ADDR 0x22000000
-
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_BOOTCOMMAND "nboot 21000000 0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
#endif
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-
/* Fuse */
#define CONFIG_FSL_IIM
-/* U-Boot memory offsets */
-#define CONFIG_LOADADDR 0x72000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Linux boot */
#define CONFIG_HOSTNAME "usbarmory"
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
#endif /* __CONFIG_H */
/* Onboard devices */
-#define CONFIG_SYS_MALLOC_LEN 0x1F0000
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#include "tegra-common-post.h"
"ramdisk_addr_r=0x46400000\0" \
"scriptaddr=0x46000000\0"
-#define CONFIG_LOADADDR 0x40480000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_SYS_I2C_SPEED 100000
/* ENET */
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif /*_VERDIN_IMX8MM_H */
-
#endif
#endif /* !CONFIG_GICV3 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-
#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111 1
#define CONFIG_BOOTP_BOOTFILESIZE
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
/* Physical Memory Map */
#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef __VEXPRESS_CA9X4_H
+#define __VEXPRESS_CA9X4_H
+
+#define VEXPRESS_ORIGINAL_MEMORY_MAP
+#include "vexpress_common.h"
+
+#endif /* VEXPRESS_CA9X4_H */
* Definitions copied from linux kernel:
* arch/arm/mach-vexpress/include/mach/motherboard.h
*/
-#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#ifdef VEXPRESS_ORIGINAL_MEMORY_MAP
/* CS register bases for the original memory map. */
#define V2M_PA_CS0 0x40000000
#define V2M_PA_CS1 0x44000000
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
-#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
/* Board info register */
#define SYS_ID V2M_SYSREGS
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_L2CACHE_OFF 1
-#define CONFIG_INITRD_TAG 1
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */
#define SCTL_BASE V2M_SYSCTL
#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
/* Physical Memory Map */
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
-#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-#define CONFIG_PLATFORM_ENV_SETTINGS \
- "loadaddr=0x80008000\0" \
- "ramdisk_addr_r=0x61000000\0" \
- "kernel_addr=0x44100000\0" \
- "ramdisk_addr=0x44800000\0" \
- "maxramdisk=0x1800000\0" \
- "pxefile_addr_r=0x88000000\0" \
- "scriptaddr=0x88000000\0" \
- "kernel_addr_r=0x80008000\0"
-#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
-#define CONFIG_PLATFORM_ENV_SETTINGS \
- "loadaddr=0xa0008000\0" \
- "ramdisk_addr_r=0x81000000\0" \
- "kernel_addr=0x0c100000\0" \
- "ramdisk_addr=0x0c800000\0" \
- "maxramdisk=0x1800000\0" \
- "pxefile_addr_r=0xa8000000\0" \
- "scriptaddr=0xa8000000\0" \
- "kernel_addr_r=0xa0008000\0"
-#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_PLATFORM_ENV_SETTINGS \
+ "kernel_addr_r=0x60100000\0" \
+ "fdt_addr_r=0x60000000\0" \
+ "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \
BOOTENV \
"console=ttyAMA0,38400n8\0" \
"dram=1024M\0" \
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_MACH_TYPE 4146
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* Enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_FEC_MXC_PHYADDR 0
/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_SPD_BUS_NUM 0
-
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_BOARD_SIZE_LIMIT 520192
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
/* SerialFlash */
#ifdef CONFIG_CMD_SF
#include "imx6_spl.h"
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
-/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
-
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
/* Memory usage */
#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_CBSIZE 512
#include "imx6_spl.h"
-#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SATA Configs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=undefined\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi; \0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
#include "mx6_common.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
-
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* I2C Configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
#define PHYS_SDRAM_SIZE SZ_512M
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
-
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-/* Switch on SERIAL_TAG */
-#define CONFIG_SERIAL_TAG
-
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
#define BOOT_SCR_STRING "source ${bootscriptaddr}\0"
#endif
-#ifndef CONFIG_OPTEE_LOAD_ADDR
-#define CONFIG_OPTEE_LOAD_ADDR 0
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_DFU_ENV_SETTINGS \
"script=boot.scr\0" \
"fdt_file=imx7s-warp.dtb\0" \
"fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \
"fdtovaddr=0x83100000\0" \
- "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"fi; " \
"fi"
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
*/
#define CONFIG_BOARD_SIZE_LIMIT 785408
-/* I2C configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* environment organization */
#define CONFIG_SYS_FSL_USDHC_NUM 1
#include <asm/arch/cpu.h>
/*
- * Define work_92105 machine type by hand -- done only for compatibility
- * with original board code
- */
-#define CONFIG_MACH_TYPE 736
-
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
* Memory configurations
*/
-#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
-/*
- * I2C driver
- */
-
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_SPEED 350000
-
-/*
- * I2C EEPROM
- */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * I2C RTC
- */
-
#define CONFIG_RTC_DS1374
/*
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_MAX_NAND_CHIPS 1
#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
-#define CONFIG_NAND_LPC32XX_MLC
/*
* GPIO
/*
* Boot Linux
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x80008000
/*
* SPL
/* Use the framework and generic lib */
/* SPL will use serial */
/* SPL will load U-Boot from NAND offset 0x40000 */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
#define CONFIG_SPL_PAD_TO 0x20000
/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
*/
/* NAND */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BBT_CUSTOM_SCAN
#endif
/* NAND */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_SYS_MALLOC_LEN (4 << 20)
#include <asm/arch/config.h>
"fdt_high=0x10000000\0" \
"initrd_high=0x10000000\0"
-#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_UBI_PART user
#define CONFIG_UBIFS_VOLUME user
"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200
-#endif
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_LOAD_ADDR 0x20000000
-
/*-----------------------------------------------------------------------
* CPU Features
*/
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x200000
/*-----------------------------------------------------------------------
* Environment configuration
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_HOSTNAME "x86"
#define CONFIG_BOOTFILE "bzImage"
-#define CONFIG_LOADADDR 0x1000000
#define CONFIG_RAMDISK_ADDR 0x4000000
#if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB)
#define CONFIG_OTHBOOTARGS "othbootargs=\0"
"ramdiskfile=initramfs.gz\0"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftpboot $ramdisk_addr_r $ramdiskfile;" \
"zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
/* Booting Linux */
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Extra Environment */
#define CONFIG_HOSTNAME "xea"
* This can be any arbitrary address as we are using PIE, but
* please note, that CONFIG_SYS_TEXT_BASE must match the below.
*/
-#define CONFIG_SYS_LOAD_ADDR 0x40000000
#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_BOOTP_MAY_FAIL
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR 0x8000000
/* Monitor Command Prompt */
/* Console I/O Buffer Size */
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
-#define CONFIG_GICV2
#define GICD_BASE 0xF9010000
#define GICC_BASE 0xF9020000
# define COUNTER_FREQUENCY 100000000
#endif
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000)
-
/* Serial setup */
#define CONFIG_CPU_ARMV8
#ifdef CONFIG_NAND_ARASAN
# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
#if defined(CONFIG_SPL_BUILD)
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* Undef unneeded configs */
#undef CONFIG_BOOTCOMMAND
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_MALLOC_LEN
#undef CONFIG_SYS_INIT_SP_ADDR
/* BOOTP options */
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x800000
#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
-#define CONFIG_SYS_MALLOC_LEN 0x800000
#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
-#define CONFIG_SYS_MALLOC_LEN 0x1a00
#endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Boot configuration */
-#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_MALLOC_LEN 0x1400000
-
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
/* SPL options */
#include "imx6_spl.h"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
-
#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-/* I2C configs */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
#endif
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */
-
/* Linux boot param area in RAM (used only when booting linux) */
#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10)
#define XTENSA_SYS_TEXT_ADDR \
(MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
-/* Used by tftpboot; env var 'loadaddr' */
-#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000)
-
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*======================*/
/* Ethernet Driver Info */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2011 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * Configuation settings for the zmx25 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_SYS_TIMER_RATE 32768
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
-/*
- * Environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "gs_fast_boot=setenv bootdelay 5\0" \
- "gs_slow_boot=setenv bootdelay 10\0" \
- "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
- "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
- "bootm 0x81000000; bootelf 0x81000000\0"
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Hardware drivers
- */
-
-/*
- * Serial
- */
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x00
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 1
-#define CONFIG_MXC_USB_PORTSC PORT_PTS_SERIAL
-#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/* SDRAM */
-#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xA0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-/*
- * CFI FLASH driver setup
- */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
-
-#endif /* __CONFIG_H */
#ifdef CONFIG_NAND_ZYNQ
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
#ifdef CONFIG_USB_EHCI_ZYNQ
/* enable preboot to be loaded before CONFIG_BOOTDELAY */
/* Boot configuration */
-#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
#ifdef CONFIG_SPL_BUILD
#define BOOTENV
#ifndef __CONFIG_ZYNQ_CSE_H
#define __CONFIG_ZYNQ_CSE_H
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#include <configs/zynq-common.h>
/* Undef unneeded configs */
} else if (likely(((n) >> 32) == 0)) { \
__rem = (u32)(n) % __base; \
(n) = (u32)(n) / __base; \
- } else \
+ } else \
__rem = __div64_32(&(n), __base); \
__rem; \
})
u32 flags_;
#endif
int seq_;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
ofnode node_;
#endif
#ifdef CONFIG_DEVRES
*/
static inline ofnode dev_ofnode(const struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
return dev->node_;
#else
return ofnode_null();
static inline int dev_of_offset(const struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
return ofnode_to_offset(dev_ofnode(dev));
#else
return -1;
static inline bool dev_has_ofnode(const struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
return ofnode_valid(dev_ofnode(dev));
#else
return false;
static inline void dev_set_ofnode(struct udevice *dev, ofnode node)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
dev->node_ = node;
#endif
}
ulong data;
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
#define of_match_ptr(_ptr) (_ptr)
#else
#define of_match_ptr(_ptr) NULL
*
* @parent: Parent device to search
* @uclass_id: Uclass to look for
- * @devp: Returns device found, if any
+ * @devp: Returns device found, if any, else NULL
* @return 0 if found, else -ENODEV
*/
int device_find_first_inactive_child(const struct udevice *parent,
*
* @parent: Parent device to search
* @uclass_id: Uclass to look for
- * @devp: Returns first child device in that uclass, if any
+ * @devp: Returns first child device in that uclass, if any, else NULL
* @return 0 if found, else -ENODEV
*/
int device_find_first_child_by_uclass(const struct udevice *parent,
*/
int ofnode_set_enabled(ofnode node, bool value);
+/**
+ * ofnode_conf_read_bool() - Read a boolean value from the U-Boot config
+ *
+ * This reads a property from the /config node of the devicetree.
+ *
+ * See doc/config.txt for bindings
+ *
+ * @prop_name property name to look up
+ * @return true, if it exists, false if not
+ */
+bool ofnode_conf_read_bool(const char *prop_name);
+
+/**
+ * ofnode_conf_read_int() - Read an integer value from the U-Boot config
+ *
+ * This reads a property from the /config node of the devicetree.
+ *
+ * See doc/config.txt for bindings
+ *
+ * @prop_name: property name to look up
+ * @default_val: default value to return if the property is not found
+ * @return integer value, if found, or @default_val if not
+ */
+int ofnode_conf_read_int(const char *prop_name, int default_val);
+
+/**
+ * ofnode_conf_read_str() - Read a string value from the U-Boot config
+ *
+ * This reads a property from the /config node of the devicetree.
+ *
+ * See doc/config.txt for bindings
+ *
+ * @prop_name: property name to look up
+ * @return string value, if found, or NULL if not
+ */
+const char *ofnode_conf_read_str(const char *prop_name);
+
#endif
};
#endif /* __spi_coldfire_h */
-
UCLASS_FIRMWARE, /* Firmware */
UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
+ UCLASS_HASH, /* Hash device */
UCLASS_HWSPINLOCK, /* Hardware semaphores */
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
* The device returned is probed if necessary, and ready for use
*
* @devp: On entry, pointer to device to lookup. On exit, returns pointer
- * to the next device in the uclass if no error occurred, or -ENODEV if
+ * to the next device in the uclass if no error occurred, or NULL if
* there is no next device.
* @return 0 if found, -ENODEV if not found, other -ve on error
*/
#define CLKID_HIFI_PLL 69
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
-#define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84
+#define CLKID_VPU_0_SEL 92
+#define CLKID_VPU_0 93
+#define CLKID_VPU_1_SEL 95
+#define CLKID_VPU_1 96
+#define CLKID_VPU 97
+#define CLKID_VAPB_0_SEL 99
+#define CLKID_VAPB_0 100
+#define CLKID_VAPB_1_SEL 102
+#define CLKID_VAPB_1 103
+#define CLKID_VAPB_SEL 104
+#define CLKID_VAPB 105
+#define CLKID_VCLK 106
+#define CLKID_VCLK2 107
+#define CLKID_VCLK_DIV1 122
+#define CLKID_VCLK_DIV2 123
+#define CLKID_VCLK_DIV4 124
+#define CLKID_VCLK_DIV6 125
+#define CLKID_VCLK_DIV12 126
+#define CLKID_VCLK2_DIV1 127
+#define CLKID_VCLK2_DIV2 128
+#define CLKID_VCLK2_DIV4 129
+#define CLKID_VCLK2_DIV6 130
+#define CLKID_VCLK2_DIV12 131
+#define CLKID_CTS_ENCL 133
+#define CLKID_VDIN_MEAS 136
#endif /* __AXG_CLKC_H */
#define CLKID_SPICC1_SCLK 261
#define CLKID_NNA_AXI_CLK 264
#define CLKID_NNA_CORE_CLK 267
+#define CLKID_MIPI_DSI_PXCLK_SEL 269
+#define CLKID_MIPI_DSI_PXCLK 270
#endif /* __G12A_CLKC_H */
#define CLK_SGMII_CDR_FB 3
#endif /* _DT_BINDINGS_CLK_MT7622_H */
-
#define UTMI_PHY_INVALID 0xff
#endif /* _COMPHY_DATA_H_ */
-
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * This header provides macros for Atmel Flexcom DT bindings.
+ *
+ * Copyright (C) 2015 Cyrille Pitchen <cyrille.pitchen@atmel.com>
+ */
+
+#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__
+#define __DT_BINDINGS_ATMEL_FLEXCOM_H__
+
+#define ATMEL_FLEXCOM_MODE_USART 1
+#define ATMEL_FLEXCOM_MODE_SPI 2
+#define ATMEL_FLEXCOM_MODE_TWI 3
+
+#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */
*/
#define ARMCLK 0
#define PRCMU_ACLK 1
-#define PRCMU_SVAMMCSPCLK 2
-#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
-#define PRCMU_SIACLK 3
-#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
-#define PRCMU_SGACLK 4
-#define PRCMU_UARTCLK 5
-#define PRCMU_MSP02CLK 6
-#define PRCMU_MSP1CLK 7
-#define PRCMU_I2CCLK 8
-#define PRCMU_SDMMCCLK 9
-#define PRCMU_SLIMCLK 10
-#define PRCMU_CAMCLK 10 /* DBx540 only. */
-#define PRCMU_PER1CLK 11
-#define PRCMU_PER2CLK 12
-#define PRCMU_PER3CLK 13
-#define PRCMU_PER5CLK 14
-#define PRCMU_PER6CLK 15
-#define PRCMU_PER7CLK 16
-#define PRCMU_LCDCLK 17
-#define PRCMU_BMLCLK 18
-#define PRCMU_HSITXCLK 19
-#define PRCMU_HSIRXCLK 20
+#define PRCMU_SVAMMCSPCLK 2
+#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
+#define PRCMU_SIACLK 3
+#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
+#define PRCMU_SGACLK 4
+#define PRCMU_UARTCLK 5
+#define PRCMU_MSP02CLK 6
+#define PRCMU_MSP1CLK 7
+#define PRCMU_I2CCLK 8
+#define PRCMU_SDMMCCLK 9
+#define PRCMU_SLIMCLK 10
+#define PRCMU_CAMCLK 10 /* DBx540 only. */
+#define PRCMU_PER1CLK 11
+#define PRCMU_PER2CLK 12
+#define PRCMU_PER3CLK 13
+#define PRCMU_PER5CLK 14
+#define PRCMU_PER6CLK 15
+#define PRCMU_PER7CLK 16
+#define PRCMU_LCDCLK 17
+#define PRCMU_BMLCLK 18
+#define PRCMU_HSITXCLK 19
+#define PRCMU_HSIRXCLK 20
#define PRCMU_HDMICLK 21
-#define PRCMU_APEATCLK 22
-#define PRCMU_APETRACECLK 23
-#define PRCMU_MCDECLK 24
-#define PRCMU_IPI2CCLK 25
-#define PRCMU_DSIALTCLK 26
-#define PRCMU_DMACLK 27
-#define PRCMU_B2R2CLK 28
-#define PRCMU_TVCLK 29
-#define SPARE_UNIPROCLK 30
-#define PRCMU_SSPCLK 31
-#define PRCMU_RNGCLK 32
-#define PRCMU_UICCCLK 33
+#define PRCMU_APEATCLK 22
+#define PRCMU_APETRACECLK 23
+#define PRCMU_MCDECLK 24
+#define PRCMU_IPI2CCLK 25
+#define PRCMU_DSIALTCLK 26
+#define PRCMU_DMACLK 27
+#define PRCMU_B2R2CLK 28
+#define PRCMU_TVCLK 29
+#define SPARE_UNIPROCLK 30
+#define PRCMU_SSPCLK 31
+#define PRCMU_RNGCLK 32
+#define PRCMU_UICCCLK 33
#define PRCMU_G1CLK 34 /* DBx540 only. */
#define PRCMU_HVACLK 35 /* DBx540 only. */
-#define PRCMU_SPARE1CLK 36
-#define PRCMU_SPARE2CLK 37
+#define PRCMU_SPARE1CLK 36
+#define PRCMU_SPARE2CLK 37
-#define PRCMU_NUM_REG_CLOCKS 38
+#define PRCMU_NUM_REG_CLOCKS 38
-#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
-#define PRCMU_SYSCLK 39
-#define PRCMU_CDCLK 40
-#define PRCMU_TIMCLK 41
-#define PRCMU_PLLSOC0 42
-#define PRCMU_PLLSOC1 43
-#define PRCMU_ARMSS 44
-#define PRCMU_PLLDDR 45
+#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
+#define PRCMU_SYSCLK 39
+#define PRCMU_CDCLK 40
+#define PRCMU_TIMCLK 41
+#define PRCMU_PLLSOC0 42
+#define PRCMU_PLLSOC1 43
+#define PRCMU_ARMSS 44
+#define PRCMU_PLLDDR 45
/* DSI Clocks */
-#define PRCMU_PLLDSI 46
-#define PRCMU_DSI0CLK 47
-#define PRCMU_DSI1CLK 48
-#define PRCMU_DSI0ESCCLK 49
-#define PRCMU_DSI1ESCCLK 50
-#define PRCMU_DSI2ESCCLK 51
+#define PRCMU_PLLDSI 46
+#define PRCMU_DSI0CLK 47
+#define PRCMU_DSI1CLK 48
+#define PRCMU_DSI0ESCCLK 49
+#define PRCMU_DSI1ESCCLK 50
+#define PRCMU_DSI2ESCCLK 51
/* LCD DSI PLL - Ux540 only */
#define PRCMU_PLLDSI_LCD 52
#define PRCMU_DSI1ESCCLK_LCD 56
#define PRCMU_DSI2ESCCLK_LCD 57
-#define PRCMU_NUM_CLKS 58
+#define PRCMU_NUM_CLKS 58
#endif
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * TI DP83867 PHY drivers
+ * Device Tree constants for the Texas Instruments DP83867 PHY
*
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright: (C) 2015 Texas Instruments, Inc.
*/
#ifndef _DT_BINDINGS_TI_DP83867_H
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
/* RGMIIDCTL internal delay for rx and tx */
-#define DP83867_RGMIIDCTL_250_PS 0x0
-#define DP83867_RGMIIDCTL_500_PS 0x1
-#define DP83867_RGMIIDCTL_750_PS 0x2
-#define DP83867_RGMIIDCTL_1_NS 0x3
-#define DP83867_RGMIIDCTL_1_25_NS 0x4
-#define DP83867_RGMIIDCTL_1_50_NS 0x5
-#define DP83867_RGMIIDCTL_1_75_NS 0x6
-#define DP83867_RGMIIDCTL_2_00_NS 0x7
-#define DP83867_RGMIIDCTL_2_25_NS 0x8
-#define DP83867_RGMIIDCTL_2_50_NS 0x9
-#define DP83867_RGMIIDCTL_2_75_NS 0xa
-#define DP83867_RGMIIDCTL_3_00_NS 0xb
-#define DP83867_RGMIIDCTL_3_25_NS 0xc
-#define DP83867_RGMIIDCTL_3_50_NS 0xd
-#define DP83867_RGMIIDCTL_3_75_NS 0xe
-#define DP83867_RGMIIDCTL_4_00_NS 0xf
+#define DP83867_RGMIIDCTL_250_PS 0x0
+#define DP83867_RGMIIDCTL_500_PS 0x1
+#define DP83867_RGMIIDCTL_750_PS 0x2
+#define DP83867_RGMIIDCTL_1_NS 0x3
+#define DP83867_RGMIIDCTL_1_25_NS 0x4
+#define DP83867_RGMIIDCTL_1_50_NS 0x5
+#define DP83867_RGMIIDCTL_1_75_NS 0x6
+#define DP83867_RGMIIDCTL_2_00_NS 0x7
+#define DP83867_RGMIIDCTL_2_25_NS 0x8
+#define DP83867_RGMIIDCTL_2_50_NS 0x9
+#define DP83867_RGMIIDCTL_2_75_NS 0xa
+#define DP83867_RGMIIDCTL_3_00_NS 0xb
+#define DP83867_RGMIIDCTL_3_25_NS 0xc
+#define DP83867_RGMIIDCTL_3_50_NS 0xd
+#define DP83867_RGMIIDCTL_3_75_NS 0xe
+#define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
#define A_DELAY_PS(val) ((val) & 0xffff)
#define G_DELAY_PS(val) ((val) & 0xffff)
#endif
-
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * This header provides constants for TI K3-AM65 pinctrl bindings.
+ * This header provides constants for pinctrl bindings for TI's K3 SoC
+ * family.
*
- * Copyright (C) 2018-2021 Texas Instruments
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
-#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
-
-#define PULL_DISABLE (1 << 16)
-#define PULL_UP (1 << 17)
-#define INPUT_EN (1 << 18)
-#define SLEWCTRL_200MHZ 0
-#define SLEWCTRL_150MHZ (1 << 19)
-#define SLEWCTRL_100MHZ (2 << 19)
-#define SLEWCTRL_50MHZ (3 << 19)
-#define TX_DIS (1 << 21)
-#define ISO_OVR (1 << 22)
-#define ISO_BYPASS (1 << 23)
-#define DS_EN (1 << 24)
-#define DS_INPUT (1 << 25)
-#define DS_FORCE_OUT_HIGH (1 << 26)
-#define DS_PULL_UP_DOWN_EN 0
-#define DS_PULL_UP_DOWN_DIS (1 << 27)
-#define DS_PULL_UP_SEL (1 << 28)
-#define WAKEUP_ENABLE (1 << 29)
-
-#define PIN_OUTPUT (PULL_DISABLE)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN 0
+#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H
+#define _DT_BINDINGS_PINCTRL_TI_K3_H
+
+#define PULLUDEN_SHIFT (16)
+#define PULLTYPESEL_SHIFT (17)
+#define RXACTIVE_SHIFT (18)
+
+#define PULL_DISABLE (1 << PULLUDEN_SHIFT)
+#define PULL_ENABLE (0 << PULLUDEN_SHIFT)
+
+#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE)
+#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
+
+#define INPUT_EN (1 << RXACTIVE_SHIFT)
+#define INPUT_DISABLE (0 << RXACTIVE_SHIFT)
+
+/* Only these macros are expected be used directly in device tree files */
+#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN)
#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (INPUT_EN)
+#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN)
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define OMAP4_UART4_RX 0x11c
#endif
-
#define STM32MP_PKG_AD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
-
#define THERMAL_NO_LIMIT (~0)
#endif
-
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct driver_info;
+/**
+ * struct phandle_0_arg - hold a phandle record with no arguments
+ *
+ * This holds a phandle pointing to another device. See 'Indexes' in the
+ * of-plat-rst documentation.
+ *
+ * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST)
+ * @arg: arguments
+ */
struct phandle_0_arg {
uint idx;
int arg[0];
};
+/**
+ * struct phandle_2_arg - hold a phandle record with up to one argument
+ *
+ * This holds a phandle pointing to another device. See 'Indexes' in the
+ * of-plat-rst documentation.
+ *
+ * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST)
+ * @arg: arguments
+ */
struct phandle_1_arg {
uint idx;
int arg[1];
};
+/**
+ * struct phandle_2_arg - hold a phandle record with up to two arguments
+ *
+ * This holds a phandle pointing to another device. See 'Indexes' in the
+ * of-plat-rst documentation.
+ *
+ * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST)
+ * @arg: arguments
+ */
struct phandle_2_arg {
uint idx;
int arg[2];
#define eeprom_write(dev_addr, offset, buffer, cnt) (-ENOSYS)
#endif
-#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
-# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
-#endif
-
#endif
#ifdef CONFIG_BOOTFILE
"bootfile=" CONFIG_BOOTFILE "\0"
#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
+#ifdef CONFIG_SYS_LOAD_ADDR
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
#if CONFIG_IS_ENABLED(CMD_SF)
#define BOOTENV_SHARED_SF(devtypel) \
- #devtypel "_boot=" \
+ #devtypel "_boot=" \
"if " #devtypel " probe ${busnum}; then " \
- "devtype=" #devtypel "; " \
- "run scan_sf_for_scripts; " \
+ "devtype=" #devtypel "; " \
+ "run scan_sf_for_scripts; " \
"fi\0"
-#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "busnum=" #instance "; " \
+#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "busnum=" #instance "; " \
"run " #devtypel "_boot\0"
-#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \
+#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \
#devtypel #instance " "
#else
#define BOOTENV_SHARED_SF(devtypel)
#else
#define NANDARGS ""
#endif
-
* 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
* Datasheet indicated it starts at bit #21 which was wrong.
* 2. FTPMU010_PDLLCR0_DLLFRAG:
- * Datasheet indicated it has 2 bit which was wrong.
+ * Datasheet indicated it has 2 bit which was wrong.
*/
#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
#ifndef __FDT_SUPPORT_H
#define __FDT_SUPPORT_H
-#ifdef CONFIG_OF_LIBFDT
+#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC)
#include <asm/u-boot.h>
#include <linux/libfdt.h>
* called at the end of the image_setup_libfdt() is to do that convertion.
*/
void ft_board_setup_ex(void *blob, struct bd_info *bd);
-void ft_cpu_setup(void *blob, struct bd_info *bd);
-void ft_pci_setup(void *blob, struct bd_info *bd);
/**
* Add system-specific data to the FDT before booting the OS.
*/
int fdtdec_get_child_count(const void *blob, int node);
-/**
- * Look in the FDT for a config item with the given name and return its value
- * as a 32-bit integer. The property must have at least 4 bytes of data. The
- * value of the first cell is returned.
- *
- * @param blob FDT blob to use
- * @param prop_name Node property name
- * @param default_val default value to return if the property is not found
- * @return integer value, if found, or default_val if not
- */
-int fdtdec_get_config_int(const void *blob, const char *prop_name,
- int default_val);
-
-/**
- * Look in the FDT for a config item with the given name
- * and return whether it exists.
- *
- * @param blob FDT blob
- * @param prop_name property name to look up
- * @return 1, if it exists, or 0 if not
- */
-int fdtdec_get_config_bool(const void *blob, const char *prop_name);
-
-/**
- * Look in the FDT for a config item with the given name and return its value
- * as a string.
- *
- * @param blob FDT blob
- * @param prop_name property name to look up
- * @returns property string, NULL on error.
- */
-char *fdtdec_get_config_string(const void *blob, const char *prop_name);
-
/*
* Look up a property in a node and return its contents in a byte
* array of given length. The property must have at least enough data for
MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\
} while (0)
-
-
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
do { \
#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
-#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
QE_RISC_ALLOCATION_RISC2)
#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
QE_RISC_ALLOCATION_RISC2 | \
#define WCR_WDE 0x04
#define WCR_WDT 0x08
#define WCR_SRS 0x10
-#define WCR_WDA 0x20
+#define WCR_WDA 0x20
#define SET_WCR_WT(x) (x << 8)
#define WCR_WT_MSK SET_WCR_WT(0xFF)
* generic_phy_configure() - configure a PHY device
*
* @phy: PHY port to be configured
- * @params: PHY Parameters, underlying data is specific to the PHY function
+ * @params: PHY Parameters, underlying data is specific to the PHY function
* @return 0 if OK, or a negative error code
*/
int generic_phy_configure(struct phy *phy, void *params);
* gzwrite_progress_finish called at end of loop to
* indicate success (retcode=0) or failure
*/
-void gzwrite_progress_init(u64 expected_size);
+void gzwrite_progress_init(ulong expected_size);
-void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes);
+void gzwrite_progress(int iteration, ulong bytes_written, ulong total_bytes);
-void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize,
+void gzwrite_progress_finish(int retcode, ulong totalwritten, ulong totalsize,
u32 expected_crc, u32 calculated_crc);
/**
* @return 0 if OK, -1 on error
*/
int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf,
- u64 startoffs, u64 szexpected);
+ ulong startoffs, ulong szexpected);
/**
* gzip()- Compress data into a buffer using the gzip algorithm
#ifndef _HASH_H
#define _HASH_H
+#ifdef USE_HOSTCC
+#include <linux/kconfig.h>
+#endif
+
struct cmd_tbl;
/*
* Maximum digest size for all algorithms we support. Having this value
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
*/
-#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#if CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512)
#define HASH_MAX_DIGEST_SIZE 64
#else
#define HASH_MAX_DIGEST_SIZE 32
*/
int acpi_i2c_of_to_plat(struct udevice *dev);
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
+
#if !CONFIG_IS_ENABLED(DM_I2C)
/*
#endif
/*
- * Many boards/controllers/drivers don't support an I2C slave interface so
- * provide a default slave address for them for use in common code. A real
- * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
- * support a slave interface.
- */
-#ifndef CONFIG_SYS_I2C_SLAVE
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-#endif
-
-/*
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
*/
-#ifdef CONFIG_SYS_I2C_EARLY_INIT
-void i2c_early_init_f(void);
-#endif
void i2c_init(int speed, int slaveaddr);
void i2c_init_board(void);
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/*
* i2c_get_bus_num:
*
* only for backwardcompatibility, should go away if we switched
* completely to new multibus support.
*/
-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
# if !defined(CONFIG_SYS_MAX_I2C_BUS)
# define CONFIG_SYS_MAX_I2C_BUS 2
# endif
#define STATUS_IBF (1 << 1)
/* Configuration byte bit defines */
-#define CONFIG_KIRQ_EN (1 << 0)
-#define CONFIG_MIRQ_EN (1 << 1)
-#define CONFIG_SET_BIST (1 << 2)
-#define CONFIG_KCLK_DIS (1 << 4)
-#define CONFIG_MCLK_DIS (1 << 5)
-#define CONFIG_AT_TRANS (1 << 6)
+#define CFG_KIRQ_EN (1 << 0)
+#define CFG_MIRQ_EN (1 << 1)
+#define CFG_SET_BIST (1 << 2)
+#define CFG_KCLK_DIS (1 << 4)
+#define CFG_MCLK_DIS (1 << 5)
+#define CFG_AT_TRANS (1 << 6)
/* i8042 commands */
#define CMD_RD_CONFIG 0x20 /* read configuration byte */
#ifdef USE_HOSTCC
#include <sys/types.h>
+#include <linux/kconfig.h>
-/* new uImage format support enabled on host */
-#define IMAGE_ENABLE_FIT 1
-#define IMAGE_ENABLE_OF_LIBFDT 1
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-#define CONFIG_FIT_RSASSA_PSS 1
-#define CONFIG_MD5
-#define CONFIG_SHA1
-#define CONFIG_SHA256
-#define CONFIG_SHA384
-#define CONFIG_SHA512
-
-#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
#else
#include <command.h>
#include <linker_lists.h>
-/* Take notice of the 'ignore' property for hashes */
-#define IMAGE_ENABLE_IGNORE 1
#define IMAGE_INDENT_STRING " "
-#define IMAGE_ENABLE_FIT CONFIG_IS_ENABLED(FIT)
-#define IMAGE_ENABLE_OF_LIBFDT CONFIG_IS_ENABLED(OF_LIBFDT)
-
#endif /* USE_HOSTCC */
-#if IMAGE_ENABLE_FIT
#include <hash.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
-#endif /* IMAGE_ENABLE_FIT */
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-# define IMAGE_BOOT_GET_CMDLINE 1
-#else
-# define IMAGE_BOOT_GET_CMDLINE 0
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-# define IMAGE_OF_BOARD_SETUP 1
-#else
-# define IMAGE_OF_BOARD_SETUP 0
-#endif
-
-#ifdef CONFIG_OF_SYSTEM_SETUP
-# define IMAGE_OF_SYSTEM_SETUP 1
-#else
-# define IMAGE_OF_SYSTEM_SETUP 0
-#endif
+#include <u-boot/hash-checksum.h>
extern ulong image_load_addr; /* Default Load Address */
extern ulong image_save_addr; /* Default Save Address */
image_header_t legacy_hdr_os_copy; /* header copy */
ulong legacy_hdr_valid;
-#if IMAGE_ENABLE_FIT
+ /*
+ * The fit_ members are only used with FIT, but it involves a lot of
+ * #ifdefs to avoid compiling that code. Since FIT is the standard
+ * format, even for SPL, this extra data size seems worth it.
+ */
const char *fit_uname_cfg; /* configuration node unit name */
void *fit_hdr_os; /* os FIT image header */
void *fit_hdr_setup; /* x86 setup FIT image header */
const char *fit_uname_setup; /* x86 setup subimage node name */
int fit_noffset_setup;/* x86 setup subimage node offset */
-#endif
#ifndef USE_HOSTCC
image_info_t os; /* os image info */
int genimg_get_comp_id(const char *name);
void genimg_print_size(uint32_t size);
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
- defined(USE_HOSTCC)
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
#define IMAGE_ENABLE_TIMESTAMP 1
#else
#define IMAGE_ENABLE_TIMESTAMP 0
int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start,
ulong *setup_len);
-#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
-#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
-#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
*/
int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong *const ld_len);
-#endif /* !USE_HOSTCC */
int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
ulong *setup_start, ulong *setup_len);
*/
int image_source_script(ulong addr, const char *fit_uname);
-#ifndef USE_HOSTCC
/**
* fit_get_node_from_config() - Look up an image a FIT by type
*
int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
ulong *initrd_start, ulong *initrd_end);
int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
-#ifdef CONFIG_SYS_BOOT_GET_KBD
int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd);
-#endif /* CONFIG_SYS_BOOT_GET_KBD */
-#endif /* !USE_HOSTCC */
/*******************************************************************/
/* Legacy format specific code (prefixed with image_) */
}
static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
{
-#ifndef USE_HOSTCC
/* Let's assume that sandbox can load any architecture */
- if (IS_ENABLED(CONFIG_SANDBOX))
+ if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX))
return true;
-#endif
return (image_get_arch(hdr) == arch) ||
(image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
}
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
-#if IMAGE_ENABLE_FIT
/* cmdline argument format parsing */
int fit_parse_conf(const char *spec, ulong addr_curr,
ulong *addr, const char **conf_name);
int fit_check_ramdisk(const void *fit, int os_noffset,
uint8_t arch, int verify);
-#endif /* IMAGE_ENABLE_FIT */
int calculate_hash(const void *data, int data_len, const char *algo,
uint8_t *value, int *value_len);
# define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE)
#endif
-#if IMAGE_ENABLE_FIT
#ifdef USE_HOSTCC
void *image_get_host_blob(void);
void image_set_host_blob(void *host_blob);
# define gd_fdt_blob() (gd->fdt_blob)
#endif
-#endif /* IMAGE_ENABLE_FIT */
-
/*
* Information passed to the signing routines
*
int size;
};
-#if FIT_IMAGE_ENABLE_VERIFY
-# include <u-boot/hash-checksum.h>
-#endif
struct checksum_algo {
const char *name;
const int checksum_len;
const EVP_MD *(*calculate_sign)(void);
#endif
int (*calculate)(const char *name,
- const struct image_region region[],
+ const struct image_region *region,
int region_count, uint8_t *checksum);
};
*/
struct padding_algo *image_get_padding_algo(const char *name);
-#if IMAGE_ENABLE_FIT
-
/**
* fit_image_verify_required_sigs() - Verify signatures marked as 'required'
*
struct cipher_algo *image_get_cipher_algo(const char *full_name);
-#ifdef CONFIG_FIT_VERBOSE
-#define fit_unsupported(msg) printf("! %s:%d " \
- "FIT images not supported for '%s'\n", \
- __FILE__, __LINE__, (msg))
-
-#define fit_unsupported_reset(msg) printf("! %s:%d " \
- "FIT images not supported for '%s' " \
- "- must reset board to recover!\n", \
- __FILE__, __LINE__, (msg))
-#else
-#define fit_unsupported(msg)
-#define fit_unsupported_reset(msg)
-#endif /* CONFIG_FIT_VERBOSE */
-#endif /* CONFIG_FIT */
-
-#if !defined(USE_HOSTCC)
-#if defined(CONFIG_ANDROID_BOOT_IMAGE)
struct andr_img_hdr;
int android_image_check_header(const struct andr_img_hdr *hdr);
int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
ulong android_image_get_kload(const struct andr_img_hdr *hdr);
ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
void android_print_contents(const struct andr_img_hdr *hdr);
-#if !defined(CONFIG_SPL_BUILD)
bool android_image_print_dtb_contents(ulong hdr_addr);
-#endif
-
-#endif /* CONFIG_ANDROID_BOOT_IMAGE */
-#endif /* !USE_HOSTCC */
/**
* board_fit_config_name_match() - Check for a matching board name
} flash_header_v1_t;
typedef struct {
- uint32_t length; /* Length of data to be read from flash */
+ uint32_t length; /* Length of data to be read from flash */
} flash_cfg_parms_t;
typedef struct {
*/
int irq_read_and_clear(struct irq *irq);
+struct phandle_2_arg;
+/**
+ * irq_get_by_phandle() - Get an irq by its phandle information (of-platadata)
+ *
+ * This function is used when of-platdata is enabled.
+ *
+ * This looks up an irq using the phandle info. With dtoc, each phandle in the
+ * 'interrupts-extended ' property is transformed into an idx representing the
+ * device. For example:
+ *
+ * interrupts-extended = <&acpi_gpe 0x3c 0>;
+ *
+ * might result in:
+ *
+ * .interrupts_extended = {6, {0x3c, 0}},},
+ *
+ * indicating that the irq is udevice idx 6 in dt-plat.c with a arguments of
+ * 0x3c and 0.This function can return a valid irq given the above
+ * information. In this example it would return an irq containing the
+ * 'acpi_gpe' device and the irq ID 0x3c.
+ *
+ * @dev: Device containing the phandle
+ * @cells: Phandle info
+ * @irq: A pointer to a irq struct to initialise
+ * @return 0 if OK, or a negative error code
+ */
+int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells,
+ struct irq *irq);
+
/**
* irq_get_by_index - Get/request an irq by integer index.
*
#define APM_16_BIT_SUPPORT 0x0001
#define APM_32_BIT_SUPPORT 0x0002
#define APM_IDLE_SLOWS_CLOCK 0x0004
-#define APM_BIOS_DISABLED 0x0008
+#define APM_BIOS_DISABLED 0x0008
#define APM_BIOS_DISENGAGED 0x0010
/*
/*
* We can't declare function 'inline' because __no_sanitize_address confilcts
* with inlining. Attempt to inline it may cause a build failure.
- * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
* '__maybe_unused' allows us to avoid defined-but-not-used warnings.
*/
# define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2)
#define IORESOURCE_IRQ_LOWLEVEL (1<<3)
#define IORESOURCE_IRQ_SHAREABLE (1<<4)
-#define IORESOURCE_IRQ_OPTIONAL (1<<5)
+#define IORESOURCE_IRQ_OPTIONAL (1<<5)
/* PnP DMA specific bits (IORESOURCE_BITS) */
#define IORESOURCE_DMA_TYPE_MASK (3<<0)
(config_enabled(option))
/*
- * U-Boot add-on: Helper macros to reference to different macros
- * (CONFIG_ or CONFIG_SPL_ prefixed), depending on the build context.
+ * U-Boot add-on: Helper macros to reference to different macros (prefixed by
+ * CONFIG_, CONFIG_SPL_, CONFIG_TPL_ or CONFIG_TOOLS_), depending on the build
+ * context.
*/
-#if defined(CONFIG_TPL_BUILD)
+#ifdef USE_HOSTCC
+#define _CONFIG_PREFIX TOOLS_
+#elif defined(CONFIG_TPL_BUILD)
#define _CONFIG_PREFIX TPL_
#elif defined(CONFIG_SPL_BUILD)
#define _CONFIG_PREFIX SPL_
/*
* CONFIG_VAL(FOO) evaluates to the value of
+ * CONFIG_TOOLS_FOO if USE_HOSTCC is defined,
* CONFIG_FOO if CONFIG_SPL_BUILD is undefined,
* CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
* CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined.
/*
* CONFIG_IS_ENABLED(FOO) expands to
+ * 1 if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* 0 otherwise.
*
* CONFIG_IS_ENABLED(FOO, (abc)) expands to
+ * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* nothing otherwise.
*
* CONFIG_IS_ENABLED(FOO, (abc), (def)) expands to
+ * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* Continue to iterate over list of given type, continuing after
* the current position.
*/
-#define list_for_each_entry_continue(pos, head, member) \
+#define list_for_each_entry_continue(pos, head, member) \
for (pos = list_entry(pos->member.next, typeof(*pos), member); \
prefetch(pos->member.next), &pos->member != (head); \
pos = list_entry(pos->member.next, typeof(*pos), member))
* Iterate over list of given type, continuing after current point,
* safe against removal of list entry.
*/
-#define list_for_each_entry_safe_continue(pos, n, head, member) \
+#define list_for_each_entry_safe_continue(pos, n, head, member) \
for (pos = list_entry(pos->member.next, typeof(*pos), member), \
n = list_entry(pos->member.next, typeof(*pos), member); \
&pos->member != (head); \
#ifndef __LINUX_MTD_BBM_H
#define __LINUX_MTD_BBM_H
-/* The maximum number of NAND chips in an array */
-#ifndef CONFIG_SYS_NAND_MAX_CHIPS
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#endif
-
/**
* struct nand_bbt_descr - bad block table descriptor
* @options: options for this descriptor
#define DoC_Mplus_Configuration 0x100a
#define DoC_Mplus_OutputControl 0x100c
#define DoC_Mplus_FlashControl 0x1020
-#define DoC_Mplus_FlashSelect 0x1022
+#define DoC_Mplus_FlashSelect 0x1022
#define DoC_Mplus_FlashCmd 0x1024
#define DoC_Mplus_FlashAddress 0x1026
#define DoC_Mplus_FlashData0 0x1028
#define DoC_Mplus_ReadPipeInit 0x102a
#define DoC_Mplus_LastDataRead 0x102c
#define DoC_Mplus_LastDataRead1 0x102d
-#define DoC_Mplus_WritePipeTerm 0x102e
+#define DoC_Mplus_WritePipeTerm 0x102e
#define DoC_Mplus_ECCSyndrome0 0x1040
#define DoC_Mplus_ECCSyndrome1 0x1041
#define DoC_Mplus_ECCSyndrome2 0x1042
#define DoC_Mplus_ECCSyndrome3 0x1043
#define DoC_Mplus_ECCSyndrome4 0x1044
#define DoC_Mplus_ECCSyndrome5 0x1045
-#define DoC_Mplus_ECCConf 0x1046
+#define DoC_Mplus_ECCConf 0x1046
#define DoC_Mplus_Toggle 0x1046
#define DoC_Mplus_DownloadStatus 0x1074
#define DoC_Mplus_CtrlConfirm 0x1076
} flstate_t;
-
/* NOTE: confusingly, this can be used to refer to more than one chip at a time,
if they're interleaved. This can even refer to individual partitions on
the same physical chip when present. */
* For each partition, these fields are available:
* name: string that will be used to label the partition's MTD device.
* size: the partition size; if defined as MTDPART_SIZ_FULL, the partition
- * will extend to the end of the master MTD device.
+ * will extend to the end of the master MTD device.
* offset: absolute starting position within the master MTD device; if
- * defined as MTDPART_OFS_APPEND, the partition will start where the
+ * defined as MTDPART_OFS_APPEND, the partition will start where the
* previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block;
* if MTDPART_OFS_RETAIN, consume as much as possible, leaving size
* after the end of partition.
* mask_flags: contains flags that have to be masked (removed) from the
- * master MTD flag set for the corresponding MTD partition.
- * For example, to force a read-only partition, simply adding
- * MTD_WRITEABLE to the mask_flags will do the trick.
+ * master MTD flag set for the corresponding MTD partition.
+ * For example, to force a read-only partition, simply adding
+ * MTD_WRITEABLE to the mask_flags will do the trick.
*
* Note: writeable partitions require their size and offset be
* erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK).
int jedec_version;
struct nand_onfi_params onfi_params;
struct nand_jedec_params jedec_params;
-
+
struct nand_data_interface *data_interface;
int read_retries;
} __attribute__((packed));
#define VIDEO_TYPE_MDA 0x10 /* Monochrome Text Display */
-#define VIDEO_TYPE_CGA 0x11 /* CGA Display */
+#define VIDEO_TYPE_CGA 0x11 /* CGA Display */
#define VIDEO_TYPE_EGAM 0x20 /* EGA/VGA in Monochrome Mode */
#define VIDEO_TYPE_EGAC 0x21 /* EGA in Color Mode */
#define VIDEO_TYPE_VGAC 0x22 /* VGA+ in Color Mode */
#define ORIG_X (screen_info.orig_x)
#define ORIG_Y (screen_info.orig_y)
#define ORIG_VIDEO_MODE (screen_info.orig_video_mode)
-#define ORIG_VIDEO_COLS (screen_info.orig_video_cols)
+#define ORIG_VIDEO_COLS (screen_info.orig_video_cols)
#define ORIG_VIDEO_EGA_BX (screen_info.orig_video_ega_bx)
#define ORIG_VIDEO_LINES (screen_info.orig_video_lines)
#define ORIG_VIDEO_ISVGA (screen_info.orig_video_isVGA)
* include/linux/serial_reg.h
*
* Copyright (C) 1992, 1994 by Theodore Ts'o.
- *
+ *
* These are the UART port assignments, expressed as offsets from the base
* register. These assignments should hold for any serial port based on
* a 8250, 16450, or 16550(A).
#define UART_LCR 3 /* Out: Line Control Register */
/*
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
*/
#define UART_ASR 0x01 /* Additional Status Register */
#define UART_RFL 0x03 /* Receiver FIFO level */
-#define UART_TFL 0x04 /* Transmitter FIFO level */
+#define UART_TFL 0x04 /* Transmitter FIFO level */
#define UART_ICR 0x05 /* Index Control Register */
/* The 16950 ICR registers */
#define UART_ACR_ASREN 0x80 /* Additional status enable */
-
/*
* These definitions are for the RSA-DV II/S card, from
*
#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
#endif /* _LINUX_SERIAL_REG_H */
-
void *memchr_inv(const void *, int, size_t);
#endif
+/**
+ * memdup() - allocate a buffer and copy in the contents
+ *
+ * Note that this returns a valid pointer even if @len is 0
+ *
+ * @src: data to copy in
+ * @len: number of bytes to copy
+ * @return allocated buffer with the copied contents, or NULL if not enough
+ * memory is available
+ *
+ */
+char *memdup(const void *src, size_t len);
+
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
* endpoint. It's set once by UDC driver when endpoint is initialized, and
* should not be changed. Should not be confused with maxpacket.
* @max_streams: The maximum number of streams supported
- * by this EP (0 - 16, actual number is 2^n)
+ * by this EP (0 - 16, actual number is 2^n)
* @maxburst: the maximum number of bursts supported by this EP (for usb3)
* @driver_data:for use by the gadget driver. all other fields are
* read-only to gadget drivers.
* @desc: endpoint descriptor. This pointer is set before the endpoint is
- * enabled and remains valid until the endpoint is disabled.
+ * enabled and remains valid until the endpoint is disabled.
* @comp_desc: In case of SuperSpeed support, this is the endpoint companion
- * descriptor that is used to configure the endpoint
+ * descriptor that is used to configure the endpoint
*
* the bus controller driver lists all the general purpose endpoints in
* gadget->ep_list. the control endpoint (gadget->ep0) is not in that list,
size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart,
size_t blockSize);
+struct abuf;
+
+/**
+ * zstd_decompress() - Decompress Zstandard data
+ *
+ * @in: Input buffer to decompress
+ * @out: Output buffer to hold the results (must be large enough)
+ * @return size of the decompressed data, or -ve on error
+ */
+int zstd_decompress(struct abuf *in, struct abuf *out);
+
#endif /* ZSTD_H */
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
+void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align);
/* Low level functions */
#define VIOLOEN (1 << 6)
#define VIOLOSTBY (1 << 7)
#define VIOLOMODE (1 << 8)
-#define VDIGEN (1 << 9)
+#define VDIGEN (1 << 9)
#define VDIGSTBY (1 << 10)
#define VDIGMODE (1 << 11)
#define VGENEN (1 << 12)
#endif /* !CONFIG_MPC83XX_SDRAM */
/*
- * CONFIG_ADDRESS - PCI Config Address Register
+ * PCI_CONFIG_ADDRESS - PCI Config Address Register
*/
#define PCI_CONFIG_ADDRESS_EN 0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
#endif
#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
#endif
#endif /* __MPC85xx_H__ */
#define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode)
#define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme
#define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read)
-#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default
+#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default
/* OTP mode selection */
#define MTD_OTP_OFF 0
/*
* to facilitate the definition, the following macros are provided
*
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0)
#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0)
*/
#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#include <asm/cache.h>
#include <nand.h>
#include <asm/mach-imx/dma.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
int nand_mtd_to_devnum(struct mtd_info *mtd);
void board_nand_init(void);
int nand_register(int devnum, struct mtd_info *mtd);
#else
+struct nand_chip;
+
extern int board_nand_init(struct nand_chip *nand);
#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
#ifndef __DSA_H__
/**
* struct dsa_ops - DSA operations
*
- * @port_enable: Initialize a switch port for I/O.
+ * @port_probe: Initialize a switch port.
+ * @port_enable: Enable I/O for a port.
* @port_disable: Disable I/O for a port.
* @xmit: Insert the DSA tag for transmission.
* DSA drivers receive a copy of the packet with headroom and
* master including any additional headers.
*/
struct dsa_ops {
+ int (*port_probe)(struct udevice *dev, int port,
+ struct phy_device *phy);
int (*port_enable)(struct udevice *dev, int port,
struct phy_device *phy);
void (*port_disable)(struct udevice *dev, int port,
int cpu_eth_init(struct bd_info *bis);
/* Driver initialization prototypes */
-int at91emac_register(struct bd_info *bis, unsigned long iobase);
int ax88180_initialize(struct bd_info *bis);
int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num);
int bfin_EMAC_initialize(struct bd_info *bis);
#define OS_SEEK_END 2
/**
+ * os_filesize() - Calculate the size of a file
+ *
+ * @fd: File descriptor as returned by os_open()
+ * Return: file size or negative error code
+ */
+int os_filesize(int fd);
+
+/**
* Access to the OS open() system call
*
* @pathname: Pathname of file to open
*/
int os_read_file(const char *name, void **bufp, int *sizep);
+/**
+ * os_map_file() - Map a file from the host filesystem into memory
+ *
+ * This can be useful when to provide a backing store for an emulated device
+ *
+ * @pathname: File pathname to map
+ * @os_flags: Flags, like OS_O_RDONLY, OS_O_RDWR
+ * @bufp: Returns buffer containing the file
+ * @sizep: Returns size of data
+ * Return: 0 if OK, -ve on error
+ */
+int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep);
+
/*
* os_find_text_base() - Find the text section in this running process
*
char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */
#endif
#ifdef CONFIG_DOS_PARTITION
- uchar sys_ind; /* partition type */
+ uchar sys_ind; /* partition type */
#endif
};
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_RTCTL 28 /* Root Control */
+#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
+#define PCI_EXP_RTCAP 30 /* Root Capabilities */
+#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
*/
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
pci_addr_t *bar, bool supports_64bit);
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
#if defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
extern struct pci_controller *pci_get_hose_head(void);
-extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
{
return interface == PHY_INTERFACE_MODE_XGMII ||
interface == PHY_INTERFACE_MODE_USXGMII ||
- interface == PHY_INTERFACE_MODE_XFI;
+ interface == PHY_INTERFACE_MODE_10GBASER;
}
#endif
}
/* PHY UIDs for various PHYs that are referenced in external code */
-#define PHY_UID_CS4340 0x13e51002
-#define PHY_UID_CS4223 0x03e57003
+#define PHY_UID_CS4340 0x13e51002
+#define PHY_UID_CS4223 0x03e57003
#define PHY_UID_TN2020 0x00a19410
#define PHY_UID_IN112525_S03 0x02107440
PHY_INTERFACE_MODE_CAUI2,
PHY_INTERFACE_MODE_CAUI4,
PHY_INTERFACE_MODE_NCSI,
- PHY_INTERFACE_MODE_XFI,
+ PHY_INTERFACE_MODE_10GBASER,
PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_NONE, /* Must be last */
[PHY_INTERFACE_MODE_CAUI2] = "caui2",
[PHY_INTERFACE_MODE_CAUI4] = "caui4",
[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
- [PHY_INTERFACE_MODE_XFI] = "xfi",
+ [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
[PHY_INTERFACE_MODE_NONE] = "",
};
*
* @return 0 if OK, or a negative error code.
*/
-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
- CONFIG_IS_ENABLED(POWER_DOMAIN)
+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(POWER_DOMAIN)
int dev_power_domain_on(struct udevice *dev);
#else
static inline int dev_power_domain_on(struct udevice *dev)
*
* @return 0 if OK, or a negative error code.
*/
-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
- CONFIG_IS_ENABLED(POWER_DOMAIN)
+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(POWER_DOMAIN)
int dev_power_domain_off(struct udevice *dev);
#else
static inline int dev_power_domain_off(struct udevice *dev)
OPMODE_ON,
};
-#ifdef CONFIG_POWER
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
enum { PMIC_I2C, PMIC_SPI, PMIC_NONE};
-#ifdef CONFIG_POWER
+/* TODO: Change to !CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
enum { I2C_PMIC, I2C_NUM, };
enum { PMIC_READ, PMIC_WRITE, };
enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, };
struct pmic *parent;
struct list_head list;
};
-#endif /* CONFIG_POWER */
+#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */
+/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */
#ifdef CONFIG_DM_PMIC
/**
* U-Boot PMIC Framework
uint trans_len;
};
-#endif /* CONFIG_DM_PMIC */
+#endif /* DM_PMIC */
-#ifdef CONFIG_POWER
+/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+
+/* Legacy API, do not use */
int pmic_init(unsigned char bus);
int power_init_board(void);
int pmic_dialog_init(unsigned char bus);
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val);
int pmic_reg_write(struct pmic *p, u32 reg, u32 val);
int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on);
-#endif
+#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */
#define pmic_i2c_addr (p->hw.i2c.addr)
#define pmic_i2c_tx_num (p->hw.i2c.tx_num)
+++ /dev/null
-#ifndef _RADEON_H
-#define _RADEON_H
-
-
-#define RADEON_REGSIZE 0x4000
-
-
-#define MM_INDEX 0x0000
-#define MM_DATA 0x0004
-#define BUS_CNTL 0x0030
-#define HI_STAT 0x004C
-#define BUS_CNTL1 0x0034
-#define I2C_CNTL_1 0x0094
-#define CONFIG_CNTL 0x00E0
-#define CONFIG_MEMSIZE 0x00F8
-#define CONFIG_APER_0_BASE 0x0100
-#define CONFIG_APER_1_BASE 0x0104
-#define CONFIG_APER_SIZE 0x0108
-#define CONFIG_REG_1_BASE 0x010C
-#define CONFIG_REG_APER_SIZE 0x0110
-#define PAD_AGPINPUT_DELAY 0x0164
-#define PAD_CTLR_STRENGTH 0x0168
-#define PAD_CTLR_UPDATE 0x016C
-#define PAD_CTLR_MISC 0x0aa0
-#define AGP_CNTL 0x0174
-#define BM_STATUS 0x0160
-#define CAP0_TRIG_CNTL 0x0950
-#define CAP1_TRIG_CNTL 0x09c0
-#define VIPH_CONTROL 0x0C40
-#define VENDOR_ID 0x0F00
-#define DEVICE_ID 0x0F02
-#define COMMAND 0x0F04
-#define STATUS 0x0F06
-#define REVISION_ID 0x0F08
-#define REGPROG_INF 0x0F09
-#define SUB_CLASS 0x0F0A
-#define BASE_CODE 0x0F0B
-#define CACHE_LINE 0x0F0C
-#define LATENCY 0x0F0D
-#define HEADER 0x0F0E
-#define BIST 0x0F0F
-#define REG_MEM_BASE 0x0F10
-#define REG_IO_BASE 0x0F14
-#define REG_REG_BASE 0x0F18
-#define ADAPTER_ID 0x0F2C
-#define BIOS_ROM 0x0F30
-#define CAPABILITIES_PTR 0x0F34
-#define INTERRUPT_LINE 0x0F3C
-#define INTERRUPT_PIN 0x0F3D
-#define MIN_GRANT 0x0F3E
-#define MAX_LATENCY 0x0F3F
-#define ADAPTER_ID_W 0x0F4C
-#define PMI_CAP_ID 0x0F50
-#define PMI_NXT_CAP_PTR 0x0F51
-#define PMI_PMC_REG 0x0F52
-#define PM_STATUS 0x0F54
-#define PMI_DATA 0x0F57
-#define AGP_CAP_ID 0x0F58
-#define AGP_STATUS 0x0F5C
-#define AGP_COMMAND 0x0F60
-#define AIC_CTRL 0x01D0
-#define AIC_STAT 0x01D4
-#define AIC_PT_BASE 0x01D8
-#define AIC_LO_ADDR 0x01DC
-#define AIC_HI_ADDR 0x01E0
-#define AIC_TLB_ADDR 0x01E4
-#define AIC_TLB_DATA 0x01E8
-#define DAC_CNTL 0x0058
-#define DAC_CNTL2 0x007c
-#define CRTC_GEN_CNTL 0x0050
-#define MEM_CNTL 0x0140
-#define MC_CNTL 0x0140
-#define EXT_MEM_CNTL 0x0144
-#define MC_TIMING_CNTL 0x0144
-#define MC_AGP_LOCATION 0x014C
-#define MEM_IO_CNTL_A0 0x0178
-#define MEM_REFRESH_CNTL 0x0178
-#define MEM_INIT_LATENCY_TIMER 0x0154
-#define MC_INIT_GFX_LAT_TIMER 0x0154
-#define MEM_SDRAM_MODE_REG 0x0158
-#define AGP_BASE 0x0170
-#define MEM_IO_CNTL_A1 0x017C
-#define MC_READ_CNTL_AB 0x017C
-#define MEM_IO_CNTL_B0 0x0180
-#define MC_INIT_MISC_LAT_TIMER 0x0180
-#define MEM_IO_CNTL_B1 0x0184
-#define MC_IOPAD_CNTL 0x0184
-#define MC_DEBUG 0x0188
-#define MC_STATUS 0x0150
-#define MEM_IO_OE_CNTL 0x018C
-#define MC_CHIP_IO_OE_CNTL_AB 0x018C
-#define MC_FB_LOCATION 0x0148
-/* #define MC_FB_LOCATION 0x0188 */
-#define HOST_PATH_CNTL 0x0130
-#define MEM_VGA_WP_SEL 0x0038
-#define MEM_VGA_RP_SEL 0x003C
-#define HDP_DEBUG 0x0138
-#define SW_SEMAPHORE 0x013C
-#define CRTC2_GEN_CNTL 0x03f8
-#define CRTC2_DISPLAY_BASE_ADDR 0x033c
-#define SURFACE_CNTL 0x0B00
-#define SURFACE0_LOWER_BOUND 0x0B04
-#define SURFACE1_LOWER_BOUND 0x0B14
-#define SURFACE2_LOWER_BOUND 0x0B24
-#define SURFACE3_LOWER_BOUND 0x0B34
-#define SURFACE4_LOWER_BOUND 0x0B44
-#define SURFACE5_LOWER_BOUND 0x0B54
-#define SURFACE6_LOWER_BOUND 0x0B64
-#define SURFACE7_LOWER_BOUND 0x0B74
-#define SURFACE0_UPPER_BOUND 0x0B08
-#define SURFACE1_UPPER_BOUND 0x0B18
-#define SURFACE2_UPPER_BOUND 0x0B28
-#define SURFACE3_UPPER_BOUND 0x0B38
-#define SURFACE4_UPPER_BOUND 0x0B48
-#define SURFACE5_UPPER_BOUND 0x0B58
-#define SURFACE6_UPPER_BOUND 0x0B68
-#define SURFACE7_UPPER_BOUND 0x0B78
-#define SURFACE0_INFO 0x0B0C
-#define SURFACE1_INFO 0x0B1C
-#define SURFACE2_INFO 0x0B2C
-#define SURFACE3_INFO 0x0B3C
-#define SURFACE4_INFO 0x0B4C
-#define SURFACE5_INFO 0x0B5C
-#define SURFACE6_INFO 0x0B6C
-#define SURFACE7_INFO 0x0B7C
-#define SURFACE_ACCESS_FLAGS 0x0BF8
-#define SURFACE_ACCESS_CLR 0x0BFC
-#define GEN_INT_CNTL 0x0040
-#define GEN_INT_STATUS 0x0044
-#define CRTC_EXT_CNTL 0x0054
-#define RB3D_CNTL 0x1C3C
-#define WAIT_UNTIL 0x1720
-#define ISYNC_CNTL 0x1724
-#define RBBM_GUICNTL 0x172C
-#define RBBM_STATUS 0x0E40
-#define RBBM_STATUS_alt_1 0x1740
-#define RBBM_CNTL 0x00EC
-#define RBBM_CNTL_alt_1 0x0E44
-#define RBBM_SOFT_RESET 0x00F0
-#define RBBM_SOFT_RESET_alt_1 0x0E48
-#define NQWAIT_UNTIL 0x0E50
-#define RBBM_DEBUG 0x0E6C
-#define RBBM_CMDFIFO_ADDR 0x0E70
-#define RBBM_CMDFIFO_DATAL 0x0E74
-#define RBBM_CMDFIFO_DATAH 0x0E78
-#define RBBM_CMDFIFO_STAT 0x0E7C
-#define CRTC_STATUS 0x005C
-#define GPIO_VGA_DDC 0x0060
-#define GPIO_DVI_DDC 0x0064
-#define GPIO_MONID 0x0068
-#define GPIO_CRT2_DDC 0x006c
-#define PALETTE_INDEX 0x00B0
-#define PALETTE_DATA 0x00B4
-#define PALETTE_30_DATA 0x00B8
-#define CRTC_H_TOTAL_DISP 0x0200
-#define CRTC_H_SYNC_STRT_WID 0x0204
-#define CRTC_H_SYNC_POL (1 << 23)
-#define CRTC_V_TOTAL_DISP 0x0208
-#define CRTC_V_SYNC_STRT_WID 0x020C
-#define CRTC_V_SYNC_POL (1 << 23)
-#define CRTC_VLINE_CRNT_VLINE 0x0210
-#define CRTC_CRNT_FRAME 0x0214
-#define CRTC_GUI_TRIG_VLINE 0x0218
-#define CRTC_DEBUG 0x021C
-#define CRTC_OFFSET_RIGHT 0x0220
-#define CRTC_OFFSET 0x0224
-#define CRTC_OFFSET_CNTL 0x0228
-#define CRTC_PITCH 0x022C
-#define OVR_CLR 0x0230
-#define OVR_WID_LEFT_RIGHT 0x0234
-#define OVR_WID_TOP_BOTTOM 0x0238
-#define DISPLAY_BASE_ADDR 0x023C
-#define SNAPSHOT_VH_COUNTS 0x0240
-#define SNAPSHOT_F_COUNT 0x0244
-#define N_VIF_COUNT 0x0248
-#define SNAPSHOT_VIF_COUNT 0x024C
-#define FP_CRTC_H_TOTAL_DISP 0x0250
-#define FP_CRTC_V_TOTAL_DISP 0x0254
-#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
-#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
-#define CUR_OFFSET 0x0260
-#define CUR_HORZ_VERT_POSN 0x0264
-#define CUR_HORZ_VERT_OFF 0x0268
-#define CUR_CLR0 0x026C
-#define CUR_CLR1 0x0270
-#define FP_HORZ_VERT_ACTIVE 0x0278
-#define CRTC_MORE_CNTL 0x027C
-#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
-#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
-#define DAC_EXT_CNTL 0x0280
-#define FP_GEN_CNTL 0x0284
-#define FP_HORZ_STRETCH 0x028C
-#define FP_VERT_STRETCH 0x0290
-#define FP_H_SYNC_STRT_WID 0x02C4
-#define FP_V_SYNC_STRT_WID 0x02C8
-#define AUX_WINDOW_HORZ_CNTL 0x02D8
-#define AUX_WINDOW_VERT_CNTL 0x02DC
-/* #define DDA_CONFIG 0x02e0 */
-/* #define DDA_ON_OFF 0x02e4 */
-#define DVI_I2C_CNTL_1 0x02e4
-#define GRPH_BUFFER_CNTL 0x02F0
-#define GRPH2_BUFFER_CNTL 0x03F0
-#define VGA_BUFFER_CNTL 0x02F4
-#define OV0_Y_X_START 0x0400
-#define OV0_Y_X_END 0x0404
-#define OV0_PIPELINE_CNTL 0x0408
-#define OV0_REG_LOAD_CNTL 0x0410
-#define OV0_SCALE_CNTL 0x0420
-#define OV0_V_INC 0x0424
-#define OV0_P1_V_ACCUM_INIT 0x0428
-#define OV0_P23_V_ACCUM_INIT 0x042C
-#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
-#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
-#define OV0_BASE_ADDR 0x043C
-#define OV0_VID_BUF0_BASE_ADRS 0x0440
-#define OV0_VID_BUF1_BASE_ADRS 0x0444
-#define OV0_VID_BUF2_BASE_ADRS 0x0448
-#define OV0_VID_BUF3_BASE_ADRS 0x044C
-#define OV0_VID_BUF4_BASE_ADRS 0x0450
-#define OV0_VID_BUF5_BASE_ADRS 0x0454
-#define OV0_VID_BUF_PITCH0_VALUE 0x0460
-#define OV0_VID_BUF_PITCH1_VALUE 0x0464
-#define OV0_AUTO_FLIP_CNTRL 0x0470
-#define OV0_DEINTERLACE_PATTERN 0x0474
-#define OV0_SUBMIT_HISTORY 0x0478
-#define OV0_H_INC 0x0480
-#define OV0_STEP_BY 0x0484
-#define OV0_P1_H_ACCUM_INIT 0x0488
-#define OV0_P23_H_ACCUM_INIT 0x048C
-#define OV0_P1_X_START_END 0x0494
-#define OV0_P2_X_START_END 0x0498
-#define OV0_P3_X_START_END 0x049C
-#define OV0_FILTER_CNTL 0x04A0
-#define OV0_FOUR_TAP_COEF_0 0x04B0
-#define OV0_FOUR_TAP_COEF_1 0x04B4
-#define OV0_FOUR_TAP_COEF_2 0x04B8
-#define OV0_FOUR_TAP_COEF_3 0x04BC
-#define OV0_FOUR_TAP_COEF_4 0x04C0
-#define OV0_FLAG_CNTRL 0x04DC
-#define OV0_SLICE_CNTL 0x04E0
-#define OV0_VID_KEY_CLR_LOW 0x04E4
-#define OV0_VID_KEY_CLR_HIGH 0x04E8
-#define OV0_GRPH_KEY_CLR_LOW 0x04EC
-#define OV0_GRPH_KEY_CLR_HIGH 0x04F0
-#define OV0_KEY_CNTL 0x04F4
-#define OV0_TEST 0x04F8
-#define SUBPIC_CNTL 0x0540
-#define SUBPIC_DEFCOLCON 0x0544
-#define SUBPIC_Y_X_START 0x054C
-#define SUBPIC_Y_X_END 0x0550
-#define SUBPIC_V_INC 0x0554
-#define SUBPIC_H_INC 0x0558
-#define SUBPIC_BUF0_OFFSET 0x055C
-#define SUBPIC_BUF1_OFFSET 0x0560
-#define SUBPIC_LC0_OFFSET 0x0564
-#define SUBPIC_LC1_OFFSET 0x0568
-#define SUBPIC_PITCH 0x056C
-#define SUBPIC_BTN_HLI_COLCON 0x0570
-#define SUBPIC_BTN_HLI_Y_X_START 0x0574
-#define SUBPIC_BTN_HLI_Y_X_END 0x0578
-#define SUBPIC_PALETTE_INDEX 0x057C
-#define SUBPIC_PALETTE_DATA 0x0580
-#define SUBPIC_H_ACCUM_INIT 0x0584
-#define SUBPIC_V_ACCUM_INIT 0x0588
-#define DISP_MISC_CNTL 0x0D00
-#define DAC_MACRO_CNTL 0x0D04
-#define DISP_PWR_MAN 0x0D08
-#define DISP_TEST_DEBUG_CNTL 0x0D10
-#define DISP_HW_DEBUG 0x0D14
-#define DAC_CRC_SIG1 0x0D18
-#define DAC_CRC_SIG2 0x0D1C
-#define OV0_LIN_TRANS_A 0x0D20
-#define OV0_LIN_TRANS_B 0x0D24
-#define OV0_LIN_TRANS_C 0x0D28
-#define OV0_LIN_TRANS_D 0x0D2C
-#define OV0_LIN_TRANS_E 0x0D30
-#define OV0_LIN_TRANS_F 0x0D34
-#define OV0_GAMMA_0_F 0x0D40
-#define OV0_GAMMA_10_1F 0x0D44
-#define OV0_GAMMA_20_3F 0x0D48
-#define OV0_GAMMA_40_7F 0x0D4C
-#define OV0_GAMMA_380_3BF 0x0D50
-#define OV0_GAMMA_3C0_3FF 0x0D54
-#define DISP_MERGE_CNTL 0x0D60
-#define DISP_OUTPUT_CNTL 0x0D64
-#define DISP_LIN_TRANS_GRPH_A 0x0D80
-#define DISP_LIN_TRANS_GRPH_B 0x0D84
-#define DISP_LIN_TRANS_GRPH_C 0x0D88
-#define DISP_LIN_TRANS_GRPH_D 0x0D8C
-#define DISP_LIN_TRANS_GRPH_E 0x0D90
-#define DISP_LIN_TRANS_GRPH_F 0x0D94
-#define DISP_LIN_TRANS_VID_A 0x0D98
-#define DISP_LIN_TRANS_VID_B 0x0D9C
-#define DISP_LIN_TRANS_VID_C 0x0DA0
-#define DISP_LIN_TRANS_VID_D 0x0DA4
-#define DISP_LIN_TRANS_VID_E 0x0DA8
-#define DISP_LIN_TRANS_VID_F 0x0DAC
-#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
-#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
-#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
-#define RMX_HORZ_PHASE 0x0DBC
-#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
-#define DAC_BROAD_PULSE 0x0DC4
-#define DAC_SKEW_CLKS 0x0DC8
-#define DAC_INCR 0x0DCC
-#define DAC_NEG_SYNC_LEVEL 0x0DD0
-#define DAC_POS_SYNC_LEVEL 0x0DD4
-#define DAC_BLANK_LEVEL 0x0DD8
-#define CLOCK_CNTL_INDEX 0x0008
-#define CLOCK_CNTL_DATA 0x000C
-#define CP_RB_CNTL 0x0704
-#define CP_RB_BASE 0x0700
-#define CP_RB_RPTR_ADDR 0x070C
-#define CP_RB_RPTR 0x0710
-#define CP_RB_WPTR 0x0714
-#define CP_RB_WPTR_DELAY 0x0718
-#define CP_IB_BASE 0x0738
-#define CP_IB_BUFSZ 0x073C
-#define SCRATCH_REG0 0x15E0
-#define GUI_SCRATCH_REG0 0x15E0
-#define SCRATCH_REG1 0x15E4
-#define GUI_SCRATCH_REG1 0x15E4
-#define SCRATCH_REG2 0x15E8
-#define GUI_SCRATCH_REG2 0x15E8
-#define SCRATCH_REG3 0x15EC
-#define GUI_SCRATCH_REG3 0x15EC
-#define SCRATCH_REG4 0x15F0
-#define GUI_SCRATCH_REG4 0x15F0
-#define SCRATCH_REG5 0x15F4
-#define GUI_SCRATCH_REG5 0x15F4
-#define SCRATCH_UMSK 0x0770
-#define SCRATCH_ADDR 0x0774
-#define DP_BRUSH_FRGD_CLR 0x147C
-#define DP_BRUSH_BKGD_CLR 0x1478
-#define DST_LINE_START 0x1600
-#define DST_LINE_END 0x1604
-#define SRC_OFFSET 0x15AC
-#define SRC_PITCH 0x15B0
-#define SRC_TILE 0x1704
-#define SRC_PITCH_OFFSET 0x1428
-#define SRC_X 0x1414
-#define SRC_Y 0x1418
-#define SRC_X_Y 0x1590
-#define SRC_Y_X 0x1434
-#define DST_Y_X 0x1438
-#define DST_WIDTH_HEIGHT 0x1598
-#define DST_HEIGHT_WIDTH 0x143c
-#define DST_OFFSET 0x1404
-#define SRC_CLUT_ADDRESS 0x1780
-#define SRC_CLUT_DATA 0x1784
-#define SRC_CLUT_DATA_RD 0x1788
-#define HOST_DATA0 0x17C0
-#define HOST_DATA1 0x17C4
-#define HOST_DATA2 0x17C8
-#define HOST_DATA3 0x17CC
-#define HOST_DATA4 0x17D0
-#define HOST_DATA5 0x17D4
-#define HOST_DATA6 0x17D8
-#define HOST_DATA7 0x17DC
-#define HOST_DATA_LAST 0x17E0
-#define DP_SRC_ENDIAN 0x15D4
-#define DP_SRC_FRGD_CLR 0x15D8
-#define DP_SRC_BKGD_CLR 0x15DC
-#define SC_LEFT 0x1640
-#define SC_RIGHT 0x1644
-#define SC_TOP 0x1648
-#define SC_BOTTOM 0x164C
-#define SRC_SC_RIGHT 0x1654
-#define SRC_SC_BOTTOM 0x165C
-#define DP_CNTL 0x16C0
-#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
-#define DP_DATATYPE 0x16C4
-#define DP_MIX 0x16C8
-#define DP_WRITE_MSK 0x16CC
-#define DP_XOP 0x17F8
-#define CLR_CMP_CLR_SRC 0x15C4
-#define CLR_CMP_CLR_DST 0x15C8
-#define CLR_CMP_CNTL 0x15C0
-#define CLR_CMP_MSK 0x15CC
-#define DSTCACHE_MODE 0x1710
-#define DSTCACHE_CTLSTAT 0x1714
-#define DEFAULT_PITCH_OFFSET 0x16E0
-#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
-#define DEFAULT_SC_TOP_LEFT 0x16EC
-#define SRC_PITCH_OFFSET 0x1428
-#define DST_PITCH_OFFSET 0x142C
-#define DP_GUI_MASTER_CNTL 0x146C
-#define SC_TOP_LEFT 0x16EC
-#define SC_BOTTOM_RIGHT 0x16F0
-#define SRC_SC_BOTTOM_RIGHT 0x16F4
-#define RB2D_DSTCACHE_MODE 0x3428
-#define RB2D_DSTCACHE_CTLSTAT 0x342C
-#define LVDS_GEN_CNTL 0x02d0
-#define LVDS_PLL_CNTL 0x02d4
-#define FP2_GEN_CNTL 0x0288
-#define TMDS_CNTL 0x0294
-#define TMDS_CRC 0x02a0
-#define TMDS_TRANSMITTER_CNTL 0x02a4
-#define MPP_TB_CONFIG 0x01c0
-#define PAMAC0_DLY_CNTL 0x0a94
-#define PAMAC1_DLY_CNTL 0x0a98
-#define PAMAC2_DLY_CNTL 0x0a9c
-#define FW_CNTL 0x0118
-#define FCP_CNTL 0x0910
-#define VGA_DDA_ON_OFF 0x02ec
-#define TV_MASTER_CNTL 0x0800
-
-/* #define BASE_CODE 0x0f0b */
-#define BIOS_0_SCRATCH 0x0010
-#define BIOS_1_SCRATCH 0x0014
-#define BIOS_2_SCRATCH 0x0018
-#define BIOS_3_SCRATCH 0x001c
-#define BIOS_4_SCRATCH 0x0020
-#define BIOS_5_SCRATCH 0x0024
-#define BIOS_6_SCRATCH 0x0028
-#define BIOS_7_SCRATCH 0x002c
-
-#define HDP_SOFT_RESET (1 << 26)
-
-#define TV_DAC_CNTL 0x088c
-#define GPIOPAD_MASK 0x0198
-#define GPIOPAD_A 0x019c
-#define GPIOPAD_EN 0x01a0
-#define GPIOPAD_Y 0x01a4
-#define ZV_LCDPAD_MASK 0x01a8
-#define ZV_LCDPAD_A 0x01ac
-#define ZV_LCDPAD_EN 0x01b0
-#define ZV_LCDPAD_Y 0x01b4
-
-/* PLL Registers */
-#define CLK_PIN_CNTL 0x0001
-#define PPLL_CNTL 0x0002
-#define PPLL_REF_DIV 0x0003
-#define PPLL_DIV_0 0x0004
-#define PPLL_DIV_1 0x0005
-#define PPLL_DIV_2 0x0006
-#define PPLL_DIV_3 0x0007
-#define VCLK_ECP_CNTL 0x0008
-#define HTOTAL_CNTL 0x0009
-#define M_SPLL_REF_FB_DIV 0x000a
-#define AGP_PLL_CNTL 0x000b
-#define SPLL_CNTL 0x000c
-#define SCLK_CNTL 0x000d
-#define MPLL_CNTL 0x000e
-#define MDLL_CKO 0x000f
-#define MDLL_RDCKA 0x0010
-#define MCLK_CNTL 0x0012
-#define AGP_PLL_CNTL 0x000b
-#define PLL_TEST_CNTL 0x0013
-#define CLK_PWRMGT_CNTL 0x0014
-#define PLL_PWRMGT_CNTL 0x0015
-#define MCLK_MISC 0x001f
-#define P2PLL_CNTL 0x002a
-#define P2PLL_REF_DIV 0x002b
-#define PIXCLKS_CNTL 0x002d
-#define SCLK_MORE_CNTL 0x0035
-
-/* MCLK_CNTL bit constants */
-#define FORCEON_MCLKA (1 << 16)
-#define FORCEON_MCLKB (1 << 17)
-#define FORCEON_YCLKA (1 << 18)
-#define FORCEON_YCLKB (1 << 19)
-#define FORCEON_MC (1 << 20)
-#define FORCEON_AIC (1 << 21)
-
-/* SCLK_CNTL bit constants */
-#define DYN_STOP_LAT_MASK 0x00007ff8
-#define CP_MAX_DYN_STOP_LAT 0x0008
-#define SCLK_FORCEON_MASK 0xffff8000
-
-/* SCLK_MORE_CNTL bit constants */
-#define SCLK_MORE_FORCEON 0x0700
-
-/* BUS_CNTL bit constants */
-#define BUS_DBL_RESYNC 0x00000001
-#define BUS_MSTR_RESET 0x00000002
-#define BUS_FLUSH_BUF 0x00000004
-#define BUS_STOP_REQ_DIS 0x00000008
-#define BUS_ROTATION_DIS 0x00000010
-#define BUS_MASTER_DIS 0x00000040
-#define BUS_ROM_WRT_EN 0x00000080
-#define BUS_DIS_ROM 0x00001000
-#define BUS_PCI_READ_RETRY_EN 0x00002000
-#define BUS_AGP_AD_STEPPING_EN 0x00004000
-#define BUS_PCI_WRT_RETRY_EN 0x00008000
-#define BUS_MSTR_RD_MULT 0x00100000
-#define BUS_MSTR_RD_LINE 0x00200000
-#define BUS_SUSPEND 0x00400000
-#define LAT_16X 0x00800000
-#define BUS_RD_DISCARD_EN 0x01000000
-#define BUS_RD_ABORT_EN 0x02000000
-#define BUS_MSTR_WS 0x04000000
-#define BUS_PARKING_DIS 0x08000000
-#define BUS_MSTR_DISCONNECT_EN 0x10000000
-#define BUS_WRT_BURST 0x20000000
-#define BUS_READ_BURST 0x40000000
-#define BUS_RDY_READ_DLY 0x80000000
-
-/* PIXCLKS_CNTL */
-#define PIX2CLK_SRC_SEL_MASK 0x03
-#define PIX2CLK_SRC_SEL_CPUCLK 0x00
-#define PIX2CLK_SRC_SEL_PSCANCLK 0x01
-#define PIX2CLK_SRC_SEL_BYTECLK 0x02
-#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
-#define PIX2CLK_ALWAYS_ONb (1<<6)
-#define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
-#define PIXCLK_TV_SRC_SEL (1 << 8)
-#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
-#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
-
-
-/* CLOCK_CNTL_INDEX bit constants */
-#define PLL_WR_EN 0x00000080
-
-/* CONFIG_CNTL bit constants */
-#define CONFIG_SYS_VGA_RAM_EN 0x00000100
-#define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16)
-#define CONFIG_SYS_ATI_REV_A11 (0 << 16)
-#define CONFIG_SYS_ATI_REV_A12 (1 << 16)
-#define CONFIG_SYS_ATI_REV_A13 (2 << 16)
-
-/* CRTC_EXT_CNTL bit constants */
-#define VGA_ATI_LINEAR 0x00000008
-#define VGA_128KAP_PAGING 0x00000010
-#define XCRT_CNT_EN (1 << 6)
-#define CRTC_HSYNC_DIS (1 << 8)
-#define CRTC_VSYNC_DIS (1 << 9)
-#define CRTC_DISPLAY_DIS (1 << 10)
-#define CRTC_CRT_ON (1 << 15)
-
-
-/* DSTCACHE_CTLSTAT bit constants */
-#define RB2D_DC_FLUSH (3 << 0)
-#define RB2D_DC_FLUSH_ALL 0xf
-#define RB2D_DC_BUSY (1 << 31)
-
-
-/* CRTC_GEN_CNTL bit constants */
-#define CRTC_DBL_SCAN_EN 0x00000001
-#define CRTC_CUR_EN 0x00010000
-#define CRTC_INTERLACE_EN (1 << 1)
-#define CRTC_BYPASS_LUT_EN (1 << 14)
-#define CRTC_EXT_DISP_EN (1 << 24)
-#define CRTC_EN (1 << 25)
-#define CRTC_DISP_REQ_EN_B (1 << 26)
-
-/* CRTC_STATUS bit constants */
-#define CRTC_VBLANK 0x00000001
-
-/* CRTC2_GEN_CNTL bit constants */
-#define CRT2_ON (1 << 7)
-#define CRTC2_DISPLAY_DIS (1 << 23)
-#define CRTC2_EN (1 << 25)
-#define CRTC2_DISP_REQ_EN_B (1 << 26)
-
-/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
-#define CUR_LOCK 0x80000000
-
-/* GPIO bit constants */
-#define GPIO_A_0 (1 << 0)
-#define GPIO_A_1 (1 << 1)
-#define GPIO_Y_0 (1 << 8)
-#define GPIO_Y_1 (1 << 9)
-#define GPIO_EN_0 (1 << 16)
-#define GPIO_EN_1 (1 << 17)
-#define GPIO_MASK_0 (1 << 24)
-#define GPIO_MASK_1 (1 << 25)
-#define VGA_DDC_DATA_OUTPUT GPIO_A_0
-#define VGA_DDC_CLK_OUTPUT GPIO_A_1
-#define VGA_DDC_DATA_INPUT GPIO_Y_0
-#define VGA_DDC_CLK_INPUT GPIO_Y_1
-#define VGA_DDC_DATA_OUT_EN GPIO_EN_0
-#define VGA_DDC_CLK_OUT_EN GPIO_EN_1
-
-
-/* FP bit constants */
-#define FP_CRTC_H_TOTAL_MASK 000003ff
-#define FP_CRTC_H_DISP_MASK 0x01ff0000
-#define FP_CRTC_V_TOTAL_MASK 0x00000fff
-#define FP_CRTC_V_DISP_MASK 0x0fff0000
-#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
-#define FP_H_SYNC_WID_MASK 0x003f0000
-#define FP_V_SYNC_STRT_MASK 0x00000fff
-#define FP_V_SYNC_WID_MASK 0x001f0000
-#define FP_CRTC_H_TOTAL_SHIFT 0x00000000
-#define FP_CRTC_H_DISP_SHIFT 0x00000010
-#define FP_CRTC_V_TOTAL_SHIFT 0x00000000
-#define FP_CRTC_V_DISP_SHIFT 0x00000010
-#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
-#define FP_H_SYNC_WID_SHIFT 0x00000010
-#define FP_V_SYNC_STRT_SHIFT 0x00000000
-#define FP_V_SYNC_WID_SHIFT 0x00000010
-
-/* FP_GEN_CNTL bit constants */
-#define FP_FPON (1 << 0)
-#define FP_TMDS_EN (1 << 2)
-#define FP_PANEL_FORMAT (1 << 3)
-#define FP_EN_TMDS (1 << 7)
-#define FP_DETECT_SENSE (1 << 8)
-#define R200_FP_SOURCE_SEL_MASK (3 << 10)
-#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
-#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
-#define R200_FP_SOURCE_SEL_RMX (2 << 10)
-#define R200_FP_SOURCE_SEL_TRANS (3 << 10)
-#define FP_SEL_CRTC1 (0 << 13)
-#define FP_SEL_CRTC2 (1 << 13)
-#define FP_USE_VGA_HSYNC (1 << 14)
-#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
-#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
-#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
-#define FP_CRTC_USE_SHADOW_VEND (1 << 18)
-#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
-#define FP_DFP_SYNC_SEL (1 << 21)
-#define FP_CRTC_LOCK_8DOT (1 << 22)
-#define FP_CRT_SYNC_SEL (1 << 23)
-#define FP_USE_SHADOW_EN (1 << 24)
-#define FP_CRT_SYNC_ALT (1 << 26)
-
-/* FP2_GEN_CNTL bit constants */
-#define FP2_BLANK_EN (1 << 1)
-#define FP2_ON (1 << 2)
-#define FP2_PANEL_FORMAT (1 << 3)
-#define FP2_SOURCE_SEL_MASK (3 << 10)
-#define FP2_SOURCE_SEL_CRTC2 (1 << 10)
-#define FP2_SRC_SEL_MASK (3 << 13)
-#define FP2_SRC_SEL_CRTC2 (1 << 13)
-#define FP2_FP_POL (1 << 16)
-#define FP2_LP_POL (1 << 17)
-#define FP2_SCK_POL (1 << 18)
-#define FP2_LCD_CNTL_MASK (7 << 19)
-#define FP2_PAD_FLOP_EN (1 << 22)
-#define FP2_CRC_EN (1 << 23)
-#define FP2_CRC_READ_EN (1 << 24)
-#define FP2_DV0_EN (1 << 25)
-#define FP2_DV0_RATE_SEL_SDR (1 << 26)
-
-
-/* LVDS_GEN_CNTL bit constants */
-#define LVDS_ON (1 << 0)
-#define LVDS_DISPLAY_DIS (1 << 1)
-#define LVDS_PANEL_TYPE (1 << 2)
-#define LVDS_PANEL_FORMAT (1 << 3)
-#define LVDS_EN (1 << 7)
-#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
-#define LVDS_BL_MOD_LEVEL_SHIFT 8
-#define LVDS_BL_MOD_EN (1 << 16)
-#define LVDS_DIGON (1 << 18)
-#define LVDS_BLON (1 << 19)
-#define LVDS_SEL_CRTC2 (1 << 23)
-#define LVDS_STATE_MASK \
- (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
-
-/* LVDS_PLL_CNTL bit constatns */
-#define HSYNC_DELAY_SHIFT 0x1c
-#define HSYNC_DELAY_MASK (0xf << 0x1c)
-
-/* TMDS_TRANSMITTER_CNTL bit constants */
-#define TMDS_PLL_EN (1 << 0)
-#define TMDS_PLLRST (1 << 1)
-#define TMDS_RAN_PAT_RST (1 << 7)
-#define TMDS_ICHCSEL (1 << 28)
-
-/* FP_HORZ_STRETCH bit constants */
-#define HORZ_STRETCH_RATIO_MASK 0xffff
-#define HORZ_STRETCH_RATIO_MAX 4096
-#define HORZ_PANEL_SIZE (0x1ff << 16)
-#define HORZ_PANEL_SHIFT 16
-#define HORZ_STRETCH_PIXREP (0 << 25)
-#define HORZ_STRETCH_BLEND (1 << 26)
-#define HORZ_STRETCH_ENABLE (1 << 25)
-#define HORZ_AUTO_RATIO (1 << 27)
-#define HORZ_FP_LOOP_STRETCH (0x7 << 28)
-#define HORZ_AUTO_RATIO_INC (1 << 31)
-
-
-/* FP_VERT_STRETCH bit constants */
-#define VERT_STRETCH_RATIO_MASK 0xfff
-#define VERT_STRETCH_RATIO_MAX 4096
-#define VERT_PANEL_SIZE (0xfff << 12)
-#define VERT_PANEL_SHIFT 12
-#define VERT_STRETCH_LINREP (0 << 26)
-#define VERT_STRETCH_BLEND (1 << 26)
-#define VERT_STRETCH_ENABLE (1 << 25)
-#define VERT_AUTO_RATIO_EN (1 << 27)
-#define VERT_FP_LOOP_STRETCH (0x7 << 28)
-#define VERT_STRETCH_RESERVED 0xf1000000
-
-/* DAC_CNTL bit constants */
-#define DAC_8BIT_EN 0x00000100
-#define DAC_4BPP_PIX_ORDER 0x00000200
-#define DAC_CRC_EN 0x00080000
-#define DAC_MASK_ALL (0xff << 24)
-#define DAC_PDWN (1 << 15)
-#define DAC_EXPAND_MODE (1 << 14)
-#define DAC_VGA_ADR_EN (1 << 13)
-#define DAC_RANGE_CNTL (3 << 0)
-#define DAC_RANGE_CNTL_MASK 0x03
-#define DAC_BLANKING (1 << 2)
-#define DAC_CMP_EN (1 << 3)
-#define DAC_CMP_OUTPUT (1 << 7)
-
-/* DAC_CNTL2 bit constants */
-#define DAC2_EXPAND_MODE (1 << 14)
-#define DAC2_CMP_EN (1 << 7)
-#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
-
-/* DAC_EXT_CNTL bit constants */
-#define DAC_FORCE_BLANK_OFF_EN (1 << 4)
-#define DAC_FORCE_DATA_EN (1 << 5)
-#define DAC_FORCE_DATA_SEL_MASK (3 << 6)
-#define DAC_FORCE_DATA_MASK 0x0003ff00
-#define DAC_FORCE_DATA_SHIFT 8
-
-/* GEN_RESET_CNTL bit constants */
-#define SOFT_RESET_GUI 0x00000001
-#define SOFT_RESET_VCLK 0x00000100
-#define SOFT_RESET_PCLK 0x00000200
-#define SOFT_RESET_ECP 0x00000400
-#define SOFT_RESET_DISPENG_XCLK 0x00000800
-
-/* MEM_CNTL bit constants */
-#define MEM_CTLR_STATUS_IDLE 0x00000000
-#define MEM_CTLR_STATUS_BUSY 0x00100000
-#define MEM_SEQNCR_STATUS_IDLE 0x00000000
-#define MEM_SEQNCR_STATUS_BUSY 0x00200000
-#define MEM_ARBITER_STATUS_IDLE 0x00000000
-#define MEM_ARBITER_STATUS_BUSY 0x00400000
-#define MEM_REQ_UNLOCK 0x00000000
-#define MEM_REQ_LOCK 0x00800000
-#define MEM_NUM_CHANNELS_MASK 0x00000001
-#define MEM_USE_B_CH_ONLY 0x00000002
-#define RV100_MEM_HALF_MODE 0x00000008
-#define R300_MEM_NUM_CHANNELS_MASK 0x00000003
-#define R300_MEM_USE_CD_CH_ONLY 0x00000004
-
-
-/* RBBM_SOFT_RESET bit constants */
-#define SOFT_RESET_CP (1 << 0)
-#define SOFT_RESET_HI (1 << 1)
-#define SOFT_RESET_SE (1 << 2)
-#define SOFT_RESET_RE (1 << 3)
-#define SOFT_RESET_PP (1 << 4)
-#define SOFT_RESET_E2 (1 << 5)
-#define SOFT_RESET_RB (1 << 6)
-#define SOFT_RESET_HDP (1 << 7)
-
-/* SURFACE_CNTL bit consants */
-#define SURF_TRANSLATION_DIS (1 << 8)
-#define NONSURF_AP0_SWP_16BPP (1 << 20)
-#define NONSURF_AP0_SWP_32BPP (1 << 21)
-#define NONSURF_AP1_SWP_16BPP (1 << 22)
-#define NONSURF_AP1_SWP_32BPP (1 << 23)
-
-#define R200_SURF_TILE_COLOR_MACRO (1 << 16)
-
-/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
-#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
-#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
-
-/* MM_INDEX bit constants */
-#define MM_APER 0x80000000
-
-/* CLR_CMP_CNTL bit constants */
-#define COMPARE_SRC_FALSE 0x00000000
-#define COMPARE_SRC_TRUE 0x00000001
-#define COMPARE_SRC_NOT_EQUAL 0x00000004
-#define COMPARE_SRC_EQUAL 0x00000005
-#define COMPARE_SRC_EQUAL_FLIP 0x00000007
-#define COMPARE_DST_FALSE 0x00000000
-#define COMPARE_DST_TRUE 0x00000100
-#define COMPARE_DST_NOT_EQUAL 0x00000400
-#define COMPARE_DST_EQUAL 0x00000500
-#define COMPARE_DESTINATION 0x00000000
-#define COMPARE_SOURCE 0x01000000
-#define COMPARE_SRC_AND_DST 0x02000000
-
-
-/* DP_CNTL bit constants */
-#define DST_X_RIGHT_TO_LEFT 0x00000000
-#define DST_X_LEFT_TO_RIGHT 0x00000001
-#define DST_Y_BOTTOM_TO_TOP 0x00000000
-#define DST_Y_TOP_TO_BOTTOM 0x00000002
-#define DST_X_MAJOR 0x00000000
-#define DST_Y_MAJOR 0x00000004
-#define DST_X_TILE 0x00000008
-#define DST_Y_TILE 0x00000010
-#define DST_LAST_PEL 0x00000020
-#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
-#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
-#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
-#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
-#define DST_BRES_SIGN 0x00000100
-#define DST_HOST_BIG_ENDIAN_EN 0x00000200
-#define DST_POLYLINE_NONLAST 0x00008000
-#define DST_RASTER_STALL 0x00010000
-#define DST_POLY_EDGE 0x00040000
-
-
-/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
-#define DST_X_MAJOR_S 0x00000000
-#define DST_Y_MAJOR_S 0x00000001
-#define DST_Y_BOTTOM_TO_TOP_S 0x00000000
-#define DST_Y_TOP_TO_BOTTOM_S 0x00008000
-#define DST_X_RIGHT_TO_LEFT_S 0x00000000
-#define DST_X_LEFT_TO_RIGHT_S 0x80000000
-
-
-/* DP_DATATYPE bit constants */
-#define DST_8BPP 0x00000002
-#define DST_15BPP 0x00000003
-#define DST_16BPP 0x00000004
-#define DST_24BPP 0x00000005
-#define DST_32BPP 0x00000006
-#define DST_8BPP_RGB332 0x00000007
-#define DST_8BPP_Y8 0x00000008
-#define DST_8BPP_RGB8 0x00000009
-#define DST_16BPP_VYUY422 0x0000000b
-#define DST_16BPP_YVYU422 0x0000000c
-#define DST_32BPP_AYUV444 0x0000000e
-#define DST_16BPP_ARGB4444 0x0000000f
-#define BRUSH_SOLIDCOLOR 0x00000d00
-#define SRC_MONO 0x00000000
-#define SRC_MONO_LBKGD 0x00010000
-#define SRC_DSTCOLOR 0x00030000
-#define BYTE_ORDER_MSB_TO_LSB 0x00000000
-#define BYTE_ORDER_LSB_TO_MSB 0x40000000
-#define DP_CONVERSION_TEMP 0x80000000
-#define HOST_BIG_ENDIAN_EN (1 << 29)
-
-
-/* DP_GUI_MASTER_CNTL bit constants */
-#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
-#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
-#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
-#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
-#define GMC_SRC_CLIP_DEFAULT 0x00000000
-#define GMC_SRC_CLIP_LEAVE 0x00000004
-#define GMC_DST_CLIP_DEFAULT 0x00000000
-#define GMC_DST_CLIP_LEAVE 0x00000008
-#define GMC_BRUSH_8x8MONO 0x00000000
-#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
-#define GMC_BRUSH_8x1MONO 0x00000020
-#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
-#define GMC_BRUSH_1x8MONO 0x00000040
-#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
-#define GMC_BRUSH_32x1MONO 0x00000060
-#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
-#define GMC_BRUSH_32x32MONO 0x00000080
-#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
-#define GMC_BRUSH_8x8COLOR 0x000000a0
-#define GMC_BRUSH_8x1COLOR 0x000000b0
-#define GMC_BRUSH_1x8COLOR 0x000000c0
-#define GMC_BRUSH_SOLID_COLOR 0x000000d0
-#define GMC_DST_8BPP 0x00000200
-#define GMC_DST_15BPP 0x00000300
-#define GMC_DST_16BPP 0x00000400
-#define GMC_DST_24BPP 0x00000500
-#define GMC_DST_32BPP 0x00000600
-#define GMC_DST_8BPP_RGB332 0x00000700
-#define GMC_DST_8BPP_Y8 0x00000800
-#define GMC_DST_8BPP_RGB8 0x00000900
-#define GMC_DST_16BPP_VYUY422 0x00000b00
-#define GMC_DST_16BPP_YVYU422 0x00000c00
-#define GMC_DST_32BPP_AYUV444 0x00000e00
-#define GMC_DST_16BPP_ARGB4444 0x00000f00
-#define GMC_SRC_MONO 0x00000000
-#define GMC_SRC_MONO_LBKGD 0x00001000
-#define GMC_SRC_DSTCOLOR 0x00003000
-#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
-#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
-#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
-#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
-#define GMC_DP_SRC_RECT 0x02000000
-#define GMC_DP_SRC_HOST 0x03000000
-#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
-#define GMC_3D_FCN_EN_CLR 0x00000000
-#define GMC_3D_FCN_EN_SET 0x08000000
-#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
-#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
-#define GMC_AUX_CLIP_LEAVE 0x00000000
-#define GMC_AUX_CLIP_CLEAR 0x20000000
-#define GMC_WRITE_MASK_LEAVE 0x00000000
-#define GMC_WRITE_MASK_SET 0x40000000
-#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
-#define GMC_SRC_DATATYPE_COLOR (3 << 12)
-#define ROP3_S 0x00cc0000
-#define ROP3_SRCCOPY 0x00cc0000
-#define ROP3_P 0x00f00000
-#define ROP3_PATCOPY 0x00f00000
-#define DP_SRC_SOURCE_MASK (7 << 24)
-#define GMC_BRUSH_NONE (15 << 4)
-#define DP_SRC_SOURCE_MEMORY (2 << 24)
-#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
-
-/* DP_MIX bit constants */
-#define DP_SRC_RECT 0x00000200
-#define DP_SRC_HOST 0x00000300
-#define DP_SRC_HOST_BYTEALIGN 0x00000400
-
-/* MPLL_CNTL bit constants */
-#define MPLL_RESET 0x00000001
-
-/* MDLL_CKO bit constants */
-#define MCKOA_SLEEP 0x00000001
-#define MCKOA_RESET 0x00000002
-#define MCKOA_REF_SKEW_MASK 0x00000700
-#define MCKOA_FB_SKEW_MASK 0x00007000
-
-/* MDLL_RDCKA bit constants */
-#define MRDCKA0_SLEEP 0x00000001
-#define MRDCKA0_RESET 0x00000002
-#define MRDCKA1_SLEEP 0x00010000
-#define MRDCKA1_RESET 0x00020000
-
-/* VCLK_ECP_CNTL constants */
-#define VCLK_SRC_SEL_MASK 0x03
-#define VCLK_SRC_SEL_CPUCLK 0x00
-#define VCLK_SRC_SEL_PSCANCLK 0x01
-#define VCLK_SRC_SEL_BYTECLK 0x02
-#define VCLK_SRC_SEL_PPLLCLK 0x03
-#define PIXCLK_ALWAYS_ONb 0x00000040
-#define PIXCLK_DAC_ALWAYS_ONb 0x00000080
-
-/* BUS_CNTL1 constants */
-#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
-#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
-#define BUS_CNTL1_AGPCLK_VALID 0x80000000
-
-/* PLL_PWRMGT_CNTL constants */
-#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
-#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
-#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
-#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
-#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
-#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
-#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
-
-/* TV_DAC_CNTL constants */
-#define TV_DAC_CNTL_BGSLEEP 0x00000040
-#define TV_DAC_CNTL_DETECT 0x00000010
-#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
-#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
-#define TV_DAC_CNTL_BGADJ__SHIFT 16
-#define TV_DAC_CNTL_DACADJ__SHIFT 20
-#define TV_DAC_CNTL_RDACPD 0x01000000
-#define TV_DAC_CNTL_GDACPD 0x02000000
-#define TV_DAC_CNTL_BDACPD 0x04000000
-
-/* DISP_MISC_CNTL constants */
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
-#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
-#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
-#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
-#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
-#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
-#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
-#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
-#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
-
-/* DISP_PWR_MAN constants */
-#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
-#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
-#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
-#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
-#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
-#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
-#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
-#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
-#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
-#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
-#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
-#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
-#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
-
-/* masks */
-
-#define CONFIG_MEMSIZE_MASK 0x1f000000
-#define MEM_CFG_TYPE 0x40000000
-#define DST_OFFSET_MASK 0x003fffff
-#define DST_PITCH_MASK 0x3fc00000
-#define DEFAULT_TILE_MASK 0xc0000000
-#define PPLL_DIV_SEL_MASK 0x00000300
-#define PPLL_RESET 0x00000001
-#define PPLL_SLEEP 0x00000002
-#define PPLL_ATOMIC_UPDATE_EN 0x00010000
-#define PPLL_REF_DIV_MASK 0x000003ff
-#define PPLL_FB3_DIV_MASK 0x000007ff
-#define PPLL_POST3_DIV_MASK 0x00070000
-#define PPLL_ATOMIC_UPDATE_R 0x00008000
-#define PPLL_ATOMIC_UPDATE_W 0x00008000
-#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
-#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
-#define R300_PPLL_REF_DIV_ACC_SHIFT 18
-
-#define GUI_ACTIVE 0x80000000
-
-
-#define MC_IND_INDEX 0x01F8
-#define MC_IND_DATA 0x01FC
-
-/* PAD_CTLR_STRENGTH */
-#define PAD_MANUAL_OVERRIDE 0x80000000
-
-/* pllCLK_PIN_CNTL */
-#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
-#define CLK_PIN_CNTL__OSC_EN 0x00000001L
-#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
-#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
-#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
-#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
-#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
-#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
-#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
-#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
-#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
-#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
-#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
-#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
-#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
-#define CLK_PIN_CNTL__CG_SPARE 0x00004000L
-#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
-#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
-#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
-#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
-#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
-#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
-#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
-#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
-
-/* pllCLK_PWRMGT_CNTL */
-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
-#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
-#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
-#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
-#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
-#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
-#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
-#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
-#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
-#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
-#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
-
-/* pllP2PLL_CNTL */
-#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
-#define P2PLL_CNTL__P2PLL_RESET 0x00000001L
-#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
-#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
-#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
-#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
-#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
-#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
-#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
-#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
-#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
-#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
-#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
-#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
-#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
-#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
-#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
-#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
-#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
-
-/* pllPIXCLKS_CNTL */
-#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
-#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
-#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
-#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
-#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
-#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
-#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
-#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
-#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
-#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
-#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
-
-
-/* pllPIXCLKS_CNTL */
-#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
-#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
-#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
-#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
-#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
-#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
-#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
-#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
-#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
-#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
-#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
-#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
-#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
-#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
-#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
-#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
-#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
-#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
-#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
-
-
-/* pllP2PLL_DIV_0 */
-#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
-#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
-
-/* pllSCLK_CNTL */
-#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
-#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
-#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
-#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
-#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
-#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
-#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
-#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
-#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
-#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
-#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
-#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
-#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
-#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
-#define SCLK_CNTL__FORCE_DISP2 0x00008000L
-#define SCLK_CNTL__FORCE_CP 0x00010000L
-#define SCLK_CNTL__FORCE_HDP 0x00020000L
-#define SCLK_CNTL__FORCE_DISP1 0x00040000L
-#define SCLK_CNTL__FORCE_TOP 0x00080000L
-#define SCLK_CNTL__FORCE_E2 0x00100000L
-#define SCLK_CNTL__FORCE_SE 0x00200000L
-#define SCLK_CNTL__FORCE_IDCT 0x00400000L
-#define SCLK_CNTL__FORCE_VIP 0x00800000L
-#define SCLK_CNTL__FORCE_RE 0x01000000L
-#define SCLK_CNTL__FORCE_PB 0x02000000L
-#define SCLK_CNTL__FORCE_TAM 0x04000000L
-#define SCLK_CNTL__FORCE_TDM 0x08000000L
-#define SCLK_CNTL__FORCE_RB 0x10000000L
-#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
-#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
-#define SCLK_CNTL__FORCE_OV0 0x80000000L
-#define SCLK_CNTL__R300_FORCE_VAP (1<<21)
-#define SCLK_CNTL__R300_FORCE_SR (1<<25)
-#define SCLK_CNTL__R300_FORCE_PX (1<<26)
-#define SCLK_CNTL__R300_FORCE_TX (1<<27)
-#define SCLK_CNTL__R300_FORCE_US (1<<28)
-#define SCLK_CNTL__R300_FORCE_SU (1<<30)
-#define SCLK_CNTL__FORCEON_MASK 0xffff8000L
-
-/* pllSCLK_CNTL2 */
-#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
-#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
-#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
-#define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
-#define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
-#define SCLK_CNTL2__R300_FORCE_GA (1<<15)
-
-/* SCLK_MORE_CNTL */
-#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
-#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
-#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
-#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
-#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
-#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
-#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
-#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
-#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
-#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
-#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
-#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
-#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
-#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
-#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
-#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
-#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
-#define SCLK_MORE_CNTL__FORCEON 0x00000700L
-
-/* MCLK_CNTL */
-#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
-#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
-#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
-#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
-#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
-#define MCLK_CNTL__FORCE_MCLKA 0x00010000L
-#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
-#define MCLK_CNTL__FORCE_MCLKB 0x00020000L
-#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
-#define MCLK_CNTL__FORCE_YCLKA 0x00040000L
-#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
-#define MCLK_CNTL__FORCE_YCLKB 0x00080000L
-#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
-#define MCLK_CNTL__FORCE_MC 0x00100000L
-#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
-#define MCLK_CNTL__FORCE_AIC 0x00200000L
-#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
-#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
-#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
-#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
-#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
-#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
-
-/* MCLK_MISC */
-#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
-#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
-#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
-#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
-#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
-#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
-#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
-#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
-#define MCLK_MISC__DLL_READY_LAT 0x00000100L
-#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
-#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
-#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
-#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
-#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
-#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
-#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
-#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
-#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
-#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
-#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
-#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
-#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
-#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
-#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
-#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
-#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
-#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
-#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
-
-/* VCLK_ECP_CNTL */
-#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
-#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
-#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
-#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
-#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
-#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
-#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
-#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
-#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
-
-/* PLL_PWRMGT_CNTL */
-#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
-#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
-#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
-#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
-#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
-#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
-#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
-#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
-#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
-#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
-#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
-#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
-#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
-#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
-#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
-#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
-#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
-#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
-#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
-#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
-#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
-#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
-#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
-#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
-#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
-#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
-#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
-#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
-#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
-#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
-#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
-#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
-
-/* CLK_PWRMGT_CNTL */
-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
-#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
-#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
-#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
-#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
-#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
-#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
-#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
-#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
-#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
-#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
-#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
-#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
-#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
-#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
-#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
-#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
-#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
-
-/* BUS_CNTL1 */
-#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
-#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
-#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
-#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
-#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
-#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
-#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
-#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
-#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
-#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
-#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
-#define BUS_CNTL1__AGPCLK_VALID 0x80000000L
-
-/* BUS_CNTL1 */
-#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
-#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
-#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
-#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
-#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
-#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
-#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
-
-/* CRTC_OFFSET_CNTL */
-#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
-#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
-
-/* CRTC_GEN_CNTL */
-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
-#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
-#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
-#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
-#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
-#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
-#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
-#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
-#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
-#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
-
-/* CRTC2_GEN_CNTL */
-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
-#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
-#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
-#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
-#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
-#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
-
-/* AGP_CNTL */
-#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
-#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
-#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
-#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
-#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
-#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
-#define AGP_CNTL__EN_2X_STBB 0x00000400L
-#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
-#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
-#define AGP_CNTL__SBA_DIS_MASK 0x00001000L
-#define AGP_CNTL__SBA_DIS 0x00001000L
-#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
-#define AGP_CNTL__AGP_REV_ID 0x00002000L
-#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
-#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
-#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
-#define AGP_CNTL__FORCE_INT_VREF 0x00010000L
-#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
-#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
-#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
-#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
-#define AGP_CNTL__EN_RBFCALM 0x00800000L
-#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
-#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
-#define AGP_CNTL__DIS_RBF_MASK 0x02000000L
-#define AGP_CNTL__DIS_RBF 0x02000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
-#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
-
-/* AGP_CNTL */
-#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
-#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
-#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
-#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
-#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
-#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
-#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
-#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
-#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
-#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
-#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
-#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
-#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
-#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
-#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
-#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
-#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
-
-/* DISP_MISC_CNTL */
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
-#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
-#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
-#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
-#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
-#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
-#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
-#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
-#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
-#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
-#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
-
-/* DISP_PWR_MAN */
-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
-#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
-#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
-#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
-#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
-#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
-#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
-#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
-#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
-#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
-#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
-#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
-#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
-#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
-
-/* MC_IND_INDEX */
-#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
-#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
-#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
-
-/* MC_IND_DATA */
-#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
-
-/* MC_CHP_IO_CNTL_A1 */
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
-
-/* MC_CHP_IO_CNTL_B1 */
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
-
-/* MC_CHP_IO_CNTL_A1 */
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
-
-/* MC_CHP_IO_CNTL_B1 */
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
-
-/* MEM_SDRAM_MODE_REG */
-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
-
-/* MEM_SDRAM_MODE_REG */
-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
-
-/* MEM_REFRESH_CNTL */
-#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
-#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
-
-/* MC_STATUS */
-#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
-#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
-#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
-#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
-#define MC_STATUS__MC_IDLE_MASK 0x00000004L
-#define MC_STATUS__MC_IDLE 0x00000004L
-#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
-#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
-#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
-#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
-#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
-#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
-#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
-#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
-#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
-#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
-
-/* MDLL_CKO */
-#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
-#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
-#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
-#define MDLL_CKO__MCKOA_RESET 0x00000002L
-#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
-#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
-#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
-#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
-#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
-#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
-#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
-#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
-#define MDLL_CKO__MCKOB_SLEEP 0x00010000L
-#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
-#define MDLL_CKO__MCKOB_RESET 0x00020000L
-#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
-#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
-#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
-#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
-#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
-#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
-#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
-
-/* MDLL_RDCKA */
-#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
-#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
-#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
-#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
-#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
-#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
-#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
-#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
-#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
-#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
-#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
-#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
-#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
-#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
-#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
-#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
-#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
-#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
-#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
-#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
-#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
-#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
-#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
-#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
-#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
-#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
-
-/* MDLL_RDCKB */
-#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
-#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
-#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
-#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
-#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
-#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
-#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
-#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
-#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
-#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
-#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
-#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
-#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
-#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
-#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
-#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
-#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
-#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
-#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
-#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
-#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
-#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
-#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
-#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
-#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
-#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
-
-#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
-#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
-#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
-#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
-#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
-#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
-#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
-#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
-
-#define pllCLK_PIN_CNTL 0x0001
-#define pllPPLL_CNTL 0x0002
-#define pllPPLL_REF_DIV 0x0003
-#define pllPPLL_DIV_0 0x0004
-#define pllPPLL_DIV_1 0x0005
-#define pllPPLL_DIV_2 0x0006
-#define pllPPLL_DIV_3 0x0007
-#define pllVCLK_ECP_CNTL 0x0008
-#define pllHTOTAL_CNTL 0x0009
-#define pllM_SPLL_REF_FB_DIV 0x000A
-#define pllAGP_PLL_CNTL 0x000B
-#define pllSPLL_CNTL 0x000C
-#define pllSCLK_CNTL 0x000D
-#define pllMPLL_CNTL 0x000E
-#define pllMDLL_CKO 0x000F
-#define pllMDLL_RDCKA 0x0010
-#define pllMDLL_RDCKB 0x0011
-#define pllMCLK_CNTL 0x0012
-#define pllPLL_TEST_CNTL 0x0013
-#define pllCLK_PWRMGT_CNTL 0x0014
-#define pllPLL_PWRMGT_CNTL 0x0015
-#define pllCG_TEST_MACRO_RW_WRITE 0x0016
-#define pllCG_TEST_MACRO_RW_READ 0x0017
-#define pllCG_TEST_MACRO_RW_DATA 0x0018
-#define pllCG_TEST_MACRO_RW_CNTL 0x0019
-#define pllDISP_TEST_MACRO_RW_WRITE 0x001A
-#define pllDISP_TEST_MACRO_RW_READ 0x001B
-#define pllDISP_TEST_MACRO_RW_DATA 0x001C
-#define pllDISP_TEST_MACRO_RW_CNTL 0x001D
-#define pllSCLK_CNTL2 0x001E
-#define pllMCLK_MISC 0x001F
-#define pllTV_PLL_FINE_CNTL 0x0020
-#define pllTV_PLL_CNTL 0x0021
-#define pllTV_PLL_CNTL1 0x0022
-#define pllTV_DTO_INCREMENTS 0x0023
-#define pllSPLL_AUX_CNTL 0x0024
-#define pllMPLL_AUX_CNTL 0x0025
-#define pllP2PLL_CNTL 0x002A
-#define pllP2PLL_REF_DIV 0x002B
-#define pllP2PLL_DIV_0 0x002C
-#define pllPIXCLKS_CNTL 0x002D
-#define pllHTOTAL2_CNTL 0x002E
-#define pllSSPLL_CNTL 0x0030
-#define pllSSPLL_REF_DIV 0x0031
-#define pllSSPLL_DIV_0 0x0032
-#define pllSS_INT_CNTL 0x0033
-#define pllSS_TST_CNTL 0x0034
-#define pllSCLK_MORE_CNTL 0x0035
-
-#define ixMC_PERF_CNTL 0x0000
-#define ixMC_PERF_SEL 0x0001
-#define ixMC_PERF_REGION_0 0x0002
-#define ixMC_PERF_REGION_1 0x0003
-#define ixMC_PERF_COUNT_0 0x0004
-#define ixMC_PERF_COUNT_1 0x0005
-#define ixMC_PERF_COUNT_2 0x0006
-#define ixMC_PERF_COUNT_3 0x0007
-#define ixMC_PERF_COUNT_MEMCH_A 0x0008
-#define ixMC_PERF_COUNT_MEMCH_B 0x0009
-#define ixMC_IMP_CNTL 0x000A
-#define ixMC_CHP_IO_CNTL_A0 0x000B
-#define ixMC_CHP_IO_CNTL_A1 0x000C
-#define ixMC_CHP_IO_CNTL_B0 0x000D
-#define ixMC_CHP_IO_CNTL_B1 0x000E
-#define ixMC_IMP_CNTL_0 0x000F
-#define ixTC_MISMATCH_1 0x0010
-#define ixTC_MISMATCH_2 0x0011
-#define ixMC_BIST_CTRL 0x0012
-#define ixREG_COLLAR_WRITE 0x0013
-#define ixREG_COLLAR_READ 0x0014
-#define ixR300_MC_IMP_CNTL 0x0018
-#define ixR300_MC_CHP_IO_CNTL_A0 0x0019
-#define ixR300_MC_CHP_IO_CNTL_A1 0x001a
-#define ixR300_MC_CHP_IO_CNTL_B0 0x001b
-#define ixR300_MC_CHP_IO_CNTL_B1 0x001c
-#define ixR300_MC_CHP_IO_CNTL_C0 0x001d
-#define ixR300_MC_CHP_IO_CNTL_C1 0x001e
-#define ixR300_MC_CHP_IO_CNTL_D0 0x001f
-#define ixR300_MC_CHP_IO_CNTL_D1 0x0020
-#define ixR300_MC_IMP_CNTL_0 0x0021
-#define ixR300_MC_ELPIDA_CNTL 0x0022
-#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
-#define ixR300_MC_READ_CNTL_CD 0x0024
-#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
-#define ixR300_MC_DEBUG_CNTL 0x0026
-#define ixR300_MC_BIST_CNTL_0 0x0028
-#define ixR300_MC_BIST_CNTL_1 0x0029
-#define ixR300_MC_BIST_CNTL_2 0x002a
-#define ixR300_MC_BIST_CNTL_3 0x002b
-#define ixR300_MC_BIST_CNTL_4 0x002c
-#define ixR300_MC_BIST_CNTL_5 0x002d
-#define ixR300_MC_IMP_STATUS 0x002e
-#define ixR300_MC_DLL_CNTL 0x002f
-#define NB_TOM 0x15C
-
-#endif /* _RADEON_H */
#ifndef _RELOCATE_H_
#define _RELOCATE_H_
-#include <common.h>
+#ifndef USE_HOSTCC
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
/**
* copy_uboot_to_ram() - Copy U-Boot to its new relocated position
*/
int do_elf_reloc_fixups(void);
+/**
+ * manual_reloc() - Manually relocate a pointer if needed
+ *
+ * This is a nop in almost all cases, except for the systems with a broken gcc
+ * which need to manually relocate some things.
+ *
+ * @ptr: Pointer to relocate
+ * @return new pointer value
+ */
+static inline void *manual_reloc(void *ptr)
+{
+#ifndef USE_HOSTCC
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC))
+ return ptr + gd->reloc_off;
+#endif
+ return ptr;
+}
+
+#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+#define MANUAL_RELOC(ptr) (ptr) = manual_reloc(ptr)
+#else
+#define MANUAL_RELOC(ptr) (void)(ptr)
+#endif
+
#endif /* _RELOCATE_H_ */
int smem_get_free_space(struct udevice *dev, unsigned int host);
#endif /* _smem_h_ */
-
0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
0xe1, 0x00, 0x00, 0x01
};
-
/* stdout */
#if !defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \
+ (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL)) || \
(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \
- defined(CONFIG_SPL_SERIAL_SUPPORT))
+ defined(CONFIG_SPL_SERIAL))
void putc(const char c);
void puts(const char *s);
int __printf(1, 2) printf(const char *fmt, ...);
* Returns a probed TEE device of the first TEE device matched by the
* match() callback or NULL.
*/
+#if CONFIG_IS_ENABLED(TEE)
struct udevice *tee_find_device(struct udevice *start,
int (*match)(struct tee_version_data *vers,
const void *data),
const void *data,
struct tee_version_data *vers);
+#else
+static inline struct udevice *tee_find_device(struct udevice *start,
+ int (*match)(struct tee_version_data *vers,
+ const void *data),
+ const void *data,
+ struct tee_version_data *vers)
+{
+ return NULL;
+}
+#endif
/**
* tee_get_version() - Query capabilities of TEE device
return optee_image_get_entry_point(hdr) - sizeof(struct optee_header);
}
-#if defined(CONFIG_OPTEE)
-int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
- unsigned long tzdram_len, unsigned long image_len);
-#else
-static inline int optee_verify_image(struct optee_header *hdr,
- unsigned long tzdram_start,
- unsigned long tzdram_len,
- unsigned long image_len)
-{
- return -EPERM;
-}
-
-#endif
-
-#if defined(CONFIG_OPTEE)
+#if defined(CONFIG_OPTEE_IMAGE)
int optee_verify_bootm_image(unsigned long image_addr,
unsigned long image_load_addr,
unsigned long image_len);
}
#endif
-#if defined(CONFIG_OPTEE) && defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OPTEE_LIB) && defined(CONFIG_OF_LIBFDT)
int optee_copy_fdt_nodes(void *new_blob);
#else
static inline int optee_copy_fdt_nodes(void *new_blob)
int ut_check_skipline(struct unit_test_state *uts);
/**
+ * ut_check_skip_to_line() - skip output until a line is found
+ *
+ * This creates a string and then checks it against the following lines of
+ * console output obtained with console_record_readline() until it is found.
+ *
+ * After the function returns, uts->expect_str holds the expected string and
+ * uts->actual_str holds the actual string read from the console.
+ *
+ * @uts: Test state
+ * @fmt: printf() format string to look for, followed by args
+ * @return 0 if OK, -ENOENT if not found, other value on error
+ */
+int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...);
+
+/**
* ut_check_console_end() - Check there is no more console output
*
* After the function returns, uts->actual_str holds the actual string read
return CMD_RET_FAILURE; \
} \
+/* Assert that a following console output line matches */
+#define ut_assert_skip_to_line(fmt, args...) \
+ if (ut_check_skip_to_line(uts, fmt, ##args)) { \
+ ut_failf(uts, __FILE__, __LINE__, __func__, \
+ "console", "\nExpected '%s',\n got to '%s'", \
+ uts->expect_str, uts->actual_str); \
+ return CMD_RET_FAILURE; \
+ } \
+
/* Assert that there is no more console output */
#define ut_assert_console_end() \
if (ut_check_console_end(uts)) { \
#define TSEC_SIZE 0x40000
#define TSEC_MDIO_OFFSET 0x40000
#else
-#define TSEC_SIZE 0x01000
+#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
#endif
#define _RSA_CHECKSUM_H
#include <errno.h>
-#include <image.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
+struct image_region;
+
/**
* hash_calculate() - Calculate hash over the data
*
* @return 0 if OK, < 0 if error
*/
int hash_calculate(const char *name,
- const struct image_region region[], int region_count,
+ const struct image_region *region, int region_count,
uint8_t *checksum);
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 ASPEED Technology Inc.
+ */
+#ifndef _UBOOT_HASH_H
+#define _UBOOT_HASH_H
+
+enum HASH_ALGO {
+ HASH_ALGO_CRC16_CCITT,
+ HASH_ALGO_CRC32,
+ HASH_ALGO_MD5,
+ HASH_ALGO_SHA1,
+ HASH_ALGO_SHA256,
+ HASH_ALGO_SHA384,
+ HASH_ALGO_SHA512,
+
+ HASH_ALGO_NUM,
+
+ HASH_ALGO_INVALID = 0xffffffff,
+};
+
+/* general APIs for hash algo information */
+enum HASH_ALGO hash_algo_lookup_by_name(const char *name);
+ssize_t hash_algo_digest_size(enum HASH_ALGO algo);
+const char *hash_algo_name(enum HASH_ALGO algo);
+
+/* device-dependent APIs */
+int hash_digest(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf);
+int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf, uint32_t chunk_sz);
+int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp);
+int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen);
+int hash_finish(struct udevice *dev, void *ctx, void *obuf);
+
+/*
+ * struct hash_ops - Driver model for Hash operations
+ *
+ * The uclass interface is implemented by all hash devices
+ * which use driver model.
+ */
+struct hash_ops {
+ /* progressive operations */
+ int (*hash_init)(struct udevice *dev, enum HASH_ALGO algo, void **ctxp);
+ int (*hash_update)(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen);
+ int (*hash_finish)(struct udevice *dev, void *ctx, void *obuf);
+
+ /* all-in-one operation */
+ int (*hash_digest)(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf);
+
+ /* all-in-one operation with watchdog triggering every chunk_sz */
+ int (*hash_digest_wd)(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf, uint32_t chunk_sz);
+};
+
+#endif
};
};
+void MD5Init(struct MD5Context *ctx);
+void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len);
+void MD5Final(unsigned char digest[16], struct MD5Context *ctx);
+
/*
* Calculate and store in 'output' the MD5 digest of 'len' bytes at
* 'input'. 'output' must have enough space to hold 16 bytes.
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#ifdef CONFIG_FIT_RSASSA_PSS
int padding_pss_verify(struct image_sign_info *info,
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#endif /* CONFIG_FIT_RSASSA_PSS */
#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
#ifndef __VERSION_H__
#define __VERSION_H__
-#include <timestamp.h>
-
#ifndef DO_DEPS_ONLY
#include "generated/version_autogenerated.h"
#endif
-#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
- U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
-
-#ifndef __ASSEMBLY__
-extern const char version_string[];
-#endif /* __ASSEMBLY__ */
#endif /* __VERSION_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __VERSION_STRING_H__
+#define __VERSION_STRING_H__
+
+extern const char version_string[];
+
+#endif /* __VERSION_STRING_H__ */
#define VNBITS(bpix) (1 << (bpix))
+enum video_format {
+ VIDEO_UNKNOWN,
+ VIDEO_X8B8G8R8,
+ VIDEO_X8R8G8B8,
+ VIDEO_X2R10G10B10,
+};
+
/**
* struct video_priv - Device information used by the video uclass
*
* @ysize: Number of pixels rows (e.g.. 768)
* @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.)
* @bpix: Encoded bits per pixel (enum video_log2_bpp)
+ * @format: Pixel format (enum video_format)
* @vidconsole_drv_name: Driver to use for the text console, NULL to
* select automatically
* @font_size: Font size in pixels (0 to use a default value)
ushort ysize;
ushort rot;
enum video_log2_bpp bpix;
+ enum video_format format;
const char *vidconsole_drv_name;
int font_size;
static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
/*{*/
- /* Char 0: ' ' */
+ /* Char 0: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 1: ' ' */
+ /* Char 1: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 2: ' ' */
+ /* Char 2: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 3: ' ' */
+ /* Char 3: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 4: ' ' */
+ /* Char 4: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 5: ' ' */
+ /* Char 5: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 6: ' ' */
+ /* Char 6: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 7: ' ' */
+ /* Char 7: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 8: ' ' */
+ /* Char 8: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 9: ' ' */
+ /* Char 9: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 10: '' */
+ /* Char 10: '' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 11: ' ' */
+ /* Char 11: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 12: ' ' */
+ /* Char 12: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 13: ' ' */
+ /* Char 13: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 14: ' ' */
+ /* Char 14: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 15: ' ' */
+ /* Char 15: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 16: ' ' */
+ /* Char 16: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 17: ' ' */
+ /* Char 17: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 18: ' ' */
+ /* Char 18: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 19: ' ' */
+ /* Char 19: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 20: ' ' */
+ /* Char 20: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 21: ' ' */
+ /* Char 21: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 22: ' ' */
+ /* Char 22: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 23: ' ' */
+ /* Char 23: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 24: ' ' */
+ /* Char 24: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 25: ' ' */
+ /* Char 25: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 26: ' ' */
+ /* Char 26: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 27: ' ' */
+ /* Char 27: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 28: ' ' */
+ /* Char 28: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 29: ' ' */
+ /* Char 29: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 30: ' ' */
+ /* Char 30: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 31: ' ' */
+ /* Char 31: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 32: ' ' */
+ /* Char 32: ' ' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 33: '!' */
+ /* Char 33: '!' */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 34: '"' */
+ /* Char 34: '"' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 35: '#' */
+ /* Char 35: '#' */
0xaa, /*= [* * ] */
0xff, /*= [****] */
0xff, /*= [****] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 36: '$' */
+ /* Char 36: '$' */
0x44, /*= [ * ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 37: '%' */
+ /* Char 37: '%' */
0xaa, /*= [* * ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 38: '&' */
+ /* Char 38: '&' */
0x66, /*= [ ** ] */
0x99, /*= [* *] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 39: ''' */
+ /* Char 39: ''' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 40: '(' */
+ /* Char 40: '(' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 41: ')' */
+ /* Char 41: ')' */
0x44, /*= [ * ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 42: '*' */
+ /* Char 42: '*' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 43: '+' */
+ /* Char 43: '+' */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 44: ',' */
+ /* Char 44: ',' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 45: '-' */
+ /* Char 45: '-' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 46: '.' */
+ /* Char 46: '.' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 47: '/' */
+ /* Char 47: '/' */
0x00, /*= [ ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 48: '0' */
+ /* Char 48: '0' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 49: '1' */
+ /* Char 49: '1' */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 50: '2' */
+ /* Char 50: '2' */
0xcc, /*= [** ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 51: '3' */
+ /* Char 51: '3' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 52: '4' */
+ /*{*/ /* Char 52: '4' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 53: '5' */
+ /*{*/ /* Char 53: '5' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 54: '6' */
+ /*{*/ /* Char 54: '6' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 55: '7' */
+ /*{*/ /* Char 55: '7' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 56: '8' */
+ /*{*/ /* Char 56: '8' */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 57: '9' */
+ /*{*/ /* Char 57: '9' */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 58: ':' */
+ /*{*/ /* Char 58: ':' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 59: ';' */
+ /*{*/ /* Char 59: ';' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x88, /*= [* ] */
/*}*/
- /*{*/ /* Char 60: '<' */
+ /*{*/ /* Char 60: '<' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x88, /*= [* ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 61: '=' */
+ /*{*/ /* Char 61: '=' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 62: '>' */
+ /*{*/ /* Char 62: '>' */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x22, /*= [ * ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 63: '?' */
+ /*{*/ /* Char 63: '?' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 64: '@' */
+ /*{*/ /* Char 64: '@' */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 65: 'A' */
+ /*{*/ /* Char 65: 'A' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 66: 'B' */
+ /*{*/ /* Char 66: 'B' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 67: 'C' */
+ /*{*/ /* Char 67: 'C' */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0x88, /*= [* ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 68: 'D' */
+ /*{*/ /* Char 68: 'D' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 69: 'E' */
+ /*{*/ /* Char 69: 'E' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 70: 'F' */
+ /*{*/ /* Char 70: 'F' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 71: 'G' */
+ /*{*/ /* Char 71: 'G' */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 72: 'H' */
+ /*{*/ /* Char 72: 'H' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 73: 'I' */
+ /*{*/ /* Char 73: 'I' */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 74: 'J' */
+ /*{*/ /* Char 74: 'J' */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 75: 'K' */
+ /*{*/ /* Char 75: 'K' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 76: 'L' */
+ /*{*/ /* Char 76: 'L' */
0x88, /*= [* ] */
0x88, /*= [* ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 77: 'M' */
+ /*{*/ /* Char 77: 'M' */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 78: 'N' */
+ /*{*/ /* Char 78: 'N' */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 79: 'O' */
+ /*{*/ /* Char 79: 'O' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 80: 'P' */
+ /*{*/ /* Char 80: 'P' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 81: 'Q' */
+ /*{*/ /* Char 81: 'Q' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 82: 'R' */
+ /*{*/ /* Char 82: 'R' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 83: 'S' */
+ /*{*/ /* Char 83: 'S' */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 84: 'T' */
+ /*{*/ /* Char 84: 'T' */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 85: 'U' */
+ /*{*/ /* Char 85: 'U' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 86: 'V' */
+ /*{*/ /* Char 86: 'V' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 87: 'W' */
+ /*{*/ /* Char 87: 'W' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 88: 'X' */
+ /*{*/ /* Char 88: 'X' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 89: 'Y' */
+ /*{*/ /* Char 89: 'Y' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 90: 'Z' */
+ /*{*/ /* Char 90: 'Z' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 91: '[' */
+ /*{*/ /* Char 91: '[' */
0x66, /*= [ ** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 92: '\' */
+ /*{*/ /* Char 92: '\' */
0x00, /*= [ ] */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 93: ']' */
+ /*{*/ /* Char 93: ']' */
0x66, /*= [ ** ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 94: '^' */
+ /*{*/ /* Char 94: '^' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 95: '_' */
+ /*{*/ /* Char 95: '_' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
/*}*/
- /*{*/ /* Char 96: '`' */
+ /*{*/ /* Char 96: '`' */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 97: 'a' */
+ /*{*/ /* Char 97: 'a' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 98: 'b' */
+ /*{*/ /* Char 98: 'b' */
0x88, /*= [* ] */
0x88, /*= [* ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 99: 'c' */
+ /*{*/ /* Char 99: 'c' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 100: 'd' */
+ /*{*/ /* Char 100: 'd' */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 101: 'e' */
+ /*{*/ /* Char 101: 'e' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 102: 'f' */
+ /*{*/ /* Char 102: 'f' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 103: 'g' */
+ /*{*/ /* Char 103: 'g' */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 104: 'h' */
+ /*{*/ /* Char 104: 'h' */
0x88, /*= [* ] */
0x88, /*= [* ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 105: 'i' */
+ /*{*/ /* Char 105: 'i' */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 106: 'j' */
+ /*{*/ /* Char 106: 'j' */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 107: 'k' */
+ /*{*/ /* Char 107: 'k' */
0x00, /*= [ ] */
0x88, /*= [* ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 108: 'l' */
+ /*{*/ /* Char 108: 'l' */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 109: 'm' */
+ /*{*/ /* Char 109: 'm' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 110: 'n' */
+ /*{*/ /* Char 110: 'n' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 111: 'o' */
+ /*{*/ /* Char 111: 'o' */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 112: 'p' */
+ /*{*/ /* Char 112: 'p' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x88, /*= [* ] */
/*}*/
- /*{*/ /* Char 113: 'q' */
+ /*{*/ /* Char 113: 'q' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x22, /*= [ * ] */
/*}*/
- /*{*/ /* Char 114: 'r' */
+ /*{*/ /* Char 114: 'r' */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 115: 's' */
+ /*{*/ /* Char 115: 's' */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 116: 't' */
+ /*{*/ /* Char 116: 't' */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 117: 'u' */
+ /*{*/ /* Char 117: 'u' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 118: 'v' */
+ /*{*/ /* Char 118: 'v' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 119: 'w' */
+ /*{*/ /* Char 119: 'w' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 120: 'x' */
+ /*{*/ /* Char 120: 'x' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 121: 'y' */
+ /*{*/ /* Char 121: 'y' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0x22, /*= [ * ] */
0xcc, /*= [** ] */
/*}*/
- /*{*/ /* Char 122: 'z' */
+ /*{*/ /* Char 122: 'z' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 123: '{' */
+ /*{*/ /* Char 123: '{' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 124: '|' */
+ /*{*/ /* Char 124: '|' */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 125: '}' */
+ /*{*/ /* Char 125: '}' */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 126: '~' */
+ /*{*/ /* Char 126: '~' */
0x55, /*= [ * *] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 127: '\7f' */
+ /*{*/ /* Char 127: '\7f' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 128: */
+ /*{*/ /* Char 128: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 129: */
+ /*{*/ /* Char 129: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 130: */
+ /*{*/ /* Char 130: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 131: */
+ /*{*/ /* Char 131: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 132: */
+ /*{*/ /* Char 132: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 133: */
+ /*{*/ /* Char 133: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 134: */
+ /*{*/ /* Char 134: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 135: */
+ /*{*/ /* Char 135: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 136: */
+ /*{*/ /* Char 136: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 137: */
+ /*{*/ /* Char 137: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 138: */
+ /*{*/ /* Char 138: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 139: */
+ /*{*/ /* Char 139: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 140: */
+ /*{*/ /* Char 140: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 141: */
+ /*{*/ /* Char 141: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 142: */
+ /*{*/ /* Char 142: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 143: */
+ /*{*/ /* Char 143: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 144: */
+ /*{*/ /* Char 144: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 145: */
+ /*{*/ /* Char 145: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 146: */
+ /*{*/ /* Char 146: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 147: */
+ /*{*/ /* Char 147: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 148: */
+ /*{*/ /* Char 148: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 149: */
+ /*{*/ /* Char 149: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 150: */
+ /*{*/ /* Char 150: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 151: */
+ /*{*/ /* Char 151: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 152: */
+ /*{*/ /* Char 152: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 153: */
+ /*{*/ /* Char 153: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 154: */
+ /*{*/ /* Char 154: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 155: */
+ /*{*/ /* Char 155: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 156: */
+ /*{*/ /* Char 156: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 157: */
+ /*{*/ /* Char 157: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 158: */
+ /*{*/ /* Char 158: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 159: */
+ /*{*/ /* Char 159: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 160: */
+ /*{*/ /* Char 160: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 161: */
+ /*{*/ /* Char 161: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 162: */
+ /*{*/ /* Char 162: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 163: */
+ /*{*/ /* Char 163: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 164: */
+ /*{*/ /* Char 164: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 165: */
+ /*{*/ /* Char 165: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 166: */
+ /*{*/ /* Char 166: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 167: */
+ /*{*/ /* Char 167: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 168: */
+ /*{*/ /* Char 168: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 169: */
+ /*{*/ /* Char 169: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 170: */
+ /*{*/ /* Char 170: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 171: */
+ /*{*/ /* Char 171: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 172: */
+ /*{*/ /* Char 172: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 173: */
+ /*{*/ /* Char 173: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 174: */
+ /*{*/ /* Char 174: */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 175: */
+ /*{*/ /* Char 175: */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 176: */
+ /*{*/ /* Char 176: */
0x88, /*= [* ] */
0x22, /*= [ * ] */
0x88, /*= [* ] */
0x88, /*= [* ] */
0x22, /*= [ * ] */
/*}*/
- /*{*/ /* Char 177: */
+ /*{*/ /* Char 177: */
0xaa, /*= [* * ] */
0x55, /*= [ * *] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x55, /*= [ * *] */
/*}*/
- /*{*/ /* Char 178: */
+ /*{*/ /* Char 178: */
0xdd, /*= [** *] */
0xbb, /*= [* **] */
0xdd, /*= [** *] */
0xdd, /*= [** *] */
0xbb, /*= [* **] */
/*}*/
- /*{*/ /* Char 179: */
+ /*{*/ /* Char 179: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 180: */
+ /*{*/ /* Char 180: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 181: */
+ /*{*/ /* Char 181: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 182: */
+ /*{*/ /* Char 182: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 183: */
+ /*{*/ /* Char 183: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 184: */
+ /*{*/ /* Char 184: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 185: */
+ /*{*/ /* Char 185: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 186: */
+ /*{*/ /* Char 186: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 187: */
+ /*{*/ /* Char 187: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 188: */
+ /*{*/ /* Char 188: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 189: */
+ /*{*/ /* Char 189: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 190: */
+ /*{*/ /* Char 190: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 191: */
+ /*{*/ /* Char 191: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 192: */
+ /*{*/ /* Char 192: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 193: */
+ /*{*/ /* Char 193: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 194: */
+ /*{*/ /* Char 194: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 195: */
+ /*{*/ /* Char 195: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 196: */
+ /*{*/ /* Char 196: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 197: */
+ /*{*/ /* Char 197: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 198: */
+ /*{*/ /* Char 198: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 199: */
+ /*{*/ /* Char 199: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 200: */
+ /*{*/ /* Char 200: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 201: */
+ /*{*/ /* Char 201: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 202: */
+ /*{*/ /* Char 202: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 203: */
+ /*{*/ /* Char 203: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 204: */
+ /*{*/ /* Char 204: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 205: */
+ /*{*/ /* Char 205: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 206: */
+ /*{*/ /* Char 206: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 207: */
+ /*{*/ /* Char 207: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 208: */
+ /*{*/ /* Char 208: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 209: */
+ /*{*/ /* Char 209: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 210: */
+ /*{*/ /* Char 210: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 211: */
+ /*{*/ /* Char 211: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 212: */
+ /*{*/ /* Char 212: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 213: */
+ /*{*/ /* Char 213: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 214: */
+ /*{*/ /* Char 214: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 215: */
+ /*{*/ /* Char 215: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 216: */
+ /*{*/ /* Char 216: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 217: */
+ /*{*/ /* Char 217: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 218: */
+ /*{*/ /* Char 218: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 219: */
+ /*{*/ /* Char 219: */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
/*}*/
- /*{*/ /* Char 220: */
+ /*{*/ /* Char 220: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0xff, /*= [****] */
/*}*/
- /*{*/ /* Char 221: */
+ /*{*/ /* Char 221: */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
/*}*/
- /*{*/ /* Char 222: */
+ /*{*/ /* Char 222: */
0x33, /*= [ **] */
0x33, /*= [ **] */
0x33, /*= [ **] */
0x33, /*= [ **] */
0x33, /*= [ **] */
/*}*/
- /*{*/ /* Char 223: */
+ /*{*/ /* Char 223: */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 224: */
+ /*{*/ /* Char 224: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 225: */
+ /*{*/ /* Char 225: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 226: */
+ /*{*/ /* Char 226: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 227: */
+ /*{*/ /* Char 227: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 228: */
+ /*{*/ /* Char 228: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 229: */
+ /*{*/ /* Char 229: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 230: */
+ /*{*/ /* Char 230: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 231: */
+ /*{*/ /* Char 231: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 232: */
+ /*{*/ /* Char 232: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 233: */
+ /*{*/ /* Char 233: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 234: */
+ /*{*/ /* Char 234: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 235: */
+ /*{*/ /* Char 235: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 236: */
+ /*{*/ /* Char 236: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 237: */
+ /*{*/ /* Char 237: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 238: */
+ /*{*/ /* Char 238: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 239: */
+ /*{*/ /* Char 239: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 240: */
+ /*{*/ /* Char 240: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 241: */
+ /*{*/ /* Char 241: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 242: */
+ /*{*/ /* Char 242: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 243: */
+ /*{*/ /* Char 243: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 244: */
+ /*{*/ /* Char 244: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 245: */
+ /*{*/ /* Char 245: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 246: */
+ /*{*/ /* Char 246: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 247: */
+ /*{*/ /* Char 247: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 248: */
+ /*{*/ /* Char 248: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 249: */
+ /*{*/ /* Char 249: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 250: */
+ /*{*/ /* Char 250: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 251: */
+ /*{*/ /* Char 251: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 252: */
+ /*{*/ /* Char 252: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 253: */
+ /*{*/ /* Char 253: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 254: */
+ /*{*/ /* Char 254: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 255: */
+ /*{*/ /* Char 255: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
int wdt_stop(struct udevice *dev);
/*
+ * Stop all registered watchdog devices.
+ *
+ * @return: 0 if ok, first error encountered otherwise (but wdt_stop()
+ * is still called on following devices)
+ */
+int wdt_stop_all(void);
+
+/*
* Reset the timer, typically restoring the counter to
* the value configured by start()
*
config SSCANF
bool
- default n
config STRTO
bool
config LIBAVB
bool "Android Verified Boot 2.0 support"
depends on ANDROID_BOOT_IMAGE
- default n
help
This enables support of Android Verified Boot 2.0 which can be used
to assure the end user of the integrity of the software running on a
The SHA256 algorithm produces a 256-bit (32-byte) hash value
(digest).
-
config SHA512
bool "Enable SHA512 support"
help
hashing algorithms. This affects the 'hash' command and also the
hash_lookup_algo() function.
+if SPL
+
+config SPL_SHA1
+ bool "Enable SHA1 support in SPL"
+ default y if SHA1
+ help
+ This option enables support of hashing using SHA1 algorithm.
+ The hash is calculated in software.
+ The SHA1 algorithm produces a 160-bit (20-byte) hash value
+ (digest).
+
+config SPL_SHA256
+ bool "Enable SHA256 support in SPL"
+ default y if SHA256
+ help
+ This option enables support of hashing using SHA256 algorithm.
+ The hash is calculated in software.
+ The SHA256 algorithm produces a 256-bit (32-byte) hash value
+ (digest).
+
+config SPL_SHA512
+ bool "Enable SHA512 support in SPL"
+ default y if SHA512
+ help
+ This option enables support of hashing using SHA512 algorithm.
+ The hash is calculated in software.
+ The SHA512 algorithm produces a 512-bit (64-byte) hash value
+ (digest).
+
+config SPL_SHA384
+ bool "Enable SHA384 support in SPL"
+ default y if SHA384
+ select SPL_SHA512
+ help
+ This option enables support of hashing using SHA384 algorithm.
+ The hash is calculated in software. This is also selects SHA512,
+ because these implementations share the bulk of the code..
+ The SHA384 algorithm produces a 384-bit (48-byte) hash value
+ (digest).
+
+config SPL_SHA_HW_ACCEL
+ bool "Enable hardware acceleration for SHA hash functions"
+ default y if SHA_HW_ACCEL
+ help
+ This option enables hardware acceleration for the SHA1 and SHA256
+ hashing algorithms. This affects the 'hash' command and also the
+ hash_lookup_algo() function.
+
+config SPL_SHA_PROG_HW_ACCEL
+ bool "Enable Progressive hashing support using hardware in SPL"
+ depends on SHA_PROG_HW_ACCEL
+ default y
+ help
+ This option enables hardware-acceleration for SHA progressive
+ hashing.
+ Data can be streamed in a block at a time and the hashing is
+ performed in hardware.
+
+endif
+
if SHA_HW_ACCEL
config SHA512_HW_ACCEL
security applications, but it can be useful for providing a quick
checksum of a block of data.
+config CRC32
+ def_bool y
+ help
+ Enables CRC32 support in U-Boot. This is normally required.
+
config CRC32C
bool
config PHANDLE_CHECK_SEQ
bool "Enable phandle check while getting sequence number"
- default n
help
When there are multiple device tree nodes with same name,
enable this config option to distinguish them using
obj-$(CONFIG_OF_LIVE) += of_live.o
obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
obj-$(CONFIG_ARCH_AT91) += at91/
-obj-$(CONFIG_OPTEE) += optee/
+obj-$(CONFIG_OPTEE_LIB) += optee/
obj-$(CONFIG_ASN1_DECODER) += asn1_decoder.o
obj-y += crypto/
obj-$(CONFIG_LIBAVB) += libavb/
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
-ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
-obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o
-endif
+obj-$(CONFIG_$(SPL_TPL_)OF_REAL) += fdtdec_common.o fdtdec.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
obj-$(CONFIG_$(SPL_TPL_)HASH) += crc16.o
+obj-$(CONFIG_MMC_SPI_CRC_ON) += crc16.o
obj-y += net_utils.o
endif
obj-$(CONFIG_ADDR_MAP) += addr_map.o
CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
obj-$(CONFIG_BCH) += bch.o
obj-$(CONFIG_MMC_SPI) += crc7.o
-#ifndef CONFIG_TPL_BUILD
-obj-y += crc32.o
-#endif
+obj-$(CONFIG_$(SPL_TPL_)CRC32) += crc32.o
obj-$(CONFIG_CRC32C) += crc32c.o
obj-y += ctype.o
obj-y += div64.o
obj-$(CONFIG_SSCANF) += sscanf.o
endif
+obj-y += abuf.o
obj-y += date.o
obj-y += rtc-lib.o
obj-$(CONFIG_LIB_ELF) += elf.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <abuf.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <string.h>
+
+void abuf_set(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_uninit(abuf);
+ abuf->data = data;
+ abuf->size = size;
+}
+
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size)
+{
+ abuf_set(abuf, map_sysmem(addr, size), size);
+}
+
+bool abuf_realloc(struct abuf *abuf, size_t new_size)
+{
+ void *ptr;
+
+ if (!new_size) {
+ /* easy case, just need to uninit, freeing any allocation */
+ abuf_uninit(abuf);
+ return true;
+ } else if (abuf->alloced) {
+ /* currently allocated, so need to reallocate */
+ ptr = realloc(abuf->data, new_size);
+ if (!ptr)
+ return false;
+ abuf->data = ptr;
+ abuf->size = new_size;
+ return true;
+ } else if (new_size <= abuf->size) {
+ /*
+ * not currently alloced and new size is no larger. Just update
+ * it. Data is lost off the end if new_size < abuf->size
+ */
+ abuf->size = new_size;
+ return true;
+ } else {
+ /* not currently allocated and new size is larger. Alloc and
+ * copy in data. The new space is not inited.
+ */
+ ptr = memdup(abuf->data, new_size);
+ if (!ptr)
+ return false;
+ abuf->data = ptr;
+ abuf->size = new_size;
+ abuf->alloced = true;
+ return true;
+ }
+}
+
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
+{
+ void *ptr;
+
+ if (sizep)
+ *sizep = abuf->size;
+ if (!abuf->size)
+ return NULL;
+ if (abuf->alloced) {
+ ptr = abuf->data;
+ } else {
+ ptr = memdup(abuf->data, abuf->size);
+ if (!ptr)
+ return NULL;
+ }
+ /* Clear everything out so there is no record of the data */
+ abuf_init(abuf);
+
+ return ptr;
+}
+
+void abuf_init_set(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_init(abuf);
+ abuf_set(abuf, data, size);
+}
+
+void abuf_init_move(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_init_set(abuf, data, size);
+ abuf->alloced = true;
+}
+
+void abuf_uninit(struct abuf *abuf)
+{
+ if (abuf->alloced)
+ free(abuf->data);
+ abuf_init(abuf);
+}
+
+void abuf_init(struct abuf *abuf)
+{
+ abuf->data = NULL;
+ abuf->size = 0;
+ abuf->alloced = false;
+}
#include <log.h>
#include <mapmem.h>
#include <tables_csum.h>
+#include <timestamp.h>
#include <version.h>
#include <acpi/acpi_table.h>
#include <asm/global_data.h>
#include <dm/acpi.h>
+/*
+ * OEM_REVISION is 32-bit unsigned number. It should be increased only when
+ * changing software version. Therefore it should not depend on build time.
+ * U-Boot calculates it from U-Boot version and represent it in hexadecimal
+ * notation. As U-Boot version is in form year.month set low 8 bits to 0x01
+ * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to
+ * value 0x20210401.
+ */
+#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \
+ (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \
+ (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \
+ ((U_BOOT_VERSION_NUM % 10) << 16) | \
+ (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \
+ ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \
+ 0x01)
+
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
{
struct acpi_table_header *header = &dmar->header;
memcpy(header->signature, signature, 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
- header->oem_revision = U_BOOT_BUILD_DATE;
+ header->oem_revision = OEM_REVISION;
memcpy(header->aslc_id, ASLC_ID, 4);
}
}
crc_table_empty = 0;
}
-#else
+#elif !defined(CONFIG_ARM64_CRC32)
/* ========================================================================
* Table of CRC-32's of all single-byte values (made by make_crc_table)
*/
*/
uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len)
{
+#ifdef CONFIG_ARM64_CRC32
+ crc = cpu_to_le32(crc);
+ while (len--)
+ crc = __builtin_aarch64_crc32b(crc, *buf++);
+ return le32_to_cpu(crc);
+#else
const uint32_t *tab = crc_table;
const uint32_t *b =(const uint32_t *)buf;
size_t rem_len;
}
return le32_to_cpu(crc);
+#endif
}
#undef DO_CRC
#include <compiler.h>
#include <console.h>
#include <div64.h>
-#include <version.h>
+#include <version_string.h>
#include <linux/ctype.h>
#include <asm/io.h>
config EFI_SETUP_EARLY
bool
- default n
choice
prompt "Store for non-volatile UEFI variables"
bool "SetTime() runtime service"
depends on EFI_GET_TIME
default y if ARCH_QEMU || SANDBOX
- default n
help
Provide the SetTime() runtime service at boottime. This service
can be used by an EFI application to adjust the real time clock.
config EFI_RUNTIME_UPDATE_CAPSULE
bool "UpdateCapsule() runtime service"
- default n
select EFI_HAVE_CAPSULE_SUPPORT
help
Select this option if you want to use UpdateCapsule and
config EFI_CAPSULE_ON_DISK
bool "Enable capsule-on-disk support"
select EFI_HAVE_CAPSULE_SUPPORT
- default n
help
Select this option if you want to use capsule-on-disk feature,
that is, capsules can be fetched and executed from files
config EFI_IGNORE_OSINDICATIONS
bool "Ignore OsIndications for CapsuleUpdate on-disk"
depends on EFI_CAPSULE_ON_DISK
- default n
help
There are boards where U-Boot does not support SetVariable at runtime.
Select this option if you want to use the capsule-on-disk feature
config EFI_CAPSULE_ON_DISK_EARLY
bool "Initiate capsule-on-disk at U-Boot boottime"
depends on EFI_CAPSULE_ON_DISK
- default n
select EFI_SETUP_EARLY
help
Normally, without this option enabled, capsules will be
config EFI_CAPSULE_FIRMWARE
bool
- default n
config EFI_CAPSULE_FIRMWARE_MANAGEMENT
bool "Capsule: Firmware Management Protocol"
select PKCS7_VERIFY
select IMAGE_SIGN_INFO
select EFI_SIGNATURE_SUPPORT
- default n
help
Select this option if you want to enable capsule
authentication
config EFI_LOADER_BOUNCE_BUFFER
bool "EFI Applications use bounce buffers for DMA operations"
depends on ARM64
- default n
help
Some hardware does not support DMA to full 64bit addresses. For this
hardware we can create a bounce buffer so that payloads don't have to
config EFI_SECURE_BOOT
bool "Enable EFI secure boot support"
- depends on EFI_LOADER
+ depends on EFI_LOADER && FIT_SIGNATURE
select HASH
select SHA256
select RSA
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
select EFI_SIGNATURE_SUPPORT
- default n
help
Select this option to enable EFI secure boot support.
Once SecureBoot mode is enforced, any EFI binary can run only if
return EFI_EXIT(ret);
}
+static __always_inline struct efi_gop_pixel efi_vid30_to_blt_col(u32 vid)
+{
+ struct efi_gop_pixel blt = {
+ .reserved = 0,
+ };
+
+ blt.blue = (vid & 0x3ff) >> 2;
+ vid >>= 10;
+ blt.green = (vid & 0x3ff) >> 2;
+ vid >>= 10;
+ blt.red = (vid & 0x3ff) >> 2;
+ return blt;
+}
+
+static __always_inline u32 efi_blt_col_to_vid30(struct efi_gop_pixel *blt)
+{
+ return (u32)(blt->red << 2) << 20 |
+ (u32)(blt->green << 2) << 10 |
+ (u32)(blt->blue << 2);
+}
+
static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid)
{
struct efi_gop_pixel blt = {
if (vid_bpp == 32)
pix = *(struct efi_gop_pixel *)&fb32[
slineoff + j + sx];
+ else if (vid_bpp == 30)
+ pix = efi_vid30_to_blt_col(fb32[
+ slineoff + j + sx]);
else
pix = efi_vid16_to_blt_col(fb16[
slineoff + j + sx]);
case EFI_BLT_VIDEO_TO_VIDEO:
if (vid_bpp == 32)
fb32[dlineoff + j + dx] = *(u32 *)&pix;
+ else if (vid_bpp == 30)
+ fb32[dlineoff + j + dx] =
+ efi_blt_col_to_vid30(&pix);
else
fb16[dlineoff + j + dx] =
efi_blt_col_to_vid16(&pix);
#else
case LCD_COLOR32:
#endif
- vid_bpp = 32;
+ if (gopobj->info.pixel_format == EFI_GOT_BGRA8)
+ vid_bpp = 32;
+ else
+ vid_bpp = 30;
break;
#ifdef CONFIG_DM_VIDEO
case VIDEO_BPP16:
dy, width, height, delta, 16);
}
+static efi_status_t gop_blt_buf_to_vid30(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx,
+ dy, width, height, delta, 30);
+}
+
static efi_status_t gop_blt_buf_to_vid32(struct efi_gop *this,
struct efi_gop_pixel *buffer,
u32 foo, efi_uintn_t sx,
ret = gop_blt_buf_to_vid32(this, buffer, operation, sx,
sy, dx, dy, width, height,
delta);
+ else if (vid_bpp == 30)
+ ret = gop_blt_buf_to_vid30(this, buffer, operation, sx,
+ sy, dx, dy, width, height,
+ delta);
else
ret = gop_blt_buf_to_vid16(this, buffer, operation, sx,
sy, dx, dy, width, height,
efi_status_t efi_gop_register(void)
{
struct efi_gop_obj *gopobj;
- u32 bpix, col, row;
+ u32 bpix, format, col, row;
u64 fb_base, fb_size;
void *fb;
efi_status_t ret;
priv = dev_get_uclass_priv(vdev);
bpix = priv->bpix;
+ format = priv->format;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
fb_base = (uintptr_t)priv->fb;
int line_len;
bpix = panel_info.vl_bpix;
+ format = VIDEO_UNKNOWN;
col = panel_info.vl_col;
row = panel_info.vl_row;
fb_base = gd->fb_base;
if (bpix == LCD_COLOR32)
#endif
{
- gopobj->info.pixel_format = EFI_GOT_BGRA8;
+ if (format == VIDEO_X2R10G10B10) {
+ gopobj->info.pixel_format = EFI_GOT_BITMASK;
+ gopobj->info.pixel_bitmask[0] = 0x3ff00000; /* red */
+ gopobj->info.pixel_bitmask[1] = 0x000ffc00; /* green */
+ gopobj->info.pixel_bitmask[2] = 0x000003ff; /* blue */
+ gopobj->info.pixel_bitmask[3] = 0xc0000000; /* reserved */
+ } else {
+ gopobj->info.pixel_format = EFI_GOT_BGRA8;
+ }
} else {
gopobj->info.pixel_format = EFI_GOT_BITMASK;
gopobj->info.pixel_bitmask[0] = 0xf800; /* red */
#include <efi_tcg2.h>
#include <log.h>
#include <malloc.h>
-#include <version.h>
+#include <version_string.h>
#include <tpm-v2.h>
#include <u-boot/hash-checksum.h>
#include <u-boot/sha1.h>
*/
static efi_status_t efi_append_scrtm_version(struct udevice *dev)
{
- u8 ver[] = U_BOOT_VERSION_STRING;
efi_status_t ret;
- ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION, sizeof(ver), ver);
+ ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION,
+ strlen(version_string) + 1,
+ (u8 *)version_string);
return ret;
}
return cell;
}
-int fdtdec_get_config_int(const void *blob, const char *prop_name,
- int default_val)
-{
- int config_node;
-
- debug("%s: %s\n", __func__, prop_name);
- config_node = fdt_path_offset(blob, "/config");
- if (config_node < 0)
- return default_val;
- return fdtdec_get_int(blob, config_node, prop_name, default_val);
-}
-
-int fdtdec_get_config_bool(const void *blob, const char *prop_name)
-{
- int config_node;
- const void *prop;
-
- debug("%s: %s\n", __func__, prop_name);
- config_node = fdt_path_offset(blob, "/config");
- if (config_node < 0)
- return 0;
- prop = fdt_get_property(blob, config_node, prop_name, NULL);
-
- return prop != NULL;
-}
-
-char *fdtdec_get_config_string(const void *blob, const char *prop_name)
-{
- const char *nodep;
- int nodeoffset;
- int len;
-
- debug("%s: %s\n", __func__, prop_name);
- nodeoffset = fdt_path_offset(blob, "/config");
- if (nodeoffset < 0)
- return NULL;
-
- nodep = fdt_getprop(blob, nodeoffset, prop_name, &len);
- if (!nodep)
- return NULL;
-
- return (char *)nodep;
-}
-
u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
{
u64 number = 0;
#ifdef CONFIG_CMD_UNZIP
__weak
-void gzwrite_progress_init(u64 expectedsize)
+void gzwrite_progress_init(ulong expectedsize)
{
putc('\n');
}
__weak
void gzwrite_progress(int iteration,
- u64 bytes_written,
- u64 total_bytes)
+ ulong bytes_written,
+ ulong total_bytes)
{
if (0 == (iteration & 3))
- printf("%llu/%llu\r", bytes_written, total_bytes);
+ printf("%lu/%lu\r", bytes_written, total_bytes);
}
__weak
void gzwrite_progress_finish(int returnval,
- u64 bytes_written,
- u64 total_bytes,
+ ulong bytes_written,
+ ulong total_bytes,
u32 expected_crc,
u32 calculated_crc)
{
if (0 == returnval) {
- printf("\n\t%llu bytes, crc 0x%08x\n",
+ printf("\n\t%lu bytes, crc 0x%08x\n",
total_bytes, calculated_crc);
} else {
- printf("\n\tuncompressed %llu of %llu\n"
+ printf("\n\tuncompressed %lu of %lu\n"
"\tcrcs == 0x%08x/0x%08x\n",
bytes_written, total_bytes,
expected_crc, calculated_crc);
int gzwrite(unsigned char *src, int len,
struct blk_desc *dev,
unsigned long szwritebuf,
- u64 startoffs,
- u64 szexpected)
+ ulong startoffs,
+ ulong szexpected)
{
int i, flags;
z_stream s;
int r = 0;
unsigned char *writebuf;
unsigned crc = 0;
- u64 totalfilled = 0;
+ ulong totalfilled = 0;
lbaint_t blksperbuf, outblock;
u32 expected_crc;
u32 payload_size;
}
if (startoffs & (dev->blksz-1)) {
- printf("%s: start offset %llu not a multiple of %lu\n",
+ printf("%s: start offset %lu not a multiple of %lu\n",
__func__, startoffs, dev->blksz);
return -1;
}
if (szexpected == 0) {
szexpected = le32_to_cpu(szuncompressed);
} else if (szuncompressed != (u32)szexpected) {
- printf("size of %llx doesn't match trailer low bits %x\n",
+ printf("size of %lx doesn't match trailer low bits %x\n",
szexpected, szuncompressed);
return -1;
}
if (lldiv(szexpected, dev->blksz) > (dev->lba - outblock)) {
- printf("%s: uncompressed size %llu exceeds device size\n",
+ printf("%s: uncompressed size %lu exceeds device size\n",
__func__, szexpected);
return -1;
}
{
#if !defined(CONFIG_SPL_BUILD) || \
(CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \
- CONFIG_IS_ENABLED(SERIAL_SUPPORT))
+ CONFIG_IS_ENABLED(SERIAL))
puts("### ERROR ### Please RESET the board ###\n");
#endif
bootstage_error(BOOTSTAGE_ID_NEED_RESET);
#include <image.h>
int hash_calculate(const char *name,
- const struct image_region region[],
+ const struct image_region *region,
int region_count, uint8_t *checksum)
{
struct hash_algo *algo;
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
#define LMB_ALLOC_ANYWHERE 0
static void lmb_dump_region(struct lmb_region *rgn, char *name)
lmb->reserved.cnt = 0;
}
+void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align)
+{
+ ulong bank_end;
+ int bank;
+
+ /*
+ * Reserve memory from aligned address below the bottom of U-Boot stack
+ * until end of U-Boot area using LMB to prevent U-Boot from overwriting
+ * that memory.
+ */
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+ /* adjust sp by 4K to be safe */
+ sp -= align;
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (!gd->bd->bi_dram[bank].size ||
+ sp < gd->bd->bi_dram[bank].start)
+ continue;
+ /* Watch out for RAM at end of address space! */
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size - 1;
+ if (sp > bank_end)
+ continue;
+ if (bank_end > end)
+ bank_end = end - 1;
+
+ lmb_reserve(lmb, sp, bank_end - sp + 1);
+ break;
+ }
+}
+
static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob)
{
arch_lmb_reserve(lmb);
board_lmb_reserve(lmb);
- if (IMAGE_ENABLE_OF_LIBFDT && fdt_blob)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob)
boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
}
#include <common.h>
#include <compiler.h>
#include <image.h>
-#include <lz4.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/unaligned.h>
+#include <u-boot/lz4.h>
static u16 LZ4_readLE16(const void *src)
{
* Start MD5 accumulation. Set bit count to 0 and buffer to mysterious
* initialization constants.
*/
-static void
+void
MD5Init(struct MD5Context *ctx)
{
ctx->buf[0] = 0x67452301;
* Update context to reflect the concatenation of another buffer full
* of bytes.
*/
-static void
+void
MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len)
{
register __u32 t;
* Final wrapup - pad to 64-byte boundary with the bit pattern
* 1 0* (64-bit count of bits processed, MSB-first)
*/
-static void
+void
MD5Final(unsigned char digest[16], struct MD5Context *ctx)
{
unsigned int count;
-config OPTEE
- bool "Support OPTEE images"
- help
- U-Boot can be configured to boot OPTEE images.
- Selecting this option will enable shared OPTEE library code and
- enable an OPTEE specific bootm command that will perform additional
- OPTEE specific checks before booting an OPTEE image created with
- mkimage.
-
-config OPTEE_LOAD_ADDR
- hex "OPTEE load address"
- default 0x00000000
- depends on OPTEE
+config OPTEE_LIB
+ bool "Support OPTEE library"
+ default y if OPTEE || OPTEE_IMAGE
help
- The load address of the bootable OPTEE binary.
+ Selecting this option will enable the shared OPTEE library code.
-config OPTEE_TZDRAM_SIZE
- hex "Amount of Trust-Zone RAM for the OPTEE image"
- default 0x0000000
- depends on OPTEE
- help
- The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
- runtime.
-
-config OPTEE_TZDRAM_BASE
- hex "Base address of Trust-Zone RAM for the OPTEE image"
- default 0x00000000
- depends on OPTEE
+config OPTEE_IMAGE
+ bool "Support OPTEE images"
help
- The base address of pre-allocated Trust Zone DRAM for
- the OPTEE runtime.
+ Selecting this option to boot OPTEE images.
+ This option enable the OPTEE specific checks done before booting
+ an OPTEE image created with mkimage
config BOOTM_OPTEE
bool "Support OPTEE bootm command"
select BOOTM_LINUX
- depends on OPTEE
- default n
+ select OPTEE_IMAGE
help
Select this command to enable chain-loading of a Linux kernel
via an OPTEE firmware.
#
# (C) Copyright 2017 Linaro
-obj-$(CONFIG_OPTEE) += optee.o
+obj-y += optee.o
#define optee_hdr_err_msg \
"OPTEE verification error:" \
- "\n\thdr=%p image=0x%08lx magic=0x%08x tzdram 0x%08lx-0x%08lx " \
+ "\n\thdr=%p image=0x%08lx magic=0x%08x" \
"\n\theader lo=0x%08x hi=0x%08x size=0x%08lx arch=0x%08x" \
"\n\tuimage params 0x%08lx-0x%08lx\n"
-int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
- unsigned long tzdram_len, unsigned long image_len)
+#if defined(CONFIG_OPTEE_IMAGE)
+static int optee_verify_image(struct optee_header *hdr, unsigned long image_len)
{
- unsigned long tzdram_end = tzdram_start + tzdram_len;
uint32_t tee_file_size;
tee_file_size = hdr->init_size + hdr->paged_size +
if (hdr->magic != OPTEE_MAGIC ||
hdr->version != OPTEE_VERSION ||
- hdr->init_load_addr_hi > tzdram_end ||
- hdr->init_load_addr_lo < tzdram_start ||
- tee_file_size > tzdram_len ||
- tee_file_size != image_len ||
- (hdr->init_load_addr_lo + tee_file_size) > tzdram_end) {
+ tee_file_size != image_len) {
return -EINVAL;
}
unsigned long image_len)
{
struct optee_header *hdr = (struct optee_header *)image_addr;
- unsigned long tzdram_start = CONFIG_OPTEE_TZDRAM_BASE;
- unsigned long tzdram_len = CONFIG_OPTEE_TZDRAM_SIZE;
-
int ret;
- ret = optee_verify_image(hdr, tzdram_start, tzdram_len, image_len);
+ ret = optee_verify_image(hdr, image_len);
if (ret)
goto error;
return ret;
error:
- printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic, tzdram_start,
- tzdram_start + tzdram_len, hdr->init_load_addr_lo,
+ printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic,
+ hdr->init_load_addr_lo,
hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr,
image_load_addr + image_len);
return ret;
}
+#endif
#if defined(CONFIG_OF_LIBFDT)
static int optee_copy_firmware_node(ofnode node, void *fdt_blob)
config SPL_RSA_VERIFY
bool
+ depends on SPL_RSA
help
Add RSA signature verification support in SPL.
#include <openssl/evp.h>
#include <openssl/engine.h>
-#if OPENSSL_VERSION_NUMBER >= 0x10000000L
-#define HAVE_ERR_REMOVE_THREAD_STATE
-#endif
-
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
-static void RSA_get0_key(const RSA *r,
- const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
-{
- if (n != NULL)
- *n = r->n;
- if (e != NULL)
- *e = r->e;
- if (d != NULL)
- *d = r->d;
-}
-#endif
-
static int rsa_err(const char *msg)
{
unsigned long sslErr = ERR_get_error();
else if (name)
snprintf(key_id, sizeof(key_id),
"%s",
- name);
+ name ? name : "");
else if (keyfile)
snprintf(key_id, sizeof(key_id), "%s", keyfile);
else
{
int ret;
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- ret = SSL_library_init();
-#else
ret = OPENSSL_init_ssl(0, NULL);
-#endif
if (!ret) {
fprintf(stderr, "Failure to init SSL library\n");
return -1;
}
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- SSL_load_error_strings();
-
- OpenSSL_add_all_algorithms();
- OpenSSL_add_all_digests();
- OpenSSL_add_all_ciphers();
-#endif
return 0;
}
e = ENGINE_by_id(engine_id);
if (!e) {
fprintf(stderr, "Engine isn't available\n");
- ret = -1;
- goto err_engine_by_id;
+ return -1;
}
if (!ENGINE_init(e)) {
ENGINE_finish(e);
err_engine_init:
ENGINE_free(e);
-err_engine_by_id:
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- ENGINE_cleanup();
-#endif
return ret;
}
-static void rsa_remove(void)
-{
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- CRYPTO_cleanup_all_ex_data();
- ERR_free_strings();
-#ifdef HAVE_ERR_REMOVE_THREAD_STATE
- ERR_remove_thread_state(NULL);
-#else
- ERR_remove_state(0);
-#endif
- EVP_cleanup();
-#endif
-}
-
static void rsa_engine_remove(ENGINE *e)
{
if (e) {
goto err_sign;
}
-#ifdef CONFIG_FIT_RSASSA_PSS
- if (padding_algo && !strcmp(padding_algo->name, "pss")) {
+ if (CONFIG_IS_ENABLED(FIT_RSASSA_PSS) && padding_algo &&
+ !strcmp(padding_algo->name, "pss")) {
if (EVP_PKEY_CTX_set_rsa_padding(ckey,
RSA_PKCS1_PSS_PADDING) <= 0) {
ret = rsa_err("Signer padding setup failed");
goto err_sign;
}
}
-#endif /* CONFIG_FIT_RSASSA_PSS */
for (i = 0; i < region_count; i++) {
if (!EVP_DigestSignUpdate(context, region[i].data,
goto err_sign;
}
- #if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- EVP_MD_CTX_cleanup(context);
- #else
- EVP_MD_CTX_reset(context);
- #endif
+ EVP_MD_CTX_reset(context);
EVP_MD_CTX_destroy(context);
debug("Got signature: %zu bytes, expected %d\n", size, EVP_PKEY_size(pkey));
if (info->engine_id) {
ret = rsa_engine_init(info->engine_id, &e);
if (ret)
- goto err_engine;
+ return ret;
}
ret = rsa_get_priv_key(info->keydir, info->keyname, info->keyfile,
EVP_PKEY_free(pkey);
if (info->engine_id)
rsa_engine_remove(e);
- rsa_remove();
return ret;
err_priv:
if (info->engine_id)
rsa_engine_remove(e);
-err_engine:
- rsa_remove();
return ret;
}
ret = rsa_get_pub_key(info->keydir, info->keyname, e, &pkey);
if (ret)
goto err_get_pub_key;
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- rsa = EVP_PKEY_get1_RSA(pkey);
-#else
+
rsa = EVP_PKEY_get0_RSA(pkey);
-#endif
ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared);
if (ret)
goto err_get_params;
if (ret)
ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
err_get_params:
-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
- RSA_free(rsa);
-#endif
EVP_PKEY_free(pkey);
err_get_pub_key:
if (info->engine_id)
};
#endif
-#ifdef CONFIG_FIT_RSASSA_PSS
+#if CONFIG_IS_ENABLED(FIT_RSASSA_PSS)
static void u32_i2osp(uint32_t val, uint8_t *buf)
{
buf[0] = (uint8_t)((val >> 24) & 0xff);
#endif
-#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_key() - Verify a signature against some data using RSA Key
*
return 0;
}
-#endif
-#if CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_with_pkey() - Verify a signature against some data using
* only modulus and exponent as RSA key properties.
struct key_prop *prop;
int ret;
+ if (!CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY))
+ return -EACCES;
+
/* Public key is self-described to fill key_prop */
ret = rsa_gen_key_prop(info->key, info->keylen, &prop);
if (ret) {
return ret;
}
-#else
-int rsa_verify_with_pkey(struct image_sign_info *info,
- const void *hash, uint8_t *sig, uint sig_len)
-{
- return -EACCES;
-}
-#endif
#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
/**
}
#endif
+char *memdup(const void *src, size_t len)
+{
+ char *p;
+
+ p = malloc(len);
+ if (!p)
+ return NULL;
+
+ memcpy(p, src, len);
+
+ return p;
+}
+
#ifndef __HAVE_ARCH_STRSTR
/**
* strstr - Find the first substring in a %NUL terminated string
out_dgt(info, dgt);
}
-#ifdef CONFIG_SPL_NET_SUPPORT
+#ifdef CONFIG_SPL_NET
static void string(struct printf_info *info, char *s)
{
char ch;
}
break;
#endif
-#ifdef CONFIG_SPL_NET_SUPPORT
+#ifdef CONFIG_SPL_NET
case 'm':
return mac_address_string(info, ptr, false);
case 'M':
}
break;
case 'p':
- if (CONFIG_IS_ENABLED(NET_SUPPORT) || _DEBUG) {
+ if (CONFIG_IS_ENABLED(NET) || _DEBUG) {
pointer(info, fmt, va_arg(va, void *));
/*
* Skip this because it pulls in _ctype which is
obj-y += zstd_decompress.o
zstd_decompress-y := huf_decompress.o decompress.o \
- entropy_common.o fse_decompress.o zstd_common.o
+ entropy_common.o fse_decompress.o zstd_common.o zstd.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#define LOG_CATEGORY LOGC_BOOT
+
+#include <common.h>
+#include <abuf.h>
+#include <log.h>
+#include <malloc.h>
+#include <linux/zstd.h>
+
+int zstd_decompress(struct abuf *in, struct abuf *out)
+{
+ ZSTD_DStream *dstream;
+ ZSTD_inBuffer in_buf;
+ ZSTD_outBuffer out_buf;
+ void *workspace;
+ size_t wsize;
+ int ret;
+
+ wsize = ZSTD_DStreamWorkspaceBound(abuf_size(in));
+ workspace = malloc(wsize);
+ if (!workspace) {
+ debug("%s: cannot allocate workspace of size %zu\n", __func__,
+ wsize);
+ return -ENOMEM;
+ }
+
+ dstream = ZSTD_initDStream(abuf_size(in), workspace, wsize);
+ if (!dstream) {
+ log_err("%s: ZSTD_initDStream failed\n", __func__);
+ ret = -EPERM;
+ goto do_free;
+ }
+
+ in_buf.src = abuf_data(in);
+ in_buf.pos = 0;
+ in_buf.size = abuf_size(in);
+
+ out_buf.dst = abuf_data(out);
+ out_buf.pos = 0;
+ out_buf.size = abuf_size(out);
+
+ while (1) {
+ size_t res;
+
+ res = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
+ if (ZSTD_isError(res)) {
+ ret = ZSTD_getErrorCode(res);
+ log_err("ZSTD_decompressStream error %d\n", ret);
+ goto do_free;
+ }
+
+ if (in_buf.pos >= abuf_size(in) || !res)
+ break;
+ }
+
+ ret = out_buf.pos;
+do_free:
+ free(workspace);
+ return ret;
+}
config IP_DEFRAG
bool "Support IP datagram reassembly"
- default n
help
Selecting this will enable IP datagram reassembly according
to the algorithm in RFC815.
#include <common.h>
#include <net.h>
-#if defined(CONFIG_CDP_VERSION)
-#include <timestamp.h>
-#endif
#include "cdp.h"
port_pdata = dev_get_parent_plat(pdev);
ops->port_disable(dev, port_pdata->index, port_pdata->phy);
- ops->port_disable(dev, priv->cpu_port, NULL);
+ ops->port_disable(dev, priv->cpu_port, priv->cpu_port_fixed_phy);
}
eth_get_ops(master)->stop(master);
static int dsa_port_of_to_pdata(struct udevice *pdev)
{
struct dsa_port_pdata *port_pdata;
- struct dsa_pdata *dsa_pdata;
struct eth_pdata *eth_pdata;
- struct udevice *dev;
const char *label;
u32 index;
int err;
if (err)
return err;
- dev = dev_get_parent(pdev);
- dsa_pdata = dev_get_uclass_plat(dev);
-
port_pdata = dev_get_parent_plat(pdev);
port_pdata->index = index;
label = ofnode_read_string(dev_ofnode(pdev), "label");
if (label)
- strncpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
+ strlcpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
eth_pdata = dev_get_plat(pdev);
eth_pdata->priv_pdata = port_pdata;
.free_pkt = dsa_port_free_pkt,
};
-static int dsa_port_probe(struct udevice *pdev)
+/*
+ * Inherit port's hwaddr from the DSA master, unless the port already has a
+ * unique MAC address specified in the environment.
+ */
+static void dsa_port_set_hwaddr(struct udevice *pdev, struct udevice *master)
{
- struct udevice *dev = dev_get_parent(pdev);
struct eth_pdata *eth_pdata, *master_pdata;
unsigned char env_enetaddr[ARP_HLEN];
+
+ eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
+ if (!is_zero_ethaddr(env_enetaddr)) {
+ /* individual port mac addrs require master to be promisc */
+ struct eth_ops *eth_ops = eth_get_ops(master);
+
+ if (eth_ops->set_promisc)
+ eth_ops->set_promisc(master, 1);
+
+ return;
+ }
+
+ master_pdata = dev_get_plat(master);
+ eth_pdata = dev_get_plat(pdev);
+ memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
+ eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
+ master_pdata->enetaddr);
+}
+
+static int dsa_port_probe(struct udevice *pdev)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
struct dsa_port_pdata *port_pdata;
- struct dsa_priv *dsa_priv;
struct udevice *master;
- int ret;
+ int err;
port_pdata = dev_get_parent_plat(pdev);
- dsa_priv = dev_get_uclass_priv(dev);
port_pdata->phy = dm_eth_phy_connect(pdev);
if (!port_pdata->phy)
* TODO: we assume the master device is always there and doesn't get
* removed during runtime.
*/
- ret = device_probe(master);
- if (ret)
- return ret;
-
- /*
- * Inherit port's hwaddr from the DSA master, unless the port already
- * has a unique MAC address specified in the environment.
- */
- eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
- if (!is_zero_ethaddr(env_enetaddr)) {
- /* individual port mac addrs require master to be promisc */
- struct eth_ops *eth_ops = eth_get_ops(master);
+ err = device_probe(master);
+ if (err)
+ return err;
- if (eth_ops->set_promisc)
- eth_ops->set_promisc(master, 1);
+ dsa_port_set_hwaddr(pdev, master);
- return 0;
+ if (ops->port_probe) {
+ err = ops->port_probe(dev, port_pdata->index,
+ port_pdata->phy);
+ if (err)
+ return err;
}
- master_pdata = dev_get_plat(master);
- eth_pdata = dev_get_plat(pdev);
- memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
- eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
- master_pdata->enetaddr);
-
return 0;
}
static int dsa_port_remove(struct udevice *pdev)
{
- struct udevice *dev = dev_get_parent(pdev);
- struct dsa_port_pdata *port_pdata;
- struct dsa_priv *dsa_priv;
-
- port_pdata = dev_get_parent_plat(pdev);
- dsa_priv = dev_get_uclass_priv(dev);
+ struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev);
port_pdata->phy = NULL;
struct dsa_port_pdata *port_pdata;
port_pdata = dev_get_parent_plat(pdev);
- strncpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
+ strlcpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
pdev->name = port_pdata->name;
}
void eth_common_init(void)
{
bootstage_mark(BOOTSTAGE_ID_NET_ETH_START);
+#if CONFIG_IS_ENABLED(ETH)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_init();
#endif
#ifdef CONFIG_PHYLIB
phy_init();
#endif
+#endif
}
int eth_mac_skip(int index)
pdata->mii_bus->write = mdio_write;
pdata->mii_bus->reset = mdio_reset;
pdata->mii_bus->priv = dev;
- strncpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN - 1);
+ strlcpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN);
return mdio_register(pdata->mii_bus);
}
memset(net_server_ethaddr, 0, 6);
}
#endif /* CONFIG_CMD_TFTPSRV */
-
int_state = disable_interrupts();
icache_enable();
-#ifdef CONFIG_DDR_32BIT
- /* It seems like no one really uses the CONFIG_DDR_32BIT mode */
-#error "Add ECC POST support for CONFIG_DDR_32BIT here!"
-#else
for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
errbit %= 63;
}
-#endif /* !CONFIG_DDR_32BIT */
ecc_clear(ddr);
libs-y += dts/
libs-y += fs/
libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
-libs-$(CONFIG_SPL_NET_SUPPORT) += net/
+libs-$(CONFIG_SPL_NET) += net/
libs-$(CONFIG_SPL_UNIT_TEST) += test/
head-y := $(addprefix $(obj)/,$(head-y))
FINAL_DTB_CONTAINER = $(obj)/$(SPL_BIN).multidtb.fit
endif
-# Build the .dtb file if:
-# - we are not using OF_PLATDATA
-# - we are using OF_CONTROL
+# Build the .dtb file if needed
+# - OF_REAL is enabled
# - we have either OF_SEPARATE or OF_HOSTFILE
build_dtb :=
-ifeq ($(CONFIG_$(SPL_TPL_)OF_PLATDATA),)
-ifneq ($(CONFIG_$(SPL_TPL_)OF_CONTROL),)
+ifneq ($(CONFIG_$(SPL_TPL_)OF_REAL),)
ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_OF_HOSTFILE),y)
build_dtb := y
endif
endif
-endif
ifneq ($(build_dtb),)
$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
# when kernel configuration changes (which is what happens when
# .config is included by main Makefile.
# ---------------------------------------------------------------------------
-# fixdep: Used to generate dependency information during build process
+# fixdep: Used to generate dependency information during build process
hostprogs-y := fixdep
always := $(hostprogs-y)
use Getopt::Long qw(:config no_auto_abbrev);
my $quiet = 0;
+my $verbose = 0;
+my %verbose_messages = ();
+my %verbose_emitted = ();
my $tree = 1;
my $chk_signoff = 1;
my $chk_patch = 1;
my $fix = 0;
my $fix_inplace = 0;
my $root;
+my $gitroot = $ENV{'GIT_DIR'};
+$gitroot = ".git" if !defined($gitroot);
my %debug;
my %camelcase = ();
my %use_type = ();
my $codespell = 0;
my $codespellfile = "/usr/share/codespell/dictionary.txt";
my $conststructsfile = "$D/const_structs.checkpatch";
-my $typedefsfile = "";
my $u_boot = 0;
+my $docsfile = "$D/../doc/develop/checkpatch.rst";
+my $typedefsfile;
my $color = "auto";
my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE
# git output parsing needs US English output, so first set backtick child process LANGUAGE
my $git_command ='export LANGUAGE=en_US.UTF-8; git';
my $tabsize = 8;
+my ${CONFIG_} = "CONFIG_";
sub help {
my ($exitcode) = @_;
Options:
-q, --quiet quiet
+ -v, --verbose verbose mode
--no-tree run without a kernel tree
--no-signoff do not check for 'Signed-off-by' line
--patch treat FILE as patchfile (default)
--color[=WHEN] Use colors 'always', 'never', or only when output
is a terminal ('auto'). Default is 'auto'.
--u-boot Run additional checks for U-Boot
+ --kconfig-prefix=WORD use WORD as a prefix for Kconfig symbols (default
+ ${CONFIG_})
-h, --help, --version display this help and exit
When FILE is - read standard input.
my $text = <$script>;
close($script);
- my @types = ();
+ my %types = ();
# Also catch when type or level is passed through a variable
- for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) {
- push (@types, $_);
+ while ($text =~ /(?:(\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) {
+ if (defined($1)) {
+ if (exists($types{$2})) {
+ $types{$2} .= ",$1" if ($types{$2} ne $1);
+ } else {
+ $types{$2} = $1;
+ }
+ } else {
+ $types{$2} = "UNDETERMINED";
+ }
}
- @types = sort(uniq(@types));
+
print("#\tMessage type\n\n");
- foreach my $type (@types) {
+ if ($color) {
+ print(" ( Color coding: ");
+ print(RED . "ERROR" . RESET);
+ print(" | ");
+ print(YELLOW . "WARNING" . RESET);
+ print(" | ");
+ print(GREEN . "CHECK" . RESET);
+ print(" | ");
+ print("Multiple levels / Undetermined");
+ print(" )\n\n");
+ }
+
+ foreach my $type (sort keys %types) {
+ my $orig_type = $type;
+ if ($color) {
+ my $level = $types{$type};
+ if ($level eq "ERROR") {
+ $type = RED . $type . RESET;
+ } elsif ($level eq "WARN") {
+ $type = YELLOW . $type . RESET;
+ } elsif ($level eq "CHK") {
+ $type = GREEN . $type . RESET;
+ }
+ }
print(++$count . "\t" . $type . "\n");
+ if ($verbose && exists($verbose_messages{$orig_type})) {
+ my $message = $verbose_messages{$orig_type};
+ $message =~ s/\n/\n\t/g;
+ print("\t" . $message . "\n\n");
+ }
}
exit($exitcode);
unshift(@ARGV, @conf_args) if @conf_args;
}
+sub load_docs {
+ open(my $docs, '<', "$docsfile")
+ or warn "$P: Can't read the documentation file $docsfile $!\n";
+
+ my $type = '';
+ my $desc = '';
+ my $in_desc = 0;
+
+ while (<$docs>) {
+ chomp;
+ my $line = $_;
+ $line =~ s/\s+$//;
+
+ if ($line =~ /^\s*\*\*(.+)\*\*$/) {
+ if ($desc ne '') {
+ $verbose_messages{$type} = trim($desc);
+ }
+ $type = $1;
+ $desc = '';
+ $in_desc = 1;
+ } elsif ($in_desc) {
+ if ($line =~ /^(?:\s{4,}|$)/) {
+ $line =~ s/^\s{4}//;
+ $desc .= $line;
+ $desc .= "\n";
+ } else {
+ $verbose_messages{$type} = trim($desc);
+ $type = '';
+ $desc = '';
+ $in_desc = 0;
+ }
+ }
+ }
+
+ if ($desc ne '') {
+ $verbose_messages{$type} = trim($desc);
+ }
+ close($docs);
+}
+
# Perl's Getopt::Long allows options to take optional arguments after a space.
# Prevent --color by itself from consuming other arguments
foreach (@ARGV) {
GetOptions(
'q|quiet+' => \$quiet,
+ 'v|verbose!' => \$verbose,
'tree!' => \$tree,
'signoff!' => \$chk_signoff,
'patch!' => \$chk_patch,
'color=s' => \$color,
'no-color' => \$color, #keep old behaviors of -nocolor
'nocolor' => \$color, #keep old behaviors of -nocolor
+ 'kconfig-prefix=s' => \${CONFIG_},
'h|help' => \$help,
'version' => \$help
) or help(1);
help(0) if ($help);
+die "$P: --git cannot be used with --file or --fix\n" if ($git && ($file || $fix));
+die "$P: --verbose cannot be used with --terse\n" if ($verbose && $terse);
+
+if ($color =~ /^[01]$/) {
+ $color = !$color;
+} elsif ($color =~ /^always$/i) {
+ $color = 1;
+} elsif ($color =~ /^never$/i) {
+ $color = 0;
+} elsif ($color =~ /^auto$/i) {
+ $color = (-t STDOUT);
+} else {
+ die "$P: Invalid color mode: $color\n";
+}
+
+load_docs() if ($verbose);
list_types(0) if ($list_types);
$fix = 1 if ($fix_inplace);
push(@ARGV, '-');
}
-if ($color =~ /^[01]$/) {
- $color = !$color;
-} elsif ($color =~ /^always$/i) {
- $color = 1;
-} elsif ($color =~ /^never$/i) {
- $color = 0;
-} elsif ($color =~ /^auto$/i) {
- $color = (-t STDOUT);
-} else {
- die "Invalid color mode: $color\n";
-}
-
# skip TAB size 1 to avoid additional checks on $tabsize - 1
-die "Invalid TAB size: $tabsize\n" if ($tabsize < 2);
+die "$P: Invalid TAB size: $tabsize\n" if ($tabsize < 2);
sub hash_save_array_words {
my ($hashRef, $arrayRef) = @_;
# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
our $Attribute = qr{
const|
+ volatile|
__percpu|
__nocast|
__safe|
our $allocFunctions = qr{(?x:
(?:(?:devm_)?
- (?:kv|k|v)[czm]alloc(?:_node|_array)? |
+ (?:kv|k|v)[czm]alloc(?:_array)?(?:_node)? |
kstrdup(?:_const)? |
kmemdup(?:_nul)?) |
(?:\w+)?alloc_skb(?:_ip_align)? |
Cc:
)};
+our $tracing_logging_tags = qr{(?xi:
+ [=-]*> |
+ <[=-]* |
+ \[ |
+ \] |
+ start |
+ called |
+ entered |
+ entry |
+ enter |
+ in |
+ inside |
+ here |
+ begin |
+ exit |
+ end |
+ done |
+ leave |
+ completed |
+ out |
+ return |
+ [\.\!:\s]*
+)};
+
+sub edit_distance_min {
+ my (@arr) = @_;
+ my $len = scalar @arr;
+ if ((scalar @arr) < 1) {
+ # if underflow, return
+ return;
+ }
+ my $min = $arr[0];
+ for my $i (0 .. ($len-1)) {
+ if ($arr[$i] < $min) {
+ $min = $arr[$i];
+ }
+ }
+ return $min;
+}
+
+sub get_edit_distance {
+ my ($str1, $str2) = @_;
+ $str1 = lc($str1);
+ $str2 = lc($str2);
+ $str1 =~ s/-//g;
+ $str2 =~ s/-//g;
+ my $len1 = length($str1);
+ my $len2 = length($str2);
+ # two dimensional array storing minimum edit distance
+ my @distance;
+ for my $i (0 .. $len1) {
+ for my $j (0 .. $len2) {
+ if ($i == 0) {
+ $distance[$i][$j] = $j;
+ } elsif ($j == 0) {
+ $distance[$i][$j] = $i;
+ } elsif (substr($str1, $i-1, 1) eq substr($str2, $j-1, 1)) {
+ $distance[$i][$j] = $distance[$i - 1][$j - 1];
+ } else {
+ my $dist1 = $distance[$i][$j - 1]; #insert distance
+ my $dist2 = $distance[$i - 1][$j]; # remove
+ my $dist3 = $distance[$i - 1][$j - 1]; #replace
+ $distance[$i][$j] = 1 + edit_distance_min($dist1, $dist2, $dist3);
+ }
+ }
+ }
+ return $distance[$len1][$len2];
+}
+
+sub find_standard_signature {
+ my ($sign_off) = @_;
+ my @standard_signature_tags = (
+ 'Signed-off-by:', 'Co-developed-by:', 'Acked-by:', 'Tested-by:',
+ 'Reviewed-by:', 'Reported-by:', 'Suggested-by:'
+ );
+ foreach my $signature (@standard_signature_tags) {
+ return $signature if (get_edit_distance($sign_off, $signature) <= 2);
+ }
+
+ return "";
+}
+
our @typeListMisordered = (
qr{char\s+(?:un)?signed},
qr{int\s+(?:(?:un)?signed\s+)?short\s},
["__ATTR", 2],
);
+my $word_pattern = '\b[A-Z]?[a-z]{2,}\b';
+
#Create a search pattern for all these functions to speed up a loop below
our $mode_perms_search = "";
foreach my $entry (@mode_permission_funcs) {
next;
}
- $$wordsRef .= '|' if ($$wordsRef ne "");
+ $$wordsRef .= '|' if (defined $$wordsRef);
$$wordsRef .= $line;
}
close($file);
return 0;
}
-my $const_structs = "";
-read_words(\$const_structs, $conststructsfile)
- or warn "No structs that should be const will be found - file '$conststructsfile': $!\n";
+my $const_structs;
+if (show_type("CONST_STRUCT")) {
+ read_words(\$const_structs, $conststructsfile)
+ or warn "No structs that should be const will be found - file '$conststructsfile': $!\n";
+}
-my $typeOtherTypedefs = "";
-if (length($typedefsfile)) {
+if (defined($typedefsfile)) {
+ my $typeOtherTypedefs;
read_words(\$typeOtherTypedefs, $typedefsfile)
or warn "No additional types will be considered - file '$typedefsfile': $!\n";
+ $typeTypedefs .= '|' . $typeOtherTypedefs if (defined $typeOtherTypedefs);
}
-$typeTypedefs .= '|' . $typeOtherTypedefs if ($typeOtherTypedefs ne "");
sub build_types {
my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)";
our $declaration_macros = qr{(?x:
(?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(|
(?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(|
- (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(|
(?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\(
)};
+our %allow_repeated_words = (
+ add => '',
+ added => '',
+ bad => '',
+ be => '',
+);
+
sub deparenthesize {
my ($string) = @_;
return "" if (!defined($string));
sub is_SPDX_License_valid {
my ($license) = @_;
- return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$root/.git"));
+ return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$gitroot"));
my $root_path = abs_path($root);
my $status = `cd "$root_path"; echo "$license" | python scripts/spdxcheck.py -`;
$camelcase_seeded = 1;
- if (-e ".git") {
+ if (-e "$gitroot") {
my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`;
chomp $git_last_include_commit;
$camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit";
return;
}
- if (-e ".git") {
+ if (-e "$gitroot") {
$files = `${git_command} ls-files "include/*.h"`;
@include_files = split('\n', $files);
}
}
}
+sub git_is_single_file {
+ my ($filename) = @_;
+
+ return 0 if ((which("git") eq "") || !(-e "$gitroot"));
+
+ my $output = `${git_command} ls-files -- $filename 2>/dev/null`;
+ my $count = $output =~ tr/\n//;
+ return $count eq 1 && $output =~ m{^${filename}$};
+}
+
sub git_commit_info {
my ($commit, $id, $desc) = @_;
- return ($id, $desc) if ((which("git") eq "") || !(-e ".git"));
+ return ($id, $desc) if ((which("git") eq "") || !(-e "$gitroot"));
my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`;
$output =~ s/^\s*//gm;
# If input is git commits, extract all commits from the commit expressions.
# For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'.
-die "$P: No git repository found\n" if ($git && !-e ".git");
+die "$P: No git repository found\n" if ($git && !-e "$gitroot");
if ($git) {
my @commits = ();
$allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"};
for my $filename (@ARGV) {
my $FILE;
+ my $is_git_file = git_is_single_file($filename);
+ my $oldfile = $file;
+ $file = 1 if ($is_git_file);
if ($git) {
open($FILE, '-|', "git format-patch -M --stdout -1 $filename") ||
die "$P: $filename: git format-patch failed - $!\n";
while (<$FILE>) {
chomp;
push(@rawlines, $_);
+ $vname = qq("$1") if ($filename eq '-' && $_ =~ m/^Subject:\s+(.+)/i);
}
close($FILE);
@modifierListFile = ();
@typeListFile = ();
build_types();
+ $file = $oldfile if ($is_git_file);
}
if (!$quiet) {
my ($formatted_email) = @_;
my $name = "";
+ my $quoted = "";
my $name_comment = "";
my $address = "";
my $comment = "";
}
}
- $name = trim($name);
- $name =~ s/^\"|\"$//g;
- $name =~ s/(\s*\([^\)]+\))\s*//;
- if (defined($1)) {
- $name_comment = trim($1);
+ # Extract comments from names excluding quoted parts
+ # "John D. (Doe)" - Do not extract
+ if ($name =~ s/\"(.+)\"//) {
+ $quoted = $1;
+ }
+ while ($name =~ s/\s*($balanced_parens)\s*/ /) {
+ $name_comment .= trim($1);
}
+ $name =~ s/^[ \"]+|[ \"]+$//g;
+ $name = trim("$quoted $name");
+
$address = trim($address);
$address =~ s/^\<|\>$//g;
+ $comment = trim($comment);
if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
}
sub format_email {
- my ($name, $address) = @_;
+ my ($name, $name_comment, $address, $comment) = @_;
my $formatted_email;
- $name = trim($name);
- $name =~ s/^\"|\"$//g;
+ $name =~ s/^[ \"]+|[ \"]+$//g;
$address = trim($address);
+ $address =~ s/(?:\.|\,|\")+$//; ##trailing commas, dots or quotes
if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
$name = "\"$name\"";
}
+ $name_comment = trim($name_comment);
+ $name_comment = " $name_comment" if ($name_comment ne "");
+ $comment = trim($comment);
+ $comment = " $comment" if ($comment ne "");
+
if ("$name" eq "") {
$formatted_email = "$address";
} else {
- $formatted_email = "$name <$address>";
+ $formatted_email = "$name$name_comment <$address>";
}
-
+ $formatted_email .= "$comment";
return $formatted_email;
}
my ($email) = @_;
my ($email_name, $name_comment, $email_address, $comment) = parse_email($email);
- return format_email($email_name, $email_address);
+ return format_email($email_name, $name_comment, $email_address, $comment);
}
sub same_email_addresses {
my ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2);
return $email1_name eq $email2_name &&
- $email1_address eq $email2_address;
+ $email1_address eq $email2_address &&
+ $name1_comment eq $name2_comment &&
+ $comment1 eq $comment2;
}
sub which {
sub ctx_locate_comment {
my ($first_line, $end_line) = @_;
+ # If c99 comment on the current line, or the line before or after
+ my ($current_comment) = ($rawlines[$end_line - 1] =~ m@^\+.*(//.*$)@);
+ return $current_comment if (defined $current_comment);
+ ($current_comment) = ($rawlines[$end_line - 2] =~ m@^[\+ ].*(//.*$)@);
+ return $current_comment if (defined $current_comment);
+ ($current_comment) = ($rawlines[$end_line] =~ m@^[\+ ].*(//.*$)@);
+ return $current_comment if (defined $current_comment);
+
# Catch a comment on the end of the line itself.
- my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
+ ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
return $current_comment if (defined $current_comment);
# Look through the context and try and figure out if there is a
splice(@lines, 1, 1);
$output = join("\n", @lines);
}
- $output = (split('\n', $output))[0] . "\n" if ($terse);
+
+ if ($terse) {
+ $output = (split('\n', $output))[0] . "\n";
+ }
+
+ if ($verbose && exists($verbose_messages{$type}) &&
+ !exists($verbose_emitted{$type})) {
+ $output .= $verbose_messages{$type} . "\n\n";
+ $verbose_emitted{$type} = 1;
+ }
push(our @report, $output);
"DEVICE_PLAT_AUTO", $herecurr);
}
+sub exclude_global_initialisers {
+ my ($realfile) = @_;
+
+ # Do not check for BPF programs (tools/testing/selftests/bpf/progs/*.c, samples/bpf/*_kern.c, *.bpf.c).
+ return $realfile =~ m@^tools/testing/selftests/bpf/progs/.*\.c$@ ||
+ $realfile =~ m@^samples/bpf/.*_kern\.c$@ ||
+ $realfile =~ m@/bpf/.*\.bpf\.c$@;
+}
+
sub process {
my $filename = shift;
my $signoff = 0;
my $author = '';
my $authorsignoff = 0;
+ my $author_sob = '';
my $is_patch = 0;
my $is_binding_patch = -1;
my $in_header_lines = $file ? 0 : 1;
if ($rawline=~/^\+\+\+\s+(\S+)/) {
$setup_docs = 0;
- if ($1 =~ m@Documentation/admin-guide/kernel-parameters.rst$@) {
+ if ($1 =~ m@Documentation/admin-guide/kernel-parameters.txt$@) {
$setup_docs = 1;
}
#next;
if (($last_binding_patch != -1) &&
($last_binding_patch ^ $is_binding_patch)) {
WARN("DT_SPLIT_BINDING_PATCH",
- "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt\n");
+ "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst\n");
}
}
# Check if the commit log has what seems like a diff which can confuse patch
if ($in_commit_log && !$commit_log_has_diff &&
- (($line =~ m@^\s+diff\b.*a/[\w/]+@ &&
- $line =~ m@^\s+diff\b.*a/([\w/]+)\s+b/$1\b@) ||
+ (($line =~ m@^\s+diff\b.*a/([\w/]+)@ &&
+ $line =~ m@^\s+diff\b.*a/[\w/]+\s+b/$1\b@) ||
$line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ ||
$line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) {
ERROR("DIFF_IN_COMMIT_MSG",
# Check the patch for a From:
if (decode("MIME-Header", $line) =~ /^From:\s*(.*)/) {
$author = $1;
+ my $curline = $linenr;
+ while(defined($rawlines[$curline]) && ($rawlines[$curline++] =~ /^[ \t]\s*(.*)/)) {
+ $author .= $1;
+ }
$author = encode("utf8", $author) if ($line =~ /=\?utf-8\?/i);
$author =~ s/"//g;
$author = reformat_email($author);
if ($line =~ /^\s*signed-off-by:\s*(.*)/i) {
$signoff++;
$in_commit_log = 0;
- if ($author ne '') {
+ if ($author ne '' && $authorsignoff != 1) {
if (same_email_addresses($1, $author)) {
$authorsignoff = 1;
+ } else {
+ my $ctx = $1;
+ my ($email_name, $email_comment, $email_address, $comment1) = parse_email($ctx);
+ my ($author_name, $author_comment, $author_address, $comment2) = parse_email($author);
+
+ if ($email_address eq $author_address && $email_name eq $author_name) {
+ $author_sob = $ctx;
+ $authorsignoff = 2;
+ } elsif ($email_address eq $author_address) {
+ $author_sob = $ctx;
+ $authorsignoff = 3;
+ } elsif ($email_name eq $author_name) {
+ $author_sob = $ctx;
+ $authorsignoff = 4;
+
+ my $address1 = $email_address;
+ my $address2 = $author_address;
+
+ if ($address1 =~ /(\S+)\+\S+(\@.*)/) {
+ $address1 = "$1$2";
+ }
+ if ($address2 =~ /(\S+)\+\S+(\@.*)/) {
+ $address2 = "$1$2";
+ }
+ if ($address1 eq $address2) {
+ $authorsignoff = 5;
+ }
+ }
}
}
}
my $ucfirst_sign_off = ucfirst(lc($sign_off));
if ($sign_off !~ /$signature_tags/) {
- WARN("BAD_SIGN_OFF",
- "Non-standard signature: $sign_off\n" . $herecurr);
+ my $suggested_signature = find_standard_signature($sign_off);
+ if ($suggested_signature eq "") {
+ WARN("BAD_SIGN_OFF",
+ "Non-standard signature: $sign_off\n" . $herecurr);
+ } else {
+ if (WARN("BAD_SIGN_OFF",
+ "Non-standard signature: '$sign_off' - perhaps '$suggested_signature'?\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/$sign_off/$suggested_signature/;
+ }
+ }
}
if (defined $space_before && $space_before ne "") {
if (WARN("BAD_SIGN_OFF",
}
my ($email_name, $name_comment, $email_address, $comment) = parse_email($email);
- my $suggested_email = format_email(($email_name, $email_address));
+ my $suggested_email = format_email(($email_name, $name_comment, $email_address, $comment));
if ($suggested_email eq "") {
ERROR("BAD_SIGN_OFF",
"Unrecognized email address: '$email'\n" . $herecurr);
# Don't force email to have quotes
# Allow just an angle bracketed address
if (!same_email_addresses($email, $suggested_email)) {
+ if (WARN("BAD_SIGN_OFF",
+ "email address '$email' might be better as '$suggested_email'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\Q$email\E/$suggested_email/;
+ }
+ }
+
+ # Address part shouldn't have comments
+ my $stripped_address = $email_address;
+ $stripped_address =~ s/\([^\(\)]*\)//g;
+ if ($email_address ne $stripped_address) {
+ if (WARN("BAD_SIGN_OFF",
+ "address part of email should not have comments: '$email_address'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\Q$email_address\E/$stripped_address/;
+ }
+ }
+
+ # Only one name comment should be allowed
+ my $comment_count = () = $name_comment =~ /\([^\)]+\)/g;
+ if ($comment_count > 1) {
WARN("BAD_SIGN_OFF",
- "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
+ "Use a single name comment in email: '$email'\n" . $herecurr);
+ }
+
+
+ # stable@vger.kernel.org or stable@kernel.org shouldn't
+ # have an email name. In addition comments should strictly
+ # begin with a #
+ if ($email =~ /^.*stable\@(?:vger\.)?kernel\.org/i) {
+ if (($comment ne "" && $comment !~ /^#.+/) ||
+ ($email_name ne "")) {
+ my $cur_name = $email_name;
+ my $new_comment = $comment;
+ $cur_name =~ s/[a-zA-Z\s\-\"]+//g;
+
+ # Remove brackets enclosing comment text
+ # and # from start of comments to get comment text
+ $new_comment =~ s/^\((.*)\)$/$1/;
+ $new_comment =~ s/^\[(.*)\]$/$1/;
+ $new_comment =~ s/^[\s\#]+|\s+$//g;
+
+ $new_comment = trim("$new_comment $cur_name") if ($cur_name ne $new_comment);
+ $new_comment = " # $new_comment" if ($new_comment ne "");
+ my $new_email = "$email_address$new_comment";
+
+ if (WARN("BAD_STABLE_ADDRESS_STYLE",
+ "Invalid email format for stable: '$email', prefer '$new_email'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/;
+ }
+ }
+ } elsif ($comment ne "" && $comment !~ /^(?:#.+|\(.+\))$/) {
+ my $new_comment = $comment;
+
+ # Extract comment text from within brackets or
+ # c89 style /*...*/ comments
+ $new_comment =~ s/^\[(.*)\]$/$1/;
+ $new_comment =~ s/^\/\*(.*)\*\/$/$1/;
+
+ $new_comment = trim($new_comment);
+ $new_comment =~ s/^[^\w]$//; # Single lettered comment with non word character is usually a typo
+ $new_comment = "($new_comment)" if ($new_comment ne "");
+ my $new_email = format_email($email_name, $name_comment, $email_address, $new_comment);
+
+ if (WARN("BAD_SIGN_OFF",
+ "Unexpected content after email: '$email', should be: '$new_email'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/;
+ }
}
}
}
if (!defined $lines[$linenr]) {
WARN("BAD_SIGN_OFF",
- "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline);
+ "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline);
} elsif ($rawlines[$linenr] !~ /^\s*signed-off-by:\s*(.*)/i) {
WARN("BAD_SIGN_OFF",
"Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]);
# Check for Gerrit Change-Ids not in any patch context
if ($realfile eq '' && !$has_patch_separator && $line =~ /^\s*change-id:/i) {
- ERROR("GERRIT_CHANGE_ID",
- "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr);
+ if (ERROR("GERRIT_CHANGE_ID",
+ "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr) &&
+ $fix) {
+ fix_delete_line($fixlinenr, $rawline);
+ }
}
# Check if the commit log is in a possible stack dump
# file delta changes
$line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ ||
# filename then :
- $line =~ /^\s*(?:Fixes:|Link:)/i ||
- # A Fixes: or Link: line
+ $line =~ /^\s*(?:Fixes:|Link:|$signature_tags)/i ||
+ # A Fixes: or Link: line or signature tag line
$commit_log_possible_stack_dump)) {
WARN("COMMIT_LOG_LONG_LINE",
"Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr);
$commit_log_possible_stack_dump = 0;
}
+# Check for lines starting with a #
+ if ($in_commit_log && $line =~ /^#/) {
+ if (WARN("COMMIT_COMMENT_SYMBOL",
+ "Commit log lines starting with '#' are dropped by git as comments\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/^/ /;
+ }
+ }
+
# Check for git id commit length and improperly formed commit descriptions
if ($in_commit_log && !$commit_log_possible_stack_dump &&
$line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i &&
($line =~ /^new file mode\s*\d+\s*$/) &&
($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) {
WARN("DT_SCHEMA_BINDING_PATCH",
- "DT bindings should be in DT schema format. See: Documentation/devicetree/writing-schema.rst\n");
+ "DT bindings should be in DT schema format. See: Documentation/devicetree/bindings/writing-schema.rst\n");
}
# Check for wrappage within a valid hunk of the file
# Check for various typo / spelling mistakes
if (defined($misspellings) &&
($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) {
- while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\b|$|[^a-z@])/gi) {
+ while ($rawline =~ /(?:^|[^\w\-'`])($misspellings)(?:[^\w\-'`]|$)/gi) {
my $typo = $1;
+ my $blank = copy_spacing($rawline);
+ my $ptr = substr($blank, 0, $-[1]) . "^" x length($typo);
+ my $hereptr = "$hereline$ptr\n";
my $typo_fix = $spelling_fix{lc($typo)};
$typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/);
$typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/);
my $msg_level = \&WARN;
$msg_level = \&CHK if ($file);
if (&{$msg_level}("TYPO_SPELLING",
- "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) &&
+ "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $hereptr) &&
$fix) {
$fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/;
}
}
}
+# check for repeated words separated by a single space
+# avoid false positive from list command eg, '-rw-r--r-- 1 root root'
+ if (($rawline =~ /^\+/ || $in_commit_log) &&
+ $rawline !~ /[bcCdDlMnpPs\?-][rwxsStT-]{9}/) {
+ pos($rawline) = 1 if (!$in_commit_log);
+ while ($rawline =~ /\b($word_pattern) (?=($word_pattern))/g) {
+
+ my $first = $1;
+ my $second = $2;
+ my $start_pos = $-[1];
+ my $end_pos = $+[2];
+ if ($first =~ /(?:struct|union|enum)/) {
+ pos($rawline) += length($first) + length($second) + 1;
+ next;
+ }
+
+ next if (lc($first) ne lc($second));
+ next if ($first eq 'long');
+
+ # check for character before and after the word matches
+ my $start_char = '';
+ my $end_char = '';
+ $start_char = substr($rawline, $start_pos - 1, 1) if ($start_pos > ($in_commit_log ? 0 : 1));
+ $end_char = substr($rawline, $end_pos, 1) if ($end_pos < length($rawline));
+
+ next if ($start_char =~ /^\S$/);
+ next if (index(" \t.,;?!", $end_char) == -1);
+
+ # avoid repeating hex occurrences like 'ff ff fe 09 ...'
+ if ($first =~ /\b[0-9a-f]{2,}\b/i) {
+ next if (!exists($allow_repeated_words{lc($first)}));
+ }
+
+ if (WARN("REPEATED_WORD",
+ "Possible repeated word: '$first'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\b$first $second\b/$first/;
+ }
+ }
+
+ # if it's a repeated word on consecutive lines in a comment block
+ if ($prevline =~ /$;+\s*$/ &&
+ $prevrawline =~ /($word_pattern)\s*$/) {
+ my $last_word = $1;
+ if ($rawline =~ /^\+\s*\*\s*$last_word /) {
+ if (WARN("REPEATED_WORD",
+ "Possible repeated word: '$last_word'\n" . $hereprev) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/(\+\s*\*\s*)$last_word /$1/;
+ }
+ }
+ }
+ }
+
# ignore non-hunk lines and lines being removed
next if (!$hunk_line || $line =~ /^-/);
if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) {
$is_start = 1;
- } elsif ($lines[$ln - 1] =~ /^\+\s*(?:help|---help---)\s*$/) {
- if ($lines[$ln - 1] =~ "---help---") {
- WARN("CONFIG_DESCRIPTION",
- "prefer 'help' over '---help---' for new help texts\n" . $herecurr);
- }
+ } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) {
$length = -1;
}
#print "is_start<$is_start> is_end<$is_end> length<$length>\n";
}
-# check for MAINTAINERS entries that don't have the right form
- if ($realfile =~ /^MAINTAINERS$/ &&
- $rawline =~ /^\+[A-Z]:/ &&
- $rawline !~ /^\+[A-Z]:\t\S/) {
- if (WARN("MAINTAINERS_STYLE",
- "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/;
+# check MAINTAINERS entries
+ if ($realfile =~ /^MAINTAINERS$/) {
+# check MAINTAINERS entries for the right form
+ if ($rawline =~ /^\+[A-Z]:/ &&
+ $rawline !~ /^\+[A-Z]:\t\S/) {
+ if (WARN("MAINTAINERS_STYLE",
+ "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/;
+ }
+ }
+# check MAINTAINERS entries for the right ordering too
+ my $preferred_order = 'MRLSWQBCPTFXNK';
+ if ($rawline =~ /^\+[A-Z]:/ &&
+ $prevrawline =~ /^[\+ ][A-Z]:/) {
+ $rawline =~ /^\+([A-Z]):\s*(.*)/;
+ my $cur = $1;
+ my $curval = $2;
+ $prevrawline =~ /^[\+ ]([A-Z]):\s*(.*)/;
+ my $prev = $1;
+ my $prevval = $2;
+ my $curindex = index($preferred_order, $cur);
+ my $previndex = index($preferred_order, $prev);
+ if ($curindex < 0) {
+ WARN("MAINTAINERS_STYLE",
+ "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr);
+ } else {
+ if ($previndex >= 0 && $curindex < $previndex) {
+ WARN("MAINTAINERS_STYLE",
+ "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev);
+ } elsif ((($prev eq 'F' && $cur eq 'F') ||
+ ($prev eq 'X' && $cur eq 'X')) &&
+ ($prevval cmp $curval) > 0) {
+ WARN("MAINTAINERS_STYLE",
+ "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev);
+ }
+ }
}
- }
-
-# discourage the use of boolean for type definition attributes of Kconfig options
- if ($realfile =~ /Kconfig/ &&
- $line =~ /^\+\s*\bboolean\b/) {
- WARN("CONFIG_TYPE_BOOLEAN",
- "Use of boolean is deprecated, please use bool instead.\n" . $herecurr);
}
if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
}
}
+# check for embedded filenames
+ if ($rawline =~ /^\+.*\Q$realfile\E/) {
+ WARN("EMBEDDED_FILENAME",
+ "It's generally not useful to have the filename in the file\n" . $herecurr);
+ }
+
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);
# check for adding lines without a newline.
if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) {
- WARN("MISSING_EOF_NEWLINE",
- "adding a line without newline at end of file\n" . $herecurr);
+ if (WARN("MISSING_EOF_NEWLINE",
+ "adding a line without newline at end of file\n" . $herecurr) &&
+ $fix) {
+ fix_delete_line($fixlinenr+1, "No newline at end of file");
+ }
+ }
+
+# check for .L prefix local symbols in .S files
+ if ($realfile =~ /\.S$/ &&
+ $line =~ /^\+\s*(?:[A-Z]+_)?SYM_[A-Z]+_(?:START|END)(?:_[A-Z_]+)?\s*\(\s*\.L/) {
+ WARN("AVOID_L_PREFIX",
+ "Avoid using '.L' prefixed local symbol names for denoting a range of code via 'SYM_*_START/END' annotations; see Documentation/asm-annotations.rst\n" . $herecurr);
}
if ($u_boot) {
# check for assignments on the start of a line
if ($sline =~ /^\+\s+($Assignment)[^=]/) {
- CHK("ASSIGNMENT_CONTINUATIONS",
- "Assignment operator '$1' should be on the previous line\n" . $hereprev);
+ my $operator = $1;
+ if (CHK("ASSIGNMENT_CONTINUATIONS",
+ "Assignment operator '$1' should be on the previous line\n" . $hereprev) &&
+ $fix && $prevrawline =~ /^\+/) {
+ # add assignment operator to the previous line, remove from current line
+ $fixed[$fixlinenr - 1] .= " $operator";
+ $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//;
+ }
}
# check for && or || at the start of a line
if ($rawline =~ /^\+\s*(&&|\|\|)/) {
- CHK("LOGICAL_CONTINUATIONS",
- "Logical continuations should be on the previous line\n" . $hereprev);
+ my $operator = $1;
+ if (CHK("LOGICAL_CONTINUATIONS",
+ "Logical continuations should be on the previous line\n" . $hereprev) &&
+ $fix && $prevrawline =~ /^\+/) {
+ # insert logical operator at last non-comment, non-whitepsace char on previous line
+ $prevline =~ /[\s$;]*$/;
+ my $line_end = substr($prevrawline, $-[0]);
+ $fixed[$fixlinenr - 1] =~ s/\Q$line_end\E$/ $operator$line_end/;
+ $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//;
+ }
}
# check indentation starts on a tab stop
if ($realfile =~ m@^(drivers/net/|net/)@ &&
$prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
$rawline =~ /^\+[ \t]*\*/ &&
- $realline > 2) {
+ $realline > 3) { # Do not warn about the initial copyright comment block after SPDX-License-Identifier
WARN("NETWORKING_BLOCK_COMMENT_STYLE",
"networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
}
}
# check for missing blank lines after declarations
- if ($sline =~ /^\+\s+\S/ && #Not at char 1
- # actual declarations
- ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
+# (declarations must have the same indentation and not be at the start of line)
+ if (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/) {
+ # use temporaries
+ my $sl = $sline;
+ my $pl = $prevline;
+ # remove $Attribute/$Sparse uses to simplify comparisons
+ $sl =~ s/\b(?:$Attribute|$Sparse)\b//g;
+ $pl =~ s/\b(?:$Attribute|$Sparse)\b//g;
+ if (($pl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
# function pointer declarations
- $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
+ $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
# foo bar; where foo is some local typedef or #define
- $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
+ $pl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
# known declaration macros
- $prevline =~ /^\+\s+$declaration_macros/) &&
+ $pl =~ /^\+\s+$declaration_macros/) &&
# for "else if" which can look like "$Ident $Ident"
- !($prevline =~ /^\+\s+$c90_Keywords\b/ ||
+ !($pl =~ /^\+\s+$c90_Keywords\b/ ||
# other possible extensions of declaration lines
- $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ ||
+ $pl =~ /(?:$Compare|$Assignment|$Operators)\s*$/ ||
# not starting a section or a macro "\" extended line
- $prevline =~ /(?:\{\s*|\\)$/) &&
+ $pl =~ /(?:\{\s*|\\)$/) &&
# looks like a declaration
- !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
+ !($sl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
# function pointer declarations
- $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
+ $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
# foo bar; where foo is some local typedef or #define
- $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
+ $sl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
# known declaration macros
- $sline =~ /^\+\s+$declaration_macros/ ||
+ $sl =~ /^\+\s+$declaration_macros/ ||
# start of struct or union or enum
- $sline =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ ||
+ $sl =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ ||
# start or end of block or continuation of declaration
- $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ ||
+ $sl =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ ||
# bitfield continuation
- $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ ||
+ $sl =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ ||
# other possible extensions of declaration lines
- $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) &&
- # indentation of previous and current line are the same
- (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) {
- if (WARN("LINE_SPACING",
- "Missing a blank line after declarations\n" . $hereprev) &&
- $fix) {
- fix_insert_line($fixlinenr, "\+");
+ $sl =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/)) {
+ if (WARN("LINE_SPACING",
+ "Missing a blank line after declarations\n" . $hereprev) &&
+ $fix) {
+ fix_insert_line($fixlinenr, "\+");
+ }
}
}
}
# check indentation of a line with a break;
-# if the previous line is a goto or return and is indented the same # of tabs
+# if the previous line is a goto, return or break
+# and is indented the same # of tabs
if ($sline =~ /^\+([\t]+)break\s*;\s*$/) {
my $tabs = $1;
- if ($prevline =~ /^\+$tabs(?:goto|return)\b/) {
- WARN("UNNECESSARY_BREAK",
- "break is not useful after a goto or return\n" . $hereprev);
+ if ($prevline =~ /^\+$tabs(goto|return|break)\b/) {
+ if (WARN("UNNECESSARY_BREAK",
+ "break is not useful after a $1\n" . $hereprev) &&
+ $fix) {
+ fix_delete_line($fixlinenr, $rawline);
+ }
}
}
#ignore lines not being added
next if ($line =~ /^[^\+]/);
+# check for self assignments used to avoid compiler warnings
+# e.g.: int foo = foo, *bar = NULL;
+# struct foo bar = *(&(bar));
+ if ($line =~ /^\+\s*(?:$Declare)?([A-Za-z_][A-Za-z\d_]*)\s*=/) {
+ my $var = $1;
+ if ($line =~ /^\+\s*(?:$Declare)?$var\s*=\s*(?:$var|\*\s*\(?\s*&\s*\(?\s*$var\s*\)?\s*\)?)\s*[;,]/) {
+ WARN("SELF_ASSIGNMENT",
+ "Do not use self-assignments to avoid compiler warnings\n" . $herecurr);
+ }
+ }
+
# check for dereferences that span multiple lines
if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ &&
$line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) {
if (defined $realline_next &&
exists $lines[$realline_next - 1] &&
!defined $suppress_export{$realline_next} &&
- ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
- $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+ ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/)) {
# Handle definitions which produce identifiers with
# a prefix:
# XXX(foo);
}
if (!defined $suppress_export{$linenr} &&
$prevline =~ /^.\s*$/ &&
- ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
- $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+ ($line =~ /EXPORT_SYMBOL.*\((.*)\)/)) {
#print "FOO B <$lines[$linenr - 1]>\n";
$suppress_export{$linenr} = 2;
}
}
# check for global initialisers.
- if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/) {
+ if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/ &&
+ !exclude_global_initialisers($realfile)) {
if (ERROR("GLOBAL_INITIALISERS",
"do not initialise globals to $1\n" . $herecurr) &&
$fix) {
}
}
+# check for const static or static <non ptr type> const declarations
+# prefer 'static const <foo>' over 'const static <foo>' and 'static <foo> const'
+ if ($sline =~ /^\+\s*const\s+static\s+($Type)\b/ ||
+ $sline =~ /^\+\s*static\s+($BasicType)\s+const\b/) {
+ if (WARN("STATIC_CONST",
+ "Move const after static - use 'static const $1'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bconst\s+static\b/static const/;
+ $fixed[$fixlinenr] =~ s/\bstatic\s+($BasicType)\s+const\b/static const $1/;
+ }
+ }
+
# check for non-global char *foo[] = {"bar", ...} declarations.
if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) {
WARN("STATIC_CONST_CHAR_ARRAY",
"char * array declaration might be better as static const\n" .
$herecurr);
- }
+ }
# check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo)
if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) {
"printk() should include KERN_<LEVEL> facility level\n" . $herecurr);
}
- if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
- my $orig = $1;
+# prefer variants of (subsystem|netdev|dev|pr)_<level> to printk(KERN_<LEVEL>
+ if ($line =~ /\b(printk(_once|_ratelimited)?)\s*\(\s*KERN_([A-Z]+)/) {
+ my $printk = $1;
+ my $modifier = $2;
+ my $orig = $3;
+ $modifier = "" if (!defined($modifier));
my $level = lc($orig);
$level = "warn" if ($level eq "warning");
my $level2 = $level;
$level2 = "dbg" if ($level eq "debug");
+ $level .= $modifier;
+ $level2 .= $modifier;
WARN("PREFER_PR_LEVEL",
- "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr);
+ "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to $printk(KERN_$orig ...\n" . $herecurr);
}
+# prefer dev_<level> to dev_printk(KERN_<LEVEL>
if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
my $orig = $1;
my $level = lc($orig);
"Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
}
+# trace_printk should not be used in production code.
+ if ($line =~ /\b(trace_printk|trace_puts|ftrace_vprintk)\s*\(/) {
+ WARN("TRACE_PRINTK",
+ "Do not use $1() in production code (this can be ignored if built only with a debug config option)\n" . $herecurr);
+ }
+
# ENOSYS means "bad syscall nr" and nothing else. This will have a small
# number of false positives, but assembly files are not checked, so at
# least the arch entry code will not trigger this warning.
"ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr);
}
+# ENOTSUPP is not a standard error code and should be avoided in new patches.
+# Folks usually mean EOPNOTSUPP (also called ENOTSUP), when they type ENOTSUPP.
+# Similarly to ENOSYS warning a small number of false positives is expected.
+ if (!$file && $line =~ /\bENOTSUPP\b/) {
+ if (WARN("ENOTSUPP",
+ "ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bENOTSUPP\b/EOPNOTSUPP/;
+ }
+ }
+
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
if ($perl_version_ok &&
$fix) {
fix_delete_line($fixlinenr, $rawline);
my $fixed_line = $rawline;
- $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*){(.*)$/;
+ $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*)\{(.*)$/;
my $line1 = $1;
my $line2 = $2;
fix_insert_line($fixlinenr, ltrim($line1));
# A colon needs no spaces before when it is
# terminating a case value or a label.
} elsif ($opv eq ':C' || $opv eq ':L') {
- if ($ctx =~ /Wx./) {
+ if ($ctx =~ /Wx./ and $realfile !~ m@.*\.lds\.h$@) {
if (ERROR("SPACING",
"space prohibited before that '$op' $at\n" . $hereptr)) {
$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) {
##
## # Remove any bracketed sections to ensure we do not
-## # falsly report the parameters of functions.
+## # falsely report the parameters of functions.
## my $ln = $line;
## while ($ln =~ s/\([^\(\)]*\)//g) {
## }
}
}
+# check if a statement with a comma should be two statements like:
+# foo = bar(), /* comma should be semicolon */
+# bar = baz();
+ if (defined($stat) &&
+ $stat =~ /^\+\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*,\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*;\s*$/) {
+ my $cnt = statement_rawlines($stat);
+ my $herectx = get_stat_here($linenr, $cnt, $here);
+ WARN("SUSPECT_COMMA_SEMICOLON",
+ "Possible comma where semicolon could be used\n" . $herectx);
+ }
+
# return is not a function
if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) {
my $spacing = $1;
$lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) {
WARN("RETURN_VOID",
"void function return statements are not generally useful\n" . $hereprev);
- }
+ }
# if statements using unnecessary parentheses - ie: if ((foo == bar))
if ($perl_version_ok &&
my ($s, $c) = ($stat, $cond);
if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) {
- ERROR("ASSIGN_IN_IF",
- "do not use assignment in if condition\n" . $herecurr);
+ if (ERROR("ASSIGN_IN_IF",
+ "do not use assignment in if condition\n" . $herecurr) &&
+ $fix && $perl_version_ok) {
+ if ($rawline =~ /^\+(\s+)if\s*\(\s*(\!)?\s*\(\s*(($Lval)\s*=\s*$LvalOrFunc)\s*\)\s*(?:($Compare)\s*($FuncArg))?\s*\)\s*(\{)?\s*$/) {
+ my $space = $1;
+ my $not = $2;
+ my $statement = $3;
+ my $assigned = $4;
+ my $test = $8;
+ my $against = $9;
+ my $brace = $15;
+ fix_delete_line($fixlinenr, $rawline);
+ fix_insert_line($fixlinenr, "$space$statement;");
+ my $newline = "${space}if (";
+ $newline .= '!' if defined($not);
+ $newline .= '(' if (defined $not && defined($test) && defined($against));
+ $newline .= "$assigned";
+ $newline .= " $test $against" if (defined($test) && defined($against));
+ $newline .= ')' if (defined $not && defined($test) && defined($against));
+ $newline .= ')';
+ $newline .= " {" if (defined($brace));
+ fix_insert_line($fixlinenr + 1, $newline);
+ }
+ }
}
# Find out what is on the end of the line after the
#CamelCase
if ($var !~ /^$Constant$/ &&
$var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&
+#Ignore some autogenerated defines and enum values
+ $var !~ /^(?:[A-Z]+_){1,5}[A-Z]{1,3}[a-z]/ &&
#Ignore Page<foo> variants
$var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
#Ignore SI style variants like nS, mV and dB
$dstat =~ s/\s*$//s;
# Flatten any parentheses and braces
- while ($dstat =~ s/\([^\(\)]*\)/1/ ||
- $dstat =~ s/\{[^\{\}]*\}/1/ ||
- $dstat =~ s/.\[[^\[\]]*\]/1/)
+ while ($dstat =~ s/\([^\(\)]*\)/1u/ ||
+ $dstat =~ s/\{[^\{\}]*\}/1u/ ||
+ $dstat =~ s/.\[[^\[\]]*\]/1u/)
{
}
$dstat !~ /^\.$Ident\s*=/ && # .foo =
$dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo
$dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...)
+ $dstat !~ /^while\s*$Constant\s*$Constant\s*$/ && # while (...) {...}
$dstat !~ /^for\s*$Constant$/ && # for (...)
$dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar()
$dstat !~ /^do\s*{/ && # do {...
next if ($arg =~ /\.\.\./);
next if ($arg =~ /^type$/i);
my $tmp_stmt = $define_stmt;
- $tmp_stmt =~ s/\b(sizeof|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
+ $tmp_stmt =~ s/\b(__must_be_array|offsetof|sizeof|sizeof_field|__stringify|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
$tmp_stmt =~ s/\#+\s*$arg\b//g;
$tmp_stmt =~ s/\b$arg\s*\#\#//g;
my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g;
"Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr);
}
+# check for unnecessary function tracing like uses
+# This does not use $logFunctions because there are many instances like
+# 'dprintk(FOO, "%s()\n", __func__);' which do not match $logFunctions
+ if ($rawline =~ /^\+.*\([^"]*"$tracing_logging_tags{0,3}%s(?:\s*\(\s*\)\s*)?$tracing_logging_tags{0,3}(?:\\n)?"\s*,\s*__func__\s*\)\s*;/) {
+ if (WARN("TRACING_LOGGING",
+ "Unnecessary ftrace-like logging - prefer using ftrace\n" . $herecurr) &&
+ $fix) {
+ fix_delete_line($fixlinenr, $rawline);
+ }
+ }
+
# check for spaces before a quoted newline
if ($rawline =~ /^.*\".*\s\\n/) {
if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
"Avoid logging continuation uses where feasible\n" . $herecurr);
}
+# check for unnecessary use of %h[xudi] and %hh[xudi] in logging functions
+ if (defined $stat &&
+ $line =~ /\b$logFunctions\s*\(/ &&
+ index($stat, '"') >= 0) {
+ my $lc = $stat =~ tr@\n@@;
+ $lc = $lc + $linenr;
+ my $stat_real = get_stat_real($linenr, $lc);
+ pos($stat_real) = index($stat_real, '"');
+ while ($stat_real =~ /[^\"%]*(%[\#\d\.\*\-]*(h+)[idux])/g) {
+ my $pspec = $1;
+ my $h = $2;
+ my $lineoff = substr($stat_real, 0, $-[1]) =~ tr@\n@@;
+ if (WARN("UNNECESSARY_MODIFIER",
+ "Integer promotion: Using '$h' in '$pspec' is unnecessary\n" . "$here\n$stat_real\n") &&
+ $fix && $fixed[$fixlinenr + $lineoff] =~ /^\+/) {
+ my $nspec = $pspec;
+ $nspec =~ s/h//g;
+ $fixed[$fixlinenr + $lineoff] =~ s/\Q$pspec\E/$nspec/;
+ }
+ }
+ }
+
# check for mask then right shift without a parentheses
if ($perl_version_ok &&
$line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ &&
my $barriers = qr{
mb|
rmb|
- wmb|
- read_barrier_depends
+ wmb
}x;
my $barrier_stems = qr{
mb__before_atomic|
}
}
-# check for smp_read_barrier_depends and read_barrier_depends
- if (!$file && $line =~ /\b(smp_|)read_barrier_depends\s*\(/) {
- WARN("READ_BARRIER_DEPENDS",
- "$1read_barrier_depends should only be used in READ_ONCE or DEC Alpha code\n" . $herecurr);
+# check for data_race without a comment.
+ if ($line =~ /\bdata_race\s*\(/) {
+ if (!ctx_has_comment($first_line, $linenr)) {
+ WARN("DATA_RACE",
+ "data_race without comment\n" . $herecurr);
+ }
}
# check of hardware specific defines
}
}
-# Check for __attribute__ packed, prefer __packed
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
- WARN("PREFER_PACKED",
- "__packed is preferred over __attribute__((packed))\n" . $herecurr);
- }
-
-# Check for __attribute__ aligned, prefer __aligned
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
- WARN("PREFER_ALIGNED",
- "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
- }
-
-# Check for __attribute__ section, prefer __section
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(.*_*section_*\s*\(\s*("[^"]*")/) {
- my $old = substr($rawline, $-[1], $+[1] - $-[1]);
- my $new = substr($old, 1, -1);
- if (WARN("PREFER_SECTION",
- "__section(\"$new\") is preferred over __attribute__((section($old)))\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/;
- }
- }
-
-# Check for __attribute__ format(printf, prefer __printf
+# Check for compiler attributes
if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
- if (WARN("PREFER_PRINTF",
- "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex;
-
+ $rawline =~ /\b__attribute__\s*\(\s*($balanced_parens)\s*\)/) {
+ my $attr = $1;
+ $attr =~ s/\s*\(\s*(.*)\)\s*/$1/;
+
+ my %attr_list = (
+ "alias" => "__alias",
+ "aligned" => "__aligned",
+ "always_inline" => "__always_inline",
+ "assume_aligned" => "__assume_aligned",
+ "cold" => "__cold",
+ "const" => "__attribute_const__",
+ "copy" => "__copy",
+ "designated_init" => "__designated_init",
+ "externally_visible" => "__visible",
+ "format" => "printf|scanf",
+ "gnu_inline" => "__gnu_inline",
+ "malloc" => "__malloc",
+ "mode" => "__mode",
+ "no_caller_saved_registers" => "__no_caller_saved_registers",
+ "noclone" => "__noclone",
+ "noinline" => "noinline",
+ "nonstring" => "__nonstring",
+ "noreturn" => "__noreturn",
+ "packed" => "__packed",
+ "pure" => "__pure",
+ "section" => "__section",
+ "used" => "__used",
+ "weak" => "__weak"
+ );
+
+ while ($attr =~ /\s*(\w+)\s*(${balanced_parens})?/g) {
+ my $orig_attr = $1;
+ my $params = '';
+ $params = $2 if defined($2);
+ my $curr_attr = $orig_attr;
+ $curr_attr =~ s/^[\s_]+|[\s_]+$//g;
+ if (exists($attr_list{$curr_attr})) {
+ my $new = $attr_list{$curr_attr};
+ if ($curr_attr eq "format" && $params) {
+ $params =~ /^\s*\(\s*(\w+)\s*,\s*(.*)/;
+ $new = "__$1\($2";
+ } else {
+ $new = "$new$params";
+ }
+ if (WARN("PREFER_DEFINED_ATTRIBUTE_MACRO",
+ "Prefer $new over __attribute__(($orig_attr$params))\n" . $herecurr) &&
+ $fix) {
+ my $remove = "\Q$orig_attr\E" . '\s*' . "\Q$params\E" . '(?:\s*,\s*)?';
+ $fixed[$fixlinenr] =~ s/$remove//;
+ $fixed[$fixlinenr] =~ s/\b__attribute__/$new __attribute__/;
+ $fixed[$fixlinenr] =~ s/\}\Q$new\E/} $new/;
+ $fixed[$fixlinenr] =~ s/ __attribute__\s*\(\s*\(\s*\)\s*\)//;
+ }
+ }
}
- }
-# Check for __attribute__ format(scanf, prefer __scanf
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
- if (WARN("PREFER_SCANF",
- "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex;
+ # Check for __attribute__ unused, prefer __always_unused or __maybe_unused
+ if ($attr =~ /^_*unused/) {
+ WARN("PREFER_DEFINED_ATTRIBUTE_MACRO",
+ "__always_unused or __maybe_unused is preferred over __attribute__((__unused__))\n" . $herecurr);
}
}
if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) {
my $cast = $1;
my $const = $2;
+ my $suffix = "";
+ my $newconst = $const;
+ $newconst =~ s/${Int_type}$//;
+ $suffix .= 'U' if ($cast =~ /\bunsigned\b/);
+ if ($cast =~ /\blong\s+long\b/) {
+ $suffix .= 'LL';
+ } elsif ($cast =~ /\blong\b/) {
+ $suffix .= 'L';
+ }
if (WARN("TYPECAST_INT_CONSTANT",
- "Unnecessary typecast of c90 int constant\n" . $herecurr) &&
+ "Unnecessary typecast of c90 int constant - '$cast$const' could be '$const$suffix'\n" . $herecurr) &&
$fix) {
- my $suffix = "";
- my $newconst = $const;
- $newconst =~ s/${Int_type}$//;
- $suffix .= 'U' if ($cast =~ /\bunsigned\b/);
- if ($cast =~ /\blong\s+long\b/) {
- $suffix .= 'LL';
- } elsif ($cast =~ /\blong\b/) {
- $suffix .= 'L';
- }
$fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/;
}
}
$specifier = $1;
$extension = $2;
$qualifier = $3;
- if ($extension !~ /[SsBKRraEehMmIiUDdgVCbGNOxtf]/ ||
+ if ($extension !~ /[4SsBKRraEehMmIiUDdgVCbGNOxtf]/ ||
($extension eq "f" &&
- defined $qualifier && $qualifier !~ /^w/)) {
+ defined $qualifier && $qualifier !~ /^w/) ||
+ ($extension eq "4" &&
+ defined $qualifier && $qualifier !~ /^cc/)) {
$bad_specifier = $specifier;
last;
}
if (defined $cond) {
substr($s, 0, length($cond), '');
}
- if ($s =~ /^\s*;/ &&
- $function_name ne 'uninitialized_var')
+ if ($s =~ /^\s*;/)
{
WARN("AVOID_EXTERNS",
"externs should be avoided in .c files\n" . $herecurr);
}
# check for function declarations that have arguments without identifier names
-# while avoiding uninitialized_var(x)
if (defined $stat &&
- $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:($Ident)|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s &&
- (!defined($1) ||
- (defined($1) && $1 ne "uninitialized_var")) &&
- $2 ne "void") {
- my $args = trim($2);
+ $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s &&
+ $1 ne "void") {
+ my $args = trim($1);
while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) {
my $arg = trim($1);
- if ($arg =~ /^$Type$/ &&
- $arg !~ /enum\s+$Ident$/) {
+ if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) {
WARN("FUNCTION_ARGUMENTS",
"function definition argument '$arg' should also have an identifier name\n" . $herecurr);
}
if (!grep(/$name/, @setup_docs)) {
CHK("UNDOCUMENTED_SETUP",
- "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.rst\n" . $herecurr);
+ "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.txt\n" . $herecurr);
}
}
}
# check for alloc argument mismatch
- if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
+ if ($line =~ /\b((?:devm_)?(?:kcalloc|kmalloc_array))\s*\(\s*sizeof\b/) {
WARN("ALLOC_ARRAY_ARGS",
"$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
}
}
}
+# check for IS_ENABLED() without CONFIG_<FOO> ($rawline for comments too)
+ if ($rawline =~ /\bIS_ENABLED\s*\(\s*(\w+)\s*\)/ && $1 !~ /^${CONFIG_}/) {
+ WARN("IS_ENABLED_CONFIG",
+ "IS_ENABLED($1) is normally used as IS_ENABLED(${CONFIG_}$1)\n" . $herecurr);
+ }
+
# check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE
- if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) {
+ if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(${CONFIG_}[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) {
my $config = $1;
if (WARN("PREFER_IS_ENABLED",
- "Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE\n" . $herecurr) &&
+ "Prefer IS_ENABLED(<FOO>) to ${CONFIG_}<FOO> || ${CONFIG_}<FOO>_MODULE\n" . $herecurr) &&
$fix) {
$fixed[$fixlinenr] = "\+#if IS_ENABLED($config)";
}
}
-# check for case / default statements not preceded by break/fallthrough/switch
- if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) {
- my $has_break = 0;
- my $has_statement = 0;
- my $count = 0;
- my $prevline = $linenr;
- while ($prevline > 1 && ($file || $count < 3) && !$has_break) {
- $prevline--;
- my $rline = $rawlines[$prevline - 1];
- my $fline = $lines[$prevline - 1];
- last if ($fline =~ /^\@\@/);
- next if ($fline =~ /^\-/);
- next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/);
- $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i);
- next if ($fline =~ /^.[\s$;]*$/);
- $has_statement = 1;
- $count++;
- $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|exit\s*\(\b|return\b|goto\b|continue\b)/);
- }
- if (!$has_break && $has_statement) {
- WARN("MISSING_BREAK",
- "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr);
- }
- }
-
# check for /* fallthrough */ like comment, prefer fallthrough;
my @fallthroughs = (
'fallthrough',
# check for various structs that are normally const (ops, kgdb, device_tree)
# and avoid what seem like struct definitions 'struct foo {'
- if ($line !~ /\bconst\b/ &&
+ if (defined($const_structs) &&
+ $line !~ /\bconst\b/ &&
$line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) {
WARN("CONST_STRUCT",
"struct $1 should normally be const\n" . $herecurr);
# use of NR_CPUS is usually wrong
# ignore definitions of NR_CPUS and usage to define arrays as likely right
+# ignore designated initializers using NR_CPUS
if ($line =~ /\bNR_CPUS\b/ &&
$line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ &&
$line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ &&
$line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ &&
$line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ &&
- $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/)
+ $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/ &&
+ $line !~ /^.\s*\.\w+\s*=\s*.*\bNR_CPUS\b/)
{
WARN("NR_CPUS",
"usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
"Using $1 should generally have parentheses around the comparison\n" . $herecurr);
}
+# return sysfs_emit(foo, fmt, ...) fmt without newline
+ if ($line =~ /\breturn\s+sysfs_emit\s*\(\s*$FuncArg\s*,\s*($String)/ &&
+ substr($rawline, $-[6], $+[6] - $-[6]) !~ /\\n"$/) {
+ my $offset = $+[6] - 1;
+ if (WARN("SYSFS_EMIT",
+ "return sysfs_emit(...) formats should include a terminating newline\n" . $herecurr) &&
+ $fix) {
+ substr($fixed[$fixlinenr], $offset, 0) = '\\n';
+ }
+ }
+
# nested likely/unlikely calls
if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) {
WARN("LIKELY_MISUSE",
}
}
-# check for mutex_trylock_recursive usage
- if ($line =~ /mutex_trylock_recursive/) {
- ERROR("LOCKING",
- "recursive locking is bad, do not use this ever.\n" . $herecurr);
- }
-
# check for lockdep_set_novalidate_class
if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
$line =~ /__lockdep_no_validate__\s*\)/ ) {
exit(0);
}
- # This is not a patch, and we are are in 'no-patch' mode so
+ # This is not a patch, and we are in 'no-patch' mode so
# just keep quiet.
if (!$chk_patch && !$is_patch) {
exit(0);
if ($signoff == 0) {
ERROR("MISSING_SIGN_OFF",
"Missing Signed-off-by: line(s)\n");
- } elsif (!$authorsignoff) {
- WARN("NO_AUTHOR_SIGN_OFF",
- "Missing Signed-off-by: line by nominal patch author '$author'\n");
+ } elsif ($authorsignoff != 1) {
+ # authorsignoff values:
+ # 0 -> missing sign off
+ # 1 -> sign off identical
+ # 2 -> names and addresses match, comments mismatch
+ # 3 -> addresses match, names different
+ # 4 -> names match, addresses different
+ # 5 -> names match, addresses excluding subaddress details (refer RFC 5233) match
+
+ my $sob_msg = "'From: $author' != 'Signed-off-by: $author_sob'";
+
+ if ($authorsignoff == 0) {
+ ERROR("NO_AUTHOR_SIGN_OFF",
+ "Missing Signed-off-by: line by nominal patch author '$author'\n");
+ } elsif ($authorsignoff == 2) {
+ CHK("FROM_SIGN_OFF_MISMATCH",
+ "From:/Signed-off-by: email comments mismatch: $sob_msg\n");
+ } elsif ($authorsignoff == 3) {
+ WARN("FROM_SIGN_OFF_MISMATCH",
+ "From:/Signed-off-by: email name mismatch: $sob_msg\n");
+ } elsif ($authorsignoff == 4) {
+ WARN("FROM_SIGN_OFF_MISMATCH",
+ "From:/Signed-off-by: email address mismatch: $sob_msg\n");
+ } elsif ($authorsignoff == 5) {
+ WARN("FROM_SIGN_OFF_MISMATCH",
+ "From:/Signed-off-by: email subaddress mismatch: $sob_msg\n");
+ }
}
}
- miiphy_register(devname, readfunc, writefunc);
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev) return -ENOMEM;
-+ strncpy(mdiodev->name, devname, MDIO_NAME_LEN);
++ strlcpy(mdiodev->name, devname, MDIO_NAME_LEN);
+ mdiodev->read = readfunc;
+ mdiodev->write = writefunc;
+
+ retval = mdio_register(mdiodev);
-+ if (retval < 0) return retval;
++ if (retval < 0) { mdio_free(mdiodev); return retval; }
@ update_read_sig @
identifier mii_reg.readfunc;
-CONFIG_16BIT
CONFIG_64BIT_PHYS_ADDR
-CONFIG_8349_CLKIN
CONFIG_83XX
-CONFIG_83XX_CLKIN
-CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
CONFIG_83XX_PCICLK
-CONFIG_83XX_PCI_STREAMING
CONFIG_88F5182
CONFIG_A003399_NOR_WORKAROUND
CONFIG_A008044_WORKAROUND
-CONFIG_ACX517AKN
-CONFIG_ACX544AKN
-CONFIG_ADDRESS
-CONFIG_ADDR_AUTO_INCR_BIT
-CONFIG_ADNPESC1
CONFIG_AEABI
-CONFIG_AEMIF_CNTRL_BASE
-CONFIG_ALTERA_SPI_IDLE_VAL
-CONFIG_ALU
CONFIG_AM335X_USB0
CONFIG_AM335X_USB0_MODE
CONFIG_AM335X_USB1
CONFIG_AM335X_USB1_MODE
-CONFIG_AM437X_USB2PHY2_HOST
CONFIG_ANDES_PCU
CONFIG_ANDES_PCU_BASE
-CONFIG_APER_0_BASE
-CONFIG_APER_1_BASE
-CONFIG_APER_SIZE
-CONFIG_APUS_FAST_EXCEPT
CONFIG_ARCH_ADPAG101P
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARCH_HAS_ILOG2_U64
CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
CONFIG_ARCH_USE_BUILTIN_BSWAP
CONFIG_ARC_MMU_VER
-CONFIG_ARMADA100
-CONFIG_ARMADA168
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ARMV7_SECURE_RESERVE_SIZE
CONFIG_ARMV8_SWITCH_TO_EL1
-CONFIG_ARM_ARCH_CP15_ERRATA
CONFIG_ARM_GIC_BASE_ADDRESS
-CONFIG_ARM_PL180_MMCI_BASE
-CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
CONFIG_ARP_TIMEOUT
-CONFIG_ASTRO_COFDMDUOS2
-CONFIG_ASTRO_TWIN7S2
-CONFIG_ASTRO_V512
-CONFIG_ASTRO_V532
-CONFIG_ASTRO_V912
CONFIG_AT91C_PQFP_UHPBUG
CONFIG_AT91RESET_EXTRST
CONFIG_AT91RM9200
CONFIG_ATMEL_LEGACY
CONFIG_ATMEL_MCI_8BIT
CONFIG_ATMEL_SPI0
-CONFIG_AT_TRANS
CONFIG_AUTO_ZRELADDR
CONFIG_BACKSIDE_L2_CACHE
CONFIG_BCH_CONST_M
CONFIG_BOARD_POSTCLK_INIT
CONFIG_BOARD_SIZE_LIMIT
CONFIG_BOOGER
-CONFIG_BOOTBLOCK
CONFIG_BOOTFILE
CONFIG_BOOTMODE
CONFIG_BOOTP_
CONFIG_BOOTSCRIPT_COPY_RAM
CONFIG_BOOTSCRIPT_HDR_ADDR
CONFIG_BOOTSCRIPT_KEY_HASH
-CONFIG_BOOT_MODE_BIT
CONFIG_BOOT_RETRY_MIN
CONFIG_BOOT_RETRY_TIME
CONFIG_BPTR_VIRT_ADDR
CONFIG_BS_HDR_SIZE
CONFIG_BS_SIZE
CONFIG_BTB
-CONFIG_BUFNO_AUTO_INCR_BIT
CONFIG_BUILD_ENVCRC
CONFIG_BUS_WIDTH
CONFIG_CDP_APPLIANCE_VLAN_TYPE
CONFIG_CLOCK_SYNTHESIZER
CONFIG_CM922T_XA10
CONFIG_CMDLINE_PS_SUPPORT
-CONFIG_CMDLINE_TAG
CONFIG_CM_INIT
CONFIG_CM_MULTIPLE_SSRAM
CONFIG_CM_REMAP
CONFIG_CM_SPD_DETECT
-CONFIG_CM_T335
-CONFIG_CM_T3X
-CONFIG_CM_T43
CONFIG_CM_TCRAM
-CONFIG_CNTL
CONFIG_COLDFIRE
CONFIG_COMMANDS
CONFIG_COMMON_BOOT
CONFIG_DCACHE
CONFIG_DCACHE_OFF
CONFIG_DCFG_ADDR
-CONFIG_DDR3
-CONFIG_DDR_2T_TIMING
-CONFIG_DDR_32BIT
-CONFIG_DDR_64BIT
-CONFIG_DDR_CLK_FREQ
-CONFIG_DDR_DEFAULT_CL
-CONFIG_DDR_ECC
-CONFIG_DDR_ECC_CMD
-CONFIG_DDR_ECC_INIT_VIA_DMA
-CONFIG_DDR_FIXED_SIZE
-CONFIG_DDR_II
-CONFIG_DDR_LOG_LEVEL
-CONFIG_DDR_MB
-CONFIG_DDR_SPD
CONFIG_DEBUG
CONFIG_DEBUG_FS
CONFIG_DEBUG_LED
CONFIG_DM9000_USE_16BIT
CONFIG_DMA_COHERENT
CONFIG_DMA_COHERENT_SIZE
-CONFIG_DMA_LPC32XX
CONFIG_DMA_NONCOHERENT
-CONFIG_DMA_REQ_BIT
CONFIG_DNET_AUTONEG_TIMEOUT
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
CONFIG_DRAM_TIMINGS_
-CONFIG_DRIVER_AT91EMAC_PHYADDR
-CONFIG_DRIVER_AT91EMAC_QUIET
CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
-CONFIG_DWC2_DFLT_SPEED_FULL
-CONFIG_DWC2_DMA_BURST_SIZE
-CONFIG_DWC2_DMA_ENABLE
-CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
-CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
-CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
-CONFIG_DWC2_HOST_RX_FIFO_SIZE
-CONFIG_DWC2_I2C_ENABLE
-CONFIG_DWC2_IC_USB_CAP
-CONFIG_DWC2_MAX_CHANNELS
-CONFIG_DWC2_MAX_PACKET_COUNT
-CONFIG_DWC2_MAX_TRANSFER_SIZE
-CONFIG_DWC2_PHY_TYPE
-CONFIG_DWC2_PHY_ULPI_DDR
-CONFIG_DWC2_PHY_ULPI_EXT_VBUS
-CONFIG_DWC2_THR_CTL
-CONFIG_DWC2_TS_DLINE
-CONFIG_DWC2_TX_THR_LENGTH
-CONFIG_DWC2_ULPI_FS_LS
-CONFIG_DWC2_UTMI_WIDTH
CONFIG_DWCDDR21MCTL
CONFIG_DWCDDR21MCTL_BASE
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_E300
CONFIG_E5500
CONFIG_ECC
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-CONFIG_ECC_MODE_MASK
-CONFIG_ECC_MODE_SHIFT
-CONFIG_ECC_SRAM_ADDR_MASK
-CONFIG_ECC_SRAM_ADDR_SHIFT
-CONFIG_ECC_SRAM_REQ_BIT
CONFIG_EDB9301
CONFIG_EDB93XX_INDUSTRIAL
CONFIG_EDB93XX_SDCS0
CONFIG_ENV_ADDR_FLEX
CONFIG_ENV_CALLBACK_LIST_DEFAULT
CONFIG_ENV_CALLBACK_LIST_STATIC
-CONFIG_ENV_COMMON_BOOT
-CONFIG_ENV_EEPROM_IS_ON_I2C
CONFIG_ENV_FLAGS_LIST_DEFAULT
CONFIG_ENV_FLAGS_LIST_STATIC
-CONFIG_ENV_FLASHBOOT
CONFIG_ENV_IS_EMBEDDED
CONFIG_ENV_IS_IN_
CONFIG_ENV_MAX_ENTRIES
CONFIG_ENV_SIZE_FLEX
CONFIG_ENV_SROM_BANK
CONFIG_ENV_TOTAL_SIZE
-CONFIG_ENV_UBIFS_OPTION
-CONFIG_ENV_UBI_MTD
CONFIG_ENV_VERSION
CONFIG_EPH_POWER_EN
CONFIG_EPOLL
CONFIG_ET1100_BASE
CONFIG_ETHADDR
CONFIG_ETHBASE
-CONFIG_ETHER_INDEX
-CONFIG_ETHER_NONE
-CONFIG_ETHER_ON_FCC
-CONFIG_ETHER_ON_FCC1
-CONFIG_ETHER_ON_FCC2
-CONFIG_ETHER_ON_FCC3
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
CONFIG_EXTRA_CLOCK
CONFIG_EXTRA_ENV
-CONFIG_EXTRA_ENV_BOARD_SETTINGS
-CONFIG_EXTRA_ENV_ITB
-CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS_COMMON
CONFIG_EXT_AHB2AHB_BASE
CONFIG_EXYNOS_SPL
CONFIG_EXYNOS_TMU
CONFIG_FACTORYSET
-CONFIG_FAST_FLASH_BIT
CONFIG_FB_ADDR
CONFIG_FB_BACKLIGHT
CONFIG_FB_DEFERRED_IO
CONFIG_FSL_DEVICE_DISABLE
CONFIG_FSL_DIU_CH7301
CONFIG_FSL_DIU_FB
-CONFIG_FSL_DMA
CONFIG_FSL_DSPI1
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_FIXED_MMC_LOCATION
CONFIG_FTWDT010_WATCHDOG
CONFIG_FZOTG266HD0A_BASE
CONFIG_GATEWAYIP
-CONFIG_GICV2
CONFIG_GLOBAL_DATA_NOT_REG10
CONFIG_GLOBAL_TIMER
CONFIG_GMII
CONFIG_HAS_FEC
CONFIG_HAS_FSL_DR_USB
CONFIG_HAS_FSL_MPH_USB
-CONFIG_HDBOOT
CONFIG_HDMI_ENCODER_I2C_ADDR
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_HIDE_LOGO_VERSION
CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
CONFIG_HSMMC2_8BIT
CONFIG_HUSH_INIT_VAR
-CONFIG_HVBOOT
CONFIG_HWCONFIG
CONFIG_HW_ENV_SETTINGS
CONFIG_I2C_ENV_EEPROM_BUS
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
CONFIG_IDE_SWAP_IO
-CONFIG_ID_EEPROM
CONFIG_IMA
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
-CONFIG_IMX_NAND
CONFIG_IMX_VIDEO_SKIP
CONFIG_INETSPACE_V2
-CONFIG_INITRD_TAG
CONFIG_INIT_IGNORE_ERROR
CONFIG_INI_ALLOW_MULTILINE
CONFIG_INI_CASE_INSENSITIVE
CONFIG_JFFS2_SUMMARY
CONFIG_JRSTARTR_JR0
CONFIG_JTAG_CONSOLE
-CONFIG_KCLK_DIS
CONFIG_KEEP_SERVERADDR
CONFIG_KEYBOARD
-CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
-CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE
-CONFIG_KEYSTONE_RBL_NAND
CONFIG_KEY_REVOCATION
-CONFIG_KGDB_BAUDRATE
-CONFIG_KGDB_SER_INDEX
CONFIG_KIRKWOOD_EGIGA_INIT
CONFIG_KIRKWOOD_GPIO
CONFIG_KIRKWOOD_PCIE_INIT
CONFIG_KIRKWOOD_RGMII_PAD_1V8
-CONFIG_KIRQ_EN
CONFIG_KM8321
CONFIG_KMTEGR1
CONFIG_KM_BOARD_EXTRA_ENV
CONFIG_KM_UBI_PART_BOOT_OPTS
CONFIG_KM_UIMAGE_NAME
CONFIG_KM_UPDATE_UBOOT
-CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
-CONFIG_KSNAV_NETCP_PDMA_RX_BASE
-CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
-CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE
-CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM
-CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE
-CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE
-CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE
-CONFIG_KSNAV_NETCP_PDMA_TX_BASE
-CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM
-CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE
-CONFIG_KSNAV_PKTDMA_NETCP
-CONFIG_KSNAV_QM_BASE_ADDRESS
-CONFIG_KSNAV_QM_CONF_BASE
-CONFIG_KSNAV_QM_DESC_SETUP_BASE
-CONFIG_KSNAV_QM_INTD_CONF_BASE
-CONFIG_KSNAV_QM_LINK_RAM_BASE
-CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE
-CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE
-CONFIG_KSNAV_QM_PDSP1_CMD_BASE
-CONFIG_KSNAV_QM_PDSP1_CTRL_BASE
-CONFIG_KSNAV_QM_PDSP1_IRAM_BASE
-CONFIG_KSNAV_QM_QPOOL_NUM
-CONFIG_KSNAV_QM_QUEUE_STATUS_BASE
-CONFIG_KSNAV_QM_REGION_NUM
-CONFIG_KSNAV_QM_STATUS_RAM_BASE
CONFIG_KSNET_CPSW_NUM_PORTS
CONFIG_KSNET_MAC_ID_BASE
CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
CONFIG_LD9040
CONFIG_LEGACY
CONFIG_LEGACY_BOOTCMD_ENV
-CONFIG_LINUX
CONFIG_LITTLETON_LCD
CONFIG_LMS283GF05
-CONFIG_LOADADDR
CONFIG_LOADS_ECHO
CONFIG_LOWPOWER_ADDR
CONFIG_LOWPOWER_FLAG
CONFIG_M520x
CONFIG_M5301x
CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_OMAPL138_LCDK
-CONFIG_MACH_TYPE
-CONFIG_MACH_TYPE_COMPAT_REV
CONFIG_MACRESET_TIMEOUT
CONFIG_MALLOC_F_ADDR
CONFIG_MALTA
CONFIG_MARCO_MEMSET
-CONFIG_MARVELL_MFP
CONFIG_MASK_AER_AO
CONFIG_MAX_DSP_CPUS
CONFIG_MAX_FPGA_DEVICES
CONFIG_MCF5253
CONFIG_MCFRTC
CONFIG_MCFTMR
-CONFIG_MCLK_DIS
CONFIG_MDIO_TIMEOUT
-CONFIG_MEMSIZE
CONFIG_MEMSIZE_IN_BYTES
-CONFIG_MEMSIZE_MASK
CONFIG_MEM_HOLE_16M
CONFIG_MEM_INIT_VALUE
CONFIG_MEM_REMAP
CONFIG_MII_INIT
CONFIG_MIPS_HUGE_TLB_SUPPORT
CONFIG_MIPS_MT_FPAFF
-CONFIG_MIRQ_EN
CONFIG_MISC_COMMON
CONFIG_MIU_1BIT_INTERLEAVED
CONFIG_MIU_2BIT_21_7_INTERLEAVED
CONFIG_MIU_2BIT_INTERLEAVED
CONFIG_MIU_LINEAR
-CONFIG_MMCBOOTCOMMAND
CONFIG_MMCROOT
CONFIG_MMC_DEFAULT_DEV
CONFIG_MMC_RPMB_TRACE
CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION
CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
CONFIG_MPC83XX_GPIO_1_INIT_VALUE
-CONFIG_MPC83XX_PCI2
CONFIG_MPC85XX_FEC
CONFIG_MPC85XX_FEC_NAME
CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MV_ETH_RXQ
CONFIG_MV_I2C_NUM
CONFIG_MV_I2C_REG
-CONFIG_MX25_CLK32
-CONFIG_MX25_HCLK_FREQ
CONFIG_MX27
CONFIG_MX27_CLK32
CONFIG_MX27_TIMER_HIGH_PRECISION
CONFIG_MX28_FEC_MAC_IN_OCOTP
-CONFIG_MX35
-CONFIG_MX35_CLK32
-CONFIG_MX35_HCLK_FREQ
CONFIG_MXC_EPDC
CONFIG_MXC_GPT_HCLK
CONFIG_MXC_NAND_HWECC
CONFIG_NAND_DATA_REG
CONFIG_NAND_ECC_BCH
CONFIG_NAND_ENV_DST
-CONFIG_NAND_FSL_ELBC
-CONFIG_NAND_FSL_IFC
CONFIG_NAND_KIRKWOOD
CONFIG_NAND_KMETER1
-CONFIG_NAND_LPC32XX_MLC
CONFIG_NAND_MODE_REG
-CONFIG_NAND_OMAP_ECCSCHEME
CONFIG_NAND_OMAP_GPMC_WSCFG
CONFIG_NAND_SECBOOT
CONFIG_NAND_SPL
CONFIG_ODROID_REV_AIN
CONFIG_OFF_PADCONF
CONFIG_OF_
-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
-CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
-CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
-CONFIG_OMAP_USB2PHY2_HOST
-CONFIG_OMAP_USB3PHY1_HOST
CONFIG_ORIGEN
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
-CONFIG_PAGE_CNT_MASK
-CONFIG_PAGE_CNT_SHIFT
CONFIG_PALMAS_AUDPWR
CONFIG_PALMAS_POWER
CONFIG_PALMAS_SMPS7_FPWM
CONFIG_PCIE_IMX
CONFIG_PCIE_IMX_PERST_GPIO
CONFIG_PCIE_IMX_POWER_GPIO
-CONFIG_PCISLAVE
CONFIG_PCI_BOOTDELAY
CONFIG_PCI_CLK_FREQ
CONFIG_PCI_CONFIG_HOST_BRIDGE
CONFIG_PL011_CLOCK
CONFIG_PL011_SERIAL_RLCR
CONFIG_PL01x_PORTS
-CONFIG_PLATFORM_ENV_SETTINGS
CONFIG_PM
CONFIG_PMC_BR_PRELIM
CONFIG_PMC_OR_PRELIM
CONFIG_POST_SKIP_ENV_FLAGS
CONFIG_POST_UART
CONFIG_POST_WATCHDOG
-CONFIG_POWER
CONFIG_POWER_FSL
CONFIG_POWER_FSL_MC13892
CONFIG_POWER_HI6553
-CONFIG_POWER_I2C
CONFIG_POWER_LTC3676
CONFIG_POWER_LTC3676_I2C_ADDR
CONFIG_POWER_MAX77696_I2C_ADDR
CONFIG_PROC_FS
CONFIG_PROFILE_ALL_BRANCHES
CONFIG_PROFILING
-CONFIG_PROOF_POINTS
CONFIG_PSRAM_SCFG
CONFIG_PWM
CONFIG_PXA_LCD
CONFIG_QUOTA
CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOT_NAND
-CONFIG_RAMBOOT_PBL
CONFIG_RAMBOOT_SPIFLASH
CONFIG_RAMBOOT_TEXT_BASE
CONFIG_RAMDISKFILE
CONFIG_RED_LED
CONFIG_REG
CONFIG_REG_0
-CONFIG_REG_1_BASE
CONFIG_REG_2
CONFIG_REG_3
CONFIG_REG_8
-CONFIG_REG_APER_SIZE
CONFIG_REMAKE_ELF
CONFIG_REQ
CONFIG_RESERVED_01_BASE
CONFIG_RESET_VECTOR_ADDRESS
CONFIG_RESTORE_FLASH
CONFIG_RES_BLOCK_SIZE
-CONFIG_REVISION_TAG
CONFIG_RMII
CONFIG_RMSTP0_ENA
CONFIG_RMSTP10_ENA
CONFIG_S5PC110
CONFIG_S5P_PA_SYSRAM
CONFIG_S6E8AX0
-CONFIG_SABRELITE
CONFIG_SAMA5D3_LCD_BASE
CONFIG_SAMSUNG
CONFIG_SAMSUNG_ONENAND
CONFIG_SERIAL_HW_FLOW_CONTROL
CONFIG_SERIAL_MULTI
CONFIG_SERIAL_SOFTWARE_FIFO
-CONFIG_SERIAL_TAG
CONFIG_SERIRQ_CONTINUOUS_MODE
CONFIG_SERVERIP
CONFIG_SETUP_INITRD_TAG
-CONFIG_SETUP_MEMORY_TAGS
-CONFIG_SET_BIST
CONFIG_SET_BOOTARGS
CONFIG_SET_DFU_ALT_BUF_LEN
-CONFIG_SFIO
CONFIG_SGI_IP28
CONFIG_SH73A0
CONFIG_SH7751_PCI
CONFIG_SHARP_LM8V31
CONFIG_SHEEVA_88SV131
-CONFIG_SHEEVA_88SV331xV5
CONFIG_SH_CMT_CLK_FREQ
CONFIG_SH_DSP
CONFIG_SH_ETHER_ALIGNE_SIZE
CONFIG_SH_ETHER_SH7734_MII
CONFIG_SH_ETHER_USE_PORT
CONFIG_SH_GPIO_PFC
-CONFIG_SH_I2C_8BIT
-CONFIG_SH_I2C_CLOCK
-CONFIG_SH_I2C_DATA_HIGH
-CONFIG_SH_I2C_DATA_LOW
CONFIG_SH_MMCIF_CLK
CONFIG_SH_QSPI_BASE
CONFIG_SH_SCIF_CLK_FREQ
CONFIG_SH_SDHI_FREQ
CONFIG_SH_SDRAM_OFFSET
-CONFIG_SIEMENS_MACH_TYPE
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
-CONFIG_SKIP_LOWLEVEL_INIT
-CONFIG_SKIP_LOWLEVEL_INIT_ONLY
CONFIG_SKIP_TRUNOFF_WATCHDOG
CONFIG_SLIC
CONFIG_SLTTMR
CONFIG_SMSTP8_ENA
CONFIG_SMSTP9_ENA
CONFIG_SOCRATES
-CONFIG_SOC_K2E
-CONFIG_SOC_K2G
-CONFIG_SOC_K2HK
-CONFIG_SOC_K2L
-CONFIG_SOC_KEYSTONE
CONFIG_SOC_OMAP3430
CONFIG_SOFT_I2C_GPIO_SCL
CONFIG_SOFT_I2C_GPIO_SDA
CONFIG_SPL_MAX_SIZE
CONFIG_SPL_MXS_PSWITCH_WAIT
CONFIG_SPL_NAND_INIT
-CONFIG_SPL_NAND_LOAD
CONFIG_SPL_NAND_MINIMAL
CONFIG_SPL_NAND_RAW_ONLY
CONFIG_SPL_NAND_SOFTECC
CONFIG_SYS_AMASK5
CONFIG_SYS_AMASK6
CONFIG_SYS_AMASK7
-CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK
CONFIG_SYS_AT91_PLLA
CONFIG_SYS_AT91_PLLB
CONFIG_SYS_ATA_PORT_ADDR
CONFIG_SYS_ATA_REG_OFFSET
CONFIG_SYS_ATA_STRIDE
-CONFIG_SYS_ATI_REV_A11
-CONFIG_SYS_ATI_REV_A12
-CONFIG_SYS_ATI_REV_A13
-CONFIG_SYS_ATI_REV_ID_MASK
CONFIG_SYS_ATMEL_CPU_NAME
CONFIG_SYS_AUTOLOAD
CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
CONFIG_SYS_CMD_IAS
CONFIG_SYS_CMD_INT
CONFIG_SYS_CMD_SUSPEND
-CONFIG_SYS_CMXFCR_MASK1
-CONFIG_SYS_CMXFCR_MASK2
-CONFIG_SYS_CMXFCR_MASK3
-CONFIG_SYS_CMXFCR_VALUE1
-CONFIG_SYS_CMXFCR_VALUE2
-CONFIG_SYS_CMXFCR_VALUE3
CONFIG_SYS_CORE_SRAM
CONFIG_SYS_CORE_SRAM_SIZE
CONFIG_SYS_CPC_REINIT_F
CONFIG_SYS_CPLD_FTIM2
CONFIG_SYS_CPLD_FTIM3
CONFIG_SYS_CPLD_SIZE
-CONFIG_SYS_CPMFCR_RAMTYPE
CONFIG_SYS_CPM_INTERRUPT
CONFIG_SYS_CPRI
CONFIG_SYS_CPRI_CLK
CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DEFAULT_VIDEO_MODE
-CONFIG_SYS_DEF_EEPROM_ADDR
CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
CONFIG_SYS_DIMM_SLOTS_PER_CTLR
CONFIG_SYS_DIRECT_FLASH_NFS
CONFIG_SYS_FAST_CLK
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
CONFIG_SYS_FAULT_MII_ADDR
-CONFIG_SYS_FCC_PSMR
CONFIG_SYS_FDT_BASE
CONFIG_SYS_FDT_LOAD_ADDR
CONFIG_SYS_FDT_PAD
CONFIG_SYS_FLASH1_BASE_PHYS
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
CONFIG_SYS_FLASHBOOT
-CONFIG_SYS_FLASH_ADDR_BASE
CONFIG_SYS_FLASH_AMD_CHECK_DQ7
CONFIG_SYS_FLASH_AUTOPROTECT_LIST
CONFIG_SYS_FLASH_BANKS_LIST
CONFIG_SYS_FLASH_BANKS_SIZES
-CONFIG_SYS_FLASH_BANK_SIZE
CONFIG_SYS_FLASH_BASE
CONFIG_SYS_FLASH_BASE0
CONFIG_SYS_FLASH_BASE1
CONFIG_SYS_FSL_FMAN_ADDR
CONFIG_SYS_FSL_GUTS_ADDR
CONFIG_SYS_FSL_I2C
-CONFIG_SYS_FSL_I2C2_OFFSET
-CONFIG_SYS_FSL_I2C2_SLAVE
-CONFIG_SYS_FSL_I2C2_SPEED
-CONFIG_SYS_FSL_I2C3_OFFSET
-CONFIG_SYS_FSL_I2C3_SLAVE
-CONFIG_SYS_FSL_I2C3_SPEED
-CONFIG_SYS_FSL_I2C4_OFFSET
-CONFIG_SYS_FSL_I2C4_SLAVE
-CONFIG_SYS_FSL_I2C4_SPEED
-CONFIG_SYS_FSL_I2C_OFFSET
-CONFIG_SYS_FSL_I2C_SLAVE
-CONFIG_SYS_FSL_I2C_SPEED
CONFIG_SYS_FSL_IFC_BASE
CONFIG_SYS_FSL_IFC_BASE1
CONFIG_SYS_FSL_IFC_BASE2
CONFIG_SYS_FSL_OCRAM_SIZE
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
CONFIG_SYS_FSL_PAMU_OFFSET
-CONFIG_SYS_FSL_PBL_PBI
-CONFIG_SYS_FSL_PBL_RCW
CONFIG_SYS_FSL_PCIE_COMPAT
CONFIG_SYS_FSL_PCI_VER_3_X
CONFIG_SYS_FSL_PEBUF_BASE
CONFIG_SYS_I2C_DIRECT_BUS
CONFIG_SYS_I2C_DVI_ADDR
CONFIG_SYS_I2C_DVI_BUS_NUM
-CONFIG_SYS_I2C_EARLY_INIT
CONFIG_SYS_I2C_EEPROM_CCID
CONFIG_SYS_I2C_EEPROM_NXID
-CONFIG_SYS_I2C_EEPROM_NXID_MAC
CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
CONFIG_SYS_I2C_EXPANDER_ADDR
CONFIG_SYS_I2C_FRAM
CONFIG_SYS_I2C_G762_ADDR
CONFIG_SYS_I2C_IFDR_DIV
-CONFIG_SYS_I2C_IHS_CH0
-CONFIG_SYS_I2C_IHS_CH1
-CONFIG_SYS_I2C_IHS_CH2
-CONFIG_SYS_I2C_IHS_CH3
-CONFIG_SYS_I2C_IHS_DUAL
-CONFIG_SYS_I2C_IHS_SLAVE_0
-CONFIG_SYS_I2C_IHS_SLAVE_0_1
-CONFIG_SYS_I2C_IHS_SLAVE_1
-CONFIG_SYS_I2C_IHS_SLAVE_1_1
-CONFIG_SYS_I2C_IHS_SLAVE_2
-CONFIG_SYS_I2C_IHS_SLAVE_2_1
-CONFIG_SYS_I2C_IHS_SLAVE_3
-CONFIG_SYS_I2C_IHS_SLAVE_3_1
-CONFIG_SYS_I2C_IHS_SPEED_0
-CONFIG_SYS_I2C_IHS_SPEED_0_1
-CONFIG_SYS_I2C_IHS_SPEED_1
-CONFIG_SYS_I2C_IHS_SPEED_1_1
-CONFIG_SYS_I2C_IHS_SPEED_2
-CONFIG_SYS_I2C_IHS_SPEED_2_1
-CONFIG_SYS_I2C_IHS_SPEED_3
-CONFIG_SYS_I2C_IHS_SPEED_3_1
CONFIG_SYS_I2C_INIT_BOARD
CONFIG_SYS_I2C_LDI_ADDR
-CONFIG_SYS_I2C_LEGACY
CONFIG_SYS_I2C_LPC32XX_SLAVE
CONFIG_SYS_I2C_LPC32XX_SPEED
-CONFIG_SYS_I2C_MAC1_BUS
-CONFIG_SYS_I2C_MAC1_CHIP_ADDR
-CONFIG_SYS_I2C_MAC1_DATA_ADDR
-CONFIG_SYS_I2C_MAC2_BUS
-CONFIG_SYS_I2C_MAC2_CHIP_ADDR
-CONFIG_SYS_I2C_MAC2_DATA_ADDR
CONFIG_SYS_I2C_MAX_HOPS
CONFIG_SYS_I2C_NOPROBES
-CONFIG_SYS_I2C_OFFSET
CONFIG_SYS_I2C_PCA953X_ADDR
CONFIG_SYS_I2C_PCA953X_WIDTH
CONFIG_SYS_I2C_PCA9557_ADDR
CONFIG_SYS_I2C_PXA
CONFIG_SYS_I2C_QIXIS_ADDR
CONFIG_SYS_I2C_RTC_ADDR
-CONFIG_SYS_I2C_S3C24X0_SLAVE
-CONFIG_SYS_I2C_S3C24X0_SPEED
-CONFIG_SYS_I2C_SH
-CONFIG_SYS_I2C_SH_BASE0
-CONFIG_SYS_I2C_SH_BASE1
-CONFIG_SYS_I2C_SH_BASE2
-CONFIG_SYS_I2C_SH_BASE3
-CONFIG_SYS_I2C_SH_BASE4
-CONFIG_SYS_I2C_SH_NUM_CONTROLLERS
-CONFIG_SYS_I2C_SH_SPEED0
-CONFIG_SYS_I2C_SH_SPEED1
-CONFIG_SYS_I2C_SH_SPEED2
-CONFIG_SYS_I2C_SH_SPEED3
-CONFIG_SYS_I2C_SH_SPEED4
-CONFIG_SYS_I2C_SLAVE
-CONFIG_SYS_I2C_SLAVE1
-CONFIG_SYS_I2C_SLAVE2
-CONFIG_SYS_I2C_SLAVE3
-CONFIG_SYS_I2C_SOFT
-CONFIG_SYS_I2C_SOFT_SLAVE
-CONFIG_SYS_I2C_SOFT_SLAVE_10
-CONFIG_SYS_I2C_SOFT_SLAVE_11
-CONFIG_SYS_I2C_SOFT_SLAVE_12
-CONFIG_SYS_I2C_SOFT_SLAVE_2
-CONFIG_SYS_I2C_SOFT_SLAVE_3
-CONFIG_SYS_I2C_SOFT_SLAVE_4
-CONFIG_SYS_I2C_SOFT_SLAVE_5
-CONFIG_SYS_I2C_SOFT_SLAVE_6
-CONFIG_SYS_I2C_SOFT_SLAVE_7
-CONFIG_SYS_I2C_SOFT_SLAVE_8
-CONFIG_SYS_I2C_SOFT_SLAVE_9
-CONFIG_SYS_I2C_SOFT_SPEED
-CONFIG_SYS_I2C_SOFT_SPEED_10
-CONFIG_SYS_I2C_SOFT_SPEED_11
-CONFIG_SYS_I2C_SOFT_SPEED_12
-CONFIG_SYS_I2C_SOFT_SPEED_2
-CONFIG_SYS_I2C_SOFT_SPEED_3
-CONFIG_SYS_I2C_SOFT_SPEED_4
-CONFIG_SYS_I2C_SOFT_SPEED_5
-CONFIG_SYS_I2C_SOFT_SPEED_6
-CONFIG_SYS_I2C_SOFT_SPEED_7
-CONFIG_SYS_I2C_SOFT_SPEED_8
-CONFIG_SYS_I2C_SOFT_SPEED_9
-CONFIG_SYS_I2C_SPEED
-CONFIG_SYS_I2C_SPEED1
-CONFIG_SYS_I2C_SPEED2
-CONFIG_SYS_I2C_SPEED3
CONFIG_SYS_I2C_TCA642X_ADDR
CONFIG_SYS_I2C_TCA642X_BUS_NUM
CONFIG_SYS_IBAT0L
CONFIG_SYS_LIME_SIZE
CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
CONFIG_SYS_LOADS_BAUD_CHANGE
-CONFIG_SYS_LOAD_ADDR
CONFIG_SYS_LOW
CONFIG_SYS_LOWMEM_BASE
CONFIG_SYS_LOW_RES_TIMER
CONFIG_SYS_MX7_HCLK
CONFIG_SYS_MXS_VDD5V_ONLY
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-CONFIG_SYS_NAND_4_ADDR_CYCLE
-CONFIG_SYS_NAND_5_ADDR_CYCLE
CONFIG_SYS_NAND_ACTL_ALE
CONFIG_SYS_NAND_ACTL_CLE
CONFIG_SYS_NAND_ACTL_DELAY
CONFIG_SYS_NAND_ACTL_NCE
CONFIG_SYS_NAND_ALE
CONFIG_SYS_NAND_AMASK
-CONFIG_SYS_NAND_BAD_BLOCK_POS
CONFIG_SYS_NAND_BASE
CONFIG_SYS_NAND_BASE2
CONFIG_SYS_NAND_BASE_LIST
CONFIG_SYS_NAND_MAX_OOBFREE
CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-CONFIG_SYS_NAND_ONFI_DETECTION
CONFIG_SYS_NAND_OR_PRELIM
CONFIG_SYS_NAND_PAGE_2K
CONFIG_SYS_NAND_PAGE_4K
-CONFIG_SYS_NAND_PAGE_COUNT
CONFIG_SYS_NAND_QUIET
CONFIG_SYS_NAND_READY_PIN
CONFIG_SYS_NAND_REGS_BASE
CONFIG_SYS_OBIR
CONFIG_SYS_OHCI_BE_CONTROLLER
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-CONFIG_SYS_OMAP24_I2C_SLAVE1
-CONFIG_SYS_OMAP24_I2C_SLAVE2
-CONFIG_SYS_OMAP24_I2C_SLAVE3
-CONFIG_SYS_OMAP24_I2C_SLAVE4
-CONFIG_SYS_OMAP24_I2C_SPEED1
-CONFIG_SYS_OMAP24_I2C_SPEED2
-CONFIG_SYS_OMAP24_I2C_SPEED3
-CONFIG_SYS_OMAP24_I2C_SPEED4
CONFIG_SYS_OMAP_ABE_SYSCK
CONFIG_SYS_ONENAND_BASE
CONFIG_SYS_ONENAND_BLOCK_SIZE
CONFIG_SYS_PCI1_MEM_PHYS
CONFIG_SYS_PCI1_MEM_SIZE
CONFIG_SYS_PCI1_MEM_VIRT
-CONFIG_SYS_PCI1_MMIO_BASE
-CONFIG_SYS_PCI1_MMIO_PHYS
-CONFIG_SYS_PCI1_MMIO_SIZE
CONFIG_SYS_PCI2_ADDR
-CONFIG_SYS_PCI2_IO_BASE
-CONFIG_SYS_PCI2_IO_PHYS
-CONFIG_SYS_PCI2_IO_SIZE
-CONFIG_SYS_PCI2_MEM_BASE
-CONFIG_SYS_PCI2_MEM_PHYS
-CONFIG_SYS_PCI2_MEM_SIZE
-CONFIG_SYS_PCI2_MMIO_BASE
-CONFIG_SYS_PCI2_MMIO_PHYS
-CONFIG_SYS_PCI2_MMIO_SIZE
CONFIG_SYS_PCI64_MEMORY_BUS
CONFIG_SYS_PCIE
CONFIG_SYS_PCIE1_ADDR
CONFIG_SYS_RCAR_I2C1_BASE
CONFIG_SYS_RCAR_I2C2_BASE
CONFIG_SYS_RCAR_I2C3_BASE
-CONFIG_SYS_RCWH_PCIHOST
CONFIG_SYS_READ_SPD
CONFIG_SYS_RESET_ADDR
CONFIG_SYS_RESET_ADDRESS
CONFIG_SYS_SMC0_SETUP0_VAL
CONFIG_SYS_SMC_CSR0_VAL
CONFIG_SYS_SPCR_OPT
-CONFIG_SYS_SPCR_TSEC1EP
-CONFIG_SYS_SPCR_TSEC2EP
CONFIG_SYS_SPD_BUS_NUM
CONFIG_SYS_SPI_ARGS_OFFS
CONFIG_SYS_SPI_ARGS_SIZE
CONFIG_SYS_TMRINTR_PRI
CONFIG_SYS_TMRPND_REG
CONFIG_SYS_TMR_BASE
-CONFIG_SYS_TSEC1
CONFIG_SYS_TSEC1_OFFSET
-CONFIG_SYS_TSEC2
CONFIG_SYS_TSEC2_OFFSET
CONFIG_SYS_TSEC3_OFFSET
CONFIG_SYS_TX_ETH_BUFFER
CONFIG_SYS_USE_FLASH
CONFIG_SYS_USE_MAIN_OSCILLATOR
CONFIG_SYS_USE_MMC
-CONFIG_SYS_USE_MPC834XSYS_USB_PHY
CONFIG_SYS_USE_NAND
CONFIG_SYS_USE_NANDFLASH
CONFIG_SYS_USE_NORFLASH
CONFIG_SYS_VCXK_RESET_DDR
CONFIG_SYS_VCXK_RESET_PIN
CONFIG_SYS_VCXK_RESET_PORT
-CONFIG_SYS_VGA_RAM_EN
CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
CONFIG_SYS_VSC7385_BASE
CONFIG_SYS_VSC7385_BASE_PHYS
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XIMG_LEN
-CONFIG_SYS_i2C_FSL
CONFIG_TAM3517_SETTINGS
CONFIG_TCA642X
CONFIG_TEGRA_BOARD_STRING
CONFIG_THUNDERX
CONFIG_TIMESTAMP
CONFIG_TIZEN
-CONFIG_TI_KSNAV
CONFIG_TMU_TIMER
CONFIG_TPL_PAD_TO
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TWL6030_POWER
CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
-CONFIG_UBIBLOCK
CONFIG_UBIFS_VOLUME
CONFIG_UBI_PART
CONFIG_UBI_SIZE
CONFIG_UBOOTPATH
-CONFIG_UBOOT_ENABLE_PADS_ALL
CONFIG_UBOOT_SECTOR_COUNT
CONFIG_UBOOT_SECTOR_START
CONFIG_UDP_CHECKSUM
CONFIG_USB_EHCI_EXYNOS
CONFIG_USB_EHCI_FARADAY
CONFIG_USB_EHCI_KIRKWOOD
-CONFIG_USB_EHCI_MXC
CONFIG_USB_EHCI_MXS
CONFIG_USB_EHCI_TXFIFO_THRESH
CONFIG_USB_ETH_QMULT
CONFIG_USB_TUSB_OMAP_DMA
CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
-CONFIG_USB_XHCI_OMAP
+CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_INTERRUPT
CONFIG_USE_ONENAND_BOARD_INIT
CONFIG_UTBIPAR_INIT_TBIPA
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
CONFIG_VERY_BIG_RAM
-CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
CONFIG_VIDEO_BCM2835
CONFIG_VIDEO_BMP_LOGO
CONFIG_VIDEO_DA8XX
write_tree_source_node(f, dti->dt, 0);
}
-
localyesconfig localmodconfig: $(obj)/conf
$(Q)perl $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config
- $(Q)if [ -f .config ]; then \
+ $(Q)if [ -f .config ]; then \
cmp -s .tmp.config .config || \
(mv -f .config .config.old.1; \
mv -f .tmp.config .config; \
default:
;
}
- return false;
+ return false;
}
/*
void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data)
{
GtkWidget *dialog;
- const gchar *intro_text =
+ const gchar *intro_text =
"Welcome to gkc, the GTK+ graphical configuration tool\n"
"For each option, a blank box indicates the feature is disabled, a\n"
"check indicates it is enabled, and a dot indicates that it is to\n"
*/
#define list_for_each_entry(pos, head, member) \
for (pos = list_entry((head)->next, typeof(*pos), member); \
- &pos->member != (head); \
+ &pos->member != (head); \
pos = list_entry(pos->member.next, typeof(*pos), member))
/**
--- /dev/null
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0
+# Copyright Thomas Gleixner <tglx@linutronix.de>
+
+from argparse import ArgumentParser
+from ply import lex, yacc
+import locale
+import traceback
+import sys
+import git
+import re
+import os
+
+class ParserException(Exception):
+ def __init__(self, tok, txt):
+ self.tok = tok
+ self.txt = txt
+
+class SPDXException(Exception):
+ def __init__(self, el, txt):
+ self.el = el
+ self.txt = txt
+
+class SPDXdata(object):
+ def __init__(self):
+ self.license_files = 0
+ self.exception_files = 0
+ self.licenses = [ ]
+ self.exceptions = { }
+
+# Read the spdx data from the LICENSES directory
+def read_spdxdata(repo):
+
+ # The subdirectories of LICENSES in the kernel source
+ # Note: exceptions needs to be parsed as last directory.
+ license_dirs = [ "preferred", "dual", "deprecated", "exceptions" ]
+ lictree = repo.head.commit.tree['LICENSES']
+
+ spdx = SPDXdata()
+
+ for d in license_dirs:
+ for el in lictree[d].traverse():
+ if not os.path.isfile(el.path):
+ continue
+
+ exception = None
+ for l in open(el.path).readlines():
+ if l.startswith('Valid-License-Identifier:'):
+ lid = l.split(':')[1].strip().upper()
+ if lid in spdx.licenses:
+ raise SPDXException(el, 'Duplicate License Identifier: %s' %lid)
+ else:
+ spdx.licenses.append(lid)
+
+ elif l.startswith('SPDX-Exception-Identifier:'):
+ exception = l.split(':')[1].strip().upper()
+ spdx.exceptions[exception] = []
+
+ elif l.startswith('SPDX-Licenses:'):
+ for lic in l.split(':')[1].upper().strip().replace(' ', '').replace('\t', '').split(','):
+ if not lic in spdx.licenses:
+ raise SPDXException(None, 'Exception %s missing license %s' %(exception, lic))
+ spdx.exceptions[exception].append(lic)
+
+ elif l.startswith("License-Text:"):
+ if exception:
+ if not len(spdx.exceptions[exception]):
+ raise SPDXException(el, 'Exception %s is missing SPDX-Licenses' %exception)
+ spdx.exception_files += 1
+ else:
+ spdx.license_files += 1
+ break
+ return spdx
+
+class id_parser(object):
+
+ reserved = [ 'AND', 'OR', 'WITH' ]
+ tokens = [ 'LPAR', 'RPAR', 'ID', 'EXC' ] + reserved
+
+ precedence = ( ('nonassoc', 'AND', 'OR'), )
+
+ t_ignore = ' \t'
+
+ def __init__(self, spdx):
+ self.spdx = spdx
+ self.lasttok = None
+ self.lastid = None
+ self.lexer = lex.lex(module = self, reflags = re.UNICODE)
+ # Initialize the parser. No debug file and no parser rules stored on disk
+ # The rules are small enough to be generated on the fly
+ self.parser = yacc.yacc(module = self, write_tables = False, debug = False)
+ self.lines_checked = 0
+ self.checked = 0
+ self.spdx_valid = 0
+ self.spdx_errors = 0
+ self.curline = 0
+ self.deepest = 0
+
+ # Validate License and Exception IDs
+ def validate(self, tok):
+ id = tok.value.upper()
+ if tok.type == 'ID':
+ if not id in self.spdx.licenses:
+ raise ParserException(tok, 'Invalid License ID')
+ self.lastid = id
+ elif tok.type == 'EXC':
+ if id not in self.spdx.exceptions:
+ raise ParserException(tok, 'Invalid Exception ID')
+ if self.lastid not in self.spdx.exceptions[id]:
+ raise ParserException(tok, 'Exception not valid for license %s' %self.lastid)
+ self.lastid = None
+ elif tok.type != 'WITH':
+ self.lastid = None
+
+ # Lexer functions
+ def t_RPAR(self, tok):
+ r'\)'
+ self.lasttok = tok.type
+ return tok
+
+ def t_LPAR(self, tok):
+ r'\('
+ self.lasttok = tok.type
+ return tok
+
+ def t_ID(self, tok):
+ r'[A-Za-z.0-9\-+]+'
+
+ if self.lasttok == 'EXC':
+ print(tok)
+ raise ParserException(tok, 'Missing parentheses')
+
+ tok.value = tok.value.strip()
+ val = tok.value.upper()
+
+ if val in self.reserved:
+ tok.type = val
+ elif self.lasttok == 'WITH':
+ tok.type = 'EXC'
+
+ self.lasttok = tok.type
+ self.validate(tok)
+ return tok
+
+ def t_error(self, tok):
+ raise ParserException(tok, 'Invalid token')
+
+ def p_expr(self, p):
+ '''expr : ID
+ | ID WITH EXC
+ | expr AND expr
+ | expr OR expr
+ | LPAR expr RPAR'''
+ pass
+
+ def p_error(self, p):
+ if not p:
+ raise ParserException(None, 'Unfinished license expression')
+ else:
+ raise ParserException(p, 'Syntax error')
+
+ def parse(self, expr):
+ self.lasttok = None
+ self.lastid = None
+ self.parser.parse(expr, lexer = self.lexer)
+
+ def parse_lines(self, fd, maxlines, fname):
+ self.checked += 1
+ self.curline = 0
+ try:
+ for line in fd:
+ line = line.decode(locale.getpreferredencoding(False), errors='ignore')
+ self.curline += 1
+ if self.curline > maxlines:
+ break
+ self.lines_checked += 1
+ if line.find("SPDX-License-Identifier:") < 0:
+ continue
+ expr = line.split(':')[1].strip()
+ # Remove trailing comment closure
+ if line.strip().endswith('*/'):
+ expr = expr.rstrip('*/').strip()
+ # Remove trailing xml comment closure
+ if line.strip().endswith('-->'):
+ expr = expr.rstrip('-->').strip()
+ # Special case for SH magic boot code files
+ if line.startswith('LIST \"'):
+ expr = expr.rstrip('\"').strip()
+ self.parse(expr)
+ self.spdx_valid += 1
+ #
+ # Should we check for more SPDX ids in the same file and
+ # complain if there are any?
+ #
+ break
+
+ except ParserException as pe:
+ if pe.tok:
+ col = line.find(expr) + pe.tok.lexpos
+ tok = pe.tok.value
+ sys.stdout.write('%s: %d:%d %s: %s\n' %(fname, self.curline, col, pe.txt, tok))
+ else:
+ sys.stdout.write('%s: %d:0 %s\n' %(fname, self.curline, col, pe.txt))
+ self.spdx_errors += 1
+
+def scan_git_tree(tree):
+ for el in tree.traverse():
+ # Exclude stuff which would make pointless noise
+ # FIXME: Put this somewhere more sensible
+ if el.path.startswith("LICENSES"):
+ continue
+ if el.path.find("license-rules.rst") >= 0:
+ continue
+ if not os.path.isfile(el.path):
+ continue
+ with open(el.path, 'rb') as fd:
+ parser.parse_lines(fd, args.maxlines, el.path)
+
+def scan_git_subtree(tree, path):
+ for p in path.strip('/').split('/'):
+ tree = tree[p]
+ scan_git_tree(tree)
+
+if __name__ == '__main__':
+
+ ap = ArgumentParser(description='SPDX expression checker')
+ ap.add_argument('path', nargs='*', help='Check path or file. If not given full git tree scan. For stdin use "-"')
+ ap.add_argument('-m', '--maxlines', type=int, default=15,
+ help='Maximum number of lines to scan in a file. Default 15')
+ ap.add_argument('-v', '--verbose', action='store_true', help='Verbose statistics output')
+ args = ap.parse_args()
+
+ # Sanity check path arguments
+ if '-' in args.path and len(args.path) > 1:
+ sys.stderr.write('stdin input "-" must be the only path argument\n')
+ sys.exit(1)
+
+ try:
+ # Use git to get the valid license expressions
+ repo = git.Repo(os.getcwd())
+ assert not repo.bare
+
+ # Initialize SPDX data
+ spdx = read_spdxdata(repo)
+
+ # Initialize the parser
+ parser = id_parser(spdx)
+
+ except SPDXException as se:
+ if se.el:
+ sys.stderr.write('%s: %s\n' %(se.el.path, se.txt))
+ else:
+ sys.stderr.write('%s\n' %se.txt)
+ sys.exit(1)
+
+ except Exception as ex:
+ sys.stderr.write('FAIL: %s\n' %ex)
+ sys.stderr.write('%s\n' %traceback.format_exc())
+ sys.exit(1)
+
+ try:
+ if len(args.path) and args.path[0] == '-':
+ stdin = os.fdopen(sys.stdin.fileno(), 'rb')
+ parser.parse_lines(stdin, args.maxlines, '-')
+ else:
+ if args.path:
+ for p in args.path:
+ if os.path.isfile(p):
+ parser.parse_lines(open(p, 'rb'), args.maxlines, p)
+ elif os.path.isdir(p):
+ scan_git_subtree(repo.head.reference.commit.tree, p)
+ else:
+ sys.stderr.write('path %s does not exist\n' %p)
+ sys.exit(1)
+ else:
+ # Full git tree scan
+ scan_git_tree(repo.head.commit.tree)
+
+ if args.verbose:
+ sys.stderr.write('\n')
+ sys.stderr.write('License files: %12d\n' %spdx.license_files)
+ sys.stderr.write('Exception files: %12d\n' %spdx.exception_files)
+ sys.stderr.write('License IDs %12d\n' %len(spdx.licenses))
+ sys.stderr.write('Exception IDs %12d\n' %len(spdx.exceptions))
+ sys.stderr.write('\n')
+ sys.stderr.write('Files checked: %12d\n' %parser.checked)
+ sys.stderr.write('Lines checked: %12d\n' %parser.lines_checked)
+ sys.stderr.write('Files with SPDX: %12d\n' %parser.spdx_valid)
+ sys.stderr.write('Files with errors: %12d\n' %parser.spdx_errors)
+
+ sys.exit(0)
+
+ except Exception as ex:
+ sys.stderr.write('FAIL: %s\n' %ex)
+ sys.stderr.write('%s\n' %traceback.format_exc())
+ sys.exit(1)
DECLARE_GLOBAL_DATA_PTR;
-/* Declare a new compression test */
+/* Declare a new bloblist test */
#define BLOBLIST_TEST(_name, _flags) \
UNIT_TEST(_name, _flags, bloblist_test)
#include <gzip.h>
#include <image.h>
#include <log.h>
-#include <lz4.h>
#include <malloc.h>
#include <mapmem.h>
#include <asm/io.h>
+#include <u-boot/lz4.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
#include <dm.h>
#include <malloc.h>
#include <mapmem.h>
+#include <timestamp.h>
#include <version.h>
#include <tables_csum.h>
#include <version.h>
#define BUF_SIZE 4096
+#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \
+ (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \
+ (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \
+ ((U_BOOT_VERSION_NUM % 10) << 16) | \
+ (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \
+ ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \
+ 0x01)
+
/**
* struct testacpi_plat - Platform data for the test ACPI device
*
ut_asserteq_mem(OEM_ID, hdr.oem_id, sizeof(hdr.oem_id));
ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id,
sizeof(hdr.oem_table_id));
- ut_asserteq(U_BOOT_BUILD_DATE, hdr.oem_revision);
+ ut_asserteq(OEM_REVISION, hdr.oem_revision);
ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id));
ut_asserteq(0x44, hdr.aslc_revision);
addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16);
ut_assert_nextline("RSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)",
addr, sizeof(struct acpi_table_header) +
- 3 * sizeof(u32), U_BOOT_BUILD_DATE);
+ 3 * sizeof(u32), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16);
ut_assert_nextline("XSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)",
addr, sizeof(struct acpi_table_header) +
- 3 * sizeof(u64), U_BOOT_BUILD_DATE);
+ 3 * sizeof(u64), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64);
ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)",
- addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE);
+ addr, sizeof(struct acpi_dmar), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)",
- addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE);
+ addr, sizeof(struct acpi_dmar), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)",
- addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE);
+ addr, sizeof(struct acpi_dmar), OEM_REVISION);
ut_assert_console_end();
return 0;
uclass_find_next_device(&dev))
ut_assert(dev_get_flags(dev) & DM_FLAG_ACTIVATED);
- ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu-test1", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu@1", &dev));
ut_asserteq_ptr(cpu_get_current_dev(), dev);
ut_asserteq(cpu_is_current(dev), 1);
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020-2021 NXP Semiconductors
+ * Copyright 2020-2021 NXP
*/
#include <net/dsa.h>
&theirs));
ut_asserteq(-EINVAL, k210_pll_calc_config(1500000000, 20000000,
&theirs));
+ ut_asserteq(-EINVAL, k210_pll_calc_config(1750000000, 13300000,
+ &theirs));
/* Verify we get the same output with brute-force */
- ut_assertok(dm_test_k210_pll_calc_config(390000000, 26000000, &ours));
- ut_assertok(k210_pll_calc_config(390000000, 26000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(26000000, 390000000, &ours));
- ut_assertok(k210_pll_calc_config(26000000, 390000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(400000000, 26000000, &ours));
- ut_assertok(k210_pll_calc_config(400000000, 26000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(27000000, 26000000, &ours));
- ut_assertok(k210_pll_calc_config(27000000, 26000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(26000000, 27000000, &ours));
- ut_assertok(k210_pll_calc_config(26000000, 27000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+#define compare(rate, rate_in) do { \
+ ut_assertok(dm_test_k210_pll_calc_config(rate, rate_in, &ours)); \
+ ut_assertok(k210_pll_calc_config(rate, rate_in, &theirs)); \
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); \
+} while (0)
+
+ compare(390000000, 26000000);
+ compare(26000000, 390000000);
+ compare(400000000, 26000000);
+ compare(27000000, 26000000);
+ compare(26000000, 27000000);
+ compare(13300000 * 64, 13300000);
+ compare(21250000, 21250000 * 70);
+ compare(21250000, 1750000000);
+ compare(1750000000, 1750000000);
return 0;
}
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <dt-structs.h>
+#include <irq.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
+#include <asm-generic/gpio.h>
#include <asm/global_data.h>
/* Test that we can find a device using of-platdata */
struct udevice *dev;
int i;
- /* Skip the clock */
- ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev));
- ut_asserteq_str("sandbox_clk_test", dev->name);
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_spl_test",
+ &dev));
- ut_assertok(uclass_next_device_err(&dev));
plat = dev_get_plat(dev);
ut_assert(plat->boolval);
ut_asserteq(1, plat->intval);
}
DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA);
#endif
+
+/* Test clocks with of-platdata */
+static int dm_test_of_plat_clk(struct unit_test_state *uts)
+{
+ struct dtd_sandbox_clk_test *plat;
+ struct udevice *dev;
+ struct clk clk;
+
+ ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev));
+ ut_asserteq_str("sandbox_clk_test", dev->name);
+ plat = dev_get_plat(dev);
+
+ ut_assertok(clk_get_by_phandle(dev, &plat->clocks[0], &clk));
+ ut_asserteq_str("sandbox_fixed_clock", clk.dev->name);
+
+ return 0;
+}
+DM_TEST(dm_test_of_plat_clk, UT_TESTF_SCAN_PDATA);
+
+/* Test irqs with of-platdata */
+static int dm_test_of_plat_irq(struct unit_test_state *uts)
+{
+ struct dtd_sandbox_irq_test *plat;
+ struct udevice *dev;
+ struct irq irq;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_irq_test",
+ &dev));
+ plat = dev_get_plat(dev);
+
+ ut_assertok(irq_get_by_phandle(dev, &plat->interrupts_extended[0],
+ &irq));
+ ut_asserteq_str("sandbox_irq", irq.dev->name);
+
+ return 0;
+}
+DM_TEST(dm_test_of_plat_irq, UT_TESTF_SCAN_PDATA);
+
+/* Test GPIOs with of-platdata */
+static int dm_test_of_plat_gpio(struct unit_test_state *uts)
+{
+ struct dtd_sandbox_gpio_test *plat;
+ struct udevice *dev;
+ struct gpio_desc desc;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_gpio_test",
+ &dev));
+ plat = dev_get_plat(dev);
+
+ ut_assertok(gpio_request_by_phandle(dev, &plat->test_gpios[0], &desc,
+ GPIOD_IS_OUT));
+ ut_asserteq_str("sandbox_gpio", desc.dev->name);
+
+ return 0;
+}
+DM_TEST(dm_test_of_plat_gpio, UT_TESTF_SCAN_PDATA);
return 0;
}
DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_conf(struct unit_test_state *uts)
+{
+ ut_assert(!ofnode_conf_read_bool("missing"));
+ ut_assert(ofnode_conf_read_bool("testing-bool"));
+
+ ut_asserteq(123, ofnode_conf_read_int("testing-int", 0));
+ ut_asserteq(6, ofnode_conf_read_int("missing", 6));
+
+ ut_assertnull(ofnode_conf_read_str("missing"));
+ ut_asserteq_str("testing", ofnode_conf_read_str("testing-str"));
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_conf, 0);
}
DM_TEST(dm_test_pci_ep_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-
return 0;
}
DM_TEST(dm_test_smem_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-
{
struct udevice *dev;
- cpu_sandbox_set_current("cpu-test1");
+ cpu_sandbox_set_current("cpu@1");
ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev));
ut_asserteq(3000000, timer_get_rate(dev));
ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
- cpu_sandbox_set_current("cpu-test2");
+ cpu_sandbox_set_current("cpu@2");
ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev));
ut_asserteq(2000000, timer_get_rate(dev));
- cpu_sandbox_set_current("cpu-test1");
+ cpu_sandbox_set_current("cpu@1");
return 0;
}
#include <common.h>
#include <dm.h>
#include <wdt.h>
+#include <asm/gpio.h>
#include <asm/state.h>
#include <asm/test.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
+#include <linux/delay.h>
+#include <watchdog.h>
/* Test that watchdog driver functions are called */
static int dm_test_wdt_base(struct unit_test_state *uts)
struct udevice *dev;
const u64 timeout = 42;
- ut_assertok(uclass_get_device(UCLASS_WDT, 0, &dev));
+ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(wdt_sandbox), &dev));
ut_assertnonnull(dev);
ut_asserteq(0, state->wdt.counter);
ut_asserteq(false, state->wdt.running);
return 0;
}
DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_wdt_gpio(struct unit_test_state *uts)
+{
+ /*
+ * The sandbox wdt gpio is "connected" to gpio bank a, offset
+ * 7. Use the sandbox back door to verify that the gpio-wdt
+ * driver behaves as expected.
+ */
+ struct udevice *wdt, *gpio;
+ const u64 timeout = 42;
+ const int offset = 7;
+ int val;
+
+ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(wdt_gpio), &wdt));
+ ut_assertnonnull(wdt);
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio));
+ ut_assertnonnull(gpio);
+ ut_assertok(wdt_start(wdt, timeout, 0));
+
+ val = sandbox_gpio_get_value(gpio, offset);
+ ut_assertok(wdt_reset(wdt));
+ ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset));
+ ut_assertok(wdt_reset(wdt));
+ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
+
+ ut_asserteq(-ENOSYS, wdt_stop(wdt));
+
+ return 0;
+}
+DM_TEST(dm_test_wdt_gpio, UT_TESTF_SCAN_FDT);
+
+static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts)
+{
+ struct sandbox_state *state = state_get_current();
+ struct udevice *gpio_wdt, *sandbox_wdt;
+ struct udevice *gpio;
+ const u64 timeout = 42;
+ const int offset = 7;
+ uint reset_count;
+ int val;
+
+ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(wdt_gpio), &gpio_wdt));
+ ut_assertnonnull(gpio_wdt);
+ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(wdt_sandbox), &sandbox_wdt));
+ ut_assertnonnull(sandbox_wdt);
+ ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio));
+ ut_assertnonnull(gpio);
+
+ /* Neither device should be "started", so watchdog_reset() should be a no-op. */
+ reset_count = state->wdt.reset_count;
+ val = sandbox_gpio_get_value(gpio, offset);
+ watchdog_reset();
+ ut_asserteq(reset_count, state->wdt.reset_count);
+ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
+
+ /* Start both devices. */
+ ut_assertok(wdt_start(gpio_wdt, timeout, 0));
+ ut_assertok(wdt_start(sandbox_wdt, timeout, 0));
+
+ /* Make sure both devices have just been pinged. */
+ timer_test_add_offset(100);
+ watchdog_reset();
+ reset_count = state->wdt.reset_count;
+ val = sandbox_gpio_get_value(gpio, offset);
+
+ /* The gpio watchdog should be pinged, the sandbox one not. */
+ timer_test_add_offset(30);
+ watchdog_reset();
+ ut_asserteq(reset_count, state->wdt.reset_count);
+ ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset));
+
+ /* After another ~30ms, both devices should get pinged. */
+ timer_test_add_offset(30);
+ watchdog_reset();
+ ut_asserteq(reset_count + 1, state->wdt.reset_count);
+ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
+
+ return 0;
+}
+DM_TEST(dm_test_wdt_watchdog_reset, UT_TESTF_SCAN_FDT);
# (C) Copyright 2018
# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
obj-y += cmd_ut_lib.o
+obj-y += abuf.o
obj-$(CONFIG_EFI_LOADER) += efi_device_path.o
obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
obj-y += hexdump.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <abuf.h>
+#include <mapmem.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static char test_data[] = "1234";
+#define TEST_DATA_LEN sizeof(test_data)
+
+/* Test abuf_set() */
+static int lib_test_abuf_set(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Force it to allocate */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN + 1));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN + 1, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Now set it again, to force it to free */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_set, 0);
+
+/* Test abuf_map_sysmem() */
+static int lib_test_abuf_map_sysmem(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong addr;
+
+ abuf_init(&buf);
+ addr = 0x100;
+ abuf_map_sysmem(&buf, addr, TEST_DATA_LEN);
+
+ ut_asserteq_ptr(map_sysmem(0x100, 0), buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_map_sysmem, 0);
+
+/* Test abuf_realloc() */
+static int lib_test_abuf_realloc(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+ void *ptr;
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+
+ /* Allocate an empty buffer */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Allocate a non-empty abuf */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ptr = buf.data;
+
+ /*
+ * Make it smaller; the pointer should remain the same. Note this relies
+ * on knowledge of how U-Boot's realloc() works
+ */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN - 1));
+ ut_asserteq(TEST_DATA_LEN - 1, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ut_asserteq_ptr(ptr, buf.data);
+
+ /*
+ * Make it larger, forcing reallocation. Note this relies on knowledge
+ * of how U-Boot's realloc() works
+ */
+ ut_asserteq(true, abuf_realloc(&buf, 0x1000));
+ ut_assert(buf.data != ptr);
+ ut_asserteq(0x1000, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Free it */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_realloc, 0);
+
+/* Test handling of buffers that are too large */
+static int lib_test_abuf_large(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+ size_t size;
+ int delta;
+ void *ptr;
+
+ /*
+ * This crashes at present due to trying to allocate more memory than
+ * available, which breaks something on sandbox.
+ */
+ return 0;
+
+ start = ut_check_free();
+
+ /* Try an impossible size */
+ abuf_init(&buf);
+ ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Start with a normal size then try to increase it, to check realloc */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ptr = buf.data;
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+
+ /* try to increase it */
+ ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN));
+ ut_asserteq_ptr(ptr, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ut_asserteq(delta, ut_check_delta(start));
+
+ /* Check for memory leaks */
+ abuf_uninit(&buf);
+ ut_assertok(ut_check_delta(start));
+
+ /* Start with a huge unallocated buf and try to move it */
+ abuf_init(&buf);
+ abuf_map_sysmem(&buf, 0, CONFIG_SYS_MALLOC_LEN);
+ ut_asserteq(CONFIG_SYS_MALLOC_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+ ut_assertnull(abuf_uninit_move(&buf, &size));
+
+ /* Check for memory leaks */
+ abuf_uninit(&buf);
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_large, 0);
+
+/* Test abuf_uninit_move() */
+static int lib_test_abuf_uninit_move(struct unit_test_state *uts)
+{
+ void *ptr, *orig_ptr;
+ struct abuf buf;
+ size_t size;
+ ulong start;
+ int delta;
+
+ start = ut_check_free();
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ /* Move an empty buffer */
+ abuf_init(&buf);
+ ut_assertnull(abuf_uninit_move(&buf, &size));
+ ut_asserteq(0, size);
+ ut_assertnull(abuf_uninit_move(&buf, NULL));
+
+ /* Move an unallocated buffer */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_assertok(ut_check_delta(start));
+ ptr = abuf_uninit_move(&buf, &size);
+ ut_asserteq(TEST_DATA_LEN, size);
+ ut_asserteq_str(ptr, test_data);
+ ut_assertnonnull(ptr);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check that freeing it frees the only allocation */
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+ free(ptr);
+ ut_assertok(ut_check_delta(start));
+
+ /* Move an allocated buffer */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ orig_ptr = buf.data;
+ strcpy(orig_ptr, test_data);
+
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+ ptr = abuf_uninit_move(&buf, &size);
+ ut_asserteq(TEST_DATA_LEN, size);
+ ut_assertnonnull(ptr);
+ ut_asserteq_ptr(ptr, orig_ptr);
+ ut_asserteq_str(ptr, test_data);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check there was no new allocation */
+ ut_asserteq(delta, ut_check_delta(start));
+
+ /* Check that freeing it frees the only allocation */
+ free(ptr);
+ ut_assertok(ut_check_delta(start));
+
+ /* Move an unallocated buffer, without the size */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_assertok(ut_check_delta(start));
+ ptr = abuf_uninit_move(&buf, NULL);
+ ut_asserteq_str(ptr, test_data);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_uninit_move, 0);
+
+/* Test abuf_uninit() */
+static int lib_test_abuf_uninit(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ /* Nothing in the buffer */
+ abuf_init(&buf);
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Not allocated */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_uninit, 0);
+
+/* Test abuf_init_set() */
+static int lib_test_abuf_init_set(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ abuf_init_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init_set, 0);
+
+/* Test abuf_init_move() */
+static int lib_test_abuf_init_move(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ void *ptr;
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ ptr = strdup(test_data);
+ ut_assertnonnull(ptr);
+
+ free(ptr);
+
+ abuf_init_move(&buf, ptr, TEST_DATA_LEN);
+ ut_asserteq_ptr(ptr, abuf_data(&buf));
+ ut_asserteq(TEST_DATA_LEN, abuf_size(&buf));
+ ut_asserteq(true, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init_move, 0);
+
+/* Test abuf_init() */
+static int lib_test_abuf_init(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ buf.data = &buf;
+ buf.size = 123;
+ buf.alloced = true;
+ abuf_init(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init, 0);
/* Allow for copying up to 32 bytes */
#define BUFLEN (SWEEP + 33)
+#define TEST_STR "hello"
+
/**
* init_buffer() - initialize buffer
*
}
LIB_TEST(lib_memmove, 0);
+
+/** lib_memdup() - unit test for memdup() */
+static int lib_memdup(struct unit_test_state *uts)
+{
+ char buf[BUFLEN];
+ size_t len;
+ char *p, *q;
+
+ /* Zero size should do nothing */
+ p = memdup(NULL, 0);
+ ut_assertnonnull(p);
+ free(p);
+
+ p = memdup(buf, 0);
+ ut_assertnonnull(p);
+ free(p);
+
+ strcpy(buf, TEST_STR);
+ len = sizeof(TEST_STR);
+ p = memdup(buf, len);
+ ut_asserteq_mem(p, buf, len);
+
+ q = memdup(p, len);
+ ut_asserteq_mem(q, buf, len);
+ free(q);
+ free(p);
+
+ return 0;
+}
+LIB_TEST(lib_memdup, 0);
#include <display_options.h>
#include <log.h>
#include <mapmem.h>
-#include <version.h>
+#include <version_string.h>
#include <test/suites.h>
#include <test/test.h>
#include <test/ut.h>
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+
+"""
+Check hashes produced by mkimage against known values
+
+This test checks the correctness of mkimage's hashes. by comparing the mkimage
+output of a fixed data block with known good hashes.
+This test doesn't run the sandbox. It only checks the host tool 'mkimage'
+"""
+
+import pytest
+import u_boot_utils as util
+
+kernel_hashes = {
+ "sha512" : "f18c1486a2c29f56360301576cdfce4dfd8e8e932d0ed8e239a1f314b8ae1d77b2a58cd7fe32e4075e69448e623ce53b0b6aa6ce5626d2c189a5beae29a68d93",
+ "sha384" : "16e28976740048485d08d793d8bf043ebc7826baf2bc15feac72825ad67530ceb3d09e0deb6932c62a5a0e9f3936baf4",
+ "sha256" : "2955c56bc1e5050c111ba6e089e0f5342bb47dedf77d87e3f429095feb98a7e5",
+ "sha1" : "652383e1a6d946953e1f65092c9435f6452c2ab7",
+ "md5" : "4879e5086e4c76128e525b5fe2af55f1",
+ "crc32" : "32eddfdf",
+ "crc16-ccitt" : "d4be"
+}
+
+class ReadonlyFitImage(object):
+ """ Helper to manipulate a FIT image on disk """
+ def __init__(self, cons, file_name):
+ self.fit = file_name
+ self.cons = cons
+ self.hashable_nodes = set()
+
+ def __fdt_list(self, path):
+ return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}')
+
+ def __fdt_get(self, node, prop):
+ val = util.run_and_log(self.cons, f'fdtget {self.fit} {node} {prop}')
+ return val.rstrip('\n')
+
+ def __fdt_get_sexadecimal(self, node, prop):
+ numbers = util.run_and_log(self.cons, f'fdtget -tbx {self.fit} {node} {prop}')
+
+ sexadecimal = ''
+ for num in numbers.rstrip('\n').split(' '):
+ sexadecimal += num.zfill(2)
+ return sexadecimal
+
+ def find_hashable_image_nodes(self):
+ for node in self.__fdt_list('/images').split():
+ # We only have known hashes for the kernel node
+ if 'kernel' not in node:
+ continue
+ self.hashable_nodes.add(f'/images/{node}')
+
+ return self.hashable_nodes
+
+ def verify_hashes(self):
+ for image in self.hashable_nodes:
+ algos = set()
+ for node in self.__fdt_list(image).split():
+ if "hash-" not in node:
+ continue
+
+ raw_hash = self.__fdt_get_sexadecimal(f'{image}/{node}', 'value')
+ algo = self.__fdt_get(f'{image}/{node}', 'algo')
+ algos.add(algo)
+
+ good_hash = kernel_hashes[algo]
+ if good_hash != raw_hash:
+ raise ValueError(f'{image} Borked hash: {algo}');
+
+ # Did we test all the hashes we set out to test?
+ missing_algos = kernel_hashes.keys() - algos
+ if (missing_algos):
+ raise ValueError(f'Missing hashes from FIT: {missing_algos}')
+
+
+@pytest.mark.buildconfigspec('hash')
+@pytest.mark.requiredtool('dtc')
+@pytest.mark.requiredtool('fdtget')
+@pytest.mark.requiredtool('fdtput')
+def test_mkimage_hashes(u_boot_console):
+ """ Test that hashes generated by mkimage are correct. """
+
+ def assemble_fit_image(dest_fit, its, destdir):
+ dtc_args = f'-I dts -O dtb -i {destdir}'
+ util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
+
+ def dtc(dts):
+ dtb = dts.replace('.dts', '.dtb')
+ util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
+
+ cons = u_boot_console
+ mkimage = cons.config.build_dir + '/tools/mkimage'
+ datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+ tempdir = cons.config.result_dir
+ fit_file = f'{tempdir}/test.fit'
+ dtc('sandbox-kernel.dts')
+
+ # Create a fake kernel image -- Avoid zeroes or crc16 will be zero
+ with open(f'{tempdir}/test-kernel.bin', 'w') as fd:
+ fd.write(500 * chr(0xa5))
+
+ assemble_fit_image(fit_file, f'{datadir}/hash-images.its', tempdir)
+
+ fit = ReadonlyFitImage(cons, fit_file)
+ nodes = fit.find_hashable_image_nodes()
+ if len(nodes) == 0:
+ raise ValueError('FIT image has no "/image" nodes with "hash-..."')
+
+ fit.verify_hashes()
('test ! ! aaa != aaa -o ! ! bbb = bbb', True),
('test ! ! aaa = aaa -o ! ! bbb != bbb', True),
('test ! ! aaa = aaa -o ! ! bbb = bbb', True),
-
- # -z operator.
-
- ('test -z "$ut_var_nonexistent"', True),
- ('test -z "$ut_var_exists"', False),
)
def exec_hush_if(u_boot_console, expr, result):
response = u_boot_console.run_command(cmd)
assert response.strip() == str(result).lower()
-def test_hush_if_test_setup(u_boot_console):
- """Set up environment variables used during the "if" tests."""
-
- u_boot_console.run_command('setenv ut_var_nonexistent')
- u_boot_console.run_command('setenv ut_var_exists 1')
-
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.parametrize('expr,result', subtests)
def test_hush_if_test(u_boot_console, expr, result):
exec_hush_if(u_boot_console, expr, result)
-def test_hush_if_test_teardown(u_boot_console):
- """Clean up environment variables used during the "if" tests."""
-
+def test_hush_z(u_boot_console):
+ """Test the -z operator"""
+ u_boot_console.run_command('setenv ut_var_nonexistent')
+ u_boot_console.run_command('setenv ut_var_exists 1')
+ exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True)
+ exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False)
u_boot_console.run_command('setenv ut_var_exists')
# We might test this on real filesystems via UMS, DFU, 'save', etc.
u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
u_boot_console.run_command('echo --- end of init ---')
+def is_sandbox(cons):
+ # Array slice removes leading/trailing quotes.
+ sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
+ return sys_arch == 'sandbox'
+
@pytest.mark.buildconfigspec('cmd_tpm_v2')
def test_tpm2_init(u_boot_console):
"""Init the software stack to use TPMv2 commands."""
-
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
-
u_boot_console.run_command('tpm2 init')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
Initiate the TPM internal state machine.
"""
+ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+def tpm2_sandbox_init(u_boot_console):
+ """Put sandbox back into a known state so we can run a test
+
+ This allows all tests to run in parallel, since no test depends on another.
+ """
+ u_boot_console.restart_uboot()
+ u_boot_console.run_command('tpm2 init')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
+ u_boot_console.run_command('tpm2 self_test full')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_self_test_full(u_boot_console):
+def test_tpm2_sandbox_self_test_full(u_boot_console):
"""Execute a TPM2_SelfTest (full) command.
Ask the TPM to perform all self tests to also enable full capabilities.
"""
+ if is_sandbox(u_boot_console):
+ u_boot_console.restart_uboot()
+ u_boot_console.run_command('tpm2 init')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
u_boot_console.run_command('tpm2 self_test continue')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
not have a password set, otherwise this test will fail. ENDORSEMENT and
PLATFORM hierarchies are also available.
"""
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
Use the LOCKOUT hierarchy for this. ENDORSEMENT and PLATFORM hierarchies are
also available.
"""
-
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
force_init(u_boot_console)
u_boot_console.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
There is no expected default values because it would depend on the chip
used. We can still save them in order to check they have changed later.
"""
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
the authentication, otherwise the lockout will be engaged after the first
failed authentication attempt.
"""
-
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
Perform a PCR read of the 0th PCR. Must be zero.
"""
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
No authentication mechanism is used here, not protecting against packet
replay, yet.
"""
-
+ if is_sandbox(u_boot_console):
+ tpm2_sandbox_init(u_boot_console)
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
Tests run with both SHA1 and SHA256 hashing.
"""
+import os
import shutil
import struct
import pytest
# Only run the full suite on a few combinations, since it doesn't add any more
# test coverage.
TESTDATA = [
- ['sha1', '', None, False, True],
- ['sha1', '', '-E -p 0x10000', False, False],
- ['sha1', '-pss', None, False, False],
- ['sha1', '-pss', '-E -p 0x10000', False, False],
- ['sha256', '', None, False, False],
- ['sha256', '', '-E -p 0x10000', False, False],
- ['sha256', '-pss', None, False, False],
- ['sha256', '-pss', '-E -p 0x10000', False, False],
- ['sha256', '-pss', None, True, False],
- ['sha256', '-pss', '-E -p 0x10000', True, True],
+ ['sha1-basic', 'sha1', '', None, False, True],
+ ['sha1-pad', 'sha1', '', '-E -p 0x10000', False, False],
+ ['sha1-pss', 'sha1', '-pss', None, False, False],
+ ['sha1-pss-pad', 'sha1', '-pss', '-E -p 0x10000', False, False],
+ ['sha256-basic', 'sha256', '', None, False, False],
+ ['sha256-pad', 'sha256', '', '-E -p 0x10000', False, False],
+ ['sha256-pss', 'sha256', '-pss', None, False, False],
+ ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x10000', False, False],
+ ['sha256-pss-required', 'sha256', '-pss', None, True, False],
+ ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x10000', True, True],
]
@pytest.mark.boardspec('sandbox')
@pytest.mark.requiredtool('fdtget')
@pytest.mark.requiredtool('fdtput')
@pytest.mark.requiredtool('openssl')
-@pytest.mark.parametrize("sha_algo,padding,sign_options,required,full_test",
+@pytest.mark.parametrize("name,sha_algo,padding,sign_options,required,full_test",
TESTDATA)
-def test_vboot(u_boot_console, sha_algo, padding, sign_options, required,
+def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
full_test):
"""Test verified boot signing with mkimage and verification with 'bootm'.
run_bootm(sha_algo, 'multi required key', '', False)
cons = u_boot_console
- tmpdir = cons.config.result_dir + '/'
+ tmpdir = os.path.join(cons.config.result_dir, name) + '/'
+ if not os.path.exists(tmpdir):
+ os.mkdir(tmpdir)
datadir = cons.config.source_dir + '/test/py/tests/vboot/'
fit = '%stest.fit' % tmpdir
mkimage = cons.config.build_dir + '/tools/mkimage'
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ hash-0 {
+ algo = "crc16-ccitt";
+ };
+ hash-1 {
+ algo = "crc32";
+ };
+ hash-2 {
+ algo = "md5";
+ };
+ hash-3 {
+ algo = "sha1";
+ };
+ hash-4 {
+ algo = "sha256";
+ };
+ hash-5 {
+ algo = "sha384";
+ };
+ hash-6 {
+ algo = "sha512";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ hash-0 {
+ algo = "crc16-ccitt";
+ };
+ hash-1 {
+ algo = "crc32";
+ };
+ hash-2 {
+ algo = "md5";
+ };
+ hash-3 {
+ algo = "sha1";
+ };
+ hash-4 {
+ algo = "sha256";
+ };
+ hash-5 {
+ algo = "sha384";
+ };
+ hash-6 {
+ algo = "sha512";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ };
+ };
+};
self.p.logfile_read = self.logstream
bcfg = self.config.buildconfig
config_spl = bcfg.get('config_spl', 'n') == 'y'
- config_spl_serial_support = bcfg.get('config_spl_serial_support',
+ config_spl_serial = bcfg.get('config_spl_serial',
'n') == 'y'
env_spl_skipped = self.config.env.get('env__spl_skipped',
False)
env_spl2_skipped = self.config.env.get('env__spl2_skipped',
True)
- if config_spl and config_spl_serial_support and not env_spl_skipped:
+ if config_spl and config_spl_serial and not env_spl_skipped:
m = self.p.expect([pattern_u_boot_spl_signon] +
self.bad_patterns)
if m != 0:
return 0;
}
+int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...)
+{
+ va_list args;
+ int len;
+ int ret;
+
+ va_start(args, fmt);
+ len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args);
+ va_end(args);
+ if (len >= sizeof(uts->expect_str)) {
+ ut_fail(uts, __FILE__, __LINE__, __func__,
+ "unit_test_state->expect_str too small");
+ return -EOVERFLOW;
+ }
+ while (1) {
+ if (!console_record_avail())
+ return -ENOENT;
+ ret = readline_check(uts);
+ if (ret < 0)
+ return ret;
+
+ if (!strcmp(uts->expect_str, uts->actual_str))
+ return 0;
+ }
+}
+
int ut_check_console_end(struct unit_test_state *uts)
{
int ret;
some cases the system dtc may not support all required features
and the path to a different version should be given here.
+config TOOLS_CRC32
+ def_bool y
+ help
+ Enable CRC32 support in the tools builds
+
config TOOLS_LIBCRYPTO
bool "Use OpenSSL's libcrypto library for host tools"
default y
This selection does not affect target features, such as runtime FIT
signature verification.
+config TOOLS_FIT
+ def_bool y
+ help
+ Enable FIT support in the tools builds.
+
+config TOOLS_FIT_FULL_CHECK
+ def_bool y
+ help
+ Do a full check of the FIT before using it in the tools builds
+
+config TOOLS_FIT_PRINT
+ def_bool y
+ help
+ Print the content of the FIT verbosely in the tools builds
+
+config TOOLS_FIT_RSASSA_PSS
+ def_bool y
+ help
+ Support the rsassa-pss signature scheme in the tools builds
+
+config TOOLS_FIT_SIGNATURE
+ def_bool y
+ help
+ Enable signature verification of FIT uImages in the tools builds
+
+config TOOLS_FIT_SIGNATURE_MAX_SIZE
+ hex
+ depends on TOOLS_FIT_SIGNATURE
+ default 0x10000000
+
+config TOOLS_FIT_VERBOSE
+ def_bool y
+ help
+ Support verbose FIT output in the tools builds
+
+config TOOLS_MD5
+ def_bool y
+ help
+ Enable MD5 support in the tools builds
+
+config TOOLS_OF_LIBFDT
+ def_bool y
+ help
+ Enable libfdt support in the tools builds
+
+config TOOLS_SHA1
+ def_bool y
+ help
+ Enable SHA1 support in the tools builds
+
+config TOOLS_SHA256
+ def_bool y
+ help
+ Enable SHA256 support in the tools builds
+
+config TOOLS_SHA384
+ def_bool y
+ help
+ Enable SHA384 support in the tools builds
+
+config TOOLS_SHA512
+ def_bool y
+ help
+ Enable SHA512 support in the tools builds
+
endmenu
lib/fdtdec_common.o \
lib/fdtdec.o \
common/image.o \
+ common/image-host.o \
imagetool.o \
imximage.o \
imx8image.o \
}
memcpy(tokens[tix].content, start, tokens[tix].size);
tokens[tix].content[tokens[tix].size] = 0;
-
+
/* If it begins with a lowercase letter then
* it's an element name
*/
global state
if args.full_help:
- pager = os.getenv('PAGER')
- if not pager:
- pager = 'more'
- fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
- 'README.rst')
- command.Run(pager, fname)
+ tools.PrintFullHelp(
+ os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README.rst')
+ )
return 0
# Put these here so that we can import this module without libfdt
scp-sunxi:
SCP firmware is required for system suspend, but is otherwise optional.
Please read the section on SCP firmware in board/sunxi/README.sunxi64
+
+k3-rti-wdt-firmware:
+If CONFIG_WDT_K3_RTI_LOAD_FW is enabled, a firmware image is needed for
+the R5F core(s) to trigger the system reset. One possible source is
+https://github.com/siemens/k3-rti-wdt.
...
43: Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig
arm:
- + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
- + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
- + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1
+ + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1
+ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1
am335x_evm_usbspl :
- + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
- + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
- + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1
+ + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1
+ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1
44: Convert CONFIG_SPL_USB_HOST to Kconfig
...
from patman import gitutil
from patman import patchstream
from patman import terminal
+from patman import tools
from patman.terminal import Print
def GetPlural(count):
global builder
if options.full_help:
- pager = os.getenv('PAGER')
- if not pager:
- pager = 'more'
- fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
- 'README')
- command.Run(pager, fname)
+ tools.PrintFullHelp(
+ os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README')
+ )
return 0
gitutil.Setup()
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:focal-20210723
+FROM ubuntu:focal-20210827
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
iasl \
imagemagick \
iputils-ping \
+ libconfuse-dev \
libgit2-dev \
libguestfs-tools \
liblz4-tool \
mount \
mtd-utils \
mtools \
+ ninja-build \
openssl \
picocom \
parted \
RUN git clone git://git.qemu.org/qemu.git /tmp/qemu && \
cd /tmp/qemu && \
git submodule update --init dtc && \
- git checkout v4.2.0 && \
+ git checkout v6.1.0 && \
+ # config user.name and user.email to make 'git am' happy
+ git config user.name u-boot && \
+ git config user.email u-boot@denx.de && \
+ # manually apply the bug fix for QEMU 6.1.0 Xilinx Zynq UART emulation codes
+ wget -O - http://patchwork.ozlabs.org/project/qemu-devel/patch/20210823020813.25192-2-bmeng.cn@gmail.com/mbox/ | git am && \
./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \
make -j$(nproc) all install && \
rm -rf /tmp/qemu
+# Build genimage (required by some targets to generate disk images)
+RUN wget -O - https://github.com/pengutronix/genimage/releases/download/v14/genimage-14.tar.xz | tar -C /tmp -xJ && \
+ cd /tmp/genimage-14 && \
+ ./configure && \
+ make -j$(nproc) && \
+ make install && \
+ rm -rf /tmp/genimage-14
+
# Create our user/group
RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot
RUN useradd -m -U uboot
# a phandle property.
PHANDLE_PROPS = {
'clocks': '#clock-cells',
+ 'interrupts-extended': '#interrupt-cells',
'gpios': '#gpio-cells',
'sandbox,emul': '#emul-cells',
}
DEVNAME(dev), strerror(errno));
return -1;
}
- if (rc != readlen) {
- fprintf(stderr,
- "Read error on %s: Attempted to read %zd bytes but got %d\n",
- DEVNAME(dev), readlen, rc);
- return -1;
- }
#ifdef DEBUG
fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
rc, (unsigned long long)blockstart + block_seek,
DEVNAME(dev));
#endif
- processed += readlen;
- readlen = min(blocklen, count - processed);
- block_seek = 0;
- blockstart += blocklen;
+ processed += rc;
+ if (rc != readlen) {
+ fprintf(stderr,
+ "Warning on %s: Attempted to read %zd bytes but got %d\n",
+ DEVNAME(dev), readlen, rc);
+ readlen -= rc;
+ block_seek += rc;
+ } else {
+ blockstart += blocklen;
+ readlen = min(blocklen, count - processed);
+ block_seek = 0;
+ }
}
return processed;
// SPDX-License-Identifier: GPL-2.0+
/*
* Image manipulator for Marvell SoCs
- * supports Kirkwood, Dove, Armada 370, Armada XP, and Armada 38x
+ * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and
+ * Armada 39x
*
* (C) Copyright 2013 Thomas Petazzoni
* <thomas.petazzoni@free-electrons.com>
return csum;
}
-size_t kwbimage_header_size(unsigned char *ptr)
-{
- if (image_version((void *)ptr) == 0)
- return sizeof(struct main_hdr_v0);
- else
- return KWBHEADER_V1_SIZE((struct main_hdr_v1 *)ptr);
-}
-
/*
* Verify checksum over a complete header that includes the checksum field.
* Return 1 when OK, otherwise 0.
struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr;
uint8_t checksum;
- checksum = image_checksum8(hdr, kwbimage_header_size(hdr));
+ checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr));
/* Calculated checksum includes the header checksum field. Compensate
* for that.
*/
}
if (4 + size_seq > sizeof(dst->key)) {
- fprintf(stderr, "export pk failed: seq too large (%d, %lu)\n",
+ fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n",
4 + size_seq, sizeof(dst->key));
fprintf(stderr, errmsg, keyname);
return -ENOBUFS;
static void kwbimage_print_header(const void *ptr)
{
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
+ struct opt_hdr_v1 *ohdr;
printf("Image Type: MVEBU Boot from %s Image\n",
image_boot_mode_name(mhdr->blockid));
- printf("Image version:%d\n", image_version((void *)ptr));
- if (image_version((void *)ptr) == 1) {
- struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
+ printf("Image version:%d\n", kwbimage_version(ptr));
- if (mhdr->ext & 0x1) {
- struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *)
- ((uint8_t *)ptr +
- sizeof(*mhdr));
-
- while (1) {
- uint32_t ohdr_size;
-
- ohdr_size = (ohdr->headersz_msb << 16) |
- le16_to_cpu(ohdr->headersz_lsb);
- if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
- printf("BIN Hdr Size: ");
- genimg_print_size(ohdr_size - 12 - 4 * ohdr->data[0]);
- }
- if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1))
- break;
- ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr +
- ohdr_size);
- }
+ for_each_opt_hdr_v1 (ohdr, mhdr) {
+ if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
+ printf("BIN Hdr Size: ");
+ genimg_print_size(opt_hdr_v1_size(ohdr) - 12 -
+ 4 * ohdr->data[0]);
}
}
+
printf("Data Size: ");
genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
printf("Load Address: %08x\n", mhdr->destaddr);
static int kwbimage_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
- uint8_t checksum;
- size_t header_size = kwbimage_header_size(ptr);
+ size_t header_size = kwbheader_size(ptr);
+ uint8_t csum;
if (header_size > image_size)
return -FDT_ERR_BADSTRUCTURE;
return -FDT_ERR_BADSTRUCTURE;
/* Only version 0 extended header has checksum */
- if (image_version((void *)ptr) == 0) {
+ if (kwbimage_version(ptr) == 0) {
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
if (mhdr->ext & 0x1) {
- struct ext_hdr_v0 *ext_hdr;
-
- if (header_size + sizeof(*ext_hdr) > image_size)
- return -FDT_ERR_BADSTRUCTURE;
+ struct ext_hdr_v0 *ext_hdr = (void *)(mhdr + 1);
- ext_hdr = (struct ext_hdr_v0 *)
- (ptr + sizeof(struct main_hdr_v0));
- checksum = image_checksum8(ext_hdr,
- sizeof(struct ext_hdr_v0)
- - sizeof(uint8_t));
- if (checksum != ext_hdr->checksum)
+ csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
+ if (csum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
- } else if (image_version((void *)ptr) == 1) {
+ } else if (kwbimage_version(ptr) == 1) {
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
+ const uint8_t *mhdr_end;
+ struct opt_hdr_v1 *ohdr;
uint32_t offset;
uint32_t size;
- if (mhdr->ext & 0x1) {
- uint32_t ohdr_size;
- struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *)
- (ptr + sizeof(*mhdr));
-
- while (1) {
- if ((uint8_t *)ohdr + sizeof(*ohdr) >
- (uint8_t *)mhdr + header_size)
- return -FDT_ERR_BADSTRUCTURE;
-
- ohdr_size = (ohdr->headersz_msb << 16) |
- le16_to_cpu(ohdr->headersz_lsb);
-
- if (ohdr_size < 8 ||
- (uint8_t *)ohdr + ohdr_size >
- (uint8_t *)mhdr + header_size)
- return -FDT_ERR_BADSTRUCTURE;
-
- if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1))
- break;
- ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr +
- ohdr_size);
- }
- }
+ mhdr_end = (uint8_t *)mhdr + header_size;
+ for_each_opt_hdr_v1 (ohdr, ptr)
+ if (!opt_hdr_v1_valid_size(ohdr, mhdr_end))
+ return -FDT_ERR_BADSTRUCTURE;
offset = le32_to_cpu(mhdr->srcaddr);
static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params)
{
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
- size_t header_size = kwbimage_header_size(ptr);
+ size_t header_size = kwbheader_size(ptr);
+ struct opt_hdr_v1 *ohdr;
int idx = params->pflag;
int cur_idx = 0;
uint32_t offset;
ulong image;
ulong size;
- if (image_version((void *)ptr) == 1 && (mhdr->ext & 0x1)) {
- struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *)
- ((uint8_t *)ptr +
- sizeof(*mhdr));
+ for_each_opt_hdr_v1 (ohdr, ptr) {
+ if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE)
+ continue;
- while (1) {
- uint32_t ohdr_size = (ohdr->headersz_msb << 16) |
- le16_to_cpu(ohdr->headersz_lsb);
-
- if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
- if (idx == cur_idx) {
- image = (ulong)&ohdr->data[4 +
- 4 * ohdr->data[0]];
- size = ohdr_size - 12 -
- 4 * ohdr->data[0];
- goto extract;
- }
- ++cur_idx;
- }
- if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1))
- break;
- ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr +
- ohdr_size);
+ if (idx == cur_idx) {
+ image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]];
+ size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0];
+ goto extract;
}
+
+ ++cur_idx;
}
if (idx != cur_idx) {
/* NAND ECC Mode */
#define IBR_HDR_ECC_DEFAULT 0x00
#define IBR_HDR_ECC_FORCED_HAMMING 0x01
-#define IBR_HDR_ECC_FORCED_RS 0x02
-#define IBR_HDR_ECC_DISABLED 0x03
+#define IBR_HDR_ECC_FORCED_RS 0x02
+#define IBR_HDR_ECC_DISABLED 0x03
/* Boot Type - block ID */
#define IBR_HDR_I2C_ID 0x4D
uint8_t checksum;
} __packed;
-struct kwb_header {
- struct main_hdr_v0 kwb_hdr;
- struct ext_hdr_v0 kwb_exthdr;
-} __packed;
-
-/* Structure of the main header, version 1 (Armada 370/38x/XP) */
+/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
struct main_hdr_v1 {
uint8_t blockid; /* 0x0 */
uint8_t flags; /* 0x1 */
#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
/*
- * Header for the optional headers, version 1 (Armada 370, Armada XP)
+ * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x)
*/
struct opt_hdr_v1 {
uint8_t headertype;
} __packed;
/*
- * Structure of secure header (Armada 38x)
+ * Structure of secure header (Armada XP/375/38x/39x)
*/
struct secure_hdr_v1 {
uint8_t headertype; /* 0x0 */
#define OPT_HDR_V1_BINARY_TYPE 0x2
#define OPT_HDR_V1_REGISTER_TYPE 0x3
-#define KWBHEADER_V1_SIZE(hdr) \
- (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
-
enum kwbimage_cmd {
CMD_INVALID,
CMD_BOOT_FROM,
* header, byte 8 was reserved, and always set to 0. In the v1 header,
* byte 8 has been changed to a proper field, set to 1.
*/
-static inline unsigned int image_version(void *header)
+static inline unsigned int kwbimage_version(const void *header)
{
- unsigned char *ptr = header;
+ const unsigned char *ptr = header;
return ptr[8];
}
+static inline size_t kwbheader_size(const void *header)
+{
+ if (kwbimage_version(header) == 0) {
+ const struct main_hdr_v0 *hdr = header;
+
+ return sizeof(*hdr) +
+ (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0;
+ } else {
+ const struct main_hdr_v1 *hdr = header;
+
+ return (hdr->headersz_msb << 16) |
+ le16_to_cpu(hdr->headersz_lsb);
+ }
+}
+
+static inline size_t kwbheader_size_for_csum(const void *header)
+{
+ if (kwbimage_version(header) == 0)
+ return sizeof(struct main_hdr_v0);
+ else
+ return kwbheader_size(header);
+}
+
+static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
+{
+ return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
+}
+
+static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr,
+ const void *mhdr_end)
+{
+ uint32_t ohdr_size;
+
+ if ((void *)(ohdr + 1) > mhdr_end)
+ return 0;
+
+ ohdr_size = opt_hdr_v1_size(ohdr);
+ if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end)
+ return 0;
+
+ return 1;
+}
+
+static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) {
+ struct main_hdr_v1 *mhdr;
+
+ if (kwbimage_version(img) != 1)
+ return NULL;
+
+ mhdr = img;
+ if (mhdr->ext & 0x1)
+ return (struct opt_hdr_v1 *)(mhdr + 1);
+ else
+ return NULL;
+}
+
+static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur)
+{
+ uint32_t size = opt_hdr_v1_size(cur);
+
+ return (uint8_t *)cur + size - 4;
+}
+
+static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur)
+{
+ return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur));
+}
+
+static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur)
+{
+ if (*opt_hdr_v1_ext(cur) & 0x1)
+ return _opt_hdr_v1_next(cur);
+ else
+ return NULL;
+}
+
+#define for_each_opt_hdr_v1(ohdr, img) \
+ for ((ohdr) = opt_hdr_v1_first((img)); \
+ (ohdr) != NULL; \
+ (ohdr) = opt_hdr_v1_next((ohdr)))
+
#endif /* _KWBIMAGE_H_ */
/*
* Boot a Marvell SoC, with Xmodem over UART0.
- * supports Kirkwood, Dove, Armada 370, Armada XP
+ * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and
+ * Armada 39x
*
* (c) 2012 Daniel Stodden <daniel.stodden@gmail.com>
+ * (c) 2021 Pali Rohár <pali@kernel.org>
+ * (c) 2021 Marek Behún <marek.behun@nic.cz>
*
* References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281
* Integrated Controller: Functional Specifications" December 2,
#include "kwbimage.h"
#include "mkimage.h"
+#include "version.h"
#include <stdlib.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdint.h>
-#include <termios.h>
-#include <sys/mman.h>
+#include <time.h>
#include <sys/stat.h>
+#ifdef __linux__
+#include "termios_linux.h"
+#else
+#include <termios.h>
+#endif
+
/*
* Marvell BootROM UART Sensing
*/
#define NAK 21 /* target block negative ack */
#define CAN 24 /* target/sender transfer cancellation */
+#define KWBOOT_XM_BLKSZ 128 /* xmodem block size */
+
struct kwboot_block {
uint8_t soh;
uint8_t pnum;
uint8_t _pnum;
- uint8_t data[128];
+ uint8_t data[KWBOOT_XM_BLKSZ];
uint8_t csum;
} __packed;
#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */
+#define KWBOOT_HDR_RSP_TIMEO 10000 /* ms */
+
+/* ARM code making baudrate changing function return to original exec address */
+static unsigned char kwboot_pre_baud_code[] = {
+ /* exec_addr: */
+ 0x00, 0x00, 0x00, 0x00, /* .word 0 */
+ 0x0c, 0xe0, 0x1f, 0xe5, /* ldr lr, exec_addr */
+};
+
+/* ARM code for binary header injection to change baudrate */
+static unsigned char kwboot_baud_code[] = {
+ /* ; #define UART_BASE 0xd0012000 */
+ /* ; #define THR 0x00 */
+ /* ; #define DLL 0x00 */
+ /* ; #define DLH 0x04 */
+ /* ; #define LCR 0x0c */
+ /* ; #define DLAB 0x80 */
+ /* ; #define LSR 0x14 */
+ /* ; #define THRE 0x20 */
+ /* ; #define TEMT 0x40 */
+ /* ; #define DIV_ROUND(a, b) ((a + b/2) / b) */
+ /* ; */
+ /* ; u32 set_baudrate(u32 old_b, u32 new_b) { */
+ /* ; const u8 *str = "$baudratechange"; */
+ /* ; u8 c; */
+ /* ; do { */
+ /* ; c = *str++; */
+ /* ; writel(UART_BASE + THR, c); */
+ /* ; } while (c); */
+ /* ; while */
+ /* ; (!(readl(UART_BASE + LSR) & TEMT)); */
+ /* ; u32 lcr = readl(UART_BASE + LCR); */
+ /* ; writel(UART_BASE + LCR, lcr | DLAB); */
+ /* ; u8 old_dll = readl(UART_BASE + DLL); */
+ /* ; u8 old_dlh = readl(UART_BASE + DLH); */
+ /* ; u16 old_dl = old_dll | (old_dlh << 8); */
+ /* ; u32 clk = old_b * old_dl; */
+ /* ; u16 new_dl = DIV_ROUND(clk, new_b); */
+ /* ; u8 new_dll = new_dl & 0xff; */
+ /* ; u8 new_dlh = (new_dl >> 8) & 0xff; */
+ /* ; writel(UART_BASE + DLL, new_dll); */
+ /* ; writel(UART_BASE + DLH, new_dlh); */
+ /* ; writel(UART_BASE + LCR, lcr & ~DLAB); */
+ /* ; msleep(1); */
+ /* ; return 0; */
+ /* ; } */
+
+ 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */
+
+ /* ; r0 = UART_BASE */
+ 0x02, 0x0a, 0xa0, 0xe3, /* mov r0, #0x2000 */
+ 0x01, 0x00, 0x4d, 0xe3, /* movt r0, #0xd001 */
+
+ /* ; r2 = address of preamble string */
+ 0xd0, 0x20, 0x8f, 0xe2, /* adr r2, preamble */
+
+ /* ; Send preamble string over UART */
+ /* .Lloop_preamble: */
+ /* */
+ /* ; Wait until Transmitter Holding is Empty */
+ /* .Lloop_thre: */
+ /* ; r1 = UART_BASE[LSR] & THRE */
+ 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
+ 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */
+ 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */
+
+ /* ; Put character into Transmitter FIFO */
+ /* ; r1 = *r2++ */
+ 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */
+ /* ; UART_BASE[THR] = r1 */
+ 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */
+
+ /* ; Loop until end of preamble string */
+ 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
+ 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */
+
+ /* ; Wait until Transmitter FIFO is Empty */
+ /* .Lloop_txempty: */
+ /* ; r1 = UART_BASE[LSR] & TEMT */
+ 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
+ 0x40, 0x00, 0x11, 0xe3, /* tst r1, #0x40 */
+ 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_txempty */
+
+ /* ; Set Divisor Latch Access Bit */
+ /* ; UART_BASE[LCR] |= DLAB */
+ 0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */
+ 0x80, 0x10, 0x81, 0xe3, /* orr r1, r1, #0x80 */
+ 0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */
+
+ /* ; Read current Divisor Latch */
+ /* ; r1 = UART_BASE[DLH]<<8 | UART_BASE[DLL] */
+ 0x00, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x00] */
+ 0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */
+ 0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */
+ 0x04, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x04] */
+ 0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */
+ 0x41, 0x14, 0xa0, 0xe1, /* asr r1, r1, #8 */
+ 0x02, 0x10, 0x81, 0xe1, /* orr r1, r1, r2 */
+
+ /* ; Read old baudrate value */
+ /* ; r2 = old_baudrate */
+ 0x8c, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */
+
+ /* ; Calculate base clock */
+ /* ; r1 = r2 * r1 */
+ 0x92, 0x01, 0x01, 0xe0, /* mul r1, r2, r1 */
+
+ /* ; Read new baudrate value */
+ /* ; r2 = baudrate */
+ 0x88, 0x20, 0x9f, 0xe5, /* ldr r2, baudrate */
+
+ /* ; Calculate new Divisor Latch */
+ /* ; r1 = DIV_ROUND(r1, r2) = */
+ /* ; = (r1 + r2/2) / r2 */
+ 0xa2, 0x10, 0x81, 0xe0, /* add r1, r1, r2, lsr #1 */
+ 0x02, 0x40, 0xa0, 0xe1, /* mov r4, r2 */
+ 0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */
+ /* .Lloop_div1: */
+ 0x84, 0x40, 0xa0, 0x91, /* movls r4, r4, lsl #1 */
+ 0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */
+ 0xfc, 0xff, 0xff, 0x9a, /* bls .Lloop_div1 */
+ 0x00, 0x30, 0xa0, 0xe3, /* mov r3, #0 */
+ /* .Lloop_div2: */
+ 0x04, 0x00, 0x51, 0xe1, /* cmp r1, r4 */
+ 0x04, 0x10, 0x41, 0x20, /* subhs r1, r1, r4 */
+ 0x03, 0x30, 0xa3, 0xe0, /* adc r3, r3, r3 */
+ 0xa4, 0x40, 0xa0, 0xe1, /* mov r4, r4, lsr #1 */
+ 0x02, 0x00, 0x54, 0xe1, /* cmp r4, r2 */
+ 0xf9, 0xff, 0xff, 0x2a, /* bhs .Lloop_div2 */
+ 0x03, 0x10, 0xa0, 0xe1, /* mov r1, r3 */
+
+ /* ; Set new Divisor Latch Low */
+ /* ; UART_BASE[DLL] = r1 & 0xff */
+ 0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */
+ 0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */
+ 0x00, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x00] */
+
+ /* ; Set new Divisor Latch High */
+ /* ; UART_BASE[DLH] = r1>>8 & 0xff */
+ 0x41, 0x24, 0xa0, 0xe1, /* asr r2, r1, #8 */
+ 0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */
+ 0x04, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x04] */
+
+ /* ; Clear Divisor Latch Access Bit */
+ /* ; UART_BASE[LCR] &= ~DLAB */
+ 0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */
+ 0x80, 0x10, 0xc1, 0xe3, /* bic r1, r1, #0x80 */
+ 0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */
+
+ /* ; Sleep 1ms ~~ 600000 cycles at 1200 MHz */
+ /* ; r1 = 600000 */
+ 0x9f, 0x1d, 0xa0, 0xe3, /* mov r1, #0x27c0 */
+ 0x09, 0x10, 0x40, 0xe3, /* movt r1, #0x0009 */
+ /* .Lloop_sleep: */
+ 0x01, 0x10, 0x41, 0xe2, /* sub r1, r1, #1 */
+ 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
+ 0xfc, 0xff, 0xff, 0x1a, /* bne .Lloop_sleep */
+
+ /* ; Return 0 - no error */
+ 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */
+ 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */
+
+ /* ; Preamble string */
+ /* preamble: */
+ 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */
+ 0x64, 0x72, 0x61, 0x74,
+ 0x65, 0x63, 0x68, 0x61,
+ 0x6e, 0x67, 0x65, 0x00,
+
+ /* ; Placeholder for old baudrate value */
+ /* old_baudrate: */
+ 0x00, 0x00, 0x00, 0x00, /* .word 0 */
+
+ /* ; Placeholder for new baudrate value */
+ /* new_baudrate: */
+ 0x00, 0x00, 0x00, 0x00, /* .word 0 */
+};
+
+#define KWBOOT_BAUDRATE_BIN_HEADER_SZ (sizeof(kwboot_baud_code) + \
+ sizeof(struct opt_hdr_v1) + 8)
+
+static const char kwb_baud_magic[16] = "$baudratechange";
static int kwboot_verbose;
static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO;
static int blk_rsp_timeo = KWBOOT_BLK_RSP_TIMEO;
+static ssize_t
+kwboot_write(int fd, const char *buf, size_t len)
+{
+ size_t tot = 0;
+
+ while (tot < len) {
+ ssize_t wr = write(fd, buf + tot, len - tot);
+
+ if (wr < 0)
+ return -1;
+
+ tot += wr;
+ }
+
+ return tot;
+}
+
static void
kwboot_printv(const char *fmt, ...)
{
fputc(c, stdout);
nl = "]\n";
- pos++;
+ pos = (pos + 1) % width;
if (pct == 100) {
- while (pos++ < width)
+ while (pos && pos++ < width)
fputc(' ', stdout);
fputs(nl, stdout);
+ nl = "";
+ pos = 0;
}
fflush(stdout);
if (kwboot_verbose)
__progress(pct, c);
+
+ if (pct == 100)
+ pct = 0;
}
static int
static int
kwboot_tty_send(int fd, const void *buf, size_t len)
{
- int rc;
- ssize_t n;
-
if (!buf)
return 0;
- rc = -1;
-
- do {
- n = write(fd, buf, len);
- if (n < 0)
- goto out;
-
- buf = (char *)buf + n;
- len -= n;
- } while (len > 0);
+ if (kwboot_write(fd, buf, len) < 0)
+ return -1;
- rc = tcdrain(fd);
-out:
- return rc;
+ return tcdrain(fd);
}
static int
}
static speed_t
-kwboot_tty_speed(int baudrate)
+kwboot_tty_baudrate_to_speed(int baudrate)
{
switch (baudrate) {
+#ifdef B4000000
+ case 4000000:
+ return B4000000;
+#endif
+#ifdef B3500000
+ case 3500000:
+ return B3500000;
+#endif
+#ifdef B3000000
+ case 3000000:
+ return B3000000;
+#endif
+#ifdef B2500000
+ case 2500000:
+ return B2500000;
+#endif
+#ifdef B2000000
+ case 2000000:
+ return B2000000;
+#endif
+#ifdef B1500000
+ case 1500000:
+ return B1500000;
+#endif
+#ifdef B1152000
+ case 1152000:
+ return B1152000;
+#endif
+#ifdef B1000000
+ case 1000000:
+ return B1000000;
+#endif
+#ifdef B921600
+ case 921600:
+ return B921600;
+#endif
+#ifdef B614400
+ case 614400:
+ return B614400;
+#endif
+#ifdef B576000
+ case 576000:
+ return B576000;
+#endif
+#ifdef B500000
+ case 500000:
+ return B500000;
+#endif
+#ifdef B460800
+ case 460800:
+ return B460800;
+#endif
+#ifdef B307200
+ case 307200:
+ return B307200;
+#endif
+#ifdef B230400
+ case 230400:
+ return B230400;
+#endif
+#ifdef B153600
+ case 153600:
+ return B153600;
+#endif
+#ifdef B115200
case 115200:
return B115200;
+#endif
+#ifdef B76800
+ case 76800:
+ return B76800;
+#endif
+#ifdef B57600
case 57600:
return B57600;
+#endif
+#ifdef B38400
case 38400:
return B38400;
+#endif
+#ifdef B19200
case 19200:
return B19200;
+#endif
+#ifdef B9600
case 9600:
return B9600;
+#endif
+#ifdef B4800
+ case 4800:
+ return B4800;
+#endif
+#ifdef B2400
+ case 2400:
+ return B2400;
+#endif
+#ifdef B1800
+ case 1800:
+ return B1800;
+#endif
+#ifdef B1200
+ case 1200:
+ return B1200;
+#endif
+#ifdef B600
+ case 600:
+ return B600;
+#endif
+#ifdef B300
+ case 300:
+ return B300;
+#endif
+#ifdef B200
+ case 200:
+ return B200;
+#endif
+#ifdef B150
+ case 150:
+ return B150;
+#endif
+#ifdef B134
+ case 134:
+ return B134;
+#endif
+#ifdef B110
+ case 110:
+ return B110;
+#endif
+#ifdef B75
+ case 75:
+ return B75;
+#endif
+#ifdef B50
+ case 50:
+ return B50;
+#endif
+ default:
+#ifdef BOTHER
+ return BOTHER;
+#else
+ return B0;
+#endif
}
+}
+
+static int
+_is_within_tolerance(int value, int reference, int tolerance)
+{
+ return 100 * value >= reference * (100 - tolerance) &&
+ 100 * value <= reference * (100 + tolerance);
+}
+static int
+kwboot_tty_change_baudrate(int fd, int baudrate)
+{
+ struct termios tio;
+ speed_t speed;
+ int rc;
+
+ rc = tcgetattr(fd, &tio);
+ if (rc)
+ return rc;
+
+ speed = kwboot_tty_baudrate_to_speed(baudrate);
+ if (speed == B0) {
+ errno = EINVAL;
+ return -1;
+ }
+
+#ifdef BOTHER
+ if (speed == BOTHER)
+ tio.c_ospeed = tio.c_ispeed = baudrate;
+#endif
+
+ rc = cfsetospeed(&tio, speed);
+ if (rc)
+ return rc;
+
+ rc = cfsetispeed(&tio, speed);
+ if (rc)
+ return rc;
+
+ rc = tcsetattr(fd, TCSANOW, &tio);
+ if (rc)
+ return rc;
+
+ rc = tcgetattr(fd, &tio);
+ if (rc)
+ return rc;
+
+ if (cfgetospeed(&tio) != speed || cfgetispeed(&tio) != speed)
+ goto baud_fail;
+
+#ifdef BOTHER
+ /*
+ * Check whether set baudrate is within 3% tolerance.
+ * If BOTHER is defined, Linux always fills out c_ospeed / c_ispeed
+ * with real values.
+ */
+ if (!_is_within_tolerance(tio.c_ospeed, baudrate, 3))
+ goto baud_fail;
+
+ if (!_is_within_tolerance(tio.c_ispeed, baudrate, 3))
+ goto baud_fail;
+#endif
+
+ return 0;
+
+baud_fail:
+ fprintf(stderr, "Could not set baudrate to requested value\n");
+ errno = EINVAL;
return -1;
}
static int
-kwboot_open_tty(const char *path, speed_t speed)
+kwboot_open_tty(const char *path, int baudrate)
{
- int rc, fd;
+ int rc, fd, flags;
struct termios tio;
rc = -1;
- fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY);
+ fd = open(path, O_RDWR | O_NOCTTY | O_NDELAY);
if (fd < 0)
goto out;
- memset(&tio, 0, sizeof(tio));
-
- tio.c_iflag = 0;
- tio.c_cflag = CREAD|CLOCAL|CS8;
+ rc = tcgetattr(fd, &tio);
+ if (rc)
+ goto out;
+ cfmakeraw(&tio);
+ tio.c_cflag |= CREAD | CLOCAL;
tio.c_cc[VMIN] = 1;
- tio.c_cc[VTIME] = 10;
-
- cfsetospeed(&tio, speed);
- cfsetispeed(&tio, speed);
+ tio.c_cc[VTIME] = 0;
rc = tcsetattr(fd, TCSANOW, &tio);
if (rc)
goto out;
+ flags = fcntl(fd, F_GETFL);
+ if (flags < 0)
+ goto out;
+
+ rc = fcntl(fd, F_SETFL, flags & ~O_NDELAY);
+ if (rc)
+ goto out;
+
+ rc = kwboot_tty_change_baudrate(fd, baudrate);
+ if (rc)
+ goto out;
+
rc = fd;
out:
if (rc < 0) {
return rc;
}
-static int
+static size_t
kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
size_t size, int pnum)
{
- const size_t blksz = sizeof(block->data);
- size_t n;
- int i;
+ size_t i, n;
block->soh = SOH;
block->pnum = pnum;
block->_pnum = ~block->pnum;
- n = size < blksz ? size : blksz;
+ n = size < KWBOOT_XM_BLKSZ ? size : KWBOOT_XM_BLKSZ;
memcpy(&block->data[0], data, n);
- memset(&block->data[n], 0, blksz - n);
+ memset(&block->data[n], 0, KWBOOT_XM_BLKSZ - n);
block->csum = 0;
for (i = 0; i < n; i++)
return n;
}
-static int
-kwboot_xm_sendblock(int fd, struct kwboot_block *block)
+static uint64_t
+_now(void)
{
- int rc, retries;
- char c;
+ struct timespec ts;
- retries = 16;
- do {
- rc = kwboot_tty_send(fd, block, sizeof(*block));
- if (rc)
- break;
+ if (clock_gettime(CLOCK_MONOTONIC, &ts)) {
+ static int err_print;
- do {
- rc = kwboot_tty_recv(fd, &c, 1, blk_rsp_timeo);
- if (rc)
- break;
-
- if (c != ACK && c != NAK && c != CAN)
- printf("%c", c);
+ if (!err_print) {
+ perror("clock_gettime() does not work");
+ err_print = 1;
+ }
- } while (c != ACK && c != NAK && c != CAN);
+ /* this will just make the timeout not work */
+ return -1ULL;
+ }
- if (c != ACK)
- kwboot_progress(-1, '+');
+ return ts.tv_sec * 1000ULL + (ts.tv_nsec + 500000) / 1000000;
+}
- } while (c == NAK && retries-- > 0);
+static int
+_is_xm_reply(char c)
+{
+ return c == ACK || c == NAK || c == CAN;
+}
- rc = -1;
+static int
+_xm_reply_to_error(int c)
+{
+ int rc = -1;
switch (c) {
case ACK:
}
static int
-kwboot_xmodem(int tty, const void *_data, size_t size)
+kwboot_baud_magic_handle(int fd, char c, int baudrate)
{
- const uint8_t *data = _data;
- int rc, pnum, N, err;
+ static size_t rcv_len;
+
+ if (rcv_len < sizeof(kwb_baud_magic)) {
+ /* try to recognize whole magic word */
+ if (c == kwb_baud_magic[rcv_len]) {
+ rcv_len++;
+ } else {
+ printf("%.*s%c", (int)rcv_len, kwb_baud_magic, c);
+ fflush(stdout);
+ rcv_len = 0;
+ }
+ }
- pnum = 1;
- N = 0;
+ if (rcv_len == sizeof(kwb_baud_magic)) {
+ /* magic word received */
+ kwboot_printv("\nChanging baudrate to %d Bd\n", baudrate);
- kwboot_printv("Sending boot image...\n");
+ return kwboot_tty_change_baudrate(fd, baudrate) ? : 1;
+ } else {
+ return 0;
+ }
+}
- sleep(2); /* flush isn't effective without it */
- tcflush(tty, TCIOFLUSH);
+static int
+kwboot_xm_recv_reply(int fd, char *c, int allow_non_xm, int *non_xm_print,
+ int baudrate, int *baud_changed)
+{
+ int timeout = allow_non_xm ? KWBOOT_HDR_RSP_TIMEO : blk_rsp_timeo;
+ uint64_t recv_until = _now() + timeout;
+ int rc;
+
+ if (non_xm_print)
+ *non_xm_print = 0;
+ if (baud_changed)
+ *baud_changed = 0;
+ while (1) {
+ rc = kwboot_tty_recv(fd, c, 1, timeout);
+ if (rc) {
+ if (errno != ETIMEDOUT)
+ return rc;
+ else if (allow_non_xm && *non_xm_print)
+ return -1;
+ else
+ *c = NAK;
+ }
+
+ /* If received xmodem reply, end. */
+ if (_is_xm_reply(*c))
+ break;
+
+ /*
+ * If receiving/printing non-xmodem text output is allowed and
+ * such a byte was received, we want to increase receiving time
+ * and either:
+ * - print the byte, if it is not part of baudrate change magic
+ * sequence while baudrate change was requested (-B option)
+ * - change baudrate
+ * Otherwise decrease timeout by time elapsed.
+ */
+ if (allow_non_xm) {
+ recv_until = _now() + timeout;
+
+ if (baudrate && !*baud_changed) {
+ rc = kwboot_baud_magic_handle(fd, *c, baudrate);
+ if (rc == 1)
+ *baud_changed = 1;
+ else if (!rc)
+ *non_xm_print = 1;
+ else
+ return rc;
+ } else if (!baudrate || !*baud_changed) {
+ putchar(*c);
+ fflush(stdout);
+ *non_xm_print = 1;
+ }
+ } else {
+ timeout = recv_until - _now();
+ if (timeout < 0) {
+ errno = ETIMEDOUT;
+ return -1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int
+kwboot_xm_sendblock(int fd, struct kwboot_block *block, int allow_non_xm,
+ int *done_print, int baudrate)
+{
+ int non_xm_print, baud_changed;
+ int rc, err, retries;
+ char c;
+
+ *done_print = 0;
+
+ retries = 16;
do {
- struct kwboot_block block;
- int n;
+ rc = kwboot_tty_send(fd, block, sizeof(*block));
+ if (rc)
+ return rc;
- n = kwboot_xm_makeblock(&block,
- data + N, size - N,
- pnum++);
- if (n < 0)
+ if (allow_non_xm && !*done_print) {
+ kwboot_progress(100, '.');
+ kwboot_printv("Done\n");
+ *done_print = 1;
+ }
+
+ rc = kwboot_xm_recv_reply(fd, &c, allow_non_xm, &non_xm_print,
+ baudrate, &baud_changed);
+ if (rc)
goto can;
- if (!n)
- break;
+ if (!allow_non_xm && c != ACK)
+ kwboot_progress(-1, '+');
+ } while (c == NAK && retries-- > 0);
+
+ if (non_xm_print)
+ kwboot_printv("\n");
+
+ if (allow_non_xm && baudrate && !baud_changed) {
+ fprintf(stderr, "Baudrate was not changed\n");
+ rc = -1;
+ errno = EPROTO;
+ goto can;
+ }
+
+ return _xm_reply_to_error(c);
+can:
+ err = errno;
+ kwboot_tty_send_char(fd, CAN);
+ kwboot_printv("\n");
+ errno = err;
+ return rc;
+}
+
+static int
+kwboot_xm_finish(int fd)
+{
+ int rc, retries;
+ char c;
- rc = kwboot_xm_sendblock(tty, &block);
+ kwboot_printv("Finishing transfer\n");
+
+ retries = 16;
+ do {
+ rc = kwboot_tty_send_char(fd, EOT);
+ if (rc)
+ return rc;
+
+ rc = kwboot_xm_recv_reply(fd, &c, 0, NULL, 0, NULL);
+ if (rc)
+ return rc;
+ } while (c == NAK && retries-- > 0);
+
+ return _xm_reply_to_error(c);
+}
+
+static int
+kwboot_xmodem_one(int tty, int *pnum, int header, const uint8_t *data,
+ size_t size, int baudrate)
+{
+ int done_print = 0;
+ size_t sent, left;
+ int rc;
+
+ kwboot_printv("Sending boot image %s (%zu bytes)...\n",
+ header ? "header" : "data", size);
+
+ left = size;
+ sent = 0;
+
+ while (sent < size) {
+ struct kwboot_block block;
+ int last_block;
+ size_t blksz;
+
+ blksz = kwboot_xm_makeblock(&block, data, left, (*pnum)++);
+ data += blksz;
+
+ last_block = (left <= blksz);
+
+ rc = kwboot_xm_sendblock(tty, &block, header && last_block,
+ &done_print, baudrate);
if (rc)
goto out;
- N += n;
- kwboot_progress(N * 100 / size, '.');
- } while (1);
+ sent += blksz;
+ left -= blksz;
- rc = kwboot_tty_send_char(tty, EOT);
+ if (!done_print)
+ kwboot_progress(sent * 100 / size, '.');
+ }
+
+ if (!done_print)
+ kwboot_printv("Done\n");
+ return 0;
out:
+ kwboot_printv("\n");
return rc;
+}
-can:
- err = errno;
- kwboot_tty_send_char(tty, CAN);
- errno = err;
- goto out;
+static int
+kwboot_xmodem(int tty, const void *_img, size_t size, int baudrate)
+{
+ const uint8_t *img = _img;
+ int rc, pnum;
+ size_t hdrsz;
+
+ hdrsz = kwbheader_size(img);
+
+ kwboot_printv("Waiting 2s and flushing tty\n");
+ sleep(2); /* flush isn't effective without it */
+ tcflush(tty, TCIOFLUSH);
+
+ pnum = 1;
+
+ rc = kwboot_xmodem_one(tty, &pnum, 1, img, hdrsz, baudrate);
+ if (rc)
+ return rc;
+
+ img += hdrsz;
+ size -= hdrsz;
+
+ rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0);
+ if (rc)
+ return rc;
+
+ rc = kwboot_xm_finish(tty);
+ if (rc)
+ return rc;
+
+ if (baudrate) {
+ char buf[sizeof(kwb_baud_magic)];
+
+ /* Wait 1s for baudrate change magic */
+ rc = kwboot_tty_recv(tty, buf, sizeof(buf), 1000);
+ if (rc)
+ return rc;
+
+ if (memcmp(buf, kwb_baud_magic, sizeof(buf))) {
+ errno = EPROTO;
+ return -1;
+ }
+
+ kwboot_printv("\nChanging baudrate back to 115200 Bd\n\n");
+ rc = kwboot_tty_change_baudrate(tty, 115200);
+ if (rc)
+ return rc;
+ }
+
+ return 0;
}
static int
-kwboot_term_pipe(int in, int out, char *quit, int *s)
+kwboot_term_pipe(int in, int out, const char *quit, int *s)
{
- ssize_t nin, nout;
+ ssize_t nin;
char _buf[128], *buf = _buf;
nin = read(in, buf, sizeof(_buf));
buf++;
nin--;
} else {
- while (*s > 0) {
- nout = write(out, quit, *s);
- if (nout <= 0)
- return -1;
- (*s) -= nout;
- }
+ if (kwboot_write(out, quit, *s) < 0)
+ return -1;
+ *s = 0;
}
}
}
- while (nin > 0) {
- nout = write(out, buf, nin);
- if (nout <= 0)
- return -1;
- nin -= nout;
- }
+ if (kwboot_write(out, buf, nin) < 0)
+ return -1;
return 0;
}
kwboot_terminal(int tty)
{
int rc, in, s;
- char *quit = "\34c";
+ const char *quit = "\34c";
struct termios otio, tio;
rc = -1;
}
kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n",
- quit[0]|0100, quit[1]);
+ quit[0] | 0100, quit[1]);
} else
in = -1;
break;
}
- if (FD_ISSET(in, &rfds)) {
+ if (in >= 0 && FD_ISSET(in, &rfds)) {
rc = kwboot_term_pipe(in, tty, quit, &s);
if (rc)
break;
}
static void *
-kwboot_mmap_image(const char *path, size_t *size, int prot)
+kwboot_read_image(const char *path, size_t *size, size_t reserve)
{
- int rc, fd, flags;
+ int rc, fd;
struct stat st;
void *img;
+ off_t tot;
rc = -1;
img = NULL;
if (rc)
goto out;
- flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED;
-
- img = mmap(NULL, st.st_size, prot, flags, fd, 0);
- if (img == MAP_FAILED) {
- img = NULL;
+ img = malloc(st.st_size + reserve);
+ if (!img)
goto out;
+
+ tot = 0;
+ while (tot < st.st_size) {
+ ssize_t rd = read(fd, img + tot, st.st_size - tot);
+
+ if (rd < 0)
+ goto out;
+
+ tot += rd;
+
+ if (!rd && tot < st.st_size) {
+ errno = EIO;
+ goto out;
+ }
}
rc = 0;
*size = st.st_size;
out:
if (rc && img) {
- munmap(img, st.st_size);
+ free(img);
img = NULL;
}
if (fd >= 0)
}
static uint8_t
-kwboot_img_csum8(void *_data, size_t size)
+kwboot_hdr_csum8(const void *hdr)
{
- uint8_t *data = _data, csum;
+ const uint8_t *data = hdr;
+ uint8_t csum;
+ size_t size;
+
+ size = kwbheader_size_for_csum(hdr);
for (csum = 0; size-- > 0; data++)
csum += *data;
}
static int
-kwboot_img_patch_hdr(void *img, size_t size)
+kwboot_img_is_secure(void *img)
+{
+ struct opt_hdr_v1 *ohdr;
+
+ for_each_opt_hdr_v1 (ohdr, img)
+ if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE)
+ return 1;
+
+ return 0;
+}
+
+static void *
+kwboot_img_grow_data_left(void *img, size_t *size, size_t grow)
+{
+ uint32_t hdrsz, datasz, srcaddr;
+ struct main_hdr_v1 *hdr = img;
+ uint8_t *data;
+
+ srcaddr = le32_to_cpu(hdr->srcaddr);
+
+ hdrsz = kwbheader_size(hdr);
+ data = (uint8_t *)img + srcaddr;
+ datasz = *size - srcaddr;
+
+ /* only move data if there is not enough space */
+ if (hdrsz + grow > srcaddr) {
+ size_t need = hdrsz + grow - srcaddr;
+
+ /* move data by enough bytes */
+ memmove(data + need, data, datasz);
+ *size += need;
+ srcaddr += need;
+ }
+
+ srcaddr -= grow;
+ hdr->srcaddr = cpu_to_le32(srcaddr);
+ hdr->destaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) - grow);
+ hdr->blocksize = cpu_to_le32(le32_to_cpu(hdr->blocksize) + grow);
+
+ return (uint8_t *)img + srcaddr;
+}
+
+static void
+kwboot_img_grow_hdr(void *img, size_t *size, size_t grow)
+{
+ uint32_t hdrsz, datasz, srcaddr;
+ struct main_hdr_v1 *hdr = img;
+ uint8_t *data;
+
+ srcaddr = le32_to_cpu(hdr->srcaddr);
+
+ hdrsz = kwbheader_size(img);
+ data = (uint8_t *)img + srcaddr;
+ datasz = *size - srcaddr;
+
+ /* only move data if there is not enough space */
+ if (hdrsz + grow > srcaddr) {
+ size_t need = hdrsz + grow - srcaddr;
+
+ /* move data by enough bytes */
+ memmove(data + need, data, datasz);
+
+ hdr->srcaddr = cpu_to_le32(srcaddr + need);
+ *size += need;
+ }
+
+ if (kwbimage_version(img) == 1) {
+ hdrsz += grow;
+ hdr->headersz_msb = hdrsz >> 16;
+ hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff);
+ }
+}
+
+static void *
+kwboot_add_bin_ohdr_v1(void *img, size_t *size, uint32_t binsz)
+{
+ struct main_hdr_v1 *hdr = img;
+ struct opt_hdr_v1 *ohdr;
+ uint32_t ohdrsz;
+
+ ohdrsz = binsz + 8 + sizeof(*ohdr);
+ kwboot_img_grow_hdr(img, size, ohdrsz);
+
+ if (hdr->ext & 0x1) {
+ for_each_opt_hdr_v1 (ohdr, img)
+ if (opt_hdr_v1_next(ohdr) == NULL)
+ break;
+
+ *opt_hdr_v1_ext(ohdr) |= 1;
+ ohdr = opt_hdr_v1_next(ohdr);
+ } else {
+ hdr->ext |= 1;
+ ohdr = (void *)(hdr + 1);
+ }
+
+ ohdr->headertype = OPT_HDR_V1_BINARY_TYPE;
+ ohdr->headersz_msb = ohdrsz >> 16;
+ ohdr->headersz_lsb = cpu_to_le16(ohdrsz & 0xffff);
+
+ memset(&ohdr->data[0], 0, ohdrsz - sizeof(*ohdr));
+
+ return &ohdr->data[4];
+}
+
+static void
+_copy_baudrate_change_code(struct main_hdr_v1 *hdr, void *dst, int pre,
+ int old_baud, int new_baud)
+{
+ size_t codesz = sizeof(kwboot_baud_code);
+ uint8_t *code = dst;
+
+ if (pre) {
+ size_t presz = sizeof(kwboot_pre_baud_code);
+
+ /*
+ * We need to prepend code that loads lr register with original
+ * value of hdr->execaddr. We do this by putting the original
+ * exec address before the code that loads it relatively from
+ * it's beginning.
+ * Afterwards we change the exec address to this code (which is
+ * at offset 4, because the first 4 bytes contain the original
+ * exec address).
+ */
+ memcpy(code, kwboot_pre_baud_code, presz);
+ *(uint32_t *)code = hdr->execaddr;
+
+ hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + 4);
+
+ code += presz;
+ }
+
+ memcpy(code, kwboot_baud_code, codesz - 8);
+ *(uint32_t *)(code + codesz - 8) = cpu_to_le32(old_baud);
+ *(uint32_t *)(code + codesz - 4) = cpu_to_le32(new_baud);
+}
+
+static int
+kwboot_img_patch(void *img, size_t *size, int baudrate)
{
- int rc;
struct main_hdr_v1 *hdr;
+ uint32_t srcaddr;
uint8_t csum;
- size_t hdrsz = sizeof(*hdr);
+ size_t hdrsz;
int image_ver;
+ int is_secure;
- rc = -1;
hdr = img;
- if (size < hdrsz) {
- errno = EINVAL;
- goto out;
- }
+ if (*size < sizeof(struct main_hdr_v1))
+ goto err;
- image_ver = image_version(img);
+ image_ver = kwbimage_version(img);
if (image_ver != 0 && image_ver != 1) {
fprintf(stderr, "Invalid image header version\n");
- errno = EINVAL;
- goto out;
+ goto err;
}
- if (image_ver == 0)
- hdrsz = sizeof(*hdr);
- else
- hdrsz = KWBHEADER_V1_SIZE(hdr);
+ hdrsz = kwbheader_size(hdr);
- if (size < hdrsz) {
- errno = EINVAL;
- goto out;
+ if (*size < hdrsz)
+ goto err;
+
+ csum = kwboot_hdr_csum8(hdr) - hdr->checksum;
+ if (csum != hdr->checksum)
+ goto err;
+
+ if (image_ver == 0) {
+ struct main_hdr_v0 *hdr_v0 = img;
+
+ hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED;
+ hdr_v0->nandpagesize = 0;
}
- csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checksum;
- if (csum != hdr->checksum) {
- errno = EINVAL;
- goto out;
+ srcaddr = le32_to_cpu(hdr->srcaddr);
+
+ switch (hdr->blockid) {
+ case IBR_HDR_SATA_ID:
+ if (srcaddr < 1)
+ goto err;
+
+ hdr->srcaddr = cpu_to_le32((srcaddr - 1) * 512);
+ break;
+
+ case IBR_HDR_SDIO_ID:
+ hdr->srcaddr = cpu_to_le32(srcaddr * 512);
+ break;
+
+ case IBR_HDR_PEX_ID:
+ if (srcaddr == 0xFFFFFFFF)
+ hdr->srcaddr = cpu_to_le32(hdrsz);
+ break;
+
+ case IBR_HDR_SPI_ID:
+ if (hdr->destaddr == cpu_to_le32(0xFFFFFFFF)) {
+ kwboot_printv("Patching destination and execution addresses from SPI/NOR XIP area to DDR area 0x00800000\n");
+ hdr->destaddr = cpu_to_le32(0x00800000);
+ hdr->execaddr = cpu_to_le32(0x00800000);
+ }
+ break;
}
- if (hdr->blockid == IBR_HDR_UART_ID) {
- rc = 0;
- goto out;
+ if (hdrsz > le32_to_cpu(hdr->srcaddr) ||
+ *size < le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize))
+ goto err;
+
+ is_secure = kwboot_img_is_secure(img);
+
+ if (hdr->blockid != IBR_HDR_UART_ID) {
+ if (is_secure) {
+ fprintf(stderr,
+ "Image has secure header with signature for non-UART booting\n");
+ goto err;
+ }
+
+ kwboot_printv("Patching image boot signature to UART\n");
+ hdr->blockid = IBR_HDR_UART_ID;
}
- hdr->blockid = IBR_HDR_UART_ID;
+ if (baudrate) {
+ uint32_t codesz = sizeof(kwboot_baud_code);
+ void *code;
- if (image_ver == 0) {
- struct main_hdr_v0 *hdr_v0 = img;
+ if (image_ver == 0) {
+ fprintf(stderr,
+ "Cannot inject code for changing baudrate into v0 image header\n");
+ goto err;
+ }
- hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED;
- hdr_v0->nandpagesize = 0;
+ if (is_secure) {
+ fprintf(stderr,
+ "Cannot inject code for changing baudrate into image with secure header\n");
+ goto err;
+ }
- hdr_v0->srcaddr = hdr_v0->ext
- ? sizeof(struct kwb_header)
- : sizeof(*hdr_v0);
+ /*
+ * First inject code that changes the baudrate from the default
+ * value of 115200 Bd to requested value. This code is inserted
+ * as a new opt hdr, so it is executed by BootROM after the
+ * header part is received.
+ */
+ kwboot_printv("Injecting binary header code for changing baudrate to %d Bd\n",
+ baudrate);
+
+ code = kwboot_add_bin_ohdr_v1(img, size, codesz);
+ _copy_baudrate_change_code(hdr, code, 0, 115200, baudrate);
+
+ /*
+ * Now inject code that changes the baudrate back to 115200 Bd.
+ * This code is prepended to the data part of the image, so it
+ * is executed before U-Boot proper.
+ */
+ kwboot_printv("Injecting code for changing baudrate back\n");
+
+ codesz += sizeof(kwboot_pre_baud_code);
+ code = kwboot_img_grow_data_left(img, size, codesz);
+ _copy_baudrate_change_code(hdr, code, 1, baudrate, 115200);
+
+ /* recompute header size */
+ hdrsz = kwbheader_size(hdr);
}
- hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;
+ if (hdrsz % KWBOOT_XM_BLKSZ) {
+ size_t offset = (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) %
+ KWBOOT_XM_BLKSZ;
- rc = 0;
-out:
- return rc;
+ if (is_secure) {
+ fprintf(stderr, "Cannot align image with secure header\n");
+ goto err;
+ }
+
+ kwboot_printv("Aligning image header to Xmodem block size\n");
+ kwboot_img_grow_hdr(img, size, offset);
+ }
+
+ hdr->checksum = kwboot_hdr_csum8(hdr) - csum;
+
+ *size = le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize);
+ return 0;
+err:
+ errno = EINVAL;
+ return -1;
}
static void
kwboot_usage(FILE *stream, char *progname)
{
+ fprintf(stream, "kwboot version %s\n", PLAIN_VERSION);
fprintf(stream,
"Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n",
progname);
fprintf(stream, "\n");
fprintf(stream,
" -b <image>: boot <image> with preamble (Kirkwood, Armada 370/XP)\n");
- fprintf(stream, " -p: patch <image> to type 0x69 (uart boot)\n");
fprintf(stream,
" -D <image>: boot <image> without preamble (Dove)\n");
fprintf(stream, " -d: enter debug mode\n");
main(int argc, char **argv)
{
const char *ttypath, *imgpath;
- int rv, rc, tty, term, prot, patch;
+ int rv, rc, tty, term;
void *bootmsg;
void *debugmsg;
void *img;
size_t size;
- speed_t speed;
+ size_t after_img_rsv;
+ int baudrate;
rv = 1;
tty = -1;
imgpath = NULL;
img = NULL;
term = 0;
- patch = 0;
size = 0;
- speed = B115200;
+ after_img_rsv = KWBOOT_XM_BLKSZ;
+ baudrate = 115200;
kwboot_verbose = isatty(STDOUT_FILENO);
break;
case 'p':
- patch = 1;
+ /* nop, for backward compatibility */
break;
case 't':
break;
case 'B':
- speed = kwboot_tty_speed(atoi(optarg));
- if (speed == -1)
- goto usage;
+ baudrate = atoi(optarg);
break;
case 'h':
if (!bootmsg && !term && !debugmsg)
goto usage;
- if (patch && !imgpath)
- goto usage;
-
if (argc - optind < 1)
goto usage;
ttypath = argv[optind++];
- tty = kwboot_open_tty(ttypath, speed);
+ tty = kwboot_open_tty(ttypath, imgpath ? 115200 : baudrate);
if (tty < 0) {
perror(ttypath);
goto out;
}
- if (imgpath) {
- prot = PROT_READ | (patch ? PROT_WRITE : 0);
+ if (baudrate == 115200)
+ /* do not change baudrate during Xmodem to the same value */
+ baudrate = 0;
+ else
+ /* ensure we have enough space for baudrate change code */
+ after_img_rsv += KWBOOT_BAUDRATE_BIN_HEADER_SZ +
+ sizeof(kwboot_pre_baud_code) +
+ sizeof(kwboot_baud_code);
- img = kwboot_mmap_image(imgpath, &size, prot);
+ if (imgpath) {
+ img = kwboot_read_image(imgpath, &size, after_img_rsv);
if (!img) {
perror(imgpath);
goto out;
}
- }
- if (patch) {
- rc = kwboot_img_patch_hdr(img, size);
+ rc = kwboot_img_patch(img, &size, baudrate);
if (rc) {
fprintf(stderr, "%s: Invalid image.\n", imgpath);
goto out;
}
if (img) {
- rc = kwboot_xmodem(tty, img, size);
+ rc = kwboot_xmodem(tty, img, size, baudrate);
if (rc) {
perror("xmodem");
goto out;
close(tty);
if (img)
- munmap(img, size);
+ free(img);
return rv;
exit (EXIT_FAILURE);
}
+ if (sbuf.st_size == 0) {
+ fprintf (stderr, "%s: Input file %s is empty, bailing out\n",
+ params.cmdname, datafile);
+ exit (EXIT_FAILURE);
+ }
+
ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0);
if (ptr == MAP_FAILED) {
fprintf (stderr, "%s: Can't read %s: %s\n",
from patman import terminal
from patman import test_util
from patman import test_checkpatch
+from patman import tools
epilog = '''Create patches from commits in a branch, check them and email them
as specified by tags you place in the commits. Use -n to do a dry run first.'''
fd.close()
elif args.full_help:
- pager = os.getenv('PAGER')
- if not pager:
- pager = shutil.which('less')
- if not pager:
- pager = 'more'
- fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
- 'README')
- command.Run(pager, fname)
+ tools.PrintFullHelp(
+ os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README')
+ )
else:
# If we are not processing tags, no need to warning about bad ones
Date: Sat Apr 15 15:39:08 2017 -0600
pci: Correct cast for sandbox
-
+
This gives a warning with some native compilers:
-
+
cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type
‘long long unsigned int’, but argument 3 has type
‘u64 {aka long unsigned int}’ [-Wformat=]
-
+
Fix it with a cast.
-
+
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit-changes: 2
- second revision change
about some things
from the first commit
END
-
+
Commit-notes:
Some notes about
the first commit
Date: Sat Apr 15 15:39:08 2017 -0600
fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base()
-
+
This gives a warning with some native compilers:
-
+
lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type
‘long long unsigned int’, but argument 3 has type
‘long unsigned int’ [-Wformat=]
-
+
Fix it with a cast.
-
+
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-to: u-boot
Series-prefix: RFC
Cover-changes: 4
- Some notes for the cover letter
-
+
Cover-letter:
test: A test patch series
This is a test of how the cover
import glob
import os
+import shlex
import shutil
import struct
import sys
hex value of size, or 'None' if the value is None
"""
return 'None' if val is None else '%#x' % len(val)
+
+def PrintFullHelp(fname):
+ """Print the full help message for a tool using an appropriate pager.
+
+ Args:
+ fname: Path to a file containing the full help message
+ """
+ pager = shlex.split(os.getenv('PAGER', ''))
+ if not pager:
+ lesspath = shutil.which('less')
+ pager = [lesspath] if lesspath else None
+ if not pager:
+ pager = ['more']
+ command.Run(*pager, fname)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * termios fuctions to support arbitrary baudrates (on Linux)
+ *
+ * Copyright (c) 2021 Pali Rohár <pali@kernel.org>
+ * Copyright (c) 2021 Marek Behún <marek.behun@nic.cz>
+ */
+
+#ifndef _TERMIOS_LINUX_H_
+#define _TERMIOS_LINUX_H_
+
+/*
+ * We need to use raw TCGETS2/TCSETS2 or TCGETS/TCSETS ioctls with the BOTHER
+ * flag in struct termios2/termios, defined in Linux headers <asm/ioctls.h>
+ * (included by <sys/ioctl.h>) and <asm/termbits.h>. Since these headers
+ * conflict with glibc's header file <termios.h>, it is not possible to use
+ * libc's termios functions and we need to reimplement them via ioctl() calls.
+ *
+ * An arbitrary baudrate is supported when the macro BOTHER is defined. The
+ * baudrate value itself is then stored into the c_ospeed and c_ispeed members.
+ * If ioctls TCGETS2/TCSETS2 are defined and supported then these fields are
+ * present in struct termios2, otherwise these fields are present in struct
+ * termios.
+ *
+ * Note that the Bnnn constants from <termios.h> need not be compatible with Bnnn
+ * constants from <asm/termbits.h>.
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <asm/termbits.h>
+
+#if defined(BOTHER) && defined(TCGETS2)
+#define termios termios2
+#endif
+
+static inline int tcgetattr(int fd, struct termios *t)
+{
+#if defined(BOTHER) && defined(TCGETS2)
+ return ioctl(fd, TCGETS2, t);
+#else
+ return ioctl(fd, TCGETS, t);
+#endif
+}
+
+static inline int tcsetattr(int fd, int a, const struct termios *t)
+{
+ int cmd;
+
+ switch (a) {
+#if defined(BOTHER) && defined(TCGETS2)
+ case TCSANOW:
+ cmd = TCSETS2;
+ break;
+ case TCSADRAIN:
+ cmd = TCSETSW2;
+ break;
+ case TCSAFLUSH:
+ cmd = TCSETSF2;
+ break;
+#else
+ case TCSANOW:
+ cmd = TCSETS;
+ break;
+ case TCSADRAIN:
+ cmd = TCSETSW;
+ break;
+ case TCSAFLUSH:
+ cmd = TCSETSF;
+ break;
+#endif
+ default:
+ errno = EINVAL;
+ return -1;
+ }
+
+ return ioctl(fd, cmd, t);
+}
+
+static inline int tcdrain(int fd)
+{
+ return ioctl(fd, TCSBRK, 1);
+}
+
+static inline int tcflush(int fd, int q)
+{
+ return ioctl(fd, TCFLSH, q);
+}
+
+static inline int tcsendbreak(int fd, int d)
+{
+ return ioctl(fd, TCSBRK, d);
+}
+
+static inline int tcflow(int fd, int a)
+{
+ return ioctl(fd, TCXONC, a);
+}
+
+static inline pid_t tcgetsid(int fd)
+{
+ pid_t sid;
+
+ if (ioctl(fd, TIOCGSID, &sid) < 0)
+ return (pid_t)-1;
+
+ return sid;
+}
+
+static inline speed_t cfgetospeed(const struct termios *t)
+{
+ return t->c_cflag & CBAUD;
+}
+
+static inline int cfsetospeed(struct termios *t, speed_t s)
+{
+ if (s & ~CBAUD) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ t->c_cflag &= ~CBAUD;
+ t->c_cflag |= s;
+
+ return 0;
+}
+
+#ifdef IBSHIFT
+static inline speed_t cfgetispeed(const struct termios *t)
+{
+ speed_t s = (t->c_cflag >> IBSHIFT) & CBAUD;
+
+ if (s == B0)
+ return cfgetospeed(t);
+ else
+ return s;
+}
+
+static inline int cfsetispeed(struct termios *t, speed_t s)
+{
+ if (s == 0)
+ s = B0;
+
+ if (s & ~CBAUD) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ t->c_cflag &= ~(CBAUD << IBSHIFT);
+ t->c_cflag |= s << IBSHIFT;
+
+ return 0;
+}
+#else /* !IBSHIFT */
+static inline speed_t cfgetispeed(const struct termios *t)
+{
+ return cfgetospeed(t);
+}
+
+static inline int cfsetispeed(struct termios *t, speed_t s)
+{
+ return cfsetospeed(t, s);
+}
+#endif /* !IBSHIFT */
+
+static inline int cfsetspeed(struct termios *t, speed_t s)
+{
+ if (cfsetospeed(t, s))
+ return -1;
+#ifdef IBSHIFT
+ if (cfsetispeed(t, s))
+ return -1;
+#endif
+
+ return 0;
+}
+
+static void cfmakeraw(struct termios *t)
+{
+ t->c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR |
+ ICRNL | IXON);
+ t->c_oflag &= ~OPOST;
+ t->c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
+ t->c_cflag &= ~(CSIZE | PARENB);
+ t->c_cflag |= CS8;
+}
+
+#endif /* _TERMIOS_LINUX_H_ */
projects / platform / kernel / u-boot.git / commitdiff