arch/arm/dts/k3-j7200-common-proc-board.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j7200-som-p0.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/net/ti-dp83867.h>
  11 #include <dt-bindings/mux/ti-serdes.h>
  12 #include <dt-bindings/phy/phy.h>
  13
  14 / {
  15         chosen {
  16                 stdout-path = "serial2:115200n8";
  17                 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
  18         };
  19
  20         aliases {
  21                 remoteproc0 = &mcu_r5fss0_core0;
  22                 remoteproc1 = &mcu_r5fss0_core1;
  23                 remoteproc2 = &main_r5fss0_core0;
  24                 remoteproc3 = &main_r5fss0_core1;
  25         };
  26
  27         vdd_mmc1: fixedregulator-sd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "vdd_mmc1";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 regulator-boot-on;
  33                 enable-active-high;
  34                 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
  35         };
  36
  37         vdd_sd_dv: gpio-regulator-vdd-sd-dv {
  38                 compatible = "regulator-gpio";
  39                 regulator-name = "vdd_sd_dv";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&vdd_sd_dv_pins_default>;
  42                 regulator-min-microvolt = <1800000>;
  43                 regulator-max-microvolt = <3300000>;
  44                 regulator-boot-on;
  45                 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
  46                 states = <1800000 0x0
  47                           3300000 0x1>;
  48         };
  49 };
  50
  51 &wkup_pmx0 {
  52         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  53                 pinctrl-single,pins = <
  54                         J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
  55                         J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
  56                 >;
  57         };
  58
  59         wkup_gpio_pins_default: wkup-gpio-pins-default {
  60                 pinctrl-single,pins = <
  61                         J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
  62                 >;
  63         };
  64
  65         mcu_cpsw_pins_default: mcu-cpsw-pins-default {
  66                 pinctrl-single,pins = <
  67                         J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
  68                         J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
  69                         J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
  70                         J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
  71                         J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
  72                         J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
  73                         J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
  74                         J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
  75                         J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
  76                         J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
  77                         J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
  78                         J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
  79                 >;
  80         };
  81
  82         mcu_mdio_pins_default: mcu-mdio1-pins-default {
  83                 pinctrl-single,pins = <
  84                         J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  85                         J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  86                 >;
  87         };
  88 };
  89
  90 &main_pmx0 {
  91         main_i2c0_pins_default: main-i2c0-pins-default {
  92                 pinctrl-single,pins = <
  93                         J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
  94                         J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
  95                 >;
  96         };
  97
  98         main_i2c1_pins_default: main-i2c1-pins-default {
  99                 pinctrl-single,pins = <
 100                         J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
 101                         J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
 102                 >;
 103         };
 104
 105         main_mmc1_pins_default: main-mmc1-pins-default {
 106                 pinctrl-single,pins = <
 107                         J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
 108                         J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
 109                         J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
 110                         J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
 111                         J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
 112                         J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
 113                         J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
 114                         J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
 115                 >;
 116         };
 117
 118         vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
 119                 pinctrl-single,pins = <
 120                         J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
 121                 >;
 122         };
 123
 124         main_usbss0_pins_default: main-usbss0-pins-default {
 125                 pinctrl-single,pins = <
 126                         J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
 127                 >;
 128         };
 129 };
 130
 131 &wkup_uart0 {
 132         /* Wakeup UART is used by System firmware */
 133         status = "reserved";
 134 };
 135
 136 &main_uart0 {
 137         /* Shared with ATF on this platform */
 138         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 139 };
 140
 141 &main_uart2 {
 142         /* MAIN UART 2 is used by R5F firmware */
 143         status = "reserved";
 144 };
 145
 146 &main_uart3 {
 147         /* UART not brought out */
 148         status = "disabled";
 149 };
 150
 151 &main_uart4 {
 152         /* UART not brought out */
 153         status = "disabled";
 154 };
 155
 156 &main_uart5 {
 157         /* UART not brought out */
 158         status = "disabled";
 159 };
 160
 161 &main_uart6 {
 162         /* UART not brought out */
 163         status = "disabled";
 164 };
 165
 166 &main_uart7 {
 167         /* UART not brought out */
 168         status = "disabled";
 169 };
 170
 171 &main_uart8 {
 172         /* UART not brought out */
 173         status = "disabled";
 174 };
 175
 176 &main_uart9 {
 177         /* UART not brought out */
 178         status = "disabled";
 179 };
 180
 181 &mcu_cpsw {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 184 };
 185
 186 &davinci_mdio {
 187         phy0: ethernet-phy@0 {
 188                 reg = <0>;
 189                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 190                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 191         };
 192 };
 193
 194 &cpsw_port1 {
 195         phy-mode = "rgmii-rxid";
 196         phy-handle = <&phy0>;
 197 };
 198
 199 &main_i2c0 {
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&main_i2c0_pins_default>;
 202         clock-frequency = <400000>;
 203
 204         exp1: gpio@20 {
 205                 compatible = "ti,tca6416";
 206                 reg = <0x20>;
 207                 gpio-controller;
 208                 #gpio-cells = <2>;
 209         };
 210
 211         exp2: gpio@22 {
 212                 compatible = "ti,tca6424";
 213                 reg = <0x22>;
 214                 gpio-controller;
 215                 #gpio-cells = <2>;
 216         };
 217 };
 218
 219 /*
 220  * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
 221  * swapped on the CPB.
 222  *
 223  * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
 224  * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
 225  */
 226 &main_i2c1 {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&main_i2c1_pins_default>;
 229         clock-frequency = <400000>;
 230
 231         exp3: gpio@20 {
 232                 compatible = "ti,tca6408";
 233                 reg = <0x20>;
 234                 gpio-controller;
 235                 #gpio-cells = <2>;
 236                 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
 237                                   "UB926_LOCK", "UB926_PWR_SW_CNTRL",
 238                                   "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
 239         };
 240 };
 241
 242 &main_sdhci0 {
 243         /* eMMC */
 244         non-removable;
 245         ti,driver-strength-ohm = <50>;
 246         disable-wp;
 247 };
 248
 249 &main_sdhci1 {
 250         /* SD card */
 251         pinctrl-0 = <&main_mmc1_pins_default>;
 252         pinctrl-names = "default";
 253         vmmc-supply = <&vdd_mmc1>;
 254         vqmmc-supply = <&vdd_sd_dv>;
 255         ti,driver-strength-ohm = <50>;
 256         disable-wp;
 257 };
 258
 259 &serdes_ln_ctrl {
 260         idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
 261                       <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
 262 };
 263
 264 &usb_serdes_mux {
 265         idle-states = <1>; /* USB0 to SERDES lane 3 */
 266 };
 267
 268 &usbss0 {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&main_usbss0_pins_default>;
 271         ti,vbus-divider;
 272         ti,usb2-only;
 273 };
 274
 275 &usb0 {
 276         dr_mode = "otg";
 277         maximum-speed = "high-speed";
 278 };
 279
 280 &tscadc0 {
 281         adc {
 282                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 283         };
 284 };
 285
 286 &serdes_refclk {
 287         clock-frequency = <100000000>;
 288 };
 289
 290 &serdes0 {
 291         serdes0_pcie_link: link@0 {
 292                 reg = <0>;
 293                 cdns,num-lanes = <2>;
 294                 #phy-cells = <0>;
 295                 cdns,phy-type = <PHY_TYPE_PCIE>;
 296                 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
 297         };
 298
 299         serdes0_qsgmii_link: link@1 {
 300                 reg = <2>;
 301                 cdns,num-lanes = <1>;
 302                 #phy-cells = <0>;
 303                 cdns,phy-type = <PHY_TYPE_QSGMII>;
 304                 resets = <&serdes_wiz0 3>;
 305         };
 306 };