arch/arm/dts/k3-am64.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM642 SoC Family
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/k3.h>
  12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
  13
  14 / {
  15         model = "Texas Instruments K3 AM642 SoC";
  16         compatible = "ti,am642";
  17         interrupt-parent = <&gic500>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 serial0 = &mcu_uart0;
  23                 serial1 = &mcu_uart1;
  24                 serial2 = &main_uart0;
  25                 serial3 = &main_uart1;
  26                 serial4 = &main_uart2;
  27                 serial5 = &main_uart3;
  28                 serial6 = &main_uart4;
  29                 serial7 = &main_uart5;
  30                 serial8 = &main_uart6;
  31                 i2c0 = &main_i2c0;
  32                 i2c1 = &main_i2c1;
  33                 ethernet0 = &cpsw_port1;
  34                 ethernet1 = &cpsw_port2;
  35         };
  36
  37         chosen { };
  38
  39         firmware {
  40                 optee {
  41                         compatible = "linaro,optee-tz";
  42                         method = "smc";
  43                 };
  44
  45                 psci: psci {
  46                         compatible = "arm,psci-1.0";
  47                         method = "smc";
  48                 };
  49         };
  50
  51         a53_timer0: timer-cl0-cpu0 {
  52                 compatible = "arm,armv8-timer";
  53                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
  54                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
  55                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
  56                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
  57         };
  58
  59         pmu: pmu {
  60                 compatible = "arm,cortex-a53-pmu";
  61                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  62         };
  63
  64         cbass_main: bus@f4000 {
  65                 compatible = "simple-bus";
  66                 #address-cells = <2>;
  67                 #size-cells = <2>;
  68                 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
  69                          <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
  70                          <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
  71                          <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
  72                          <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
  73                          <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
  74                          <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
  75                          <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
  76                          <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
  77                          <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
  78                          <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
  79                          <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
  80                          <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
  81                          <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
  82                          <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
  83                          <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
  84                          <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
  85                          <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
  86                          <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
  87                          <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
  88                          <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
  89                          <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
  90                          <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
  91                          <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
  92
  93                          /* MCU Domain Range */
  94                          <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
  95
  96                 cbass_mcu: bus@4000000 {
  97                         compatible = "simple-bus";
  98                         #address-cells = <2>;
  99                         #size-cells = <2>;
 100                         ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
 101                 };
 102         };
 103 };
 104
 105 /* Now include the peripherals for each bus segments */
 106 #include "k3-am64-main.dtsi"
 107 #include "k3-am64-mcu.dtsi"