1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 #include <asm/config_mpc85xx.h>
13 #ifndef HWCONFIG_BUFFER_SIZE
14 #define HWCONFIG_BUFFER_SIZE 256
17 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
19 #ifndef CONFIG_MAX_MEM_MAPPED
20 #if defined(CONFIG_E500) || \
21 defined(CONFIG_MPC86xx) || \
23 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
25 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
30 * Provide a default boot page translation virtual address that lines up with
31 * Freescale's default e500 reset page.
33 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
34 #ifndef CONFIG_BPTR_VIRT_ADDR
35 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
39 /* Since so many PPC SOCs have a semi-common LBC, define this here */
40 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
41 defined(CONFIG_MPC83xx)
42 #if !defined(CONFIG_FSL_IFC)
43 #define CONFIG_FSL_LBC
47 /* The TSEC driver uses the PHYLIB infrastructure */
48 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
49 #include <config_phylib_all_drivers.h>
50 #endif /* TSEC_ENET */
52 /* The FMAN driver uses the PHYLIB infrastructure */
54 /* All PPC boards must swap IDE bytes */
55 #define CONFIG_IDE_SWAP_IO
57 #if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
59 * TODO: Convert this to a clock driver exists that can give us the UART
62 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
65 #endif /* _ASM_CONFIG_H_ */