board/technexion/pico-imx7d/pico-imx7d.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 NXP Semiconductors
   4  */
   5
   6 #include <init.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/mx7-pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/global_data.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <asm/io.h>
  18 #include <common.h>
  19 #include <i2c.h>
  20 #include <miiphy.h>
  21 #include <power/pmic.h>
  22 #include <power/pfuze3000_pmic.h>
  23 #include "../../freescale/common/pfuze.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  28         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  29
  30 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  31         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  32
  33 #ifdef CONFIG_SYS_I2C_MXC
  34 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  35
  36 /* I2C4 for PMIC */
  37 static struct i2c_pads_info i2c_pad_info4 = {
  38         .scl = {
  39                 .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
  40                 .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
  41                 .gp = IMX_GPIO_NR(6, 16),
  42         },
  43         .sda = {
  44                 .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
  45                 .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
  46                 .gp = IMX_GPIO_NR(6, 17),
  47         },
  48 };
  49 #endif
  50
  51 int dram_init(void)
  52 {
  53         gd->ram_size = imx_ddr_size();
  54
  55         /* Subtract the defined OPTEE runtime firmware length */
  56 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
  57                 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
  58 #endif
  59
  60         return 0;
  61 }
  62
  63 #ifdef CONFIG_POWER
  64 #define I2C_PMIC        3
  65 int power_init_board(void)
  66 {
  67         struct pmic *p;
  68         int ret;
  69         unsigned int reg, rev_id;
  70
  71         ret = power_pfuze3000_init(I2C_PMIC);
  72         if (ret)
  73                 return ret;
  74
  75         p = pmic_get("PFUZE3000");
  76         ret = pmic_probe(p);
  77         if (ret) {
  78                 printf("Warning:  Cannot find PMIC PFUZE3000\n");
  79                 printf("\tPower consumption is not optimized.\n");
  80                 return 0;
  81         }
  82
  83         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  84         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  85         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  86
  87         /* disable Low Power Mode during standby mode */
  88         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  89         reg |= 0x1;
  90         pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  91
  92         /* SW1A/1B mode set to APS/APS */
  93         reg = 0x8;
  94         pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
  95         pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
  96
  97         /* SW1A/1B standby voltage set to 1.025V */
  98         reg = 0xd;
  99         pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 100         pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 101
 102         /* decrease SW1B normal voltage to 0.975V */
 103         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 104         reg &= ~0x1f;
 105         reg |= PFUZE3000_SW1AB_SETP(975);
 106         pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 107
 108         return 0;
 109 }
 110 #endif
 111
 112 static iomux_v3_cfg_t const wdog_pads[] = {
 113         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 114 };
 115
 116 static iomux_v3_cfg_t const uart5_pads[] = {
 117         MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 118         MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 119 };
 120
 121 #ifdef CONFIG_FEC_MXC
 122 static int setup_fec(void)
 123 {
 124         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 125                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 126
 127         /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
 128         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 129                         (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 130                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 131
 132         return set_clk_enet(ENET_125MHZ);
 133 }
 134
 135 int board_phy_config(struct phy_device *phydev)
 136 {
 137         unsigned short val;
 138
 139         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 140         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 141         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 142         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 143
 144         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 145         val &= 0xffe7;
 146         val |= 0x18;
 147         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 148
 149         /* introduce tx clock delay */
 150         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 151         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 152         val |= 0x0100;
 153         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 154
 155         if (phydev->drv->config)
 156                 phydev->drv->config(phydev);
 157
 158         return 0;
 159 }
 160 #endif
 161
 162 static void setup_iomux_uart(void)
 163 {
 164         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 165 }
 166
 167 int board_early_init_f(void)
 168 {
 169         setup_iomux_uart();
 170
 171 #ifdef CONFIG_SYS_I2C_MXC
 172         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 173 #endif
 174
 175         return 0;
 176 }
 177
 178 #ifdef CONFIG_DM_VIDEO
 179 void setup_lcd(void)
 180 {
 181         gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
 182         gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
 183         /* Set Brightness to high */
 184         gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
 185         /* Set LCD enable to high */
 186         gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
 187 }
 188 #endif
 189
 190 int board_init(void)
 191 {
 192         /* address of boot parameters */
 193         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 194
 195 #ifdef CONFIG_DM_VIDEO
 196         setup_lcd();
 197 #endif
 198 #ifdef CONFIG_FEC_MXC
 199         setup_fec();
 200 #endif
 201
 202         return 0;
 203 }
 204
 205 int board_late_init(void)
 206 {
 207         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 208
 209         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 210
 211         set_wdog_reset(wdog);
 212
 213         /*
 214          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 215          * since we use PMIC_PWRON to reset the board.
 216          */
 217         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 218
 219         return 0;
 220 }
 221
 222 int checkboard(void)
 223 {
 224         puts("Board: i.MX7D PICOSOM\n");
 225
 226         return 0;
 227 }
 228
 229 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 230         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 231 };
 232
 233 int board_ehci_hcd_init(int port)
 234 {
 235         switch (port) {
 236         case 0:
 237                 break;
 238         case 1:
 239                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 240                                                  ARRAY_SIZE(usb_otg2_pads));
 241                 break;
 242         default:
 243                 return -EINVAL;
 244         }
 245         return 0;
 246 }
 247