arch/arm/dts/k3-am64.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM642 SoC Family
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/k3.h>
  12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
  13
  14 / {
  15         model = "Texas Instruments K3 AM642 SoC";
  16         compatible = "ti,am642";
  17         interrupt-parent = <&gic500>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 serial0 = &mcu_uart0;
  23                 serial1 = &mcu_uart1;
  24                 serial2 = &main_uart0;
  25                 serial3 = &main_uart1;
  26                 serial4 = &main_uart2;
  27                 serial5 = &main_uart3;
  28                 serial6 = &main_uart4;
  29                 serial7 = &main_uart5;
  30                 serial8 = &main_uart6;
  31                 ethernet0 = &cpsw_port1;
  32                 ethernet1 = &cpsw_port2;
  33         };
  34
  35         chosen { };
  36
  37         firmware {
  38                 optee {
  39                         compatible = "linaro,optee-tz";
  40                         method = "smc";
  41                 };
  42
  43                 psci: psci {
  44                         compatible = "arm,psci-1.0";
  45                         method = "smc";
  46                 };
  47         };
  48
  49         a53_timer0: timer-cl0-cpu0 {
  50                 compatible = "arm,armv8-timer";
  51                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
  52                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
  53                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
  54                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
  55         };
  56
  57         pmu: pmu {
  58                 compatible = "arm,cortex-a53-pmu";
  59                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  60         };
  61
  62         cbass_main: bus@f4000 {
  63                 compatible = "simple-bus";
  64                 #address-cells = <2>;
  65                 #size-cells = <2>;
  66                 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
  67                          <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
  68                          <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
  69                          <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
  70                          <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
  71                          <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
  72                          <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
  73                          <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
  74                          <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
  75                          <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
  76                          <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
  77                          <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
  78                          <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
  79                          <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
  80                          <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
  81                          <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
  82                          <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
  83                          <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
  84                          <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
  85                          <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
  86                          <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
  87                          <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
  88                          <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
  89                          <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
  90
  91                          /* MCU Domain Range */
  92                          <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
  93
  94                 cbass_mcu: bus@4000000 {
  95                         compatible = "simple-bus";
  96                         #address-cells = <2>;
  97                         #size-cells = <2>;
  98                         ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
  99                 };
 100         };
 101 };
 102
 103 /* Now include the peripherals for each bus segments */
 104 #include "k3-am64-main.dtsi"
 105 #include "k3-am64-mcu.dtsi"