drivers/mmc/ftsdc010_mci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Faraday MMC/SD Host Controller
   4  *
   5  * (C) Copyright 2010 Faraday Technology
   6  * Dante Su <dantesu@faraday-tech.com>
   7  *
   8  * Copyright 2018 Andes Technology, Inc.
   9  * Author: Rick Chen (rick@andestech.com)
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <part.h>
  17 #include <mmc.h>
  18 #include <asm/global_data.h>
  19 #include <linux/bitops.h>
  20 #include <linux/io.h>
  21 #include <linux/errno.h>
  22 #include <asm/byteorder.h>
  23 #include <faraday/ftsdc010.h>
  24 #include "ftsdc010_mci.h"
  25 #include <dm.h>
  26 #include <dt-structs.h>
  27 #include <errno.h>
  28 #include <mapmem.h>
  29 #include <pwrseq.h>
  30 #include <syscon.h>
  31 #include <linux/err.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
  36 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
  37
  38 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  39 struct ftsdc010 {
  40         fdt32_t         bus_width;
  41         bool            cap_mmc_highspeed;
  42         bool            cap_sd_highspeed;
  43         fdt32_t         clock_freq_min_max[2];
  44         struct phandle_2_cell   clocks[4];
  45         fdt32_t         fifo_depth;
  46         fdt32_t         reg[2];
  47 };
  48 #endif
  49
  50 struct ftsdc010_plat {
  51 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  52         struct ftsdc010 dtplat;
  53 #endif
  54         struct mmc_config cfg;
  55         struct mmc mmc;
  56 };
  57
  58 struct ftsdc_priv {
  59         struct clk clk;
  60         struct ftsdc010_chip chip;
  61         int fifo_depth;
  62         bool fifo_mode;
  63         u32 minmax[2];
  64 };
  65
  66 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
  67 {
  68         struct ftsdc010_chip *chip = mmc->priv;
  69         struct ftsdc010_mmc __iomem *regs = chip->regs;
  70         int ret = -ETIMEDOUT;
  71         uint32_t ts, st;
  72         uint32_t cmd   = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
  73         uint32_t arg   = mmc_cmd->cmdarg;
  74         uint32_t flags = mmc_cmd->resp_type;
  75
  76         cmd |= FTSDC010_CMD_CMD_EN;
  77
  78         if (chip->acmd) {
  79                 cmd |= FTSDC010_CMD_APP_CMD;
  80                 chip->acmd = 0;
  81         }
  82
  83         if (flags & MMC_RSP_PRESENT)
  84                 cmd |= FTSDC010_CMD_NEED_RSP;
  85
  86         if (flags & MMC_RSP_136)
  87                 cmd |= FTSDC010_CMD_LONG_RSP;
  88
  89         writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
  90                 &regs->clr);
  91         writel(arg, &regs->argu);
  92         writel(cmd, &regs->cmd);
  93
  94         if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
  95                 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  96                         if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
  97                                 writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
  98                                 ret = 0;
  99                                 break;
 100                         }
 101                 }
 102         } else {
 103                 st = 0;
 104                 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
 105                         st = readl(&regs->status);
 106                         writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
 107                         if (st & FTSDC010_STATUS_RSP_MASK)
 108                                 break;
 109                 }
 110                 if (st & FTSDC010_STATUS_RSP_CRC_OK) {
 111                         if (flags & MMC_RSP_136) {
 112                                 mmc_cmd->response[0] = readl(&regs->rsp3);
 113                                 mmc_cmd->response[1] = readl(&regs->rsp2);
 114                                 mmc_cmd->response[2] = readl(&regs->rsp1);
 115                                 mmc_cmd->response[3] = readl(&regs->rsp0);
 116                         } else {
 117                                 mmc_cmd->response[0] = readl(&regs->rsp0);
 118                         }
 119                         ret = 0;
 120                 } else {
 121                         debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
 122                                 mmc_cmd->cmdidx, st);
 123                 }
 124         }
 125
 126         if (ret) {
 127                 debug("ftsdc010: cmd timeout (op code=%d)\n",
 128                         mmc_cmd->cmdidx);
 129         } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
 130                 chip->acmd = 1;
 131         }
 132
 133         return ret;
 134 }
 135
 136 static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
 137 {
 138         struct ftsdc010_chip *chip = mmc->priv;
 139         struct ftsdc010_mmc __iomem *regs = chip->regs;
 140         uint32_t div;
 141
 142         for (div = 0; div < 0x7f; ++div) {
 143                 if (rate >= chip->sclk / (2 * (div + 1)))
 144                         break;
 145         }
 146         chip->rate = chip->sclk / (2 * (div + 1));
 147
 148         writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
 149
 150         if (IS_SD(mmc)) {
 151                 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
 152
 153                 if (chip->rate > 25000000)
 154                         setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
 155                 else
 156                         clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
 157         }
 158 }
 159
 160 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
 161 {
 162         int ret = -ETIMEDOUT;
 163         uint32_t st, timeout = 10000000;
 164         while (timeout--) {
 165                 st = readl(&regs->status);
 166                 if (!(st & mask))
 167                         continue;
 168                 writel(st & mask, &regs->clr);
 169                 ret = 0;
 170                 break;
 171         }
 172
 173         if (ret){
 174                 debug("ftsdc010: wait st(0x%x) timeout\n", mask);
 175         }
 176
 177         return ret;
 178 }
 179
 180 /*
 181  * u-boot mmc api
 182  */
 183 static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
 184         struct mmc_data *data)
 185 {
 186         struct mmc *mmc = mmc_get_mmc_dev(dev);
 187         int ret = -EOPNOTSUPP;
 188         uint32_t len = 0;
 189         struct ftsdc010_chip *chip = mmc->priv;
 190         struct ftsdc010_mmc __iomem *regs = chip->regs;
 191
 192         if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
 193                 printf("ftsdc010: the card is write protected!\n");
 194                 return ret;
 195         }
 196
 197         if (data) {
 198                 uint32_t dcr;
 199
 200                 len = data->blocksize * data->blocks;
 201
 202                 /* 1. data disable + fifo reset */
 203                 dcr = 0;
 204 #ifdef CONFIG_FTSDC010_SDIO
 205                 dcr |= FTSDC010_DCR_FIFO_RST;
 206 #endif
 207                 writel(dcr, &regs->dcr);
 208
 209                 /* 2. clear status register */
 210                 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
 211                         | FTSDC010_STATUS_FIFO_ORUN, &regs->clr);
 212
 213                 /* 3. data timeout (1 sec) */
 214                 writel(chip->rate, &regs->dtr);
 215
 216                 /* 4. data length (bytes) */
 217                 writel(len, &regs->dlr);
 218
 219                 /* 5. data enable */
 220                 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
 221                 if (data->flags & MMC_DATA_WRITE)
 222                         dcr |= FTSDC010_DCR_DATA_WRITE;
 223                 writel(dcr, &regs->dcr);
 224         }
 225
 226         ret = ftsdc010_send_cmd(mmc, cmd);
 227         if (ret) {
 228                 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
 229                 return ret;
 230         }
 231
 232         if (!data)
 233                 return ret;
 234
 235         if (data->flags & MMC_DATA_WRITE) {
 236                 const uint8_t *buf = (const uint8_t *)data->src;
 237
 238                 while (len > 0) {
 239                         int wlen;
 240
 241                         /* wait for tx ready */
 242                         ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
 243                         if (ret)
 244                                 break;
 245
 246                         /* write bytes to ftsdc010 */
 247                         for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
 248                                 writel(*(uint32_t *)buf, &regs->dwr);
 249                                 buf  += 4;
 250                                 wlen += 4;
 251                         }
 252
 253                         len -= wlen;
 254                 }
 255
 256         } else {
 257                 uint8_t *buf = (uint8_t *)data->dest;
 258
 259                 while (len > 0) {
 260                         int rlen;
 261
 262                         /* wait for rx ready */
 263                         ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
 264                         if (ret)
 265                                 break;
 266
 267                         /* fetch bytes from ftsdc010 */
 268                         for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
 269                                 *(uint32_t *)buf = readl(&regs->dwr);
 270                                 buf  += 4;
 271                                 rlen += 4;
 272                         }
 273
 274                         len -= rlen;
 275                 }
 276
 277         }
 278
 279         if (!ret) {
 280                 ret = ftsdc010_wait(regs,
 281                         FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
 282         }
 283
 284         return ret;
 285 }
 286
 287 static int ftsdc010_set_ios(struct udevice *dev)
 288 {
 289         struct mmc *mmc = mmc_get_mmc_dev(dev);
 290         struct ftsdc010_chip *chip = mmc->priv;
 291         struct ftsdc010_mmc __iomem *regs = chip->regs;
 292
 293         ftsdc010_clkset(mmc, mmc->clock);
 294
 295         clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
 296         switch (mmc->bus_width) {
 297         case 4:
 298                 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
 299                 break;
 300         case 8:
 301                 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
 302                 break;
 303         default:
 304                 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
 305                 break;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int ftsdc010_get_cd(struct udevice *dev)
 312 {
 313         struct mmc *mmc = mmc_get_mmc_dev(dev);
 314         struct ftsdc010_chip *chip = mmc->priv;
 315         struct ftsdc010_mmc __iomem *regs = chip->regs;
 316         return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
 317 }
 318
 319 static int ftsdc010_get_wp(struct udevice *dev)
 320 {
 321         struct mmc *mmc = mmc_get_mmc_dev(dev);
 322         struct ftsdc010_chip *chip = mmc->priv;
 323         struct ftsdc010_mmc __iomem *regs = chip->regs;
 324         if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
 325                 printf("ftsdc010: write protected\n");
 326                 chip->wprot = 1;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int ftsdc010_init(struct mmc *mmc)
 333 {
 334         struct ftsdc010_chip *chip = mmc->priv;
 335         struct ftsdc010_mmc __iomem *regs = chip->regs;
 336         uint32_t ts;
 337
 338         chip->fifo = (readl(&regs->feature) & 0xff) << 2;
 339
 340         /* 1. chip reset */
 341         writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
 342         for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
 343                 if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
 344                         continue;
 345                 break;
 346         }
 347         if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
 348                 printf("ftsdc010: reset failed\n");
 349                 return -EOPNOTSUPP;
 350         }
 351
 352         /* 2. enter low speed mode (400k card detection) */
 353         ftsdc010_clkset(mmc, 400000);
 354
 355         /* 3. interrupt disabled */
 356         writel(0, &regs->int_mask);
 357
 358         return 0;
 359 }
 360
 361 static int ftsdc010_probe(struct udevice *dev)
 362 {
 363         struct mmc *mmc = mmc_get_mmc_dev(dev);
 364         return ftsdc010_init(mmc);
 365 }
 366
 367 const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
 368         .send_cmd       = ftsdc010_request,
 369         .set_ios        = ftsdc010_set_ios,
 370         .get_cd         = ftsdc010_get_cd,
 371         .get_wp         = ftsdc010_get_wp,
 372 };
 373
 374 static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 375                      uint caps, u32 max_clk, u32 min_clk)
 376 {
 377         cfg->name = name;
 378         cfg->f_min = min_clk;
 379         cfg->f_max = max_clk;
 380         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 381         cfg->host_caps = caps;
 382         if (buswidth == 8) {
 383                 cfg->host_caps |= MMC_MODE_8BIT;
 384                 cfg->host_caps &= ~MMC_MODE_4BIT;
 385         } else {
 386                 cfg->host_caps |= MMC_MODE_4BIT;
 387                 cfg->host_caps &= ~MMC_MODE_8BIT;
 388         }
 389         cfg->part_type = PART_TYPE_DOS;
 390         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 391 }
 392
 393 static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
 394 {
 395 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 396         struct ftsdc_priv *priv = dev_get_priv(dev);
 397         struct ftsdc010_chip *chip = &priv->chip;
 398         chip->name = dev->name;
 399         chip->ioaddr = dev_read_addr_ptr(dev);
 400         chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 401                                         "bus-width", 4);
 402         chip->priv = dev;
 403         priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 404                                     "fifo-depth", 0);
 405         priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
 406                                           "fifo-mode");
 407         if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
 408                          "clock-freq-min-max", priv->minmax, 2)) {
 409                 int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 410                                   "max-frequency", -EINVAL);
 411                 if (val < 0)
 412                         return val;
 413
 414                 priv->minmax[0] = 400000;  /* 400 kHz */
 415                 priv->minmax[1] = val;
 416         } else {
 417                 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
 418                 __func__);
 419         }
 420 #endif
 421         chip->sclk = priv->minmax[1];
 422         chip->regs = chip->ioaddr;
 423         return 0;
 424 }
 425
 426 static int ftsdc010_mmc_probe(struct udevice *dev)
 427 {
 428         struct ftsdc010_plat *plat = dev_get_plat(dev);
 429         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 430         struct ftsdc_priv *priv = dev_get_priv(dev);
 431         struct ftsdc010_chip *chip = &priv->chip;
 432         struct udevice *pwr_dev __maybe_unused;
 433
 434 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 435         int ret;
 436         struct ftsdc010 *dtplat = &plat->dtplat;
 437         chip->name = dev->name;
 438         chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
 439         chip->buswidth = dtplat->bus_width;
 440         chip->priv = dev;
 441         chip->dev_index = 1;
 442         memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
 443         ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
 444         if (ret < 0)
 445                 return ret;
 446 #endif
 447
 448         if (dev_read_bool(dev, "cap-mmc-highspeed") || \
 449                   dev_read_bool(dev, "cap-sd-highspeed"))
 450                 chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 451
 452         ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
 453                         priv->minmax[1] , priv->minmax[0]);
 454         chip->mmc = &plat->mmc;
 455         chip->mmc->priv = &priv->chip;
 456         chip->mmc->dev = dev;
 457         upriv->mmc = chip->mmc;
 458         return ftsdc010_probe(dev);
 459 }
 460
 461 int ftsdc010_mmc_bind(struct udevice *dev)
 462 {
 463         struct ftsdc010_plat *plat = dev_get_plat(dev);
 464
 465         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 466 }
 467
 468 static const struct udevice_id ftsdc010_mmc_ids[] = {
 469         { .compatible = "andestech,atfsdc010" },
 470         { }
 471 };
 472
 473 U_BOOT_DRIVER(ftsdc010_mmc) = {
 474         .name           = "ftsdc010_mmc",
 475         .id             = UCLASS_MMC,
 476         .of_match       = ftsdc010_mmc_ids,
 477         .of_to_plat = ftsdc010_mmc_of_to_plat,
 478         .ops            = &dm_ftsdc010_mmc_ops,
 479         .bind           = ftsdc010_mmc_bind,
 480         .probe          = ftsdc010_mmc_probe,
 481         .priv_auto      = sizeof(struct ftsdc_priv),
 482         .plat_auto      = sizeof(struct ftsdc010_plat),
 483 };