# May be overridden by arch/$(ARCH)/config.mk
ifdef CONFIG_LTO
quiet_cmd_u-boot__ ?= LTO $@
- cmd_u-boot__ ?= \
+ cmd_u-boot__ ?= \
$(CC) -nostdlib -nostartfiles \
$(LTO_FINAL_LDFLAGS) $(c_flags) \
$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \
typedef unsigned int UHItype __attribute__ ((mode (HI)));
#if MIN_UNITS_PER_WORD > 1
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
#if __SIZEOF_LONG_LONG__ > 4
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
- .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
- .word 0xe5901008 // ldr r1, [r0, #8]
- .word 0xe129f001 // msr CPSR_fc, r1
+ .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
+ .word 0xe5901008 // ldr r1, [r0, #8]
+ .word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
- .word 0xe590d000 // ldr sp, [r0]
- .word 0xe590e004 // ldr lr, [r0, #4]
- .word 0xe5901010 // ldr r1, [r0, #16]
- .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
- .word 0xe590100c // ldr r1, [r0, #12]
- .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
+ .word 0xe590d000 // ldr sp, [r0]
+ .word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901010 // ldr r1, [r0, #16]
+ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
+ .word 0xe590100c // ldr r1, [r0, #12]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
- .word 0xe12fff1e // bx lr ; return to FEL
+ .word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)
pre-silicon platforms (simulator and emulator):
-------------------------
- | FIT Image |
+ | FIT Image |
| (linux + DTB + RFS) |
------------------------- ----> 0x0120_0000
- | Debug Server FW |
+ | Debug Server FW |
------------------------- ----> 0x00C0_0000
- | AIOP FW |
+ | AIOP FW |
------------------------- ----> 0x0070_0000
- | MC FW |
+ | MC FW |
------------------------- ----> 0x006C_0000
- | MC DPL Blob |
+ | MC DPL Blob |
------------------------- ----> 0x0020_0000
- | BootLoader + Env|
+ | BootLoader + Env|
------------------------- ----> 0x0000_1000
- | PBI |
+ | PBI |
------------------------- ----> 0x0000_0080
- | RCW |
+ | RCW |
------------------------- ----> 0x0000_0000
32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
----------------------------------------- ----> 0x5_8790_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8510_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_84F0_0000 | 64K
| Debug Server FW (2M) | | Alt
----------------------------------------- ----> 0x5_84D0_0000 | Bank
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8490_0000 (vbank4)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8480_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8470_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8430_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8420_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8410_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8400_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8390_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8110_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_80F0_0000 | 64K
| Debug Server FW (2M) | | Bank
----------------------------------------- ----> 0x5_80D0_0000 |
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8090_0000 (vbank0)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8080_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8070_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8030_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8020_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8010_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8000_0000 ---
128-MB NOR flash layout for QDS and RDB boards
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
- * placeholders.
+ * placeholders.
*/
.macro tzasc_prog, xreg
mov x16, #0x10000
mul x14, \xreg, x16
add x14, x14,x12
- mov x1, #0x8
+ mov x1, #0x8
add x1, x1, x14
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
/*
* Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
*
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
/* UART1 */
#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
/* Enhanced SDRAM Controller (ESDRAMC) registers */
struct esdramc_regs {
- u32 ctl0; /* control 0 */
- u32 cfg0; /* configuration 0 */
- u32 ctl1; /* control 1 */
- u32 cfg1; /* configuration 1 */
- u32 misc; /* miscellaneous */
+ u32 ctl0; /* control 0 */
+ u32 cfg0; /* configuration 0 */
+ u32 ctl1; /* control 1 */
+ u32 cfg1; /* configuration 1 */
+ u32 misc; /* miscellaneous */
u32 pad[3];
u32 cdly1; /* Delay Line 1 configuration debug */
u32 cdly2; /* delay line 2 configuration debug */
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
- u32 ctrl; /* control */
- u32 pre; /* prescaler */
- u32 stat; /* status */
- u32 intr; /* interrupt */
- u32 cmp[3]; /* output compare 1-3 */
+ u32 ctrl; /* control */
+ u32 pre; /* prescaler */
+ u32 stat; /* status */
+ u32 intr; /* interrupt */
+ u32 cmp[3]; /* output compare 1-3 */
u32 capt[2]; /* input capture 1-2 */
u32 counter; /* counter */
};
#define GPT_CTRL_TEN 1 /* Timer enable */
/* WDOG enable */
-#define WCR_WDE 0x04
+#define WCR_WDE 0x04
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#else
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
-#define ROM_VERSION_OFFSET 0x48
+#define ROM_VERSION_OFFSET 0x48
#endif
#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
/* GLB_RST_CON */
PMU_GLB_SRST_CTRL_SHIFT = 2,
PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
- PMU_RST_BY_FST_GLB_SRST = 0,
- PMU_RST_BY_SND_GLB_SRST = 1,
+ PMU_RST_BY_FST_GLB_SRST = 0,
+ PMU_RST_BY_SND_GLB_SRST = 1,
PMU_RST_DISABLE = 2,
WDT_GLB_SRST_CTRL_SHIFT = 1,
WDT_GLB_SRST_CTRL_MASK = BIT(1),
- WDT_TRIGGER_SND_GLB_SRST = 0,
- WDT_TRIGGER_FST_GLB_SRST = 1,
- TSADC_GLB_SRST_CTRL_SHIFT = 0,
- TSADC_GLB_SRST_CTRL_MASK = BIT(0),
- TSADC_TRIGGER_SND_GLB_SRST = 0,
- TSADC_TRIGGER_FST_GLB_SRST = 1,
+ WDT_TRIGGER_SND_GLB_SRST = 0,
+ WDT_TRIGGER_FST_GLB_SRST = 1,
+ TSADC_GLB_SRST_CTRL_SHIFT = 0,
+ TSADC_GLB_SRST_CTRL_MASK = BIT(0),
+ TSADC_TRIGGER_SND_GLB_SRST = 0,
+ TSADC_TRIGGER_FST_GLB_SRST = 1,
};
#endif
VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+ VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
- VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
#else
- b \master_label
+ b \master_label
#endif
.endm
#include <linux/mtd/rawnand.h>
#include <asm/arch/hardware.h>
-#define NAND_READ_START 0x00
-#define NAND_READ_END 0x30
-#define NAND_STATUS 0x70
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
#define MASK_CLE 0x10
#define MASK_ALE 0x08
/*************************************************************************
*
* void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
- * CCI_MN_DVM_DOMAIN_CTL_SET);
+ * CCI_MN_DVM_DOMAIN_CTL_SET);
*
* Add fully-coherent masters to DVM domain
*
* This is meant to be used by do_div() from include/asm/div64.h only.
*
* Input parameters:
- * xh-xl = dividend (clobbered)
- * r4 = divisor (preserved)
+ * xh-xl = dividend (clobbered)
+ * r4 = divisor (preserved)
*
* Output values:
- * yh-yl = result
- * xh = remainder
+ * yh-yl = result
+ * xh = remainder
*
* Clobbered regs: xl, ip
*/
#endif
@ The division loop for needed upper bit positions.
- @ Break out early if dividend reaches 0.
+ @ Break out early if dividend reaches 0.
2: cmp xh, yl
orrcs yh, yh, ip
subscs xh, xh, yl
#ifndef __ASSEMBLY__
typedef struct at91_ebi {
- u32 csa; /* 0x00 Chip Select Assignment Register */
+ u32 csa; /* 0x00 Chip Select Assignment Register */
u32 cfgr; /* 0x04 Configuration Register */
u32 reserved[2];
} at91_ebi_t;
#define AT91_EBI_CSA_CS4A 0x0010
typedef struct at91_sdramc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
- u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
- u32 cr; /* 0x08 SDRAMC Configuration Register */
- u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
- u32 lpr; /* 0x10 SDRAMC Low Power Register */
- u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
- u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
- u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
- u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
+ u32 cr; /* 0x08 SDRAMC Configuration Register */
+ u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
+ u32 lpr; /* 0x10 SDRAMC Low Power Register */
+ u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
+ u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
+ u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
+ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
u32 reserved[3];
} at91_sdramc_t;
typedef struct at91_smc {
- u32 csr[8]; /* 0x00 SDRAMC Mode Register */
+ u32 csr[8]; /* 0x00 SDRAMC Mode Register */
} at91_smc_t;
#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
typedef struct at91_bfc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 mr; /* 0x00 SDRAMC Mode Register */
} at91_bfc_t;
typedef struct at91_mc {
#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
#define AT91_ST_WDMR_RSTEN 0x00010000
-#define AT91_ST_WDMR_EXTEN 0x00020000
+#define AT91_ST_WDMR_EXTEN 0x00020000
#endif
struct da8xx_usb_regs {
dv_reg revision;
dv_reg control;
- dv_reg status;
- dv_reg emulation;
- dv_reg mode;
- dv_reg autoreq;
- dv_reg srpfixtime;
- dv_reg teardown;
- dv_reg intsrc;
- dv_reg intsrc_set;
- dv_reg intsrc_clr;
- dv_reg intmsk;
- dv_reg intmsk_set;
- dv_reg intmsk_clr;
- dv_reg intsrcmsk;
- dv_reg eoi;
- dv_reg intvector;
- dv_reg grndis_size[4];
+ dv_reg status;
+ dv_reg emulation;
+ dv_reg mode;
+ dv_reg autoreq;
+ dv_reg srpfixtime;
+ dv_reg teardown;
+ dv_reg intsrc;
+ dv_reg intsrc_set;
+ dv_reg intsrc_clr;
+ dv_reg intmsk;
+ dv_reg intmsk_set;
+ dv_reg intmsk_clr;
+ dv_reg intsrcmsk;
+ dv_reg eoi;
+ dv_reg intvector;
+ dv_reg grndis_size[4];
};
#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
#define CFGCHIP2_OTGMODE (3 << 13)
#define CFGCHIP2_NO_OVERRIDE (0 << 13)
#define CFGCHIP2_FORCE_HOST (1 << 13)
-#define CFGCHIP2_FORCE_DEVICE (2 << 13)
+#define CFGCHIP2_FORCE_DEVICE (2 << 13)
#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
#define CFGCHIP2_PHYPWRDN (1 << 10)
#define CFGCHIP2_OTGPWRDN (1 << 9)
-#define CFGCHIP2_DATPOL (1 << 8)
+#define CFGCHIP2_DATPOL (1 << 8)
#define CFGCHIP2_USB1SUSPENDM (1 << 7)
#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
/* pin table definition */
struct pinmux_resource {
const struct pinmux_config *pins;
- const int n_pins;
+ const int n_pins;
};
#define PINMUX_ITEM(item) { \
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7))
-obj-y += cpu.o
+obj-y += cpu.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
-obj-y += cache.o init.o
+obj-y += cache.o init.o
obj-$(CONFIG_FEC_MXC) += mac.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
ifneq ($(CONFIG_SPL_BUILD),y)
#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
-#define KS2_UART0_BASE 0x02530c00
-#define KS2_UART1_BASE 0x02531000
+#define KS2_UART0_BASE 0x02530c00
+#define KS2_UART1_BASE 0x02531000
/* Boot Config */
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#endif
/* AEMIF */
-#define KS2_AEMIF_CNTRL_BASE 0x21000a00
+#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* Flag from ks2_debug options to check if DSPs need to stay ON */
if (pv->value[opp]) {
/* Handle non-empty members only */
pv->value[opp] = optimize_vcore_voltage(pv, opp);
- px = (struct volts *)vcores;
+ px = (struct volts *)vcores;
j = 0;
while (px < pv) {
/*
.control_std_fuse_die_id_1 = 0x4A002208,
.control_std_fuse_die_id_2 = 0x4A00220C,
.control_std_fuse_die_id_3 = 0x4A002210,
- .control_phy_power_usb = 0x4A002370,
+ .control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
#define TVR_ARM_TIMER_OFFS 0
#define TVR_ARM_TIMER_MASK 0xffffffff
#define TVR_ARM_TIMER_MAX 0xffffffff
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
static inline ulong read_timer(void)
{
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
#define CPU_32_PORT0_16(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
+ PORT_10(fn, pfx, sfx), \
PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
# Copyright (c) 2016 Andreas Färber
obj-y += clk_rk3368.o
obj-y += rk3368.o
-obj-y += syscon_rk3368.o
+obj-y += syscon_rk3368.o
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
*
- * Only SROMC is defined as of now
+ * Only SROMC is defined as of now
*/
#ifndef __ASM_ARCH_SROMC_H_
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
- } else {
+ } else {
/* any other frequency that is a multiple of 24 */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
/* Set work mode register */
mctl_set_cr(para);
* MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
* write levelling disabled, TDQS disabled, output buffer enabled
* MR2: manual full array self refresh, dynamic ODT off,
- * CAS write latency (CWL): 8
+ * CAS write latency (CWL): 8
*/
static u32 mr_ddr3[7] = {
0x00001c70, 0x00000040, 0x00000018, 0x00000000,
_vectors:
#if defined(CONFIG_CF_SBF)
INITSP: .long 0 /* Initial SP */
-INITPC: .long ASM_DRAMINIT /* Initial PC */
+INITPC: .long ASM_DRAMINIT /* Initial PC */
#else
INITSP: .long 0 /* Initial SP */
-INITPC: .long _START /* Initial PC */
+INITPC: .long _START /* Initial PC */
#endif
vector02_0F:
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
+ * int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
INITSP: .long 0 /* Initial SP */
#ifdef CONFIG_CF_SBF
-INITPC: .long ASM_DRAMINIT /* Initial PC */
+INITPC: .long ASM_DRAMINIT /* Initial PC */
#endif
#ifdef CONFIG_SYS_NAND_BOOT
-INITPC: .long ASM_DRAMINIT_N /* Initial PC */
+INITPC: .long ASM_DRAMINIT_N /* Initial PC */
#endif
#else
INITSP: .long 0 /* Initial SP */
-INITPC: .long _START /* Initial PC */
+INITPC: .long _START /* Initial PC */
#endif
#define MCF_GPIO_PAR_TIMER 0x10004C
#define MCF_DSCR_EIM 0x100050
-#define MCF_DCSR_FEC12C 0x100052
+#define MCF_DCSR_FEC12C 0x100052
#define MCF_DCSR_UART 0x100053
#define MCF_DCSR_QSPI 0x100054
#define MCF_DCSR_TIMER 0x100055
umul_ppmm (__w.s.high, __w.s.low, u, v); \
__w.ll; })
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef int word_type __attribute__ ((mode (__word__)));
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac0 \n" \
- " .set pop \n" \
- : "=r" (mflo0)); \
+ " .set pop \n" \
+ : "=r" (mflo0)); \
mflo0; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac1 \n" \
- " .set pop \n" \
- : "=r" (mflo1)); \
+ " .set pop \n" \
+ : "=r" (mflo1)); \
mflo1; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac2 \n" \
- " .set pop \n" \
- : "=r" (mflo2)); \
+ " .set pop \n" \
+ : "=r" (mflo2)); \
mflo2; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac3 \n" \
- " .set pop \n" \
- : "=r" (mflo3)); \
+ " .set pop \n" \
+ : "=r" (mflo3)); \
mflo3; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac0 \n" \
- " .set pop \n" \
- : "=r" (mfhi0)); \
+ " .set pop \n" \
+ : "=r" (mfhi0)); \
mfhi0; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac1 \n" \
- " .set pop \n" \
- : "=r" (mfhi1)); \
+ " .set pop \n" \
+ : "=r" (mfhi1)); \
mfhi1; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac2 \n" \
- " .set pop \n" \
- : "=r" (mfhi2)); \
+ " .set pop \n" \
+ : "=r" (mfhi2)); \
mfhi2; \
})
" .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac3 \n" \
- " .set pop \n" \
- : "=r" (mfhi3)); \
+ " .set pop \n" \
+ : "=r" (mfhi3)); \
mfhi3; \
})
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
-#define BOARD_ID_FAMILY_MASK 0xfff000
-#define BOARD_ID_FAMILY_V5 0x556000
-#define BOARD_ID_FAMILY_K7 0x74b000
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
-#define BOARD_ID_FAMILY_MASK 0xfff000
-#define BOARD_ID_FAMILY_V5 0x556000
-#define BOARD_ID_FAMILY_K7 0x74b000
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
#define WD_ENABLE 0x1
! Turn off the watchdog, according to Faraday FTWDT010 spec
- li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
lwi $p1, [$p0] ! Get the config of WD
andi $p1, $p1, 0x1f ! Wipe out useless bits
li $r0, ~WD_ENABLE
*/
#define ENA_DCAC 2UL
#define DIS_DCAC ~ENA_DCAC
-#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
+#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 1 ! Determine interruption type
- bal do_interruption
+ bal do_interruption
.align 5
tlb_not_present:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 2 ! Determine interruption type
- bal do_interruption
+ bal do_interruption
.align 5
tlb_misc:
SAVE_ALL
move $r0, $sp ! To get the kernel stack
li $r1, 3 ! Determine interruption type
- bal do_interruption
+ bal do_interruption
.align 5
tlb_vlpt_miss:
_start_e500:
/* Enable debug exception */
li r1,MSR_DE
- mtmsr r1
+ mtmsr r1
/*
* If we got an ePAPR device tree pointer passed in as r3, we need that
li r0,0
-1: subi r4,r4,4
- stw r0,0(r4)
- cmplw r4,r3
+1: subi r4,r4,4
+ stw r0,0(r4)
+ cmplw r4,r3
bne 1b
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
-#define LBCR_BMTPS 0x0000000F
-#define LBCR_BMTPS_SHIFT 0
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT 0
/* LCRR - Clock Ratio Register
*/
*/
typedef struct cpc_corenet {
- u32 cpccsr0; /* Config/status reg */
+ u32 cpccsr0; /* Config/status reg */
u32 res1;
u32 cpccfg0; /* Configuration register */
u32 res2;
#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
-#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
#define MAS5 SPRN_MAS5
#define MAS6 SPRN_MAS6
#define MAS7 SPRN_MAS7
-#define MAS8 SPRN_MAS8
+#define MAS8 SPRN_MAS8
#if defined(CONFIG_MPC85xx)
#define DAR_DEAR DEAR
*
* @param dev device to use
* @param offset GPIO offset within bank
- * @param output 0 to set as input, 1 to set as output
+ * @param output 0 to set as input, 1 to set as output
* @return -1 on error, 0 if ok
*/
int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,
* MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing
*/
- movl $0x80000008, %eax /* Address sizes leaf */
+ movl $0x80000008, %eax /* Address sizes leaf */
cpuid
sub $32, %al
movzx %al, %eax
.globl __idt_handler
__idt_handler:
pushal
- movb $0, %al /* This instruction gets modified */
- ljmp $0, $__interrupt_handler_16bit
+ movb $0, %al /* This instruction gets modified */
+ ljmp $0, $__interrupt_handler_16bit
.globl __idt_handler_size
__idt_handler_size:
.long . - __idt_handler
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
/*----------------------------------------------------------------------
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += cache.o misc.o relocate.o time.o
+obj-y += cache.o misc.o relocate.o time.o
MPP43_GPIO,
MPP44_GPIO,
MPP45_GPIO,
- MPP46_GPIO, /* M_RLED */
+ MPP46_GPIO, /* M_RLED */
MPP47_GPIO, /* M_GLED */
MPP48_GPIO, /* B_RLED */
MPP49_GPIO, /* B_GLED */
nitrogen6q i.MX6Q/6D 1GB
nitrogen6dl i.MX6DL 1GB
nitrogen6s i.MX6S 512MB
- nitrogen6q2g i.MX6Q/6D 2GB
+ nitrogen6q2g i.MX6Q/6D 2GB
nitrogen6dl2g i.MX6DL 2GB
nitrogen6s1g i.MX6S 1GB
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4020_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4020_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4020_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
-U-boot | 1MB | 0x4010_0000
-U-boot Env | 1MB | 0x4030_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4030_0000
PPA FIT image | 2MB | 0x4040_0000
PFE firmware | 20K | 0x00a0_0000
Linux ITB | ~53MB | 0x4100_0000
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
QSPI flash map:
Start Address End Address Description Size
0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
-0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
+0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
CONFIG_SYS_MBAR -- define MBAR offset
-CONFIG_MONITOR_IS_IN_RAM -- Not support
+CONFIG_MONITOR_IS_IN_RAM -- Not support
CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
/*SYS_nRESWARM */\
- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
/* - PEN_IRQ */\
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
*/
-.equ PPMCR0, 0xfc04002d
+.equ PPMCR0, 0xfc04002d
.equ MSCR_SDRAMC, 0xec094060
.equ MISCCR2, 0xec09001a
.equ DDR_RCR, 0xfc0b8180
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
{0x0884, 0, 0}, /* CFG_UART2_RTSN_OUT */
{0x0888, 683, 0}, /* CFG_UART2_RXD_IN */
{0x088C, 0, 0}, /* CFG_UART2_RXD_OEN */
- {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */
+ {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */
{0x0894, 835, 0}, /* CFG_UART2_TXD_IN */
{0x0898, 0, 0}, /* CFG_UART2_TXD_OEN */
{0x089C, 0, 0}, /* CFG_UART2_TXD_OUT */
{0x0C48, 0, 404}, /* CFG_VOUT1_D22_IN */
{0x0C78, 0, 0}, /* CFG_VOUT1_D4_IN */
{0x0C84, 0, 365}, /* CFG_VOUT1_D5_IN */
- {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */
+ {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */
{0x0C9C, 0, 218}, /* CFG_VOUT1_D7_IN */
};
*
* based on: cmd_jffs2.c
*
- * Add support for a CRAMFS located in RAM
+ * Add support for a CRAMFS located in RAM
*/
static unsigned int cs;
static unsigned int mode;
static unsigned int freq;
-static int bitlen;
-static uchar dout[MAX_SPI_BYTES];
-static uchar din[MAX_SPI_BYTES];
+static int bitlen;
+static uchar dout[MAX_SPI_BYTES];
+static uchar din[MAX_SPI_BYTES];
static int do_spi_xfer(int bus, int cs)
{
#endif
#ifdef CONFIG_SHA1
{
- .name = "sha1",
+ .name = "sha1",
.digest_size = SHA1_SUM_LEN,
.chunk_size = CHUNKSZ_SHA1,
#ifdef CONFIG_SHA_HW_ACCEL
*
* This call is similar to hwconfig_f(), except that it takes additional
* argument @subopt. In this example:
- * "dr_usb:mode=peripheral"
+ * "dr_usb:mode=peripheral"
* "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its
* argument.
*/
int action; /* what to do */
int ip_wanted; /* needed */
int *irq_handle; /* for USB int requests */
- unsigned int irqpipe; /* pipe for release_irq */
+ unsigned int irqpipe; /* pipe for release_irq */
unsigned char irqmaxp; /* max packed for irq Pipe */
unsigned char irqinterval; /* Intervall for IRQ Pipe */
struct scsi_cmd *srb; /* current srb */
#ccflags-y += -DET_DEBUG -DDEBUG
-obj-$(CONFIG_PARTITIONS) += part.o
+obj-$(CONFIG_PARTITIONS) += part.o
obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o
obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o
obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o
on OMAP3:
nandecc hw
-nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
-spl export atags /* export ATAGS */
+nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
+spl export atags /* export ATAGS */
nand erase 0x680000 0x20000 /* erase - one page */
nand write 0x80000100 0x680000 0x20000 /* write the image - one page */
call with FDT:
nandecc hw
-nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
+nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
tftpboot 0x80000100 devkit8000.dtb /* Read fdt */
spl export fdt 0x82000000 - 0x80000100 /* export FDT */
nand erase 0x680000 0x20000 /* erase - one page */
CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved.
-CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
+CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
CONFIG_SPL_OS_BOOT Activate Falcon Mode.
A board may chose to look at the environment for decisions about falcon
mode. In this case the following variables may be supported:
-boot_os : Set to yes/Yes/true/True/1 to enable booting to OS,
+boot_os : Set to yes/Yes/true/True/1 to enable booting to OS,
any other value to fall back to U-Boot (including
unset)
falcon_args_file : Filename to load as the 'args' portion of falcon mode
Partition Map for USB device 0 -- Partition Type: DOS
Part Start Sector Num Sectors UUID Type
- 1 3072 263168 000c4046-01 06
- 2 266240 13457408 000c4046-02 83
+ 1 3072 263168 000c4046-01 06
+ 2 266240 13457408 000c4046-02 83
Odroid # ls usb 0:2 /boot
<DIR> 4096 .
Required properties:
--------------------
- compatible: Shall be: "ti,am654-secure-proxy"
-- reg-names data - Map the data region
+- reg-names data - Map the data region
scfg - Map the secure configuration region
rt - Map the Realtime region.
- reg: Contains the register map per reg-names.
--------------------
- compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200
"ti,am64-ddrss" for am642
-- reg-names cfg - Map the controller configuration region
+- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
- reg: Contains the register map per reg-names.
- power-domains: Should contain two entries:
Required properties:
--------------------
- compatible: Shall be: "ti,am654-ddrss"
-- reg-names ss - Map the sub system wrapper logic region
+- reg-names ss - Map the sub system wrapper logic region
ctl - Map the controller region
phy - Map the PHY region
- reg: Contains the register map per reg-names.
tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
compatible = "altr,tse-msgdma-1.0";
- reg = <0x00000001 0x00001000 0x00000400>,
+ reg = <0x00000001 0x00001000 0x00000400>,
<0x00000001 0x00001460 0x00000020>,
<0x00000001 0x00001480 0x00000020>,
<0x00000001 0x000014A0 0x00000008>,
fec0: ethernet@9000 {
compatible = "fsl,mcf-dma-fec";
- reg = <0x9000 0x800>;
+ reg = <0x9000 0x800>;
mii-base = <0>;
phy-addr = <0>;
timeout-loop = <5000>;
fec0: ethernet@fc030000 {
compatible = "fsl,mcf-fec";
- reg = <0xfc030000 0x400>;
+ reg = <0xfc030000 0x400>;
mii-base = <0>;
phy-addr = <0>;
timeout-loop = <5000>;
Required properties for the pinctrl driver:
- compatible: "brcm,bcm6838-pinctrl"
-- regmap: specify the gpio test port syscon
+- regmap: specify the gpio test port syscon
- brcm,pins-count: the number of pin
- brcm,functions-count: the number of function
----------------------------------------------------------------------
MPP# 0x1 0x2 0x3 0x4
----------------------------------------------------------------------
-0 SDIO_CLK - SPI0_CLK -
+0 SDIO_CLK - SPI0_CLK -
1 SDIO_CMD - SPI0_MISO -
-2 SDIO_D[0] - SPI0_MOSI -
-3 SDIO_D[1] - SPI0_CS0n -
+2 SDIO_D[0] - SPI0_MOSI -
+3 SDIO_D[1] - SPI0_CS0n -
4 SDIO_D[2] - I2C0_SDA SPI0_CS1n
5 SDIO_D[3] - I2C0_SCK -
6 SDIO_DS - - -
7 SDIO_D[4] - UART1_RXD -
-8 SDIO_D[5] - UART1_TXD -
-9 SDIO_D[6] - SPI0_CS1n -
+8 SDIO_D[5] - UART1_TXD -
+9 SDIO_D[6] - SPI0_CS1n -
10 SDIO_D[7] - - -
-11 - - UART0_TXD -
-12 SDIO_CARD_PW_OFF SDIO_HW_RST - -
+11 - - UART0_TXD -
+12 SDIO_CARD_PW_OFF SDIO_HW_RST - -
13 - - - -
14 - - - -
15 - - - -
"marvell,armada-8k-cpm-pinctrl",
"marvell,armada-8k-cps-pinctrl"
- bank-name: A string defining the pinc controller bank name
-- reg: A pair of values defining the pin controller base address
+- reg: A pair of values defining the pin controller base address
and the address space
- pin-count: Numeric value defining the amount of multi purpose pins
included in this bank
- anatop-reg-offset: u32 value representing the anatop MFD register offset.
- anatop-vol-bit-shift: u32 value representing the bit shift for the register.
- anatop-vol-bit-width: u32 value representing the number of bits used in the
- register.
+ register.
- anatop-min-bit-val: u32 value representing the minimum value of this
- register.
+ register.
- anatop-min-voltage: u32 value representing the minimum voltage of this
- regulator.
+ regulator.
- anatop-max-voltage: u32 value representing the maximum voltage of this
- regulator.
+ regulator.
Optional properties:
- anatop-delay-reg-offset: u32 value representing the anatop MFD step time
- register offset.
+ register offset.
- anatop-delay-bit-shift: u32 value representing the bit shift for the step
- time register.
+ time register.
- anatop-delay-bit-width: u32 value representing the number of bits used in
- the step time register.
+ the step time register.
- anatop-enable-bit: u32 value representing regulator enable bit offset.
- vin-supply: input supply phandle.
The SPI master node requires the following properties:
- #address-cells - number of cells required to define a chip select
- address on the SPI bus.
+ address on the SPI bus.
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
- recommended practice.
+ recommended practice.
- cs-gpios - (optional) gpios chip select.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
contain the following properties.
- reg - (required) chip select address of device.
- compatible - (required) name of SPI device following generic names
- recommended practice
+ recommended practice
- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
- spi-cpol - (optional) Empty property indicating device requires
- inverse clock polarity (CPOL) mode
+ inverse clock polarity (CPOL) mode
- spi-cpha - (optional) Empty property indicating device requires
- shifted clock phase (CPHA) mode
+ shifted clock phase (CPHA) mode
- spi-cs-high - (optional) Empty property indicating device requires
- chip select active high
+ chip select active high
- spi-3wire - (optional) Empty property indicating device requires
- 3-wire mode.
+ 3-wire mode.
- spi-tx-bus-width - (optional) The bus width(number of data wires) that
used for MOSI. Defaults to 1 if not present.
- spi-rx-bus-width - (optional) The bus width(number of data wires) that
- reg : Physical base address and size of SPI registers map.
- clock : Clock phandle (see clock bindings for details).
- #address-cells : Number of cells required to define a chip select
- address on the SPI bus. Should be set to 1.
+ address on the SPI bus. Should be set to 1.
- #size-cells : Should be zero.
- pinctrl-names : Must be "default"
- pinctrl-n : At least one pinctrl phandle
Example:
tpm {
- compatible = "sandbox,tpm2";
+ compatible = "sandbox,tpm2";
};
struct l2cache *regs;
u32 iprefetch;
u32 dprefetch;
- u32 tram_ctl[2];
- u32 dram_ctl[2];
+ u32 tram_ctl[2];
+ u32 dram_ctl[2];
};
static int v5l2_enable(struct udevice *dev)
static const struct cache_ops sandbox_cache_ops = {
.get_info = sandbox_get_info,
- .enable = sandbox_enable,
+ .enable = sandbox_enable,
.disable = snadbox_disable,
};
}
static const struct clk_ops clk_pllv3_sys_ops = {
- .enable = clk_pllv3_generic_enable,
+ .enable = clk_pllv3_generic_enable,
.disable = clk_pllv3_generic_disable,
.get_rate = clk_pllv3_sys_get_rate,
.set_rate = clk_pllv3_sys_set_rate,
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2013 Samsung Electronics Co., Ltd.
-# http://www.samsung.com
+# http://www.samsung.com
obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
obj-y += rsa_mod_exp/
* 0110 16Gb 2GB
*
* SPD byte8 - module memory bus width
- * bit[2:0] primary bus width
+ * bit[2:0] primary bus width
* 000 8bits
- * 001 16bits
- * 010 32bits
- * 011 64bits
+ * 001 16bits
+ * 010 32bits
+ * 011 64bits
*
* SPD byte7 - module organiztion
- * bit[2:0] sdram device width
- * 000 4bits
- * 001 8bits
- * 010 16bits
- * 011 32bits
+ * bit[2:0] sdram device width
+ * 000 4bits
+ * 001 8bits
+ * 010 16bits
+ * 011 32bits
*
*/
static unsigned long long
#define SPD_COL_NUM_MASK (7 << SPD_COL_NUM_OFF)
#define SPD_MODULE_ORG_BYTE 7
-#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
+#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
#define SPD_MODULE_SDRAM_DEV_WIDTH_MASK (7 << SPD_MODULE_SDRAM_DEV_WIDTH_OFF)
#define SPD_MODULE_BANK_NUM_MIN 1
#define SPD_MODULE_BANK_NUM_OFF 3
obj-y += scmi_agent-uclass.o
obj-y += smt.o
-obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o
+obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o
obj-$(CONFIG_DM_MAILBOX) += mailbox_agent.o
obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o
#define IC_TX_EMPTY 0x0010
#define IC_TX_OVER 0x0008
#define IC_RX_FULL 0x0004
-#define IC_RX_OVER 0x0002
+#define IC_RX_OVER 0x0002
#define IC_RX_UNDER 0x0001
/* fifo threshold register definitions */
* I2C Driver for Atmel ATSHA204 over I2C
*
* Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
- * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
*
* int i, j;
* for (i = 0; i < 256; ++i) {
- * u8 c = 0;
- * for (j = 0; j < 8; ++j) {
- * c = (c << 1) | ((i >> j) & 1);
- * }
- * bitreverse_table[i] = c;
+ * u8 c = 0;
+ * for (j = 0; j < 8; ++j) {
+ * c = (c << 1) | ((i >> j) & 1);
+ * }
+ * bitreverse_table[i] = c;
* }
*/
*
* int i, j;
* for (i = 0; i < 256; ++i) {
- * u16 c = i << 8;
- * for (j = 0; j < 8; ++j) {
- * int b = c >> 15;
- * c <<= 1;
- * if (b)
- * c ^= 0x8005;
- * }
- * crc16_table[i] = c;
+ * u16 c = i << 8;
+ * for (j = 0; j < 8; ++j) {
+ * int b = c >> 15;
+ * c <<= 1;
+ * if (b)
+ * c ^= 0x8005;
+ * }
+ * crc16_table[i] = c;
* }
*/
static u16 const crc16_table[256] = {
int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan)
{
- if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
+ if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
sizeof(scan->data)) != sizeof(scan->data))
return -1;
obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
-obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
mmc_go_idle(mmc);
start = get_timer(0);
- /* Asking to the card its capabilities */
+ /* Asking to the card its capabilities */
for (i = 0; ; i++) {
err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
* device name
* @name: MTD device name to open
*
- * This function returns MTD device description structure in case of
- * success and an error code in case of failure.
+ * This function returns MTD device description structure in case of
+ * success and an error code in case of failure.
*/
struct mtd_info *get_mtd_device_nm(const char *name)
{
#define NAND_TIMEOUT 10240
#define NAND_ECC_BUSY 0xC
#define NAND_4BITECC_MASK 0x03FF03FF
-#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
+#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
#define ECC_STATE_NO_ERR 0x0
#define ECC_STATE_TOO_MANY_ERRS 0x1
#define ECC_STATE_ERR_CORR_COMP_P 0x2
nand->bbt_td = &bbt_main_descr;
nand->bbt_md = &bbt_mirror_descr;
- /* set up nand options */
+ /* set up nand options */
nand->options = NAND_NO_SUBPAGE_WRITE;
nand->bbt_options = NAND_BBT_USE_FLASH;
static void ioread16_rep(void *addr, void *buf, int len)
{
int i;
- u16 *p = (u16 *) buf;
+ u16 *p = (u16 *) buf;
for (i = 0; i < len; i++)
p[i] = readw(addr);
if (ret)
return ret;
- u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
- u32 time_start;
+ u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
+ u32 time_start;
- time_start = get_timer(0);
- while (get_timer(time_start) < timer) {
+ time_start = get_timer(0);
+ while (get_timer(time_start) < timer) {
if (chip->dev_ready) {
if (chip->dev_ready(mtd))
break;
LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
- LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
+ LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
#endif
/**
* flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
- * boundary[], diesize[], mtd->size, mtd->erasesize,
- * mtd->eraseregions
+ * boundary[], diesize[], mtd->size, mtd->erasesize,
+ * mtd->eraseregions
* @param mtd - MTD device structure
*/
static void flexonenand_get_size(struct mtd_info *mtd)
{ INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
- { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
+ { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
/* EON -- en25xxx */
*
* A big-endian CRC written this way would be coded like:
* for (i = 0; i < input_bits; i++) {
- * multiple = remainder & 0x80000000 ? CRCPOLY : 0;
- * remainder = (remainder << 1 | next_input_bit()) ^ multiple;
+ * multiple = remainder & 0x80000000 ? CRCPOLY : 0;
+ * remainder = (remainder << 1 | next_input_bit()) ^ multiple;
* }
* Notice how, to get at bit 32 of the shifted remainder, we look
* at bit 31 of the remainder *before* shifting it.
* This changes the code to:
* for (i = 0; i < input_bits; i++) {
* remainder ^= next_input_bit() << 31;
- * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
- * remainder = (remainder << 1) ^ multiple;
+ * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
+ * remainder = (remainder << 1) ^ multiple;
* }
* With this optimization, the little-endian code is simpler:
* for (i = 0; i < input_bits; i++) {
* remainder ^= next_input_bit();
- * multiple = (remainder & 1) ? CRCPOLY : 0;
- * remainder = (remainder >> 1) ^ multiple;
+ * multiple = (remainder & 1) ? CRCPOLY : 0;
+ * remainder = (remainder >> 1) ^ multiple;
* }
*
* Note that the other details of endianness have been hidden in CRCPOLY
* order, we can actually do the merging 8 or more bits at a time rather
* than one bit at a time:
* for (i = 0; i < input_bytes; i++) {
- * remainder ^= next_input_byte() << 24;
- * for (j = 0; j < 8; j++) {
- * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
- * remainder = (remainder << 1) ^ multiple;
- * }
+ * remainder ^= next_input_byte() << 24;
+ * for (j = 0; j < 8; j++) {
+ * multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
+ * remainder = (remainder << 1) ^ multiple;
+ * }
* }
* Or in little-endian:
* for (i = 0; i < input_bytes; i++) {
- * remainder ^= next_input_byte();
- * for (j = 0; j < 8; j++) {
- * multiple = (remainder & 1) ? CRCPOLY : 0;
- * remainder = (remainder << 1) ^ multiple;
- * }
+ * remainder ^= next_input_byte();
+ * for (j = 0; j < 8; j++) {
+ * multiple = (remainder & 1) ? CRCPOLY : 0;
+ * remainder = (remainder << 1) ^ multiple;
+ * }
* }
* If the input is a multiple of 32 bits, you can even XOR in a 32-bit
* word at a time and increase the inner loop count to 32.
.start = xgmac_eth_start,
.send = xgmac_tx,
.recv = xgmac_rx,
- .free_pkt = xgmac_free_pkt,
+ .free_pkt = xgmac_free_pkt,
.stop = xgmac_eth_stop,
.write_hwaddr = xgmac_eth_write_hwaddr,
.read_rom_hwaddr = xgmac_eth_read_rom_hwaddr,
--------------------------------------
12/15/2003 Initial port to u-boot by
- Sascha Hauer <saschahauer@web.de>
+ Sascha Hauer <saschahauer@web.de>
06/03/2008 Remy Bohmer <linux@bohmer.net>
- Fixed the driver to work with DM9000A.
#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
#define DM9000_DMP_PACKET(func,packet,length) \
do { \
- int i; \
+ int i; \
printf("%s: length: %d\n", func, length); \
for (i = 0; i < length; i++) { \
if (i % 8 == 0) \
#define E1000_ERR_MASTER_REQUESTS_PENDING 10
#define E1000_ERR_HOST_INTERFACE_COMMAND 11
#define E1000_BLK_PHY_RESET 12
-#define E1000_ERR_SWFW_SYNC 13
+#define E1000_ERR_SWFW_SYNC 13
/* PCI Device IDs */
#define E1000_DEV_ID_82542 0x1000
/* Below are the register offsets and bit definitions
* of the Lan911x memory space
*/
-#define RX_DATA_FIFO 0x00
+#define RX_DATA_FIFO 0x00
-#define TX_DATA_FIFO 0x20
+#define TX_DATA_FIFO 0x20
#define TX_CMD_A_INT_ON_COMP 0x80000000
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
}
#define cache_clean_descriptor(desc) \
- flush_dcache_range((uintptr_t)(desc), \
+ flush_dcache_range((uintptr_t)(desc), \
(uintptr_t)(desc) + sizeof(struct emac_dma_desc))
#define cache_inv_descriptor(desc) \
setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
#endif
- return busno;
+ return busno;
}
#else
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
- /* name first last reg offset */
+ /* name first last reg offset */
BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0),
BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0),
BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0),
};
static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
- /* name first last reg offset */
+ /* name first last reg offset */
BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 0x6, 0),
BANK_PMX("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 0xb, 0),
BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0x0, 0),
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR1_0 F_(IRQ0, IP2_27_24)
/* GPSR2 */
-#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
+#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
#define GPSR2_26 F_(SDA3, IP10_7_4)
#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/*
* tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
- * interface.
+ * interface.
* @return: 0 on success, not 0 on failure
*/
int tps65910_set_i2c_control(void)
.set_invert = meson_pwm_set_invert,
};
-#define XTAL -1
+#define XTAL -1
/* Local clock ids aliases to avoid define conflicts */
#define GXBB_CLKID_HDMI_PLL 2
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
-#define DDRSS_V2A_R1_MAT_REG 0x0020
-#define DDRSS_ECC_CTRL_REG 0x0120
+#define DDRSS_V2A_R1_MAT_REG 0x0020
+#define DDRSS_ECC_CTRL_REG 0x0120
struct k3_ddrss_desc {
struct udevice *dev;
unsigned int freq;
ulong clock;
unsigned int mode;
- u8 num_cs;
+ u8 num_cs;
unsigned int mtiming;
size_t cmd_len;
u8 cmd_buf[16];
DECLARE_GLOBAL_DATA_PTR;
#define SITES_MAX 16
-#define FLAGS_VER2 0x1
-#define FLAGS_VER3 0x2
+#define FLAGS_VER2 0x1
+#define FLAGS_VER3 0x2
#define TMR_DISABLE 0x0
#define TMR_ME 0x80000000
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Microchip Corporation
- * Wenyou.Yang <wenyou.yang@microchip.com>
+ * Wenyou.Yang <wenyou.yang@microchip.com>
*/
#include <common.h>
* @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
* there's now way for software to detect this in runtime.
* @is_utmi_l1_suspend: the core asserts output signal
- * 0 - utmi_sleep_n
- * 1 - utmi_l1_suspend_n
+ * 0 - utmi_sleep_n
+ * 1 - utmi_l1_suspend_n
* @is_selfpowered: true when we are selfpowered
* @is_fpga: true when we are using the FPGA board
* @needs_fifo_resize: not all users might want fifo resizing, flag it
* @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
- * 0 - -6dB de-emphasis
- * 1 - -3.5dB de-emphasis
- * 2 - No de-emphasis
- * 3 - Reserved
+ * 0 - -6dB de-emphasis
+ * 1 - -3.5dB de-emphasis
+ * 2 - No de-emphasis
+ * 3 - Reserved
* @index: index of _this_ controller
* @list: to maintain the list of dwc3 controllers
*/
* BESL value in the LPM token is less than or equal to LPM
* NYET threshold.
*/
- if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
+ if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
-#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
+#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */
#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
* so using '|=' isn't safe as it may ack an interrupt.
*/
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
-#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE)
+#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE)
static inline void udc_set_mask_UDCCR(int mask)
{
*
* To generate the content of the array below, use ie. the following command:
* $ hexdump -v -e '/4 "0x%08x, "' r8a779x_usb3_v3.dlmem | \
- * sed "s@\(.\{47\}\) @\1\n@g"
+ * sed "s@\(.\{47\}\) @\1\n@g"
*
* [1] git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
*/
&& (musb_ep->dma->actual_len
== musb_ep->packet_sz)) {
/* In double buffer case, continue to unload fifo if
- * there is Rx packet in FIFO.
- **/
+ * there is Rx packet in FIFO.
+ **/
csr = musb_readw(epio, MUSB_RXCSR);
if ((csr & MUSB_RXCSR_RXPKTRDY) &&
hw_ep->rx_double_buffered)
/* TxType/RxType */
#define MUSB_TYPE_SPEED 0xc0
#define MUSB_TYPE_SPEED_SHIFT 6
-#define MUSB_TYPE_SPEED_HIGH 1
-#define MUSB_TYPE_SPEED_FULL 2
+#define MUSB_TYPE_SPEED_HIGH 1
+#define MUSB_TYPE_SPEED_FULL 2
#define MUSB_TYPE_SPEED_LOW 3
#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
#define MUSB_TYPE_PROTO_SHIFT 4
#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
-#define MUSB_TYPE_PROTO_BULK 2
-#define MUSB_TYPE_PROTO_INTR 3
+#define MUSB_TYPE_PROTO_BULK 2
+#define MUSB_TYPE_PROTO_INTR 3
/* CONFIGDATA */
#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
* values are not supported
*/
struct musb_epinfo {
- u8 epnum; /* endpoint number */
+ u8 epnum; /* endpoint number */
u8 epdir; /* endpoint direction */
u16 epsize; /* endpoint FIFO size */
};
#include "musb_hcd.h"
/* MSC control transfers */
-#define USB_MSC_BBB_RESET 0xFF
+#define USB_MSC_BBB_RESET 0xFF
#define USB_MSC_BBB_GET_MAX_LUN 0xFE
/* Endpoint configuration information */
#ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED
#define VCXK_BWS(x, data) vcxk_bws[x] = data;
- #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask;
- #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask;
+ #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask;
+ #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask;
#define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data;
#else
u_char double_bws[16384];
#endif
#define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2]
-#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2]
+#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2]
#define VC2K_Bright vcxk_bws[0x8000]
#define VC8K_BrightH vcxk_bws[0xC000]
#define VC8K_BrightL vcxk_bws[0xC001]
* set the display brightness
* PARAMETER
* side 1 set front side brightness
- * 2 set back side brightness
+ * 2 set back side brightness
* 3 set brightness for both sides
* brightness 0..1000
***
VC4K16_Bright1 = brightness + 23;
if ((side == 0) || (side & 0x2))
VC4K16_Bright2 = brightness + 23;
- } else {
+ } else {
VC2K_Bright = (brightness >> 4) + 2;
VC8K_BrightH = (brightness + 23) >> 8;
VC8K_BrightL = (brightness + 23) & 0xFF;
* Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
* setenv videomode
* video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
- * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
+ * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
* Watchdog driver for Orion/Kirkwood processors
*
* Authors: Tomas Hlavacek <tmshlvck@gmail.com>
- * Sylver Bruneau <sylver.bruneau@googlemail.com>
- * Marek Behun <marek.behun@nic.cz>
+ * Sylver Bruneau <sylver.bruneau@googlemail.com>
+ * Marek Behun <marek.behun@nic.cz>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
struct btrfs_key key;
static const char* dir_item_str[] = {
[BTRFS_FT_REG_FILE] = " ",
- [BTRFS_FT_DIR] = "DIR",
+ [BTRFS_FT_DIR] = "DIR",
[BTRFS_FT_CHRDEV] = "CHR",
[BTRFS_FT_BLKDEV] = "BLK",
[BTRFS_FT_FIFO] = "FIF",
__u32 inode; /* inode number */
__u32 version; /* inode version */
__u32 offset; /* offset on jeb */
- __u32 totlen; /* record length */
+ __u32 totlen; /* record length */
} __attribute__((packed));
struct jffs2_sum_dirent_flash
__u32 offset; /* offset on jeb */
__u32 pino; /* parent inode */
__u32 version; /* dirent version */
- __u32 ino; /* == zero for unlink */
+ __u32 ino; /* == zero for unlink */
uint8_t nsize; /* dirent name size */
uint8_t type; /* dirent type */
uint8_t name[0]; /* dirent name */
__u32 inode; /* inode number */
__u32 version; /* inode version */
__u32 offset; /* offset on jeb */
- __u32 totlen; /* record length */
+ __u32 totlen; /* record length */
} __attribute__((packed));
struct jffs2_sum_dirent_mem
__u32 offset; /* ofset on jeb */
__u32 pino; /* parent inode */
__u32 version; /* dirent version */
- __u32 ino; /* == zero for unlink */
+ __u32 ino; /* == zero for unlink */
uint8_t nsize; /* dirent name size */
uint8_t type; /* dirent type */
uint8_t name[0]; /* dirent name */
struct jffs2_sum_marker
{
__u32 offset; /* offset of the summary node in the jeb */
- __u32 magic; /* == JFFS2_SUM_MAGIC */
+ __u32 magic; /* == JFFS2_SUM_MAGIC */
};
#define JFFS2_SUMMARY_FRAME_SIZE (sizeof(struct jffs2_raw_summary) + sizeof(struct jffs2_sum_marker))
};
struct super_operations {
- struct inode *(*alloc_inode)(struct super_block *sb);
+ struct inode *(*alloc_inode)(struct super_block *sb);
void (*destroy_inode)(struct inode *);
- void (*dirty_inode) (struct inode *, int flags);
+ void (*dirty_inode) (struct inode *, int flags);
int (*write_inode) (struct inode *, struct writeback_control *wbc);
int (*drop_inode) (struct inode *);
void (*evict_inode) (struct inode *);
char s_id[32]; /* Informational name */
u8 s_uuid[16]; /* UUID */
- void *s_fs_info; /* Filesystem private info */
+ void *s_fs_info; /* Filesystem private info */
unsigned int s_max_links;
#ifndef __UBOOT__
fmode_t s_mode;
#define f_dentry f_path.dentry
#define f_vfsmnt f_path.mnt
const struct file_operations *f_op;
- unsigned int f_flags;
+ unsigned int f_flags;
loff_t f_pos;
unsigned int f_uid, f_gid;
#if BITS_PER_LONG==32
#define MAX_LFS_FILESIZE (((u64)PAGE_CACHE_SIZE << (BITS_PER_LONG-1))-1)
#elif BITS_PER_LONG==64
-#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL
+#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL
#endif
/*
* I2C Driver for Atmel ATSHA204 over I2C
*
* Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
- * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
(AT91_PMC_PLLAR_29 | \
AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
AT91_PMC_PLLXR_PLLCOUNT(63) | \
- AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
+ AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
+ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
#define PIXIS_LBMAP_ALTBANK 0x40
#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
/*
* Use:
- * boot-mode=mix
- * boot-mode=sd
- * boot-mode=net
+ * boot-mode=mix
+ * boot-mode=sd
+ * boot-mode=net
*/
#define MY_CONFIG_BOOT_MODE "boot-mode=sd\0"
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
- "fdt_addr=0x64f00000\0" \
+ "fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
"pxefile_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
"scriptaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
- "ramdisk_addr_r=0x28000000\0" \
+ "ramdisk_addr_r=0x28000000\0" \
"fdt_addr_r=0x18000000\0" \
"fdtfile=imx6q-novena.dtb\0" \
"stdout=serial,vidconsole\0" \
"${defargs} " \
"${optargs} " \
"root=${ramroot} ramdisk_size=${ramdisk_size} " \
- "rootfstype=${ramrootfstype}\0" \
+ "rootfstype=${ramrootfstype}\0" \
"ramboot=run mmcbootenv; " \
"if run loadimage && run loaddtb && run loadramdisk; then " \
"echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \
"mmcrootfstype=ext4 rootwait\0" \
"kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \
"splashpos=0,0\0" \
- "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \
"check_env=if test -n ${flash_env_version}; " \
"then env default env_version; " \
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
+#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
"era fe000000 fe1dffff;" \
"cp.b 100000 fe000000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "update_fdt=tftp 100000 ${fdt_file};" \
+ "update_fdt=tftp 100000 ${fdt_file};" \
"era fe1e0000 fe1fffff;" \
"cp.b 100000 fe1e0000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "update_initrd=tftp 100000 ${initrd_file};" \
+ "update_initrd=tftp 100000 ${initrd_file};" \
"era fe200000 fe9fffff;" \
"cp.b 100000 fe200000 ${filesize};" \
"setenv filesize;saveenv\0" \
"clean_data=era fea00000 fff5ffff\0" \
- "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
- "load_usb=usb start;" \
+ "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
+ "load_usb=usb start;" \
"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
"boot_usb=run load_usb usbargs addcons;" \
"bootm ${kernel_addr_r} - ${fdt_addr};" \
} else if (likely(((n) >> 32) == 0)) { \
__rem = (u32)(n) % __base; \
(n) = (u32)(n) / __base; \
- } else \
+ } else \
__rem = __div64_32(&(n), __base); \
__rem; \
})
*/
#define ARMCLK 0
#define PRCMU_ACLK 1
-#define PRCMU_SVAMMCSPCLK 2
-#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
-#define PRCMU_SIACLK 3
-#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
-#define PRCMU_SGACLK 4
-#define PRCMU_UARTCLK 5
-#define PRCMU_MSP02CLK 6
-#define PRCMU_MSP1CLK 7
-#define PRCMU_I2CCLK 8
-#define PRCMU_SDMMCCLK 9
-#define PRCMU_SLIMCLK 10
-#define PRCMU_CAMCLK 10 /* DBx540 only. */
-#define PRCMU_PER1CLK 11
-#define PRCMU_PER2CLK 12
-#define PRCMU_PER3CLK 13
-#define PRCMU_PER5CLK 14
-#define PRCMU_PER6CLK 15
-#define PRCMU_PER7CLK 16
-#define PRCMU_LCDCLK 17
-#define PRCMU_BMLCLK 18
-#define PRCMU_HSITXCLK 19
-#define PRCMU_HSIRXCLK 20
+#define PRCMU_SVAMMCSPCLK 2
+#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
+#define PRCMU_SIACLK 3
+#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
+#define PRCMU_SGACLK 4
+#define PRCMU_UARTCLK 5
+#define PRCMU_MSP02CLK 6
+#define PRCMU_MSP1CLK 7
+#define PRCMU_I2CCLK 8
+#define PRCMU_SDMMCCLK 9
+#define PRCMU_SLIMCLK 10
+#define PRCMU_CAMCLK 10 /* DBx540 only. */
+#define PRCMU_PER1CLK 11
+#define PRCMU_PER2CLK 12
+#define PRCMU_PER3CLK 13
+#define PRCMU_PER5CLK 14
+#define PRCMU_PER6CLK 15
+#define PRCMU_PER7CLK 16
+#define PRCMU_LCDCLK 17
+#define PRCMU_BMLCLK 18
+#define PRCMU_HSITXCLK 19
+#define PRCMU_HSIRXCLK 20
#define PRCMU_HDMICLK 21
-#define PRCMU_APEATCLK 22
-#define PRCMU_APETRACECLK 23
-#define PRCMU_MCDECLK 24
-#define PRCMU_IPI2CCLK 25
-#define PRCMU_DSIALTCLK 26
-#define PRCMU_DMACLK 27
-#define PRCMU_B2R2CLK 28
-#define PRCMU_TVCLK 29
-#define SPARE_UNIPROCLK 30
-#define PRCMU_SSPCLK 31
-#define PRCMU_RNGCLK 32
-#define PRCMU_UICCCLK 33
+#define PRCMU_APEATCLK 22
+#define PRCMU_APETRACECLK 23
+#define PRCMU_MCDECLK 24
+#define PRCMU_IPI2CCLK 25
+#define PRCMU_DSIALTCLK 26
+#define PRCMU_DMACLK 27
+#define PRCMU_B2R2CLK 28
+#define PRCMU_TVCLK 29
+#define SPARE_UNIPROCLK 30
+#define PRCMU_SSPCLK 31
+#define PRCMU_RNGCLK 32
+#define PRCMU_UICCCLK 33
#define PRCMU_G1CLK 34 /* DBx540 only. */
#define PRCMU_HVACLK 35 /* DBx540 only. */
-#define PRCMU_SPARE1CLK 36
-#define PRCMU_SPARE2CLK 37
+#define PRCMU_SPARE1CLK 36
+#define PRCMU_SPARE2CLK 37
-#define PRCMU_NUM_REG_CLOCKS 38
+#define PRCMU_NUM_REG_CLOCKS 38
-#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
-#define PRCMU_SYSCLK 39
-#define PRCMU_CDCLK 40
-#define PRCMU_TIMCLK 41
-#define PRCMU_PLLSOC0 42
-#define PRCMU_PLLSOC1 43
-#define PRCMU_ARMSS 44
-#define PRCMU_PLLDDR 45
+#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
+#define PRCMU_SYSCLK 39
+#define PRCMU_CDCLK 40
+#define PRCMU_TIMCLK 41
+#define PRCMU_PLLSOC0 42
+#define PRCMU_PLLSOC1 43
+#define PRCMU_ARMSS 44
+#define PRCMU_PLLDDR 45
/* DSI Clocks */
-#define PRCMU_PLLDSI 46
-#define PRCMU_DSI0CLK 47
-#define PRCMU_DSI1CLK 48
-#define PRCMU_DSI0ESCCLK 49
-#define PRCMU_DSI1ESCCLK 50
-#define PRCMU_DSI2ESCCLK 51
+#define PRCMU_PLLDSI 46
+#define PRCMU_DSI0CLK 47
+#define PRCMU_DSI1CLK 48
+#define PRCMU_DSI0ESCCLK 49
+#define PRCMU_DSI1ESCCLK 50
+#define PRCMU_DSI2ESCCLK 51
/* LCD DSI PLL - Ux540 only */
#define PRCMU_PLLDSI_LCD 52
#define PRCMU_DSI1ESCCLK_LCD 56
#define PRCMU_DSI2ESCCLK_LCD 57
-#define PRCMU_NUM_CLKS 58
+#define PRCMU_NUM_CLKS 58
#endif
#if CONFIG_IS_ENABLED(CMD_SF)
#define BOOTENV_SHARED_SF(devtypel) \
- #devtypel "_boot=" \
+ #devtypel "_boot=" \
"if " #devtypel " probe ${busnum}; then " \
- "devtype=" #devtypel "; " \
- "run scan_sf_for_scripts; " \
+ "devtype=" #devtypel "; " \
+ "run scan_sf_for_scripts; " \
"fi\0"
-#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "busnum=" #instance "; " \
+#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "busnum=" #instance "; " \
"run " #devtypel "_boot\0"
-#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \
+#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \
#devtypel #instance " "
#else
#define BOOTENV_SHARED_SF(devtypel)
* 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
* Datasheet indicated it starts at bit #21 which was wrong.
* 2. FTPMU010_PDLLCR0_DLLFRAG:
- * Datasheet indicated it has 2 bit which was wrong.
+ * Datasheet indicated it has 2 bit which was wrong.
*/
#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
-#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
QE_RISC_ALLOCATION_RISC2)
#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
QE_RISC_ALLOCATION_RISC2 | \
#define WCR_WDE 0x04
#define WCR_WDT 0x08
#define WCR_SRS 0x10
-#define WCR_WDA 0x20
+#define WCR_WDA 0x20
#define SET_WCR_WT(x) (x << 8)
#define WCR_WT_MSK SET_WCR_WT(0xFF)
* generic_phy_configure() - configure a PHY device
*
* @phy: PHY port to be configured
- * @params: PHY Parameters, underlying data is specific to the PHY function
+ * @params: PHY Parameters, underlying data is specific to the PHY function
* @return 0 if OK, or a negative error code
*/
int generic_phy_configure(struct phy *phy, void *params);
} flash_header_v1_t;
typedef struct {
- uint32_t length; /* Length of data to be read from flash */
+ uint32_t length; /* Length of data to be read from flash */
} flash_cfg_parms_t;
typedef struct {
#define APM_16_BIT_SUPPORT 0x0001
#define APM_32_BIT_SUPPORT 0x0002
#define APM_IDLE_SLOWS_CLOCK 0x0004
-#define APM_BIOS_DISABLED 0x0008
+#define APM_BIOS_DISABLED 0x0008
#define APM_BIOS_DISENGAGED 0x0010
/*
/*
* We can't declare function 'inline' because __no_sanitize_address confilcts
* with inlining. Attempt to inline it may cause a build failure.
- * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
* '__maybe_unused' allows us to avoid defined-but-not-used warnings.
*/
# define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2)
#define IORESOURCE_IRQ_LOWLEVEL (1<<3)
#define IORESOURCE_IRQ_SHAREABLE (1<<4)
-#define IORESOURCE_IRQ_OPTIONAL (1<<5)
+#define IORESOURCE_IRQ_OPTIONAL (1<<5)
/* PnP DMA specific bits (IORESOURCE_BITS) */
#define IORESOURCE_DMA_TYPE_MASK (3<<0)
* Continue to iterate over list of given type, continuing after
* the current position.
*/
-#define list_for_each_entry_continue(pos, head, member) \
+#define list_for_each_entry_continue(pos, head, member) \
for (pos = list_entry(pos->member.next, typeof(*pos), member); \
prefetch(pos->member.next), &pos->member != (head); \
pos = list_entry(pos->member.next, typeof(*pos), member))
* Iterate over list of given type, continuing after current point,
* safe against removal of list entry.
*/
-#define list_for_each_entry_safe_continue(pos, n, head, member) \
+#define list_for_each_entry_safe_continue(pos, n, head, member) \
for (pos = list_entry(pos->member.next, typeof(*pos), member), \
n = list_entry(pos->member.next, typeof(*pos), member); \
&pos->member != (head); \
#define DoC_Mplus_Configuration 0x100a
#define DoC_Mplus_OutputControl 0x100c
#define DoC_Mplus_FlashControl 0x1020
-#define DoC_Mplus_FlashSelect 0x1022
+#define DoC_Mplus_FlashSelect 0x1022
#define DoC_Mplus_FlashCmd 0x1024
#define DoC_Mplus_FlashAddress 0x1026
#define DoC_Mplus_FlashData0 0x1028
#define DoC_Mplus_ReadPipeInit 0x102a
#define DoC_Mplus_LastDataRead 0x102c
#define DoC_Mplus_LastDataRead1 0x102d
-#define DoC_Mplus_WritePipeTerm 0x102e
+#define DoC_Mplus_WritePipeTerm 0x102e
#define DoC_Mplus_ECCSyndrome0 0x1040
#define DoC_Mplus_ECCSyndrome1 0x1041
#define DoC_Mplus_ECCSyndrome2 0x1042
#define DoC_Mplus_ECCSyndrome3 0x1043
#define DoC_Mplus_ECCSyndrome4 0x1044
#define DoC_Mplus_ECCSyndrome5 0x1045
-#define DoC_Mplus_ECCConf 0x1046
+#define DoC_Mplus_ECCConf 0x1046
#define DoC_Mplus_Toggle 0x1046
#define DoC_Mplus_DownloadStatus 0x1074
#define DoC_Mplus_CtrlConfirm 0x1076
* For each partition, these fields are available:
* name: string that will be used to label the partition's MTD device.
* size: the partition size; if defined as MTDPART_SIZ_FULL, the partition
- * will extend to the end of the master MTD device.
+ * will extend to the end of the master MTD device.
* offset: absolute starting position within the master MTD device; if
- * defined as MTDPART_OFS_APPEND, the partition will start where the
+ * defined as MTDPART_OFS_APPEND, the partition will start where the
* previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block;
* if MTDPART_OFS_RETAIN, consume as much as possible, leaving size
* after the end of partition.
* mask_flags: contains flags that have to be masked (removed) from the
- * master MTD flag set for the corresponding MTD partition.
- * For example, to force a read-only partition, simply adding
- * MTD_WRITEABLE to the mask_flags will do the trick.
+ * master MTD flag set for the corresponding MTD partition.
+ * For example, to force a read-only partition, simply adding
+ * MTD_WRITEABLE to the mask_flags will do the trick.
*
* Note: writeable partitions require their size and offset be
* erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK).
} __attribute__((packed));
#define VIDEO_TYPE_MDA 0x10 /* Monochrome Text Display */
-#define VIDEO_TYPE_CGA 0x11 /* CGA Display */
+#define VIDEO_TYPE_CGA 0x11 /* CGA Display */
#define VIDEO_TYPE_EGAM 0x20 /* EGA/VGA in Monochrome Mode */
#define VIDEO_TYPE_EGAC 0x21 /* EGA in Color Mode */
#define VIDEO_TYPE_VGAC 0x22 /* VGA+ in Color Mode */
#define ORIG_X (screen_info.orig_x)
#define ORIG_Y (screen_info.orig_y)
#define ORIG_VIDEO_MODE (screen_info.orig_video_mode)
-#define ORIG_VIDEO_COLS (screen_info.orig_video_cols)
+#define ORIG_VIDEO_COLS (screen_info.orig_video_cols)
#define ORIG_VIDEO_EGA_BX (screen_info.orig_video_ega_bx)
#define ORIG_VIDEO_LINES (screen_info.orig_video_lines)
#define ORIG_VIDEO_ISVGA (screen_info.orig_video_isVGA)
*/
#define UART_ASR 0x01 /* Additional Status Register */
#define UART_RFL 0x03 /* Receiver FIFO level */
-#define UART_TFL 0x04 /* Transmitter FIFO level */
+#define UART_TFL 0x04 /* Transmitter FIFO level */
#define UART_ICR 0x05 /* Index Control Register */
/* The 16950 ICR registers */
* endpoint. It's set once by UDC driver when endpoint is initialized, and
* should not be changed. Should not be confused with maxpacket.
* @max_streams: The maximum number of streams supported
- * by this EP (0 - 16, actual number is 2^n)
+ * by this EP (0 - 16, actual number is 2^n)
* @maxburst: the maximum number of bursts supported by this EP (for usb3)
* @driver_data:for use by the gadget driver. all other fields are
* read-only to gadget drivers.
* @desc: endpoint descriptor. This pointer is set before the endpoint is
- * enabled and remains valid until the endpoint is disabled.
+ * enabled and remains valid until the endpoint is disabled.
* @comp_desc: In case of SuperSpeed support, this is the endpoint companion
- * descriptor that is used to configure the endpoint
+ * descriptor that is used to configure the endpoint
*
* the bus controller driver lists all the general purpose endpoints in
* gadget->ep_list. the control endpoint (gadget->ep0) is not in that list,
#define VIOLOEN (1 << 6)
#define VIOLOSTBY (1 << 7)
#define VIOLOMODE (1 << 8)
-#define VDIGEN (1 << 9)
+#define VDIGEN (1 << 9)
#define VDIGSTBY (1 << 10)
#define VDIGMODE (1 << 11)
#define VGENEN (1 << 12)
#endif
#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
#endif
#endif /* __MPC85xx_H__ */
#define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode)
#define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme
#define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read)
-#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default
+#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default
/* OTP mode selection */
#define MTD_OTP_OFF 0
/*
* to facilitate the definition, the following macros are provided
*
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0)
#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0)
char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */
#endif
#ifdef CONFIG_DOS_PARTITION
- uchar sys_ind; /* partition type */
+ uchar sys_ind; /* partition type */
#endif
};
}
/* PHY UIDs for various PHYs that are referenced in external code */
-#define PHY_UID_CS4340 0x13e51002
-#define PHY_UID_CS4223 0x03e57003
+#define PHY_UID_CS4340 0x13e51002
+#define PHY_UID_CS4223 0x03e57003
#define PHY_UID_TN2020 0x00a19410
#define PHY_UID_IN112525_S03 0x02107440
#define TSEC_SIZE 0x40000
#define TSEC_MDIO_OFFSET 0x40000
#else
-#define TSEC_SIZE 0x01000
+#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
#endif
static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
/*{*/
- /* Char 0: ' ' */
+ /* Char 0: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 1: ' ' */
+ /* Char 1: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 2: ' ' */
+ /* Char 2: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 3: ' ' */
+ /* Char 3: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 4: ' ' */
+ /* Char 4: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 5: ' ' */
+ /* Char 5: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 6: ' ' */
+ /* Char 6: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 7: ' ' */
+ /* Char 7: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 8: ' ' */
+ /* Char 8: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 9: ' ' */
+ /* Char 9: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 10: '' */
+ /* Char 10: '' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 11: ' ' */
+ /* Char 11: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 12: ' ' */
+ /* Char 12: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 13: ' ' */
+ /* Char 13: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 14: ' ' */
+ /* Char 14: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 15: ' ' */
+ /* Char 15: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 16: ' ' */
+ /* Char 16: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 17: ' ' */
+ /* Char 17: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 18: ' ' */
+ /* Char 18: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 19: ' ' */
+ /* Char 19: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 20: ' ' */
+ /* Char 20: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 21: ' ' */
+ /* Char 21: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 22: ' ' */
+ /* Char 22: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 23: ' ' */
+ /* Char 23: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 24: ' ' */
+ /* Char 24: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 25: ' ' */
+ /* Char 25: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 26: ' ' */
+ /* Char 26: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 27: ' ' */
+ /* Char 27: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 28: ' ' */
+ /* Char 28: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 29: ' ' */
+ /* Char 29: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 30: ' ' */
+ /* Char 30: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 31: ' ' */
+ /* Char 31: ' ' */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 32: ' ' */
+ /* Char 32: ' ' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 33: '!' */
+ /* Char 33: '!' */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 34: '"' */
+ /* Char 34: '"' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 35: '#' */
+ /* Char 35: '#' */
0xaa, /*= [* * ] */
0xff, /*= [****] */
0xff, /*= [****] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 36: '$' */
+ /* Char 36: '$' */
0x44, /*= [ * ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 37: '%' */
+ /* Char 37: '%' */
0xaa, /*= [* * ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 38: '&' */
+ /* Char 38: '&' */
0x66, /*= [ ** ] */
0x99, /*= [* *] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 39: ''' */
+ /* Char 39: ''' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 40: '(' */
+ /* Char 40: '(' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 41: ')' */
+ /* Char 41: ')' */
0x44, /*= [ * ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 42: '*' */
+ /* Char 42: '*' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 43: '+' */
+ /* Char 43: '+' */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 44: ',' */
+ /* Char 44: ',' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 45: '-' */
+ /* Char 45: '-' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 46: '.' */
+ /* Char 46: '.' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 47: '/' */
+ /* Char 47: '/' */
0x00, /*= [ ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 48: '0' */
+ /* Char 48: '0' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 49: '1' */
+ /* Char 49: '1' */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 50: '2' */
+ /* Char 50: '2' */
0xcc, /*= [** ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
/*{*/
- /* Char 51: '3' */
+ /* Char 51: '3' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 52: '4' */
+ /*{*/ /* Char 52: '4' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 53: '5' */
+ /*{*/ /* Char 53: '5' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 54: '6' */
+ /*{*/ /* Char 54: '6' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 55: '7' */
+ /*{*/ /* Char 55: '7' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 56: '8' */
+ /*{*/ /* Char 56: '8' */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 57: '9' */
+ /*{*/ /* Char 57: '9' */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 58: ':' */
+ /*{*/ /* Char 58: ':' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 59: ';' */
+ /*{*/ /* Char 59: ';' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x88, /*= [* ] */
/*}*/
- /*{*/ /* Char 60: '<' */
+ /*{*/ /* Char 60: '<' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x88, /*= [* ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 61: '=' */
+ /*{*/ /* Char 61: '=' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 62: '>' */
+ /*{*/ /* Char 62: '>' */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x22, /*= [ * ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 63: '?' */
+ /*{*/ /* Char 63: '?' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 64: '@' */
+ /*{*/ /* Char 64: '@' */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 65: 'A' */
+ /*{*/ /* Char 65: 'A' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 66: 'B' */
+ /*{*/ /* Char 66: 'B' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 67: 'C' */
+ /*{*/ /* Char 67: 'C' */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0x88, /*= [* ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 68: 'D' */
+ /*{*/ /* Char 68: 'D' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 69: 'E' */
+ /*{*/ /* Char 69: 'E' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 70: 'F' */
+ /*{*/ /* Char 70: 'F' */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 71: 'G' */
+ /*{*/ /* Char 71: 'G' */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 72: 'H' */
+ /*{*/ /* Char 72: 'H' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 73: 'I' */
+ /*{*/ /* Char 73: 'I' */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 74: 'J' */
+ /*{*/ /* Char 74: 'J' */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 75: 'K' */
+ /*{*/ /* Char 75: 'K' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 76: 'L' */
+ /*{*/ /* Char 76: 'L' */
0x88, /*= [* ] */
0x88, /*= [* ] */
0x88, /*= [* ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 77: 'M' */
+ /*{*/ /* Char 77: 'M' */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 78: 'N' */
+ /*{*/ /* Char 78: 'N' */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 79: 'O' */
+ /*{*/ /* Char 79: 'O' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 80: 'P' */
+ /*{*/ /* Char 80: 'P' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xcc, /*= [** ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 81: 'Q' */
+ /*{*/ /* Char 81: 'Q' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 82: 'R' */
+ /*{*/ /* Char 82: 'R' */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 83: 'S' */
+ /*{*/ /* Char 83: 'S' */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 84: 'T' */
+ /*{*/ /* Char 84: 'T' */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 85: 'U' */
+ /*{*/ /* Char 85: 'U' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 86: 'V' */
+ /*{*/ /* Char 86: 'V' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 87: 'W' */
+ /*{*/ /* Char 87: 'W' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 88: 'X' */
+ /*{*/ /* Char 88: 'X' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 89: 'Y' */
+ /*{*/ /* Char 89: 'Y' */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 90: 'Z' */
+ /*{*/ /* Char 90: 'Z' */
0xee, /*= [*** ] */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 91: '[' */
+ /*{*/ /* Char 91: '[' */
0x66, /*= [ ** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 92: '\' */
+ /*{*/ /* Char 92: '\' */
0x00, /*= [ ] */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 93: ']' */
+ /*{*/ /* Char 93: ']' */
0x66, /*= [ ** ] */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 94: '^' */
+ /*{*/ /* Char 94: '^' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 95: '_' */
+ /*{*/ /* Char 95: '_' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
/*}*/
- /*{*/ /* Char 96: '`' */
+ /*{*/ /* Char 96: '`' */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 97: 'a' */
+ /*{*/ /* Char 97: 'a' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 98: 'b' */
+ /*{*/ /* Char 98: 'b' */
0x88, /*= [* ] */
0x88, /*= [* ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 99: 'c' */
+ /*{*/ /* Char 99: 'c' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 100: 'd' */
+ /*{*/ /* Char 100: 'd' */
0x22, /*= [ * ] */
0x22, /*= [ * ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 101: 'e' */
+ /*{*/ /* Char 101: 'e' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 102: 'f' */
+ /*{*/ /* Char 102: 'f' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 103: 'g' */
+ /*{*/ /* Char 103: 'g' */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 104: 'h' */
+ /*{*/ /* Char 104: 'h' */
0x88, /*= [* ] */
0x88, /*= [* ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 105: 'i' */
+ /*{*/ /* Char 105: 'i' */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 106: 'j' */
+ /*{*/ /* Char 106: 'j' */
0x44, /*= [ * ] */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 107: 'k' */
+ /*{*/ /* Char 107: 'k' */
0x00, /*= [ ] */
0x88, /*= [* ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 108: 'l' */
+ /*{*/ /* Char 108: 'l' */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 109: 'm' */
+ /*{*/ /* Char 109: 'm' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 110: 'n' */
+ /*{*/ /* Char 110: 'n' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 111: 'o' */
+ /*{*/ /* Char 111: 'o' */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 112: 'p' */
+ /*{*/ /* Char 112: 'p' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x88, /*= [* ] */
/*}*/
- /*{*/ /* Char 113: 'q' */
+ /*{*/ /* Char 113: 'q' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x22, /*= [ * ] */
/*}*/
- /*{*/ /* Char 114: 'r' */
+ /*{*/ /* Char 114: 'r' */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0xaa, /*= [* * ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 115: 's' */
+ /*{*/ /* Char 115: 's' */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 116: 't' */
+ /*{*/ /* Char 116: 't' */
0x00, /*= [ ] */
0x44, /*= [ * ] */
0xee, /*= [*** ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 117: 'u' */
+ /*{*/ /* Char 117: 'u' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 118: 'v' */
+ /*{*/ /* Char 118: 'v' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 119: 'w' */
+ /*{*/ /* Char 119: 'w' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 120: 'x' */
+ /*{*/ /* Char 120: 'x' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 121: 'y' */
+ /*{*/ /* Char 121: 'y' */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xaa, /*= [* * ] */
0x22, /*= [ * ] */
0xcc, /*= [** ] */
/*}*/
- /*{*/ /* Char 122: 'z' */
+ /*{*/ /* Char 122: 'z' */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 123: '{' */
+ /*{*/ /* Char 123: '{' */
0x22, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x22, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 124: '|' */
+ /*{*/ /* Char 124: '|' */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 125: '}' */
+ /*{*/ /* Char 125: '}' */
0x88, /*= [* ] */
0x44, /*= [ * ] */
0x66, /*= [ ** ] */
0x88, /*= [* ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 126: '~' */
+ /*{*/ /* Char 126: '~' */
0x55, /*= [ * *] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 127: '\7f' */
+ /*{*/ /* Char 127: '\7f' */
0x44, /*= [ * ] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 128: */
+ /*{*/ /* Char 128: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 129: */
+ /*{*/ /* Char 129: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 130: */
+ /*{*/ /* Char 130: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 131: */
+ /*{*/ /* Char 131: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 132: */
+ /*{*/ /* Char 132: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 133: */
+ /*{*/ /* Char 133: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 134: */
+ /*{*/ /* Char 134: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 135: */
+ /*{*/ /* Char 135: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 136: */
+ /*{*/ /* Char 136: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 137: */
+ /*{*/ /* Char 137: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 138: */
+ /*{*/ /* Char 138: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 139: */
+ /*{*/ /* Char 139: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 140: */
+ /*{*/ /* Char 140: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 141: */
+ /*{*/ /* Char 141: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 142: */
+ /*{*/ /* Char 142: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 143: */
+ /*{*/ /* Char 143: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 144: */
+ /*{*/ /* Char 144: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 145: */
+ /*{*/ /* Char 145: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 146: */
+ /*{*/ /* Char 146: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 147: */
+ /*{*/ /* Char 147: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 148: */
+ /*{*/ /* Char 148: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 149: */
+ /*{*/ /* Char 149: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 150: */
+ /*{*/ /* Char 150: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 151: */
+ /*{*/ /* Char 151: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 152: */
+ /*{*/ /* Char 152: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 153: */
+ /*{*/ /* Char 153: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 154: */
+ /*{*/ /* Char 154: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 155: */
+ /*{*/ /* Char 155: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 156: */
+ /*{*/ /* Char 156: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 157: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 158: */
+ /*{*/ /* Char 158: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 159: */
+ /*{*/ /* Char 159: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
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- /*{*/ /* Char 160: */
+ /*{*/ /* Char 160: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 161: */
+ /*{*/ /* Char 161: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 162: */
+ /*{*/ /* Char 162: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 163: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 164: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
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- /*{*/ /* Char 165: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 166: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 167: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 168: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 169: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 170: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
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0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 171: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 172: */
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0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 173: */
+ /*{*/ /* Char 173: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 174: */
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0x00, /*= [ ] */
0x66, /*= [ ** ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 175: */
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0x00, /*= [ ] */
0xcc, /*= [** ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 176: */
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0x88, /*= [* ] */
0x22, /*= [ * ] */
0x88, /*= [* ] */
0x88, /*= [* ] */
0x22, /*= [ * ] */
/*}*/
- /*{*/ /* Char 177: */
+ /*{*/ /* Char 177: */
0xaa, /*= [* * ] */
0x55, /*= [ * *] */
0xaa, /*= [* * ] */
0xaa, /*= [* * ] */
0x55, /*= [ * *] */
/*}*/
- /*{*/ /* Char 178: */
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0xdd, /*= [** *] */
0xbb, /*= [* **] */
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- /*{*/ /* Char 179: */
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0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
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- /*{*/ /* Char 180: */
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0x44, /*= [ * ] */
0xcc, /*= [** ] */
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0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 181: */
+ /*{*/ /* Char 181: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 182: */
+ /*{*/ /* Char 182: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 183: */
+ /*{*/ /* Char 183: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 184: */
+ /*{*/ /* Char 184: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 185: */
+ /*{*/ /* Char 185: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 186: */
+ /*{*/ /* Char 186: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 187: */
+ /*{*/ /* Char 187: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xee, /*= [*** ] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 188: */
+ /*{*/ /* Char 188: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 189: */
+ /*{*/ /* Char 189: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 190: */
+ /*{*/ /* Char 190: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 191: */
+ /*{*/ /* Char 191: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xcc, /*= [** ] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 192: */
+ /*{*/ /* Char 192: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 193: */
+ /*{*/ /* Char 193: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 194: */
+ /*{*/ /* Char 194: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 195: */
+ /*{*/ /* Char 195: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 196: */
+ /*{*/ /* Char 196: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 197: */
+ /*{*/ /* Char 197: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 198: */
+ /*{*/ /* Char 198: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 199: */
+ /*{*/ /* Char 199: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 200: */
+ /*{*/ /* Char 200: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 201: */
+ /*{*/ /* Char 201: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 202: */
+ /*{*/ /* Char 202: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 203: */
+ /*{*/ /* Char 203: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 204: */
+ /*{*/ /* Char 204: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 205: */
+ /*{*/ /* Char 205: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 206: */
+ /*{*/ /* Char 206: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 207: */
+ /*{*/ /* Char 207: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 208: */
+ /*{*/ /* Char 208: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 209: */
+ /*{*/ /* Char 209: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 210: */
+ /*{*/ /* Char 210: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 211: */
+ /*{*/ /* Char 211: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 212: */
+ /*{*/ /* Char 212: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0x77, /*= [ ***] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 213: */
+ /*{*/ /* Char 213: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 214: */
+ /*{*/ /* Char 214: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 215: */
+ /*{*/ /* Char 215: */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
0xff, /*= [****] */
0x66, /*= [ ** ] */
0x66, /*= [ ** ] */
/*}*/
- /*{*/ /* Char 216: */
+ /*{*/ /* Char 216: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xff, /*= [****] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 217: */
+ /*{*/ /* Char 217: */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
0xcc, /*= [** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 218: */
+ /*{*/ /* Char 218: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x77, /*= [ ***] */
0x44, /*= [ * ] */
0x44, /*= [ * ] */
/*}*/
- /*{*/ /* Char 219: */
+ /*{*/ /* Char 219: */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
/*}*/
- /*{*/ /* Char 220: */
+ /*{*/ /* Char 220: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
0xff, /*= [****] */
0xff, /*= [****] */
/*}*/
- /*{*/ /* Char 221: */
+ /*{*/ /* Char 221: */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
0xcc, /*= [** ] */
/*}*/
- /*{*/ /* Char 222: */
+ /*{*/ /* Char 222: */
0x33, /*= [ **] */
0x33, /*= [ **] */
0x33, /*= [ **] */
0x33, /*= [ **] */
0x33, /*= [ **] */
/*}*/
- /*{*/ /* Char 223: */
+ /*{*/ /* Char 223: */
0xff, /*= [****] */
0xff, /*= [****] */
0xff, /*= [****] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 224: */
+ /*{*/ /* Char 224: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 225: */
+ /*{*/ /* Char 225: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 226: */
+ /*{*/ /* Char 226: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 227: */
+ /*{*/ /* Char 227: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 228: */
+ /*{*/ /* Char 228: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 229: */
+ /*{*/ /* Char 229: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 230: */
+ /*{*/ /* Char 230: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 231: */
+ /*{*/ /* Char 231: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 232: */
+ /*{*/ /* Char 232: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 233: */
+ /*{*/ /* Char 233: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 234: */
+ /*{*/ /* Char 234: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 235: */
+ /*{*/ /* Char 235: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 236: */
+ /*{*/ /* Char 236: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 237: */
+ /*{*/ /* Char 237: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 238: */
+ /*{*/ /* Char 238: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 239: */
+ /*{*/ /* Char 239: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 240: */
+ /*{*/ /* Char 240: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 241: */
+ /*{*/ /* Char 241: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 242: */
+ /*{*/ /* Char 242: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 243: */
+ /*{*/ /* Char 243: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 244: */
+ /*{*/ /* Char 244: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 245: */
+ /*{*/ /* Char 245: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 246: */
+ /*{*/ /* Char 246: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 247: */
+ /*{*/ /* Char 247: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 248: */
+ /*{*/ /* Char 248: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 249: */
+ /*{*/ /* Char 249: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 250: */
+ /*{*/ /* Char 250: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 251: */
+ /*{*/ /* Char 251: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 252: */
+ /*{*/ /* Char 252: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 253: */
+ /*{*/ /* Char 253: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 254: */
+ /*{*/ /* Char 254: */
0x00, /*= [ ] */
0x00, /*= [ ] */
0x66, /*= [ ** ] */
0x00, /*= [ ] */
0x00, /*= [ ] */
/*}*/
- /*{*/ /* Char 255: */
+ /*{*/ /* Char 255: */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
0xee, /*= [*** ] */
# when kernel configuration changes (which is what happens when
# .config is included by main Makefile.
# ---------------------------------------------------------------------------
-# fixdep: Used to generate dependency information during build process
+# fixdep: Used to generate dependency information during build process
hostprogs-y := fixdep
always := $(hostprogs-y)
localyesconfig localmodconfig: $(obj)/conf
$(Q)perl $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config
- $(Q)if [ -f .config ]; then \
+ $(Q)if [ -f .config ]; then \
cmp -s .tmp.config .config || \
(mv -f .config .config.old.1; \
mv -f .tmp.config .config; \
default:
;
}
- return false;
+ return false;
}
/*
*/
#define list_for_each_entry(pos, head, member) \
for (pos = list_entry((head)->next, typeof(*pos), member); \
- &pos->member != (head); \
+ &pos->member != (head); \
pos = list_entry(pos->member.next, typeof(*pos), member))
/**
/* NAND ECC Mode */
#define IBR_HDR_ECC_DEFAULT 0x00
#define IBR_HDR_ECC_FORCED_HAMMING 0x01
-#define IBR_HDR_ECC_FORCED_RS 0x02
-#define IBR_HDR_ECC_DISABLED 0x03
+#define IBR_HDR_ECC_FORCED_RS 0x02
+#define IBR_HDR_ECC_DISABLED 0x03
/* Boot Type - block ID */
#define IBR_HDR_I2C_ID 0x4D
projects / platform / kernel / u-boot.git / commitdiff