1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Andes Technology Corporation
4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
15 #include <asm/macro.h>
16 #include <generated/asm-offsets.h>
19 * parameters for the SDRAM controller
21 #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
22 #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
23 #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
24 #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
25 #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
26 #define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
28 #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
29 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
30 #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
31 #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
33 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
34 #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
38 * for Orca and Emerald
40 #define BOARD_ID_REG 0x104
41 #define BOARD_ID_FAMILY_MASK 0xfff000
42 #define BOARD_ID_FAMILY_V5 0x556000
43 #define BOARD_ID_FAMILY_K7 0x74b000
46 * parameters for the static memory controller
48 #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
49 #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
51 #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
52 #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
55 * for Orca and Emerald
57 #define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
58 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
61 * parameters for the pmu controoler
63 #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
66 * numeric 7 segment display
69 write32 CONFIG_DEBUG_LED, \num
73 * Waiting for SDRAM to set up
76 li $r0, CONFIG_FTSDMC021_BASE
78 lwi $r1, [$r0+FTSDMC021_CR2]
85 li $r0, SMC_BANK0_CR_A
97 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
103 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
113 #ifdef CONFIG_MEM_REMAP
118 lmw.bim $r12, [$r5], $r19
119 smw.bim $r12, [$r4], $r19
121 #endif /* #ifdef CONFIG_MEM_REMAP */
128 * Some of Andes CPU version support FPU coprocessor, if so,
129 * and toolchain support FPU instruction set, we should enable it.
131 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
133 mfsr $r0, $CPU_VER /* enable FPU if it exists */
136 beqz $r0, 1f /* skip if no COP */
137 mfsr $r0, $FUCOP_EXIST
139 beqz $r0, 1f /* skip if no FPU */
147 #endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */