drivers/mtd/nand/raw/fsl_elbc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   3  *
   4  * Copyright (c) 2006-2008 Freescale Semiconductor
   5  *
   6  * Authors: Nick Spence <nick.spence@freescale.com>,
   7  *          Scott Wood <scottwood@freescale.com>
   8  */
   9
  10 #include <common.h>
  11 #include <command.h>
  12 #include <malloc.h>
  13 #include <nand.h>
  14 #include <dm/devres.h>
  15
  16 #include <linux/mtd/mtd.h>
  17 #include <linux/mtd/rawnand.h>
  18 #include <linux/mtd/nand_ecc.h>
  19
  20 #include <asm/io.h>
  21 #include <linux/errno.h>
  22
  23 #ifdef VERBOSE_DEBUG
  24 #define DEBUG_ELBC
  25 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  26 #else
  27 #define vdbg(format, arg...) do {} while (0)
  28 #endif
  29
  30 /* Can't use plain old DEBUG because the linux mtd
  31  * headers define it as a macro.
  32  */
  33 #ifdef DEBUG_ELBC
  34 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  35 #else
  36 #define dbg(format, arg...) do {} while (0)
  37 #endif
  38
  39 #define MAX_BANKS 8
  40 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  41
  42 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  43
  44 struct fsl_elbc_ctrl;
  45
  46 /* mtd information per set */
  47
  48 struct fsl_elbc_mtd {
  49         struct nand_chip chip;
  50         struct fsl_elbc_ctrl *ctrl;
  51
  52         struct device *dev;
  53         int bank;               /* Chip select bank number           */
  54         u8 __iomem *vbase;      /* Chip select base virtual address  */
  55         int page_size;          /* NAND page size (0=512, 1=2048)    */
  56         unsigned int fmr;       /* FCM Flash Mode Register value     */
  57 };
  58
  59 /* overview of the fsl elbc controller */
  60
  61 struct fsl_elbc_ctrl {
  62         struct nand_hw_control controller;
  63         struct fsl_elbc_mtd *chips[MAX_BANKS];
  64
  65         /* device info */
  66         fsl_lbc_t *regs;
  67         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  68         unsigned int page;       /* Last page written to / read from      */
  69         unsigned int read_bytes; /* Number of bytes read during command   */
  70         unsigned int column;     /* Saved column from SEQIN               */
  71         unsigned int index;      /* Pointer to next byte to 'read'        */
  72         unsigned int status;     /* status read from LTESR after last op  */
  73         unsigned int mdr;        /* UPM/FCM Data Register value           */
  74         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  75         unsigned int oob;        /* Non zero if operating on OOB data     */
  76 };
  77
  78 /* These map to the positions used by the FCM hardware ECC generator */
  79
  80 /* Small Page FLASH with FMR[ECCM] = 0 */
  81 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  82         .eccbytes = 3,
  83         .eccpos = {6, 7, 8},
  84         .oobfree = { {0, 5}, {9, 7} },
  85 };
  86
  87 /* Small Page FLASH with FMR[ECCM] = 1 */
  88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  89         .eccbytes = 3,
  90         .eccpos = {8, 9, 10},
  91         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  92 };
  93
  94 /* Large Page FLASH with FMR[ECCM] = 0 */
  95 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  96         .eccbytes = 12,
  97         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
  98         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
  99 };
 100
 101 /* Large Page FLASH with FMR[ECCM] = 1 */
 102 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 103         .eccbytes = 12,
 104         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 105         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 106 };
 107
 108 /*
 109  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 110  * 1, so we have to adjust bad block pattern. This pattern should be used for
 111  * x8 chips only. So far hardware does not support x16 chips anyway.
 112  */
 113 static u8 scan_ff_pattern[] = { 0xff, };
 114
 115 static struct nand_bbt_descr largepage_memorybased = {
 116         .options = 0,
 117         .offs = 0,
 118         .len = 1,
 119         .pattern = scan_ff_pattern,
 120 };
 121
 122 /*
 123  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 124  * interfere with ECC positions, that's why we implement our own descriptors.
 125  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 126  */
 127 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 128 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 129
 130 static struct nand_bbt_descr bbt_main_descr = {
 131         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 132                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 133         .offs = 11,
 134         .len = 4,
 135         .veroffs = 15,
 136         .maxblocks = 4,
 137         .pattern = bbt_pattern,
 138 };
 139
 140 static struct nand_bbt_descr bbt_mirror_descr = {
 141         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 142                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 143         .offs = 11,
 144         .len = 4,
 145         .veroffs = 15,
 146         .maxblocks = 4,
 147         .pattern = mirror_pattern,
 148 };
 149
 150 /*=================================*/
 151
 152 /*
 153  * Set up the FCM hardware block and page address fields, and the fcm
 154  * structure addr field to point to the correct FCM buffer in memory
 155  */
 156 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 157 {
 158         struct nand_chip *chip = mtd_to_nand(mtd);
 159         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 160         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 161         fsl_lbc_t *lbc = ctrl->regs;
 162         int buf_num;
 163
 164         ctrl->page = page_addr;
 165
 166         if (priv->page_size) {
 167                 out_be32(&lbc->fbar, page_addr >> 6);
 168                 out_be32(&lbc->fpar,
 169                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 170                          (oob ? FPAR_LP_MS : 0) | column);
 171                 buf_num = (page_addr & 1) << 2;
 172         } else {
 173                 out_be32(&lbc->fbar, page_addr >> 5);
 174                 out_be32(&lbc->fpar,
 175                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 176                          (oob ? FPAR_SP_MS : 0) | column);
 177                 buf_num = page_addr & 7;
 178         }
 179
 180         ctrl->addr = priv->vbase + buf_num * 1024;
 181         ctrl->index = column;
 182
 183         /* for OOB data point to the second half of the buffer */
 184         if (oob)
 185                 ctrl->index += priv->page_size ? 2048 : 512;
 186
 187         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 188              "index %x, pes %d ps %d\n",
 189              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 190              chip->phys_erase_shift, chip->page_shift);
 191 }
 192
 193 /*
 194  * execute FCM command and wait for it to complete
 195  */
 196 static int fsl_elbc_run_command(struct mtd_info *mtd)
 197 {
 198         struct nand_chip *chip = mtd_to_nand(mtd);
 199         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 200         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 201         fsl_lbc_t *lbc = ctrl->regs;
 202         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 203         u32 time_start;
 204         u32 ltesr;
 205
 206         /* Setup the FMR[OP] to execute without write protection */
 207         out_be32(&lbc->fmr, priv->fmr | 3);
 208         if (ctrl->use_mdr)
 209                 out_be32(&lbc->mdr, ctrl->mdr);
 210
 211         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 212              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 213         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 214              "fbcr=%08x bank=%d\n",
 215              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 216              in_be32(&lbc->fbcr), priv->bank);
 217
 218         /* execute special operation */
 219         out_be32(&lbc->lsor, priv->bank);
 220
 221         /* wait for FCM complete flag or timeout */
 222         time_start = get_timer(0);
 223
 224         ltesr = 0;
 225         while (get_timer(time_start) < timeo) {
 226                 ltesr = in_be32(&lbc->ltesr);
 227                 if (ltesr & LTESR_CC)
 228                         break;
 229         }
 230
 231         ctrl->status = ltesr & LTESR_NAND_MASK;
 232         out_be32(&lbc->ltesr, ctrl->status);
 233         out_be32(&lbc->lteatr, 0);
 234
 235         /* store mdr value in case it was needed */
 236         if (ctrl->use_mdr)
 237                 ctrl->mdr = in_be32(&lbc->mdr);
 238
 239         ctrl->use_mdr = 0;
 240
 241         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 242              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 243
 244         /* returns 0 on success otherwise non-zero) */
 245         return ctrl->status == LTESR_CC ? 0 : -EIO;
 246 }
 247
 248 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 249 {
 250         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 251         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 252         fsl_lbc_t *lbc = ctrl->regs;
 253
 254         if (priv->page_size) {
 255                 out_be32(&lbc->fir,
 256                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 257                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 258                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 259                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 260                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 261
 262                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 263                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 264         } else {
 265                 out_be32(&lbc->fir,
 266                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 267                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 268                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 269                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 270
 271                 if (oob)
 272                         out_be32(&lbc->fcr,
 273                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 274                 else
 275                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 276         }
 277 }
 278
 279 /* cmdfunc send commands to the FCM */
 280 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 281                              int column, int page_addr)
 282 {
 283         struct nand_chip *chip = mtd_to_nand(mtd);
 284         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 285         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 286         fsl_lbc_t *lbc = ctrl->regs;
 287
 288         ctrl->use_mdr = 0;
 289
 290         /* clear the read buffer */
 291         ctrl->read_bytes = 0;
 292         if (command != NAND_CMD_PAGEPROG)
 293                 ctrl->index = 0;
 294
 295         switch (command) {
 296         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 297         case NAND_CMD_READ1:
 298                 column += 256;
 299
 300         /* fall-through */
 301         case NAND_CMD_READ0:
 302                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 303                      " 0x%x, column: 0x%x.\n", page_addr, column);
 304
 305                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 306                 set_addr(mtd, 0, page_addr, 0);
 307
 308                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 309                 ctrl->index += column;
 310
 311                 fsl_elbc_do_read(chip, 0);
 312                 fsl_elbc_run_command(mtd);
 313                 return;
 314
 315         /* READOOB reads only the OOB because no ECC is performed. */
 316         case NAND_CMD_READOOB:
 317                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 318                      " 0x%x, column: 0x%x.\n", page_addr, column);
 319
 320                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 321                 set_addr(mtd, column, page_addr, 1);
 322
 323                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 324
 325                 fsl_elbc_do_read(chip, 1);
 326                 fsl_elbc_run_command(mtd);
 327
 328                 return;
 329
 330         /* READID must read all 5 possible bytes while CEB is active */
 331         case NAND_CMD_READID:
 332         case NAND_CMD_PARAM:
 333                 vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
 334
 335                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 336                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 337                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 338                 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
 339                 /*
 340                  * although currently it's 8 bytes for READID, we always read
 341                  * the maximum 256 bytes(for PARAM)
 342                  */
 343                 out_be32(&lbc->fbcr, 256);
 344                 ctrl->read_bytes = 256;
 345                 ctrl->use_mdr = 1;
 346                 ctrl->mdr = column;
 347                 set_addr(mtd, 0, 0, 0);
 348                 fsl_elbc_run_command(mtd);
 349                 return;
 350
 351         /* ERASE1 stores the block and page address */
 352         case NAND_CMD_ERASE1:
 353                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 354                      "page_addr: 0x%x.\n", page_addr);
 355                 set_addr(mtd, 0, page_addr, 0);
 356                 return;
 357
 358         /* ERASE2 uses the block and page address from ERASE1 */
 359         case NAND_CMD_ERASE2:
 360                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 361
 362                 out_be32(&lbc->fir,
 363                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 364                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 365                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 366
 367                 out_be32(&lbc->fcr,
 368                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 369                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 370
 371                 out_be32(&lbc->fbcr, 0);
 372                 ctrl->read_bytes = 0;
 373
 374                 fsl_elbc_run_command(mtd);
 375                 return;
 376
 377         /* SEQIN sets up the addr buffer and all registers except the length */
 378         case NAND_CMD_SEQIN: {
 379                 u32 fcr;
 380                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 381                      "page_addr: 0x%x, column: 0x%x.\n",
 382                      page_addr, column);
 383
 384                 ctrl->column = column;
 385                 ctrl->oob = 0;
 386
 387                 if (priv->page_size) {
 388                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 389                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 390
 391                         out_be32(&lbc->fir,
 392                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 393                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 394                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 395                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 396                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 397                 } else {
 398                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 399                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 400
 401                         out_be32(&lbc->fir,
 402                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 403                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 404                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 405                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 406                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 407                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 408
 409                         if (column >= mtd->writesize) {
 410                                 /* OOB area --> READOOB */
 411                                 column -= mtd->writesize;
 412                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 413                                 ctrl->oob = 1;
 414                         } else if (column < 256) {
 415                                 /* First 256 bytes --> READ0 */
 416                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 417                         } else {
 418                                 /* Second 256 bytes --> READ1 */
 419                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 420                         }
 421                 }
 422
 423                 out_be32(&lbc->fcr, fcr);
 424                 set_addr(mtd, column, page_addr, ctrl->oob);
 425                 return;
 426         }
 427
 428         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 429         case NAND_CMD_PAGEPROG: {
 430                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 431                      "writing %d bytes.\n", ctrl->index);
 432
 433                 /* if the write did not start at 0 or is not a full page
 434                  * then set the exact length, otherwise use a full page
 435                  * write so the HW generates the ECC.
 436                  */
 437                 if (ctrl->oob || ctrl->column != 0 ||
 438                     ctrl->index != mtd->writesize + mtd->oobsize)
 439                         out_be32(&lbc->fbcr, ctrl->index);
 440                 else
 441                         out_be32(&lbc->fbcr, 0);
 442
 443                 fsl_elbc_run_command(mtd);
 444
 445                 return;
 446         }
 447
 448         /* CMD_STATUS must read the status byte while CEB is active */
 449         /* Note - it does not wait for the ready line */
 450         case NAND_CMD_STATUS:
 451                 out_be32(&lbc->fir,
 452                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 453                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 454                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 455                 out_be32(&lbc->fbcr, 1);
 456                 set_addr(mtd, 0, 0, 0);
 457                 ctrl->read_bytes = 1;
 458
 459                 fsl_elbc_run_command(mtd);
 460
 461                 /* The chip always seems to report that it is
 462                  * write-protected, even when it is not.
 463                  */
 464                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 465                 return;
 466
 467         /* RESET without waiting for the ready line */
 468         case NAND_CMD_RESET:
 469                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 470                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 471                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 472                 fsl_elbc_run_command(mtd);
 473                 return;
 474
 475         default:
 476                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 477                         command);
 478         }
 479 }
 480
 481 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 482 {
 483         /* The hardware does not seem to support multiple
 484          * chips per bank.
 485          */
 486 }
 487
 488 /*
 489  * Write buf to the FCM Controller Data Buffer
 490  */
 491 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 492 {
 493         struct nand_chip *chip = mtd_to_nand(mtd);
 494         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 495         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 496         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 497
 498         if (len <= 0) {
 499                 printf("write_buf of %d bytes", len);
 500                 ctrl->status = 0;
 501                 return;
 502         }
 503
 504         if ((unsigned int)len > bufsize - ctrl->index) {
 505                 printf("write_buf beyond end of buffer "
 506                        "(%d requested, %u available)\n",
 507                        len, bufsize - ctrl->index);
 508                 len = bufsize - ctrl->index;
 509         }
 510
 511         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 512         /*
 513          * This is workaround for the weird elbc hangs during nand write,
 514          * Scott Wood says: "...perhaps difference in how long it takes a
 515          * write to make it through the localbus compared to a write to IMMR
 516          * is causing problems, and sync isn't helping for some reason."
 517          * Reading back the last byte helps though.
 518          */
 519         in_8(&ctrl->addr[ctrl->index] + len - 1);
 520
 521         ctrl->index += len;
 522 }
 523
 524 /*
 525  * read a byte from either the FCM hardware buffer if it has any data left
 526  * otherwise issue a command to read a single byte.
 527  */
 528 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 529 {
 530         struct nand_chip *chip = mtd_to_nand(mtd);
 531         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 532         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 533
 534         /* If there are still bytes in the FCM, then use the next byte. */
 535         if (ctrl->index < ctrl->read_bytes)
 536                 return in_8(&ctrl->addr[ctrl->index++]);
 537
 538         printf("read_byte beyond end of buffer\n");
 539         return ERR_BYTE;
 540 }
 541
 542 /*
 543  * Read from the FCM Controller Data Buffer
 544  */
 545 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 546 {
 547         struct nand_chip *chip = mtd_to_nand(mtd);
 548         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 549         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 550         int avail;
 551
 552         if (len < 0)
 553                 return;
 554
 555         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 556         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 557         ctrl->index += avail;
 558
 559         if (len > avail)
 560                 printf("read_buf beyond end of buffer "
 561                        "(%d requested, %d available)\n",
 562                        len, avail);
 563 }
 564
 565 /* This function is called after Program and Erase Operations to
 566  * check for success or failure.
 567  */
 568 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 569 {
 570         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 571         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 572         fsl_lbc_t *lbc = ctrl->regs;
 573
 574         if (ctrl->status != LTESR_CC)
 575                 return NAND_STATUS_FAIL;
 576
 577         /* Use READ_STATUS command, but wait for the device to be ready */
 578         ctrl->use_mdr = 0;
 579         out_be32(&lbc->fir,
 580                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 581                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 582         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 583         out_be32(&lbc->fbcr, 1);
 584         set_addr(mtd, 0, 0, 0);
 585         ctrl->read_bytes = 1;
 586
 587         fsl_elbc_run_command(mtd);
 588
 589         if (ctrl->status != LTESR_CC)
 590                 return NAND_STATUS_FAIL;
 591
 592         /* The chip always seems to report that it is
 593          * write-protected, even when it is not.
 594          */
 595         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 596         return fsl_elbc_read_byte(mtd);
 597 }
 598
 599 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 600                               uint8_t *buf, int oob_required, int page)
 601 {
 602         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 603         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 604
 605         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 606                 mtd->ecc_stats.failed++;
 607
 608         return 0;
 609 }
 610
 611 /* ECC will be calculated automatically, and errors will be detected in
 612  * waitfunc.
 613  */
 614 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 615                                 const uint8_t *buf, int oob_required,
 616                                 int page)
 617 {
 618         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 619         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 620
 621         return 0;
 622 }
 623
 624 static struct fsl_elbc_ctrl *elbc_ctrl;
 625
 626 /* ECC will be calculated automatically, and errors will be detected in
 627  * waitfunc.
 628  */
 629 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 630                                 uint32_t offset, uint32_t data_len,
 631                                 const uint8_t *buf, int oob_required, int page)
 632 {
 633         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 634         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 635
 636         return 0;
 637 }
 638
 639 static void fsl_elbc_ctrl_init(void)
 640 {
 641         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 642         if (!elbc_ctrl)
 643                 return;
 644
 645         elbc_ctrl->regs = LBC_BASE_ADDR;
 646
 647         /* clear event registers */
 648         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 649         out_be32(&elbc_ctrl->regs->lteatr, 0);
 650
 651         /* Enable interrupts for any detected events */
 652         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 653
 654         elbc_ctrl->read_bytes = 0;
 655         elbc_ctrl->index = 0;
 656         elbc_ctrl->addr = NULL;
 657 }
 658
 659 static int fsl_elbc_chip_init(int devnum, u8 *addr)
 660 {
 661         struct mtd_info *mtd;
 662         struct nand_chip *nand;
 663         struct fsl_elbc_mtd *priv;
 664         uint32_t br = 0, or = 0;
 665         int ret;
 666
 667         if (!elbc_ctrl) {
 668                 fsl_elbc_ctrl_init();
 669                 if (!elbc_ctrl)
 670                         return -1;
 671         }
 672
 673         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 674         if (!priv)
 675                 return -ENOMEM;
 676
 677         priv->ctrl = elbc_ctrl;
 678         priv->vbase = addr;
 679
 680         /* Find which chip select it is connected to.  It'd be nice
 681          * if we could pass more than one datum to the NAND driver...
 682          */
 683         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 684                 phys_addr_t phys_addr = virt_to_phys(addr);
 685
 686                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 687                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 688
 689                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 690                     (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
 691                         break;
 692         }
 693
 694         if (priv->bank >= MAX_BANKS) {
 695                 printf("fsl_elbc_nand: address did not match any "
 696                        "chip selects\n");
 697                 kfree(priv);
 698                 return -ENODEV;
 699         }
 700
 701         nand = &priv->chip;
 702         mtd = nand_to_mtd(nand);
 703
 704         elbc_ctrl->chips[priv->bank] = priv;
 705
 706         /* fill in nand_chip structure */
 707         /* set up function call table */
 708         nand->read_byte = fsl_elbc_read_byte;
 709         nand->write_buf = fsl_elbc_write_buf;
 710         nand->read_buf = fsl_elbc_read_buf;
 711         nand->select_chip = fsl_elbc_select_chip;
 712         nand->cmdfunc = fsl_elbc_cmdfunc;
 713         nand->waitfunc = fsl_elbc_wait;
 714
 715         /* set up nand options */
 716         nand->bbt_td = &bbt_main_descr;
 717         nand->bbt_md = &bbt_mirror_descr;
 718
 719         /* set up nand options */
 720         nand->options = NAND_NO_SUBPAGE_WRITE;
 721         nand->bbt_options = NAND_BBT_USE_FLASH;
 722
 723         nand->controller = &elbc_ctrl->controller;
 724         nand_set_controller_data(nand, priv);
 725
 726         nand->ecc.read_page = fsl_elbc_read_page;
 727         nand->ecc.write_page = fsl_elbc_write_page;
 728         nand->ecc.write_subpage = fsl_elbc_write_subpage;
 729
 730         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 731
 732         /* If CS Base Register selects full hardware ECC then use it */
 733         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 734                 nand->ecc.mode = NAND_ECC_HW;
 735
 736                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 737                                    &fsl_elbc_oob_sp_eccm1 :
 738                                    &fsl_elbc_oob_sp_eccm0;
 739
 740                 nand->ecc.size = 512;
 741                 nand->ecc.bytes = 3;
 742                 nand->ecc.steps = 1;
 743                 nand->ecc.strength = 1;
 744         } else {
 745                 /* otherwise fall back to software ECC */
 746 #if defined(CONFIG_NAND_ECC_BCH)
 747                 nand->ecc.mode = NAND_ECC_SOFT_BCH;
 748 #else
 749                 nand->ecc.mode = NAND_ECC_SOFT;
 750 #endif
 751         }
 752
 753         ret = nand_scan_ident(mtd, 1, NULL);
 754         if (ret)
 755                 return ret;
 756
 757         /* Large-page-specific setup */
 758         if (mtd->writesize == 2048) {
 759                 setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
 760                              OR_FCM_PGS);
 761                 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 762
 763                 priv->page_size = 1;
 764                 nand->badblock_pattern = &largepage_memorybased;
 765
 766                 /*
 767                  * Hardware expects small page has ECCM0, large page has
 768                  * ECCM1 when booting from NAND, and we follow that even
 769                  * when not booting from NAND.
 770                  */
 771                 priv->fmr |= FMR_ECCM;
 772
 773                 /* adjust ecc setup if needed */
 774                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 775                         nand->ecc.steps = 4;
 776                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 777                                            &fsl_elbc_oob_lp_eccm1 :
 778                                            &fsl_elbc_oob_lp_eccm0;
 779                 }
 780         } else if (mtd->writesize == 512) {
 781                 clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
 782                              OR_FCM_PGS);
 783                 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 784         } else {
 785                 return -ENODEV;
 786         }
 787
 788         ret = nand_scan_tail(mtd);
 789         if (ret)
 790                 return ret;
 791
 792         ret = nand_register(devnum, mtd);
 793         if (ret)
 794                 return ret;
 795
 796         return 0;
 797 }
 798
 799 #ifndef CONFIG_SYS_NAND_BASE_LIST
 800 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 801 #endif
 802
 803 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
 804         CONFIG_SYS_NAND_BASE_LIST;
 805
 806 void board_nand_init(void)
 807 {
 808         int i;
 809
 810         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 811                 fsl_elbc_chip_init(i, (u8 *)base_address[i]);
 812 }