arch/mips/include/asm/mipsregs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   4  * Copyright (C) 2000 Silicon Graphics, Inc.
   5  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   6  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   7  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
   8  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   9  */
  10 #ifndef _ASM_MIPSREGS_H
  11 #define _ASM_MIPSREGS_H
  12
  13 #include <asm/compiler.h>
  14 #include <asm/isa-rev.h>
  15 /*
  16  * The following macros are especially useful for __asm__
  17  * inline assembler.
  18  */
  19 #ifndef __STR
  20 #define __STR(x) #x
  21 #endif
  22 #ifndef STR
  23 #define STR(x) __STR(x)
  24 #endif
  25
  26 /*
  27  *  Configure language
  28  */
  29 #ifdef __ASSEMBLY__
  30 #define _ULCAST_
  31 #define _U64CAST_
  32 #else
  33 #define _ULCAST_ (unsigned long)
  34 #define _U64CAST_ (u64)
  35 #endif
  36
  37 /*
  38  * Coprocessor 0 register names
  39  */
  40 #define CP0_INDEX $0
  41 #define CP0_RANDOM $1
  42 #define CP0_ENTRYLO0 $2
  43 #define CP0_ENTRYLO1 $3
  44 #define CP0_CONF $3
  45 #define CP0_GLOBALNUMBER $3, 1
  46 #define CP0_CONTEXT $4
  47 #define CP0_PAGEMASK $5
  48 #define CP0_PAGEGRAIN $5, 1
  49 #define CP0_SEGCTL0 $5, 2
  50 #define CP0_SEGCTL1 $5, 3
  51 #define CP0_SEGCTL2 $5, 4
  52 #define CP0_WIRED $6
  53 #define CP0_INFO $7
  54 #define CP0_HWRENA $7
  55 #define CP0_BADVADDR $8
  56 #define CP0_BADINSTR $8, 1
  57 #define CP0_COUNT $9
  58 #define CP0_ENTRYHI $10
  59 #define CP0_GUESTCTL1 $10, 4
  60 #define CP0_GUESTCTL2 $10, 5
  61 #define CP0_GUESTCTL3 $10, 6
  62 #define CP0_COMPARE $11
  63 #define CP0_GUESTCTL0EXT $11, 4
  64 #define CP0_STATUS $12
  65 #define CP0_GUESTCTL0 $12, 6
  66 #define CP0_GTOFFSET $12, 7
  67 #define CP0_CAUSE $13
  68 #define CP0_EPC $14
  69 #define CP0_PRID $15
  70 #define CP0_EBASE $15, 1
  71 #define CP0_CMGCRBASE $15, 3
  72 #define CP0_CONFIG $16
  73 #define CP0_CONFIG3 $16, 3
  74 #define CP0_CONFIG5 $16, 5
  75 #define CP0_CONFIG6 $16, 6
  76 #define CP0_LLADDR $17
  77 #define CP0_WATCHLO $18
  78 #define CP0_WATCHHI $19
  79 #define CP0_XCONTEXT $20
  80 #define CP0_FRAMEMASK $21
  81 #define CP0_DIAGNOSTIC $22
  82 #define CP0_DEBUG $23
  83 #define CP0_DEPC $24
  84 #define CP0_PERFORMANCE $25
  85 #define CP0_ECC $26
  86 #define CP0_CACHEERR $27
  87 #define CP0_TAGLO $28
  88 #define CP0_TAGHI $29
  89 #define CP0_ERROREPC $30
  90 #define CP0_DESAVE $31
  91
  92 /*
  93  * R4640/R4650 cp0 register names.  These registers are listed
  94  * here only for completeness; without MMU these CPUs are not useable
  95  * by Linux.  A future ELKS port might take make Linux run on them
  96  * though ...
  97  */
  98 #define CP0_IBASE $0
  99 #define CP0_IBOUND $1
 100 #define CP0_DBASE $2
 101 #define CP0_DBOUND $3
 102 #define CP0_CALG $17
 103 #define CP0_IWATCH $18
 104 #define CP0_DWATCH $19
 105
 106 /*
 107  * Coprocessor 0 Set 1 register names
 108  */
 109 #define CP0_S1_DERRADDR0  $26
 110 #define CP0_S1_DERRADDR1  $27
 111 #define CP0_S1_INTCONTROL $20
 112
 113 /*
 114  * Coprocessor 0 Set 2 register names
 115  */
 116 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 117
 118 /*
 119  * Coprocessor 0 Set 3 register names
 120  */
 121 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 122
 123 /*
 124  *  TX39 Series
 125  */
 126 #define CP0_TX39_CACHE  $7
 127
 128
 129 /* Generic EntryLo bit definitions */
 130 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 131 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 132 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 133 #define ENTRYLO_C_SHIFT         3
 134 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 135
 136 /* R3000 EntryLo bit definitions */
 137 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 138 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 139 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 140 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 141
 142 /* MIPS32/64 EntryLo bit definitions */
 143 #define MIPS_ENTRYLO_PFN_SHIFT  6
 144 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 145 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 146
 147 /*
 148  * MIPSr6+ GlobalNumber register definitions
 149  */
 150 #define MIPS_GLOBALNUMBER_VP_SHF        0
 151 #define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 152 #define MIPS_GLOBALNUMBER_CORE_SHF      8
 153 #define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 154 #define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
 155 #define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 156
 157 /*
 158  * Values for PageMask register
 159  */
 160 #ifdef CONFIG_CPU_VR41XX
 161
 162 /* Why doesn't stupidity hurt ... */
 163
 164 #define PM_1K           0x00000000
 165 #define PM_4K           0x00001800
 166 #define PM_16K          0x00007800
 167 #define PM_64K          0x0001f800
 168 #define PM_256K         0x0007f800
 169
 170 #else
 171
 172 #define PM_4K           0x00000000
 173 #define PM_8K           0x00002000
 174 #define PM_16K          0x00006000
 175 #define PM_32K          0x0000e000
 176 #define PM_64K          0x0001e000
 177 #define PM_128K         0x0003e000
 178 #define PM_256K         0x0007e000
 179 #define PM_512K         0x000fe000
 180 #define PM_1M           0x001fe000
 181 #define PM_2M           0x003fe000
 182 #define PM_4M           0x007fe000
 183 #define PM_8M           0x00ffe000
 184 #define PM_16M          0x01ffe000
 185 #define PM_32M          0x03ffe000
 186 #define PM_64M          0x07ffe000
 187 #define PM_256M         0x1fffe000
 188 #define PM_1G           0x7fffe000
 189
 190 #endif
 191
 192 /*
 193  * Values used for computation of new tlb entries
 194  */
 195 #define PL_4K           12
 196 #define PL_16K          14
 197 #define PL_64K          16
 198 #define PL_256K         18
 199 #define PL_1M           20
 200 #define PL_4M           22
 201 #define PL_16M          24
 202 #define PL_64M          26
 203 #define PL_256M         28
 204
 205 /*
 206  * PageGrain bits
 207  */
 208 #define PG_RIE          (_ULCAST_(1) <<  31)
 209 #define PG_XIE          (_ULCAST_(1) <<  30)
 210 #define PG_ELPA         (_ULCAST_(1) <<  29)
 211 #define PG_ESP          (_ULCAST_(1) <<  28)
 212 #define PG_IEC          (_ULCAST_(1) <<  27)
 213
 214 /* MIPS32/64 EntryHI bit definitions */
 215 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 216 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 217 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 218
 219 /*
 220  * R4x00 interrupt enable / cause bits
 221  */
 222 #define IE_SW0          (_ULCAST_(1) <<  8)
 223 #define IE_SW1          (_ULCAST_(1) <<  9)
 224 #define IE_IRQ0         (_ULCAST_(1) << 10)
 225 #define IE_IRQ1         (_ULCAST_(1) << 11)
 226 #define IE_IRQ2         (_ULCAST_(1) << 12)
 227 #define IE_IRQ3         (_ULCAST_(1) << 13)
 228 #define IE_IRQ4         (_ULCAST_(1) << 14)
 229 #define IE_IRQ5         (_ULCAST_(1) << 15)
 230
 231 /*
 232  * R4x00 interrupt cause bits
 233  */
 234 #define C_SW0           (_ULCAST_(1) <<  8)
 235 #define C_SW1           (_ULCAST_(1) <<  9)
 236 #define C_IRQ0          (_ULCAST_(1) << 10)
 237 #define C_IRQ1          (_ULCAST_(1) << 11)
 238 #define C_IRQ2          (_ULCAST_(1) << 12)
 239 #define C_IRQ3          (_ULCAST_(1) << 13)
 240 #define C_IRQ4          (_ULCAST_(1) << 14)
 241 #define C_IRQ5          (_ULCAST_(1) << 15)
 242
 243 /*
 244  * Bitfields in the R4xx0 cp0 status register
 245  */
 246 #define ST0_IE                  0x00000001
 247 #define ST0_EXL                 0x00000002
 248 #define ST0_ERL                 0x00000004
 249 #define ST0_KSU                 0x00000018
 250 #  define KSU_USER              0x00000010
 251 #  define KSU_SUPERVISOR        0x00000008
 252 #  define KSU_KERNEL            0x00000000
 253 #define ST0_UX                  0x00000020
 254 #define ST0_SX                  0x00000040
 255 #define ST0_KX                  0x00000080
 256 #define ST0_DE                  0x00010000
 257 #define ST0_CE                  0x00020000
 258
 259 /*
 260  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 261  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 262  * processors.
 263  */
 264 #define ST0_CO                  0x08000000
 265
 266 /*
 267  * Bitfields in the R[23]000 cp0 status register.
 268  */
 269 #define ST0_IEC                 0x00000001
 270 #define ST0_KUC                 0x00000002
 271 #define ST0_IEP                 0x00000004
 272 #define ST0_KUP                 0x00000008
 273 #define ST0_IEO                 0x00000010
 274 #define ST0_KUO                 0x00000020
 275 /* bits 6 & 7 are reserved on R[23]000 */
 276 #define ST0_ISC                 0x00010000
 277 #define ST0_SWC                 0x00020000
 278 #define ST0_CM                  0x00080000
 279
 280 /*
 281  * Bits specific to the R4640/R4650
 282  */
 283 #define ST0_UM                  (_ULCAST_(1) <<  4)
 284 #define ST0_IL                  (_ULCAST_(1) << 23)
 285 #define ST0_DL                  (_ULCAST_(1) << 24)
 286
 287 /*
 288  * Enable the MIPS MDMX and DSP ASEs
 289  */
 290 #define ST0_MX                  0x01000000
 291
 292 /*
 293  * Status register bits available in all MIPS CPUs.
 294  */
 295 #define ST0_IM                  0x0000ff00
 296 #define  STATUSB_IP0            8
 297 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 298 #define  STATUSB_IP1            9
 299 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 300 #define  STATUSB_IP2            10
 301 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 302 #define  STATUSB_IP3            11
 303 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 304 #define  STATUSB_IP4            12
 305 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 306 #define  STATUSB_IP5            13
 307 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 308 #define  STATUSB_IP6            14
 309 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 310 #define  STATUSB_IP7            15
 311 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 312 #define  STATUSB_IP8            0
 313 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 314 #define  STATUSB_IP9            1
 315 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 316 #define  STATUSB_IP10           2
 317 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 318 #define  STATUSB_IP11           3
 319 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 320 #define  STATUSB_IP12           4
 321 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 322 #define  STATUSB_IP13           5
 323 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 324 #define  STATUSB_IP14           6
 325 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 326 #define  STATUSB_IP15           7
 327 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 328 #define ST0_IMPL                (_ULCAST_(3) <<  16)
 329 #define ST0_CH                  0x00040000
 330 #define ST0_NMI                 0x00080000
 331 #define ST0_SR                  0x00100000
 332 #define ST0_TS                  0x00200000
 333 #define ST0_BEV                 0x00400000
 334 #define ST0_RE                  0x02000000
 335 #define ST0_FR                  0x04000000
 336 #define ST0_CU                  0xf0000000
 337 #define ST0_CU0                 0x10000000
 338 #define ST0_CU1                 0x20000000
 339 #define ST0_CU2                 0x40000000
 340 #define ST0_CU3                 0x80000000
 341 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 342
 343 /*
 344  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 345  */
 346 #define INTCTLB_IPFDC           23
 347 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 348 #define INTCTLB_IPPCI           26
 349 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 350 #define INTCTLB_IPTI            29
 351 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 352
 353 /*
 354  * Bitfields and bit numbers in the coprocessor 0 cause register.
 355  *
 356  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 357  */
 358 #define CAUSEB_EXCCODE          2
 359 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 360 #define CAUSEB_IP               8
 361 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 362 #define  CAUSEB_IP0             8
 363 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 364 #define  CAUSEB_IP1             9
 365 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 366 #define  CAUSEB_IP2             10
 367 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 368 #define  CAUSEB_IP3             11
 369 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 370 #define  CAUSEB_IP4             12
 371 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 372 #define  CAUSEB_IP5             13
 373 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 374 #define  CAUSEB_IP6             14
 375 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 376 #define  CAUSEB_IP7             15
 377 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 378 #define CAUSEB_FDCI             21
 379 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 380 #define CAUSEB_WP               22
 381 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 382 #define CAUSEB_IV               23
 383 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 384 #define CAUSEB_PCI              26
 385 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 386 #define CAUSEB_DC               27
 387 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 388 #define CAUSEB_CE               28
 389 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 390 #define CAUSEB_TI               30
 391 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 392 #define CAUSEB_BD               31
 393 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 394
 395 /*
 396  * Cause.ExcCode trap codes.
 397  */
 398 #define EXCCODE_INT             0       /* Interrupt pending */
 399 #define EXCCODE_MOD             1       /* TLB modified fault */
 400 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 401 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 402 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 403 #define EXCCODE_ADES            5       /* Address error on a store */
 404 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 405 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 406 #define EXCCODE_SYS             8       /* System call */
 407 #define EXCCODE_BP              9       /* Breakpoint */
 408 #define EXCCODE_RI              10      /* Reserved instruction exception */
 409 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 410 #define EXCCODE_OV              12      /* Arithmetic overflow */
 411 #define EXCCODE_TR              13      /* Trap instruction */
 412 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 413 #define EXCCODE_FPE             15      /* Floating point exception */
 414 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 415 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 416 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 417 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 418 #define EXCCODE_WATCH           23      /* Watch address reference */
 419 #define EXCCODE_MCHECK          24      /* Machine check */
 420 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 421 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 422 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 423
 424 /* Implementation specific trap codes used by MIPS cores */
 425 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 426
 427 /*
 428  * Bits in the coprocessor 0 config register.
 429  */
 430 /* Generic bits.  */
 431 #define CONF_CM_CACHABLE_NO_WA          0
 432 #define CONF_CM_CACHABLE_WA             1
 433 #define CONF_CM_UNCACHED                2
 434 #define CONF_CM_CACHABLE_NONCOHERENT    3
 435 #define CONF_CM_CACHABLE_CE             4
 436 #define CONF_CM_CACHABLE_COW            5
 437 #define CONF_CM_CACHABLE_CUW            6
 438 #define CONF_CM_CACHABLE_ACCELERATED    7
 439 #define CONF_CM_CMASK                   7
 440 #define CONF_BE                 (_ULCAST_(1) << 15)
 441
 442 /* Bits common to various processors.  */
 443 #define CONF_CU                 (_ULCAST_(1) <<  3)
 444 #define CONF_DB                 (_ULCAST_(1) <<  4)
 445 #define CONF_IB                 (_ULCAST_(1) <<  5)
 446 #define CONF_DC                 (_ULCAST_(7) <<  6)
 447 #define CONF_IC                 (_ULCAST_(7) <<  9)
 448 #define CONF_EB                 (_ULCAST_(1) << 13)
 449 #define CONF_EM                 (_ULCAST_(1) << 14)
 450 #define CONF_SM                 (_ULCAST_(1) << 16)
 451 #define CONF_SC                 (_ULCAST_(1) << 17)
 452 #define CONF_EW                 (_ULCAST_(3) << 18)
 453 #define CONF_EP                 (_ULCAST_(15)<< 24)
 454 #define CONF_EC                 (_ULCAST_(7) << 28)
 455 #define CONF_CM                 (_ULCAST_(1) << 31)
 456
 457 /* Bits specific to the R4xx0.  */
 458 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 459 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 460 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 461
 462 /* Bits specific to the R5000.  */
 463 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 464 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 465
 466 /* Bits specific to the RM7000.  */
 467 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 468 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 469 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 470 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 471 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 472 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 473
 474 /* Bits specific to the R10000.  */
 475 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 476 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 477 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 478 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 479 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 480 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 481 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 482 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 483 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 484 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 485 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 486
 487 /* Bits specific to the VR41xx.  */
 488 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 489 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 490 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 491 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 492 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 493
 494 /* Bits specific to the R30xx.  */
 495 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 496 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 497 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 498 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 499 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 500 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 501 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 502 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 503 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 504
 505 /* Bits specific to the TX49.  */
 506 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 507 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 508 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 509 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 510
 511 /* Bits specific to the MIPS32/64 PRA.  */
 512 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 513 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 514 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 515 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 516 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 517 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 518 #define MIPS_CONF_IMPL          (_ULCAST_(0x1ff) << 16)
 519 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 520
 521 /*
 522  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 523  */
 524 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 525 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 526 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 527 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 528 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 529 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 530 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 531 #define MIPS_CONF1_DA_SHF       7
 532 #define MIPS_CONF1_DA_SZ        3
 533 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 534 #define MIPS_CONF1_DL_SHF       10
 535 #define MIPS_CONF1_DL_SZ        3
 536 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 537 #define MIPS_CONF1_DS_SHF       13
 538 #define MIPS_CONF1_DS_SZ        3
 539 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 540 #define MIPS_CONF1_IA_SHF       16
 541 #define MIPS_CONF1_IA_SZ        3
 542 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 543 #define MIPS_CONF1_IL_SHF       19
 544 #define MIPS_CONF1_IL_SZ        3
 545 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 546 #define MIPS_CONF1_IS_SHF       22
 547 #define MIPS_CONF1_IS_SZ        3
 548 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 549 #define MIPS_CONF1_TLBS_SHIFT   (25)
 550 #define MIPS_CONF1_TLBS_SIZE    (6)
 551 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 552
 553 #define MIPS_CONF2_SA_SHF       0
 554 #define MIPS_CONF2_SA           (_ULCAST_(15) << 0)
 555 #define MIPS_CONF2_SL_SHF       4
 556 #define MIPS_CONF2_SL           (_ULCAST_(15) << 4)
 557 #define MIPS_CONF2_SS_SHF       8
 558 #define MIPS_CONF2_SS           (_ULCAST_(15) << 8)
 559 #define MIPS_CONF2_L2B          (_ULCAST_(1) << 12)
 560 #define MIPS_CONF2_SU           (_ULCAST_(15) << 12)
 561 #define MIPS_CONF2_TA           (_ULCAST_(15) << 16)
 562 #define MIPS_CONF2_TL           (_ULCAST_(15) << 20)
 563 #define MIPS_CONF2_TS           (_ULCAST_(15) << 24)
 564 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 565
 566 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 567 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 568 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 569 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 570 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 571 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 572 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 573 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 574 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 575 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 576 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 577 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 578 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 579 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 580 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 581 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 582 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 583 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 584 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 585 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 586 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 587 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 588 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 589 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 590 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 591 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 592 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 593
 594 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 595 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 596 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 597 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 598 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 599 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 600 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 601 /* bits 10:8 in FTLB-only configurations */
 602 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 603 /* bits 12:8 in VTLB-FTLB only configurations */
 604 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 605 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 606 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 607 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 608 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 609 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 610 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 611 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 612 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 613 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 614 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 615 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 616
 617 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 618 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 619 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 620 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 621 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 622 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 623 #define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
 624 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 625 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 626 #define MIPS_CONF5_L2C          (_ULCAST_(1) << 10)
 627 #define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
 628 #define MIPS_CONF5_MI           (_ULCAST_(1) << 17)
 629 #define MIPS_CONF5_CRCP         (_ULCAST_(1) << 18)
 630 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 631 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 632 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 633 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 634
 635 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 636 /* proAptiv FTLB on/off bit */
 637 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 638 /* Loongson-3 FTLB on/off bit */
 639 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 640 /* FTLB probability bits */
 641 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 642
 643 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 644
 645 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 646
 647 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 648 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 649
 650 /* Ingenic HPTLB off bits */
 651 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
 652
 653 /* Ingenic Config7 bits */
 654 #define MIPS_CONF7_BTB_LOOP_EN  (_ULCAST_(1) << 4)
 655
 656 /* Config7 Bits specific to MIPS Technologies. */
 657
 658 /* Performance counters implemented Per TC */
 659 #define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
 660
 661 /* WatchLo* register definitions */
 662 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 663
 664 /* WatchHi* register definitions */
 665 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 666 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 667 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 668 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 669 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 670 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 671 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 672 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 673 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 674 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 675 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 676 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 677 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 678
 679 /* PerfCnt control register definitions */
 680 #define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
 681 #define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
 682 #define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
 683 #define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
 684 #define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
 685 #define MIPS_PERFCTRL_EVENT_S   5
 686 #define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 687 #define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
 688 #define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
 689 #define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
 690 #define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
 691 #define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
 692 #define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
 693 #define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
 694 #define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
 695
 696 /* PerfCnt control register MT extensions used by MIPS cores */
 697 #define MIPS_PERFCTRL_VPEID_S   16
 698 #define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 699 #define MIPS_PERFCTRL_TCID_S    22
 700 #define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 701 #define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
 702 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
 703 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
 704 #define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
 705
 706 /* PerfCnt control register MT extensions used by BMIPS5000 */
 707 #define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
 708
 709 /* PerfCnt control register MT extensions used by Netlogic XLR */
 710 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
 711
 712 /* MAAR bit definitions */
 713 #define MIPS_MAAR_VH            (_U64CAST_(1) << 63)
 714 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 715 #define MIPS_MAAR_ADDR_SHIFT    12
 716 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 717 #define MIPS_MAAR_VL            (_ULCAST_(1) << 0)
 718
 719 /* MAARI bit definitions */
 720 #define MIPS_MAARI_INDEX        (_ULCAST_(0x3f) << 0)
 721
 722 /* EBase bit definitions */
 723 #define MIPS_EBASE_CPUNUM_SHIFT 0
 724 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 725 #define MIPS_EBASE_WG_SHIFT     11
 726 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 727 #define MIPS_EBASE_BASE_SHIFT   12
 728 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 729
 730 /* CMGCRBase bit definitions */
 731 #define MIPS_CMGCRB_BASE        11
 732 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 733
 734 /* LLAddr bit definitions */
 735 #define MIPS_LLADDR_LLB_SHIFT   0
 736 #define MIPS_LLADDR_LLB         (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 737
 738 /*
 739  * Bits in the MIPS32 Memory Segmentation registers.
 740  */
 741 #define MIPS_SEGCFG_PA_SHIFT    9
 742 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 743 #define MIPS_SEGCFG_AM_SHIFT    4
 744 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 745 #define MIPS_SEGCFG_EU_SHIFT    3
 746 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 747 #define MIPS_SEGCFG_C_SHIFT     0
 748 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 749
 750 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 751 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 752 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 753 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 754 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 755 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 756 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 757
 758 #define MIPS_PWFIELD_GDI_SHIFT  24
 759 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 760 #define MIPS_PWFIELD_UDI_SHIFT  18
 761 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 762 #define MIPS_PWFIELD_MDI_SHIFT  12
 763 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 764 #define MIPS_PWFIELD_PTI_SHIFT  6
 765 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 766 #define MIPS_PWFIELD_PTEI_SHIFT 0
 767 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 768
 769 #define MIPS_PWSIZE_PS_SHIFT    30
 770 #define MIPS_PWSIZE_PS_MASK     0x40000000
 771 #define MIPS_PWSIZE_GDW_SHIFT   24
 772 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 773 #define MIPS_PWSIZE_UDW_SHIFT   18
 774 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 775 #define MIPS_PWSIZE_MDW_SHIFT   12
 776 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 777 #define MIPS_PWSIZE_PTW_SHIFT   6
 778 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 779 #define MIPS_PWSIZE_PTEW_SHIFT  0
 780 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 781
 782 #define MIPS_PWCTL_PWEN_SHIFT   31
 783 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 784 #define MIPS_PWCTL_XK_SHIFT     28
 785 #define MIPS_PWCTL_XK_MASK      0x10000000
 786 #define MIPS_PWCTL_XS_SHIFT     27
 787 #define MIPS_PWCTL_XS_MASK      0x08000000
 788 #define MIPS_PWCTL_XU_SHIFT     26
 789 #define MIPS_PWCTL_XU_MASK      0x04000000
 790 #define MIPS_PWCTL_DPH_SHIFT    7
 791 #define MIPS_PWCTL_DPH_MASK     0x00000080
 792 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 793 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 794 #define MIPS_PWCTL_PSN_SHIFT    0
 795 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 796
 797 /* GuestCtl0 fields */
 798 #define MIPS_GCTL0_GM_SHIFT     31
 799 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 800 #define MIPS_GCTL0_RI_SHIFT     30
 801 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 802 #define MIPS_GCTL0_MC_SHIFT     29
 803 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 804 #define MIPS_GCTL0_CP0_SHIFT    28
 805 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 806 #define MIPS_GCTL0_AT_SHIFT     26
 807 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 808 #define MIPS_GCTL0_GT_SHIFT     25
 809 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 810 #define MIPS_GCTL0_CG_SHIFT     24
 811 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 812 #define MIPS_GCTL0_CF_SHIFT     23
 813 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 814 #define MIPS_GCTL0_G1_SHIFT     22
 815 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 816 #define MIPS_GCTL0_G0E_SHIFT    19
 817 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 818 #define MIPS_GCTL0_PT_SHIFT     18
 819 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 820 #define MIPS_GCTL0_RAD_SHIFT    9
 821 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 822 #define MIPS_GCTL0_DRG_SHIFT    8
 823 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 824 #define MIPS_GCTL0_G2_SHIFT     7
 825 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 826 #define MIPS_GCTL0_GEXC_SHIFT   2
 827 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 828 #define MIPS_GCTL0_SFC2_SHIFT   1
 829 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 830 #define MIPS_GCTL0_SFC1_SHIFT   0
 831 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 832
 833 /* GuestCtl0.AT Guest address translation control */
 834 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 835 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 836
 837 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 838 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 839 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 840 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 841 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 842 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 843 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 844 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 845
 846 /* GuestCtl0Ext fields */
 847 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 848 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 849 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 850 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 851 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 852 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 853 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 854 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 855 #define MIPS_GCTL0EXT_OG_SHIFT  2
 856 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 857 #define MIPS_GCTL0EXT_BG_SHIFT  1
 858 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 859 #define MIPS_GCTL0EXT_MG_SHIFT  0
 860 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 861
 862 /* GuestCtl0Ext.RPW Root page walk configuration */
 863 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 864 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 865 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 866
 867 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 868 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 869 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 870
 871 /* GuestCtl1 fields */
 872 #define MIPS_GCTL1_ID_SHIFT     0
 873 #define MIPS_GCTL1_ID_WIDTH     8
 874 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 875 #define MIPS_GCTL1_RID_SHIFT    16
 876 #define MIPS_GCTL1_RID_WIDTH    8
 877 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 878 #define MIPS_GCTL1_EID_SHIFT    24
 879 #define MIPS_GCTL1_EID_WIDTH    8
 880 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 881
 882 /* GuestID reserved for root context */
 883 #define MIPS_GCTL1_ROOT_GUESTID 0
 884
 885 /* CDMMBase register bit definitions */
 886 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 887 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 888 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 889 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 890 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 891 #define MIPS_CDMMBASE_ADDR_START 15
 892
 893 /* RDHWR register numbers */
 894 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 895 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 896 #define MIPS_HWR_CC             2       /* Cycle counter */
 897 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 898 #define MIPS_HWR_ULR            29      /* UserLocal */
 899 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 900 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 901
 902 /* Bits in HWREna register */
 903 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 904 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 905 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 906 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 907 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 908 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 909 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 910
 911 /*
 912  * Bitfields in the TX39 family CP0 Configuration Register 3
 913  */
 914 #define TX39_CONF_ICS_SHIFT     19
 915 #define TX39_CONF_ICS_MASK      0x00380000
 916 #define TX39_CONF_ICS_1KB       0x00000000
 917 #define TX39_CONF_ICS_2KB       0x00080000
 918 #define TX39_CONF_ICS_4KB       0x00100000
 919 #define TX39_CONF_ICS_8KB       0x00180000
 920 #define TX39_CONF_ICS_16KB      0x00200000
 921
 922 #define TX39_CONF_DCS_SHIFT     16
 923 #define TX39_CONF_DCS_MASK      0x00070000
 924 #define TX39_CONF_DCS_1KB       0x00000000
 925 #define TX39_CONF_DCS_2KB       0x00010000
 926 #define TX39_CONF_DCS_4KB       0x00020000
 927 #define TX39_CONF_DCS_8KB       0x00030000
 928 #define TX39_CONF_DCS_16KB      0x00040000
 929
 930 #define TX39_CONF_CWFON         0x00004000
 931 #define TX39_CONF_WBON          0x00002000
 932 #define TX39_CONF_RF_SHIFT      10
 933 #define TX39_CONF_RF_MASK       0x00000c00
 934 #define TX39_CONF_DOZE          0x00000200
 935 #define TX39_CONF_HALT          0x00000100
 936 #define TX39_CONF_LOCK          0x00000080
 937 #define TX39_CONF_ICE           0x00000020
 938 #define TX39_CONF_DCE           0x00000010
 939 #define TX39_CONF_IRSIZE_SHIFT  2
 940 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 941 #define TX39_CONF_DRSIZE_SHIFT  0
 942 #define TX39_CONF_DRSIZE_MASK   0x00000003
 943
 944 /*
 945  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 946  */
 947 /* Disable Branch Target Address Cache */
 948 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 949 /* Enable Branch Prediction Global History */
 950 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 951 /* Disable Branch Return Cache */
 952 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 953
 954 /* Flush ITLB */
 955 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 956 /* Flush DTLB */
 957 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 958 /* Flush VTLB */
 959 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 960 /* Flush FTLB */
 961 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 962
 963 /* CvmCtl register field definitions */
 964 #define CVMCTL_IPPCI_SHIFT      7
 965 #define CVMCTL_IPPCI            (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
 966 #define CVMCTL_IPTI_SHIFT       4
 967 #define CVMCTL_IPTI             (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
 968
 969 /* CvmMemCtl2 register field definitions */
 970 #define CVMMEMCTL2_INHIBITTS    (_U64CAST_(1) << 17)
 971
 972 /* CvmVMConfig register field definitions */
 973 #define CVMVMCONF_DGHT          (_U64CAST_(1) << 60)
 974 #define CVMVMCONF_MMUSIZEM1_S   12
 975 #define CVMVMCONF_MMUSIZEM1     (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
 976 #define CVMVMCONF_RMMUSIZEM1_S  0
 977 #define CVMVMCONF_RMMUSIZEM1    (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
 978
 979 /*
 980  * Coprocessor 1 (FPU) register names
 981  */
 982 #define CP1_REVISION    $0
 983 #define CP1_UFR         $1
 984 #define CP1_UNFR        $4
 985 #define CP1_FCCR        $25
 986 #define CP1_FEXR        $26
 987 #define CP1_FENR        $28
 988 #define CP1_STATUS      $31
 989
 990
 991 /*
 992  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 993  */
 994 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 995 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 996 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 997 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 998 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 999 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
1000 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
1001 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
1002 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
1003 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
1004
1005 /*
1006  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1007  */
1008 #define MIPS_FCCR_CONDX_S       0
1009 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1010 #define MIPS_FCCR_COND0_S       0
1011 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1012 #define MIPS_FCCR_COND1_S       1
1013 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1014 #define MIPS_FCCR_COND2_S       2
1015 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1016 #define MIPS_FCCR_COND3_S       3
1017 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1018 #define MIPS_FCCR_COND4_S       4
1019 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1020 #define MIPS_FCCR_COND5_S       5
1021 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1022 #define MIPS_FCCR_COND6_S       6
1023 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1024 #define MIPS_FCCR_COND7_S       7
1025 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1026
1027 /*
1028  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1029  */
1030 #define MIPS_FENR_FS_S          2
1031 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
1032
1033 /*
1034  * FPU Status Register Values
1035  */
1036 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
1037 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
1038
1039 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
1040 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
1041
1042 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
1043 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
1044 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
1045 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
1046 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
1047 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
1048 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
1049 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
1050 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
1051 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1052 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1053 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1054 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1055 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1056 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1057 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1058
1059 /*
1060  * Bits 22:20 of the FPU Status Register will be read as 0,
1061  * and should be written as zero.
1062  * MAC2008 was removed in Release 5 so we still treat it as
1063  * reserved.
1064  */
1065 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1066
1067 #define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1068 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1069 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1070
1071 /*
1072  * X the exception cause indicator
1073  * E the exception enable
1074  * S the sticky/flag bit
1075 */
1076 #define FPU_CSR_ALL_X   0x0003f000
1077 #define FPU_CSR_UNI_X   0x00020000
1078 #define FPU_CSR_INV_X   0x00010000
1079 #define FPU_CSR_DIV_X   0x00008000
1080 #define FPU_CSR_OVF_X   0x00004000
1081 #define FPU_CSR_UDF_X   0x00002000
1082 #define FPU_CSR_INE_X   0x00001000
1083
1084 #define FPU_CSR_ALL_E   0x00000f80
1085 #define FPU_CSR_INV_E   0x00000800
1086 #define FPU_CSR_DIV_E   0x00000400
1087 #define FPU_CSR_OVF_E   0x00000200
1088 #define FPU_CSR_UDF_E   0x00000100
1089 #define FPU_CSR_INE_E   0x00000080
1090
1091 #define FPU_CSR_ALL_S   0x0000007c
1092 #define FPU_CSR_INV_S   0x00000040
1093 #define FPU_CSR_DIV_S   0x00000020
1094 #define FPU_CSR_OVF_S   0x00000010
1095 #define FPU_CSR_UDF_S   0x00000008
1096 #define FPU_CSR_INE_S   0x00000004
1097
1098 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1099 #define FPU_CSR_RM      0x00000003
1100 #define FPU_CSR_RN      0x0     /* nearest */
1101 #define FPU_CSR_RZ      0x1     /* towards zero */
1102 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1103 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1104
1105
1106 #ifndef __ASSEMBLY__
1107
1108 /*
1109  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1110  */
1111 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1112     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1113 #define get_isa16_mode(x)               ((x) & 0x1)
1114 #define msk_isa16_mode(x)               ((x) & ~0x1)
1115 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1116 #else
1117 #define get_isa16_mode(x)               0
1118 #define msk_isa16_mode(x)               (x)
1119 #define set_isa16_mode(x)               do { } while(0)
1120 #endif
1121
1122 /*
1123  * microMIPS instructions can be 16-bit or 32-bit in length. This
1124  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1125  */
1126 static inline int mm_insn_16bit(u16 insn)
1127 {
1128         u16 opcode = (insn >> 10) & 0x7;
1129
1130         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1131 }
1132
1133 /*
1134  * Helper macros for generating raw instruction encodings in inline asm.
1135  */
1136 #ifdef CONFIG_CPU_MICROMIPS
1137 #define _ASM_INSN16_IF_MM(_enc)                 \
1138         ".insn\n\t"                             \
1139         ".hword (" #_enc ")\n\t"
1140 #define _ASM_INSN32_IF_MM(_enc)                 \
1141         ".insn\n\t"                             \
1142         ".hword ((" #_enc ") >> 16)\n\t"        \
1143         ".hword ((" #_enc ") & 0xffff)\n\t"
1144 #else
1145 #define _ASM_INSN_IF_MIPS(_enc)                 \
1146         ".insn\n\t"                             \
1147         ".word (" #_enc ")\n\t"
1148 #endif
1149
1150 #ifndef _ASM_INSN16_IF_MM
1151 #define _ASM_INSN16_IF_MM(_enc)
1152 #endif
1153 #ifndef _ASM_INSN32_IF_MM
1154 #define _ASM_INSN32_IF_MM(_enc)
1155 #endif
1156 #ifndef _ASM_INSN_IF_MIPS
1157 #define _ASM_INSN_IF_MIPS(_enc)
1158 #endif
1159
1160 /*
1161  * parse_r var, r - Helper assembler macro for parsing register names.
1162  *
1163  * This converts the register name in $n form provided in \r to the
1164  * corresponding register number, which is assigned to the variable \var. It is
1165  * needed to allow explicit encoding of instructions in inline assembly where
1166  * registers are chosen by the compiler in $n form, allowing us to avoid using
1167  * fixed register numbers.
1168  *
1169  * It also allows newer instructions (not implemented by the assembler) to be
1170  * transparently implemented using assembler macros, instead of needing separate
1171  * cases depending on toolchain support.
1172  *
1173  * Simple usage example:
1174  * __asm__ __volatile__("parse_r __rt, %0\n\t"
1175  *                      ".insn\n\t"
1176  *                      "# di    %0\n\t"
1177  *                      ".word   (0x41606000 | (__rt << 16))"
1178  *                      : "=r" (status);
1179  */
1180
1181 /* Match an individual register number and assign to \var */
1182 #define _IFC_REG(n)                             \
1183         ".ifc   \\r, $" #n "\n\t"               \
1184         "\\var  = " #n "\n\t"                   \
1185         ".endif\n\t"
1186
1187 __asm__(".macro parse_r var r\n\t"
1188         "\\var  = -1\n\t"
1189         _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
1190         _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
1191         _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
1192         _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1193         _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1194         _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1195         _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1196         _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1197         ".iflt  \\var\n\t"
1198         ".error \"Unable to parse register name \\r\"\n\t"
1199         ".endif\n\t"
1200         ".endm");
1201
1202 #undef _IFC_REG
1203
1204 /*
1205  * C macros for generating assembler macros for common instruction formats.
1206  *
1207  * The names of the operands can be chosen by the caller, and the encoding of
1208  * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1209  * the ENC encodings.
1210  */
1211
1212 /* Instructions with no operands */
1213 #define _ASM_MACRO_0(OP, ENC)                                           \
1214         __asm__(".macro " #OP "\n\t"                                    \
1215                 ENC                                                     \
1216                 ".endm")
1217
1218 /* Instructions with 1 register operand & 1 immediate operand */
1219 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC)                                \
1220         __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t"                   \
1221                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1222                 ENC                                                     \
1223                 ".endm")
1224
1225 /* Instructions with 2 register operands */
1226 #define _ASM_MACRO_2R(OP, R1, R2, ENC)                                  \
1227         __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t"                   \
1228                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1229                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1230                 ENC                                                     \
1231                 ".endm")
1232
1233 /* Instructions with 3 register operands */
1234 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)                              \
1235         __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t"          \
1236                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1237                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1238                 "parse_r __" #R3 ", \\" #R3 "\n\t"                      \
1239                 ENC                                                     \
1240                 ".endm")
1241
1242 /* Instructions with 2 register operands and 1 optional select operand */
1243 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)                         \
1244         __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"    \
1245                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1246                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1247                 ENC                                                     \
1248                 ".endm")
1249
1250 /*
1251  * TLB Invalidate Flush
1252  */
1253 static inline void tlbinvf(void)
1254 {
1255         __asm__ __volatile__(
1256                 ".set push\n\t"
1257                 ".set noreorder\n\t"
1258                 "# tlbinvf\n\t"
1259                 _ASM_INSN_IF_MIPS(0x42000004)
1260                 _ASM_INSN32_IF_MM(0x0000537c)
1261                 ".set pop");
1262 }
1263
1264
1265 /*
1266  * Functions to access the R10000 performance counters.  These are basically
1267  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1268  * performance counter number encoded into bits 1 ... 5 of the instruction.
1269  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1270  * disassembler these will look like an access to sel 0 or 1.
1271  */
1272 #define read_r10k_perf_cntr(counter)                            \
1273 ({                                                              \
1274         unsigned int __res;                                     \
1275         __asm__ __volatile__(                                   \
1276         "mfpc\t%0, %1"                                          \
1277         : "=r" (__res)                                          \
1278         : "i" (counter));                                       \
1279                                                                 \
1280         __res;                                                  \
1281 })
1282
1283 #define write_r10k_perf_cntr(counter,val)                       \
1284 do {                                                            \
1285         __asm__ __volatile__(                                   \
1286         "mtpc\t%0, %1"                                          \
1287         :                                                       \
1288         : "r" (val), "i" (counter));                            \
1289 } while (0)
1290
1291 #define read_r10k_perf_event(counter)                           \
1292 ({                                                              \
1293         unsigned int __res;                                     \
1294         __asm__ __volatile__(                                   \
1295         "mfps\t%0, %1"                                          \
1296         : "=r" (__res)                                          \
1297         : "i" (counter));                                       \
1298                                                                 \
1299         __res;                                                  \
1300 })
1301
1302 #define write_r10k_perf_cntl(counter,val)                       \
1303 do {                                                            \
1304         __asm__ __volatile__(                                   \
1305         "mtps\t%0, %1"                                          \
1306         :                                                       \
1307         : "r" (val), "i" (counter));                            \
1308 } while (0)
1309
1310
1311 /*
1312  * Macros to access the system control coprocessor
1313  */
1314
1315 #define ___read_32bit_c0_register(source, sel, vol)                     \
1316 ({ unsigned int __res;                                                  \
1317         if (sel == 0)                                                   \
1318                 __asm__ vol(                                            \
1319                         "mfc0\t%0, " #source "\n\t"                     \
1320                         : "=r" (__res));                                \
1321         else                                                            \
1322                 __asm__ vol(                                            \
1323                         ".set\tpush\n\t"                                \
1324                         ".set\tmips32\n\t"                              \
1325                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1326                         ".set\tpop\n\t"                                 \
1327                         : "=r" (__res));                                \
1328         __res;                                                          \
1329 })
1330
1331 #define ___read_64bit_c0_register(source, sel, vol)                     \
1332 ({ unsigned long long __res;                                            \
1333         if (sizeof(unsigned long) == 4)                                 \
1334                 __res = __read_64bit_c0_split(source, sel, vol);        \
1335         else if (sel == 0)                                              \
1336                 __asm__ vol(                                            \
1337                         ".set\tpush\n\t"                                \
1338                         ".set\tmips3\n\t"                               \
1339                         "dmfc0\t%0, " #source "\n\t"                    \
1340                         ".set\tpop"                                     \
1341                         : "=r" (__res));                                \
1342         else                                                            \
1343                 __asm__ vol(                                            \
1344                         ".set\tpush\n\t"                                \
1345                         ".set\tmips64\n\t"                              \
1346                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1347                         ".set\tpop"                                     \
1348                         : "=r" (__res));                                \
1349         __res;                                                          \
1350 })
1351
1352 #define __read_32bit_c0_register(source, sel)                           \
1353         ___read_32bit_c0_register(source, sel, __volatile__)
1354
1355 #define __read_const_32bit_c0_register(source, sel)                     \
1356         ___read_32bit_c0_register(source, sel,)
1357
1358 #define __read_64bit_c0_register(source, sel)                           \
1359         ___read_64bit_c0_register(source, sel, __volatile__)
1360
1361 #define __read_const_64bit_c0_register(source, sel)                     \
1362         ___read_64bit_c0_register(source, sel,)
1363
1364 #define __write_32bit_c0_register(register, sel, value)                 \
1365 do {                                                                    \
1366         if (sel == 0)                                                   \
1367                 __asm__ __volatile__(                                   \
1368                         "mtc0\t%z0, " #register "\n\t"                  \
1369                         : : "Jr" ((unsigned int)(value)));              \
1370         else                                                            \
1371                 __asm__ __volatile__(                                   \
1372                         ".set\tpush\n\t"                                \
1373                         ".set\tmips32\n\t"                              \
1374                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1375                         ".set\tpop"                                     \
1376                         : : "Jr" ((unsigned int)(value)));              \
1377 } while (0)
1378
1379 #define __write_64bit_c0_register(register, sel, value)                 \
1380 do {                                                                    \
1381         if (sizeof(unsigned long) == 4)                                 \
1382                 __write_64bit_c0_split(register, sel, value);           \
1383         else if (sel == 0)                                              \
1384                 __asm__ __volatile__(                                   \
1385                         ".set\tpush\n\t"                                \
1386                         ".set\tmips3\n\t"                               \
1387                         "dmtc0\t%z0, " #register "\n\t"                 \
1388                         ".set\tpop"                                     \
1389                         : : "Jr" (value));                              \
1390         else                                                            \
1391                 __asm__ __volatile__(                                   \
1392                         ".set\tpush\n\t"                                \
1393                         ".set\tmips64\n\t"                              \
1394                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1395                         ".set\tpop"                                     \
1396                         : : "Jr" (value));                              \
1397 } while (0)
1398
1399 #define __read_ulong_c0_register(reg, sel)                              \
1400         ((sizeof(unsigned long) == 4) ?                                 \
1401         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1402         (unsigned long) __read_64bit_c0_register(reg, sel))
1403
1404 #define __read_const_ulong_c0_register(reg, sel)                        \
1405         ((sizeof(unsigned long) == 4) ?                                 \
1406         (unsigned long) __read_const_32bit_c0_register(reg, sel) :      \
1407         (unsigned long) __read_const_64bit_c0_register(reg, sel))
1408
1409 #define __write_ulong_c0_register(reg, sel, val)                        \
1410 do {                                                                    \
1411         if (sizeof(unsigned long) == 4)                                 \
1412                 __write_32bit_c0_register(reg, sel, val);               \
1413         else                                                            \
1414                 __write_64bit_c0_register(reg, sel, val);               \
1415 } while (0)
1416
1417 /*
1418  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1419  */
1420 #define __read_32bit_c0_ctrl_register(source)                           \
1421 ({ unsigned int __res;                                                  \
1422         __asm__ __volatile__(                                           \
1423                 "cfc0\t%0, " #source "\n\t"                             \
1424                 : "=r" (__res));                                        \
1425         __res;                                                          \
1426 })
1427
1428 #define __write_32bit_c0_ctrl_register(register, value)                 \
1429 do {                                                                    \
1430         __asm__ __volatile__(                                           \
1431                 "ctc0\t%z0, " #register "\n\t"                          \
1432                 : : "Jr" ((unsigned int)(value)));                      \
1433 } while (0)
1434
1435 /*
1436  * These versions are only needed for systems with more than 38 bits of
1437  * physical address space running the 32-bit kernel.  That's none atm :-)
1438  */
1439 #define __read_64bit_c0_split(source, sel, vol)                         \
1440 ({                                                                      \
1441         unsigned long long __val;                                       \
1442                                                                         \
1443         if (sel == 0)                                                   \
1444                 __asm__ vol(                                            \
1445                         ".set\tpush\n\t"                                \
1446                         ".set\tmips64\n\t"                              \
1447                         "dmfc0\t%L0, " #source "\n\t"                   \
1448                         "dsra\t%M0, %L0, 32\n\t"                        \
1449                         "sll\t%L0, %L0, 0\n\t"                          \
1450                         ".set\tpop"                                     \
1451                         : "=r" (__val));                                \
1452         else                                                            \
1453                 __asm__ vol(                                            \
1454                         ".set\tpush\n\t"                                \
1455                         ".set\tmips64\n\t"                              \
1456                         "dmfc0\t%L0, " #source ", " #sel "\n\t"         \
1457                         "dsra\t%M0, %L0, 32\n\t"                        \
1458                         "sll\t%L0, %L0, 0\n\t"                          \
1459                         ".set\tpop"                                     \
1460                         : "=r" (__val));                                \
1461                                                                         \
1462         __val;                                                          \
1463 })
1464
1465 #define __write_64bit_c0_split(source, sel, val)                        \
1466 do {                                                                    \
1467         unsigned long long __tmp = (val);                               \
1468         if (MIPS_ISA_REV >= 2)                                          \
1469                 __asm__ __volatile__(                                   \
1470                         ".set\tpush\n\t"                                \
1471                         ".set\t" MIPS_ISA_LEVEL "\n\t"                  \
1472                         "dins\t%L0, %M0, 32, 32\n\t"                    \
1473                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1474                         ".set\tpop"                                     \
1475                         : "+r" (__tmp));                                \
1476         else if (sel == 0)                                              \
1477                 __asm__ __volatile__(                                   \
1478                         ".set\tpush\n\t"                                \
1479                         ".set\tmips64\n\t"                              \
1480                         "dsll\t%L0, %L0, 32\n\t"                        \
1481                         "dsrl\t%L0, %L0, 32\n\t"                        \
1482                         "dsll\t%M0, %M0, 32\n\t"                        \
1483                         "or\t%L0, %L0, %M0\n\t"                         \
1484                         "dmtc0\t%L0, " #source "\n\t"                   \
1485                         ".set\tpop"                                     \
1486                         : "+r" (__tmp));                                \
1487         else                                                            \
1488                 __asm__ __volatile__(                                   \
1489                         ".set\tpush\n\t"                                \
1490                         ".set\tmips64\n\t"                              \
1491                         "dsll\t%L0, %L0, 32\n\t"                        \
1492                         "dsrl\t%L0, %L0, 32\n\t"                        \
1493                         "dsll\t%M0, %M0, 32\n\t"                        \
1494                         "or\t%L0, %L0, %M0\n\t"                         \
1495                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1496                         ".set\tpop"                                     \
1497                         : "+r" (__tmp));                                \
1498 } while (0)
1499
1500 #ifndef TOOLCHAIN_SUPPORTS_XPA
1501 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1502         _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1503         _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1504 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1505         _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1506         _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1507 #define _ASM_SET_XPA ""
1508 #else   /* !TOOLCHAIN_SUPPORTS_XPA */
1509 #define _ASM_SET_XPA ".set\txpa\n\t"
1510 #endif
1511
1512 #define __readx_32bit_c0_register(source, sel)                          \
1513 ({                                                                      \
1514         unsigned int __res;                                             \
1515                                                                         \
1516         __asm__ __volatile__(                                           \
1517         "       .set    push                                    \n"     \
1518         "       .set    mips32r2                                \n"     \
1519         _ASM_SET_XPA                                                    \
1520         "       mfhc0   %0, " #source ", %1                     \n"     \
1521         "       .set    pop                                     \n"     \
1522         : "=r" (__res)                                                  \
1523         : "i" (sel));                                                   \
1524         __res;                                                          \
1525 })
1526
1527 #define __writex_32bit_c0_register(register, sel, value)                \
1528 do {                                                                    \
1529         __asm__ __volatile__(                                           \
1530         "       .set    push                                    \n"     \
1531         "       .set    mips32r2                                \n"     \
1532         _ASM_SET_XPA                                                    \
1533         "       mthc0   %z0, " #register ", %1                  \n"     \
1534         "       .set    pop                                     \n"     \
1535         :                                                               \
1536         : "Jr" (value), "i" (sel));                                     \
1537 } while (0)
1538
1539 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1540 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1541
1542 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1543 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1544
1545 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1546 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1547
1548 #define readx_c0_entrylo0()     __readx_32bit_c0_register($2, 0)
1549 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1550
1551 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1552 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1553
1554 #define readx_c0_entrylo1()     __readx_32bit_c0_register($3, 0)
1555 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1556
1557 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1558 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1559
1560 #define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
1561
1562 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1563 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1564
1565 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1566 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1567
1568 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1569 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1570
1571 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1572 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1573
1574 #define read_c0_memorymapid()           __read_32bit_c0_register($4, 5)
1575 #define write_c0_memorymapid(val)       __write_32bit_c0_register($4, 5, val)
1576
1577 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1578 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1579
1580 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1581 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1582
1583 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1584 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1585
1586 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1587
1588 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1589 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1590
1591 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1592 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1593
1594 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1595 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1596
1597 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1598 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1599
1600 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1601 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1602
1603 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1604 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1605
1606 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1607 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1608
1609 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1610 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1611
1612 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1613 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1614
1615 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1616 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1617
1618 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1619 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1620
1621 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1622 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1623
1624 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1625 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1626
1627 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1628 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1629
1630 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1631
1632 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1633
1634 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1635 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1636
1637 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1638 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1639
1640 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1641 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1642
1643 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1644 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1645
1646 #define read_c0_prid()          __read_const_32bit_c0_register($15, 0)
1647
1648 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1649
1650 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1651 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1652 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1653 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1654 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1655 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1656 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1657 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1658 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1659 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1660 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1661 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1662 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1663 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1664 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1665 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1666
1667 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1668 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1669 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1670 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1671 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1672 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1673
1674 /*
1675  * The WatchLo register.  There may be up to 8 of them.
1676  */
1677 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1678 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1679 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1680 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1681 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1682 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1683 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1684 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1685 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1686 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1687 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1688 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1689 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1690 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1691 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1692 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1693
1694 /*
1695  * The WatchHi register.  There may be up to 8 of them.
1696  */
1697 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1698 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1699 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1700 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1701 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1702 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1703 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1704 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1705
1706 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1707 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1708 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1709 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1710 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1711 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1712 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1713 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1714
1715 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1716 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1717
1718 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1719 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1720
1721 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1722 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1723
1724 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1725 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1726
1727 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1728 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1729 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1730
1731 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1732 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1733
1734 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1735 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1736
1737 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1738 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1739
1740 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1741 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1742
1743 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1744 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1745
1746 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1747 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1748
1749 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1750 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1751
1752 /*
1753  * MIPS32 / MIPS64 performance counters
1754  */
1755 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1756 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1757 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1758 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1759 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1760 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1761 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1762 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1763 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1764 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1765 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1766 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1767 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1768 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1769 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1770 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1771 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1772 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1773 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1774 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1775 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1776 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1777 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1778 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1779
1780 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1781 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1782
1783 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1784 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1785
1786 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1787
1788 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1789 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1790
1791 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1792 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1793
1794 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1795 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1796
1797 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1798 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1799
1800 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1801 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1802
1803 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1804 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1805
1806 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1807 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1808
1809 /* MIPSR2 */
1810 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1811 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1812
1813 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1814 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1815
1816 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1817 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1818
1819 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1820 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1821
1822 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1823 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1824
1825 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1826 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1827
1828 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1829 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1830
1831 /* MIPSR3 */
1832 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1833 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1834
1835 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1836 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1837
1838 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1839 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1840
1841 /* Hardware Page Table Walker */
1842 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1843 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1844
1845 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1846 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1847
1848 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1849 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1850
1851 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1852 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1853
1854 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1855 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1856
1857 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1858 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1859
1860 /* Cavium OCTEON (cnMIPS) */
1861 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1862 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1863
1864 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1865 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1866
1867 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1868 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1869
1870 #define read_c0_cvmmemctl2()    __read_64bit_c0_register($16, 6)
1871 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1872
1873 #define read_c0_cvmvmconfig()   __read_64bit_c0_register($16, 7)
1874 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1875
1876 /*
1877  * The cacheerr registers are not standardized.  On OCTEON, they are
1878  * 64 bits wide.
1879  */
1880 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1881 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1882
1883 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1884 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1885
1886 /* BMIPS3300 */
1887 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1888 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1889
1890 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1891 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1892
1893 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1894 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1895
1896 /* BMIPS43xx */
1897 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1898 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1899
1900 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1901 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1902
1903 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1904 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1905
1906 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1907 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1908
1909 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1910 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1911
1912 /* BMIPS5000 */
1913 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1914 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1915
1916 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1917 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1918
1919 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1920 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1921
1922 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1923 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1924
1925 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1926 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1927
1928 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1929 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1930
1931 /* Ingenic page ctrl register */
1932 #define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
1933
1934 /*
1935  * Macros to access the guest system control coprocessor
1936  */
1937
1938 #ifndef TOOLCHAIN_SUPPORTS_VIRT
1939 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1940         _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1941         _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1942 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1943         _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1944         _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1945 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1946         _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1947         _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1948 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1949         _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1950         _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1951 _ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
1952                        _ASM_INSN32_IF_MM(0x0000017c));
1953 _ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
1954                        _ASM_INSN32_IF_MM(0x0000117c));
1955 _ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
1956                        _ASM_INSN32_IF_MM(0x0000217c));
1957 _ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
1958                        _ASM_INSN32_IF_MM(0x0000317c));
1959 _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1960                        _ASM_INSN32_IF_MM(0x0000517c));
1961 #define _ASM_SET_VIRT ""
1962 #else   /* !TOOLCHAIN_SUPPORTS_VIRT */
1963 #define _ASM_SET_VIRT ".set\tvirt\n\t"
1964 #endif
1965
1966 #define __read_32bit_gc0_register(source, sel)                          \
1967 ({ int __res;                                                           \
1968         __asm__ __volatile__(                                           \
1969                 ".set\tpush\n\t"                                        \
1970                 ".set\tmips32r2\n\t"                                    \
1971                 _ASM_SET_VIRT                                           \
1972                 "mfgc0\t%0, " #source ", %1\n\t"                        \
1973                 ".set\tpop"                                             \
1974                 : "=r" (__res)                                          \
1975                 : "i" (sel));                                           \
1976         __res;                                                          \
1977 })
1978
1979 #define __read_64bit_gc0_register(source, sel)                          \
1980 ({ unsigned long long __res;                                            \
1981         __asm__ __volatile__(                                           \
1982                 ".set\tpush\n\t"                                        \
1983                 ".set\tmips64r2\n\t"                                    \
1984                 _ASM_SET_VIRT                                           \
1985                 "dmfgc0\t%0, " #source ", %1\n\t"                       \
1986                 ".set\tpop"                                             \
1987                 : "=r" (__res)                                          \
1988                 : "i" (sel));                                           \
1989         __res;                                                          \
1990 })
1991
1992 #define __write_32bit_gc0_register(register, sel, value)                \
1993 do {                                                                    \
1994         __asm__ __volatile__(                                           \
1995                 ".set\tpush\n\t"                                        \
1996                 ".set\tmips32r2\n\t"                                    \
1997                 _ASM_SET_VIRT                                           \
1998                 "mtgc0\t%z0, " #register ", %1\n\t"                     \
1999                 ".set\tpop"                                             \
2000                 : : "Jr" ((unsigned int)(value)),                       \
2001                     "i" (sel));                                         \
2002 } while (0)
2003
2004 #define __write_64bit_gc0_register(register, sel, value)                \
2005 do {                                                                    \
2006         __asm__ __volatile__(                                           \
2007                 ".set\tpush\n\t"                                        \
2008                 ".set\tmips64r2\n\t"                                    \
2009                 _ASM_SET_VIRT                                           \
2010                 "dmtgc0\t%z0, " #register ", %1\n\t"                    \
2011                 ".set\tpop"                                             \
2012                 : : "Jr" (value),                                       \
2013                     "i" (sel));                                         \
2014 } while (0)
2015
2016 #define __read_ulong_gc0_register(reg, sel)                             \
2017         ((sizeof(unsigned long) == 4) ?                                 \
2018         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
2019         (unsigned long) __read_64bit_gc0_register(reg, sel))
2020
2021 #define __write_ulong_gc0_register(reg, sel, val)                       \
2022 do {                                                                    \
2023         if (sizeof(unsigned long) == 4)                                 \
2024                 __write_32bit_gc0_register(reg, sel, val);              \
2025         else                                                            \
2026                 __write_64bit_gc0_register(reg, sel, val);              \
2027 } while (0)
2028
2029 #define read_gc0_index()                __read_32bit_gc0_register($0, 0)
2030 #define write_gc0_index(val)            __write_32bit_gc0_register($0, 0, val)
2031
2032 #define read_gc0_entrylo0()             __read_ulong_gc0_register($2, 0)
2033 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register($2, 0, val)
2034
2035 #define read_gc0_entrylo1()             __read_ulong_gc0_register($3, 0)
2036 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register($3, 0, val)
2037
2038 #define read_gc0_context()              __read_ulong_gc0_register($4, 0)
2039 #define write_gc0_context(val)          __write_ulong_gc0_register($4, 0, val)
2040
2041 #define read_gc0_contextconfig()        __read_32bit_gc0_register($4, 1)
2042 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register($4, 1, val)
2043
2044 #define read_gc0_userlocal()            __read_ulong_gc0_register($4, 2)
2045 #define write_gc0_userlocal(val)        __write_ulong_gc0_register($4, 2, val)
2046
2047 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register($4, 3)
2048 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register($4, 3, val)
2049
2050 #define read_gc0_pagemask()             __read_32bit_gc0_register($5, 0)
2051 #define write_gc0_pagemask(val)         __write_32bit_gc0_register($5, 0, val)
2052
2053 #define read_gc0_pagegrain()            __read_32bit_gc0_register($5, 1)
2054 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register($5, 1, val)
2055
2056 #define read_gc0_segctl0()              __read_ulong_gc0_register($5, 2)
2057 #define write_gc0_segctl0(val)          __write_ulong_gc0_register($5, 2, val)
2058
2059 #define read_gc0_segctl1()              __read_ulong_gc0_register($5, 3)
2060 #define write_gc0_segctl1(val)          __write_ulong_gc0_register($5, 3, val)
2061
2062 #define read_gc0_segctl2()              __read_ulong_gc0_register($5, 4)
2063 #define write_gc0_segctl2(val)          __write_ulong_gc0_register($5, 4, val)
2064
2065 #define read_gc0_pwbase()               __read_ulong_gc0_register($5, 5)
2066 #define write_gc0_pwbase(val)           __write_ulong_gc0_register($5, 5, val)
2067
2068 #define read_gc0_pwfield()              __read_ulong_gc0_register($5, 6)
2069 #define write_gc0_pwfield(val)          __write_ulong_gc0_register($5, 6, val)
2070
2071 #define read_gc0_pwsize()               __read_ulong_gc0_register($5, 7)
2072 #define write_gc0_pwsize(val)           __write_ulong_gc0_register($5, 7, val)
2073
2074 #define read_gc0_wired()                __read_32bit_gc0_register($6, 0)
2075 #define write_gc0_wired(val)            __write_32bit_gc0_register($6, 0, val)
2076
2077 #define read_gc0_pwctl()                __read_32bit_gc0_register($6, 6)
2078 #define write_gc0_pwctl(val)            __write_32bit_gc0_register($6, 6, val)
2079
2080 #define read_gc0_hwrena()               __read_32bit_gc0_register($7, 0)
2081 #define write_gc0_hwrena(val)           __write_32bit_gc0_register($7, 0, val)
2082
2083 #define read_gc0_badvaddr()             __read_ulong_gc0_register($8, 0)
2084 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register($8, 0, val)
2085
2086 #define read_gc0_badinstr()             __read_32bit_gc0_register($8, 1)
2087 #define write_gc0_badinstr(val)         __write_32bit_gc0_register($8, 1, val)
2088
2089 #define read_gc0_badinstrp()            __read_32bit_gc0_register($8, 2)
2090 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register($8, 2, val)
2091
2092 #define read_gc0_count()                __read_32bit_gc0_register($9, 0)
2093
2094 #define read_gc0_entryhi()              __read_ulong_gc0_register($10, 0)
2095 #define write_gc0_entryhi(val)          __write_ulong_gc0_register($10, 0, val)
2096
2097 #define read_gc0_compare()              __read_32bit_gc0_register($11, 0)
2098 #define write_gc0_compare(val)          __write_32bit_gc0_register($11, 0, val)
2099
2100 #define read_gc0_status()               __read_32bit_gc0_register($12, 0)
2101 #define write_gc0_status(val)           __write_32bit_gc0_register($12, 0, val)
2102
2103 #define read_gc0_intctl()               __read_32bit_gc0_register($12, 1)
2104 #define write_gc0_intctl(val)           __write_32bit_gc0_register($12, 1, val)
2105
2106 #define read_gc0_cause()                __read_32bit_gc0_register($13, 0)
2107 #define write_gc0_cause(val)            __write_32bit_gc0_register($13, 0, val)
2108
2109 #define read_gc0_epc()                  __read_ulong_gc0_register($14, 0)
2110 #define write_gc0_epc(val)              __write_ulong_gc0_register($14, 0, val)
2111
2112 #define read_gc0_prid()                 __read_32bit_gc0_register($15, 0)
2113
2114 #define read_gc0_ebase()                __read_32bit_gc0_register($15, 1)
2115 #define write_gc0_ebase(val)            __write_32bit_gc0_register($15, 1, val)
2116
2117 #define read_gc0_ebase_64()             __read_64bit_gc0_register($15, 1)
2118 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register($15, 1, val)
2119
2120 #define read_gc0_config()               __read_32bit_gc0_register($16, 0)
2121 #define read_gc0_config1()              __read_32bit_gc0_register($16, 1)
2122 #define read_gc0_config2()              __read_32bit_gc0_register($16, 2)
2123 #define read_gc0_config3()              __read_32bit_gc0_register($16, 3)
2124 #define read_gc0_config4()              __read_32bit_gc0_register($16, 4)
2125 #define read_gc0_config5()              __read_32bit_gc0_register($16, 5)
2126 #define read_gc0_config6()              __read_32bit_gc0_register($16, 6)
2127 #define read_gc0_config7()              __read_32bit_gc0_register($16, 7)
2128 #define write_gc0_config(val)           __write_32bit_gc0_register($16, 0, val)
2129 #define write_gc0_config1(val)          __write_32bit_gc0_register($16, 1, val)
2130 #define write_gc0_config2(val)          __write_32bit_gc0_register($16, 2, val)
2131 #define write_gc0_config3(val)          __write_32bit_gc0_register($16, 3, val)
2132 #define write_gc0_config4(val)          __write_32bit_gc0_register($16, 4, val)
2133 #define write_gc0_config5(val)          __write_32bit_gc0_register($16, 5, val)
2134 #define write_gc0_config6(val)          __write_32bit_gc0_register($16, 6, val)
2135 #define write_gc0_config7(val)          __write_32bit_gc0_register($16, 7, val)
2136
2137 #define read_gc0_lladdr()               __read_ulong_gc0_register($17, 0)
2138 #define write_gc0_lladdr(val)           __write_ulong_gc0_register($17, 0, val)
2139
2140 #define read_gc0_watchlo0()             __read_ulong_gc0_register($18, 0)
2141 #define read_gc0_watchlo1()             __read_ulong_gc0_register($18, 1)
2142 #define read_gc0_watchlo2()             __read_ulong_gc0_register($18, 2)
2143 #define read_gc0_watchlo3()             __read_ulong_gc0_register($18, 3)
2144 #define read_gc0_watchlo4()             __read_ulong_gc0_register($18, 4)
2145 #define read_gc0_watchlo5()             __read_ulong_gc0_register($18, 5)
2146 #define read_gc0_watchlo6()             __read_ulong_gc0_register($18, 6)
2147 #define read_gc0_watchlo7()             __read_ulong_gc0_register($18, 7)
2148 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register($18, 0, val)
2149 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register($18, 1, val)
2150 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register($18, 2, val)
2151 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register($18, 3, val)
2152 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register($18, 4, val)
2153 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register($18, 5, val)
2154 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register($18, 6, val)
2155 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register($18, 7, val)
2156
2157 #define read_gc0_watchhi0()             __read_32bit_gc0_register($19, 0)
2158 #define read_gc0_watchhi1()             __read_32bit_gc0_register($19, 1)
2159 #define read_gc0_watchhi2()             __read_32bit_gc0_register($19, 2)
2160 #define read_gc0_watchhi3()             __read_32bit_gc0_register($19, 3)
2161 #define read_gc0_watchhi4()             __read_32bit_gc0_register($19, 4)
2162 #define read_gc0_watchhi5()             __read_32bit_gc0_register($19, 5)
2163 #define read_gc0_watchhi6()             __read_32bit_gc0_register($19, 6)
2164 #define read_gc0_watchhi7()             __read_32bit_gc0_register($19, 7)
2165 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register($19, 0, val)
2166 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register($19, 1, val)
2167 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register($19, 2, val)
2168 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register($19, 3, val)
2169 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register($19, 4, val)
2170 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register($19, 5, val)
2171 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register($19, 6, val)
2172 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register($19, 7, val)
2173
2174 #define read_gc0_xcontext()             __read_ulong_gc0_register($20, 0)
2175 #define write_gc0_xcontext(val)         __write_ulong_gc0_register($20, 0, val)
2176
2177 #define read_gc0_perfctrl0()            __read_32bit_gc0_register($25, 0)
2178 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register($25, 0, val)
2179 #define read_gc0_perfcntr0()            __read_32bit_gc0_register($25, 1)
2180 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register($25, 1, val)
2181 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register($25, 1)
2182 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register($25, 1, val)
2183 #define read_gc0_perfctrl1()            __read_32bit_gc0_register($25, 2)
2184 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register($25, 2, val)
2185 #define read_gc0_perfcntr1()            __read_32bit_gc0_register($25, 3)
2186 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register($25, 3, val)
2187 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register($25, 3)
2188 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register($25, 3, val)
2189 #define read_gc0_perfctrl2()            __read_32bit_gc0_register($25, 4)
2190 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register($25, 4, val)
2191 #define read_gc0_perfcntr2()            __read_32bit_gc0_register($25, 5)
2192 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register($25, 5, val)
2193 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register($25, 5)
2194 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register($25, 5, val)
2195 #define read_gc0_perfctrl3()            __read_32bit_gc0_register($25, 6)
2196 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register($25, 6, val)
2197 #define read_gc0_perfcntr3()            __read_32bit_gc0_register($25, 7)
2198 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register($25, 7, val)
2199 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register($25, 7)
2200 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register($25, 7, val)
2201
2202 #define read_gc0_errorepc()             __read_ulong_gc0_register($30, 0)
2203 #define write_gc0_errorepc(val)         __write_ulong_gc0_register($30, 0, val)
2204
2205 #define read_gc0_kscratch1()            __read_ulong_gc0_register($31, 2)
2206 #define read_gc0_kscratch2()            __read_ulong_gc0_register($31, 3)
2207 #define read_gc0_kscratch3()            __read_ulong_gc0_register($31, 4)
2208 #define read_gc0_kscratch4()            __read_ulong_gc0_register($31, 5)
2209 #define read_gc0_kscratch5()            __read_ulong_gc0_register($31, 6)
2210 #define read_gc0_kscratch6()            __read_ulong_gc0_register($31, 7)
2211 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register($31, 2, val)
2212 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register($31, 3, val)
2213 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register($31, 4, val)
2214 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register($31, 5, val)
2215 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register($31, 6, val)
2216 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register($31, 7, val)
2217
2218 /* Cavium OCTEON (cnMIPS) */
2219 #define read_gc0_cvmcount()             __read_ulong_gc0_register($9, 6)
2220 #define write_gc0_cvmcount(val)         __write_ulong_gc0_register($9, 6, val)
2221
2222 #define read_gc0_cvmctl()               __read_64bit_gc0_register($9, 7)
2223 #define write_gc0_cvmctl(val)           __write_64bit_gc0_register($9, 7, val)
2224
2225 #define read_gc0_cvmmemctl()            __read_64bit_gc0_register($11, 7)
2226 #define write_gc0_cvmmemctl(val)        __write_64bit_gc0_register($11, 7, val)
2227
2228 #define read_gc0_cvmmemctl2()           __read_64bit_gc0_register($16, 6)
2229 #define write_gc0_cvmmemctl2(val)       __write_64bit_gc0_register($16, 6, val)
2230
2231 /*
2232  * Macros to access the floating point coprocessor control registers
2233  */
2234 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2235 ({                                                                      \
2236         unsigned int __res;                                             \
2237                                                                         \
2238         __asm__ __volatile__(                                           \
2239         "       .set    push                                    \n"     \
2240         "       .set    reorder                                 \n"     \
2241         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2242         "       # like Octeon.                                  \n"     \
2243         "       .set    mips1                                   \n"     \
2244         "       "STR(gas_hardfloat)"                            \n"     \
2245         "       cfc1    %0,"STR(source)"                        \n"     \
2246         "       .set    pop                                     \n"     \
2247         : "=r" (__res));                                                \
2248         __res;                                                          \
2249 })
2250
2251 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2252 do {                                                                    \
2253         __asm__ __volatile__(                                           \
2254         "       .set    push                                    \n"     \
2255         "       .set    reorder                                 \n"     \
2256         "       "STR(gas_hardfloat)"                            \n"     \
2257         "       ctc1    %0,"STR(dest)"                          \n"     \
2258         "       .set    pop                                     \n"     \
2259         : : "r" (val));                                                 \
2260 } while (0)
2261
2262 #ifdef GAS_HAS_SET_HARDFLOAT
2263 #define read_32bit_cp1_register(source)                                 \
2264         _read_32bit_cp1_register(source, .set hardfloat)
2265 #define write_32bit_cp1_register(dest, val)                             \
2266         _write_32bit_cp1_register(dest, val, .set hardfloat)
2267 #else
2268 #define read_32bit_cp1_register(source)                                 \
2269         _read_32bit_cp1_register(source, )
2270 #define write_32bit_cp1_register(dest, val)                             \
2271         _write_32bit_cp1_register(dest, val, )
2272 #endif
2273
2274 #ifdef TOOLCHAIN_SUPPORTS_DSP
2275 #define rddsp(mask)                                                     \
2276 ({                                                                      \
2277         unsigned int __dspctl;                                          \
2278                                                                         \
2279         __asm__ __volatile__(                                           \
2280         "       .set push                                       \n"     \
2281         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2282         "       .set dsp                                        \n"     \
2283         "       rddsp   %0, %x1                                 \n"     \
2284         "       .set pop                                        \n"     \
2285         : "=r" (__dspctl)                                               \
2286         : "i" (mask));                                                  \
2287         __dspctl;                                                       \
2288 })
2289
2290 #define wrdsp(val, mask)                                                \
2291 do {                                                                    \
2292         __asm__ __volatile__(                                           \
2293         "       .set push                                       \n"     \
2294         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2295         "       .set dsp                                        \n"     \
2296         "       wrdsp   %0, %x1                                 \n"     \
2297         "       .set pop                                        \n"     \
2298         :                                                               \
2299         : "r" (val), "i" (mask));                                       \
2300 } while (0)
2301
2302 #define mflo0()                                                         \
2303 ({                                                                      \
2304         long mflo0;                                                     \
2305         __asm__(                                                        \
2306         "       .set push                                       \n"     \
2307         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2308         "       .set dsp                                        \n"     \
2309         "       mflo %0, $ac0                                   \n"     \
2310         "       .set pop                                        \n"     \
2311         : "=r" (mflo0));                                                \
2312         mflo0;                                                          \
2313 })
2314
2315 #define mflo1()                                                         \
2316 ({                                                                      \
2317         long mflo1;                                                     \
2318         __asm__(                                                        \
2319         "       .set push                                       \n"     \
2320         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2321         "       .set dsp                                        \n"     \
2322         "       mflo %0, $ac1                                   \n"     \
2323         "       .set pop                                        \n"     \
2324         : "=r" (mflo1));                                                \
2325         mflo1;                                                          \
2326 })
2327
2328 #define mflo2()                                                         \
2329 ({                                                                      \
2330         long mflo2;                                                     \
2331         __asm__(                                                        \
2332         "       .set push                                       \n"     \
2333         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2334         "       .set dsp                                        \n"     \
2335         "       mflo %0, $ac2                                   \n"     \
2336         "       .set pop                                        \n"     \
2337         : "=r" (mflo2));                                                \
2338         mflo2;                                                          \
2339 })
2340
2341 #define mflo3()                                                         \
2342 ({                                                                      \
2343         long mflo3;                                                     \
2344         __asm__(                                                        \
2345         "       .set push                                       \n"     \
2346         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2347         "       .set dsp                                        \n"     \
2348         "       mflo %0, $ac3                                   \n"     \
2349         "       .set pop                                        \n"     \
2350         : "=r" (mflo3));                                                \
2351         mflo3;                                                          \
2352 })
2353
2354 #define mfhi0()                                                         \
2355 ({                                                                      \
2356         long mfhi0;                                                     \
2357         __asm__(                                                        \
2358         "       .set push                                       \n"     \
2359         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2360         "       .set dsp                                        \n"     \
2361         "       mfhi %0, $ac0                                   \n"     \
2362         "       .set pop                                        \n"     \
2363         : "=r" (mfhi0));                                                \
2364         mfhi0;                                                          \
2365 })
2366
2367 #define mfhi1()                                                         \
2368 ({                                                                      \
2369         long mfhi1;                                                     \
2370         __asm__(                                                        \
2371         "       .set push                                       \n"     \
2372         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2373         "       .set dsp                                        \n"     \
2374         "       mfhi %0, $ac1                                   \n"     \
2375         "       .set pop                                        \n"     \
2376         : "=r" (mfhi1));                                                \
2377         mfhi1;                                                          \
2378 })
2379
2380 #define mfhi2()                                                         \
2381 ({                                                                      \
2382         long mfhi2;                                                     \
2383         __asm__(                                                        \
2384         "       .set push                                       \n"     \
2385         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2386         "       .set dsp                                        \n"     \
2387         "       mfhi %0, $ac2                                   \n"     \
2388         "       .set pop                                        \n"     \
2389         : "=r" (mfhi2));                                                \
2390         mfhi2;                                                          \
2391 })
2392
2393 #define mfhi3()                                                         \
2394 ({                                                                      \
2395         long mfhi3;                                                     \
2396         __asm__(                                                        \
2397         "       .set push                                       \n"     \
2398         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2399         "       .set dsp                                        \n"     \
2400         "       mfhi %0, $ac3                                   \n"     \
2401         "       .set pop                                        \n"     \
2402         : "=r" (mfhi3));                                                \
2403         mfhi3;                                                          \
2404 })
2405
2406
2407 #define mtlo0(x)                                                        \
2408 ({                                                                      \
2409         __asm__(                                                        \
2410         "       .set push                                       \n"     \
2411         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2412         "       .set dsp                                        \n"     \
2413         "       mtlo %0, $ac0                                   \n"     \
2414         "       .set pop                                        \n"     \
2415         :                                                               \
2416         : "r" (x));                                                     \
2417 })
2418
2419 #define mtlo1(x)                                                        \
2420 ({                                                                      \
2421         __asm__(                                                        \
2422         "       .set push                                       \n"     \
2423         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2424         "       .set dsp                                        \n"     \
2425         "       mtlo %0, $ac1                                   \n"     \
2426         "       .set pop                                        \n"     \
2427         :                                                               \
2428         : "r" (x));                                                     \
2429 })
2430
2431 #define mtlo2(x)                                                        \
2432 ({                                                                      \
2433         __asm__(                                                        \
2434         "       .set push                                       \n"     \
2435         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2436         "       .set dsp                                        \n"     \
2437         "       mtlo %0, $ac2                                   \n"     \
2438         "       .set pop                                        \n"     \
2439         :                                                               \
2440         : "r" (x));                                                     \
2441 })
2442
2443 #define mtlo3(x)                                                        \
2444 ({                                                                      \
2445         __asm__(                                                        \
2446         "       .set push                                       \n"     \
2447         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2448         "       .set dsp                                        \n"     \
2449         "       mtlo %0, $ac3                                   \n"     \
2450         "       .set pop                                        \n"     \
2451         :                                                               \
2452         : "r" (x));                                                     \
2453 })
2454
2455 #define mthi0(x)                                                        \
2456 ({                                                                      \
2457         __asm__(                                                        \
2458         "       .set push                                       \n"     \
2459         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2460         "       .set dsp                                        \n"     \
2461         "       mthi %0, $ac0                                   \n"     \
2462         "       .set pop                                        \n"     \
2463         :                                                               \
2464         : "r" (x));                                                     \
2465 })
2466
2467 #define mthi1(x)                                                        \
2468 ({                                                                      \
2469         __asm__(                                                        \
2470         "       .set push                                       \n"     \
2471         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2472         "       .set dsp                                        \n"     \
2473         "       mthi %0, $ac1                                   \n"     \
2474         "       .set pop                                        \n"     \
2475         :                                                               \
2476         : "r" (x));                                                     \
2477 })
2478
2479 #define mthi2(x)                                                        \
2480 ({                                                                      \
2481         __asm__(                                                        \
2482         "       .set push                                       \n"     \
2483         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2484         "       .set dsp                                        \n"     \
2485         "       mthi %0, $ac2                                   \n"     \
2486         "       .set pop                                        \n"     \
2487         :                                                               \
2488         : "r" (x));                                                     \
2489 })
2490
2491 #define mthi3(x)                                                        \
2492 ({                                                                      \
2493         __asm__(                                                        \
2494         "       .set push                                       \n"     \
2495         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2496         "       .set dsp                                        \n"     \
2497         "       mthi %0, $ac3                                   \n"     \
2498         "       .set pop                                        \n"     \
2499         :                                                               \
2500         : "r" (x));                                                     \
2501 })
2502
2503 #else
2504
2505 #define rddsp(mask)                                                     \
2506 ({                                                                      \
2507         unsigned int __res;                                             \
2508                                                                         \
2509         __asm__ __volatile__(                                           \
2510         "       .set    push                                    \n"     \
2511         "       .set    noat                                    \n"     \
2512         "       # rddsp $1, %x1                                 \n"     \
2513         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2514         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2515         "       move    %0, $1                                  \n"     \
2516         "       .set    pop                                     \n"     \
2517         : "=r" (__res)                                                  \
2518         : "i" (mask));                                                  \
2519         __res;                                                          \
2520 })
2521
2522 #define wrdsp(val, mask)                                                \
2523 do {                                                                    \
2524         __asm__ __volatile__(                                           \
2525         "       .set    push                                    \n"     \
2526         "       .set    noat                                    \n"     \
2527         "       move    $1, %0                                  \n"     \
2528         "       # wrdsp $1, %x1                                 \n"     \
2529         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2530         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2531         "       .set    pop                                     \n"     \
2532         :                                                               \
2533         : "r" (val), "i" (mask));                                       \
2534 } while (0)
2535
2536 #define _dsp_mfxxx(ins)                                                 \
2537 ({                                                                      \
2538         unsigned long __treg;                                           \
2539                                                                         \
2540         __asm__ __volatile__(                                           \
2541         "       .set    push                                    \n"     \
2542         "       .set    noat                                    \n"     \
2543         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2544         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2545         "       move    %0, $1                                  \n"     \
2546         "       .set    pop                                     \n"     \
2547         : "=r" (__treg)                                                 \
2548         : "i" (ins));                                                   \
2549         __treg;                                                         \
2550 })
2551
2552 #define _dsp_mtxxx(val, ins)                                            \
2553 do {                                                                    \
2554         __asm__ __volatile__(                                           \
2555         "       .set    push                                    \n"     \
2556         "       .set    noat                                    \n"     \
2557         "       move    $1, %0                                  \n"     \
2558         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2559         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2560         "       .set    pop                                     \n"     \
2561         :                                                               \
2562         : "r" (val), "i" (ins));                                        \
2563 } while (0)
2564
2565 #ifdef CONFIG_CPU_MICROMIPS
2566
2567 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2568 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2569
2570 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2571 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2572
2573 #else  /* !CONFIG_CPU_MICROMIPS */
2574
2575 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2576 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2577
2578 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2579 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2580
2581 #endif /* CONFIG_CPU_MICROMIPS */
2582
2583 #define mflo0() _dsp_mflo(0)
2584 #define mflo1() _dsp_mflo(1)
2585 #define mflo2() _dsp_mflo(2)
2586 #define mflo3() _dsp_mflo(3)
2587
2588 #define mfhi0() _dsp_mfhi(0)
2589 #define mfhi1() _dsp_mfhi(1)
2590 #define mfhi2() _dsp_mfhi(2)
2591 #define mfhi3() _dsp_mfhi(3)
2592
2593 #define mtlo0(x) _dsp_mtlo(x, 0)
2594 #define mtlo1(x) _dsp_mtlo(x, 1)
2595 #define mtlo2(x) _dsp_mtlo(x, 2)
2596 #define mtlo3(x) _dsp_mtlo(x, 3)
2597
2598 #define mthi0(x) _dsp_mthi(x, 0)
2599 #define mthi1(x) _dsp_mthi(x, 1)
2600 #define mthi2(x) _dsp_mthi(x, 2)
2601 #define mthi3(x) _dsp_mthi(x, 3)
2602
2603 #endif
2604
2605 /*
2606  * TLB operations.
2607  *
2608  * It is responsibility of the caller to take care of any TLB hazards.
2609  */
2610 static inline void tlb_probe(void)
2611 {
2612         __asm__ __volatile__(
2613                 ".set noreorder\n\t"
2614                 "tlbp\n\t"
2615                 ".set reorder");
2616 }
2617
2618 static inline void tlb_read(void)
2619 {
2620 #if MIPS34K_MISSED_ITLB_WAR
2621         int res = 0;
2622
2623         __asm__ __volatile__(
2624         "       .set    push                                    \n"
2625         "       .set    noreorder                               \n"
2626         "       .set    noat                                    \n"
2627         "       .set    mips32r2                                \n"
2628         "       .word   0x41610001              # dvpe $1       \n"
2629         "       move    %0, $1                                  \n"
2630         "       ehb                                             \n"
2631         "       .set    pop                                     \n"
2632         : "=r" (res));
2633
2634         instruction_hazard();
2635 #endif
2636
2637         __asm__ __volatile__(
2638                 ".set noreorder\n\t"
2639                 "tlbr\n\t"
2640                 ".set reorder");
2641
2642 #if MIPS34K_MISSED_ITLB_WAR
2643         if ((res & _ULCAST_(1)))
2644                 __asm__ __volatile__(
2645                 "       .set    push                            \n"
2646                 "       .set    noreorder                       \n"
2647                 "       .set    noat                            \n"
2648                 "       .set    mips32r2                        \n"
2649                 "       .word   0x41600021      # evpe          \n"
2650                 "       ehb                                     \n"
2651                 "       .set    pop                             \n");
2652 #endif
2653 }
2654
2655 static inline void tlb_write_indexed(void)
2656 {
2657         __asm__ __volatile__(
2658                 ".set noreorder\n\t"
2659                 "tlbwi\n\t"
2660                 ".set reorder");
2661 }
2662
2663 static inline void tlb_write_random(void)
2664 {
2665         __asm__ __volatile__(
2666                 ".set noreorder\n\t"
2667                 "tlbwr\n\t"
2668                 ".set reorder");
2669 }
2670
2671 /*
2672  * Guest TLB operations.
2673  *
2674  * It is responsibility of the caller to take care of any TLB hazards.
2675  */
2676 static inline void guest_tlb_probe(void)
2677 {
2678         __asm__ __volatile__(
2679                 ".set push\n\t"
2680                 ".set noreorder\n\t"
2681                 _ASM_SET_VIRT
2682                 "tlbgp\n\t"
2683                 ".set pop");
2684 }
2685
2686 static inline void guest_tlb_read(void)
2687 {
2688         __asm__ __volatile__(
2689                 ".set push\n\t"
2690                 ".set noreorder\n\t"
2691                 _ASM_SET_VIRT
2692                 "tlbgr\n\t"
2693                 ".set pop");
2694 }
2695
2696 static inline void guest_tlb_write_indexed(void)
2697 {
2698         __asm__ __volatile__(
2699                 ".set push\n\t"
2700                 ".set noreorder\n\t"
2701                 _ASM_SET_VIRT
2702                 "tlbgwi\n\t"
2703                 ".set pop");
2704 }
2705
2706 static inline void guest_tlb_write_random(void)
2707 {
2708         __asm__ __volatile__(
2709                 ".set push\n\t"
2710                 ".set noreorder\n\t"
2711                 _ASM_SET_VIRT
2712                 "tlbgwr\n\t"
2713                 ".set pop");
2714 }
2715
2716 /*
2717  * Guest TLB Invalidate Flush
2718  */
2719 static inline void guest_tlbinvf(void)
2720 {
2721         __asm__ __volatile__(
2722                 ".set push\n\t"
2723                 ".set noreorder\n\t"
2724                 _ASM_SET_VIRT
2725                 "tlbginvf\n\t"
2726                 ".set pop");
2727 }
2728
2729 /*
2730  * Manipulate bits in a register.
2731  */
2732 #define __BUILD_SET_COMMON(name)                                \
2733 static inline unsigned int                                      \
2734 set_##name(unsigned int set)                                    \
2735 {                                                               \
2736         unsigned int res, new;                                  \
2737                                                                 \
2738         res = read_##name();                                    \
2739         new = res | set;                                        \
2740         write_##name(new);                                      \
2741                                                                 \
2742         return res;                                             \
2743 }                                                               \
2744                                                                 \
2745 static inline unsigned int                                      \
2746 clear_##name(unsigned int clear)                                \
2747 {                                                               \
2748         unsigned int res, new;                                  \
2749                                                                 \
2750         res = read_##name();                                    \
2751         new = res & ~clear;                                     \
2752         write_##name(new);                                      \
2753                                                                 \
2754         return res;                                             \
2755 }                                                               \
2756                                                                 \
2757 static inline unsigned int                                      \
2758 change_##name(unsigned int change, unsigned int val)            \
2759 {                                                               \
2760         unsigned int res, new;                                  \
2761                                                                 \
2762         res = read_##name();                                    \
2763         new = res & ~change;                                    \
2764         new |= (val & change);                                  \
2765         write_##name(new);                                      \
2766                                                                 \
2767         return res;                                             \
2768 }
2769
2770 /*
2771  * Manipulate bits in a c0 register.
2772  */
2773 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2774
2775 __BUILD_SET_C0(status)
2776 __BUILD_SET_C0(cause)
2777 __BUILD_SET_C0(config)
2778 __BUILD_SET_C0(config5)
2779 __BUILD_SET_C0(config7)
2780 __BUILD_SET_C0(intcontrol)
2781 __BUILD_SET_C0(intctl)
2782 __BUILD_SET_C0(srsmap)
2783 __BUILD_SET_C0(pagegrain)
2784 __BUILD_SET_C0(guestctl0)
2785 __BUILD_SET_C0(guestctl0ext)
2786 __BUILD_SET_C0(guestctl1)
2787 __BUILD_SET_C0(guestctl2)
2788 __BUILD_SET_C0(guestctl3)
2789 __BUILD_SET_C0(brcm_config_0)
2790 __BUILD_SET_C0(brcm_bus_pll)
2791 __BUILD_SET_C0(brcm_reset)
2792 __BUILD_SET_C0(brcm_cmt_intr)
2793 __BUILD_SET_C0(brcm_cmt_ctrl)
2794 __BUILD_SET_C0(brcm_config)
2795 __BUILD_SET_C0(brcm_mode)
2796
2797 /*
2798  * Manipulate bits in a guest c0 register.
2799  */
2800 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2801
2802 __BUILD_SET_GC0(wired)
2803 __BUILD_SET_GC0(status)
2804 __BUILD_SET_GC0(cause)
2805 __BUILD_SET_GC0(ebase)
2806 __BUILD_SET_GC0(config1)
2807
2808 /*
2809  * Return low 10 bits of ebase.
2810  * Note that under KVM (MIPSVZ) this returns vcpu id.
2811  */
2812 static inline unsigned int get_ebase_cpunum(void)
2813 {
2814         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2815 }
2816
2817 static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
2818                                  u32 low1)
2819 {
2820         write_c0_entrylo0(low0);
2821         write_c0_pagemask(pagemask);
2822         write_c0_entrylo1(low1);
2823         write_c0_entryhi(hi);
2824         write_c0_index(index);
2825         tlb_write_indexed();
2826 }
2827
2828 #endif /* !__ASSEMBLY__ */
2829
2830 #endif /* _ASM_MIPSREGS_H */