1 // SPDX-License-Identifier: GPL-2.0+
4 * Josef Baumgartner <josef.baumgartner@telex.de>
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
13 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
22 #include <asm/global_data.h>
23 #include <asm/immap.h>
26 #include <linux/delay.h>
29 DECLARE_GLOBAL_DATA_PTR;
32 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
34 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
38 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
40 /* we don't return! */
44 #if defined(CONFIG_DISPLAY_CPUINFO)
45 int print_cpuinfo(void)
47 char buf1[32], buf2[32];
49 printf("CPU: Freescale Coldfire MCF5208\n"
50 " CPU CLK %s MHz BUS CLK %s MHz\n",
51 strmhz(buf1, gd->cpu_clk),
52 strmhz(buf2, gd->bus_clk));
55 #endif /* CONFIG_DISPLAY_CPUINFO */
57 #if defined(CONFIG_WATCHDOG)
58 /* Called by macro WATCHDOG_RESET */
59 void watchdog_reset(void)
61 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
63 out_be16(&wdt->sr, 0x5555);
64 out_be16(&wdt->sr, 0xaaaa);
67 int watchdog_disable(void)
69 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
71 /* reset watchdog counter */
72 out_be16(&wdt->sr, 0x5555);
73 out_be16(&wdt->sr, 0xaaaa);
74 /* disable watchdog timer */
75 out_be16(&wdt->cr, 0);
77 puts("WATCHDOG:disabled\n");
81 int watchdog_init(void)
83 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
85 /* disable watchdog */
86 out_be16(&wdt->cr, 0);
88 /* set timeout and enable watchdog */
90 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
92 /* reset watchdog counter */
93 out_be16(&wdt->sr, 0x5555);
94 out_be16(&wdt->sr, 0xaaaa);
96 puts("WATCHDOG:enabled\n");
99 #endif /* #ifdef CONFIG_WATCHDOG */
100 #endif /* #ifdef CONFIG_M5208 */
103 #if defined(CONFIG_DISPLAY_CPUINFO)
105 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
106 * determine which one we are running on, based on the Chip Identification
109 int print_cpuinfo(void)
112 unsigned short cir; /* Chip Identification Register */
113 unsigned short pin; /* Part identification number */
114 unsigned char prn; /* Part revision number */
117 cir = mbar_readShort(MCF_CCM_CIR);
118 pin = cir >> MCF_CCM_CIR_PIN_LEN;
119 prn = cir & MCF_CCM_CIR_PRN_MASK;
122 case MCF_CCM_CIR_PIN_MCF5270:
125 case MCF_CCM_CIR_PIN_MCF5271:
134 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
135 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
137 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
138 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
139 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
143 #endif /* CONFIG_DISPLAY_CPUINFO */
145 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
147 /* Call the board specific reset actions first. */
152 mbar_writeByte(MCF_RCM_RCR,
153 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
157 #if defined(CONFIG_WATCHDOG)
158 void watchdog_reset(void)
160 mbar_writeShort(MCF_WTM_WSR, 0x5555);
161 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
164 int watchdog_disable(void)
166 mbar_writeShort(MCF_WTM_WCR, 0);
170 int watchdog_init(void)
172 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
175 #endif /* #ifdef CONFIG_WATCHDOG */
180 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
182 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
184 out_be16(&wdp->wdog_wrrr, 0);
187 /* enable watchdog, set timeout to 0 and wait */
188 out_be16(&wdp->wdog_wrrr, 1);
191 /* we don't return! */
195 #if defined(CONFIG_DISPLAY_CPUINFO)
196 int print_cpuinfo(void)
198 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
203 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
213 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
218 printf("Freescale MCF5272 %s\n", suf);
221 #endif /* CONFIG_DISPLAY_CPUINFO */
223 #if defined(CONFIG_WATCHDOG)
224 /* Called by macro WATCHDOG_RESET */
225 void watchdog_reset(void)
227 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
229 out_be16(&wdt->wdog_wcr, 0);
232 int watchdog_disable(void)
234 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
236 /* reset watchdog counter */
237 out_be16(&wdt->wdog_wcr, 0);
238 /* disable watchdog interrupt */
239 out_be16(&wdt->wdog_wirr, 0);
240 /* disable watchdog timer */
241 out_be16(&wdt->wdog_wrrr, 0);
243 puts("WATCHDOG:disabled\n");
247 int watchdog_init(void)
249 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
251 /* disable watchdog interrupt */
252 out_be16(&wdt->wdog_wirr, 0);
254 /* set timeout and enable watchdog */
255 out_be16(&wdt->wdog_wrrr,
256 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
258 /* reset watchdog counter */
259 out_be16(&wdt->wdog_wcr, 0);
261 puts("WATCHDOG:enabled\n");
264 #endif /* #ifdef CONFIG_WATCHDOG */
266 #endif /* #ifdef CONFIG_M5272 */
269 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
271 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
275 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
277 /* we don't return! */
281 #if defined(CONFIG_DISPLAY_CPUINFO)
282 int print_cpuinfo(void)
286 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
287 strmhz(buf, CONFIG_SYS_CLK));
290 #endif /* CONFIG_DISPLAY_CPUINFO */
292 #if defined(CONFIG_WATCHDOG)
293 /* Called by macro WATCHDOG_RESET */
294 void watchdog_reset(void)
296 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
298 out_be16(&wdt->wsr, 0x5555);
299 out_be16(&wdt->wsr, 0xaaaa);
302 int watchdog_disable(void)
304 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
306 /* reset watchdog counter */
307 out_be16(&wdt->wsr, 0x5555);
308 out_be16(&wdt->wsr, 0xaaaa);
310 /* disable watchdog timer */
311 out_be16(&wdt->wcr, 0);
313 puts("WATCHDOG:disabled\n");
317 int watchdog_init(void)
319 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
321 /* disable watchdog */
322 out_be16(&wdt->wcr, 0);
324 /* set timeout and enable watchdog */
326 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
328 /* reset watchdog counter */
329 out_be16(&wdt->wsr, 0x5555);
330 out_be16(&wdt->wsr, 0xaaaa);
332 puts("WATCHDOG:enabled\n");
335 #endif /* #ifdef CONFIG_WATCHDOG */
337 #endif /* #ifdef CONFIG_M5275 */
340 #if defined(CONFIG_DISPLAY_CPUINFO)
341 int print_cpuinfo(void)
343 unsigned char resetsource = MCFRESET_RSR;
345 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
346 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
347 printf("Reset:%s%s%s%s%s%s%s\n",
348 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
349 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
350 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
351 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
352 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
353 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
354 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
357 #endif /* CONFIG_DISPLAY_CPUINFO */
359 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
361 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
367 #if defined(CONFIG_DISPLAY_CPUINFO)
368 int print_cpuinfo(void)
372 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
373 strmhz(buf, CONFIG_SYS_CLK));
376 #endif /* CONFIG_DISPLAY_CPUINFO */
378 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
380 /* enable watchdog, set timeout to 0 and wait */
381 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
384 /* we don't return! */
390 #if defined(CONFIG_DISPLAY_CPUINFO)
391 int print_cpuinfo(void)
395 unsigned char resetsource = mbar_readLong(SIM_RSR);
396 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
397 strmhz(buf, CONFIG_SYS_CLK));
399 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
400 printf("Reset:%s%s\n",
401 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
403 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
408 #endif /* CONFIG_DISPLAY_CPUINFO */
410 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
412 /* enable watchdog, set timeout to 0 and wait */
413 mbar_writeByte(SIM_SYPCR, 0xc0);
416 /* we don't return! */
421 #if defined(CONFIG_MCFFEC)
422 /* Default initializations for MCFFEC controllers. To override,
423 * create a board-specific function called:
424 * int board_eth_init(struct bd_info *bis)
427 int cpu_eth_init(struct bd_info *bis)
429 return mcffec_initialize(bis);