1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010 Samsung Electronics
4 * Naveen Krishna Ch <ch.naveen@samsung.com>
6 * Note: This file contains the register description for Memory subsystem
7 * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
9 * Only SROMC is defined as of now
12 #ifndef __ASM_ARCH_SROMC_H_
13 #define __ASM_ARCH_SROMC_H_
15 #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
16 #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
17 /* 1-> Byte base address*/
18 #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
19 #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
21 #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
22 #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
23 #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
24 #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
25 #define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
26 #define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
27 #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
34 #endif /* __ASSEMBLY__ */
36 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
37 void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
39 #endif /* __ASM_ARCH_SMC_H_ */