1 Texas Instruments' K3 J721E DDRSS
2 ==================================
3 The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
4 logic to integrate these blocks in the device. The DDR subsystem is
5 used to provide an interface to external SDRAM devices which can be
6 utilized for storing program or data.
12 - compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200
13 "ti,am64-ddrss" for am642
14 - reg-names cfg - Map the controller configuration region
15 ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
16 - reg: Contains the register map per reg-names.
17 - power-domains: Should contain two entries:
18 - an entry to TISCI DDR CFG device
19 - an entry to TISCI DDR DATA.
20 This property is as per the binding,
21 doc/device-tree-bindings/power/ti,sci-pm-domain.txt
22 - clocks: Should contain two entries.
23 - An entry to DDRSS clock
24 - An rntry to SoC bypass clock
25 Should be defined as per the appropriate clock bindings
27 doc/device-tree-bindings/clock/ti,sci-clk.txt
28 - ti,ddr-freq1: First frequency set point
29 - ti,ddr-freq2: Second frequency set point
30 - ti,ddr-fhs-cnt: Number of times to communicate to DDR for frequency handshake.
31 - ti,ctl-data: An array containing the controller settings.
32 - ti,pi-data: An array containing the phy independent block settings
33 - ti,phy-data: An array containing the ddr phy settings.
38 memorycontroller: memorycontroller@0298e000 {
39 compatible = "ti,j721e-ddrss";
40 reg = <0x0 0x02990000 0x0 0x4000>,
41 <0x0 0x0114000 0x0 0x100>;
42 reg-names = "cfg", "ctrl_mmr_lp4";
43 power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
44 <&k3_pds 90 TI_SCI_PD_SHARED>;
45 clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
46 ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
47 ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
48 ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
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