drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  11  * to uboot.
  12  *
  13  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <log.h>
  19 #include <malloc.h>
  20 #include <dm.h>
  21 #include <dm/device_compat.h>
  22 #include <dm/devres.h>
  23 #include <linux/bug.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/list.h>
  27
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30
  31 #include "core.h"
  32 #include "gadget.h"
  33 #include "io.h"
  34
  35 #include "linux-compat.h"
  36
  37 /**
  38  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  39  * @dwc: pointer to our context structure
  40  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  41  *
  42  * Caller should take care of locking. This function will
  43  * return 0 on success or -EINVAL if wrong Test Selector
  44  * is passed
  45  */
  46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  47 {
  48         u32             reg;
  49
  50         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  51         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  52
  53         switch (mode) {
  54         case TEST_J:
  55         case TEST_K:
  56         case TEST_SE0_NAK:
  57         case TEST_PACKET:
  58         case TEST_FORCE_EN:
  59                 reg |= mode << 1;
  60                 break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  66
  67         return 0;
  68 }
  69
  70 /**
  71  * dwc3_gadget_get_link_state - Gets current state of USB Link
  72  * @dwc: pointer to our context structure
  73  *
  74  * Caller should take care of locking. This function will
  75  * return the link state on success (>= 0) or -ETIMEDOUT.
  76  */
  77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  78 {
  79         u32             reg;
  80
  81         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  82
  83         return DWC3_DSTS_USBLNKST(reg);
  84 }
  85
  86 /**
  87  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  88  * @dwc: pointer to our context structure
  89  * @state: the state to put link into
  90  *
  91  * Caller should take care of locking. This function will
  92  * return 0 on success or -ETIMEDOUT.
  93  */
  94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  95 {
  96         int             retries = 10000;
  97         u32             reg;
  98
  99         /*
 100          * Wait until device controller is ready. Only applies to 1.94a and
 101          * later RTL.
 102          */
 103         if (dwc->revision >= DWC3_REVISION_194A) {
 104                 while (--retries) {
 105                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 106                         if (reg & DWC3_DSTS_DCNRD)
 107                                 udelay(5);
 108                         else
 109                                 break;
 110                 }
 111
 112                 if (retries <= 0)
 113                         return -ETIMEDOUT;
 114         }
 115
 116         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 117         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 118
 119         /* set requested state */
 120         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 121         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 122
 123         /*
 124          * The following code is racy when called from dwc3_gadget_wakeup,
 125          * and is not needed, at least on newer versions
 126          */
 127         if (dwc->revision >= DWC3_REVISION_194A)
 128                 return 0;
 129
 130         /* wait for a change in DSTS */
 131         retries = 10000;
 132         while (--retries) {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 134
 135                 if (DWC3_DSTS_USBLNKST(reg) == state)
 136                         return 0;
 137
 138                 udelay(5);
 139         }
 140
 141         dev_vdbg(dwc->dev, "link state change request timed out\n");
 142
 143         return -ETIMEDOUT;
 144 }
 145
 146 /**
 147  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 148  * @dwc: pointer to our context structure
 149  *
 150  * This function will a best effort FIFO allocation in order
 151  * to improve FIFO usage and throughput, while still allowing
 152  * us to enable as many endpoints as possible.
 153  *
 154  * Keep in mind that this operation will be highly dependent
 155  * on the configured size for RAM1 - which contains TxFifo -,
 156  * the amount of endpoints enabled on coreConsultant tool, and
 157  * the width of the Master Bus.
 158  *
 159  * In the ideal world, we would always be able to satisfy the
 160  * following equation:
 161  *
 162  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 163  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 164  *
 165  * Unfortunately, due to many variables that's not always the case.
 166  */
 167 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 168 {
 169         int             last_fifo_depth = 0;
 170         int             fifo_size;
 171         int             mdwidth;
 172         int             num;
 173
 174         if (!dwc->needs_fifo_resize)
 175                 return 0;
 176
 177         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 178
 179         /* MDWIDTH is represented in bits, we need it in bytes */
 180         mdwidth >>= 3;
 181
 182         /*
 183          * FIXME For now we will only allocate 1 wMaxPacketSize space
 184          * for each enabled endpoint, later patches will come to
 185          * improve this algorithm so that we better use the internal
 186          * FIFO space
 187          */
 188         for (num = 0; num < dwc->num_in_eps; num++) {
 189                 /* bit0 indicates direction; 1 means IN ep */
 190                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 191                 int             mult = 1;
 192                 int             tmp;
 193
 194                 if (!(dep->flags & DWC3_EP_ENABLED))
 195                         continue;
 196
 197                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 198                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 199                         mult = 3;
 200
 201                 /*
 202                  * REVISIT: the following assumes we will always have enough
 203                  * space available on the FIFO RAM for all possible use cases.
 204                  * Make sure that's true somehow and change FIFO allocation
 205                  * accordingly.
 206                  *
 207                  * If we have Bulk or Isochronous endpoints, we want
 208                  * them to be able to be very, very fast. So we're giving
 209                  * those endpoints a fifo_size which is enough for 3 full
 210                  * packets
 211                  */
 212                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 213                 tmp += mdwidth;
 214
 215                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 216
 217                 fifo_size |= (last_fifo_depth << 16);
 218
 219                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 220                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 221
 222                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 223
 224                 last_fifo_depth += (fifo_size & 0xffff);
 225         }
 226
 227         return 0;
 228 }
 229
 230 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 231                 int status)
 232 {
 233         struct dwc3                     *dwc = dep->dwc;
 234
 235         if (req->queued) {
 236                 dep->busy_slot++;
 237                 /*
 238                  * Skip LINK TRB. We can't use req->trb and check for
 239                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 240                  * just completed (not the LINK TRB).
 241                  */
 242                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 243                         DWC3_TRB_NUM- 1) &&
 244                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 245                         dep->busy_slot++;
 246                 req->queued = false;
 247         }
 248
 249         list_del(&req->list);
 250         req->trb = NULL;
 251         if (req->request.length)
 252                 dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
 253
 254         if (req->request.status == -EINPROGRESS)
 255                 req->request.status = status;
 256
 257         if (dwc->ep0_bounced && dep->number == 0)
 258                 dwc->ep0_bounced = false;
 259         else
 260                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 261                                 req->direction);
 262
 263         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 264                         req, dep->name, req->request.actual,
 265                         req->request.length, status);
 266
 267         spin_unlock(&dwc->lock);
 268         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 269         spin_lock(&dwc->lock);
 270 }
 271
 272 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 273 {
 274         u32             timeout = 500;
 275         u32             reg;
 276
 277         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 278         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 279
 280         do {
 281                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 282                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 283                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 284                                         DWC3_DGCMD_STATUS(reg));
 285                         return 0;
 286                 }
 287
 288                 /*
 289                  * We can't sleep here, because it's also called from
 290                  * interrupt context.
 291                  */
 292                 timeout--;
 293                 if (!timeout)
 294                         return -ETIMEDOUT;
 295                 udelay(1);
 296         } while (1);
 297 }
 298
 299 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 300                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 301 {
 302         u32                     timeout = 500;
 303         u32                     reg;
 304
 305         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 306         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 307         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 308
 309         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 310         do {
 311                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 312                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 313                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 314                                         DWC3_DEPCMD_STATUS(reg));
 315                         return 0;
 316                 }
 317
 318                 /*
 319                  * We can't sleep here, because it is also called from
 320                  * interrupt context.
 321                  */
 322                 timeout--;
 323                 if (!timeout)
 324                         return -ETIMEDOUT;
 325
 326                 udelay(1);
 327         } while (1);
 328 }
 329
 330 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 331                 struct dwc3_trb *trb)
 332 {
 333         u32             offset = (char *) trb - (char *) dep->trb_pool;
 334
 335         return dep->trb_pool_dma + offset;
 336 }
 337
 338 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 339 {
 340         if (dep->trb_pool)
 341                 return 0;
 342
 343         if (dep->number == 0 || dep->number == 1)
 344                 return 0;
 345
 346         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 347                                            DWC3_TRB_NUM,
 348                                            (unsigned long *)&dep->trb_pool_dma);
 349         if (!dep->trb_pool) {
 350                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 351                                 dep->name);
 352                 return -ENOMEM;
 353         }
 354
 355         return 0;
 356 }
 357
 358 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 359 {
 360         dma_free_coherent(dep->trb_pool);
 361
 362         dep->trb_pool = NULL;
 363         dep->trb_pool_dma = 0;
 364 }
 365
 366 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 367 {
 368         struct dwc3_gadget_ep_cmd_params params;
 369         u32                     cmd;
 370
 371         memset(&params, 0x00, sizeof(params));
 372
 373         if (dep->number != 1) {
 374                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 375                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 376                 if (dep->number > 1) {
 377                         if (dwc->start_config_issued)
 378                                 return 0;
 379                         dwc->start_config_issued = true;
 380                         cmd |= DWC3_DEPCMD_PARAM(2);
 381                 }
 382
 383                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 384         }
 385
 386         return 0;
 387 }
 388
 389 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 390                 const struct usb_endpoint_descriptor *desc,
 391                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 392                 bool ignore, bool restore)
 393 {
 394         struct dwc3_gadget_ep_cmd_params params;
 395
 396         memset(&params, 0x00, sizeof(params));
 397
 398         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 399                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 400
 401         /* Burst size is only needed in SuperSpeed mode */
 402         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 403                 u32 burst = dep->endpoint.maxburst - 1;
 404
 405                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 406         }
 407
 408         if (ignore)
 409                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 410
 411         if (restore) {
 412                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 413                 params.param2 |= dep->saved_state;
 414         }
 415
 416         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 417                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 418
 419         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 420                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 421                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 422                 dep->stream_capable = true;
 423         }
 424
 425         if (!usb_endpoint_xfer_control(desc))
 426                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 427
 428         /*
 429          * We are doing 1:1 mapping for endpoints, meaning
 430          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 431          * so on. We consider the direction bit as part of the physical
 432          * endpoint number. So USB endpoint 0x81 is 0x03.
 433          */
 434         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 435
 436         /*
 437          * We must use the lower 16 TX FIFOs even though
 438          * HW might have more
 439          */
 440         if (dep->direction)
 441                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 442
 443         if (desc->bInterval) {
 444                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 445                 dep->interval = 1 << (desc->bInterval - 1);
 446         }
 447
 448         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 449                         DWC3_DEPCMD_SETEPCONFIG, &params);
 450 }
 451
 452 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 453 {
 454         struct dwc3_gadget_ep_cmd_params params;
 455
 456         memset(&params, 0x00, sizeof(params));
 457
 458         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 459
 460         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 461                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 462 }
 463
 464 /**
 465  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 466  * @dep: endpoint to be initialized
 467  * @desc: USB Endpoint Descriptor
 468  *
 469  * Caller should take care of locking
 470  */
 471 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 472                 const struct usb_endpoint_descriptor *desc,
 473                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 474                 bool ignore, bool restore)
 475 {
 476         struct dwc3             *dwc = dep->dwc;
 477         u32                     reg;
 478         int                     ret;
 479
 480         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 481
 482         if (!(dep->flags & DWC3_EP_ENABLED)) {
 483                 ret = dwc3_gadget_start_config(dwc, dep);
 484                 if (ret)
 485                         return ret;
 486         }
 487
 488         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 489                         restore);
 490         if (ret)
 491                 return ret;
 492
 493         if (!(dep->flags & DWC3_EP_ENABLED)) {
 494                 struct dwc3_trb *trb_st_hw;
 495                 struct dwc3_trb *trb_link;
 496
 497                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 498                 if (ret)
 499                         return ret;
 500
 501                 dep->endpoint.desc = desc;
 502                 dep->comp_desc = comp_desc;
 503                 dep->type = usb_endpoint_type(desc);
 504                 dep->flags |= DWC3_EP_ENABLED;
 505
 506                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 507                 reg |= DWC3_DALEPENA_EP(dep->number);
 508                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 509
 510                 if (!usb_endpoint_xfer_isoc(desc))
 511                         return 0;
 512
 513                 /* Link TRB for ISOC. The HWO bit is never reset */
 514                 trb_st_hw = &dep->trb_pool[0];
 515
 516                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 517                 memset(trb_link, 0, sizeof(*trb_link));
 518
 519                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 520                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 521                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 522                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 523         }
 524
 525         return 0;
 526 }
 527
 528 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 529 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 530 {
 531         struct dwc3_request             *req;
 532
 533         if (!list_empty(&dep->req_queued)) {
 534                 dwc3_stop_active_transfer(dwc, dep->number, true);
 535
 536                 /* - giveback all requests to gadget driver */
 537                 while (!list_empty(&dep->req_queued)) {
 538                         req = next_request(&dep->req_queued);
 539
 540                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 541                 }
 542         }
 543
 544         while (!list_empty(&dep->request_list)) {
 545                 req = next_request(&dep->request_list);
 546
 547                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 548         }
 549 }
 550
 551 /**
 552  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 553  * @dep: the endpoint to disable
 554  *
 555  * This function also removes requests which are currently processed ny the
 556  * hardware and those which are not yet scheduled.
 557  * Caller should take care of locking.
 558  */
 559 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 560 {
 561         struct dwc3             *dwc = dep->dwc;
 562         u32                     reg;
 563
 564         dwc3_remove_requests(dwc, dep);
 565
 566         /* make sure HW endpoint isn't stalled */
 567         if (dep->flags & DWC3_EP_STALL)
 568                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 569
 570         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 571         reg &= ~DWC3_DALEPENA_EP(dep->number);
 572         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 573
 574         dep->stream_capable = false;
 575         dep->endpoint.desc = NULL;
 576         dep->comp_desc = NULL;
 577         dep->type = 0;
 578         dep->flags = 0;
 579
 580         return 0;
 581 }
 582
 583 /* -------------------------------------------------------------------------- */
 584
 585 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 586                 const struct usb_endpoint_descriptor *desc)
 587 {
 588         return -EINVAL;
 589 }
 590
 591 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 592 {
 593         return -EINVAL;
 594 }
 595
 596 /* -------------------------------------------------------------------------- */
 597
 598 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 599                 const struct usb_endpoint_descriptor *desc)
 600 {
 601         struct dwc3_ep                  *dep;
 602         unsigned long                   flags;
 603         int                             ret;
 604
 605         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 606                 pr_debug("dwc3: invalid parameters\n");
 607                 return -EINVAL;
 608         }
 609
 610         if (!desc->wMaxPacketSize) {
 611                 pr_debug("dwc3: missing wMaxPacketSize\n");
 612                 return -EINVAL;
 613         }
 614
 615         dep = to_dwc3_ep(ep);
 616
 617         if (dep->flags & DWC3_EP_ENABLED) {
 618                 WARN(true, "%s is already enabled\n",
 619                                 dep->name);
 620                 return 0;
 621         }
 622
 623         switch (usb_endpoint_type(desc)) {
 624         case USB_ENDPOINT_XFER_CONTROL:
 625                 strlcat(dep->name, "-control", sizeof(dep->name));
 626                 break;
 627         case USB_ENDPOINT_XFER_ISOC:
 628                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 629                 break;
 630         case USB_ENDPOINT_XFER_BULK:
 631                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 632                 break;
 633         case USB_ENDPOINT_XFER_INT:
 634                 strlcat(dep->name, "-int", sizeof(dep->name));
 635                 break;
 636         default:
 637                 dev_err(dep->dwc->dev, "invalid endpoint transfer type\n");
 638         }
 639
 640         spin_lock_irqsave(&dwc->lock, flags);
 641         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 642         spin_unlock_irqrestore(&dwc->lock, flags);
 643
 644         return ret;
 645 }
 646
 647 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 648 {
 649         struct dwc3_ep                  *dep;
 650         unsigned long                   flags;
 651         int                             ret;
 652
 653         if (!ep) {
 654                 pr_debug("dwc3: invalid parameters\n");
 655                 return -EINVAL;
 656         }
 657
 658         dep = to_dwc3_ep(ep);
 659
 660         if (!(dep->flags & DWC3_EP_ENABLED)) {
 661                 WARN(true, "%s is already disabled\n",
 662                                 dep->name);
 663                 return 0;
 664         }
 665
 666         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 667                         dep->number >> 1,
 668                         (dep->number & 1) ? "in" : "out");
 669
 670         spin_lock_irqsave(&dwc->lock, flags);
 671         ret = __dwc3_gadget_ep_disable(dep);
 672         spin_unlock_irqrestore(&dwc->lock, flags);
 673
 674         return ret;
 675 }
 676
 677 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 678         gfp_t gfp_flags)
 679 {
 680         struct dwc3_request             *req;
 681         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 682
 683         req = kzalloc(sizeof(*req), gfp_flags);
 684         if (!req)
 685                 return NULL;
 686
 687         req->epnum      = dep->number;
 688         req->dep        = dep;
 689
 690         return &req->request;
 691 }
 692
 693 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 694                 struct usb_request *request)
 695 {
 696         struct dwc3_request             *req = to_dwc3_request(request);
 697
 698         kfree(req);
 699 }
 700
 701 /**
 702  * dwc3_prepare_one_trb - setup one TRB from one request
 703  * @dep: endpoint for which this request is prepared
 704  * @req: dwc3_request pointer
 705  */
 706 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 707                 struct dwc3_request *req, dma_addr_t dma,
 708                 unsigned length, unsigned last, unsigned chain, unsigned node)
 709 {
 710         struct dwc3_trb         *trb;
 711
 712         dev_vdbg(dep->dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 713                  dep->name, req, (unsigned long long)dma,
 714                  length, last ? " last" : "", chain ? " chain" : "");
 715
 716
 717         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 718
 719         if (!req->trb) {
 720                 dwc3_gadget_move_request_queued(req);
 721                 req->trb = trb;
 722                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 723                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 724         }
 725
 726         dep->free_slot++;
 727         /* Skip the LINK-TRB on ISOC */
 728         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 729                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 730                 dep->free_slot++;
 731
 732         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 733         trb->bpl = lower_32_bits(dma);
 734         trb->bph = upper_32_bits(dma);
 735
 736         switch (usb_endpoint_type(dep->endpoint.desc)) {
 737         case USB_ENDPOINT_XFER_CONTROL:
 738                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 739                 break;
 740
 741         case USB_ENDPOINT_XFER_ISOC:
 742                 if (!node)
 743                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 744                 else
 745                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 746                 break;
 747
 748         case USB_ENDPOINT_XFER_BULK:
 749         case USB_ENDPOINT_XFER_INT:
 750                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 751                 break;
 752         default:
 753                 /*
 754                  * This is only possible with faulty memory because we
 755                  * checked it already :)
 756                  */
 757                 BUG();
 758         }
 759
 760         if (!req->request.no_interrupt && !chain)
 761                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 762
 763         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 764                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 765                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 766         } else if (last) {
 767                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 768         }
 769
 770         if (chain)
 771                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 772
 773         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 774                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 775
 776         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 777
 778         dwc3_flush_cache((uintptr_t)dma, length);
 779         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
 780 }
 781
 782 /*
 783  * dwc3_prepare_trbs - setup TRBs from requests
 784  * @dep: endpoint for which requests are being prepared
 785  * @starting: true if the endpoint is idle and no requests are queued.
 786  *
 787  * The function goes through the requests list and sets up TRBs for the
 788  * transfers. The function returns once there are no more TRBs available or
 789  * it runs out of requests.
 790  */
 791 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 792 {
 793         struct dwc3_request     *req, *n;
 794         u32                     trbs_left;
 795         u32                     max;
 796
 797         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 798
 799         /* the first request must not be queued */
 800         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 801
 802         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 803         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 804                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 805                 if (trbs_left > max)
 806                         trbs_left = max;
 807         }
 808
 809         /*
 810          * If busy & slot are equal than it is either full or empty. If we are
 811          * starting to process requests then we are empty. Otherwise we are
 812          * full and don't do anything
 813          */
 814         if (!trbs_left) {
 815                 if (!starting)
 816                         return;
 817                 trbs_left = DWC3_TRB_NUM;
 818                 /*
 819                  * In case we start from scratch, we queue the ISOC requests
 820                  * starting from slot 1. This is done because we use ring
 821                  * buffer and have no LST bit to stop us. Instead, we place
 822                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 823                  * after the first request so we start at slot 1 and have
 824                  * 7 requests proceed before we hit the first IOC.
 825                  * Other transfer types don't use the ring buffer and are
 826                  * processed from the first TRB until the last one. Since we
 827                  * don't wrap around we have to start at the beginning.
 828                  */
 829                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 830                         dep->busy_slot = 1;
 831                         dep->free_slot = 1;
 832                 } else {
 833                         dep->busy_slot = 0;
 834                         dep->free_slot = 0;
 835                 }
 836         }
 837
 838         /* The last TRB is a link TRB, not used for xfer */
 839         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 840                 return;
 841
 842         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 843                 unsigned        length;
 844                 dma_addr_t      dma;
 845
 846                 dma = req->request.dma;
 847                 length = req->request.length;
 848
 849                 dwc3_prepare_one_trb(dep, req, dma, length,
 850                                      true, false, 0);
 851
 852                 break;
 853         }
 854 }
 855
 856 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 857                 int start_new)
 858 {
 859         struct dwc3_gadget_ep_cmd_params params;
 860         struct dwc3_request             *req;
 861         struct dwc3                     *dwc = dep->dwc;
 862         int                             ret;
 863         u32                             cmd;
 864
 865         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 866                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 867                 return -EBUSY;
 868         }
 869         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 870
 871         /*
 872          * If we are getting here after a short-out-packet we don't enqueue any
 873          * new requests as we try to set the IOC bit only on the last request.
 874          */
 875         if (start_new) {
 876                 if (list_empty(&dep->req_queued))
 877                         dwc3_prepare_trbs(dep, start_new);
 878
 879                 /* req points to the first request which will be sent */
 880                 req = next_request(&dep->req_queued);
 881         } else {
 882                 dwc3_prepare_trbs(dep, start_new);
 883
 884                 /*
 885                  * req points to the first request where HWO changed from 0 to 1
 886                  */
 887                 req = next_request(&dep->req_queued);
 888         }
 889         if (!req) {
 890                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 891                 return 0;
 892         }
 893
 894         memset(&params, 0, sizeof(params));
 895
 896         if (start_new) {
 897                 params.param0 = upper_32_bits(req->trb_dma);
 898                 params.param1 = lower_32_bits(req->trb_dma);
 899                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 900         } else {
 901                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 902         }
 903
 904         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 905         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 906         if (ret < 0) {
 907                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 908
 909                 /*
 910                  * FIXME we need to iterate over the list of requests
 911                  * here and stop, unmap, free and del each of the linked
 912                  * requests instead of what we do now.
 913                  */
 914                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 915                                 req->direction);
 916                 list_del(&req->list);
 917                 return ret;
 918         }
 919
 920         dep->flags |= DWC3_EP_BUSY;
 921
 922         if (start_new) {
 923                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 924                                 dep->number);
 925                 WARN_ON_ONCE(!dep->resource_index);
 926         }
 927
 928         return 0;
 929 }
 930
 931 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 932                 struct dwc3_ep *dep, u32 cur_uf)
 933 {
 934         u32 uf;
 935
 936         if (list_empty(&dep->request_list)) {
 937                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 938                         dep->name);
 939                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 940                 return;
 941         }
 942
 943         /* 4 micro frames in the future */
 944         uf = cur_uf + dep->interval * 4;
 945
 946         __dwc3_gadget_kick_transfer(dep, uf, 1);
 947 }
 948
 949 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 950                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 951 {
 952         u32 cur_uf, mask;
 953
 954         mask = ~(dep->interval - 1);
 955         cur_uf = event->parameters & mask;
 956
 957         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 958 }
 959
 960 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 961 {
 962         struct dwc3             *dwc = dep->dwc;
 963         int                     ret;
 964
 965         req->request.actual     = 0;
 966         req->request.status     = -EINPROGRESS;
 967         req->direction          = dep->direction;
 968         req->epnum              = dep->number;
 969
 970         /*
 971          * DWC3 hangs on OUT requests smaller than maxpacket size,
 972          * so HACK the request length
 973          */
 974         if (dep->direction == 0 &&
 975             req->request.length < dep->endpoint.maxpacket)
 976                 req->request.length = dep->endpoint.maxpacket;
 977
 978         /*
 979          * We only add to our list of requests now and
 980          * start consuming the list once we get XferNotReady
 981          * IRQ.
 982          *
 983          * That way, we avoid doing anything that we don't need
 984          * to do now and defer it until the point we receive a
 985          * particular token from the Host side.
 986          *
 987          * This will also avoid Host cancelling URBs due to too
 988          * many NAKs.
 989          */
 990         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 991                         dep->direction);
 992         if (ret)
 993                 return ret;
 994
 995         list_add_tail(&req->list, &dep->request_list);
 996
 997         /*
 998          * There are a few special cases:
 999          *
1000          * 1. XferNotReady with empty list of requests. We need to kick the
1001          *    transfer here in that situation, otherwise we will be NAKing
1002          *    forever. If we get XferNotReady before gadget driver has a
1003          *    chance to queue a request, we will ACK the IRQ but won't be
1004          *    able to receive the data until the next request is queued.
1005          *    The following code is handling exactly that.
1006          *
1007          */
1008         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1009                 /*
1010                  * If xfernotready is already elapsed and it is a case
1011                  * of isoc transfer, then issue END TRANSFER, so that
1012                  * you can receive xfernotready again and can have
1013                  * notion of current microframe.
1014                  */
1015                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1016                         if (list_empty(&dep->req_queued)) {
1017                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1018                                 dep->flags = DWC3_EP_ENABLED;
1019                         }
1020                         return 0;
1021                 }
1022
1023                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1024                 if (ret && ret != -EBUSY)
1025                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1026                                         dep->name);
1027                 return ret;
1028         }
1029
1030         /*
1031          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1032          *    kick the transfer here after queuing a request, otherwise the
1033          *    core may not see the modified TRB(s).
1034          */
1035         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1036                         (dep->flags & DWC3_EP_BUSY) &&
1037                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1038                 WARN_ON_ONCE(!dep->resource_index);
1039                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1040                                 false);
1041                 if (ret && ret != -EBUSY)
1042                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1043                                         dep->name);
1044                 return ret;
1045         }
1046
1047         /*
1048          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1049          * right away, otherwise host will not know we have streams to be
1050          * handled.
1051          */
1052         if (dep->stream_capable) {
1053                 int     ret;
1054
1055                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1056                 if (ret && ret != -EBUSY) {
1057                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1058                                         dep->name);
1059                 }
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1066         gfp_t gfp_flags)
1067 {
1068         struct dwc3_request             *req = to_dwc3_request(request);
1069         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1070
1071         unsigned long                   flags;
1072
1073         int                             ret;
1074
1075         spin_lock_irqsave(&dwc->lock, flags);
1076         if (!dep->endpoint.desc) {
1077                 dev_dbg(dep->dwc->dev,
1078                         "trying to queue request %p to disabled %s\n", request,
1079                         ep->name);
1080                 ret = -ESHUTDOWN;
1081                 goto out;
1082         }
1083
1084         if (req->dep != dep) {
1085                 WARN(true, "request %p belongs to '%s'\n", request,
1086                      req->dep->name);
1087                 ret = -EINVAL;
1088                 goto out;
1089         }
1090
1091         dev_vdbg(dep->dwc->dev, "queing request %p to %s length %d\n",
1092                  request, ep->name, request->length);
1093
1094         ret = __dwc3_gadget_ep_queue(dep, req);
1095
1096 out:
1097         spin_unlock_irqrestore(&dwc->lock, flags);
1098
1099         return ret;
1100 }
1101
1102 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1103                 struct usb_request *request)
1104 {
1105         struct dwc3_request             *req = to_dwc3_request(request);
1106         struct dwc3_request             *r = NULL;
1107
1108         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1109         struct dwc3                     *dwc = dep->dwc;
1110
1111         unsigned long                   flags;
1112         int                             ret = 0;
1113
1114         spin_lock_irqsave(&dwc->lock, flags);
1115
1116         list_for_each_entry(r, &dep->request_list, list) {
1117                 if (r == req)
1118                         break;
1119         }
1120
1121         if (r != req) {
1122                 list_for_each_entry(r, &dep->req_queued, list) {
1123                         if (r == req)
1124                                 break;
1125                 }
1126                 if (r == req) {
1127                         /* wait until it is processed */
1128                         dwc3_stop_active_transfer(dwc, dep->number, true);
1129                         goto out1;
1130                 }
1131                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1132                                 request, ep->name);
1133                 ret = -EINVAL;
1134                 goto out0;
1135         }
1136
1137 out1:
1138         /* giveback the request */
1139         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1140
1141 out0:
1142         spin_unlock_irqrestore(&dwc->lock, flags);
1143
1144         return ret;
1145 }
1146
1147 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1148 {
1149         struct dwc3_gadget_ep_cmd_params        params;
1150         struct dwc3                             *dwc = dep->dwc;
1151         int                                     ret;
1152
1153         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1154                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1155                 return -EINVAL;
1156         }
1157
1158         memset(&params, 0x00, sizeof(params));
1159
1160         if (value) {
1161                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1162                                 (!list_empty(&dep->req_queued) ||
1163                                  !list_empty(&dep->request_list)))) {
1164                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1165                                         dep->name);
1166                         return -EAGAIN;
1167                 }
1168
1169                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1170                         DWC3_DEPCMD_SETSTALL, &params);
1171                 if (ret)
1172                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1173                                         dep->name);
1174                 else
1175                         dep->flags |= DWC3_EP_STALL;
1176         } else {
1177                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1178                         DWC3_DEPCMD_CLEARSTALL, &params);
1179                 if (ret)
1180                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1181                                         dep->name);
1182                 else
1183                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1184         }
1185
1186         return ret;
1187 }
1188
1189 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1190 {
1191         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1192
1193         unsigned long                   flags;
1194
1195         int                             ret;
1196
1197         spin_lock_irqsave(&dwc->lock, flags);
1198         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1199         spin_unlock_irqrestore(&dwc->lock, flags);
1200
1201         return ret;
1202 }
1203
1204 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1205 {
1206         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1207         unsigned long                   flags;
1208         int                             ret;
1209
1210         spin_lock_irqsave(&dwc->lock, flags);
1211         dep->flags |= DWC3_EP_WEDGE;
1212
1213         if (dep->number == 0 || dep->number == 1)
1214                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1215         else
1216                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1217         spin_unlock_irqrestore(&dwc->lock, flags);
1218
1219         return ret;
1220 }
1221
1222 /* -------------------------------------------------------------------------- */
1223
1224 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1225         .bLength        = USB_DT_ENDPOINT_SIZE,
1226         .bDescriptorType = USB_DT_ENDPOINT,
1227         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1228 };
1229
1230 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1231         .enable         = dwc3_gadget_ep0_enable,
1232         .disable        = dwc3_gadget_ep0_disable,
1233         .alloc_request  = dwc3_gadget_ep_alloc_request,
1234         .free_request   = dwc3_gadget_ep_free_request,
1235         .queue          = dwc3_gadget_ep0_queue,
1236         .dequeue        = dwc3_gadget_ep_dequeue,
1237         .set_halt       = dwc3_gadget_ep0_set_halt,
1238         .set_wedge      = dwc3_gadget_ep_set_wedge,
1239 };
1240
1241 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1242         .enable         = dwc3_gadget_ep_enable,
1243         .disable        = dwc3_gadget_ep_disable,
1244         .alloc_request  = dwc3_gadget_ep_alloc_request,
1245         .free_request   = dwc3_gadget_ep_free_request,
1246         .queue          = dwc3_gadget_ep_queue,
1247         .dequeue        = dwc3_gadget_ep_dequeue,
1248         .set_halt       = dwc3_gadget_ep_set_halt,
1249         .set_wedge      = dwc3_gadget_ep_set_wedge,
1250 };
1251
1252 /* -------------------------------------------------------------------------- */
1253
1254 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1255 {
1256         struct dwc3             *dwc = gadget_to_dwc(g);
1257         u32                     reg;
1258
1259         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1260         return DWC3_DSTS_SOFFN(reg);
1261 }
1262
1263 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1264 {
1265         struct dwc3             *dwc = gadget_to_dwc(g);
1266
1267         unsigned long           timeout;
1268         unsigned long           flags;
1269
1270         u32                     reg;
1271
1272         int                     ret = 0;
1273
1274         u8                      link_state;
1275         u8                      speed;
1276
1277         spin_lock_irqsave(&dwc->lock, flags);
1278
1279         /*
1280          * According to the Databook Remote wakeup request should
1281          * be issued only when the device is in early suspend state.
1282          *
1283          * We can check that via USB Link State bits in DSTS register.
1284          */
1285         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1286
1287         speed = reg & DWC3_DSTS_CONNECTSPD;
1288         if (speed == DWC3_DSTS_SUPERSPEED) {
1289                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1290                 ret = -EINVAL;
1291                 goto out;
1292         }
1293
1294         link_state = DWC3_DSTS_USBLNKST(reg);
1295
1296         switch (link_state) {
1297         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1298         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1299                 break;
1300         default:
1301                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1302                                 link_state);
1303                 ret = -EINVAL;
1304                 goto out;
1305         }
1306
1307         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1308         if (ret < 0) {
1309                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1310                 goto out;
1311         }
1312
1313         /* Recent versions do this automatically */
1314         if (dwc->revision < DWC3_REVISION_194A) {
1315                 /* write zeroes to Link Change Request */
1316                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1317                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1318                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1319         }
1320
1321         /* poll until Link State changes to ON */
1322         timeout = 1000;
1323
1324         while (timeout--) {
1325                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1326
1327                 /* in HS, means ON */
1328                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1329                         break;
1330         }
1331
1332         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1333                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1334                 ret = -EINVAL;
1335         }
1336
1337 out:
1338         spin_unlock_irqrestore(&dwc->lock, flags);
1339
1340         return ret;
1341 }
1342
1343 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1344                 int is_selfpowered)
1345 {
1346         struct dwc3             *dwc = gadget_to_dwc(g);
1347         unsigned long           flags;
1348
1349         spin_lock_irqsave(&dwc->lock, flags);
1350         dwc->is_selfpowered = !!is_selfpowered;
1351         spin_unlock_irqrestore(&dwc->lock, flags);
1352
1353         return 0;
1354 }
1355
1356 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1357 {
1358         u32                     reg;
1359         u32                     timeout = 500;
1360
1361         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1362         if (is_on) {
1363                 if (dwc->revision <= DWC3_REVISION_187A) {
1364                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1365                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1366                 }
1367
1368                 if (dwc->revision >= DWC3_REVISION_194A)
1369                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1370                 reg |= DWC3_DCTL_RUN_STOP;
1371
1372                 if (dwc->has_hibernation)
1373                         reg |= DWC3_DCTL_KEEP_CONNECT;
1374
1375                 dwc->pullups_connected = true;
1376         } else {
1377                 reg &= ~DWC3_DCTL_RUN_STOP;
1378
1379                 if (dwc->has_hibernation && !suspend)
1380                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1381
1382                 dwc->pullups_connected = false;
1383         }
1384
1385         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386
1387         do {
1388                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1389                 if (is_on) {
1390                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1391                                 break;
1392                 } else {
1393                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1394                                 break;
1395                 }
1396                 timeout--;
1397                 if (!timeout)
1398                         return -ETIMEDOUT;
1399                 udelay(1);
1400         } while (1);
1401
1402         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1403                         dwc->gadget_driver
1404                         ? dwc->gadget_driver->function : "no-function",
1405                         is_on ? "connect" : "disconnect");
1406
1407         return 0;
1408 }
1409
1410 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1411 {
1412         struct dwc3             *dwc = gadget_to_dwc(g);
1413         unsigned long           flags;
1414         int                     ret;
1415
1416         is_on = !!is_on;
1417
1418         spin_lock_irqsave(&dwc->lock, flags);
1419         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1420         spin_unlock_irqrestore(&dwc->lock, flags);
1421
1422         return ret;
1423 }
1424
1425 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1426 {
1427         u32                     reg;
1428
1429         /* Enable all but Start and End of Frame IRQs */
1430         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1431                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1432                         DWC3_DEVTEN_CMDCMPLTEN |
1433                         DWC3_DEVTEN_ERRTICERREN |
1434                         DWC3_DEVTEN_WKUPEVTEN |
1435                         DWC3_DEVTEN_ULSTCNGEN |
1436                         DWC3_DEVTEN_CONNECTDONEEN |
1437                         DWC3_DEVTEN_USBRSTEN |
1438                         DWC3_DEVTEN_DISCONNEVTEN);
1439
1440         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1441 }
1442
1443 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1444 {
1445         /* mask all interrupts */
1446         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1447 }
1448
1449 static int dwc3_gadget_start(struct usb_gadget *g,
1450                 struct usb_gadget_driver *driver)
1451 {
1452         struct dwc3             *dwc = gadget_to_dwc(g);
1453         struct dwc3_ep          *dep;
1454         unsigned long           flags;
1455         int                     ret = 0;
1456         u32                     reg;
1457
1458         spin_lock_irqsave(&dwc->lock, flags);
1459
1460         if (dwc->gadget_driver) {
1461                 dev_err(dwc->dev, "%s is already bound to %s\n",
1462                                 dwc->gadget.name,
1463                                 dwc->gadget_driver->function);
1464                 ret = -EBUSY;
1465                 goto err1;
1466         }
1467
1468         dwc->gadget_driver      = driver;
1469
1470         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1471         reg &= ~(DWC3_DCFG_SPEED_MASK);
1472
1473         /**
1474          * WORKAROUND: DWC3 revision < 2.20a have an issue
1475          * which would cause metastability state on Run/Stop
1476          * bit if we try to force the IP to USB2-only mode.
1477          *
1478          * Because of that, we cannot configure the IP to any
1479          * speed other than the SuperSpeed
1480          *
1481          * Refers to:
1482          *
1483          * STAR#9000525659: Clock Domain Crossing on DCTL in
1484          * USB 2.0 Mode
1485          */
1486         if (dwc->revision < DWC3_REVISION_220A) {
1487                 reg |= DWC3_DCFG_SUPERSPEED;
1488         } else {
1489                 switch (dwc->maximum_speed) {
1490                 case USB_SPEED_LOW:
1491                         reg |= DWC3_DSTS_LOWSPEED;
1492                         break;
1493                 case USB_SPEED_FULL:
1494                         reg |= DWC3_DSTS_FULLSPEED1;
1495                         break;
1496                 case USB_SPEED_HIGH:
1497                         reg |= DWC3_DSTS_HIGHSPEED;
1498                         break;
1499                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1500                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1501                 default:
1502                         reg |= DWC3_DSTS_SUPERSPEED;
1503                 }
1504         }
1505         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1506
1507         dwc->start_config_issued = false;
1508
1509         /* Start with SuperSpeed Default */
1510         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1511
1512         dep = dwc->eps[0];
1513         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1514                         false);
1515         if (ret) {
1516                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1517                 goto err2;
1518         }
1519
1520         dep = dwc->eps[1];
1521         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1522                         false);
1523         if (ret) {
1524                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1525                 goto err3;
1526         }
1527
1528         /* begin to receive SETUP packets */
1529         dwc->ep0state = EP0_SETUP_PHASE;
1530         dwc3_ep0_out_start(dwc);
1531
1532         dwc3_gadget_enable_irq(dwc);
1533
1534         spin_unlock_irqrestore(&dwc->lock, flags);
1535
1536         return 0;
1537
1538 err3:
1539         __dwc3_gadget_ep_disable(dwc->eps[0]);
1540
1541 err2:
1542         dwc->gadget_driver = NULL;
1543
1544 err1:
1545         spin_unlock_irqrestore(&dwc->lock, flags);
1546
1547         return ret;
1548 }
1549
1550 static int dwc3_gadget_stop(struct usb_gadget *g)
1551 {
1552         struct dwc3             *dwc = gadget_to_dwc(g);
1553         unsigned long           flags;
1554
1555         spin_lock_irqsave(&dwc->lock, flags);
1556
1557         dwc3_gadget_disable_irq(dwc);
1558         __dwc3_gadget_ep_disable(dwc->eps[0]);
1559         __dwc3_gadget_ep_disable(dwc->eps[1]);
1560
1561         dwc->gadget_driver      = NULL;
1562
1563         spin_unlock_irqrestore(&dwc->lock, flags);
1564
1565         return 0;
1566 }
1567
1568 static const struct usb_gadget_ops dwc3_gadget_ops = {
1569         .get_frame              = dwc3_gadget_get_frame,
1570         .wakeup                 = dwc3_gadget_wakeup,
1571         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1572         .pullup                 = dwc3_gadget_pullup,
1573         .udc_start              = dwc3_gadget_start,
1574         .udc_stop               = dwc3_gadget_stop,
1575 };
1576
1577 /* -------------------------------------------------------------------------- */
1578
1579 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1580                 u8 num, u32 direction)
1581 {
1582         struct dwc3_ep                  *dep;
1583         u8                              i;
1584
1585         for (i = 0; i < num; i++) {
1586                 u8 epnum = (i << 1) | (!!direction);
1587
1588                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1589                 if (!dep)
1590                         return -ENOMEM;
1591
1592                 dep->dwc = dwc;
1593                 dep->number = epnum;
1594                 dep->direction = !!direction;
1595                 dwc->eps[epnum] = dep;
1596
1597                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1598                                 (epnum & 1) ? "in" : "out");
1599
1600                 dep->endpoint.name = dep->name;
1601
1602                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1603
1604                 if (epnum == 0 || epnum == 1) {
1605                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1606                         dep->endpoint.maxburst = 1;
1607                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1608                         if (!epnum)
1609                                 dwc->gadget.ep0 = &dep->endpoint;
1610                 } else {
1611                         int             ret;
1612
1613                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1614                         dep->endpoint.max_streams = 15;
1615                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1616                         list_add_tail(&dep->endpoint.ep_list,
1617                                         &dwc->gadget.ep_list);
1618
1619                         ret = dwc3_alloc_trb_pool(dep);
1620                         if (ret)
1621                                 return ret;
1622                 }
1623
1624                 INIT_LIST_HEAD(&dep->request_list);
1625                 INIT_LIST_HEAD(&dep->req_queued);
1626         }
1627
1628         return 0;
1629 }
1630
1631 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1632 {
1633         int                             ret;
1634
1635         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1636
1637         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1638         if (ret < 0) {
1639                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1640                 return ret;
1641         }
1642
1643         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1644         if (ret < 0) {
1645                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1646                 return ret;
1647         }
1648
1649         return 0;
1650 }
1651
1652 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1653 {
1654         struct dwc3_ep                  *dep;
1655         u8                              epnum;
1656
1657         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1658                 dep = dwc->eps[epnum];
1659                 if (!dep)
1660                         continue;
1661                 /*
1662                  * Physical endpoints 0 and 1 are special; they form the
1663                  * bi-directional USB endpoint 0.
1664                  *
1665                  * For those two physical endpoints, we don't allocate a TRB
1666                  * pool nor do we add them the endpoints list. Due to that, we
1667                  * shouldn't do these two operations otherwise we would end up
1668                  * with all sorts of bugs when removing dwc3.ko.
1669                  */
1670                 if (epnum != 0 && epnum != 1) {
1671                         dwc3_free_trb_pool(dep);
1672                         list_del(&dep->endpoint.ep_list);
1673                 }
1674
1675                 kfree(dep);
1676         }
1677 }
1678
1679 /* -------------------------------------------------------------------------- */
1680
1681 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1682                 struct dwc3_request *req, struct dwc3_trb *trb,
1683                 const struct dwc3_event_depevt *event, int status)
1684 {
1685         unsigned int            count;
1686         unsigned int            s_pkt = 0;
1687         unsigned int            trb_status;
1688
1689         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1690                 /*
1691                  * We continue despite the error. There is not much we
1692                  * can do. If we don't clean it up we loop forever. If
1693                  * we skip the TRB then it gets overwritten after a
1694                  * while since we use them in a ring buffer. A BUG()
1695                  * would help. Lets hope that if this occurs, someone
1696                  * fixes the root cause instead of looking away :)
1697                  */
1698                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1699                                 dep->name, trb);
1700         count = trb->size & DWC3_TRB_SIZE_MASK;
1701
1702         if (dep->direction) {
1703                 if (count) {
1704                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1705                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1706                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1707                                                 dep->name);
1708                                 /*
1709                                  * If missed isoc occurred and there is
1710                                  * no request queued then issue END
1711                                  * TRANSFER, so that core generates
1712                                  * next xfernotready and we will issue
1713                                  * a fresh START TRANSFER.
1714                                  * If there are still queued request
1715                                  * then wait, do not issue either END
1716                                  * or UPDATE TRANSFER, just attach next
1717                                  * request in request_list during
1718                                  * giveback.If any future queued request
1719                                  * is successfully transferred then we
1720                                  * will issue UPDATE TRANSFER for all
1721                                  * request in the request_list.
1722                                  */
1723                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1724                         } else {
1725                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1726                                                 dep->name);
1727                                 status = -ECONNRESET;
1728                         }
1729                 } else {
1730                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1731                 }
1732         } else {
1733                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1734                         s_pkt = 1;
1735         }
1736
1737         /*
1738          * We assume here we will always receive the entire data block
1739          * which we should receive. Meaning, if we program RX to
1740          * receive 4K but we receive only 2K, we assume that's all we
1741          * should receive and we simply bounce the request back to the
1742          * gadget driver for further processing.
1743          */
1744         req->request.actual += req->request.length - count;
1745         if (s_pkt)
1746                 return 1;
1747         if ((event->status & DEPEVT_STATUS_LST) &&
1748                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1749                                 DWC3_TRB_CTRL_HWO)))
1750                 return 1;
1751         if ((event->status & DEPEVT_STATUS_IOC) &&
1752                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1753                 return 1;
1754         return 0;
1755 }
1756
1757 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1758                 const struct dwc3_event_depevt *event, int status)
1759 {
1760         struct dwc3_request     *req;
1761         struct dwc3_trb         *trb;
1762         unsigned int            slot;
1763
1764         req = next_request(&dep->req_queued);
1765         if (!req) {
1766                 WARN_ON_ONCE(1);
1767                 return 1;
1768         }
1769
1770         slot = req->start_slot;
1771         if ((slot == DWC3_TRB_NUM - 1) &&
1772             usb_endpoint_xfer_isoc(dep->endpoint.desc))
1773                 slot++;
1774         slot %= DWC3_TRB_NUM;
1775         trb = &dep->trb_pool[slot];
1776
1777         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
1778         __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1779         dwc3_gadget_giveback(dep, req, status);
1780
1781         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1782                         list_empty(&dep->req_queued)) {
1783                 if (list_empty(&dep->request_list)) {
1784                         /*
1785                          * If there is no entry in request list then do
1786                          * not issue END TRANSFER now. Just set PENDING
1787                          * flag, so that END TRANSFER is issued when an
1788                          * entry is added into request list.
1789                          */
1790                         dep->flags = DWC3_EP_PENDING_REQUEST;
1791                 } else {
1792                         dwc3_stop_active_transfer(dwc, dep->number, true);
1793                         dep->flags = DWC3_EP_ENABLED;
1794                 }
1795                 return 1;
1796         }
1797
1798         return 1;
1799 }
1800
1801 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1802                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1803 {
1804         unsigned                status = 0;
1805         int                     clean_busy;
1806
1807         if (event->status & DEPEVT_STATUS_BUSERR)
1808                 status = -ECONNRESET;
1809
1810         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1811         if (clean_busy)
1812                 dep->flags &= ~DWC3_EP_BUSY;
1813
1814         /*
1815          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1816          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1817          */
1818         if (dwc->revision < DWC3_REVISION_183A) {
1819                 u32             reg;
1820                 int             i;
1821
1822                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1823                         dep = dwc->eps[i];
1824
1825                         if (!(dep->flags & DWC3_EP_ENABLED))
1826                                 continue;
1827
1828                         if (!list_empty(&dep->req_queued))
1829                                 return;
1830                 }
1831
1832                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1833                 reg |= dwc->u1u2;
1834                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1835
1836                 dwc->u1u2 = 0;
1837         }
1838 }
1839
1840 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1841                 const struct dwc3_event_depevt *event)
1842 {
1843         struct dwc3_ep          *dep;
1844         u8                      epnum = event->endpoint_number;
1845
1846         dep = dwc->eps[epnum];
1847
1848         if (!(dep->flags & DWC3_EP_ENABLED))
1849                 return;
1850
1851         if (epnum == 0 || epnum == 1) {
1852                 dwc3_ep0_interrupt(dwc, event);
1853                 return;
1854         }
1855
1856         switch (event->endpoint_event) {
1857         case DWC3_DEPEVT_XFERCOMPLETE:
1858                 dep->resource_index = 0;
1859
1860                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1861                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1862                                         dep->name);
1863                         return;
1864                 }
1865
1866                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1867                 break;
1868         case DWC3_DEPEVT_XFERINPROGRESS:
1869                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1870                 break;
1871         case DWC3_DEPEVT_XFERNOTREADY:
1872                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1873                         dwc3_gadget_start_isoc(dwc, dep, event);
1874                 } else {
1875                         int ret;
1876
1877                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1878                                         dep->name, event->status &
1879                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1880                                         ? "Transfer Active"
1881                                         : "Transfer Not Active");
1882
1883                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1884                         if (!ret || ret == -EBUSY)
1885                                 return;
1886
1887                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1888                                         dep->name);
1889                 }
1890
1891                 break;
1892         case DWC3_DEPEVT_STREAMEVT:
1893                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1894                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1895                                         dep->name);
1896                         return;
1897                 }
1898
1899                 switch (event->status) {
1900                 case DEPEVT_STREAMEVT_FOUND:
1901                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1902                                         event->parameters);
1903
1904                         break;
1905                 case DEPEVT_STREAMEVT_NOTFOUND:
1906                         /* FALLTHROUGH */
1907                 default:
1908                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1909                 }
1910                 break;
1911         case DWC3_DEPEVT_RXTXFIFOEVT:
1912                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1913                 break;
1914         case DWC3_DEPEVT_EPCMDCMPLT:
1915                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1916                 break;
1917         }
1918 }
1919
1920 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1921 {
1922         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1923                 spin_unlock(&dwc->lock);
1924                 dwc->gadget_driver->disconnect(&dwc->gadget);
1925                 spin_lock(&dwc->lock);
1926         }
1927 }
1928
1929 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1930 {
1931         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1932                 spin_unlock(&dwc->lock);
1933                 dwc->gadget_driver->suspend(&dwc->gadget);
1934                 spin_lock(&dwc->lock);
1935         }
1936 }
1937
1938 static void dwc3_resume_gadget(struct dwc3 *dwc)
1939 {
1940         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1941                 spin_unlock(&dwc->lock);
1942                 dwc->gadget_driver->resume(&dwc->gadget);
1943         }
1944 }
1945
1946 static void dwc3_reset_gadget(struct dwc3 *dwc)
1947 {
1948         if (!dwc->gadget_driver)
1949                 return;
1950
1951         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1952                 spin_unlock(&dwc->lock);
1953                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1954                 spin_lock(&dwc->lock);
1955         }
1956 }
1957
1958 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1959 {
1960         struct dwc3_ep *dep;
1961         struct dwc3_gadget_ep_cmd_params params;
1962         u32 cmd;
1963         int ret;
1964
1965         dep = dwc->eps[epnum];
1966
1967         if (!dep->resource_index)
1968                 return;
1969
1970         /*
1971          * NOTICE: We are violating what the Databook says about the
1972          * EndTransfer command. Ideally we would _always_ wait for the
1973          * EndTransfer Command Completion IRQ, but that's causing too
1974          * much trouble synchronizing between us and gadget driver.
1975          *
1976          * We have discussed this with the IP Provider and it was
1977          * suggested to giveback all requests here, but give HW some
1978          * extra time to synchronize with the interconnect. We're using
1979          * an arbitraty 100us delay for that.
1980          *
1981          * Note also that a similar handling was tested by Synopsys
1982          * (thanks a lot Paul) and nothing bad has come out of it.
1983          * In short, what we're doing is:
1984          *
1985          * - Issue EndTransfer WITH CMDIOC bit set
1986          * - Wait 100us
1987          */
1988
1989         cmd = DWC3_DEPCMD_ENDTRANSFER;
1990         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1991         cmd |= DWC3_DEPCMD_CMDIOC;
1992         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1993         memset(&params, 0, sizeof(params));
1994         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1995         WARN_ON_ONCE(ret);
1996         dep->resource_index = 0;
1997         dep->flags &= ~DWC3_EP_BUSY;
1998         udelay(100);
1999 }
2000
2001 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2002 {
2003         u32 epnum;
2004
2005         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2006                 struct dwc3_ep *dep;
2007
2008                 dep = dwc->eps[epnum];
2009                 if (!dep)
2010                         continue;
2011
2012                 if (!(dep->flags & DWC3_EP_ENABLED))
2013                         continue;
2014
2015                 dwc3_remove_requests(dwc, dep);
2016         }
2017 }
2018
2019 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2020 {
2021         u32 epnum;
2022
2023         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2024                 struct dwc3_ep *dep;
2025                 struct dwc3_gadget_ep_cmd_params params;
2026                 int ret;
2027
2028                 dep = dwc->eps[epnum];
2029                 if (!dep)
2030                         continue;
2031
2032                 if (!(dep->flags & DWC3_EP_STALL))
2033                         continue;
2034
2035                 dep->flags &= ~DWC3_EP_STALL;
2036
2037                 memset(&params, 0, sizeof(params));
2038                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2039                                 DWC3_DEPCMD_CLEARSTALL, &params);
2040                 WARN_ON_ONCE(ret);
2041         }
2042 }
2043
2044 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2045 {
2046         int                     reg;
2047
2048         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2049         reg &= ~DWC3_DCTL_INITU1ENA;
2050         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2051
2052         reg &= ~DWC3_DCTL_INITU2ENA;
2053         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2054
2055         dwc3_disconnect_gadget(dwc);
2056         dwc->start_config_issued = false;
2057
2058         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2059         dwc->setup_packet_pending = false;
2060         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2061 }
2062
2063 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2064 {
2065         u32                     reg;
2066
2067         /*
2068          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2069          * would cause a missing Disconnect Event if there's a
2070          * pending Setup Packet in the FIFO.
2071          *
2072          * There's no suggested workaround on the official Bug
2073          * report, which states that "unless the driver/application
2074          * is doing any special handling of a disconnect event,
2075          * there is no functional issue".
2076          *
2077          * Unfortunately, it turns out that we _do_ some special
2078          * handling of a disconnect event, namely complete all
2079          * pending transfers, notify gadget driver of the
2080          * disconnection, and so on.
2081          *
2082          * Our suggested workaround is to follow the Disconnect
2083          * Event steps here, instead, based on a setup_packet_pending
2084          * flag. Such flag gets set whenever we have a XferNotReady
2085          * event on EP0 and gets cleared on XferComplete for the
2086          * same endpoint.
2087          *
2088          * Refers to:
2089          *
2090          * STAR#9000466709: RTL: Device : Disconnect event not
2091          * generated if setup packet pending in FIFO
2092          */
2093         if (dwc->revision < DWC3_REVISION_188A) {
2094                 if (dwc->setup_packet_pending)
2095                         dwc3_gadget_disconnect_interrupt(dwc);
2096         }
2097
2098         dwc3_reset_gadget(dwc);
2099
2100         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2101         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2102         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2103         dwc->test_mode = false;
2104
2105         dwc3_stop_active_transfers(dwc);
2106         dwc3_clear_stall_all_ep(dwc);
2107         dwc->start_config_issued = false;
2108
2109         /* Reset device address to zero */
2110         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2111         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2112         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2113 }
2114
2115 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2116 {
2117         u32 reg;
2118         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2119
2120         /*
2121          * We change the clock only at SS but I dunno why I would want to do
2122          * this. Maybe it becomes part of the power saving plan.
2123          */
2124
2125         if (speed != DWC3_DSTS_SUPERSPEED)
2126                 return;
2127
2128         /*
2129          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2130          * each time on Connect Done.
2131          */
2132         if (!usb30_clock)
2133                 return;
2134
2135         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2136         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2137         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2138 }
2139
2140 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2141 {
2142         struct dwc3_ep          *dep;
2143         int                     ret;
2144         u32                     reg;
2145         u8                      speed;
2146
2147         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2148         speed = reg & DWC3_DSTS_CONNECTSPD;
2149         dwc->speed = speed;
2150
2151         dwc3_update_ram_clk_sel(dwc, speed);
2152
2153         switch (speed) {
2154         case DWC3_DCFG_SUPERSPEED:
2155                 /*
2156                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2157                  * would cause a missing USB3 Reset event.
2158                  *
2159                  * In such situations, we should force a USB3 Reset
2160                  * event by calling our dwc3_gadget_reset_interrupt()
2161                  * routine.
2162                  *
2163                  * Refers to:
2164                  *
2165                  * STAR#9000483510: RTL: SS : USB3 reset event may
2166                  * not be generated always when the link enters poll
2167                  */
2168                 if (dwc->revision < DWC3_REVISION_190A)
2169                         dwc3_gadget_reset_interrupt(dwc);
2170
2171                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2172                 dwc->gadget.ep0->maxpacket = 512;
2173                 dwc->gadget.speed = USB_SPEED_SUPER;
2174                 break;
2175         case DWC3_DCFG_HIGHSPEED:
2176                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2177                 dwc->gadget.ep0->maxpacket = 64;
2178                 dwc->gadget.speed = USB_SPEED_HIGH;
2179                 break;
2180         case DWC3_DCFG_FULLSPEED2:
2181         case DWC3_DCFG_FULLSPEED1:
2182                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2183                 dwc->gadget.ep0->maxpacket = 64;
2184                 dwc->gadget.speed = USB_SPEED_FULL;
2185                 break;
2186         case DWC3_DCFG_LOWSPEED:
2187                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2188                 dwc->gadget.ep0->maxpacket = 8;
2189                 dwc->gadget.speed = USB_SPEED_LOW;
2190                 break;
2191         }
2192
2193         /* Enable USB2 LPM Capability */
2194
2195         if ((dwc->revision > DWC3_REVISION_194A)
2196                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2197                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2198                 reg |= DWC3_DCFG_LPM_CAP;
2199                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2200
2201                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2202                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2203
2204                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2205
2206                 /*
2207                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2208                  * DCFG.LPMCap is set, core responses with an ACK and the
2209                  * BESL value in the LPM token is less than or equal to LPM
2210                  * NYET threshold.
2211                  */
2212                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2213                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2214
2215                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2216                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2217
2218                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2219         } else {
2220                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2221                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2222                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2223         }
2224
2225         dep = dwc->eps[0];
2226         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2227                         false);
2228         if (ret) {
2229                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2230                 return;
2231         }
2232
2233         dep = dwc->eps[1];
2234         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2235                         false);
2236         if (ret) {
2237                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2238                 return;
2239         }
2240
2241         /*
2242          * Configure PHY via GUSB3PIPECTLn if required.
2243          *
2244          * Update GTXFIFOSIZn
2245          *
2246          * In both cases reset values should be sufficient.
2247          */
2248 }
2249
2250 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2251 {
2252         /*
2253          * TODO take core out of low power mode when that's
2254          * implemented.
2255          */
2256
2257         dwc->gadget_driver->resume(&dwc->gadget);
2258 }
2259
2260 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2261                 unsigned int evtinfo)
2262 {
2263         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2264         unsigned int            pwropt;
2265
2266         /*
2267          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2268          * Hibernation mode enabled which would show up when device detects
2269          * host-initiated U3 exit.
2270          *
2271          * In that case, device will generate a Link State Change Interrupt
2272          * from U3 to RESUME which is only necessary if Hibernation is
2273          * configured in.
2274          *
2275          * There are no functional changes due to such spurious event and we
2276          * just need to ignore it.
2277          *
2278          * Refers to:
2279          *
2280          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2281          * operational mode
2282          */
2283         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2284         if ((dwc->revision < DWC3_REVISION_250A) &&
2285                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2286                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2287                                 (next == DWC3_LINK_STATE_RESUME)) {
2288                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2289                         return;
2290                 }
2291         }
2292
2293         /*
2294          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2295          * on the link partner, the USB session might do multiple entry/exit
2296          * of low power states before a transfer takes place.
2297          *
2298          * Due to this problem, we might experience lower throughput. The
2299          * suggested workaround is to disable DCTL[12:9] bits if we're
2300          * transitioning from U1/U2 to U0 and enable those bits again
2301          * after a transfer completes and there are no pending transfers
2302          * on any of the enabled endpoints.
2303          *
2304          * This is the first half of that workaround.
2305          *
2306          * Refers to:
2307          *
2308          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2309          * core send LGO_Ux entering U0
2310          */
2311         if (dwc->revision < DWC3_REVISION_183A) {
2312                 if (next == DWC3_LINK_STATE_U0) {
2313                         u32     u1u2;
2314                         u32     reg;
2315
2316                         switch (dwc->link_state) {
2317                         case DWC3_LINK_STATE_U1:
2318                         case DWC3_LINK_STATE_U2:
2319                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2320                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2321                                                 | DWC3_DCTL_ACCEPTU2ENA
2322                                                 | DWC3_DCTL_INITU1ENA
2323                                                 | DWC3_DCTL_ACCEPTU1ENA);
2324
2325                                 if (!dwc->u1u2)
2326                                         dwc->u1u2 = reg & u1u2;
2327
2328                                 reg &= ~u1u2;
2329
2330                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2331                                 break;
2332                         default:
2333                                 /* do nothing */
2334                                 break;
2335                         }
2336                 }
2337         }
2338
2339         switch (next) {
2340         case DWC3_LINK_STATE_U1:
2341                 if (dwc->speed == USB_SPEED_SUPER)
2342                         dwc3_suspend_gadget(dwc);
2343                 break;
2344         case DWC3_LINK_STATE_U2:
2345         case DWC3_LINK_STATE_U3:
2346                 dwc3_suspend_gadget(dwc);
2347                 break;
2348         case DWC3_LINK_STATE_RESUME:
2349                 dwc3_resume_gadget(dwc);
2350                 break;
2351         default:
2352                 /* do nothing */
2353                 break;
2354         }
2355
2356         dwc->link_state = next;
2357 }
2358
2359 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2360                 unsigned int evtinfo)
2361 {
2362         unsigned int is_ss = evtinfo & (1UL << 4);
2363
2364         /**
2365          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2366          * have a known issue which can cause USB CV TD.9.23 to fail
2367          * randomly.
2368          *
2369          * Because of this issue, core could generate bogus hibernation
2370          * events which SW needs to ignore.
2371          *
2372          * Refers to:
2373          *
2374          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2375          * Device Fallback from SuperSpeed
2376          */
2377         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2378                 return;
2379
2380         /* enter hibernation here */
2381 }
2382
2383 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2384                 const struct dwc3_event_devt *event)
2385 {
2386         switch (event->type) {
2387         case DWC3_DEVICE_EVENT_DISCONNECT:
2388                 dwc3_gadget_disconnect_interrupt(dwc);
2389                 break;
2390         case DWC3_DEVICE_EVENT_RESET:
2391                 dwc3_gadget_reset_interrupt(dwc);
2392                 break;
2393         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2394                 dwc3_gadget_conndone_interrupt(dwc);
2395                 break;
2396         case DWC3_DEVICE_EVENT_WAKEUP:
2397                 dwc3_gadget_wakeup_interrupt(dwc);
2398                 break;
2399         case DWC3_DEVICE_EVENT_HIBER_REQ:
2400                 if (!dwc->has_hibernation) {
2401                         WARN(1 ,"unexpected hibernation event\n");
2402                         break;
2403                 }
2404                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2405                 break;
2406         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2407                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2408                 break;
2409         case DWC3_DEVICE_EVENT_EOPF:
2410                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2411                 break;
2412         case DWC3_DEVICE_EVENT_SOF:
2413                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2414                 break;
2415         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2416                 dev_vdbg(dwc->dev, "Erratic Error\n");
2417                 break;
2418         case DWC3_DEVICE_EVENT_CMD_CMPL:
2419                 dev_vdbg(dwc->dev, "Command Complete\n");
2420                 break;
2421         case DWC3_DEVICE_EVENT_OVERFLOW:
2422                 dev_vdbg(dwc->dev, "Overflow\n");
2423                 break;
2424         default:
2425                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2426         }
2427 }
2428
2429 static void dwc3_process_event_entry(struct dwc3 *dwc,
2430                 const union dwc3_event *event)
2431 {
2432         /* Endpoint IRQ, handle it and return early */
2433         if (event->type.is_devspec == 0) {
2434                 /* depevt */
2435                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2436         }
2437
2438         switch (event->type.type) {
2439         case DWC3_EVENT_TYPE_DEV:
2440                 dwc3_gadget_interrupt(dwc, &event->devt);
2441                 break;
2442         /* REVISIT what to do with Carkit and I2C events ? */
2443         default:
2444                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2445         }
2446 }
2447
2448 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2449 {
2450         struct dwc3_event_buffer *evt;
2451         irqreturn_t ret = IRQ_NONE;
2452         int left;
2453         u32 reg;
2454
2455         evt = dwc->ev_buffs[buf];
2456         left = evt->count;
2457
2458         if (!(evt->flags & DWC3_EVENT_PENDING))
2459                 return IRQ_NONE;
2460
2461         while (left > 0) {
2462                 union dwc3_event event;
2463
2464                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2465
2466                 dwc3_process_event_entry(dwc, &event);
2467
2468                 /*
2469                  * FIXME we wrap around correctly to the next entry as
2470                  * almost all entries are 4 bytes in size. There is one
2471                  * entry which has 12 bytes which is a regular entry
2472                  * followed by 8 bytes data. ATM I don't know how
2473                  * things are organized if we get next to the a
2474                  * boundary so I worry about that once we try to handle
2475                  * that.
2476                  */
2477                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2478                 left -= 4;
2479
2480                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2481         }
2482
2483         evt->count = 0;
2484         evt->flags &= ~DWC3_EVENT_PENDING;
2485         ret = IRQ_HANDLED;
2486
2487         /* Unmask interrupt */
2488         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2489         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2490         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2491
2492         return ret;
2493 }
2494
2495 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2496 {
2497         struct dwc3 *dwc = _dwc;
2498         unsigned long flags;
2499         irqreturn_t ret = IRQ_NONE;
2500         int i;
2501
2502         spin_lock_irqsave(&dwc->lock, flags);
2503
2504         for (i = 0; i < dwc->num_event_buffers; i++)
2505                 ret |= dwc3_process_event_buf(dwc, i);
2506
2507         spin_unlock_irqrestore(&dwc->lock, flags);
2508
2509         return ret;
2510 }
2511
2512 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2513 {
2514         struct dwc3_event_buffer *evt;
2515         u32 count;
2516         u32 reg;
2517
2518         evt = dwc->ev_buffs[buf];
2519
2520         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2521         count &= DWC3_GEVNTCOUNT_MASK;
2522         if (!count)
2523                 return IRQ_NONE;
2524
2525         evt->count = count;
2526         evt->flags |= DWC3_EVENT_PENDING;
2527
2528         /* Mask interrupt */
2529         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2530         reg |= DWC3_GEVNTSIZ_INTMASK;
2531         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2532
2533         return IRQ_WAKE_THREAD;
2534 }
2535
2536 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2537 {
2538         struct dwc3                     *dwc = _dwc;
2539         int                             i;
2540         irqreturn_t                     ret = IRQ_NONE;
2541
2542         spin_lock(&dwc->lock);
2543
2544         for (i = 0; i < dwc->num_event_buffers; i++) {
2545                 irqreturn_t status;
2546
2547                 status = dwc3_check_event_buf(dwc, i);
2548                 if (status == IRQ_WAKE_THREAD)
2549                         ret = status;
2550         }
2551
2552         spin_unlock(&dwc->lock);
2553
2554         return ret;
2555 }
2556
2557 /**
2558  * dwc3_gadget_init - Initializes gadget related registers
2559  * @dwc: pointer to our controller context structure
2560  *
2561  * Returns 0 on success otherwise negative errno.
2562  */
2563 int dwc3_gadget_init(struct dwc3 *dwc)
2564 {
2565         int                                     ret;
2566
2567         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2568                                         (unsigned long *)&dwc->ctrl_req_addr);
2569         if (!dwc->ctrl_req) {
2570                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2571                 ret = -ENOMEM;
2572                 goto err0;
2573         }
2574
2575         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2576                                           (unsigned long *)&dwc->ep0_trb_addr);
2577         if (!dwc->ep0_trb) {
2578                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2579                 ret = -ENOMEM;
2580                 goto err1;
2581         }
2582
2583         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2584                                   DWC3_EP0_BOUNCE_SIZE);
2585         if (!dwc->setup_buf) {
2586                 ret = -ENOMEM;
2587                 goto err2;
2588         }
2589
2590         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2591                                         (unsigned long *)&dwc->ep0_bounce_addr);
2592         if (!dwc->ep0_bounce) {
2593                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2594                 ret = -ENOMEM;
2595                 goto err3;
2596         }
2597
2598         dwc->gadget.ops                 = &dwc3_gadget_ops;
2599         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2600         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2601         dwc->gadget.name                = "dwc3-gadget";
2602
2603         /*
2604          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2605          * on ep out.
2606          */
2607         dwc->gadget.quirk_ep_out_aligned_size = true;
2608
2609         /*
2610          * REVISIT: Here we should clear all pending IRQs to be
2611          * sure we're starting from a well known location.
2612          */
2613
2614         ret = dwc3_gadget_init_endpoints(dwc);
2615         if (ret)
2616                 goto err4;
2617
2618         ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
2619         if (ret) {
2620                 dev_err(dwc->dev, "failed to register udc\n");
2621                 goto err4;
2622         }
2623
2624         return 0;
2625
2626 err4:
2627         dwc3_gadget_free_endpoints(dwc);
2628         dma_free_coherent(dwc->ep0_bounce);
2629
2630 err3:
2631         kfree(dwc->setup_buf);
2632
2633 err2:
2634         dma_free_coherent(dwc->ep0_trb);
2635
2636 err1:
2637         dma_free_coherent(dwc->ctrl_req);
2638
2639 err0:
2640         return ret;
2641 }
2642
2643 /* -------------------------------------------------------------------------- */
2644
2645 void dwc3_gadget_exit(struct dwc3 *dwc)
2646 {
2647         usb_del_gadget_udc(&dwc->gadget);
2648
2649         dwc3_gadget_free_endpoints(dwc);
2650
2651         dma_free_coherent(dwc->ep0_bounce);
2652
2653         kfree(dwc->setup_buf);
2654
2655         dma_free_coherent(dwc->ep0_trb);
2656
2657         dma_free_coherent(dwc->ctrl_req);
2658 }
2659
2660 /**
2661  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2662  * @dwc: struct dwce *
2663  *
2664  * Handles ep0 and gadget interrupt
2665  *
2666  * Should be called from dwc3 core.
2667  */
2668 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2669 {
2670         int ret = dwc3_interrupt(0, dwc);
2671
2672         if (ret == IRQ_WAKE_THREAD) {
2673                 int i;
2674                 struct dwc3_event_buffer *evt;
2675
2676                 dwc3_thread_interrupt(0, dwc);
2677
2678                 /* Clean + Invalidate the buffers after touching them */
2679                 for (i = 0; i < dwc->num_event_buffers; i++) {
2680                         evt = dwc->ev_buffs[i];
2681                         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
2682                 }
2683         }
2684 }