======================================================================
+Changes since U-Boot 1.1.4:
+======================================================================
+
+* VoiceBlue update: use new MTD flash partitioning methods, use more
+ reasonable TEXT_BASE, update default environment and enable keyed
+ autoboot.
+ Patch by Ladislav Michl, 16. Aug 2005
+
+* Add forgotten changes for the PLEB 2 Board.
+ Patch by David Snowdon, 13. Aug 2005
+
+* Add support for wrPPMC7xx/74xx boards
+ Patch by Richard Danter, 12 Aug 2005
+
+* Add support for gth2 board
+ Patch by Thomas Lange, Aug 11 2005
+
+* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
+ Patch by Martin Krause, 8 Jun 2006
+
+ This patch supports two serial consoles on boards with
+ a MPC5xxx CPU. The console can be switched at runtime
+ by setting stdin, stdout and stderr to the desired serial
+ interface (serial0 or serial1). The PSCs to be used as
+ console port are definded by CONFIG_PSC_CONSOLE
+ and CONFIG_PSC_CONSOLE2.
+ See README.serial_multi for details.
+
+* Bugfix in I2C initialisation on S3C2400.
+ If the bus is blocked because of a previously interrupted
+ transfer, up to eleven clocks are generated on the I2CSCL
+ line to complete the transfer and to free the bus.
+ With this fix pin I2CSCL (PG6) is really configured as GPIO
+ so the clock pulses are really generated.
+ Patch by Martin Krause, 04 Apr 2006
+
+* Fix DDR6 errata on TQM834x boards
+ Patch by Thomas Waehner, 07 Mar 2006
+
+* Remove obsolete flash driver board/tqm5200/flash.c
+ Patch by Martin Krause, 11 Jan 2006
+
+* Update configuration for CMC-PU2 board
+ Patch by Martin Krause, 17 Nov 2005
+
+* Add support for PS/2 keyboard on TQM85xx board
+ Patch by Martin Krause, 07 Nov 2005
+
+ Tested on a STK85XX baseboard. Make sure the PS/2 controller
+ has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
+
+* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
+ In tsc2000_read_channel() the delay after setting the multiplexer
+ to a temperature channel is increased from 1,5 ms to 10 ms. This
+ is to allow the multiplexer inputs to stabilize after huge steps
+ of the input signal level.
+ Patch by Martin Krause, 08 Nov 2005
+
+* Adjust TQM5200 make targets
+ Make the automatic CS configuration the default.
+ The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
+ and CONFIG_TQM5200_AC are removed.
+ "TQM5200_config" is now the default for STK52XX.200 base boards.
+ On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
+ Patch by Martin Krause, 07 Nov 2005
+
+* Fix setting of environment variable "ver" on trab board
+ The environment variable "ver" is now set before
+ do_auto_update() is called, so that "ver" can be used
+ in USB update scripts.
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix wrong usage of udelay() in led_blink() on trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix udelay bug in vfd.c for trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Disable JFFS2 support for trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Change mtdparts definition on trab board to match current flash map
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix memory init problems on MCC200 board
+
+* Fix IxEthDB.h to compile again
+ Patch by Stefan Roese, 14 Jun 2006
+
+* Minor cleanup for PCS440EP board
+ Patch by Stefan Roese, 13 Jun 2006
+
+* Add MCF5282 support (without preloader)
+ relocate ichache_State to ram
+ u-boot can run from internal flash
+ Add EB+MCF-EV123 board support.
+ Add m68k Boards to MAKEALL
+ Patch from Jens Scharsig, 08 Aug 2005
+
+* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Add EPCS Controller bootrom work-around
+ -When booting from an epcs controller, the epcs bootrom may leave the
+ slave select in an asserted state causing soft reset hang. This
+ patch ensures slave select is negated at reset.
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Update PK1C20 board
+ -Update base addresses for standard configuration
+ -Eliminate use of CACHE_BYPASS in board code
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Fix I/O Macros and mini-app stubs
+ -Fix asm/io.h macros
+ -Eliminate use of CACHE_BYPASS in cpu code
+ -Eliminate assembler warnings
+ -Fix mini-app stubs and force no small data
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Fix U-Boot environment sector protection on MCC200 board
+
+* Minor cleanup for PCS440EP board
+
+* Update PCS440EP port to fit into one flash device (incl. environment)
+ Patch by Stefan Roese, 06 Jun 2006
+
+* Add support for PCS440EP board
+ Patch by Stefan Roese, 02 Jun 2006
+
+* Fix examples/Makefile; some build targets were lost
+
+* Fix watchdog handling in CFI flash driver
+ Just use udelay() when waiting for status changes which will
+ implicitely trigger the watchdog.
+
+* Fix PCI to memory window size problems on PM82x boards
+ We use the "automatic" mode that was used for the MPC8266ADS and
+ MPC8272 boards. Eventually this should be used on all boards?]
+ Patch by Wolfgang Grandegger, 17 Jan 2006
+
+* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
+ Patch by Stefan Roese, 29 May 2006
+
+* Update Intel IXP4xx support
+ - Add IXP4xx NPE ethernet MAC support
+ - Add support for Intel IXDPG425 board
+ - Add support for Prodrive PDNB3 board
+ - Add IRQ support
+ Patch by Stefan Roese, 23 May 2006
+
+* Fix problem in PVR detection for 440GR
+ Patch by Stefan Roese, 18 May 2006
+
+* Fix gcc 3.4.x AFLAGS setting for m68k platform.
+
+* Enable autoboot for M5271EVB board.
+
+* Changed default ramdisk addr in yosemite/yellowstone ports
+ Patch by Stefan Roese, 15 May 2006
+
+* Fix PCMCIA support on virtlab2
+
+* Add support for VirtLab2 board
+ (needed because of differences in the PCMCIA hardware).
+
+* Minor cleanup.
+
+* Update yosemite configuration to enable flash write buffer support
+ Patch by Stefan Roese, 10 May 2006
+
+* Fix compile warnings in common/xyzModem.c
+ Patch by Stefan Roese, 10 May 2006
+
+* Add support for AMCC 440EP Rev C and 440GR Rev B
+ Patch by John Otken, 08 May 2006
+
+* OMAP 5912/OSK: update EMIFS CS1 timings:
+ Problems have been seen in the linux kernel's smc91x network driver
+ due to improper bus timings. The latest 2.6 OMAP kernels currently
+ have a workaround, but this fix belongs in u-boot.
+ Patch by Kevin Hilman, 13 Oct 2005
+
+* Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports
+ Patch by Hiroki Kaminaga, 11 Mar 2006
+
+* Update omap5912osk board support
+ - Fix OMAP support that omap5912osk compiles in current source tree
+ - Update with code from "http://omap.spectrumdigital.com/osk5912"
+ to fix problems with DDR initialization
+ - Fix timer setup
+ - Use CFI flash driver and support complete 32MB of onboard flash
+ - Add "print_cpuinfo()" and "checkboard()" functions to display
+ CPU (with frequency) and Board infos
+ Patch by Stefan Roese, 10 May 2006
+
+* Fix watchdog issues for ColdFire boards.
+
+* Add M5271EVB board support.
+
+* Make R5200 specific low level initialization board conditional.
+
+* Update CPU target identification strings for ColdFire family.
+
+* Update register definitions for MCF5271.
+
+* Fix serial console support for MCF5271.
+
+* Fixes for gcc 3.4 based m68k toolchain,
+ based on patch by Jate Sujjavanich.
+
+* Fix lowboot support on MCC200 board
+
+* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
+ - Removed MPC8349ADS port
+ - Added PCI support to MPC8349ADS
+ - reworked memory map to allow mapping of all regions with BATs
+ Patch by Kumar Gala, 20 Apr 2006
+
+* Coding Style cleanup
+
+* Write RTC seconds first to maintain settings integrity per
+ Maxim/Dallas DS1306 data sheet.
+ Patch by Alan J. Luse, 02 May 2006
+
+* Scheduled for removal: strnicmp() which is unused
+
+* Update for Intel Monahans boards:
+ - support for magic key detection and handling on delta board
+ - NAND support for zylonite board + some minor cleanup
+
+* Declare load_serial_ymodem() when using CFG_CMD_LOADB.
+ Patch by Jon Loeliger, 01 May 2006
+
+* Fixed handling of bad checksums with "mkimage -l"
+
+* Added support for BC3450 board
+ Patch by Stefan Strobl, 21 Oct 2005
+
+* Update for NC650 board:
+ - Support rev1 and rev2 hardware
+ - adapt to new NAND layer
+ - add CP850 configuration based on NC650
+
+* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
+ is configured; othrwise DMA accesses aren't cache coherent which
+ causes for example USB to fail.
+
+* Some code cleanup
+
+* Fix dbau1x00 boards broken by dbau1550 patch
+ PLL:s were not set for boards other than 1550.
+ Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
+ Default boot is now bootp for cards other than 1550.
+ Patch by Thomas Lange, 10 Aug 2005
+
+* Fixes common/cmd_flash.c:
+ - fix some compiler/parser error, if using m68k tool chain
+ - optical fix for protect on/off all messages, if using more
+ then one bank
+ Patch by Jens Scharsig, 28 Jul 2005
+
+* Fix Quad UART mapping on MCC200 board due to new HW revision
+
+* Fix JFFS2 support for legacy NAND driver.
+
+* Remove dependencies between DoC code and old legacy NAND driver.
+
+* Fix PM828_PCI target, for which PCI was *not* configured in.
+
+* Fix Lite5200B support: initialize SDelay register
+ See Freescale's AN3221 "MPC5200B SDRAM Initialization and
+ Configuration", 3.3.1 SDelay--MBAR + 0x0190
+
+* Changes/fixes for drivers/cfi_flash.c:
+
+ - Add Intel legacy lock/unlock support to common CFI driver
+
+ On some Intel flash's (e.g. Intel J3) legacy unlocking is
+ supported, meaning that unlocking of one sector will unlock
+ all sectors of this bank. Using this feature, unlocking
+ of all sectors upon startup (via env var "unlock=yes") will
+ get much faster.
+
+ - Fixed problem with multiple reads of envronment variable
+ "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
+
+ - Removed unwanted linefeeds from "protect" command when
+ CFG_FLASH_PROTECTION is enabled.
+
+ - Changed p3p400 board to use CFG_FLASH_PROTECTION
+
+ Patch by Stefan Roese, 01 Apr 2006
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Correctly handle the cases where CFG_HZ != 1000 (several
+ XScale-based boards)
+ - Fix the timeout calculation of buffered writes (off by a
+ factor of 1000)
+ Patch by Anders Larsen, 31 Mar 2006
+
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+ 405 SDRAM: - The SDRAM parameters can now be defined in the board
+ config file and the 405 SDRAM controller values will
+ be calculated upon bootup (see PPChameleonEVB).
+ When those settings are not defined in the board
+ config file, the register setup will be as it is now,
+ so this implementation should not break any current
+ design using this code.
+
+ Thanks to Andrea Marson from DAVE for this patch.
+
+ 440 DDR: - Added function sdram_tr1_set to auto calculate the
+ TR1 value for the DDR.
+ - Added ECC support (see p3p440).
+
+ Patch by Stefan Roese, 17 Mar 2006
+
+* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
+ Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
+
+* Add support for ymodem protocol download
+ Patch by Stefano Babic, 29 Mar 2006
+
+* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
+ Merge from Markus Klotzbücher's repo, 01 Apr 2006
+
+* GCC-4.x fixes: clean up global data pointer initialization for all
+ boards
+
+* Update for Delta board:
+ - redundant NAND environment
+ - misc Monahans cleanups (remove dead code etc.)
+ - DA9030 Initialization; some minimal changes to PXA I2C driver to
+ make it work with the Monahans.
+ - Make Monahans clock frequency configurable using
+ CFG_MONAHANS_RUN_MODE_OSC_RATIO and
+ CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
+ Merge from Markus Klotzbücher's repo, 25 Mar 2006
+
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
+* Add command for handling DDR ECC registers on MPC8349EE MDS board.
+
+* Fix DDR ECC bit definitions for MPC83xx.
+
+* Add initial support for MPC8349E MDS board.
+
+* Add support for ECC DDR initialization on MPC83xx.
+
+* Add DMA support for MPC83xx.
+
+* Add sync in do_reset() routine for MPC83xx after RPR register
+ was written to. It is need on some targets when BAT translation
+ is enabled.
+
+* Add bit definitions for MPC83xx DDR controller registers.
+
+* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
+
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
+* Add support for DS1374 RTC chip.
+
+* Add support for Lite5200B board.
+ Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
+
+* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
+ timer and cpu_reset code from cpu/$(CPU) into the new
+ cpu/$(CPU)/$(SOC) directories
+ Patch by Andreas Engel, 13 Mar 2006
+
+* Change max size of uncompressed uImage's to 8MByte and add
+ CFG_BOOTM_LEN to adjust this setting.
+
+ As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
+ uImages was restricted to 4MBytes. This default size is now
+ increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
+ in the board config file.
+
+ Patch by Stefan Roese, 13 Mar 2006
+
+* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
+ Patch by Stefan Roese, 13 Mar 2006
+
+* cpu/ppc4xx/start.S : exceptions are enabled after relocation
+ Patch by Cedric Vincent, 06 Jul 2005
+
+* au1x00_eth.c: check malloc return value and abort if it failed
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Change the sequence of events in soft_i2c.c:send_ack() to keep from
+ incorrectly generating start/stop conditions on the bus.
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+ should look at LSB of L1CSRn registers to determine if L1 cache is
+ enabled, not the MSB.
+ Patch by Murray Jensen, 19 Jul 2005
+
+* Fix array overflow with fw_setenv on uninitialised environment
+ Patch by Murray Jensen, 15 Jul 2005
+
+* Add support for EmbeddedPlanet EP88x boards
+ Patch by Yuli Barcohen, 13 Jul 2005
+
+* Remove board specific configuration includes from the common xilinx
+ ethernet and iic adapter code.
+ Patch by Michael Libeskind, 12 Jul 2005
+
+* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add (some) definitions for the MPC85xx local bus controller
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add CPM2 I/O pin functions for MPC85xx processors
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Fix compile problem
+
+* Added PCI support for MPC8349ADS board
+ Patch by Kumar Gala 11 Jan 2006
+
+* Enable address translation on MPC83xx
+ Patch by Kumar Gala, 10 Feb 2006
+
+* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
+ Patch by Kumar Gala, 25 Jan 2006
+
+* Fixed defines for MPC83xx SICRL register to match current specs
+ Patch by Kumar Gala, 23 Jan 2006
+
+* Only disable the MPC83xx watchdog if its enabled out of reset.
+ If its disabled out of reset SW can later enable it if so desired
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow config of GPIO direction & data registers at boot on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Enable time handling on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Make System IO Config Registers board configurable on MPC83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Fixed PCI indirect config ops to handle multiple PCI controllers
+ We need to adjust the bus number we are trying to access based
+ on which PCI controller its on
+ Patch by Kumar Gala, 12 Jan 2006
+
+* Report back PCI bus when doing table based device config
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added support for PCI prefetchable region and BARs
+ If a host controller sets up a region as prefetchable and
+ a device's BAR denotes it as prefetchable, allocate the
+ BAR into the prefetch region.
+
+ If a BAR is prefetchable and no prefetchable region has
+ been setup by the controller we fall back to allocating
+ the BAR into the normally memory region.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add helper function for generic flat device tree fixups for mpc83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for passing initrd information via flat device tree
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added OF_STDOUT_PATH and OF_SOC
+
+ OF_STDOUT_PATH specifies the path to the device the kernel can use
+ for console output
+
+ OF_SOC specifies the proper name of the SOC node if one exists.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow board code to fixup the flat device tree before booting a kernel
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added CONFIG_ options for bd_t and env in flat dev tree
+
+ CONFIG_OF_HAS_BD_T will put a copy of the bd_t
+ into the resulting flat device tree.
+
+ CONFIG_OF_HAS_UBOOT_ENV will copy the environment
+ variables from u-boot into the flat device tree
+
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for the DHCP vendor optional bootfile (#67).
+ Ignores the vendor TFTP server name option (#66).
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
+ Patch by Andy Fleming, 14 Jun 2005
+
+* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
+ Patch by Gerhard Jaeger, 21 Jun 2005
+
+* Add netconsole and some more commands to RPXlite_DW board
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix bad declaration on pci_cfgfunc_nothing
+ Patch by Sam Song, 19 Jun 2005
+
+* Adjust "echo" as a default command
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
+ Patch by KokHow Teh, 16 Jun 2005
+
+* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
+ Patch by Rick Bronson, 15 Jun 2005
+
+* Coding Style cleanup
+
+* Avoid dereferencing NULL in find_cmd() if no valid commands were found
+ Patch by Andrew Dyer, 13 Jun 2005
+
+* Add ADI Blackfin support
+ - add support for Analog Devices Blackfin BF533 CPU
+ - add support for the ADI BF533 Stamp uClinux board
+ - add support for the ADI BF533 EZKit board
+ Patches by Richard Klingler, 11 Jun 2005
+
+* Add loads of ntohl() in image header handling
+ Patch by Steven Scholz, 10 Jun 2005
+
+* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
+ variable to set clock
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* RPXlite configuration fixes
+ - Use correct flash sector size
+ - Use correct memory test end address
+ - Add support for bzip2 compression
+ - Various small fixes
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Memory configuration changes for ZPC.1900 board
+ - Fix SDRAM timing on both local bus and 60x bus
+ - Add support for second flash bank (SIMM)
+ - Change boot flash base
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Add support for Adder boards with 16MB SDRAM;
+ add support for second FEC on Adder87x board.
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Fix conditional for including ks8695eth driver
+ Patch by Greg Ungerer, 04 Jun 2005
+
+* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
+ Patch by Friedrich Lobenstock, 02 Jun 2005
+
+* Fix comment in common/soft_i2c.c
+ Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
+
+* Cleanup compiler warnings.
+ Patch by Greg Ungerer, 21 May 2005
+
+* Word alignment fixes for word aligned NS16550 UART
+ Patch by Jean-Paul Saman, 01 Mar 2005
+
+ Fixes bug with UART that only supports word aligned access: removed
+ "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
+ (broken!) versions of GCC generate byte accesses when encountering
+ the packed attribute regardless if the struct is already correctly
+ aligned for a platform. Peripherals that can only handle word
+ aligned access won't work properly when accessed with byte access.
+ The struct NS16550 is already word aligned for REG_SIZE = 4, so
+ there is no need to packed the struct in that case.
+
+* Fix behaviour if gatewayip is not set
+ Patch by Robin Gilks, 23 Dec 2004
+
+* Fix cleanup for netstart board.
+ Remove build results from repository
+
+* Some code cleanup for GCC 4.x
+
+* Fixes to support environment in NAND flash;
+ enable NAND flash based environment for delta board.
+
+* Add support for Intel Monahans CPU on Zylonite and Delta boards
+ (This is Work in Progress!)
+
+* Add support for TQM8260-AI boards.
+
+* Minor code cleanup
+
+* Merge the new NAND code (testing-NAND brach); see doc/README.nand
+ Rewrite of NAND code based on what is in 2.6.12 Linux kernel
+ Patch by Ladislav Michl, 29 Jun 2005
+
+* Add lowboot target to mcc200 board
+ Patch by Stefan Roese, 4 Mar 2006
+
+* Fix problem with flash_get_size() from CFI driver update
+ Patch by Stefan Roese, 1 Mar 2006
+
+* Make CFG_NO_FLASH work on ARM systems
+ Patch by Markus Klotzbuecher, 27 Feb 2006
+
+* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
+ use hush shell.
+
+* Convert mcc200 to use common CFI flash driver
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Add env-variable "unlock" to handle initial state of sectors
+ (locked/unlocked).
+
+ Only the U-Boot image and it's environment is protected,
+ all other sectors are unprotected (unlocked) if flash
+ hardware protection is used (CFG_FLASH_PROTECTION) and
+ the environment variable "unlock" is set to "yes".
+
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Update drivers/cfi_flash.c:
+ - find_sector() called in both versions of flash_write_cfiword()
+ Patch by Peter Pearse, 27th Feb 2006
+
+* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
+ Patch by Jose Maria Lopez, 16 Jan 2006
+
+* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
+ Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
+
+* Changes/fixes for drivers/cfi_flash.c:
+ We *should* check if there are any error bits if the previous call
+ returned ERR_OK (Otherwise we will have output an error message in
+ flash_status_check() already.) The original code would only check for
+ error bits if flash_status_check() returns ERR_TIMEOUT.
+ Patch by Marcus Hall, 23 Aug 2005
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
+ - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
+ Patch by Sangmoon Kim, 19 Aug 2005
+
+* Fixes for drivers/cfi_flash.c:
+ - Fix wrong timeout value usage in flash_status_check()
+ - Round write_tout up when converting to msec in flash_get_size()
+ - Remove clearing flash status at the end of flash_write_cfibuffer()
+ which sets Intel 28F640J3 flash back to command mode on CSB472
+ Patch by Tolunay Orkun, 02 July 2005
+
+* Add basic support for the SMMACO4 Board from PanDaCom.
+ Patch by Heiko Schocher, 20 Feb 2006
+
+* Add GIT version information (commid ID) to untagged U-Boot versions
+
+ As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
+ of all unreleased (untagged) U-Boot images will be automatically
+ extended upon compiletime with a part of the GIT commit ID and
+ possibly with "dirty" if uncommited changes are detected.
+
+ Here an example for the resulting version:
+ "U-Boot 1.1.4-g3457ac18-dirty"
+
+ The version is now maintained in the toplevel Makefile and the
+ version headers are autogenerated.
+
+ Patch by Stefan Roese, 9 Feb 2006
+
+* Update default environment for INKA4x00 board.
+
+* Convert CPCI750 to use common CFI flash driver
+ Patch by Reinhard Arlt, 8 Feb 2006
+
+* Various changes to esd HH405 board specific files
+ Patch by Matthias Fuchs, 07 Feb 2006
+
+* Cleanup U-Boot boot messages on ARM.
+
+ To match the U-Boot user interface on ARM platforms to the U-Boot
+ standard (as on PPC platforms), some messages with debug character
+ are removed from the default U-Boot build.
+ Enable DEBUG for lib_arm/board.c to enable debug messages.
+ New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
+ Patch by Stefan Roese, 24 Jan 2006
+
+* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
+ Patch by Stefan Roese, 18 Jan 2006
+
+* Add VGA support (CT69000) to CPCI750 board.
+ Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
+ Patch by Reinhard Arlt, 30 Dec 2005
+
+* PMC405 and CPCI405: Moved configuration of pci resources
+ into config file.
+ PMC405 and CPCI2DP: Added firmware download and booting via pci.
+ Patch by Matthias Fuchs, 20 Dec 2005
+
+* Add ColdFire targets to MAKEALL script
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Add support for r5200 board
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Add support for Freescale M5271 processor
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Fix 28F256J3A support on PM520 board
+ (without bank-switching only 32 MB can be accessed)
+
+* Fix mkimage bug with multifile images created on 64 bit systems.
+
+* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
+
+* Fix compiler problem with at91rm9200dk board.
+ Patch by Eugen Bigz, 19 Dec 2005
+
+======================================================================
Changes for U-Boot 1.1.4:
======================================================================
+ * Add support for AMCC 440SPe CPU based eval board (Yucca).
+
+ * Call serial_initialize() before first debug() is used.
+
* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
- Changed GPIO setup to enable another address line in order to
address 64M of FLASH.
* Add support for multiple PHYs.
Tested on the following boards:
- cmcpu2 (at91rm9200/ether.c)
+ cmcpu2 (at91rm9200/ether.c)
PPChameleon (ppc4xx/4xx_enet.c)
- yukon (mpc8220/fec.c)
- uc100 (mpc8xx/fec.c)
- tqm834x (mpc834x/tsec.c) with EEPRO100
+ yukon (mpc8220/fec.c)
+ uc100 (mpc8xx/fec.c)
+ tqm834x (mpc834x/tsec.c) with EEPRO100
lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
Main changes include:
common/miiphyutil.c
The first one is to define a single, static partition:
#undef CONFIG_JFFS2_CMDLINE
- #define CONFIG_JFFS2_DEV "nor0"
- #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
- #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
- #define CONFIG_JFFS2_PART_OFFSET 0x00000000
+ #define CONFIG_JFFS2_DEV "nor0"
+ #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
+ #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
+ #define CONFIG_JFFS2_PART_OFFSET 0x00000000
The second method uses the mtdparts command line option and dynamic
partitioning:
/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
- #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
- #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+ #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
+ #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
Command line of course produces bigger images, and may be inappropriate
for some targets, so by default it's off.
- use -mtune=xscale and -march=armv5 options for PXA
* Patch by Florian Schlote, 08 Sep 2004:
- Add support for SenTec-COBRA5272-board (Coldfire).
+ Add support for SenTec-COBRA5272-board (ColdFire).
* Patch by Gleb Natapov, 07 Sep 2004:
mpc824x: set PCI latency timer to a sane value
* Patch by Stefan Roese, 16 Dez 2004:
- ext2fs support added
- Tundra universe support added
- - Coldfire MCF5249 support added (no preloader needed!)
+ - ColdFire MCF5249 support added (no preloader needed!)
- MCF5249 board TASREG added
- PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
VOM405, WUH405
* Fix NSCU config; add ethernet wakeup code.
-* Add link for preloader for Motorola Coldfire to README.m68k
+* Add link for preloader for Motorola ColdFire to README.m68k
* Patch by Michael Bendzick, 12 Jul 2004:
fix output formatting in drivers/cfi_flash.c
* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004:
- Fixes for Coldfire port
+ Fixes for ColdFire port
* Patch by Brad Kemp, 11 Feb 2004:
Fix CFI flash driver problems
- 4xx: removed spurious MII error messages on "mii info" command.
* Patch by Bernhard Kuhn, 28 Nov 2003:
- add support for Coldfire CPU
+ add support for ColdFire CPU
add support for Motorola M5272C3 and M5282EVB boards
* Patch by Pierre Aubert, 24 Nov 2003:
Bring ARM memory layout in sync with the documentation:
stack and malloc-heap are now located _below_ the U-Boot code
-* Accelerate booting on TRAB board: read and check autoupdate image
+* Accelerate booting on TRAB board: read and check autoupdate image
headers first instead of always reading the whole images.
* Fix type in MPC5XXX code (pointed out by Victor Wren)
* Make 5200 reset command _really_ reset the board, without running
any other code after it
-* Fix errors with flash erase when range spans across banks
+* Fix errors with flash erase when range spans across banks
that are mapped in reverse order
* Fix flash mapping and display on P3G4 board
or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
-* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz)
+* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz)
to allow for more accurate baudrate settings
(error now 0.7% at 115 kbps, instead of 3.5% before)
Update for MPC8266ADS board
* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
- instead CFG_MONITOR_LEN is now only used to determine _at_compile_
+ instead CFG_MONITOR_LEN is now only used to determine _at_compile_
_time_ (!) if the environment is embedded within the U-Boot image,
or in a separate flash sector.
* Patch by Thomas Schäfer, 28 Apr 2003:
Fix SPD handling for 256 ECC DIMM on Walnut
-* Add support for arbitrary bitmaps for TRAB's VFD command;
+* Add support for arbitrary bitmaps for TRAB's VFD command;
allow to pass boot bitmap addresses in environment variables;
allow for zero boot delay
* Add VFD type detection to trab board
-* extend drivers/cs8900.c driver to synchronize ethaddr environment
+* extend drivers/cs8900.c driver to synchronize ethaddr environment
variable with value in the EEPROM
* Patch by Stefan Roese, 10 Feb 2003:
* Patch by Pierre Aubert, 05 Nov 2002
Add support for slave serial Spartan 2 FPGAs
-* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
+* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
drivers
* Add support for log buffer which can be passed to Linux kernel's
#########################################################################
LIST_5xxx=" \
- cpci5200 icecube_5100 icecube_5200 EVAL5200 \
+ BC3450 cpci5200 EVAL5200 icecube_5100 \
+ icecube_5200 lite5200b mcc200 o2dnt \
pf5200 PM520 Total5100 Total5200 \
- Total5200_Rev2 TQM5200_auto o2dnt \
+ Total5200_Rev2 TQM5200 \
"
#########################################################################
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
- ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \
- ETX094 IVMS8 NETVIA svm_sc8xx \
- FADS823 IVMS8_128 NETVIA_V2 SXNI855T \
- FADS850SAR IVMS8_256 NX823 TOP860 \
- FADS860T KUP4K pcu_e TQM823L \
- FLAGADM KUP4X QS823 TQM823L_LCD \
- FPS850L LANTEC QS850 TQM850L \
- GEN860T lwmon QS860T TQM855L \
- GEN860T_SC MBX quantum TQM860L \
- uc100 \
+ EP88x IVML24_256 NETTA_ISDN SPD823TS \
+ ESTEEM192E IVMS8 NETVIA svm_sc8xx \
+ ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
+ FADS823 IVMS8_256 NX823 TOP860 \
+ FADS850SAR KUP4K pcu_e TQM823L \
+ FADS860T KUP4X QS823 TQM823L_LCD \
+ FLAGADM LANTEC QS850 TQM850L \
+ FPS850L lwmon QS860T TQM855L \
+ GEN860T MBX quantum TQM860L \
+ GEN860T_SC uc100 \
v37 \
"
HH405 HUB405 JSE KAREF \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
- ORSG p3p440 PCI405 PIP405 \
- PLU405 PMC405 PPChameleonEVB sbc405 \
- VOH405 VOM405 W7OLMC W7OLMG \
- walnut WUH405 XPEDITE1K yellowstone \
- yosemite yucca \
+ ORSG p3p440 PCI405 pcs440ep \
- PIP405 PLU405 PMC405 PPChameleonEVB \
- sbc405 VOH405 VOM405 W7OLMC \
++ PIP405 PLU405 PMC405 PPChameleonEVB \
++ sbc405 VOH405 VOM405 W7OLMC \
+ W7OLMG walnut WUH405 XPEDITE1K \
- yellowstone yosemite \
++ yellowstone yosemite yucca \
"
#########################################################################
#########################################################################
LIST_83xx=" \
- MPC8349ADS TQM834x\
+ TQM834x MPC8349EMDS \
"
"
LIST_7xx=" \
- BAB7xx CPCI750 ELPPC \
+ BAB7xx CPCI750 ELPPC ppmc7xx \
"
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
- mx1ads mx1fs2 omap1510inn omap1610h2 \
- omap1610inn omap730p2 scb9328 smdk2400 \
- smdk2410 trab VCMA9 versatile \
- versatileab versatilepb voiceblue
+ mx1ads mx1fs2 netstar omap1510inn \
+ omap1610h2 omap1610inn omap730p2 scb9328 \
+ smdk2400 smdk2410 trab VCMA9 \
+ versatile versatileab versatilepb voiceblue
"
#########################################################################
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
- innokom lubbock pxa255_idp wepep250 \
- xaeniax xm250 xsengine \
+ delta innokom lubbock pleb2 \
+ pxa255_idp wepep250 xaeniax xm250 \
+ xsengine zylonite \
"
-LIST_ixp="ixdp425"
+LIST_ixp="ixdp425 ixdpg425 pdnb3"
LIST_arm=" \
LIST_mips5kc="purple"
-LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
+LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
#########################################################################
LIST_nios=" \
- ADNPESC1 ADNPESC1_base_32 \
+ ADNPESC1 ADNPESC1_base_32 \
ADNPESC1_DNPEVA2_base_32 \
- DK1C20 DK1C20_standard_32 \
- DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
+ DK1C20 DK1C20_standard_32 \
+ DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
"
#########################################################################
## Nios-II Systems
#########################################################################
-LIST_nios2="PCI5441 PK1C20"
+LIST_nios2=" \
+ EP1C20 EP1S10 EP1S40 \
+ PCI5441 PK1C20 \
+"
#########################################################################
## MicroBlaze Systems
#########################################################################
-LIST_microblaze="suzaku"
+LIST_microblaze=" \
+ suzaku
+"
+
+#########################################################################
+## ColdFire Systems
+#########################################################################
+
+LIST_coldfire=" \
+ cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \
+ M5271EVB M5272C3 M5282EVB TASREG \
+ r5200 M5271EVB \
+"
#-----------------------------------------------------------------------
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
- ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
+# ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
}
#-----------------------------------------------------------------------
microblaze| \
mips|mips_el| \
nios|nios2| \
- x86|I486)
+ x86|I486| \
+ coldfire)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# MA 02111-1307 USA
#
+VERSION = 1
+PATCHLEVEL = 1
+SUBLEVEL = 4
+EXTRAVERSION =
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+VERSION_FILE = include/version_autogenerated.h
+
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/i386/ \
-e s/sun4u/sparc64/ \
# load ARCH, BOARD, and CPU configuration
include include/config.mk
export ARCH CPU BOARD VENDOR SOC
-# load other configuration
-include $(TOPDIR)/config.mk
-
ifndef CROSS_COMPILE
ifeq ($(HOSTARCH),ppc)
CROSS_COMPILE =
ifeq ($(ARCH),microblaze)
CROSS_COMPILE = mb-
endif
+ifeq ($(ARCH),blackfin)
+CROSS_COMPILE = bfin-elf-
+endif
endif
endif
export CROSS_COMPILE
+# load other configuration
+include $(TOPDIR)/config.mk
+
+
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
+ifeq ($(CPU),bf533)
+OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
+OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
+endif
LIBS = lib_generic/libgeneric.a
LIBS += board/$(BOARDDIR)/lib$(BOARD).a
LIBS += rtc/librtc.a
LIBS += dtt/libdtt.a
LIBS += drivers/libdrivers.a
+LIBS += drivers/nand/libnand.a
+LIBS += drivers/nand_legacy/libnand_legacy.a
LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/cpu/libcpu.a
LIBS += common/libcommon.a
+LIBS += $(BOARDLIBS)
.PHONY : $(LIBS)
# Add GCC lib
u-boot.img: u-boot.bin
./tools/mkimage -A $(ARCH) -T firmware -C none \
-a $(TEXT_BASE) -e 0 \
- -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
--start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
$(SUBDIRS):
$(MAKE) -C $@ all
+version:
+ @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
+ echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
+ echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
+ $(TOPDIR)) >> $(VERSION_FILE); \
+ echo "\"" >> $(VERSION_FILE)
+
gdbtools:
$(MAKE) -C tools/gdb || exit 1
aev_config: unconfig
@./mkconfig -a aev ppc mpc5xxx tqm5200
+BC3450_config: unconfig
+ @./mkconfig -a BC3450 ppc mpc5xxx bc3450
+
cpci5200_config: unconfig
@./mkconfig -a cpci5200 ppc mpc5xxx cpci5200 esd
}
@./mkconfig -a IceCube ppc mpc5xxx icecube
-inka4x0_config: unconfig
+inka4x0_config: unconfig
@./mkconfig inka4x0 ppc mpc5xxx inka4x0
+lite5200b_config \
+lite5200b_LOWBOOT_config: unconfig
+ @ >include/config.h
+ @ echo "#define CONFIG_MPC5200_DDR" >>include/config.h
+ @ echo "... DDR memory revision"
+ @ echo "#define CONFIG_MPC5200" >>include/config.h
+ @ echo "#define CONFIG_LITE5200B" >>include/config.h
+ @[ -z "$(findstring LOWBOOT_,$@)" ] || \
+ { echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+ echo "... with LOWBOOT configuration" ; \
+ }
+ @ echo "... with MPC5200B processor"
+ @./mkconfig -a IceCube ppc mpc5xxx icecube
+
+mcc200_config \
+mcc200_lowboot_config: unconfig
+ @ >include/config.h
+ @[ -z "$(findstring lowboot_,$@)" ] || \
+ { echo "TEXT_BASE = 0xFC000000" >board/mcc200/config.tmp ; \
+ echo "... with lowboot configuration" ; \
+ }
+ @./mkconfig mcc200 ppc mpc5xxx mcc200
+
o2dnt_config:
- @./mkconfig -a o2dnt ppc mpc5xxx o2dnt
+ @./mkconfig o2dnt ppc mpc5xxx o2dnt
pf5200_config: unconfig
- @./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd
+ @./mkconfig pf5200 ppc mpc5xxx pf5200 esd
PM520_config \
PM520_DDR_config \
}
@./mkconfig -a PM520 ppc mpc5xxx pm520
+smmaco4_config: unconfig
+ @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
+
+spieval_config: unconfig
+ @echo "#define CONFIG_CS_AUTOCONF">>include/config.h
+ @echo "... with automatic CS configuration"
+ @./mkconfig -a spieval ppc mpc5xxx tqm5200
+
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
}
@./mkconfig -a Total5200 ppc mpc5xxx total5200
-TQM5200_auto_config \
-TQM5200_AA_config \
-TQM5200_AB_config \
-TQM5200_AC_config \
+TQM5200_config \
+TQM5200_STK100_config \
MiniFAP_config: unconfig
@ >include/config.h
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
- echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
- @[ -z "$(findstring AA,$@)" ] || \
- { echo "#define CONFIG_TQM5200_AA" >>include/config.h ; \
- echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \
- }
- @[ -z "$(findstring AB,$@)" ] || \
- { echo "#define CONFIG_TQM5200_AB" >>include/config.h ; \
- echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \
- echo "... with Graphics Controller"; \
- }
- @[ -z "$(findstring AC,$@)" ] || \
- { echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \
- echo "... with 4 MB Flash, 128 MB SDRAM" ; \
- echo "... with Graphics Controller"; \
- }
- @[ -z "$(findstring auto,$@)" ] || \
- { echo "#define CONFIG_CS_AUTOCONF" >>include/config.h ; \
- echo "... with automatic CS configuration" ; \
+ @[ -z "$(findstring STK100,$@)" ] || \
+ { echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
+ echo "... on a STK52XX.100 base board" ; \
}
+ @echo "#define CONFIG_CS_AUTOCONF">>include/config.h ;
+ @echo "... with automatic CS configuration" ;
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
-spieval_config: unconfig
- echo "#define CONFIG_CS_AUTOCONF">>include/config.h
- echo "... with automatic CS configuration"
- @./mkconfig -a spieval ppc mpc5xxx tqm5200
-
#########################################################################
## MPC8xx Systems
#########################################################################
ELPT860_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
+EP88x_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8xx ep88x
+
ESTEEM192E_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx esteem192e
}
@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
-NC650_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx nc650
+NC650_Rev1_config \
+NC650_Rev2_config \
+CP850_config: unconfig
+ @ >include/config.h
+ @[ -z "$(findstring CP850,$@)" ] || \
+ { echo "#define CONFIG_CP850 1" >>include/config.h ; \
+ echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+ }
+ @[ -z "$(findstring Rev1,$@)" ] || \
+ { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \
+ }
+ @[ -z "$(findstring Rev2,$@)" ] || \
+ { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+ }
+ @./mkconfig -a NC650 ppc mpc8xx nc650
NX823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx nx823
TQM855M_config \
TQM860M_config \
TQM862M_config \
-TQM866M_config: unconfig
+TQM866M_config \
+virtlab2_config: unconfig
@ >include/config.h
@[ -z "$(findstring _LCD,$@)" ] || \
{ echo "#define CONFIG_LCD" >>include/config.h ; \
PCI405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
+pcs440ep_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx pcs440ep
+
PIP405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
yellowstone_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
+ yucca_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx yucca amcc
+
#########################################################################
## MPC8220 Systems
#########################################################################
PM828_PCI_config \
PM828_ROMBOOT_config \
PM828_ROMBOOT_PCI_config: unconfig
- @if [ -z "$(findstring _PCI_,$@)" ] ; then \
+ @if [ "$(findstring _PCI_,$@)" ] ; then \
echo "#define CONFIG_PCI" >>include/config.h ; \
echo "... with PCI enabled" ; \
else \
TQM8260_AF_config \
TQM8260_AG_config \
TQM8260_AH_config \
+TQM8260_AI_config \
TQM8265_AA_config: unconfig
@case "$@" in \
- TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \
- TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \
- TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \
- TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \
- TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
- TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no; BMODE=8260;; \
- TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
- TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=8260;; \
- TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;; \
- TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \
+ TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \
+ TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \
+ TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \
+ TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \
+ TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
+ TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no; BMODE=8260;; \
+ TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
+ TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=8260;; \
+ TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;; \
+ TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
+ TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \
esac; \
>include/config.h ; \
if [ "$${CTYPE}" != "MPC8260" ] ; then \
ZPC1900_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
-#========================================================================
-# M68K
-#========================================================================
#########################################################################
## Coldfire
#########################################################################
cobra5272_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
+EB+MCF-EV123_config : unconfig
+ @ >include/config.h
+ @echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk
+ @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+
+EB+MCF-EV123_internal_config : unconfig
+ @ >include/config.h
+ @echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk
+ @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+
+M5271EVB_config : unconfig
+ @./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
+
M5272C3_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
TASREG_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd
+r5200_config : unconfig
+ @./mkconfig $(@:_config=) m68k mcf52x2 r5200
+
#########################################################################
## MPC83xx Systems
#########################################################################
TQM834x_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx tqm834x
+MPC8349EMDS_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc83xx mpc8349emds
+
#########################################################################
## MPC85xx Systems
#########################################################################
ZUMA_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
+ppmc7xx_config: unconfig
+ @./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
+
#========================================================================
# ARM
#========================================================================
mx1fs2_config : unconfig
@./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx
+netstar_32_config \
+netstar_config: unconfig
+ @if [ "$(findstring _32_,$@)" ] ; then \
+ echo "... 32MB SDRAM" ; \
+ echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>include/config.h ; \
+ else \
+ echo "... 64MB SDRAM" ; \
+ echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>include/config.h ; \
+ fi
+ @./mkconfig -a netstar arm arm925t netstar
+
omap1510inn_config : unconfig
@./mkconfig $(@:_config=) arm arm925t omap1510inn
omap5912osk_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs omap5912osk
+ @./mkconfig $(@:_config=) arm arm926ejs omap5912osk NULL omap
omap1610inn_config \
omap1610inn_cs0boot_config \
echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
- @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+ @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
omap730p2_config \
omap730p2_cs0boot_config \
echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
- @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
+ @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
scb9328_config : unconfig
@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
cm41xx_config : unconfig
@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
+gth2_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_GTH2 1" >>include/config.h
+ @./mkconfig -a gth2 mips mips gth2
+
#########################################################################
## S3C44B0 Systems
#########################################################################
csb226_config : unconfig
@./mkconfig $(@:_config=) arm pxa csb226
+delta_config :
+ @./mkconfig $(@:_config=) arm pxa delta
+
innokom_config : unconfig
@./mkconfig $(@:_config=) arm pxa innokom
ixdp425_config : unconfig
@./mkconfig $(@:_config=) arm ixp ixdp425
+ixdpg425_config : unconfig
+ @./mkconfig $(@:_config=) arm ixp ixdp425
+
lubbock_config : unconfig
@./mkconfig $(@:_config=) arm pxa lubbock
+pleb2_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa pleb2
+
logodl_config : unconfig
@./mkconfig $(@:_config=) arm pxa logodl
+pdnb3_config : unconfig
+ @./mkconfig $(@:_config=) arm ixp pdnb3 prodrive
+
pxa255_idp_config: unconfig
@./mkconfig $(@:_config=) arm pxa pxa255_idp
xsengine_config : unconfig
@./mkconfig $(@:_config=) arm pxa xsengine
+zylonite_config :
+ @./mkconfig $(@:_config=) arm pxa zylonite
+
#########################################################################
## ARM1136 Systems
#########################################################################
## Nios-II
#########################################################################
+EP1C20_config : unconfig
+ @./mkconfig EP1C20 nios2 nios2 ep1c20 altera
+
+EP1S10_config : unconfig
+ @./mkconfig EP1S10 nios2 nios2 ep1s10 altera
+
+EP1S40_config : unconfig
+ @./mkconfig EP1S40 nios2 nios2 ep1s40 altera
+
PK1C20_config : unconfig
@./mkconfig PK1C20 nios2 nios2 pk1c20 psyent
@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
#########################################################################
+## Blackfin
+#########################################################################
+ezkit533_config : unconfig
+ @./mkconfig $(@:_config=) blackfin bf533 ezkit533
+
+stamp_config : unconfig
+ @./mkconfig $(@:_config=) blackfin bf533 stamp
+
+dspstamp_config : unconfig
+ @./mkconfig $(@:_config=) blackfin bf533 dsp_stamp
+
+#########################################################################
+#########################################################################
#########################################################################
clean:
rm -f examples/hello_world examples/timer \
examples/eepro100_eeprom examples/sched \
examples/mem_to_mem_idma2intr examples/82559_eeprom \
+ examples/smc91111_eeprom \
examples/test_burst
rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
rm -f tools/mpc86x_clk tools/ncb
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
rm -f tools/env/fw_printenv tools/env/fw_setenv
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
+ rm -f board/netstar/eeprom board/netstar/crcek
+ rm -f board/netstar/*.srec board/netstar/*.bin
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
- rm -f $(OBJS) *.bak tags TAGS
+ rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
rm -fr *.*~
rm -f u-boot u-boot.map u-boot.hex $(ALL)
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
--- /dev/null
-#define GPIO_MAX 32
-#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
-#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
-#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
-#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
-#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
- /* For the other GPIO number, you must shift */
-/*----------------------------------------------------------------------------+
-| Declare GPIO Configuration values
-+----------------------------------------------------------------------------*/
-typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
-typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
-
-typedef struct {
- unsigned long add; /* gpio core base address */
- gpio_driver_t in_out; /* Driver Setting */
- gpio_select_t alt_nb; /* Selected Alternate */
-} gpio_param_s;
-
+ /*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ #ifndef __YUCCA_H_
+ #define __YUCCA_H_
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ /*----------------------------------------------------------------------------+
+ | Defines
+ +----------------------------------------------------------------------------*/
+
+ #define TMR_FREQ_EXT 25000000
+ #define BOARD_UART_CLOCK 11059200
+
+ #define BOARD_OPTION_SELECTED 1
+ #define BOARD_OPTION_NOT_SELECTED 0
+
+ #define ENGINEERING_CLOCK_CHECKING "clk_chk"
+ #define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
+
+ #define ENGINEERING_CLOCK_CHECKING_DATA 1
+ #define ENGINEERING_EXTERNAL_CLOCK_DATA 2
+
+ /* ethernet definition */
+ #define MAX_ENETMODE_PARM 3
+ #define ENETMODE_NEG 0
+ #define ENETMODE_SPEED 1
+ #define ENETMODE_DUPLEX 2
+
+ #define ENETMODE_AUTONEG 0
+ #define ENETMODE_NO_AUTONEG 1
+ #define ENETMODE_10 2
+ #define ENETMODE_100 3
+ #define ENETMODE_1000 4
+ #define ENETMODE_HALF 5
+ #define ENETMODE_FULL 6
+
+ #define NUM_TLB_ENTRIES 64
+
+ /*----------------------------------------------------------------------------+
+ | TLB specific defines.
+ +----------------------------------------------------------------------------*/
+ #define TLB_256MB_ALIGN_MASK 0xF0000000
+ #define TLB_16MB_ALIGN_MASK 0xFF000000
+ #define TLB_1MB_ALIGN_MASK 0xFFF00000
+ #define TLB_256KB_ALIGN_MASK 0xFFFC0000
+ #define TLB_64KB_ALIGN_MASK 0xFFFF0000
+ #define TLB_16KB_ALIGN_MASK 0xFFFFC000
+ #define TLB_4KB_ALIGN_MASK 0xFFFFF000
+ #define TLB_1KB_ALIGN_MASK 0xFFFFFC00
+ #define TLB_256MB_SIZE 0x10000000
+ #define TLB_16MB_SIZE 0x01000000
+ #define TLB_1MB_SIZE 0x00100000
+ #define TLB_256KB_SIZE 0x00040000
+ #define TLB_64KB_SIZE 0x00010000
+ #define TLB_16KB_SIZE 0x00004000
+ #define TLB_4KB_SIZE 0x00001000
+ #define TLB_1KB_SIZE 0x00000400
+
+ #define TLB_WORD0_EPN_MASK 0xFFFFFC00
+ #define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+ #define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+ #define TLB_WORD0_V_MASK 0x00000200
+ #define TLB_WORD0_V_ENABLE 0x00000200
+ #define TLB_WORD0_V_DISABLE 0x00000000
+ #define TLB_WORD0_TS_MASK 0x00000100
+ #define TLB_WORD0_TS_1 0x00000100
+ #define TLB_WORD0_TS_0 0x00000000
+ #define TLB_WORD0_SIZE_MASK 0x000000F0
+ #define TLB_WORD0_SIZE_1KB 0x00000000
+ #define TLB_WORD0_SIZE_4KB 0x00000010
+ #define TLB_WORD0_SIZE_16KB 0x00000020
+ #define TLB_WORD0_SIZE_64KB 0x00000030
+ #define TLB_WORD0_SIZE_256KB 0x00000040
+ #define TLB_WORD0_SIZE_1MB 0x00000050
+ #define TLB_WORD0_SIZE_16MB 0x00000070
+ #define TLB_WORD0_SIZE_256MB 0x00000090
+ #define TLB_WORD0_TPAR_MASK 0x0000000F
+ #define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+ #define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+ #define TLB_WORD1_RPN_MASK 0xFFFFFC00
+ #define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+ #define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+ #define TLB_WORD1_PAR1_MASK 0x00000300
+ #define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+ #define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+ #define TLB_WORD1_PAR1_0 0x00000000
+ #define TLB_WORD1_PAR1_1 0x00000100
+ #define TLB_WORD1_PAR1_2 0x00000200
+ #define TLB_WORD1_PAR1_3 0x00000300
+ #define TLB_WORD1_ERPN_MASK 0x0000000F
+ #define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+ #define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+ #define TLB_WORD2_PAR2_MASK 0xC0000000
+ #define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+ #define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+ #define TLB_WORD2_PAR2_0 0x00000000
+ #define TLB_WORD2_PAR2_1 0x40000000
+ #define TLB_WORD2_PAR2_2 0x80000000
+ #define TLB_WORD2_PAR2_3 0xC0000000
+ #define TLB_WORD2_U0_MASK 0x00008000
+ #define TLB_WORD2_U0_ENABLE 0x00008000
+ #define TLB_WORD2_U0_DISABLE 0x00000000
+ #define TLB_WORD2_U1_MASK 0x00004000
+ #define TLB_WORD2_U1_ENABLE 0x00004000
+ #define TLB_WORD2_U1_DISABLE 0x00000000
+ #define TLB_WORD2_U2_MASK 0x00002000
+ #define TLB_WORD2_U2_ENABLE 0x00002000
+ #define TLB_WORD2_U2_DISABLE 0x00000000
+ #define TLB_WORD2_U3_MASK 0x00001000
+ #define TLB_WORD2_U3_ENABLE 0x00001000
+ #define TLB_WORD2_U3_DISABLE 0x00000000
+ #define TLB_WORD2_W_MASK 0x00000800
+ #define TLB_WORD2_W_ENABLE 0x00000800
+ #define TLB_WORD2_W_DISABLE 0x00000000
+ #define TLB_WORD2_I_MASK 0x00000400
+ #define TLB_WORD2_I_ENABLE 0x00000400
+ #define TLB_WORD2_I_DISABLE 0x00000000
+ #define TLB_WORD2_M_MASK 0x00000200
+ #define TLB_WORD2_M_ENABLE 0x00000200
+ #define TLB_WORD2_M_DISABLE 0x00000000
+ #define TLB_WORD2_G_MASK 0x00000100
+ #define TLB_WORD2_G_ENABLE 0x00000100
+ #define TLB_WORD2_G_DISABLE 0x00000000
+ #define TLB_WORD2_E_MASK 0x00000080
+ #define TLB_WORD2_E_ENABLE 0x00000080
+ #define TLB_WORD2_E_DISABLE 0x00000000
+ #define TLB_WORD2_UX_MASK 0x00000020
+ #define TLB_WORD2_UX_ENABLE 0x00000020
+ #define TLB_WORD2_UX_DISABLE 0x00000000
+ #define TLB_WORD2_UW_MASK 0x00000010
+ #define TLB_WORD2_UW_ENABLE 0x00000010
+ #define TLB_WORD2_UW_DISABLE 0x00000000
+ #define TLB_WORD2_UR_MASK 0x00000008
+ #define TLB_WORD2_UR_ENABLE 0x00000008
+ #define TLB_WORD2_UR_DISABLE 0x00000000
+ #define TLB_WORD2_SX_MASK 0x00000004
+ #define TLB_WORD2_SX_ENABLE 0x00000004
+ #define TLB_WORD2_SX_DISABLE 0x00000000
+ #define TLB_WORD2_SW_MASK 0x00000002
+ #define TLB_WORD2_SW_ENABLE 0x00000002
+ #define TLB_WORD2_SW_DISABLE 0x00000000
+ #define TLB_WORD2_SR_MASK 0x00000001
+ #define TLB_WORD2_SR_ENABLE 0x00000001
+ #define TLB_WORD2_SR_DISABLE 0x00000000
+
+ /*----------------------------------------------------------------------------+
+ | Board specific defines.
+ +----------------------------------------------------------------------------*/
+ #define NONCACHE_MEMORY_SIZE (64*1024)
+ #define NONCACHE_AREA0_ENDOFFSET (64*1024)
+ #define NONCACHE_AREA1_ENDOFFSET (32*1024)
+
+ #define FLASH_SECTORSIZE 0x00010000
+
+ /* SDRAM MICRON */
+ #define SDRAM_MICRON 0x2C
+
+ #define SDRAM_TRUE 1
+ #define SDRAM_FALSE 0
+ #define SDRAM_DDR1 1
+ #define SDRAM_DDR2 2
+ #define SDRAM_NONE 0
+ #define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
+ #define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
+ #define MAXBANKSPERDIMM 2
+ #define MAXRANKSPERDIMM 2
+ #define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
+ #define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
+ #define ERROR_STR_LENGTH 256
+ #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
+
+ /*----------------------------------------------------------------------------+
+ | SDR Configuration registers
+ +----------------------------------------------------------------------------*/
+ /* Serial Device Strap Reg 0 */
+ #define sdr_pstrp0 0x0040
+
+ #define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
+ #define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
+ #define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
+
+ #define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
+ #define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
+ #define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
+
+ #define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
+ #define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
+ #define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
+ #define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
+ #define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
+
+ /* Serial Device Enabled - Addr = 0xA8 */
+ #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+ /* Serial Device Enabled - Addr = 0xA4 */
+ #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+ /* Pin Straps Reg */
+ #define SDR0_PSTRP0 0x0040
+ #define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+ /* fpgareg - defines are in include/config/YUCCA.h */
+
+ #define SDR0_CUST0_ENET3_MASK 0x00000080
+ #define SDR0_CUST0_ENET3_COPPER 0x00000000
+ #define SDR0_CUST0_ENET3_FIBER 0x00000080
+ #define SDR0_CUST0_RGMII3_MASK 0x00000070
+ #define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+ #define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+ #define SDR0_CUST0_RGMII3_DISAB 0x00000000
+ #define SDR0_CUST0_RGMII3_RTBI 0x00000040
+ #define SDR0_CUST0_RGMII3_RGMII 0x00000050
+ #define SDR0_CUST0_RGMII3_TBI 0x00000060
+ #define SDR0_CUST0_RGMII3_GMII 0x00000070
+ #define SDR0_CUST0_ENET2_MASK 0x00000008
+ #define SDR0_CUST0_ENET2_COPPER 0x00000000
+ #define SDR0_CUST0_ENET2_FIBER 0x00000008
+ #define SDR0_CUST0_RGMII2_MASK 0x00000007
+ #define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+ #define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+ #define SDR0_CUST0_RGMII2_DISAB 0x00000000
+ #define SDR0_CUST0_RGMII2_RTBI 0x00000004
+ #define SDR0_CUST0_RGMII2_RGMII 0x00000005
+ #define SDR0_CUST0_RGMII2_TBI 0x00000006
+ #define SDR0_CUST0_RGMII2_GMII 0x00000007
+
+ #define ONE_MILLION 1000000
+ #define ONE_BILLION 1000000000
+
+ /*----------------------------------------------------------------------------+
+ | X
+ | XX
+ | XX XXX XXXXX XX XXX XXXXX
+ | XX XX X XXX XX XX
+ | XX XX XXXXXX XX XX
+ | XX XX X XX XX XX XX
+ | XXX XX XXXXX X XXXX XXX
+ +----------------------------------------------------------------------------*/
+ /*----------------------------------------------------------------------------+
+ | Declare Configuration values
+ +----------------------------------------------------------------------------*/
+
+ typedef enum config_selection {
+ CONFIG_NOT_SELECTED,
+ CONFIG_SELECTED
+ } config_selection_t;
+
+ typedef enum config_list {
+ UART2_IN_SERVICE_MODE,
+ CPU_TRACE_MODE,
+ UART1_CTS_RTS,
+ CONFIG_NB
+ } config_list_t;
+
+ #define MAX_CONFIG_SELECT_NB 3
+
+ #define BOARD_INFO_UART2_IN_SERVICE_MODE 1
+ #define BOARD_INFO_CPU_TRACE_MODE 2
+ #define BOARD_INFO_UART1_CTS_RTS_MODE 4
+
+ void force_bup_config_selection(config_selection_t *confgi_select_P);
+ void update_config_selection_table(config_selection_t *config_select_P);
+ void display_config_selection(config_selection_t *config_select_P);
+
+ /*----------------------------------------------------------------------------+
+ | XX
+ |
+ | XXXX XX XXX XXX XXXX
+ | XX XX XX XX XX XX
+ | XX XXX XX XX XX XX XX
+ | XX XX XXXXX XX XX XX
+ | XXXX XX XXXX XXXX
+ | XXXX
+ |
+ |
+ |
+ | +------------------------------------------------------------------+
+ | | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
+ | +----------------------+------------------+-----+------------+-----+
+ | | | | | | |
+ | | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | |
+ | | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | |
+ | | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | |
+ | | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | |
+ | | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | |
+ | | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | |
+ | | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA |
+ | | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA |
+ | | GPIO0_8 | PERREADY | I | TRCES4 | NA |
+ | | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA |
+ | | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA |
+ | | GPIO0_11 | IRQ0 | I | TRCTS2 | NA |
+ | | GPIO0_12 | IRQ1 | I | TRCTS3 | NA |
+ | | GPIO0_13 | IRQ2 | I | TRCTS4 | NA |
+ | | GPIO0_14 | IRQ3 | I | TRCTS5 | NA |
+ | | GPIO0_15 | IRQ4 | I | TRCTS6 | NA |
+ | | GPIO0_16 | IRQ5 | I | UART2RX | I |
+ | | GPIO0_17 | PERBE0_N | O | UART2TX | O |
+ | | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA |
+ | | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA |
+ | | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA |
+ | | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA |
+ | | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA |
+ | | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA |
+ | | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA |
+ | | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA |
+ | | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA |
+ | | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA |
+ | | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA |
+ | | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA |
+ | | GPIO0_30 | UART1RX | I | NA | NA |
+ | | GPIO0_31 | UART1TX | O | NA | NA |
+ | | | | | | |
+ | +----------------------+------------------+-----+------------+-----+
+ |
+ +----------------------------------------------------------------------------*/
+
+ unsigned long auto_calc_speed(void);
+ /*----------------------------------------------------------------------------+
+ | Prototypes
+ +----------------------------------------------------------------------------*/
+ void print_evb440spe_info(void);
+
+ int onboard_pci_arbiter_selected(int core_pci);
+
+ #ifdef __cplusplus
+ }
+ #endif
+ #endif /* __YUCCA_H_ */
#include <command.h>
#include <net.h> /* for print_IPaddr */
+DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_COMMANDS & CFG_CMD_BDI)
static void print_num(const char *, ulong);
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
int i;
bd_t *bd = gd->bd;
char buf[32];
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440SP)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
int i;
bd_t *bd = gd->bd;
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
int i;
bd_t *bd = gd->bd;
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
int i;
bd_t *bd = gd->bd;
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
int i;
bd_t *bd = gd->bd;
#include <serial.h>
#include <devices.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_SERIAL_MULTI)
static struct serial_device *serial_devices = NULL;
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
- || defined(CONFIG_405EP)
+ || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
- return &serial0_device;
+ #if defined(CONFIG_UART1_CONSOLE)
+ return &serial1_device;
+ #else
+ return &serial0_device;
+ #endif
#else
#error No default console
#endif
static int serial_register (struct serial_device *dev)
{
- DECLARE_GLOBAL_DATA_PTR;
-
dev->init += gd->reloc_off;
dev->setbrg += gd->reloc_off;
dev->getc += gd->reloc_off;
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
- || defined(CONFIG_405EP)
+ || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif
int serial_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
struct serial_device *dev = default_serial_console ();
void serial_setbrg (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
struct serial_device *dev = default_serial_console ();
int serial_getc (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
struct serial_device *dev = default_serial_console ();
int serial_tstc (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
struct serial_device *dev = default_serial_console ();
void serial_putc (const char c)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
struct serial_device *dev = default_serial_console ();
void serial_puts (const char *s)
{
- DECLARE_GLOBAL_DATA_PTR;
-
if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
struct serial_device *dev = default_serial_console ();
#include <asm/processor.h>
#include <pci.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#ifdef CONFIG_PCI
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
/*#define DEBUG*/
/*-----------------------------------------------------------------------------+
*-----------------------------------------------------------------------------*/
void pci_405gp_init(struct pci_controller *hose)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int i, reg_num = 0;
bd_t *bd = gd->bd;
unsigned short temp_short;
unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
- unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
- unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
char *ptmla_str, *ptmms_str;
-#else
+#endif
unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
-#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
{
unsigned int cmdstat = 0;
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
/* always enable io space on vga boards */
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
- #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long strap;
mfsdr(sdr_sdstp1,strap);
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
#elif defined(PCIX0_BRDGOPT1)
out32r( PCIX0_POM0SA, 0 ); /* disable */
out32r( PCIX0_POM1SA, 0 ); /* disable */
out32r( PCIX0_POM2SA, 0 ); /* disable */
+ #if defined(CONFIG_440SPE)
+ out32r( PCIX0_POM0LAL, 0x10000000 );
+ out32r( PCIX0_POM0LAH, 0x0000000c );
+ #else
out32r( PCIX0_POM0LAL, 0x00000000 );
out32r( PCIX0_POM0LAH, 0x00000003 );
+ #endif
out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
out32r( PCIX0_POM0PCIAH, 0x00000000 );
out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
/*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#include <asm/cache.h>
#include <ppc4xx.h>
+#if !defined(CONFIG_405)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
#if defined(CONFIG_440)
#define FREQ_EBC (sys_info.freqEPB)
return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE)
unsigned long val;
mfsdr(sdr_sdstp1, val);
}
#endif
- #if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440GX) || defined(CONFIG_440SP)
+ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define I2C_BOOTROM
return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#endif
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE)
unsigned long val;
mfsdr(sdr_sdcs, val);
int checkcpu (void)
{
#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
- DECLARE_GLOBAL_DATA_PTR;
uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
puts("EP Rev. B");
break;
+
+ case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
+ puts("EP Rev. C");
+ break;
#endif /* CONFIG_440EP */
#ifdef CONFIG_440GR
case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
puts("GR Rev. A");
break;
+
+ case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
+ puts("GR Rev. B");
+ break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */
puts("SP Rev. B");
break;
+ case PVR_440SPe_RA:
+ puts("SPe 3GA533C");
+ break;
+ case PVR_440SPe_RB:
+ puts("SPe 3GB533C");
+ break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
#include <commproc.h>
#include "vecnum.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/****************************************************************************/
/*
};
static struct irq_action irq_vecs[32];
+ void uic0_interrupt( void * parms); /* UIC0 handler */
#if defined(CONFIG_440)
static struct irq_action irq_vecs1[32]; /* For UIC1 */
void uic1_interrupt( void * parms); /* UIC1 handler */
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
-
- void uic0_interrupt( void * parms); /* UIC0 handler */
void uic2_interrupt( void * parms); /* UIC2 handler */
- #endif /* CONFIG_440GX */
+ #endif /* CONFIG_440GX CONFIG_440SPE */
+
+ #if defined(CONFIG_440SPE)
+ static struct irq_action irq_vecs3[32]; /* For UIC3 */
+ void uic3_interrupt( void * parms); /* UIC3 handler */
+ #endif /* CONFIG_440SPE */
#endif /* CONFIG_440 */
int interrupt_init_cpu (unsigned *decrementer_count)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int vec;
unsigned long val;
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
#endif /* CONFIG_440GX */
+ #if defined(CONFIG_440SPE)
+ irq_vecs3[vec].handler = NULL;
+ irq_vecs3[vec].arg = NULL;
+ irq_vecs3[vec].count = 0;
+ #endif /* CONFIG_440SPE */
#endif
}
} /* external_interrupt CONFIG_440GX */
+ #elif defined(CONFIG_440SPE)
+ void external_interrupt(struct pt_regs *regs)
+ {
+ ulong uic_msr;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ /* 440 SPe uses base uic register */
+ uic_msr = mfdcr(uic0msr);
+
+ if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+ uic1_interrupt(0);
+
+ if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+ uic2_interrupt(0);
+
+ if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) )
+ uic3_interrupt(0);
+
+ if (uic_msr & ~(UICB0_ALL))
+ uic0_interrupt(0);
+
+ mtdcr(uic0sr, uic_msr);
+
+ return;
+ } /* external_interrupt CONFIG_440SPE */
+
#else
void external_interrupt(struct pt_regs *regs)
}
#endif
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
}
#endif /* defined(CONFIG_440) */
- #if defined(CONFIG_440GX)
- /* Handler for UIC1 interrupt */
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+ /* Handler for UIC2 interrupt */
void uic2_interrupt( void * parms)
{
ulong uic2_msr;
(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
} else {
mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
- printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
+ printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec);
}
/*
}
#endif /* defined(CONFIG_440GX) */
+ #if defined(CONFIG_440SPE)
+ /* Handler for UIC3 interrupt */
+ void uic3_interrupt( void * parms)
+ {
+ ulong uic3_msr;
+ ulong msr_shift;
+ int vec;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ uic3_msr = mfdcr(uic3msr);
+ msr_shift = uic3_msr;
+ vec = 0;
+
+ while (msr_shift != 0) {
+ if (msr_shift & 0x80000000) {
+ /*
+ * Increment irq counter (for debug purpose only)
+ */
+ irq_vecs3[vec].count++;
+
+ if (irq_vecs3[vec].handler != NULL) {
+ /* call isr */
+ (*irq_vecs3[vec].handler)(irq_vecs3[vec].arg);
+ } else {
+ mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec));
+ printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec);
+ }
+
+ /*
+ * After servicing the interrupt, we have to remove the status indicator.
+ */
+ mtdcr(uic3sr, (0x80000000 >> vec));
+ }
+
+ /*
+ * Shift msr to next position and increment vector
+ */
+ msr_shift <<= 1;
+ vec++;
+ }
+ }
+ #endif /* defined(CONFIG_440SPE) */
+
/****************************************************************************/
/*
int i = vec;
#if defined(CONFIG_440)
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
irqa[i].arg = arg;
#if defined(CONFIG_440)
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
int i = vec;
#if defined(CONFIG_440)
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
#endif
#if defined(CONFIG_440)
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
printf("\n");
#endif
- #if defined(CONFIG_440GX)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");
printf("\n");
#endif
+ #if defined(CONFIG_440SPE)
+ printf ("\nUIC 3\n");
+ printf ("Nr Routine Arg Count\n");
+
+ for (vec=0; vec<32; vec++) {
+ if (irq_vecs3[vec].handler != NULL)
+ printf ("%02d %08lx %08lx %d\n",
+ vec+63, (ulong)irq_vecs3[vec].handler,
+ (ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count);
+ }
+ printf("\n");
+ #endif
+
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#include <malloc.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/*****************************************************************************/
#ifdef CONFIG_IOP480
int serial_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
volatile char val;
unsigned short br_reg;
void serial_setbrg (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned short br_reg;
br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
- #if defined(CONFIG_440SP)
+ #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
#endif
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440GX */
int serial_init(void)
#endif
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned long reg;
unsigned long udiv;
unsigned short bdiv;
unsigned long tmp;
#endif
- #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
int serial_init (void)
#endif
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned long reg;
unsigned long tmp;
unsigned long clk;
void serial_setbrg (void)
#endif
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned long tmp;
unsigned long clk;
unsigned long udiv;
#else
udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
#endif /* CONFIG_405EP */
+
+ #if !defined(CFG_EXT_SERIAL_CLOCK) && \
+ ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440SPE) )
+ serial_divs (gd->baudrate, &udiv, &bdiv);
+ tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */
+ #if defined(CONFIG_SERIAL_MULTI)
+ if (UART0_BASE == dev_base) {
+ mtsdr (UART0_SDR, tmp);
+ } else {
+ mtsdr (UART1_SDR, tmp);
+ }
+ #else
+ mtsdr (UART0_SDR, tmp);
+ #endif
+
+ #else
+
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
+ #endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
#if defined(CONFIG_SERIAL_MULTI)
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
#if (CONFIG_KGDB_SER_INDEX & 2)
void kgdb_serial_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
volatile char val;
unsigned short br_reg;
#include <ppc4xx.h>
#include <asm/processor.h>
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
#define ONE_BILLION 1000000000
-
+ #ifdef DEBUG
+ #define DEBUGF(fmt,args...) printf(fmt ,##args)
+ #else
+ #define DEBUGF(fmt,args...)
+ #endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
return sys_info.freqPCI;
}
- #elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
+ #elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
unsigned long m;
unsigned long prbdv0;
+ #if defined(CONFIG_440SPE)
+ unsigned long sys_freq;
+ unsigned long sys_per=0;
+ unsigned long msr;
+ unsigned long pci_clock_per;
+ unsigned long sdr_ddrpll;
+
+ /*-------------------------------------------------------------------------+
+ | Get the system clock period.
+ +-------------------------------------------------------------------------*/
+ sys_per = determine_sysper();
+
+ msr = (mfmsr () & ~(MSR_EE)); /* disable interrupts */
+
+ /*-------------------------------------------------------------------------+
+ | Calculate the system clock speed from the period.
+ +-------------------------------------------------------------------------*/
+ sys_freq=(ONE_BILLION/sys_per)*1000;
+ #endif
+
/* Extract configured divisors */
mfsdr( sdr_sdstp0,strp0 );
mfsdr( sdr_sdstp1,strp1 );
m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
/* Now calculate the individual clocks */
+ #if defined(CONFIG_440SPE)
+ sysInfo->freqVCOMhz = (m * sys_freq) ;
+ #else
sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+ #endif
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+ #if defined(CONFIG_440SPE)
+ /* Determine PCI Clock Period */
+ pci_clock_per = determine_pci_clock_per();
+ sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
+ mfsdr(sdr_ddr0, sdr_ddrpll);
+ sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
+ #endif
+
+
+ }
+
+ #endif
+
+ #if defined(CONFIG_440SPE)
+ unsigned long determine_sysper(void)
+ {
+ unsigned int fpga_clocking_reg;
+ unsigned int master_clock_selection;
+ unsigned long master_clock_per = 0;
+ unsigned long fb_div_selection;
+ unsigned int vco_div_reg_value;
+ unsigned long vco_div_selection;
+ unsigned long sys_per = 0;
+ int extClkVal;
+
+ /*-------------------------------------------------------------------------+
+ | Read FPGA reg 0 and reg 1 to get FPGA reg information
+ +-------------------------------------------------------------------------*/
+ fpga_clocking_reg = in16(FPGA_REG16);
+
+
+ /* Determine Master Clock Source Selection */
+ master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;
+
+ switch(master_clock_selection) {
+ case FPGA_REG16_MASTER_CLK_66_66:
+ master_clock_per = PERIOD_66_66MHZ;
+ break;
+ case FPGA_REG16_MASTER_CLK_50:
+ master_clock_per = PERIOD_50_00MHZ;
+ break;
+ case FPGA_REG16_MASTER_CLK_33_33:
+ master_clock_per = PERIOD_33_33MHZ;
+ break;
+ case FPGA_REG16_MASTER_CLK_25:
+ master_clock_per = PERIOD_25_00MHZ;
+ break;
+ case FPGA_REG16_MASTER_CLK_EXT:
+ if ((extClkVal==EXTCLK_33_33)
+ && (extClkVal==EXTCLK_50)
+ && (extClkVal==EXTCLK_66_66)
+ && (extClkVal==EXTCLK_83)) {
+ /* calculate master clock period from external clock value */
+ master_clock_per=(ONE_BILLION/extClkVal) * 1000;
+ } else {
+ /* Unsupported */
+ DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
+ hang();
+ }
+ break;
+ default:
+ /* Unsupported */
+ DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
+ hang();
+ break;
+ }
+
+ /* Determine FB divisors values */
+ if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
+ if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
+ fb_div_selection = FPGA_FB_DIV_6;
+ else
+ fb_div_selection = FPGA_FB_DIV_12;
+ } else {
+ if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
+ fb_div_selection = FPGA_FB_DIV_10;
+ else
+ fb_div_selection = FPGA_FB_DIV_20;
+ }
+
+ /* Determine VCO divisors values */
+ vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;
+
+ switch(vco_div_reg_value) {
+ case FPGA_REG16_VCO_DIV_4:
+ vco_div_selection = FPGA_VCO_DIV_4;
+ break;
+ case FPGA_REG16_VCO_DIV_6:
+ vco_div_selection = FPGA_VCO_DIV_6;
+ break;
+ case FPGA_REG16_VCO_DIV_8:
+ vco_div_selection = FPGA_VCO_DIV_8;
+ break;
+ case FPGA_REG16_VCO_DIV_10:
+ default:
+ vco_div_selection = FPGA_VCO_DIV_10;
+ break;
+ }
+
+ if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
+ switch(master_clock_per) {
+ case PERIOD_25_00MHZ:
+ if (fb_div_selection == FPGA_FB_DIV_12) {
+ if (vco_div_selection == FPGA_VCO_DIV_4)
+ sys_per = PERIOD_75_00MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_50_00MHZ;
+ }
+ break;
+ case PERIOD_33_33MHZ:
+ if (fb_div_selection == FPGA_FB_DIV_6) {
+ if (vco_div_selection == FPGA_VCO_DIV_4)
+ sys_per = PERIOD_50_00MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_33_33MHZ;
+ }
+ if (fb_div_selection == FPGA_FB_DIV_10) {
+ if (vco_div_selection == FPGA_VCO_DIV_4)
+ sys_per = PERIOD_83_33MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_10)
+ sys_per = PERIOD_33_33MHZ;
+ }
+ if (fb_div_selection == FPGA_FB_DIV_12) {
+ if (vco_div_selection == FPGA_VCO_DIV_4)
+ sys_per = PERIOD_100_00MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_66_66MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_8)
+ sys_per = PERIOD_50_00MHZ;
+ }
+ break;
+ case PERIOD_50_00MHZ:
+ if (fb_div_selection == FPGA_FB_DIV_6) {
+ if (vco_div_selection == FPGA_VCO_DIV_4)
+ sys_per = PERIOD_75_00MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_50_00MHZ;
+ }
+ if (fb_div_selection == FPGA_FB_DIV_10) {
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_83_33MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_10)
+ sys_per = PERIOD_50_00MHZ;
+ }
+ if (fb_div_selection == FPGA_FB_DIV_12) {
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_100_00MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_8)
+ sys_per = PERIOD_75_00MHZ;
+ }
+ break;
+ case PERIOD_66_66MHZ:
+ if (fb_div_selection == FPGA_FB_DIV_6) {
+ if (vco_div_selection == FPGA_VCO_DIV_4)
+ sys_per = PERIOD_100_00MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_6)
+ sys_per = PERIOD_66_66MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_8)
+ sys_per = PERIOD_50_00MHZ;
+ }
+ if (fb_div_selection == FPGA_FB_DIV_10) {
+ if (vco_div_selection == FPGA_VCO_DIV_8)
+ sys_per = PERIOD_83_33MHZ;
+ if (vco_div_selection == FPGA_VCO_DIV_10)
+ sys_per = PERIOD_66_66MHZ;
+ }
+ if (fb_div_selection == FPGA_FB_DIV_12) {
+ if (vco_div_selection == FPGA_VCO_DIV_8)
+ sys_per = PERIOD_100_00MHZ;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (sys_per == 0) {
+ /* Other combinations are not supported */
+ DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
+ hang();
+ }
+ } else {
+ /* calcul system clock without cheking */
+ /* if engineering option clock no check is selected */
+ /* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
+ sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
+ }
+
+ return(sys_per);
+
+ }
+
+ /*-------------------------------------------------------------------------+
+ | determine_pci_clock_per.
+ +-------------------------------------------------------------------------*/
+ unsigned long determine_pci_clock_per(void)
+ {
+ unsigned long pci_clock_selection, pci_period;
+
+ /*-------------------------------------------------------------------------+
+ | Read FPGA reg 6 to get PCI 0 FPGA reg information
+ +-------------------------------------------------------------------------*/
+ pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */
+
+
+ pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;
+
+ switch (pci_clock_selection) {
+ case FPGA_REG16_PCI0_CLK_133_33:
+ pci_period = PERIOD_133_33MHZ;
+ break;
+ case FPGA_REG16_PCI0_CLK_100:
+ pci_period = PERIOD_100_00MHZ;
+ break;
+ case FPGA_REG16_PCI0_CLK_66_66:
+ pci_period = PERIOD_66_66MHZ;
+ break;
+ default:
+ pci_period = PERIOD_33_33MHZ;;
+ break;
+ }
+
+ return(pci_period);
}
#endif
int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
- DECLARE_GLOBAL_DATA_PTR;
-
sys_info_t sys_info;
get_sys_info (&sys_info);
#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
#ifdef CONFIG_IOP480
- DECLARE_GLOBAL_DATA_PTR;
-
gd->cpu_clk = 66000000;
gd->bus_clk = 66000000;
#endif
/**************************************************************************/
_start_440:
+ /*----------------------------------------------------------------+
+ | Core bug fix. Clear the esr
+ +-----------------------------------------------------------------*/
+ addi r0,r0,0x0000
+ mtspr esr,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
- #if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
ori r1,r1,0x6000 /* cache touch */
mtspr ccr0,r1
+ #if defined (CONFIG_440SPE)
+ /*----------------------------------------------------------------+
+ | Initialize Core Configuration Reg1.
+ | a. ICDPEI: Record even parity. Normal operation.
+ | b. ICTPEI: Record even parity. Normal operation.
+ | c. DCTPEI: Record even parity. Normal operation.
+ | d. DCDPEI: Record even parity. Normal operation.
+ | e. DCUPEI: Record even parity. Normal operation.
+ | f. DCMPEI: Record even parity. Normal operation.
+ | g. FCOM: Normal operation
+ | h. MMUPEI: Record even parity. Normal operation.
+ | i. FFF: Flush only as much data as necessary.
+ | j. TCS: Timebase increments from externally supplied clock
+ +-----------------------------------------------------------------*/
+ addis r0, r0, 0x0000
+ ori r0, r0, 0x0080
+ mtspr ccr1, r0
+
+ /*----------------------------------------------------------------+
+ | Reset the timebase.
+ | The previous write to CCR1 sets the timebase source.
+ +-----------------------------------------------------------------*/
+ addi r0, r0, 0x0000
+ mtspr tbl, r0
+ mtspr tbu, r0
+ #endif
+
/*----------------------------------------------------------------*/
/* Setup interrupt vectors */
/*----------------------------------------------------------------*/
mtspr ivlim,r1
mtspr dvlim,r1
+ /*----------------------------------------------------------------+
+ |Initialize MMUCR[STID] = 0.
+ +-----------------------------------------------------------------*/
+ mfspr r0,mmucr
+ addis r1,0,0xFFFF
+ ori r1,r1,0xFF00
+ and r0,r0,r1
+ mtspr mmucr,r0
+
/*----------------------------------------------------------------*/
/* Clear all TLB entries -- TID = 0, TS = 0 */
/*----------------------------------------------------------------*/
- mtspr mmucr,r0
+ addis r0,0,0x0000
li r1,0x003f /* 64 TLB entries */
mtctr r1
- 0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
+ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
+ tlbwe r0,r1,0x0001
+ tlbwe r0,r1,0x0002
subi r1,r1,0x0001
- bdnz 0b
+ bdnz rsttlb
/*----------------------------------------------------------------*/
/* TLB entry setup -- step thru tlbtab */
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
-#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
- lis r1,0x0002 /* set CE bit (Critical Exceptions) */
- ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
- mtmsr r1 /* change MSR */
-#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
- bl __440gx_msr_set
- b __440gx_msr_continue
-
-__440gx_msr_set:
- lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
- ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
- mtspr srr1,r1
- mflr r1
- mtspr srr0,r1
- rfi
-__440gx_msr_continue:
-#endif
/*----------------------------------------------------------------*/
/* Debug setup -- some (not very good) ice's need an event*/
addi r3,r3,32
bdnz ..d_ag
#else
- #if defined (CONFIG_440GX) || defined(CONFIG_440SP)
+ #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr isram0_sb3cr,r1
+ #elif defined(CONFIG_440SPE)
+ lis r1,0x0000 /* BAS = 0000_0000 */
+ ori r1,r1,0x0984 /* first 64k */
+ mtdcr isram0_sb0cr,r1
+ lis r1,0x0001
+ ori r1,r1,0x0984 /* second 64k */
+ mtdcr isram0_sb1cr,r1
+ lis r1, 0x0002
+ ori r1,r1, 0x0984 /* third 64k */
+ mtdcr isram0_sb2cr,r1
+ lis r1, 0x0003
+ ori r1,r1, 0x0984 /* fourth 64k */
+ mtdcr isram0_sb3cr,r1
#else
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
mtspr esr,r0 /* clear Exception Syndrome Reg */
mttcr r0 /* timer control register */
mtexier r0 /* disable all interrupts */
- addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
- oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */
- mtmsr r4 /* change MSR */
addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
mtdbsr r4 /* clear/reset the dbsr */
mttcr r4 /* clear Timer Control Reg */
mtxer r4 /* clear Fixed-Point Exception Reg */
mtevpr r4 /* clear Exception Vector Prefix Reg */
- addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
- oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
- mtmsr r4 /* change MSR */
addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
/* dbsr is cleared by setting bits to 1) */
mtdbsr r4 /* clear/reset the dbsr */
*/
.globl relocate_code
relocate_code:
- #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
- dccci 0,0 /* Invalidate data cache, now no longer our stack */
+ /*
+ * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
+ * to speed up the boot process. Now this cache needs to be disabled.
+ */
+ iccci 0,0 /* Invalidate inst cache */
+ dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
+ isync
addi r1,r0,0x0000 /* TLB entry #0 */
tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
+ sync
isync
#endif
mr r1, r3 /* Set new stack pointer */
cmplw 0, r7, r8
blt 4b
- #if !defined(CONFIG_440_GX)
++#if !defined(CONFIG_440_GX) && !defined(CONFIG_440SPE)
+ addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
+ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
+ mtmsr r7 /* change MSR */
+#else
+ bl __440gx_msr_set
+ b __440gx_msr_continue
+
+__440gx_msr_set:
+ addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
+ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
+ mtspr srr1,r7
+ mflr r7
+ mtspr srr0,r7
+ rfi
+__440gx_msr_continue:
+#endif
+
mtlr r4 /* restore link register */
blr
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
*(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
- #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
if (PCI_BUS(dev) > 0) \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
else \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
+ u32 b, d,f; \
+ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
+ b = b - hose->first_busno; \
+ dev = PCI_BDF(b, d, f); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
+ #define PVR_440SPe_RA 0x53421890
+ #define PVR_440SPe_RB 0x53521891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
defined (CONFIG_75x) || \
defined (CONFIG_74xx) || \
defined (CONFIG_MPC8220) || \
- defined(CONFIG_MPC85xx)
+ defined (CONFIG_MPC85xx) || \
+ defined (CONFIG_MPC83XX)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
unsigned short in16(unsigned int);
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
+ # if defined(CONFIG_440SPE)
+ unsigned long determine_sysper(void);
+ unsigned long determine_pci_clock_per(void);
+ # endif
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
+ #define xer_reg 0x001
+ #define lr_reg 0x008
#define dec 0x016 /* decrementer */
#define srr0 0x01a /* save/restore register 0 */
#define srr1 0x01b /* save/restore register 1 */
#define ivpr 0x03f /* interrupt prefix register */
#define usprg0 0x100 /* user special purpose register general 0 */
#define usprg1 0x110 /* user special purpose register general 1 */
+ #define tblr 0x10c /* time base lower, read only */
+ #define tbur 0x10d /* time base upper, read only */
#define sprg1 0x111 /* special purpose register general 1 */
#define sprg2 0x112 /* special purpose register general 2 */
#define sprg3 0x113 /* special purpose register general 3 */
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
- #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
#define sdr_malrbl 0x02a0
#define sdr_maltbs 0x02c0
#define sdr_malrbs 0x02e0
- #define sdr_pci0 0x0300
- #define sdr_usb0 0x0320
+ #define sdr_pci0 0x0300
+ #define sdr_usb0 0x0320
#define sdr_cust0 0x4000
- #define sdr_sdstp2 0x4001
#define sdr_cust1 0x4002
- #define sdr_sdstp3 0x4003
#define sdr_pfc0 0x4100 /* Pin Function 0 */
#define sdr_pfc1 0x4101 /* Pin Function 1 */
#define sdr_plbtr 0x4200
#define mem_dlycal 0x0084 /* delay line calibration register */
#define mem_eccesr 0x0098 /* ECC error status */
+ #ifdef CONFIG_440_GX
+ #define sdr_amp 0x0240
+ #define sdr_xpllc 0x01c1
+ #define sdr_xplld 0x01c2
+ #define sdr_xcr 0x01c0
+ #define sdr_sdstp2 0x4001
+ #define sdr_sdstp3 0x4003
+ #endif /* CONFIG_440_GX */
+
+ #ifdef CONFIG_440SPE
+ #undef sdr_sdstp2
+ #define sdr_sdstp2 0x0022
+ #undef sdr_sdstp3
+ #define sdr_sdstp3 0x0023
+ #define sdr_ddr0 0x00E1
+ #define sdr_uart2 0x0122
+ #define sdr_xcr0 0x01c0
+ /* #define sdr_xcr1 0x01c3 only one PCIX - SG */
+ /* #define sdr_xcr2 0x01c6 only one PCIX - SG */
+ #define sdr_xpllc0 0x01c1
+ #define sdr_xplld0 0x01c2
+ #define sdr_xpllc1 0x01c4 /*notRCW - SG */
+ #define sdr_xplld1 0x01c5 /*notRCW - SG */
+ #define sdr_xpllc2 0x01c7 /*notRCW - SG */
+ #define sdr_xplld2 0x01c8 /*notRCW - SG */
+ #define sdr_amp0 0x0240
+ #define sdr_amp1 0x0241
+ #define sdr_cust2 0x4004
+ #define sdr_cust3 0x4006
+ #define sdr_sdstp4 0x4001
+ #define sdr_sdstp5 0x4003
+ #define sdr_sdstp6 0x4005
+ #define sdr_sdstp7 0x4007
+
+ /*----------------------------------------------------------------------------+
+ | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+ +----------------------------------------------------------------------------*/
+ #define CCR0_PRE 0x40000000
+ #define CCR0_CRPE 0x08000000
+ #define CCR0_DSTG 0x00200000
+ #define CCR0_DAPUIB 0x00100000
+ #define CCR0_DTB 0x00008000
+ #define CCR0_GICBT 0x00004000
+ #define CCR0_GDCBT 0x00002000
+ #define CCR0_FLSTA 0x00000100
+ #define CCR0_ICSLC_MASK 0x0000000C
+ #define CCR0_ICSLT_MASK 0x00000003
+ #define CCR1_TCS_MASK 0x00000080
+ #define CCR1_TCS_INTCLK 0x00000000
+ #define CCR1_TCS_EXTCLK 0x00000080
+ #define MMUCR_SEOA 0x01000000
+ #define MMUCR_U1TE 0x00400000
+ #define MMUCR_U2SWOAE 0x00200000
+ #define MMUCR_DULXE 0x00800000
+ #define MMUCR_IULXE 0x00400000
+ #define MMUCR_STS 0x00100000
+ #define MMUCR_STID_MASK 0x000000FF
+
+ #define SDR0_CFGADDR 0x00E
+ #define SDR0_CFGDATA 0x00F
+
+ /******************************************************************************
+ * PCI express defines
+ ******************************************************************************/
+ #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
+ #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
+ #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
+ #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
+ #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
+ #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
+ #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
+ #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
+ #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
+ #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
+ #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
+ #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
+ #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
+ #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
+ #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
+ #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
+ #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
+ #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
+ #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
+ #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
+ #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
+ #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
+ #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
+ #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
+ #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
+ #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
+ #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
+ #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
+ #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
+ #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
+ #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
+ #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
+ #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
+
+ #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
+ #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
+ #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
+ #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
+ #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
+ #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
+ #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
+ #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
+ #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
+ #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
+ #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
+ #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
+ #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
+ #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
+ #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
+ #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
+ #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
+ #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
+ #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
+ #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
+ #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
+ #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
+ #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
+ #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
+ #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
+ #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
+ #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
+ #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
+ #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
+ #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
+ #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
+ #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
+ #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
+ #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
+ #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
+ #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
+ #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
+ #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
+ #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
+ #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
+ #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
+ #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
+ #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
+
+ /*----------------------------------------------------------------------------+
+ | SDRAM Controller
+ +----------------------------------------------------------------------------*/
+ /*-----------------------------------------------------------------------------+
+ | SDRAM DLYCAL Options
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
+ #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+ #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+ /*----------------------------------------------------------------------------+
+ | Memory queue defines
+ +----------------------------------------------------------------------------*/
+ /* A REVOIR versus RWC - SG*/
+ #define SDRAMQ_DCR_BASE 0x040
+
+ #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
+ #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
+ #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
+ #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
+ #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
+ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
+ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
+ #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
+ #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
+ #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
+ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
+ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
+ #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
+ #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
+ #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
+
+ /*-----------------------------------------------------------------------------+
+ | Memory Bank 0-7 configuration
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
+ #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
+ #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
+ #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
+ #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
+ #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
+ #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
+ #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
+ #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
+ #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
+ #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
+ #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
+ #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
+ #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
+ #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
+ #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
+
+ /*----------------------------------------------------------------------------+
+ | Memory controller defines
+ +----------------------------------------------------------------------------*/
+ #define SDRAMC_DCR_BASE 0x010
+ #define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */
+ #define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */
+
+ /* A REVOIR versus specs 4 bank - SG*/
+ #define SDRAM_MCSTAT 0x14 /* memory controller status */
+ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
+ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
+ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
+ #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
+ #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
+ #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
+ #define SDRAM_CODT 0x26 /* on die termination for controller */
+ #define SDRAM_VVPR 0x27 /* variable VRef programmming */
+ #define SDRAM_OPARS 0x28 /* on chip driver control setup */
+ #define SDRAM_OPART 0x29 /* on chip driver control trigger */
+ #define SDRAM_RTR 0x30 /* refresh timer */
+ #define SDRAM_PMIT 0x34 /* power management idle timer */
+ #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
+ #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
+ #define SDRAM_MB2CF 0x48
+ #define SDRAM_MB3CF 0x4C
+ #define SDRAM_INITPLR0 0x50 /* manual initialization control */
+ #define SDRAM_INITPLR1 0x51 /* manual initialization control */
+ #define SDRAM_INITPLR2 0x52 /* manual initialization control */
+ #define SDRAM_INITPLR3 0x53 /* manual initialization control */
+ #define SDRAM_INITPLR4 0x54 /* manual initialization control */
+ #define SDRAM_INITPLR5 0x55 /* manual initialization control */
+ #define SDRAM_INITPLR6 0x56 /* manual initialization control */
+ #define SDRAM_INITPLR7 0x57 /* manual initialization control */
+ #define SDRAM_INITPLR8 0x58 /* manual initialization control */
+ #define SDRAM_INITPLR9 0x59 /* manual initialization control */
+ #define SDRAM_INITPLR10 0x5a /* manual initialization control */
+ #define SDRAM_INITPLR11 0x5b /* manual initialization control */
+ #define SDRAM_INITPLR12 0x5c /* manual initialization control */
+ #define SDRAM_INITPLR13 0x5d /* manual initialization control */
+ #define SDRAM_INITPLR14 0x5e /* manual initialization control */
+ #define SDRAM_INITPLR15 0x5f /* manual initialization control */
+ #define SDRAM_RQDC 0x70 /* read DQS delay control */
+ #define SDRAM_RFDC 0x74 /* read feedback delay control */
+ #define SDRAM_RDCC 0x78 /* read data capture control */
+ #define SDRAM_DLCR 0x7A /* delay line calibration */
+ #define SDRAM_CLKTR 0x80 /* DDR clock timing */
+ #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
+ #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
+ #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
+ #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
+ #define SDRAM_MMODE 0x88 /* memory mode */
+ #define SDRAM_MEMODE 0x89 /* memory extended mode */
+ #define SDRAM_ECCCR 0x98 /* ECC error status */
+ #define SDRAM_CID 0xA4 /* core ID */
+ #define SDRAM_RID 0xA8 /* revision ID */
+
+ /*-----------------------------------------------------------------------------+
+ | Memory Controller Status
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
+ #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
+ #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
+ #define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
+ #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
+ #define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
+
+ /*-----------------------------------------------------------------------------+
+ | Memory Controller Options 1
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
+ #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
+ #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
+ #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
+ #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
+ #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
+ #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
+ #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
+ #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
+ #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
+ #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
+ #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
+ #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
+ #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
+ #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
+ #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
+ #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
+ #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
+ #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
+ #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
+ #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
+ #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
+ #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
+ #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
+ #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
+ #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
+ #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
+ #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
+ #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
+ #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
+ #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
+ #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
+ #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
+ #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
+ #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
+
+ /*-----------------------------------------------------------------------------+
+ | Memory Controller Options 2
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
+ #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
+ #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
+ #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
+ #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
+ #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
+ #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
+ #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
+ #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
+ #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
+ #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
+ #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
+ #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
+ #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
+ #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
+ #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
+ #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
+ #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Refresh Timer Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_RTR_RINT_MASK 0xFFF80000
+ #define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
+ #define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Read DQS Delay Control Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_RQDC_RQDE_MASK 0x80000000
+ #define SDRAM_RQDC_RQDE_DISABLE 0x00000000
+ #define SDRAM_RQDC_RQDE_ENABLE 0x80000000
+ #define SDRAM_RQDC_RQFD_MASK 0x000001FF
+ #define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+
+ #define SDRAM_RQDC_RQFD_MAX 0x1FF
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Read Data Capture Control Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_RDCC_RDSS_MASK 0xC0000000
+ #define SDRAM_RDCC_RDSS_T1 0x00000000
+ #define SDRAM_RDCC_RDSS_T2 0x40000000
+ #define SDRAM_RDCC_RDSS_T3 0x80000000
+ #define SDRAM_RDCC_RDSS_T4 0xC0000000
+ #define SDRAM_RDCC_RSAE_MASK 0x00000001
+ #define SDRAM_RDCC_RSAE_DISABLE 0x00000001
+ #define SDRAM_RDCC_RSAE_ENABLE 0x00000000
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Read Feedback Delay Control Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_RFDC_ARSE_MASK 0x80000000
+ #define SDRAM_RFDC_ARSE_DISABLE 0x80000000
+ #define SDRAM_RFDC_ARSE_ENABLE 0x00000000
+ #define SDRAM_RFDC_RFOS_MASK 0x007F0000
+ #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+ #define SDRAM_RFDC_RFFD_MASK 0x000003FF
+ #define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+
+ #define SDRAM_RFDC_RFFD_MAX 0x7FF
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Delay Line Calibration Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_DLCR_DCLM_MASK 0x80000000
+ #define SDRAM_DLCR_DCLM_MANUEL 0x80000000
+ #define SDRAM_DLCR_DCLM_AUTO 0x00000000
+ #define SDRAM_DLCR_DLCR_MASK 0x08000000
+ #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
+ #define SDRAM_DLCR_DLCR_IDLE 0x00000000
+ #define SDRAM_DLCR_DLCS_MASK 0x07000000
+ #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
+ #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
+ #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
+ #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
+ #define SDRAM_DLCR_DLCS_ERROR 0x04000000
+ #define SDRAM_DLCR_DLCV_MASK 0x000001FF
+ #define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+ #define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Controller On Die Termination Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_CODT_ODT_ON 0x80000000
+ #define SDRAM_CODT_ODT_OFF 0x00000000
+ #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
+ #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
+ #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
+ #define SDRAM_CODT_DQS_MASK 0x00000010
+ #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
+ #define SDRAM_CODT_DQS_SINGLE_END 0x00000010
+ #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
+ #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
+ #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
+ #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
+ #define SDRAM_CODT_IO_HIZ 0x00000000
+ #define SDRAM_CODT_IO_NMODE 0x00000001
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Mode Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_MMODE_WR_MASK 0x00000E00
+ #define SDRAM_MMODE_WR_DDR1 0x00000000
+ #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
+ #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
+ #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
+ #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
+ #define SDRAM_MMODE_DCL_MASK 0x00000070
+ #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
+ #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
+ #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
+ #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
+ #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
+ #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
+ #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
+ #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
+ #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Extended Mode Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_MEMODE_DIC_MASK 0x00000002
+ #define SDRAM_MEMODE_DIC_NORMAL 0x00000000
+ #define SDRAM_MEMODE_DIC_WEAK 0x00000002
+ #define SDRAM_MEMODE_DLL_MASK 0x00000001
+ #define SDRAM_MEMODE_DLL_DISABLE 0x00000001
+ #define SDRAM_MEMODE_DLL_ENABLE 0x00000000
+ #define SDRAM_MEMODE_RTT_MASK 0x00000044
+ #define SDRAM_MEMODE_RTT_DISABLED 0x00000000
+ #define SDRAM_MEMODE_RTT_75OHM 0x00000004
+ #define SDRAM_MEMODE_RTT_150OHM 0x00000040
+ #define SDRAM_MEMODE_DQS_MASK 0x00000400
+ #define SDRAM_MEMODE_DQS_DISABLE 0x00000400
+ #define SDRAM_MEMODE_DQS_ENABLE 0x00000000
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Clock Timing Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+ #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
+ #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM Write Timing Register
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_WRDTR_LLWP_MASK 0x10000000
+ #define SDRAM_WRDTR_LLWP_DIS 0x10000000
+ #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
+ #define SDRAM_WRDTR_WTR_MASK 0x0E000000
+ #define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+ #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
+ #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM SDTR1 Options
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_SDTR1_LDOF_MASK 0x80000000
+ #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
+ #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
+ #define SDRAM_SDTR1_RTW_MASK 0x00F00000
+ #define SDRAM_SDTR1_RTW_2_CLK 0x00200000
+ #define SDRAM_SDTR1_RTW_3_CLK 0x00300000
+ #define SDRAM_SDTR1_WTWO_MASK 0x000F0000
+ #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
+ #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
+ #define SDRAM_SDTR1_RTRO_MASK 0x0000F000
+ #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
+ #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM SDTR2 Options
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_SDTR2_RCD_MASK 0xF0000000
+ #define SDRAM_SDTR2_RCD_1_CLK 0x10000000
+ #define SDRAM_SDTR2_RCD_2_CLK 0x20000000
+ #define SDRAM_SDTR2_RCD_3_CLK 0x30000000
+ #define SDRAM_SDTR2_RCD_4_CLK 0x40000000
+ #define SDRAM_SDTR2_RCD_5_CLK 0x50000000
+ #define SDRAM_SDTR2_WTR_MASK 0x0F000000
+ #define SDRAM_SDTR2_WTR_1_CLK 0x01000000
+ #define SDRAM_SDTR2_WTR_2_CLK 0x02000000
+ #define SDRAM_SDTR2_WTR_3_CLK 0x03000000
+ #define SDRAM_SDTR2_WTR_4_CLK 0x04000000
+ #define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+ #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
+ #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
+ #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
+ #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
+ #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
+ #define SDRAM_SDTR2_WPC_MASK 0x0000F000
+ #define SDRAM_SDTR2_WPC_2_CLK 0x00002000
+ #define SDRAM_SDTR2_WPC_3_CLK 0x00003000
+ #define SDRAM_SDTR2_WPC_4_CLK 0x00004000
+ #define SDRAM_SDTR2_WPC_5_CLK 0x00005000
+ #define SDRAM_SDTR2_WPC_6_CLK 0x00006000
+ #define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
+ #define SDRAM_SDTR2_RPC_MASK 0x00000F00
+ #define SDRAM_SDTR2_RPC_2_CLK 0x00000200
+ #define SDRAM_SDTR2_RPC_3_CLK 0x00000300
+ #define SDRAM_SDTR2_RPC_4_CLK 0x00000400
+ #define SDRAM_SDTR2_RP_MASK 0x000000F0
+ #define SDRAM_SDTR2_RP_3_CLK 0x00000030
+ #define SDRAM_SDTR2_RP_4_CLK 0x00000040
+ #define SDRAM_SDTR2_RP_5_CLK 0x00000050
+ #define SDRAM_SDTR2_RP_6_CLK 0x00000060
+ #define SDRAM_SDTR2_RP_7_CLK 0x00000070
+ #define SDRAM_SDTR2_RRD_MASK 0x0000000F
+ #define SDRAM_SDTR2_RRD_2_CLK 0x00000002
+ #define SDRAM_SDTR2_RRD_3_CLK 0x00000003
+
+ /*-----------------------------------------------------------------------------+
+ | SDRAM SDTR3 Options
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_SDTR3_RAS_MASK 0x1F000000
+ #define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+ #define SDRAM_SDTR3_RC_MASK 0x001F0000
+ #define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+ #define SDRAM_SDTR3_XCS_MASK 0x00001F00
+ #define SDRAM_SDTR3_XCS 0x00000D00
+ #define SDRAM_SDTR3_RFC_MASK 0x0000003F
+ #define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+
+ /*-----------------------------------------------------------------------------+
+ | Memory Bank 0-1 configuration
+ +-----------------------------------------------------------------------------*/
+ #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
+ #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
+ #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
+ #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
+ #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
+ #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
+ #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
+ #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
+ #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
+ #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
+ #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
+ #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
+ #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
+ #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
+ #endif /* CONFIG_440SPE */
+
+ #ifndef CONFIG_440_GX
+ #endif /* not CONFIG_440SPE */
+
/*-----------------------------------------------------------------------------
| External Bus Controller
+----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
- #if defined (CONFIG_440GX) || defined(CONFIG_440SP)
+ #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
- #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
+ #if defined(CONFIG_440SPE)
+ #define UIC2_DCR_BASE 0xe0
+ #define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
+ #define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
+ #define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */
+ #define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */
+ #define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */
+ #define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */
+ #define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */
+ #define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */
+ #define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */
+
+ #define UIC3_DCR_BASE 0xf0
+ #define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */
+ #define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */
+ #define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */
+ #define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */
+ #define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */
+ #define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */
+ #define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */
+ #define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */
+ #define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */
+ #endif /* CONFIG_440SPE */
+
#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
#define uicvr uic0vr
#define uicvcr uic0vcr
+ #if defined(CONFIG_440SPE)
+ /*----------------------------------------------------------------------------+
+ | Clock / Power-on-reset DCR's.
+ +----------------------------------------------------------------------------*/
+ #define CPR0_CFGADDR 0x00C
+ #define CPR0_CFGDATA 0x00D
+
+ #define CPR0_CLKUPD 0x20
+ #define CPR0_CLKUPD_BSY_MASK 0x80000000
+ #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
+ #define CPR0_CLKUPD_BSY_BUSY 0x80000000
+ #define CPR0_CLKUPD_CUI_MASK 0x80000000
+ #define CPR0_CLKUPD_CUI_DISABLE 0x00000000
+ #define CPR0_CLKUPD_CUI_ENABLE 0x80000000
+ #define CPR0_CLKUPD_CUD_MASK 0x40000000
+ #define CPR0_CLKUPD_CUD_DISABLE 0x00000000
+ #define CPR0_CLKUPD_CUD_ENABLE 0x40000000
+
+ #define CPR0_PLLC 0x40
+ #define CPR0_PLLC_RST_MASK 0x80000000
+ #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
+ #define CPR0_PLLC_RST_PLLRESET 0x80000000
+ #define CPR0_PLLC_ENG_MASK 0x40000000
+ #define CPR0_PLLC_ENG_DISABLE 0x00000000
+ #define CPR0_PLLC_ENG_ENABLE 0x40000000
+ #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+ #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+ #define CPR0_PLLC_SRC_MASK 0x20000000
+ #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
+ #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
+ #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+ #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+ #define CPR0_PLLC_SEL_MASK 0x07000000
+ #define CPR0_PLLC_SEL_PLLOUT 0x00000000
+ #define CPR0_PLLC_SEL_CPU 0x01000000
+ #define CPR0_PLLC_SEL_EBC 0x05000000
+ #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+ #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
+ #define CPR0_PLLC_TUNE_MASK 0x000003FF
+ #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+ #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+ #define CPR0_PLLD 0x60
+ #define CPR0_PLLD_FBDV_MASK 0x1F000000
+ #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+ #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+ #define CPR0_PLLD_FWDVA_MASK 0x000F0000
+ #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
+ #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+ #define CPR0_PLLD_FWDVB_MASK 0x00000700
+ #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
+ #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+ #define CPR0_PLLD_LFBDV_MASK 0x0000003F
+ #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+ #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+
+ #define CPR0_PRIMAD 0x80
+ #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
+ #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+ #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+
+ #define CPR0_PRIMBD 0xA0
+ #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
+ #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+ #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+
+ #define CPR0_OPBD 0xC0
+ #define CPR0_OPBD_OPBDV0_MASK 0x03000000
+ #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+ #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+ #define CPR0_PERD 0xE0
+ #define CPR0_PERD_PERDV0_MASK 0x03000000
+ #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+ #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+ #define CPR0_MALD 0x100
+ #define CPR0_MALD_MALDV0_MASK 0x03000000
+ #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+ #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+ #define CPR0_ICFG 0x140
+ #define CPR0_ICFG_RLI_MASK 0x80000000
+ #define CPR0_ICFG_RLI_RESETCPR 0x00000000
+ #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
+ #define CPR0_ICFG_ICS_MASK 0x00000007
+ #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+ #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+
+ /************************/
+ /* IIC defines */
+ /************************/
+ #define IIC0_MMIO_BASE 0xA0000400
+ #define IIC1_MMIO_BASE 0xA0000500
+
+ #endif /* CONFIG_440SP */
+
/*-----------------------------------------------------------------------------
| DMA
+----------------------------------------------------------------------------*/
#define UIC_GPTCT 0x00000004 /* GPT count timer */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
- #else /* CONFIG_440SP */
+ #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
- #endif /* CONFIG_440SP */
+ #elif !defined(CONFIG_440SPE)
+ #define UIC_U0 0x80000000 /* UART 0 */
+ #define UIC_U1 0x40000000 /* UART 1 */
+ #define UIC_IIC0 0x20000000 /* IIC */
+ #define UIC_IIC1 0x10000000 /* IIC */
+ #define UIC_PIM 0x08000000 /* PCI inbound message */
+ #define UIC_PCRW 0x04000000 /* PCI command register write */
+ #define UIC_PPM 0x02000000 /* PCI power management */
+ #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
+ #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
+ #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
+ #define UIC_MTE 0x00200000 /* MAL TXEOB */
+ #define UIC_MRE 0x00100000 /* MAL RXEOB */
+ #define UIC_D0 0x00080000 /* DMA channel 0 */
+ #define UIC_D1 0x00040000 /* DMA channel 1 */
+ #define UIC_D2 0x00020000 /* DMA channel 2 */
+ #define UIC_D3 0x00010000 /* DMA channel 3 */
+ #define UIC_RSVD0 0x00008000 /* Reserved */
+ #define UIC_RSVD1 0x00004000 /* Reserved */
+ #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
+ #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
+ #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
+ #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
+ #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
+ #define UIC_EIR0 0x00000100 /* External interrupt 0 */
+ #define UIC_EIR1 0x00000080 /* External interrupt 1 */
+ #define UIC_EIR2 0x00000040 /* External interrupt 2 */
+ #define UIC_EIR3 0x00000020 /* External interrupt 3 */
+ #define UIC_EIR4 0x00000010 /* External interrupt 4 */
+ #define UIC_EIR5 0x00000008 /* External interrupt 5 */
+ #define UIC_EIR6 0x00000004 /* External interrupt 6 */
+ #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
+ #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+ #endif /* CONFIG_440GX */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Reserved */
#define UIC_XOR 0x00000001 /* XOR */
- #else /* CONFIG_440SP */
+ #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
+ #define UIC_MS 0x80000000 /* MAL SERR */
+ #define UIC_MTDE 0x40000000 /* MAL TXDE */
+ #define UIC_MRDE 0x20000000 /* MAL RXDE */
+ #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
+ #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
+ #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+ #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
+ #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
+ #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
+ #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
+ #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
+ #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
+ #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
+ #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
+ #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
+ #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
+ #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
+ #define UIC_PPMI 0x00004000 /* PPM interrupt status */
+ #define UIC_EIR7 0x00002000 /* External interrupt 7 */
+ #define UIC_EIR8 0x00001000 /* External interrupt 8 */
+ #define UIC_EIR9 0x00000800 /* External interrupt 9 */
+ #define UIC_EIR10 0x00000400 /* External interrupt 10 */
+ #define UIC_EIR11 0x00000200 /* External interrupt 11 */
+ #define UIC_EIR12 0x00000100 /* External interrupt 12 */
+ #define UIC_SRE 0x00000080 /* Serial ROM error */
+ #define UIC_RSVD2 0x00000040 /* Reserved */
+ #define UIC_RSVD3 0x00000020 /* Reserved */
+ #define UIC_PAE 0x00000010 /* PCI asynchronous error */
+ #define UIC_ETH0 0x00000008 /* Ethernet 0 */
+ #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+ #define UIC_ETH1 0x00000002 /* Ethernet 1 */
+ #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+ #elif !defined(CONFIG_440SPE)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
- #endif /* CONFIG_440GX */
+ #endif /* CONFIG_440_GX */
+ /*---------------------------------------------------------------------------+
+ | Universal interrupt controller interrupts
+ +---------------------------------------------------------------------------*/
+ #if defined(CONFIG_440SPE)
+ /*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
+ /*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
+ #define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
+ #define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
+ #define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
+ #define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
+ #define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
+ #define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
+
+ #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
+ UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
+ /*---------------------------------------------------------------------------+
+ | Universal interrupt controller 0 interrupts (UIC0)
+ +---------------------------------------------------------------------------*/
+ #define UIC_U0 0x80000000 /* UART 0 */
+ #define UIC_U1 0x40000000 /* UART 1 */
+ #define UIC_IIC0 0x20000000 /* IIC */
+ #define UIC_IIC1 0x10000000 /* IIC */
+ #define UIC_PIM 0x08000000 /* PCI inbound message */
+ #define UIC_PCRW 0x04000000 /* PCI command register write */
+ #define UIC_PPM 0x02000000 /* PCI power management */
+ #define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
+ #define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
+ #define UIC_EIR15 0x00400000 /* External intp 15 */
+ #define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
+ #define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
+ #define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
+ #define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
+ #define UIC_EIR14 0x00002000 /* External interrupt 14 */
+ #define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
+ #define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
+ #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
+ #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
+ #define UIC_I2OID 0x00000100 /* I2O inbound door bell */
+ #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
+ #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
+ #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
+ #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
+ #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
+ #define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
+ /*---------------------------------------------------------------------------+
+ | Universal interrupt controller 1 interrupts (UIC1)
+ +---------------------------------------------------------------------------*/
+ #define UIC_EIR13 0x80000000 /* externei intp 13 */
+ #define UIC_MS 0x40000000 /* MAL SERR */
+ #define UIC_MTDE 0x20000000 /* MAL TXDE */
+ #define UIC_MRDE 0x10000000 /* MAL RXDE */
+ #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
+ #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+ #define UIC_MTE 0x02000000 /* MAL TXEOB */
+ #define UIC_MRE 0x01000000 /* MAL RXEOB */
+ #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
+ #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
+ #define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
+ #define UIC_L2C 0x00100000 /* L2 cache */
+ #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
+ #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
+ #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
+ #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
+ #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
+ #define UIC_EIR12 0x00004000 /* External interrupt 12 */
+ #define UIC_EIR11 0x00002000 /* External interrupt 11 */
+ #define UIC_EIR10 0x00001000 /* External interrupt 10 */
+ #define UIC_EIR9 0x00000800 /* External interrupt 9 */
+ #define UIC_EIR8 0x00000400 /* External interrupt 8 */
+ #define UIC_DMAE 0x00000200 /* dma error */
+ #define UIC_I2OE 0x00000100 /* i2o error */
+ #define UIC_SRE 0x00000080 /* Serial ROM error */
+ #define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
+ #define UIC_EIR7 0x00000020 /* External interrupt 7 */
+ #define UIC_EIR6 0x00000010 /* External interrupt 6 */
+ #define UIC_ETH0 0x00000008 /* Ethernet 0 */
+ #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+ #define UIC_ETH1 0x00000002 /* reserved */
+ #define UIC_XOR 0x00000001 /* xor */
+
+ /*---------------------------------------------------------------------------+
+ | Universal interrupt controller 2 interrupts (UIC2)
+ +---------------------------------------------------------------------------*/
+ #define UIC_PEOAL 0x80000000 /* PE0 AL */
+ #define UIC_PEOVA 0x40000000 /* PE0 VPD access */
+ #define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
+ #define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
+ #define UIC_PE0TCR 0x08000000 /* PE0 TCR */
+ #define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
+ #define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
+ #define UIC_PE1AL 0x00800000 /* PE1 AL */
+ #define UIC_PE1VA 0x00400000 /* PE1 VPD access */
+ #define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
+ #define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
+ #define UIC_PE1TCR 0x00080000 /* PE1 TCR */
+ #define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
+ #define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
+ #define UIC_PE2AL 0x00008000 /* PE2 AL */
+ #define UIC_PE2VA 0x00004000 /* PE2 VPD access */
+ #define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
+ #define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
+ #define UIC_PE2TCR 0x00000800 /* PE2 TCR */
+ #define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
+ #define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
+ #define UIC_EIR5 0x00000080 /* External interrupt 5 */
+ #define UIC_EIR4 0x00000040 /* External interrupt 4 */
+ #define UIC_EIR3 0x00000020 /* External interrupt 3 */
+ #define UIC_EIR2 0x00000010 /* External interrupt 2 */
+ #define UIC_EIR1 0x00000008 /* External interrupt 1 */
+ #define UIC_EIR0 0x00000004 /* External interrupt 0 */
+ #endif /* CONFIG_440SPE */
/*-----------------------------------------------------------------------------+
| External Bus Controller Bit Settings
/*-----------------------------------------------------------------------------+
| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
+ #if defined(CONFIG_440SPE)
+ #define SDR0_CP440 0x0180
+ #define SDR0_CP440_ERPN_MASK 0x30000000
+ #define SDR0_CP440_ERPN_MASK_HI 0x3000
+ #define SDR0_CP440_ERPN_MASK_LO 0x0000
+ #define SDR0_CP440_ERPN_EBC 0x10000000
+ #define SDR0_CP440_ERPN_EBC_HI 0x1000
+ #define SDR0_CP440_ERPN_EBC_LO 0x0000
+ #define SDR0_CP440_ERPN_PCI 0x20000000
+ #define SDR0_CP440_ERPN_PCI_HI 0x2000
+ #define SDR0_CP440_ERPN_PCI_LO 0x0000
+ #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
+ #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
+ #define SDR0_CP440_NTO1_MASK 0x00000002
+ #define SDR0_CP440_NTO1_NTOP 0x00000000
+ #define SDR0_CP440_NTO1_NTO1 0x00000002
+ #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
+ #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
+ #define SDR0_CFGADDR 0x00E /*already defined line 277 */
+ #define SDR0_CFGDATA 0x00F
+
+
+ #define SDR0_SDSTP0 0x0020
+ #define SDR0_SDSTP0_ENG_MASK 0x80000000
+ #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
+ #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
+ #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
+ #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
+ #define SDR0_SDSTP0_SRC_MASK 0x40000000
+ #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
+ #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
+ #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+ #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+ #define SDR0_SDSTP0_SEL_MASK 0x38000000
+ #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
+ #define SDR0_SDSTP0_SEL_CPU 0x08000000
+ #define SDR0_SDSTP0_SEL_EBC 0x28000000
+ #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
+ #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
+ #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
+ #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
+ #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
+ #define SDR0_SDSTP0_FBDV_MASK 0x0001F000
+ #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
+ #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
+ #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
+ #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
+ #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
+ #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
+ #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
+ #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
+ #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
+ #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
+ #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
+ #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
+ #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
+ #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
+
+
+ #define SDR0_SDSTP1 0x0021
+ #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
+ #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
+ #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
+ #define SDR0_SDSTP1_PERDV0_MASK 0x03000000
+ #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+ #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
+ #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
+ #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
+ #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+ #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
+ #define SDR0_SDSTP1_DDR1_MODE 0x00100000
+ #define SDR0_SDSTP1_DDR2_MODE 0x00200000
+ #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
+ #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
+ #define SDR0_SDSTP1_ERPN_MASK 0x00080000
+ #define SDR0_SDSTP1_ERPN_EBC 0x00000000
+ #define SDR0_SDSTP1_ERPN_PCI 0x00080000
+ #define SDR0_SDSTP1_PAE_MASK 0x00040000
+ #define SDR0_SDSTP1_PAE_DISABLE 0x00000000
+ #define SDR0_SDSTP1_PAE_ENABLE 0x00040000
+ #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
+ #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
+ #define SDR0_SDSTP1_PHCE_MASK 0x00020000
+ #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
+ #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
+ #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
+ #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
+ #define SDR0_SDSTP1_PISE_MASK 0x00010000
+ #define SDR0_SDSTP1_PISE_DISABLE 0x00000000
+ #define SDR0_SDSTP1_PISE_ENABLE 0x00001000
+ #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
+ #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
+ #define SDR0_SDSTP1_PCWE_MASK 0x00008000
+ #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
+ #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
+ #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
+ #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
+ #define SDR0_SDSTP1_PPIM_MASK 0x00007800
+ #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
+ #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
+ #define SDR0_SDSTP1_PR64E_MASK 0x00000400
+ #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
+ #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
+ #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
+ #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
+ #define SDR0_SDSTP1_PXFS_MASK 0x00000300
+ #define SDR0_SDSTP1_PXFS_100_133 0x00000000
+ #define SDR0_SDSTP1_PXFS_66_100 0x00000100
+ #define SDR0_SDSTP1_PXFS_50_66 0x00000200
+ #define SDR0_SDSTP1_PXFS_0_50 0x00000300
+ #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+ #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+ #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
+ #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
+ #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
+ #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
+ #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
+ #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
+ #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
+ #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
+ #define SDR0_SDSTP1_ETH_MASK 0x00000004
+ #define SDR0_SDSTP1_ETH_10_100 0x00000000
+ #define SDR0_SDSTP1_ETH_GIGA 0x00000004
+ #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
+ #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
+ #define SDR0_SDSTP1_NTO1_MASK 0x00000001
+ #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
+ #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
+ #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
+ #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
+
+ #define SDR0_SDSTP2 0x0022
+ #define SDR0_SDSTP2_P1AE_MASK 0x80000000
+ #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
+ #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
+ #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
+ #define SDR0_SDSTP2_P1HCE_MASK 0x40000000
+ #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
+ #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+ #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+ #define SDR0_SDSTP2_P1ISE_MASK 0x20000000
+ #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
+ #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+ #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+ #define SDR0_SDSTP2_P1CWE_MASK 0x10000000
+ #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
+ #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
+ #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
+ #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
+ #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
+ #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+ #define SDR0_SDSTP2_P1R64E_MASK 0x00800000
+ #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
+ #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
+ #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
+ #define SDR0_SDSTP2_P1XFS_MASK 0x00600000
+ #define SDR0_SDSTP2_P1XFS_100_133 0x00000000
+ #define SDR0_SDSTP2_P1XFS_66_100 0x00200000
+ #define SDR0_SDSTP2_P1XFS_50_66 0x00400000
+ #define SDR0_SDSTP2_P1XFS_0_50 0x00600000
+ #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
+ #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
+ #define SDR0_SDSTP2_P2AE_MASK 0x00040000
+ #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
+ #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
+ #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
+ #define SDR0_SDSTP2_P2HCE_MASK 0x00020000
+ #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
+ #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
+ #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
+ #define SDR0_SDSTP2_P2ISE_MASK 0x00010000
+ #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
+ #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
+ #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
+ #define SDR0_SDSTP2_P2CWE_MASK 0x00008000
+ #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
+ #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
+ #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
+ #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
+ #define SDR0_SDSTP2_P2PIM_MASK 0x00007800
+ #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
+ #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
+ #define SDR0_SDSTP2_P2XFS_MASK 0x00000300
+ #define SDR0_SDSTP2_P2XFS_100_133 0x00000000
+ #define SDR0_SDSTP2_P2XFS_66_100 0x00000100
+ #define SDR0_SDSTP2_P2XFS_50_66 0x00000200
+ #define SDR0_SDSTP2_P2XFS_0_50 0x00000100
+ #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+ #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+
+ #define SDR0_SDSTP3 0x0023
+
+ #define SDR0_PINSTP 0x0040
+ #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
+ #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
+ #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
+ #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
+ #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
+ #define SDR0_SDCS 0x0060
+ #define SDR0_ECID0 0x0080
+ #define SDR0_ECID1 0x0081
+ #define SDR0_ECID2 0x0082
+ #define SDR0_JTAG 0x00C0
+
+ #define SDR0_DDR0 0x00E1
+ #define SDR0_DDR0_DPLLRST 0x80000000
+ #define SDR0_DDR0_DDRM_MASK 0x60000000
+ #define SDR0_DDR0_DDRM_DDR1 0x20000000
+ #define SDR0_DDR0_DDRM_DDR2 0x40000000
+ #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
+ #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
+ #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
+ #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
+
+ #define SDR0_UART0 0x0120
+ #define SDR0_UART1 0x0121
+ #define SDR0_UART2 0x0122
+ #define SDR0_UARTX_UXICS_MASK 0xF0000000
+ #define SDR0_UARTX_UXICS_PLB 0x20000000
+ #define SDR0_UARTX_UXEC_MASK 0x00800000
+ #define SDR0_UARTX_UXEC_INT 0x00000000
+ #define SDR0_UARTX_UXEC_EXT 0x00800000
+ #define SDR0_UARTX_UXDIV_MASK 0x000000FF
+ #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+ #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
+
+ #define SDR0_CP440 0x0180
+ #define SDR0_CP440_ERPN_MASK 0x30000000
+ #define SDR0_CP440_ERPN_MASK_HI 0x3000
+ #define SDR0_CP440_ERPN_MASK_LO 0x0000
+ #define SDR0_CP440_ERPN_EBC 0x10000000
+ #define SDR0_CP440_ERPN_EBC_HI 0x1000
+ #define SDR0_CP440_ERPN_EBC_LO 0x0000
+ #define SDR0_CP440_ERPN_PCI 0x20000000
+ #define SDR0_CP440_ERPN_PCI_HI 0x2000
+ #define SDR0_CP440_ERPN_PCI_LO 0x0000
+ #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
+ #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
+ #define SDR0_CP440_NTO1_MASK 0x00000002
+ #define SDR0_CP440_NTO1_NTOP 0x00000000
+ #define SDR0_CP440_NTO1_NTO1 0x00000002
+ #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
+ #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
+
+ #define SDR0_XCR0 0x01C0
+ #define SDR0_XCR1 0x01C3
+ #define SDR0_XCR2 0x01C6
+ #define SDR0_XCRn_PAE_MASK 0x80000000
+ #define SDR0_XCRn_PAE_DISABLE 0x00000000
+ #define SDR0_XCRn_PAE_ENABLE 0x80000000
+ #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
+ #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
+ #define SDR0_XCRn_PHCE_MASK 0x40000000
+ #define SDR0_XCRn_PHCE_DISABLE 0x00000000
+ #define SDR0_XCRn_PHCE_ENABLE 0x40000000
+ #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+ #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+ #define SDR0_XCRn_PISE_MASK 0x20000000
+ #define SDR0_XCRn_PISE_DISABLE 0x00000000
+ #define SDR0_XCRn_PISE_ENABLE 0x20000000
+ #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+ #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+ #define SDR0_XCRn_PCWE_MASK 0x10000000
+ #define SDR0_XCRn_PCWE_DISABLE 0x00000000
+ #define SDR0_XCRn_PCWE_ENABLE 0x10000000
+ #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
+ #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
+ #define SDR0_XCRn_PPIM_MASK 0x0F000000
+ #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
+ #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+ #define SDR0_XCRn_PR64E_MASK 0x00800000
+ #define SDR0_XCRn_PR64E_DISABLE 0x00000000
+ #define SDR0_XCRn_PR64E_ENABLE 0x00800000
+ #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
+ #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
+ #define SDR0_XCRn_PXFS_MASK 0x00600000
+ #define SDR0_XCRn_PXFS_100_133 0x00000000
+ #define SDR0_XCRn_PXFS_66_100 0x00200000
+ #define SDR0_XCRn_PXFS_50_66 0x00400000
+ #define SDR0_XCRn_PXFS_0_33 0x00600000
+ #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
+ #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
+
+ #define SDR0_XPLLC0 0x01C1
+ #define SDR0_XPLLD0 0x01C2
+ #define SDR0_XPLLC1 0x01C4
+ #define SDR0_XPLLD1 0x01C5
+ #define SDR0_XPLLC2 0x01C7
+ #define SDR0_XPLLD2 0x01C8
+ #define SDR0_SRST 0x0200
+ #define SDR0_SLPIPE 0x0220
+
+ #define SDR0_AMP0 0x0240
+ #define SDR0_AMP0_PRIORITY 0xFFFF0000
+ #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
+ #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
+
+ #define SDR0_AMP1 0x0241
+ #define SDR0_AMP1_PRIORITY 0xFC000000
+ #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
+ #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
+
+ #define SDR0_MIRQ0 0x0260
+ #define SDR0_MIRQ1 0x0261
+ #define SDR0_MALTBL 0x0280
+ #define SDR0_MALRBL 0x02A0
+ #define SDR0_MALTBS 0x02C0
+ #define SDR0_MALRBS 0x02E0
+
+ /* Reserved for Customer Use */
+ #define SDR0_CUST0 0x4000
+ #define SDR0_CUST0_AUTONEG_MASK 0x8000000
+ #define SDR0_CUST0_NO_AUTONEG 0x0000000
+ #define SDR0_CUST0_AUTONEG 0x8000000
+ #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
+ #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
+ #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
+ #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
+ #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
+ #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
+ #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
+
+ #define SDR0_SDSTP4 0x4001
+ #define SDR0_CUST1 0x4002
+ #define SDR0_SDSTP5 0x4003
+ #define SDR0_CUST2 0x4004
+ #define SDR0_SDSTP6 0x4005
+ #define SDR0_CUST3 0x4006
+ #define SDR0_SDSTP7 0x4007
+
+ #define SDR0_PFC0 0x4100
+ #define SDR0_PFC0_GPIO_0 0x80000000
+ #define SDR0_PFC0_PCIX0REQ2_N 0x00000000
+ #define SDR0_PFC0_GPIO_1 0x40000000
+ #define SDR0_PFC0_PCIX0REQ3_N 0x00000000
+ #define SDR0_PFC0_GPIO_2 0x20000000
+ #define SDR0_PFC0_PCIX0GNT2_N 0x00000000
+ #define SDR0_PFC0_GPIO_3 0x10000000
+ #define SDR0_PFC0_PCIX0GNT3_N 0x00000000
+ #define SDR0_PFC0_GPIO_4 0x08000000
+ #define SDR0_PFC0_PCIX1REQ2_N 0x00000000
+ #define SDR0_PFC0_GPIO_5 0x04000000
+ #define SDR0_PFC0_PCIX1REQ3_N 0x00000000
+ #define SDR0_PFC0_GPIO_6 0x02000000
+ #define SDR0_PFC0_PCIX1GNT2_N 0x00000000
+ #define SDR0_PFC0_GPIO_7 0x01000000
+ #define SDR0_PFC0_PCIX1GNT3_N 0x00000000
+ #define SDR0_PFC0_GPIO_8 0x00800000
+ #define SDR0_PFC0_PERREADY 0x00000000
+ #define SDR0_PFC0_GPIO_9 0x00400000
+ #define SDR0_PFC0_PERCS1_N 0x00000000
+ #define SDR0_PFC0_GPIO_10 0x00200000
+ #define SDR0_PFC0_PERCS2_N 0x00000000
+ #define SDR0_PFC0_GPIO_11 0x00100000
+ #define SDR0_PFC0_IRQ0 0x00000000
+ #define SDR0_PFC0_GPIO_12 0x00080000
+ #define SDR0_PFC0_IRQ1 0x00000000
+ #define SDR0_PFC0_GPIO_13 0x00040000
+ #define SDR0_PFC0_IRQ2 0x00000000
+ #define SDR0_PFC0_GPIO_14 0x00020000
+ #define SDR0_PFC0_IRQ3 0x00000000
+ #define SDR0_PFC0_GPIO_15 0x00010000
+ #define SDR0_PFC0_IRQ4 0x00000000
+ #define SDR0_PFC0_GPIO_16 0x00008000
+ #define SDR0_PFC0_IRQ5 0x00000000
+ #define SDR0_PFC0_GPIO_17 0x00004000
+ #define SDR0_PFC0_PERBE0_N 0x00000000
+ #define SDR0_PFC0_GPIO_18 0x00002000
+ #define SDR0_PFC0_PCI0GNT0_N 0x00000000
+ #define SDR0_PFC0_GPIO_19 0x00001000
+ #define SDR0_PFC0_PCI0GNT1_N 0x00000000
+ #define SDR0_PFC0_GPIO_20 0x00000800
+ #define SDR0_PFC0_PCI0REQ0_N 0x00000000
+ #define SDR0_PFC0_GPIO_21 0x00000400
+ #define SDR0_PFC0_PCI0REQ1_N 0x00000000
+ #define SDR0_PFC0_GPIO_22 0x00000200
+ #define SDR0_PFC0_PCI1GNT0_N 0x00000000
+ #define SDR0_PFC0_GPIO_23 0x00000100
+ #define SDR0_PFC0_PCI1GNT1_N 0x00000000
+ #define SDR0_PFC0_GPIO_24 0x00000080
+ #define SDR0_PFC0_PCI1REQ0_N 0x00000000
+ #define SDR0_PFC0_GPIO_25 0x00000040
+ #define SDR0_PFC0_PCI1REQ1_N 0x00000000
+ #define SDR0_PFC0_GPIO_26 0x00000020
+ #define SDR0_PFC0_PCI2GNT0_N 0x00000000
+ #define SDR0_PFC0_GPIO_27 0x00000010
+ #define SDR0_PFC0_PCI2GNT1_N 0x00000000
+ #define SDR0_PFC0_GPIO_28 0x00000008
+ #define SDR0_PFC0_PCI2REQ0_N 0x00000000
+ #define SDR0_PFC0_GPIO_29 0x00000004
+ #define SDR0_PFC0_PCI2REQ1_N 0x00000000
+ #define SDR0_PFC0_GPIO_30 0x00000002
+ #define SDR0_PFC0_UART1RX 0x00000000
+ #define SDR0_PFC0_GPIO_31 0x00000001
+ #define SDR0_PFC0_UART1TX 0x00000000
+
+ #define SDR0_PFC1 0x4101
+ #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
+ #define SDR0_PFC1_UART1_DSR_DTR 0x00000000
+ #define SDR0_PFC1_UART1_CTS_RTS 0x02000000
+ #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
+ #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
+ #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
+ #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
+ #define SDR0_PFC1_ETH_10_100 0x00000000
+ #define SDR0_PFC1_ETH_GIGA 0x00200000
+ #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
+ #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
+ #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
+ #define SDR0_PFC1_CPU_NO_TRACE 0x00000000
+ #define SDR0_PFC1_CPU_TRACE 0x00080000
+ #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
+ #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
+
+ #define SDR0_MFR 0x4300
+ #endif /* CONFIG_440SPE */
+
+
#define SDR0_SDCS_SDD (0x80000000 >> 31)
#if defined(CONFIG_440GP)
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
- #if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
+ #if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
+#define GPIO0 0
+#define GPIO1 1
+
#if defined(CONFIG_440GP)
-#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
+#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
-#define GPIO0_OR (GPIO_BASE0+0x0)
-#define GPIO0_TCR (GPIO_BASE0+0x4)
-#define GPIO0_ODR (GPIO_BASE0+0x18)
-#define GPIO0_IR (GPIO_BASE0+0x1C)
+#define GPIO0_OR (GPIO0_BASE+0x0)
+#define GPIO0_TCR (GPIO0_BASE+0x4)
+#define GPIO0_ODR (GPIO0_BASE+0x18)
+#define GPIO0_IR (GPIO0_BASE+0x1C)
#endif /* CONFIG_440GP */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
-#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
-
-#define GPIO0_OR (GPIO_BASE0+0x0)
-#define GPIO0_TCR (GPIO_BASE0+0x4)
-#define GPIO0_OSRL (GPIO_BASE0+0x8)
-#define GPIO0_OSRH (GPIO_BASE0+0xC)
-#define GPIO0_TSRL (GPIO_BASE0+0x10)
-#define GPIO0_TSRH (GPIO_BASE0+0x14)
-#define GPIO0_ODR (GPIO_BASE0+0x18)
-#define GPIO0_IR (GPIO_BASE0+0x1C)
-#define GPIO0_RR1 (GPIO_BASE0+0x20)
-#define GPIO0_RR2 (GPIO_BASE0+0x24)
-#define GPIO0_RR3 (GPIO_BASE0+0x28)
-#define GPIO0_ISR1L (GPIO_BASE0+0x30)
-#define GPIO0_ISR1H (GPIO_BASE0+0x34)
-#define GPIO0_ISR2L (GPIO_BASE0+0x38)
-#define GPIO0_ISR2H (GPIO_BASE0+0x3C)
-#define GPIO0_ISR3L (GPIO_BASE0+0x40)
-#define GPIO0_ISR3H (GPIO_BASE0+0x44)
-
-#define GPIO1_OR (GPIO_BASE1+0x0)
-#define GPIO1_TCR (GPIO_BASE1+0x4)
-#define GPIO1_OSRL (GPIO_BASE1+0x8)
-#define GPIO1_OSRH (GPIO_BASE1+0xC)
-#define GPIO1_TSRL (GPIO_BASE1+0x10)
-#define GPIO1_TSRH (GPIO_BASE1+0x14)
-#define GPIO1_ODR (GPIO_BASE1+0x18)
-#define GPIO1_IR (GPIO_BASE1+0x1C)
-#define GPIO1_RR1 (GPIO_BASE1+0x20)
-#define GPIO1_RR2 (GPIO_BASE1+0x24)
-#define GPIO1_RR3 (GPIO_BASE1+0x28)
-#define GPIO1_ISR1L (GPIO_BASE1+0x30)
-#define GPIO1_ISR1H (GPIO_BASE1+0x34)
-#define GPIO1_ISR2L (GPIO_BASE1+0x38)
-#define GPIO1_ISR2H (GPIO_BASE1+0x3C)
-#define GPIO1_ISR3L (GPIO_BASE1+0x40)
-#define GPIO1_ISR3H (GPIO_BASE1+0x44)
+#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
+#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
+
+/* Offsets */
+#define GPIOx_OR 0x00 /* GPIO Output Register */
+#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
+#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
+#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
+#define GPIOx_IR 0x1C /* GPIO Input Register */
+#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
+#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
+#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
+#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
+
+#define GPIO0_OR (GPIO0_BASE+0x0)
+#define GPIO0_TCR (GPIO0_BASE+0x4)
+#define GPIO0_OSRL (GPIO0_BASE+0x8)
+#define GPIO0_OSRH (GPIO0_BASE+0xC)
+#define GPIO0_TSRL (GPIO0_BASE+0x10)
+#define GPIO0_TSRH (GPIO0_BASE+0x14)
+#define GPIO0_ODR (GPIO0_BASE+0x18)
+#define GPIO0_IR (GPIO0_BASE+0x1C)
+#define GPIO0_RR1 (GPIO0_BASE+0x20)
+#define GPIO0_RR2 (GPIO0_BASE+0x24)
+#define GPIO0_RR3 (GPIO0_BASE+0x28)
+#define GPIO0_ISR1L (GPIO0_BASE+0x30)
+#define GPIO0_ISR1H (GPIO0_BASE+0x34)
+#define GPIO0_ISR2L (GPIO0_BASE+0x38)
+#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
+#define GPIO0_ISR3L (GPIO0_BASE+0x40)
+#define GPIO0_ISR3H (GPIO0_BASE+0x44)
+
+#define GPIO1_OR (GPIO1_BASE+0x0)
+#define GPIO1_TCR (GPIO1_BASE+0x4)
+#define GPIO1_OSRL (GPIO1_BASE+0x8)
+#define GPIO1_OSRH (GPIO1_BASE+0xC)
+#define GPIO1_TSRL (GPIO1_BASE+0x10)
+#define GPIO1_TSRH (GPIO1_BASE+0x14)
+#define GPIO1_ODR (GPIO1_BASE+0x18)
+#define GPIO1_IR (GPIO1_BASE+0x1C)
+#define GPIO1_RR1 (GPIO1_BASE+0x20)
+#define GPIO1_RR2 (GPIO1_BASE+0x24)
+#define GPIO1_RR3 (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
+#define GPIO_GROUP_MAX 2
+#define GPIO_MAX 32
+#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
+#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+ /* For the other GPIO number, you must shift */
+
+#ifndef __ASSEMBLY__
+
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long add; /* gpio core base address */
+ gpio_driver_t in_out; /* Driver Setting */
+ gpio_select_t alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+
+#endif /* __ASSEMBLY__ */
+
/*
* Macros for accessing the indirect EBC registers
*/
unsigned long freqOPB;
unsigned long freqEPB;
unsigned long freqPCI;
+ #ifdef CONFIG_440SPE
+ unsigned long freqDDR;
+ #endif
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
#endif
#include <environment.h>
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CFG_ENV_IS_EMBEDDED)
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+ gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
+
+ #ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+ #endif
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
board_early_init_r ();
#endif
- gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
-
monitor_flash_len = (ulong)&__init_end - dest_addr;
- #ifdef CONFIG_SERIAL_MULTI
- serial_initialize();
- #endif
-
/*
* We have to relocate the command table manually
*/
WATCHDOG_RESET();
-#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)
+#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
+ defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
icache_enable (); /* it's time to enable the instruction cache */
#endif
projects / platform / kernel / u-boot.git / commitdiff