Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).

[platform/kernel/u-boot.git] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index c1e787f..f37c1d6 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -383,23 +383,6 @@ _start:
        mtspr   tcr,r0                  /* disable all */
        mtspr   esr,r0                  /* clear exception syndrome register */
        mtxer   r0                      /* clear integer exception register */
-#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
-       lis     r1,0x0002               /* set CE bit (Critical Exceptions) */
-       ori     r1,r1,0x1000            /* set ME bit (Machine Exceptions) */
-       mtmsr   r1                      /* change MSR */
-#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
-       bl      __440gx_msr_set
-       b       __440gx_msr_continue
-
-__440gx_msr_set:
-       lis     r1, 0x0002              /* set CE bit (Critical Exceptions) */
-       ori     r1,r1,0x1000    /* set ME bit (Machine Exceptions) */
-       mtspr   srr1,r1
-       mflr    r1
-       mtspr   srr0,r1
-       rfi
-__440gx_msr_continue:
-#endif
 
        /*----------------------------------------------------------------*/
        /* Debug setup -- some (not very good) ice's need an event*/
@@ -514,9 +497,6 @@ __440gx_msr_continue:
        mtspr   esr,r0                  /* clear Exception Syndrome Reg */
        mttcr   r0                      /* timer control register */
        mtexier r0                      /* disable all interrupts */
-       addi    r4,r0,0x1000            /* set ME bit (Machine Exceptions) */
-       oris    r4,r4,0x2               /* set CE bit (Critical Exceptions) */
-       mtmsr   r4                      /* change MSR */
        addis   r4,r0,0xFFFF            /* set r4 to 0xFFFFFFFF (status in the */
        ori     r4,r4,0xFFFF            /* dbsr is cleared by setting bits to 1) */
        mtdbsr  r4                      /* clear/reset the dbsr */
@@ -627,9 +607,6 @@ __440gx_msr_continue:
        mttcr   r4                      /* clear Timer Control Reg */
        mtxer   r4                      /* clear Fixed-Point Exception Reg */
        mtevpr  r4                      /* clear Exception Vector Prefix Reg */
-       addi    r4,r0,0x1000            /* set ME bit (Machine Exceptions) */
-       oris    r4,r4,0x0002            /* set CE bit (Critical Exceptions) */
-       mtmsr   r4                      /* change MSR */
        addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
                                        /* dbsr is cleared by setting bits to 1) */
        mtdbsr  r4                      /* clear/reset the dbsr */
@@ -1277,12 +1254,19 @@ ppcSync:
        .globl  relocate_code
 relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
-       dccci   0,0                         /* Invalidate data cache, now no longer our stack */
+       /*
+        * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
+        * to speed up the boot process. Now this cache needs to be disabled.
+        */
+       iccci   0,0                     /* Invalidate inst cache */
+       dccci   0,0                     /* Invalidate data cache, now no longer our stack */
        sync
+       isync
        addi    r1,r0,0x0000            /* TLB entry #0 */
        tlbre   r0,r1,0x0002            /* Read contents */
        ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
        tlbwe   r0,r1,0x0002            /* Save it out */
+       sync
        isync
 #endif
        mr      r1,  r3         /* Set new stack pointer                */
@@ -1484,6 +1468,24 @@ trap_init:
        cmplw   0, r7, r8
        blt     4b
 
+#if !defined(CONFIG_440_GX) && !defined(CONFIG_440SPE)
+       addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
+       oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
+       mtmsr   r7                      /* change MSR */
+#else
+       bl      __440gx_msr_set
+       b       __440gx_msr_continue
+
+__440gx_msr_set:
+       addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
+       oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
+       mtspr   srr1,r7
+       mflr    r7
+       mtspr   srr0,r7
+       rfi
+__440gx_msr_continue:
+#endif
+
        mtlr    r4                      /* restore link register        */
        blr