F: arch/arm/mach-apple/
F: configs/apple_m1_defconfig
F: drivers/iommu/apple_dart.c
+F: drivers/pinctrl/pinctrl-apple.c
F: include/configs/apple.h
ARM
CLOCK
M: Lukasz Majewski <lukma@denx.de>
+M: Sean Anderson <seanga2@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-clk.git
F: drivers/clk/
F: tools/env*
F: tools/mkenvimage.c
+ENVIRONMENT AS TEXT
+M: Simon Glass <sjg@chromium.org>
+R: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: doc/usage/environment.rst
+F: scripts/env2string.awk
+
+FASTBOOT
+S: Orphaned
+F: cmd/fastboot.c
+F: doc/android/fastboot*.rst
+F: include/fastboot.h
+F: include/fastboot-internal.h
+F: include/net/fastboot.h
+F: drivers/fastboot/
+F: drivers/usb/gadget/f_fastboot.c
+F: net/fastboot.c
+F: test/dm/fastboot.c
+
FPGA
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
VERSION = 2022
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
timestamp_h := include/generated/timestamp_autogenerated.h
defaultenv_h := include/generated/defaultenv_autogenerated.h
dt_h := include/generated/dt.h
+env_h := include/generated/environment.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
+ $(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD))
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
@# options are whitelisted, so new ones should not be added.
echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
echo " but u-boot-nodtb.bin shows $$file_size" >&2 ; \
exit 1; \
- fi \
+ fi; \
fi
ifeq ($(CONFIG_INIT_SP_RELATIVE)$(CONFIG_OF_SEPARATE),yy)
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
+ $(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
--toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . -m --allow-missing \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
+ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
u-boot.sym: u-boot FORCE
$(call if_changed,sym)
+# Environment processing
+# ---------------------------------------------------------------------------
+
+# Directory where we expect the .env file, if it exists
+ENV_DIR := $(srctree)/board/$(BOARDDIR)
+
+# Basename of .env file, stripping quotes
+ENV_SOURCE_FILE := $(CONFIG_ENV_SOURCE_FILE:"%"=%)
+
+# Filename of .env file
+ENV_FILE_CFG := $(ENV_DIR)/$(ENV_SOURCE_FILE).env
+
+# Default filename, if CONFIG_ENV_SOURCE_FILE is empty
+ENV_FILE_BOARD := $(ENV_DIR)/$(CONFIG_SYS_BOARD:"%"=%).env
+
+# Select between the CONFIG_ENV_SOURCE_FILE and the default one
+ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD)))
+
+# Run the environment text file through the preprocessor, but only if it is
+# non-empty, to save time and possible build errors if something is wonky with
+# the board
+quiet_cmd_gen_envp = ENVP $@
+ cmd_gen_envp = \
+ if [ -s "$(ENV_FILE)" ]; then \
+ $(CPP) -P $(CFLAGS) -x assembler-with-cpp -D__ASSEMBLY__ \
+ -D__UBOOT_CONFIG__ \
+ -I . -I include -I $(srctree)/include \
+ -include linux/kconfig.h -include include/config.h \
+ -I$(srctree)/arch/$(ARCH)/include \
+ $< -o $@; \
+ else \
+ echo -n >$@ ; \
+ fi
+include/generated/env.in: include/generated/env.txt FORCE
+ $(call cmd,gen_envp)
+
+# Regenerate the environment if it changes
+# We use 'wildcard' since the file is not required to exist (at present), in
+# which case we don't want this dependency, but instead should create an empty
+# file
+# This rule is useful since it shows the source file for the environment
+quiet_cmd_envc = ENVC $@
+ cmd_envc = \
+ if [ -f "$<" ]; then \
+ cat $< > $@; \
+ elif [ -n "$(ENV_SOURCE_FILE)" ]; then \
+ echo "Missing file $(ENV_FILE_CFG)"; \
+ else \
+ echo -n >$@ ; \
+ fi
+
+include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
+ $(call cmd,envc)
+
+# Write out the resulting environment, converted to a C string
+quiet_cmd_gen_envt = ENVT $@
+ cmd_gen_envt = \
+ awk -f $(srctree)/scripts/env2string.awk $< >$@
+$(env_h): include/generated/env.in
+ $(call cmd,gen_envt)
+
+# ---------------------------------------------------------------------------
+
# The actual objects are generated when descending,
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
# prepare2 creates a makefile if using a separate output directory
prepare2: prepare3 outputmakefile cfg
-prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) \
+prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) $(env_h) \
include/config/auto.conf
ifeq ($(wildcard $(LDSCRIPT)),)
@echo >&2 " Could not find linker script."
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Autoboot Command:
- CONFIG_BOOTCOMMAND
- Only needed when CONFIG_BOOTDELAY is enabled;
- define a command string that is automatically executed
- when no character is read on the console interface
- within "Boot Delay" after reset.
-
- CONFIG_RAMBOOT and CONFIG_NFSBOOT
- The value of these goes into the environment as
- "ramboot" and "nfsboot" respectively, and can be used
- as a convenience, when switching between booting from
- RAM and NFS.
-
- Serial Download Echo Mode:
CONFIG_LOADS_ECHO
If defined to 1, all characters received during a
least one non-MTD partition type as well.
- IDE Reset method:
- CONFIG_IDE_RESET_ROUTINE - this is defined in several
- board configurations files but used nowhere!
-
CONFIG_IDE_RESET - is this is defined, IDE Reset will
be performed by calling the function
ide_set_reset(int reset)
- Keyboard Support:
See Kconfig help for available keyboard drivers.
- CONFIG_KEYBOARD
-
- Define this to enable a custom keyboard support.
- This simply calls drv_keyboard_init() which must be
- defined in your board-specific files. This option is deprecated
- and is only used by novena. For new boards, use driver model
- instead.
-
- Video support:
CONFIG_FSL_DIU_FB
Enable the Freescale DIU video driver. Reference boards for
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
-- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
- CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
- CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
- CONFIG_SYS_BR1_PRELIM:
- Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
-
-- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
- CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
- CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
- Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
-
- CONFIG_SYS_SRIO:
Chip has SRIO or not
For now: just type "help <command>".
-Environment Variables:
-======================
-
-U-Boot supports user configuration using Environment Variables which
-can be made persistent by saving to Flash memory.
-
-Environment Variables are set using "setenv", printed using
-"printenv", and saved to Flash using "saveenv". Using "setenv"
-without a value can be used to delete a variable from the
-environment. As long as you don't save the environment you are
-working with an in-memory copy. In case the Flash area containing the
-environment is erased by accident, a default environment is provided.
-
-Some configuration options can be set using Environment Variables.
-
-List of environment variables (most likely not complete):
-
- baudrate - see CONFIG_BAUDRATE
-
- bootdelay - see CONFIG_BOOTDELAY
-
- bootcmd - see CONFIG_BOOTCOMMAND
-
- bootargs - Boot arguments when booting an RTOS image
-
- bootfile - Name of the image to load with TFTP
-
- bootm_low - Memory range available for image processing in the bootm
- command can be restricted. This variable is given as
- a hexadecimal number and defines lowest address allowed
- for use by the bootm command. See also "bootm_size"
- environment variable. Address defined by "bootm_low" is
- also the base of the initial memory mapping for the Linux
- kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
- bootm_mapsize.
-
- bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
- This variable is given as a hexadecimal number and it
- defines the size of the memory region starting at base
- address bootm_low that is accessible by the Linux kernel
- during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used
- as the default value if it is defined, and bootm_size is
- used otherwise.
-
- bootm_size - Memory range available for image processing in the bootm
- command can be restricted. This variable is given as
- a hexadecimal number and defines the size of the region
- allowed for use by the bootm command. See also "bootm_low"
- environment variable.
-
- bootstopkeysha256, bootdelaykey, bootstopkey - See README.autoboot
-
- updatefile - Location of the software update file on a TFTP server, used
- by the automatic software update feature. Please refer to
- documentation in doc/README.update for more details.
-
- autoload - if set to "no" (any string beginning with 'n'),
- "bootp" will just load perform a lookup of the
- configuration from the BOOTP server, but not try to
- load any image using TFTP
-
- autostart - if set to "yes", an image loaded using the "bootp",
- "rarpboot", "tftpboot" or "diskboot" commands will
- be automatically started (by internally calling
- "bootm")
-
- If set to "no", a standalone image passed to the
- "bootm" command will be copied to the load address
- (and eventually uncompressed), but NOT be started.
- This can be used to load and uncompress arbitrary
- data.
-
- fdt_high - if set this restricts the maximum address that the
- flattened device tree will be copied into upon boot.
- For example, if you have a system with 1 GB memory
- at physical address 0x10000000, while Linux kernel
- only recognizes the first 704 MB as low memory, you
- may need to set fdt_high as 0x3C000000 to have the
- device tree blob be copied to the maximum address
- of the 704 MB low memory, so that Linux kernel can
- access it during the boot procedure.
-
- If this is set to the special value 0xFFFFFFFF then
- the fdt will not be copied at all on boot. For this
- to work it must reside in writable memory, have
- sufficient padding on the end of it for u-boot to
- add the information it needs into it, and the memory
- must be accessible by the kernel.
-
- fdtcontroladdr- if set this is the address of the control flattened
- device tree used by U-Boot when CONFIG_OF_CONTROL is
- defined.
-
- i2cfast - (PPC405GP|PPC405EP only)
- if set to 'y' configures Linux I2C driver for fast
- mode (400kHZ). This environment variable is used in
- initialization code. So, for changes to be effective
- it must be saved and board must be reset.
-
- initrd_high - restrict positioning of initrd images:
- If this variable is not set, initrd images will be
- copied to the highest possible address in RAM; this
- is usually what you want since it allows for
- maximum initrd size. If for some reason you want to
- make sure that the initrd image is loaded below the
- CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
- variable to a value of "no" or "off" or "0".
- Alternatively, you can set it to a maximum upper
- address to use (U-Boot will still check that it
- does not overwrite the U-Boot stack and data).
-
- For instance, when you have a system with 16 MB
- RAM, and want to reserve 4 MB from use by Linux,
- you can do this by adding "mem=12M" to the value of
- the "bootargs" variable. However, now you must make
- sure that the initrd image is placed in the first
- 12 MB as well - this can be done with
-
- setenv initrd_high 00c00000
-
- If you set initrd_high to 0xFFFFFFFF, this is an
- indication to U-Boot that all addresses are legal
- for the Linux kernel, including addresses in flash
- memory. In this case U-Boot will NOT COPY the
- ramdisk at all. This may be useful to reduce the
- boot time on your system, but requires that this
- feature is supported by your Linux kernel.
-
- ipaddr - IP address; needed for tftpboot command
-
- loadaddr - Default load address for commands like "bootp",
- "rarpboot", "tftpboot", "loadb" or "diskboot"
-
- loads_echo - see CONFIG_LOADS_ECHO
-
- serverip - TFTP server IP address; needed for tftpboot command
-
- bootretry - see CONFIG_BOOT_RETRY_TIME
-
- bootdelaykey - see CONFIG_AUTOBOOT_DELAY_STR
-
- bootstopkey - see CONFIG_AUTOBOOT_STOP_STR
-
- ethprime - controls which interface is used first.
-
- ethact - controls which interface is currently active.
- For example you can do the following
-
- => setenv ethact FEC
- => ping 192.168.0.1 # traffic sent on FEC
- => setenv ethact SCC
- => ping 10.0.0.1 # traffic sent on SCC
-
- ethrotate - When set to "no" U-Boot does not go through all
- available network interfaces.
- It just stays at the currently selected interface.
-
- netretry - When set to "no" each network operation will
- either succeed or fail without retrying.
- When set to "once" the network operation will
- fail when all the available network interfaces
- are tried once without success.
- Useful on scripts which control the retry operation
- themselves.
-
- npe_ucode - set load address for the NPE microcode
-
- silent_linux - If set then Linux will be told to boot silently, by
- changing the console to be empty. If "yes" it will be
- made silent. If "no" it will not be made silent. If
- unset, then it will be made silent if the U-Boot console
- is silent.
-
- tftpsrcp - If this is set, the value is used for TFTP's
- UDP source port.
-
- tftpdstp - If this is set, the value is used for TFTP's UDP
- destination port instead of the Well Know Port 69.
-
- tftpblocksize - Block size to use for TFTP transfers; if not set,
- we use the TFTP server's default block size
-
- tftptimeout - Retransmission timeout for TFTP packets (in milli-
- seconds, minimum value is 1000 = 1 second). Defines
- when a packet is considered to be lost so it has to
- be retransmitted. The default is 5000 = 5 seconds.
- Lowering this value may make downloads succeed
- faster in networks with high packet loss rates or
- with unreliable TFTP servers.
-
- tftptimeoutcountmax - maximum count of TFTP timeouts (no
- unit, minimum value = 0). Defines how many timeouts
- can happen during a single file transfer before that
- transfer is aborted. The default is 10, and 0 means
- 'no timeouts allowed'. Increasing this value may help
- downloads succeed with high packet loss rates, or with
- unreliable TFTP servers or client hardware.
-
- tftpwindowsize - if this is set, the value is used for TFTP's
- window size as described by RFC 7440.
- This means the count of blocks we can receive before
- sending ack to server.
-
- vlan - When set to a value < 4095 the traffic over
- Ethernet is encapsulated/received over 802.1q
- VLAN tagged frames.
-
- bootpretryperiod - Period during which BOOTP/DHCP sends retries.
- Unsigned value, in milliseconds. If not set, the period will
- be either the default (28000), or a value based on
- CONFIG_NET_RETRY_COUNT, if defined. This value has
- precedence over the valu based on CONFIG_NET_RETRY_COUNT.
-
- memmatches - Number of matches found by the last 'ms' command, in hex
-
- memaddr - Address of the last match found by the 'ms' command, in hex,
- or 0 if none
-
- mempos - Index position of the last match found by the 'ms' command,
- in units of the size (.b, .w, .l) of the search
-
- zbootbase - (x86 only) Base address of the bzImage 'setup' block
-
- zbootaddr - (x86 only) Address of the loaded bzImage, typically
- BZIMAGE_LOAD_ADDR which is 0x100000
-
-The following image location variables contain the location of images
-used in booting. The "Image" column gives the role of the image and is
-not an environment variable name. The other columns are environment
-variable names. "File Name" gives the name of the file on a TFTP
-server, "RAM Address" gives the location in RAM the image will be
-loaded to, and "Flash Location" gives the image's address in NOR
-flash or offset in NAND flash.
-
-*Note* - these variables don't have to be defined for all boards, some
-boards currently use other variables for these purposes, and some
-boards use these variables for other purposes.
-
-Image File Name RAM Address Flash Location
------ --------- ----------- --------------
-u-boot u-boot u-boot_addr_r u-boot_addr
-Linux kernel bootfile kernel_addr_r kernel_addr
-device tree blob fdtfile fdt_addr_r fdt_addr
-ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr
-
-The following environment variables may be used and automatically
-updated by the network boot commands ("bootp" and "rarpboot"),
-depending the information provided by your boot server:
-
- bootfile - see above
- dnsip - IP address of your Domain Name Server
- dnsip2 - IP address of your secondary Domain Name Server
- gatewayip - IP address of the Gateway (Router) to use
- hostname - Target hostname
- ipaddr - see above
- netmask - Subnet Mask
- rootpath - Pathname of the root filesystem on the NFS server
- serverip - see above
-
-
-There are two special Environment Variables:
-
- serial# - contains hardware identification information such
- as type string and/or serial number
- ethaddr - Ethernet address
-
-These variables can be set only once (usually during manufacturing of
-the board). U-Boot refuses to delete or overwrite these variables
-once they have been set once.
-
-
-Further special Environment Variables:
-
- ver - Contains the U-Boot version string as printed
- with the "version" command. This variable is
- readonly (see CONFIG_VERSION_VARIABLE).
-
-
-Please note that changes to some configuration parameters may take
-only effect after the next boot (yes, that's just like Windoze :-).
-
-
-Callback functions for environment variables:
----------------------------------------------
-
-For some environment variables, the behavior of u-boot needs to change
-when their values are changed. This functionality allows functions to
-be associated with arbitrary variables. On creation, overwrite, or
-deletion, the callback will provide the opportunity for some side
-effect to happen or for the change to be rejected.
-
-The callbacks are named and associated with a function using the
-U_BOOT_ENV_CALLBACK macro in your board or driver code.
-
-These callbacks are associated with variables in one of two ways. The
-static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
-in the board configuration to a string that defines a list of
-associations. The list must be in the following format:
-
- entry = variable_name[:callback_name]
- list = entry[,list]
-
-If the callback name is not specified, then the callback is deleted.
-Spaces are also allowed anywhere in the list.
-
-Callbacks can also be associated by defining the ".callbacks" variable
-with the same list format above. Any association in ".callbacks" will
-override any association in the static list. You can define
-CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
-".callbacks" environment variable in the default or embedded environment.
-
-If CONFIG_REGEX is defined, the variable_name above is evaluated as a
-regular expression. This allows multiple variables to be connected to
-the same callback without explicitly listing them all out.
-
-The signature of the callback functions is:
-
- int callback(const char *name, const char *value, enum env_op op, int flags)
-
-* name - changed environment variable
-* value - new value of the environment variable
-* op - operation (create, overwrite, or delete)
-* flags - attributes of the environment variable change, see flags H_* in
- include/search.h
-
-The return value is 0 if the variable change is accepted and 1 otherwise.
-
-
Note for Redundant Ethernet Interfaces:
=======================================
imply PHY_FIXED
imply DM_DSA
imply CMD_EXTENSION
+ imply KEYBOARD
config SH
bool "SuperH architecture"
select CLK
select CMD_USB
select DM
+ select DM_GPIO
select DM_KEYBOARD
select DM_SERIAL
select DM_USB
select LINUX_KERNEL_IMAGE_HEADER
select OF_CONTROL
select OF_BOARD
+ select PINCTRL
select POSITION_INDEPENDENT
select USB
imply CMD_DM
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
+ select FSL_DDR_BIST
+ select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
+ select FSL_DDR_BIST
+ select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-a2197-revA.dtb \
+ zynqmp-dlc21-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
zynqmp-g-a2197-00-revA.dtb \
zynqmp-m-a2197-01-revA.dtb \
0x08 0x04
0x08 0x04>;
};
+
+&hace {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&acry {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
};
};
+ hace: hace@1e6d0000 {
+ compatible = "aspeed,ast2600-hace";
+ reg = <0x1e6d0000 0x200>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_GATE_YCLK>;
+ status = "disabled";
+ };
+
+ acry: acry@1e6fa000 {
+ compatible = "aspeed,ast2600-acry";
+ reg = <0x1e6fa000 0x1000>,
+ <0x1e710000 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
+ status = "disabled";
+ };
+
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
/dts-v1/;
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
#include "k3-am642.dtsi"
#include "k3-am64-sk-lp4-1333MTs.dtsi"
#include "k3-am64-ddr.dtsi"
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
>;
};
+
+ main_usb0_pins_default: main-usb0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
};
&dmsc {
pinctrl-0 = <&main_mmc1_pins_default>;
};
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&serdes0 {
+ serdes0_usb_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
#include "k3-am642-sk-u-boot.dtsi"
&cpsw_port2 {
status = "disabled";
};
+
+&main_usb0_pins_default {
+ u-boot,dm-spl;
+};
+
+&serdes_ln_ctrl {
+ u-boot,mux-autoprobe;
+};
+
+&usbss0 {
+ u-boot,dm-spl;
+};
+
+&usb0 {
+ dr_mode = "host";
+ u-boot,dm-spl;
+};
+
+&serdes_wiz0 {
+ u-boot,dm-spl;
+};
+
+&serdes0_usb_link {
+ u-boot,dm-spl;
+};
+
+&serdes0 {
+ u-boot,dm-spl;
+};
+
+&serdes_refclk {
+ u-boot,dm-spl;
+};
enet1-sgmii-phy = &sgmii_phy1;
spi0 = &qspi;
spi1 = &dspi1;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &swp2;
+ ethernet4 = &swp3;
+ ethernet5 = &swp4;
+ ethernet6 = &swp5;
+ };
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ sja1105: ethernet-switch@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,sja1105t";
+ /* 12 MHz */
+ spi-max-frequency = <12000000>;
+ /* Sample data on trailing clock edge */
+ spi-cpha;
+ /* SPI controller settings for SJA1105 timing requirements */
+ fsl,spi-cs-sck-delay = <1000>;
+ fsl,spi-sck-cs-delay = <1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swp5: port@0 {
+ /* ETH5 written on chassis */
+ label = "swp5";
+ phy-handle = <&rgmii_phy6>;
+ phy-mode = "rgmii-id";
+ reg = <0>;
+ };
+
+ swp2: port@1 {
+ /* ETH2 written on chassis */
+ label = "swp2";
+ phy-handle = <&rgmii_phy3>;
+ phy-mode = "rgmii-id";
+ reg = <1>;
+ };
+
+ swp3: port@2 {
+ /* ETH3 written on chassis */
+ label = "swp3";
+ phy-handle = <&rgmii_phy4>;
+ phy-mode = "rgmii-id";
+ reg = <2>;
+ };
+
+ swp4: port@3 {
+ /* ETH4 written on chassis */
+ label = "swp4";
+ phy-handle = <&rgmii_phy5>;
+ phy-mode = "rgmii-id";
+ reg = <3>;
+ };
+
+ port@4 {
+ /* Internal port connected to eth2 */
+ ethernet = <&enet2>;
+ phy-mode = "rgmii";
+ reg = <4>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
};
};
status = "okay";
};
+/* RGMII delays added via PCB traces */
+&enet2 {
+ phy-mode = "rgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
&i2c0 {
status = "okay";
};
reg = <0x2>;
};
+ /* BCM5464 quad PHY */
+ rgmii_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ rgmii_phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ rgmii_phy5: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ rgmii_phy6: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
/* SGMII PCS for enet0 */
tbi0: tbi-phy@1f {
reg = <0x1f>;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
st,syscfg = <&syscfg>;
pinctrl-0 = <&fmc_pins_d32>;
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
qflash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
st,syscfg = <&syscfg>;
pinctrl-0 = <&fmc_pins_d32>;
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <91>;
spi-max-frequency = <108000000>;
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
flash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <92>;
spi-max-frequency = <108000000>;
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
qflash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
soc {
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
- reg = <0x40016C00 0x800>;
+ reg = <0x40016c00 0x800>;
resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
<&clk_hse>;
clock-names = "pclk", "px_clk", "ref";
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
flash0: mx66l51235l@0 {
#address-cells = <1>;
#size-cells = <1>;
DDR_MR3
>;
-#ifdef DDR_PHY_CAL_SKIP
- st,phy-cal = <
- DDR_DX0DLLCR
- DDR_DX0DQTR
- DDR_DX0DQSTR
- DDR_DX1DLLCR
- DDR_DX1DQTR
- DDR_DX1DQSTR
- DDR_DX2DLLCR
- DDR_DX2DQTR
- DDR_DX2DQSTR
- DDR_DX3DLLCR
- DDR_DX3DQTR
- DDR_DX3DQSTR
- >;
-
-#endif
-
status = "okay";
};
};
#undef DDR_ODTCR
#undef DDR_ZQ0CR1
#undef DDR_DX0GCR
-#undef DDR_DX0DLLCR
-#undef DDR_DX0DQTR
-#undef DDR_DX0DQSTR
#undef DDR_DX1GCR
-#undef DDR_DX1DLLCR
-#undef DDR_DX1DQTR
-#undef DDR_DX1DQSTR
#undef DDR_DX2GCR
-#undef DDR_DX2DLLCR
-#undef DDR_DX2DQTR
-#undef DDR_DX2DQSTR
#undef DDR_DX3GCR
-#undef DDR_DX3DLLCR
-#undef DDR_DX3DQTR
-#undef DDR_DX3DQSTR
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE80
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE80
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
compatible = "st,stm32mp1-ddr";
- reg = <0x5A003000 0x550
- 0x5A004000 0x234>;
+ reg = <0x5a003000 0x550
+ 0x5a004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
u-boot-stm32 {
filename = "u-boot.stm32";
mkimage {
- args = "-T stm32image -a 0xC0100000 -e 0xC0100000";
+ args = "-T stm32image -a 0xc0100000 -e 0xc0100000";
u-boot {
};
};
spl-stm32 {
filename = "u-boot-spl.stm32";
mkimage {
- args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500";
+ args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500";
u-boot-spl {
};
};
&sdmmc1 {
u-boot,dm-spl;
+ st,use-ckin;
+ st,cmd-gpios = <&gpiod 2 0>;
+ st,ck-gpios = <&gpioc 12 0>;
+ st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {
};
};
+
+ðernet0 {
+ mdio0 {
+ ethernet-phy@7 {
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <1000>;
+ };
+ };
+};
+
&sdmmc1 {
u-boot,dm-spl;
+ st,use-ckin;
+ st,cmd-gpios = <&gpiod 2 0>;
+ st,ck-gpios = <&gpioc 12 0>;
+ st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP DLC21 revA
+ *
+ * (C) Copyright 2019 - 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <include/dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Smartlynq+ DLC21 RevA";
+ compatible = "xlnx,zynqmp-dlc21-revA", "xlnx,zynqmp-dlc21",
+ "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ spi0 = &spi0;
+ nvmem0 = &eeprom;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>, <0x8 0 0x3 0x80000000>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+ "", "", "", "", "", /* 5 - 9 */
+ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "DISP_SCL", "DISP_DC_B", "DISP_RES_B", "DISP_CS_B", /* 25 - 29 */
+ "", "DISP_SDI", "SYSTEM_RST_R_B", "", "I2C0_SCL", /* 30 - 34 */
+ "I2C0_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+ "", "", "", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+ "SYSCTLR_UTIL_2V5_EN", "", "", "", "", /* 125 - 129 */
+ "", "", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "", /* 130 - 134 */
+ "", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+ "", "", "SYSCTLR_ETH_RESET_B", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO34/35 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ jtag_vref: mcp4725@62 {
+ compatible = "microchip,mcp4725";
+ reg = <0x62>;
+ vref-millivolt = <3300>;
+ };
+
+ eeprom: eeprom@50 { /* u46 */
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+ /* u138 - TUSB320IRWBR - for USB-C */
+};
+
+
+&usb0 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+};
+
+&usb1 {
+ status = "disabled"; /* Any unknown issue with USB-C */
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+ /delete-property/ phy-names ;
+ /delete-property/ phys ;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk ;
+ snps,dis_u3_susphy_quirk ;
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ is-decoded-cs = <0>;
+ num-cs = <1>;
+ u-boot,dm-pre-reloc;
+ displayspi@0 {
+ compatible = "syncoam,seps525";
+ u-boot,dm-pre-reloc;
+ reg = <0>;
+ status = "okay";
+ spi-max-frequency = <10000000>;
+ spi-cpol;
+ spi-cpha;
+ rotate = <0>;
+ fps = <50>;
+ buswidth = <8>;
+ txbuflen = <64000>;
+ reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>;
+ dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>;
+ debug = <0>;
+ };
+};
si5332_1: si5332_1 { /* clk0_sgmii - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <33333333>; /* FIXME */
+ clock-frequency = <125000000>;
};
si5332_2: si5332_2 { /* clk1_usb - u142 */
#define ASPEED_MAC_COUNT 4
#define ASPEED_DRAM_BASE 0x80000000
#define ASPEED_SRAM_BASE 0x10000000
-#define ASPEED_SRAM_SIZE 0x10000
+#define ASPEED_SRAM_SIZE 0x16000
#else
#err "Unrecognized Aspeed platform."
#endif
#define SCU_UNLOCK_KEY 0x1688a8a8
#define SCU_CLKGATE1_EMMC BIT(27)
+#define SCU_CLKGATE1_ACRY BIT(24)
#define SCU_CLKGATE1_MAC2 BIT(21)
#define SCU_CLKGATE1_MAC1 BIT(20)
-#define SCU_CLKGATE1_USB_HUB BIT(14)
-#define SCU_CLKGATE1_USB_HOST2 BIT(7)
+#define SCU_CLKGATE1_USB_HUB BIT(14)
+#define SCU_CLKGATE1_HACE BIT(13)
+#define SCU_CLKGATE1_USB_HOST2 BIT(7)
#define SCU_CLKGATE2_FSI BIT(30)
#define SCU_CLKGATE2_MAC4 BIT(21)
mov r9, r0
bl board_init_f_init_reserve
+#if defined(CONFIG_DEBUG_UART) && CONFIG_IS_ENABLED(SERIAL)
+ bl debug_uart_init
+#endif
+
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS)
CLEAR_BSS
#endif
mov x18, x0
bl board_init_f_init_reserve
+#if defined(CONFIG_DEBUG_UART) && CONFIG_IS_ENABLED(SERIAL)
+ bl debug_uart_init
+#endif
+
mov x0, #0
bl board_init_f
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
+ /* Skip relocation in case gd->gd_flags & GD_FLG_SKIP_RELOC */
+ ldr x0, [x18, #GD_FLAGS] /* x0 <- gd->flags */
+ tbnz x0, 11, relocation_return /* GD_FLG_SKIP_RELOC is bit 11 */
+
adr lr, relocation_return
#if CONFIG_POSITION_INDEPENDENT
/* Add in link-vs-runtime offset */
orr r9, r9, ip, lspush #\push
mov ip, ip, lspull #\pull
orr ip, ip, lr, lspush #\push
- str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
+ str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f
bge 12b
PLD( cmn r2, #96 )
PLD( bge 13b )
struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
{
- /*
- * When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff
- * to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL
- * has been located in SPI for XIP. In this case, the load buffer for
- * SPL image loading will be set to the remapped address of the next
- * BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR
- */
- return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ return (struct image_header *)(CONFIG_SYS_LOAD_ADDR);
}
#ifdef CONFIG_SPL_OS_BOOT
imply CMD_HASH
imply CRC32_VERIFY
imply HASH_VERIFY
+ imply KEYBOARD
imply USB_ETHER_ASIX
imply USB_ETHER_RTL8152
imply USB_ETHER_SMSC95XX
imply CMD_SPL
config TARGET_TQMA6
- bool "TQ Systems TQMa6 board"
+ bool "TQ-Systems TQMa6 board"
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select MXC_SPI
source "board/technexion/pico-imx6/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
-source "board/tqc/tqma6/Kconfig"
+source "board/tq/tqma6/Kconfig"
source "board/toradex/apalis_imx6/Kconfig"
source "board/toradex/colibri_imx6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
*/
#ifdef CONFIG_IDE
#define __io
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
#define GPIO0_BASE 0xff720000
#define PMUGRF_BASE 0xff320000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
-#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
- struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
-#endif
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
GRF_GPIO3B7_SEL_MASK,
GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
#else
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- rk_setreg(&grf->io_vsel, 1 << 0);
-
- /*
- * Let's enable these power rails here, we are already running the SPI
- * Flash based code.
- */
- spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
- spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
- spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
- spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
-#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+ if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB)) {
+ rk_setreg(&grf->io_vsel, 1 << 0);
+
+ /*
+ * Let's enable these power rails here, we are already running
+ * the SPI-Flash-based code.
+ */
+ spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2),
+ GPIO_PULL_NORMAL);
+
+ spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4),
+ GPIO_PULL_NORMAL);
+ }
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
default y if ZYNQ_QSPI
config SYS_BOARD
+ string "Board name"
default "zynqmp"
config SYS_VENDOR
Overwrite bootmode selected via boot mode pins to tell SPL what should
be the next boot device.
+config SPL_ZYNQMP_RESTORE_JTAG
+ bool "Restore JTAG"
+ depends on SPL
+ help
+ Booting SPL in secure mode causes the CSU to disable the JTAG interface
+ even if no eFuses were burnt. This option restores the interface if
+ possible.
+
config ZYNQ_SDHCI_MAX_FREQ
default 200000000
#define RESET_REASON_INTERNAL BIT(1)
#define RESET_REASON_EXTERNAL BIT(0)
+#define CRLAPB_DBG_LPD_CTRL_SETUP_CLK 0x01002002
+#define CRLAPB_RST_LPD_DBG_RESET 0
+
struct crlapb_regs {
u32 reserved0[36];
u32 cpu_r5_ctrl; /* 0x90 */
- u32 reserved1[37];
+ u32 reserved1[7];
+ u32 dbg_lpd_ctrl; /* 0xB0 */
+ u32 reserved2[29];
u32 timestamp_ref_ctrl; /* 0x128 */
- u32 reserved2[53];
+ u32 reserved3[53];
u32 boot_mode; /* 0x200 */
- u32 reserved3_0[7];
+ u32 reserved4_0[7];
u32 reset_reason; /* 0x220 */
- u32 reserved3_1[6];
+ u32 reserved4_1[6];
u32 rst_lpd_top; /* 0x23C */
- u32 reserved4[4];
+ u32 rst_lpd_dbg; /* 0x240 */
+ u32 reserved5[3];
u32 boot_pin_ctrl; /* 0x250 */
- u32 reserved5[21];
+ u32 reserved6[21];
};
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
#define ZYNQMP_SILICON_VER_MASK 0xF
#define ZYNQMP_SILICON_VER_SHIFT 0
+#define CSU_JTAG_SEC_GATE_DISABLE GENMASK(7, 0)
+#define CSU_JTAG_DAP_ENABLE_DEBUG GENMASK(7, 0)
+#define CSU_JTAG_CHAIN_WR_SETUP GENMASK(1, 0)
+#define CSU_PCAP_PROG_RELEASE_PL BIT(0)
+
struct csu_regs {
u32 reserved0[4];
u32 multi_boot;
- u32 reserved1[11];
+ u32 reserved1[7];
+ u32 jtag_chain_status_wr;
+ u32 jtag_chain_status;
+ u32 jtag_sec;
+ u32 jtag_dap_cfg;
u32 idcode;
u32 version;
+ u32 reserved2[3055];
+ u32 pcap_prog;
};
#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
-#ifdef CONFIG_ELBC_BR0_OR0
-#define CONFIG_SYS_BR0_PRELIM (\
- CONFIG_BR0_OR0_BASE |\
- CONFIG_BR0_PORTSIZE |\
- CONFIG_BR0_ERRORCHECKING |\
- CONFIG_BR0_WRITE_PROTECT_BIT |\
- CONFIG_BR0_MACHINE |\
- CONFIG_BR0_ATOMIC |\
- CONFIG_BR0_VALID_BIT \
-)
-#define CONFIG_SYS_OR0_PRELIM (\
- CONFIG_OR0_AM |\
- CONFIG_OR0_XAM |\
- CONFIG_OR0_BCTLD |\
- CONFIG_OR0_BI |\
- CONFIG_OR0_COLS |\
- CONFIG_OR0_ROWS |\
- CONFIG_OR0_PMSEL |\
- CONFIG_OR0_SCY |\
- CONFIG_OR0_PGS |\
- CONFIG_OR0_CSCT |\
- CONFIG_OR0_CST |\
- CONFIG_OR0_CHT |\
- CONFIG_OR0_RST |\
- CONFIG_OR0_CSNT |\
- CONFIG_OR0_ACS |\
- CONFIG_OR0_XACS |\
- CONFIG_OR0_SETA |\
- CONFIG_OR0_TRLX |\
- CONFIG_OR0_EHTR |\
- CONFIG_OR0_EAD \
-)
-#endif /* CONFIG_ELBC_BR0_OR0 */
-
-#ifdef CONFIG_ELBC_BR1_OR1
-#define CONFIG_SYS_BR1_PRELIM (\
- CONFIG_BR1_OR1_BASE |\
- CONFIG_BR1_PORTSIZE |\
- CONFIG_BR1_ERRORCHECKING |\
- CONFIG_BR1_WRITE_PROTECT_BIT |\
- CONFIG_BR1_MACHINE |\
- CONFIG_BR1_ATOMIC |\
- CONFIG_BR1_VALID_BIT \
-)
-#define CONFIG_SYS_OR1_PRELIM (\
- CONFIG_OR1_AM |\
- CONFIG_OR1_XAM |\
- CONFIG_OR1_BCTLD |\
- CONFIG_OR1_BI |\
- CONFIG_OR1_COLS |\
- CONFIG_OR1_ROWS |\
- CONFIG_OR1_PMSEL |\
- CONFIG_OR1_SCY |\
- CONFIG_OR1_PGS |\
- CONFIG_OR1_CSCT |\
- CONFIG_OR1_CST |\
- CONFIG_OR1_CHT |\
- CONFIG_OR1_RST |\
- CONFIG_OR1_CSNT |\
- CONFIG_OR1_ACS |\
- CONFIG_OR1_XACS |\
- CONFIG_OR1_SETA |\
- CONFIG_OR1_TRLX |\
- CONFIG_OR1_EHTR |\
- CONFIG_OR1_EAD \
-)
-#endif /* CONFIG_ELBC_BR1_OR1 */
-
-#ifdef CONFIG_ELBC_BR2_OR2
-#define CONFIG_SYS_BR2_PRELIM (\
- CONFIG_BR2_OR2_BASE |\
- CONFIG_BR2_PORTSIZE |\
- CONFIG_BR2_ERRORCHECKING |\
- CONFIG_BR2_WRITE_PROTECT_BIT |\
- CONFIG_BR2_MACHINE |\
- CONFIG_BR2_ATOMIC |\
- CONFIG_BR2_VALID_BIT \
-)
-#define CONFIG_SYS_OR2_PRELIM (\
- CONFIG_OR2_AM |\
- CONFIG_OR2_XAM |\
- CONFIG_OR2_BCTLD |\
- CONFIG_OR2_BI |\
- CONFIG_OR2_COLS |\
- CONFIG_OR2_ROWS |\
- CONFIG_OR2_PMSEL |\
- CONFIG_OR2_SCY |\
- CONFIG_OR2_PGS |\
- CONFIG_OR2_CSCT |\
- CONFIG_OR2_CST |\
- CONFIG_OR2_CHT |\
- CONFIG_OR2_RST |\
- CONFIG_OR2_CSNT |\
- CONFIG_OR2_ACS |\
- CONFIG_OR2_XACS |\
- CONFIG_OR2_SETA |\
- CONFIG_OR2_TRLX |\
- CONFIG_OR2_EHTR |\
- CONFIG_OR2_EAD \
-)
-#endif /* CONFIG_ELBC_BR2_OR2 */
-
-#ifdef CONFIG_ELBC_BR3_OR3
-#define CONFIG_SYS_BR3_PRELIM (\
- CONFIG_BR3_OR3_BASE |\
- CONFIG_BR3_PORTSIZE |\
- CONFIG_BR3_ERRORCHECKING |\
- CONFIG_BR3_WRITE_PROTECT_BIT |\
- CONFIG_BR3_MACHINE |\
- CONFIG_BR3_ATOMIC |\
- CONFIG_BR3_VALID_BIT \
-)
-#define CONFIG_SYS_OR3_PRELIM (\
- CONFIG_OR3_AM |\
- CONFIG_OR3_XAM |\
- CONFIG_OR3_BCTLD |\
- CONFIG_OR3_BI |\
- CONFIG_OR3_COLS |\
- CONFIG_OR3_ROWS |\
- CONFIG_OR3_PMSEL |\
- CONFIG_OR3_SCY |\
- CONFIG_OR3_PGS |\
- CONFIG_OR3_CSCT |\
- CONFIG_OR3_CST |\
- CONFIG_OR3_CHT |\
- CONFIG_OR3_RST |\
- CONFIG_OR3_CSNT |\
- CONFIG_OR3_ACS |\
- CONFIG_OR3_XACS |\
- CONFIG_OR3_SETA |\
- CONFIG_OR3_TRLX |\
- CONFIG_OR3_EHTR |\
- CONFIG_OR3_EAD \
-)
-#endif /* CONFIG_ELBC_BR3_OR3 */
-
-#ifdef CONFIG_ELBC_BR4_OR4
-#define CONFIG_SYS_BR4_PRELIM (\
- CONFIG_BR4_OR4_BASE |\
- CONFIG_BR4_PORTSIZE |\
- CONFIG_BR4_ERRORCHECKING |\
- CONFIG_BR4_WRITE_PROTECT_BIT |\
- CONFIG_BR4_MACHINE |\
- CONFIG_BR4_ATOMIC |\
- CONFIG_BR4_VALID_BIT \
-)
-#define CONFIG_SYS_OR4_PRELIM (\
- CONFIG_OR4_AM |\
- CONFIG_OR4_XAM |\
- CONFIG_OR4_BCTLD |\
- CONFIG_OR4_BI |\
- CONFIG_OR4_COLS |\
- CONFIG_OR4_ROWS |\
- CONFIG_OR4_PMSEL |\
- CONFIG_OR4_SCY |\
- CONFIG_OR4_PGS |\
- CONFIG_OR4_CSCT |\
- CONFIG_OR4_CST |\
- CONFIG_OR4_CHT |\
- CONFIG_OR4_RST |\
- CONFIG_OR4_CSNT |\
- CONFIG_OR4_ACS |\
- CONFIG_OR4_XACS |\
- CONFIG_OR4_SETA |\
- CONFIG_OR4_TRLX |\
- CONFIG_OR4_EHTR |\
- CONFIG_OR4_EAD \
-)
-#endif /* CONFIG_ELBC_BR4_OR4 */
-
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
help
Debug Event Register (37-47)
-comment "Memory mapping"
-
-config SYS_BR0_PRELIM
- hex "Preliminary value for BR0"
-
-config SYS_OR0_PRELIM
- hex "Preliminary value for OR0"
-
-config SYS_BR1_PRELIM_BOOL
- bool "Define Bank 1"
-
-config SYS_BR1_PRELIM
- hex "Preliminary value for BR1"
- depends on SYS_BR1_PRELIM_BOOL
-
-config SYS_OR1_PRELIM
- hex "Preliminary value for OR1"
- depends on SYS_BR1_PRELIM_BOOL
-
-config SYS_BR2_PRELIM_BOOL
- bool "Define Bank 2"
-
-config SYS_BR2_PRELIM
- hex "Preliminary value for BR2"
- depends on SYS_BR2_PRELIM_BOOL
-
-config SYS_OR2_PRELIM
- hex "Preliminary value for OR2"
- depends on SYS_BR2_PRELIM_BOOL
-
-config SYS_BR3_PRELIM_BOOL
- bool "Define Bank 3"
-
-config SYS_BR3_PRELIM
- hex "Preliminary value for BR3"
- depends on SYS_BR3_PRELIM_BOOL
-
-config SYS_OR3_PRELIM
- hex "Preliminary value for OR3"
- depends on SYS_BR3_PRELIM_BOOL
-
-config SYS_BR4_PRELIM_BOOL
- bool "Define Bank 4"
-
-config SYS_BR4_PRELIM
- hex "Preliminary value for BR4"
- depends on SYS_BR4_PRELIM_BOOL
-
-config SYS_OR4_PRELIM
- hex "Preliminary value for OR4"
- depends on SYS_BR4_PRELIM_BOOL
-
-config SYS_BR5_PRELIM_BOOL
- bool "Define Bank 5"
-
-config SYS_BR5_PRELIM
- hex "Preliminary value for BR5"
- depends on SYS_BR5_PRELIM_BOOL
-
-config SYS_OR5_PRELIM
- hex "Preliminary value for OR5"
- depends on SYS_BR5_PRELIM_BOOL
-
-config SYS_BR6_PRELIM_BOOL
- bool "Define Bank 6"
-
-config SYS_BR6_PRELIM
- hex "Preliminary value for BR6"
- depends on SYS_BR6_PRELIM_BOOL
-
-config SYS_OR6_PRELIM
- hex "Preliminary value for OR6"
- depends on SYS_BR6_PRELIM_BOOL
-
-config SYS_BR7_PRELIM_BOOL
- bool "Define Bank 7"
-
-config SYS_BR7_PRELIM
- hex "Preliminary value for BR7"
- depends on SYS_BR7_PRELIM_BOOL
-
-config SYS_OR7_PRELIM
- hex "Preliminary value for OR7"
- depends on SYS_BR7_PRELIM_BOOL
-
config SYS_IMMR
hex "Value for IMMR"
/* The FMAN driver uses the PHYLIB infrastructure */
-/* All PPC boards must swap IDE bytes */
-#define CONFIG_IDE_SWAP_IO
-
#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
/*
* TODO: Convert this to a clock driver exists that can give us the UART
default 32 if HOST_32BIT
default 64 if HOST_64BIT
+config SYS_FDT_LOAD_ADDR
+ hex "Address at which to load devicetree"
+ default 0x100
+ help
+ With sandbox the devicetree is loaded into the emulated RAM. This sets
+ the address that is used. There must be enough space at this address
+ to load the full devicetree without it overwriting anything else.
+
+ See `doc/arch/sandbox.rst` for more information.
+
endmenu
return 0;
}
+int os_unmap(void *buf, int size)
+{
+ if (munmap(buf, size)) {
+ printf("Can't unmap %p %x\n", buf, size);
+ return -EIO;
+ }
+
+ return 0;
+}
+
/* Restore tty state when we exit */
static struct termios orig_term;
static bool term_setup;
void os_putc(int ch)
{
- putchar(ch);
+ fputc(ch, stdout);
}
void os_puts(const char *str)
efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
- os_fd_restore();
- os_relaunch(os_argv);
+ if (reset_type == EFI_RESET_SHUTDOWN)
+ sandbox_exit();
+ else
+ sandbox_reset();
}
void sandbox_reset(void)
test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
test5-gpios = <&gpio_a 19>;
+ bool-value;
int-value = <1234>;
uint-value = <(-1234)>;
int64-value = /bits/ 64 <0x1111222233334444>;
if (bl33_info->version != BL33_INFO_VERSION)
printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
-
+#if CONFIG_IS_ENABLED(BNXT_ETH)
+ if (chimp_fastboot_optee() != 0)
+ printf("*** warning: secure chimp fastboot failed! ***\n");
+#endif
return 0;
}
ofnode node;
int i, ret;
+ brdcode = 0;
+ ddr3code = 0;
+ somcode = 0;
+
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
printf("%s: no /config node?\n", __func__);
return;
}
- brdcode = 0;
- ddr3code = 0;
- somcode = 0;
-
ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+ gpio_free_list_nodev(gpio, ret);
+
ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
+ gpio_free_list_nodev(gpio, ret);
+
ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+ gpio_free_list_nodev(gpio, ret);
+
printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
somcode, ddr3code, brdcode);
}
obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += qemu_mtdparts.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += qemu_dfu.o
-obj-$(CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT) += qemu_capsule.o
node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
if (node < 0)
- lcd_dt_simplefb_add_node(blob);
+ fdt_simplefb_add_node(blob);
#ifdef CONFIG_EFI_LOADER
/* Reserve the spin table */
--- /dev/null
+stdin=serial
+#ifdef CONFIG_SANDBOX_SDL
+stdin+=,cros-ec-keyb,usbkbd
+#endif
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+
+ethaddr=02:00:11:22:33:44
+eth2addr=02:00:11:22:33:48
+eth3addr=02:00:11:22:33:45
+eth4addr=02:00:11:22:33:48
+eth5addr=02:00:11:22:33:46
+eth6addr=02:00:11:22:33:47
+ipaddr=192.0.2.1
+
+/*
+ * These are used for distro boot which is not supported. But once bootmethod
+ * is provided these will be used again.
+ */
+bootm_size=0x10000000
+kernel_addr_r=0x1000000
+fdt_addr_r=0xc00000
+ramdisk_addr_r=0x2000000
+scriptaddr=0x1000
+pxefile_addr_r=0x2000
{
gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+ gd->env_addr = (ulong)&default_environment[0];
+
synquacer_setup_scbm_smmu();
return 0;
mtd = get_mtd_device_nm("nor0");
if (!IS_ERR_OR_NULL(mtd))
board_get_alt_info_mtd(mtd, buf);
+
+ mtd = get_mtd_device_nm("nor1");
+ if (!IS_ERR_OR_NULL(mtd))
+ board_get_alt_info_mtd(mtd, buf);
}
mtd = get_mtd_device_nm("nand0");
#include <dm.h>
#include <env.h>
#include <env_internal.h>
+#include <fdt_simplefb.h>
#include <fdt_support.h>
#include <g_dnl.h>
#include <generic-phy.h>
if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ if (CONFIG_IS_ENABLED(FDT_SIMPLEFB))
+ fdt_simplefb_enable_and_mem_rsv(blob);
+
return 0;
}
#endif
default "tqma6"
config SYS_VENDOR
- default "tqc"
+ default "tq"
config SYS_CONFIG_NAME
default "tqma6"
default 0x4fc00000 if TQMA6Q || TQMA6DL
config IMX_CONFIG
- default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
- default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL
- default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
+ default "board/tq/tqma6/tqma6q.cfg" if TQMA6Q
+ default "board/tq/tqma6/tqma6dl.cfg" if TQMA6DL
+ default "board/tq/tqma6/tqma6s.cfg" if TQMA6S
endif
-TQ SYSTEMS TQMA6 BOARD
+TQ-SYSTEMS TQMA6 BOARD
M: Markus Niebel <Markus.Niebel@tq-group.com>
S: Maintained
-F: board/tqc/tqma6/
+F: board/tq/tqma6/
F: include/configs/tqma6.h
F: configs/tqma6*_defconfig
-U-Boot for the TQ Systems TQMa6 modules
+U-Boot for the TQ-Systems TQMa6 modules
This file contains information for the port of
-U-Boot to the TQ Systems TQMa6 modules.
+U-Boot to the TQ-Systems TQMa6 modules.
1. Boot source
--------------
2. Building
------------
-To build U-Boot for the TQ Systems TQMa6 modules:
+To build U-Boot for the TQ-Systems TQMa6 modules:
make tqma6<x>_<baseboard>_<boot>_config
make
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
- * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Copyright (C) 2013, 2014 TQ-Systems (ported SabreSD to TQMa6x)
* Author: Markus Niebel <markus.niebel@tq-group.com>
*/
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013, 2014 TQ Systems
+ * Copyright (C) 2013, 2014 TQ-Systems
* Author: Markus Niebel <markus.niebel@tq-group.com>
*/
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
- * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Copyright (C) 2013, 2014 TQ-Systems (ported SabreSD to TQMa6x)
* Author: Markus Niebel <markus.niebel@tq-group.com>
*/
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
- * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Copyright (C) 2013, 2014 TQ-Systems (ported SabreSD to TQMa6x)
* Author: Markus Niebel <markus.niebel@tq-group.com>
*
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06013C00U);
+ psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+ psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010702U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010502U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010802U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01030A00U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x43041010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00818126U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300501U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000700U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D0BU);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1607010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x00000018U);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010101U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F010101U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F07U);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000700U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000201U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000001U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000101U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x024B2B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00370F08U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000501U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000700U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x810091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00030236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12344000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000879DBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000080U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180204, 0xFCFFE000U, 0x00000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02040U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x033FFFFFU);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FF9FFFU);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F76FFFU);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x02FBFFBFU);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FF4FF4U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+ psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ mask_delay(1);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+ mask_delay(5);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
+ psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+ psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+ psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+ int cur_r006_trefprd;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+ >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return 0;
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+
+ Xil_Out32(0xFD080200U, 0x110091C7U);
+
+ cur_r006_trefprd = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x810091C7U);
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0, n_code = 0, i_code = 0, r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int count = 0, i = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ xil_printf("#SERDES initialization timed out\n\r");
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if (p_code >= 0x26 && p_code <= 0x3C)
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if (n_code >= 0x26 && n_code <= 0x3C)
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if (i_code >= 0xC && i_code <= 0x12)
+ match_ical_code[i_code - 0xc] += 1;
+
+ if (r_code >= 0x6 && r_code <= 0xC)
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
return multiboot;
}
+#if defined(CONFIG_SPL_BUILD)
+static void restore_jtag(void)
+{
+ if (current_el() != 3)
+ return;
+
+ writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
+ writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
+ writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
+ writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
+ writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
+ writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
+}
+#endif
+
#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
zynqmp_pm_cfg_obj_size);
printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
+
+ /* the CSU disables the JTAG interface when secure boot is enabled */
+ if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
+ restore_jtag();
#else
if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
xilinx_read_eeprom();
lmb_init(&lmb);
lmb_add(&lmb, gd->ram_base, gd->ram_size);
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
- size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
+ size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
if (!reg)
const char *mode;
char *new_targets;
char *env_targets;
- int ret;
+ int ret, multiboot;
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
usb_ether_init();
if (ret)
return ret;
+ multiboot = multi_boot();
+ if (multiboot >= 0)
+ env_set_hex("multiboot", multiboot);
+
bootmode = zynqmp_get_bootmode();
puts("Bootmode: ");
break;
case SD1_LSHFT_MODE:
puts("LVL_SHFT_");
- /* fall through */
+ fallthrough;
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
memset(buf, 0, sizeof(buf));
multiboot = multi_boot();
+ if (multiboot < 0)
+ multiboot = 0;
+
+ multiboot = env_get_hex("multiboot", multiboot);
debug("Multiboot: %d\n", multiboot);
switch (zynqmp_get_bootmode()) {
if (!multiboot)
snprintf(buf, DFU_ALT_BUF_LEN,
"mmc %d:1=boot.bin fat %d 1;"
- "u-boot.itb fat %d 1",
- bootseq, bootseq, bootseq);
+ "%s fat %d 1",
+ bootseq, bootseq,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
else
snprintf(buf, DFU_ALT_BUF_LEN,
"mmc %d:1=boot%04d.bin fat %d 1;"
- "u-boot.itb fat %d 1",
- bootseq, multiboot, bootseq, bootseq);
+ "%s fat %d 1",
+ bootseq, multiboot, bootseq,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
snprintf(buf, DFU_ALT_BUF_LEN,
"sf 0:0=boot.bin raw %x 0x1500000;"
- "u-boot.itb raw 0x%x 0x500000",
- multiboot * SZ_32K, CONFIG_SYS_SPI_U_BOOT_OFFS);
+ "%s raw 0x%x 0x500000",
+ multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
+ CONFIG_SYS_SPI_U_BOOT_OFFS);
break;
default:
return;
static int do_bootm_standalone(int flag, int argc, char *const argv[],
bootm_headers_t *images)
{
- char *s;
int (*appl)(int, char *const[]);
- /* Don't start if "autostart" is set to "no" */
- s = env_get("autostart");
- if ((s != NULL) && !strcmp(s, "no")) {
+ if (!env_get_autostart()) {
env_set_hex("filesize", images->os.image_len);
return 0;
}
#include <env.h>
#include <fpga.h>
#include <image.h>
+#include <init.h>
#include <mapmem.h>
#include <rtc.h>
#include <watchdog.h>
* calculate_hash - calculate and return hash for provided input data
* @data: pointer to the input data
* @data_len: data length
- * @algo: requested hash algorithm
+ * @name: requested hash algorithm name
* @value: pointer to the char, will hold hash value data (caller must
* allocate enough free space)
* value_len: length of the calculated hash
return -1;
}
- hash_algo = hash_algo_lookup_by_name(algo);
+ hash_algo = hash_algo_lookup_by_name(name);
if (hash_algo == HASH_ALGO_INVALID) {
debug("Unsupported hash algorithm\n");
return -1;
#ifndef USE_HOSTCC
#include <common.h>
#include <env.h>
+#include <init.h>
#include <lmb.h>
#include <log.h>
#include <malloc.h>
#include <linux/errno.h>
#include <asm/io.h>
-#ifdef CONFIG_CMD_BDI
-extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/* Set this if we have less than 4 MB of malloc() space */
* Scenario 2: If there is an fdt_addr specified, pass it along to
* bootm, and adjust argc appropriately.
*
- * Scenario 3: fdt blob is not available.
+ * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
+ * bootm, and adjust argc appropriately.
+ *
+ * Scenario 4: fdt blob is not available.
*/
bootm_argv[3] = env_get("fdt_addr_r");
if (!bootm_argv[3])
bootm_argv[3] = env_get("fdt_addr");
+ if (!bootm_argv[3])
+ bootm_argv[3] = env_get("fdtcontroladdr");
+
if (bootm_argv[3]) {
if (!bootm_argv[2])
bootm_argv[2] = "-";
config CMD_TRACE
bool "trace - Support tracing of function calls and timing"
+ depends on TRACE
+ default y
help
Enables a command to control using of function tracing within
U-Boot. This allows recording of call traces including timing
int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd)
{
- const char *ep = env_get("autostart");
-
- if (ep && !strcmp(ep, "yes")) {
+ if (env_get_autostart()) {
char *local_args[2];
local_args[0] = (char *)cmd;
local_args[1] = NULL;
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
char *sload = NULL;
- const char *ep = env_get("autostart");
int rcode = 0;
/* Consume 'bootelf' */
else
addr = load_elf_image_shdr(addr);
- if (ep && !strcmp(ep, "no"))
+ if (!env_get_autostart())
return rcode;
printf("## Starting application at 0x%08lx ...\n", addr);
if (argc < 1 || argc > 2)
return CMD_RET_USAGE;
int min_dev = 0;
- int max_dev = CONFIG_HOST_MAX_DEVICES - 1;
+ int max_dev = SANDBOX_HOST_MAX_DEVICES - 1;
if (argc >= 2) {
char *ep;
char *dev_str = argv[1];
for (i = 0; i < count; i++) {
struct disk_partition p;
- if (part_get_info(dev, i+1, &p))
+ if (part_get_info(dev, i + 1, &p))
goto fail;
- if ((partitions[i].size && p.size < partitions[i].size) ||
- (partitions[i].start && p.start < partitions[i].start) ||
- (p.sys_ind != partitions[i].sys_ind))
+ if ((partitions[i].size && p.size != partitions[i].size) ||
+ (partitions[i].start && p.start != partitions[i].start) ||
+ p.sys_ind != partitions[i].sys_ind)
goto fail;
}
ret = 0;
return ret == 0 ? 0 : 1;
}
-#ifdef CONFIG_CMD_SF_TEST
enum {
STAGE_ERASE,
STAGE_CHECK,
STAGE_COUNT,
};
-static char *stage_name[STAGE_COUNT] = {
+static const char *stage_name[STAGE_COUNT] = {
"erase",
"check",
"write",
return 0;
}
-#endif /* CONFIG_CMD_SF_TEST */
static int do_spi_flash(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
ret = do_spi_flash_erase(argc, argv);
else if (strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
-#ifdef CONFIG_CMD_SF_TEST
- else if (!strcmp(cmd, "test"))
+ else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
-#endif
else
ret = -1;
return CMD_RET_USAGE;
}
-#ifdef CONFIG_CMD_SF_TEST
-#define SF_TEST_HELP "\nsf test offset len " \
- "- run a very basic destructive test"
-#else
-#define SF_TEST_HELP
-#endif
-
-U_BOOT_CMD(
- sf, 5, 1, do_spi_flash,
- "SPI flash sub-system",
+#ifdef CONFIG_SYS_LONGHELP
+static const char long_help[] =
"probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset|partition len - read `len' bytes starting at\n"
" at `addr' to flash at `offset'\n"
" or to start of mtd `partition'\n"
"sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n"
- " at address 'sector'\n"
- SF_TEST_HELP
+ " at address 'sector'"
+#ifdef CONFIG_CMD_SF_TEST
+ "\nsf test offset len - run a very basic destructive test"
+#endif
+#endif /* CONFIG_SYS_LONGHELP */
+ ;
+
+U_BOOT_CMD(
+ sf, 5, 1, do_spi_flash,
+ "SPI flash sub-system", long_help
);
void *key;
struct udevice *dev;
- rc = get_tpm(&dev);
- if (rc)
- return rc;
+ err = get_tpm(&dev);
+ if (err)
+ return err;
if (argc < 5)
return CMD_RET_USAGE;
return CMD_RET_FAILURE;
parse_byte_string(argv[4], usage_auth, NULL);
- err = tpm_find_key_sha1(usage_auth, parent_hash, &parent_handle);
+ err = tpm1_find_key_sha1(dev, usage_auth, parent_hash, &parent_handle);
if (err) {
printf("Could not find matching parent key (err = %d)\n", err);
return CMD_RET_FAILURE;
printf("Found parent key %08x\n", parent_handle);
- err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
+ err = tpm1_load_key2_oiap(dev, parent_handle, key, key_len, usage_auth,
&key_handle);
if (!err) {
printf("Key handle is 0x%x\n", key_handle);
static int do_tpm_list(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ struct udevice *dev;
int type = 0;
u16 res_count;
u8 buf[288];
int err;
uint i;
+ err = get_tpm(&dev);
+ if (err)
+ return err;
+
if (argc != 2)
return CMD_RET_USAGE;
}
/* fetch list of already loaded resources in the TPM */
- err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
+ err = tpm_get_capability(dev, TPM_CAP_HANDLE, type, buf,
sizeof(buf));
if (err) {
printf("tpm_get_capability returned error %d.\n", err);
more data will be recorded until some is removed. The buffer is
allocated immediately after the malloc() region is ready.
+config CONSOLE_RECORD_OUT_SIZE_F
+ hex "Output buffer size before relocation"
+ depends on CONSOLE_RECORD
+ default 0x400 if CONSOLE_RECORD
+ help
+ Set the size of the console output buffer before relocation. When
+ this fills up, no more data will be recorded until some is removed.
+ The buffer is allocated immediately after the early malloc() region is
+ ready.
+
config CONSOLE_RECORD_IN_SIZE
hex "Input buffer size"
depends on CONSOLE_RECORD
This enables a bloblist in TPL. The bloblist is set up in TPL and
passed to SPL and U-Boot proper.
+if BLOBLIST
+
config BLOBLIST_SIZE
hex "Size of bloblist"
depends on BLOBLIST
is set up in the first part of U-Boot to run (TPL, SPL or U-Boot
proper), and this sane bloblist is used for subsequent stages.
+config BLOBLIST_ALLOC
+ bool "Allocate bloblist"
+ help
+ Allocate the bloblist using malloc(). This avoids the need to
+ specify a fixed address on systems where this is unknown or can
+ change at runtime.
+
config BLOBLIST_ADDR
hex "Address of bloblist"
- depends on BLOBLIST
default 0xc000 if SANDBOX
help
Sets the address of the bloblist, set up by the first part of U-Boot
which runs. Subsequent U-Boot stages typically use the same address.
+ This is not used if BLOBLIST_ALLOC is selected.
+
config BLOBLIST_SIZE_RELOC
hex "Size of bloblist after relocation"
- depends on BLOBLIST
default BLOBLIST_SIZE
help
Sets the size of the bloblist in bytes after relocation. Since U-Boot
size than the one set up by SPL. This bloblist is set up during the
relocation process.
+endif # BLOBLIST
+
endmenu
source "common/spl/Kconfig"
Enable image_sign_info helper functions in SPL.
endif
+
+config FDT_SIMPLEFB
+ bool "FDT tools for simplefb support"
+ depends on OF_LIBFDT
+ help
+ Enable the fdt tools to manage the simple fb nodes in device tree.
+ These functions can be used by board to indicate to the OS
+ the presence of the simple frame buffer with associated reserved
+ memory
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
+obj-$(CONFIG_FDT_SIMPLEFB) += fdt_simplefb.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_MII) += miiphyutil.o
obj-$(CONFIG_CMD_MII) += miiphyutil.o
obj-$(CONFIG_LCD) += lcd.o lcd_console.o
endif
obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o
-obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_UPDATE_COMMON) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
#include <common.h>
#include <bloblist.h>
#include <log.h>
+#include <malloc.h>
#include <mapmem.h>
#include <spl.h>
#include <asm/global_data.h>
ret = bloblist_check(CONFIG_BLOBLIST_ADDR,
CONFIG_BLOBLIST_SIZE);
if (ret) {
+ ulong addr;
+
log(LOGC_BLOBLIST, expected ? LOGL_WARNING : LOGL_DEBUG,
"Existing bloblist not found: creating new bloblist\n");
- ret = bloblist_new(CONFIG_BLOBLIST_ADDR, CONFIG_BLOBLIST_SIZE,
- 0);
+ if (IS_ENABLED(CONFIG_BLOBLIST_ALLOC)) {
+ void *ptr = memalign(BLOBLIST_ALIGN,
+ CONFIG_BLOBLIST_SIZE);
+
+ if (!ptr)
+ return log_msg_ret("alloc", -ENOMEM);
+ addr = map_to_sysmem(ptr);
+ } else {
+ addr = CONFIG_BLOBLIST_ADDR;
+ }
+ ret = bloblist_new(addr, CONFIG_BLOBLIST_SIZE, 0);
} else {
log(LOGC_BLOBLIST, LOGL_DEBUG, "Found existing bloblist\n");
}
static int reloc_bloblist(void)
{
#ifdef CONFIG_BLOBLIST
- if (gd->flags & GD_FLG_SKIP_RELOC)
+ /*
+ * Relocate only if we are supposed to send it
+ */
+ if ((gd->flags & GD_FLG_SKIP_RELOC) &&
+ CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) {
+ debug("Not relocating bloblist\n");
return 0;
+ }
if (gd->new_bloblist) {
int size = CONFIG_BLOBLIST_SIZE;
static int setup_reloc(void)
{
- if (gd->flags & GD_FLG_SKIP_RELOC) {
- debug("Skipping relocation due to flag\n");
- return 0;
- }
-
+ if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
#ifdef CONFIG_SYS_TEXT_BASE
#ifdef ARM
- gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
+ gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
#elif defined(CONFIG_M68K)
- /*
- * On all ColdFire arch cpu, monitor code starts always
- * just after the default vector table location, so at 0x400
- */
- gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
+ /*
+ * On all ColdFire arch cpu, monitor code starts always
+ * just after the default vector table location, so at 0x400
+ */
+ gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
#elif !defined(CONFIG_SANDBOX)
- gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
+ gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
#endif
#endif
+ }
+
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
- debug("Relocation Offset is: %08lx\n", gd->reloc_off);
- debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
- gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
- gd->start_addr_sp);
+ if (gd->flags & GD_FLG_SKIP_RELOC) {
+ debug("Skipping relocation due to flag\n");
+ } else {
+ debug("Relocation Offset is: %08lx\n", gd->reloc_off);
+ debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
+ gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
+ gd->start_addr_sp);
+ }
return 0;
}
int ret;
ret = membuff_new((struct membuff *)&gd->console_out,
- CONFIG_CONSOLE_RECORD_OUT_SIZE);
+ gd->flags & GD_FLG_RELOC ?
+ CONFIG_CONSOLE_RECORD_OUT_SIZE :
+ CONFIG_CONSOLE_RECORD_OUT_SIZE_F);
if (ret)
return ret;
ret = membuff_new((struct membuff *)&gd->console_in,
DECLARE_GLOBAL_DATA_PTR;
-static int lcd_dt_simplefb_configure_node(void *blob, int off)
+static int fdt_simplefb_configure_node(void *blob, int off)
{
int xsize, ysize;
int bpix; /* log2 of bits per pixel */
xsize * (1 << bpix) / 8, name);
}
-int lcd_dt_simplefb_add_node(void *blob)
+int fdt_simplefb_add_node(void *blob)
{
static const char compat[] = "simple-framebuffer";
static const char disabled[] = "disabled";
if (ret < 0)
return -1;
- return lcd_dt_simplefb_configure_node(blob, off);
+ return fdt_simplefb_configure_node(blob, off);
}
-int lcd_dt_simplefb_enable_existing_node(void *blob)
+int fdt_simplefb_enable_existing_node(void *blob)
{
int off;
if (off < 0)
return -1;
- return lcd_dt_simplefb_configure_node(blob, off);
+ return fdt_simplefb_configure_node(blob, off);
}
+
+#if CONFIG_IS_ENABLED(DM_VIDEO)
+int fdt_simplefb_enable_and_mem_rsv(void *blob)
+{
+ struct fdt_memory mem;
+ int ret;
+
+ /* nothing to do when video is not active */
+ if (!video_is_active())
+ return 0;
+
+ ret = fdt_simplefb_enable_existing_node(blob);
+ if (ret)
+ return ret;
+
+ /* nothing to do when the frame buffer is not defined */
+ if (gd->video_bottom == gd->video_top)
+ return 0;
+
+ /* reserved with no-map tag the video buffer */
+ mem.start = gd->video_bottom;
+ mem.end = gd->video_top - 1;
+
+ return fdtdec_add_reserved_memory(blob, "framebuffer", &mem, NULL, 0, NULL,
+ FDTDEC_RESERVED_MEMORY_NO_MAP);
+}
+#endif
if (fit_image_get_data_size(fit, node, &len))
return -ENOENT;
+ /* Dont bother to copy 0 byte data, but warn, though */
+ if (!len) {
+ log_warning("%s: Skip load '%s': image size is 0!\n",
+ __func__, fit_get_name(fit, node, NULL));
+ return 0;
+ }
+
src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
length = len;
ifneq ($(BOARD),)
ifdef VENDOR
BOARDDIR = $(VENDOR)/$(BOARD)
+ENVDIR=${vendor}/env
else
BOARDDIR = $(BOARD)
+ENVDIR=${board}/env
endif
endif
ifdef BOARD
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFFE00201
+CONFIG_SYS_OR0_PRELIM=0xFFE00014
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0x0
+CONFIG_SYS_OR1_PRELIM=0x0
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0x30000001
+CONFIG_SYS_OR2_PRELIM=0xFFF80000
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0x0
+CONFIG_SYS_OR3_PRELIM=0x0
+CONFIG_SYS_BR4_PRELIM_BOOL=y
+CONFIG_SYS_BR4_PRELIM=0x0
+CONFIG_SYS_OR4_PRELIM=0x0
+CONFIG_SYS_BR5_PRELIM_BOOL=y
+CONFIG_SYS_BR5_PRELIM=0x0
+CONFIG_SYS_OR5_PRELIM=0x0
+CONFIG_SYS_BR6_PRELIM_BOOL=y
+CONFIG_SYS_BR6_PRELIM=0x0
+CONFIG_SYS_OR6_PRELIM=0x0
+CONFIG_SYS_BR7_PRELIM_BOOL=y
+CONFIG_SYS_BR7_PRELIM=0x701
+CONFIG_SYS_OR7_PRELIM=0xFFC0007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bootm ffe40000"
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_DER=0x2002000F
-CONFIG_SYS_BR0_PRELIM=0x04000801
-CONFIG_SYS_OR0_PRELIM=0xFFC00926
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0x00000081
-CONFIG_SYS_OR1_PRELIM=0xFE000E00
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0x08000801
-CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0x0C000401
-CONFIG_SYS_OR3_PRELIM=0xFFFF8142
-CONFIG_SYS_BR4_PRELIM_BOOL=y
-CONFIG_SYS_BR4_PRELIM=0x10000801
-CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
-CONFIG_SYS_BR5_PRELIM_BOOL=y
-CONFIG_SYS_BR5_PRELIM=0x14000801
-CONFIG_SYS_OR5_PRELIM=0xFFFF8916
-CONFIG_SYS_BR6_PRELIM_BOOL=y
-CONFIG_SYS_BR6_PRELIM=0x18000801
-CONFIG_SYS_OR6_PRELIM=0xFFFF0908
-CONFIG_SYS_BR7_PRELIM_BOOL=y
-CONFIG_SYS_BR7_PRELIM=0x1C000001
-CONFIG_SYS_OR7_PRELIM=0xFFFF810A
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_ENV_ADDR=0x4004000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0x4000801
+CONFIG_SYS_OR0_PRELIM=0xFFC00926
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0x81
+CONFIG_SYS_OR1_PRELIM=0xFE000E00
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0x8000801
+CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xC000401
+CONFIG_SYS_OR3_PRELIM=0xFFFF8142
+CONFIG_SYS_BR4_PRELIM_BOOL=y
+CONFIG_SYS_BR4_PRELIM=0x10000801
+CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
+CONFIG_SYS_BR5_PRELIM_BOOL=y
+CONFIG_SYS_BR5_PRELIM=0x14000801
+CONFIG_SYS_OR5_PRELIM=0xFFFF8916
+CONFIG_SYS_BR6_PRELIM_BOOL=y
+CONFIG_SYS_BR6_PRELIM=0x18000801
+CONFIG_SYS_OR6_PRELIM=0xFFFF0908
+CONFIG_SYS_BR7_PRELIM_BOOL=y
+CONFIG_SYS_BR7_PRELIM=0x1C000001
+CONFIG_SYS_OR7_PRELIM=0xFFFF810A
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_DM=y
CONFIG_FSL_SATA=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFE001001
+CONFIG_SYS_OR0_PRELIM=0xFF800193
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0600C21
+CONFIG_SYS_OR1_PRELIM=0xFFFF8396
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xF0000801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_DM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF807001
+CONFIG_SYS_OR0_PRELIM=0xFF806E65
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xFF007001
+CONFIG_SYS_OR1_PRELIM=0xFF806E65
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xF0007861
+CONFIG_SYS_OR2_PRELIM=0xFC006901
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xF8006801
+CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_DM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF801001
+CONFIG_SYS_OR0_PRELIM=0xFF806E65
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xFF001001
+CONFIG_SYS_OR1_PRELIM=0xFF806E65
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xF0001861
+CONFIG_SYS_OR2_PRELIM=0xFC006901
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xF8000801
+CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
CONFIG_DM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF801001
+CONFIG_SYS_OR0_PRELIM=0xFF806E65
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xFF001001
+CONFIG_SYS_OR1_PRELIM=0xFF806E65
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xF0001861
+CONFIG_SYS_OR2_PRELIM=0xFC006901
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xF8000801
+CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF800C21
+CONFIG_SYS_OR0_PRELIM=0xFFFF8396
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xEF001001
+CONFIG_SYS_OR1_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF800C21
+CONFIG_SYS_OR0_PRELIM=0xFFFF8396
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xEF001001
+CONFIG_SYS_OR1_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF800C21
+CONFIG_SYS_OR0_PRELIM=0xFFFF8796
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xEC001001
+CONFIG_SYS_OR1_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEC001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEC001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEC001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF800C21
+CONFIG_SYS_OR0_PRELIM=0xFFFF8396
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xEF001001
+CONFIG_SYS_OR1_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF800C21
+CONFIG_SYS_OR0_PRELIM=0xFFFF8396
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xEF001001
+CONFIG_SYS_OR1_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xEF001001
+CONFIG_SYS_OR0_PRELIM=0xFC000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xFFB00801
+CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFA00801
+CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFFA00C21
+CONFIG_SYS_OR0_PRELIM=0xFFFC0796
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8001001
+CONFIG_SYS_OR1_PRELIM=0xF8000F85
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFFA00C21
+CONFIG_SYS_OR0_PRELIM=0xFFFC0796
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xE8001001
+CONFIG_SYS_OR2_PRELIM=0xF8000F85
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFFA00C21
+CONFIG_SYS_OR0_PRELIM=0xFFFC0796
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xE8001001
+CONFIG_SYS_OR2_PRELIM=0xF8000F85
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xE8001001
+CONFIG_SYS_OR0_PRELIM=0xF8000F85
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0001001
+CONFIG_SYS_OR1_PRELIM=0xF8000FF7
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xFFDF0801
+CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg"
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt;run mmcboot;run nandboot;run netboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run eval_boot_device;part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;setenv bootargs console=${console} vt.global_cursor_default=0 root=PARTUUID=${root_fs_partuuid} rootfstype=ext4 rootwait rootdelay=1;fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};bootz ${loadaddr} - ${fdtaddr}"
CONFIG_BOARD_LATE_INIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if mmc dev 1; mmc rescan; then run emmc_setup; else echo ERROR: eMMC device not detected!; panic; fi; if run loaduimage; then run mmcboot; else echo ERROR Unable to load uImage from eMMC!; echo Performing Rollback!; setenv _active_ ${active_root}; setenv _inactive_ ${inactive_root}; setenv active_root ${_inactive_}; setenv inactive_root ${_active_}; saveenv; reset; fi; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR: SD/MMC-Card not detected!; panic; fi; run fusecmd; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run fusecmd; if run netboot; then echo Booting from network; else echo ERROR: Cannot boot from network!; panic; fi; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR: SD/MMC-Card not detected!; panic; fi; if run loaduimage; then echo Bootable SD/MMC-Card inserted, booting from it!; run mmcboot; else echo ERROR: Unable to load uImage from SD/MMC-Card!; panic; fi; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_GPIO=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_CLK_CCF=y
+CONFIG_SPL_CLK_CCF=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_TORRENT=y
+CONFIG_SPL_PHY_CADENCE_TORRENT=y
+CONFIG_PHY_J721E_WIZ=y
+CONFIG_SPL_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
CONFIG_SPL_TEXT_BASE=0x70000000
CONFIG_SPL_SPI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_CLK_CCF=y
+CONFIG_SPL_CLK_CCF=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_SIERRA=y
+CONFIG_SPL_PHY_CADENCE_SIERRA=y
+CONFIG_PHY_CADENCE_TORRENT=y
+CONFIG_SPL_PHY_CADENCE_TORRENT=y
+CONFIG_PHY_J721E_WIZ=y
+CONFIG_SPL_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bootm ffc20000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f650000"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="ap121 # "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f680000"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="ap143 # "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f060000"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="ap152 # "
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&run alteraload&&bootm 0x80000;update;reset"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:3; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:3; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x22000000 uImage; bootm"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x71000000 dtb; fatload mmc 0:1 0x72000000 zImage; bootz 0x72000000 - 0x71000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};fatload mmc 0:1 0x21000000 dtb;fatload mmc 0:1 0x22000000 uImage;bootm 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_nand};nand read 0x21000000 0x180000 0x080000;nand read 0x22000000 0x200000 0x400000;bootm 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_nand};sf probe 0; sf read 0x22000000 0x100000 0x300000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x600000; nand read 0x21000000 0x180000 0x80000; bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x600000; nand read 0x21000000 0x180000 0x20000; bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x100000 0x300000; bootm 0x22000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flash_pending_rfs_imgs;run fastboot_nitro && run bootcmd_mmc_fits || run bootcmd_usb || run bootcmd_pxe"
CONFIG_LOGLEVEL=7
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter passphrase to stop autoboot, booting in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR="123"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run set_gpio122; run set_gpio96; sf probe; run manage_userdata; run bootcmd_nand"
CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SMP=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run mmcboot; run nandboot; run netboot"
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
+CONFIG_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS_SUBST=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tpm init; tpm startup TPM2_SU_CLEAR; read mmc 0:2 100000 0 80; setexpr loader *001004f0; setexpr size *00100518; setexpr blocks $size / 200; read mmc 0:2 100000 80 $blocks; setexpr setup $loader - 1000; setexpr cmdline_ptr $loader - 2000; setexpr.s cmdline *$cmdline_ptr; setexpr cmdline gsub %U \\\\${uuid}; if part uuid mmc 0:2 uuid; then zboot start 100000 0 0 0 $setup cmdline; zboot load; zboot setup; zboot dump; zboot go;fi"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
+CONFIG_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
+CONFIG_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
+CONFIG_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="echo SD boot attempt ...; run sdbootscript; run sdboot; echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; echo USB boot attempt ...; run usbbootscript; "
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="mmc dev 0; if mmc rescan; then if run loadbootscript; then run bootscript; fi; fi; mmc dev 1; if mmc rescan; then run emmcboot; fi;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFFE00201
+CONFIG_SYS_OR0_PRELIM=0xFFE00014
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0x0
+CONFIG_SYS_OR1_PRELIM=0x0
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0x0
+CONFIG_SYS_OR2_PRELIM=0x0
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0x0
+CONFIG_SYS_OR3_PRELIM=0x0
+CONFIG_SYS_BR4_PRELIM_BOOL=y
+CONFIG_SYS_BR4_PRELIM=0x0
+CONFIG_SYS_OR4_PRELIM=0x0
+CONFIG_SYS_BR5_PRELIM_BOOL=y
+CONFIG_SYS_BR5_PRELIM=0x0
+CONFIG_SYS_OR5_PRELIM=0x0
+CONFIG_SYS_BR6_PRELIM_BOOL=y
+CONFIG_SYS_BR6_PRELIM=0x0
+CONFIG_SYS_OR6_PRELIM=0x0
+CONFIG_SYS_BR7_PRELIM_BOOL=y
+CONFIG_SYS_BR7_PRELIM=0x701
+CONFIG_SYS_OR7_PRELIM=0xFF00007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_IMX_HAB=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb "
# CONFIG_CONSOLE_MUX is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_LOAD_ADDR=0xa0000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if fatload mmc 0 0xa0000000 uImage; then bootm 0xa0000000; fi; if usb reset && fatload usb 0 0xa0000000 uImage; then bootm 0xa0000000; fi; bootm 0xc0000;"
CONFIG_SYS_DEVICE_NULLDEV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
CONFIG_LOGLEVEL=3
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;run boot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;run boot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if env exists keyprogram; then; setenv keyprogram; run nfsboot; fi; run dobootfail"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp; tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; setenv bootargs ${bootargs} ${nfsargs} ${userargs}; bootm ${loadaddr} - ${dtbaddr}"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_TARGET_DEVKIT8000=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda1 ro quiet"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;run boot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run check_em_pad; then run recovery;else if test ${BOOT_FROM} = FACTORY; then run factory_nfs;else run boot_mmc;fi;fi"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test -n ${bootenv} && usb start; then if run loadbootenv; then echo Loaded environment ${bootenv} from usb;run importbootenv;fi;if test -n ${bootenvcmd}; then echo Running bootenvcmd ...;run bootenvcmd;fi;fi;run setnandbootenv subbootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; ubifsload 0x1100000 ${initrd}; bootm 0x800000 0x1100000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv ethact ethernet-controller@72000; ${x_bootcmd_ethernet}; setenv ethact ethernet-controller@76000; ${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv ethact egiga0; ${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe; sf read ${loadaddr} 0xd0000 0x2d0000; sf read ${ramdisk_addr_r} 0x3a0000 0x430000; bootm ${loadaddr} ${ramdisk_addr_r}"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="printenv"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="printenv"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1"
CONFIG_ROCKCHIP_RV1108=y
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_TARGET_ELGIN_RV1108=y
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0xc6000 0x294000; bootm 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_ASPEED=y
-CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_ASPEED_AST2600=y
CONFIG_TARGET_EVB_AST2600=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x83000000
CONFIG_SPL_SIZE_LIMIT=0x10000
CONFIG_SPL=y
# CONFIG_ARMV7_NONSEC is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_FIT=y
-# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="bootm 20100000"
+CONFIG_BOOTCOMMAND="run bootspi"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000
+CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
+CONFIG_DM_HASH=y
+CONFIG_HASH_ASPEED=y
+CONFIG_ASPEED_ACRY=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_WDT=y
+CONFIG_SHA512_ALGO=y
+CONFIG_SHA512=y
+CONFIG_SHA384=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
+CONFIG_PHANDLE_CHECK_SEQ=y
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
CONFIG_ROCKCHIP_RK3128=y
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
CONFIG_ROCKCHIP_RV1108=y
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x62000000
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="sf probe;sf read 0x62000000 0x140800 0x500000;dcache off;go 0x62000000"
CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/mmcblk0p3 rw rootwait console=$consoledev,$baudrate $othbootargs;ext2load mmc 0:2 ${kernel_addr} $bootfile;ext2load mmc 0:2 ${fdt_addr} $fdtfile;bootm ${kernel_addr} - ${fdt_addr}"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_ICS8N3QV01=y
CONFIG_CPU=y
CONFIG_CPU_MPC83XX=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFE001001
+CONFIG_SYS_OR0_PRELIM=0xFF800FF6
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE0601001
+CONFIG_SYS_OR1_PRELIM=0xFFF00850
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xE0701001
+CONFIG_SYS_OR2_PRELIM=0xFFF00850
CONFIG_DM_PCA953X=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run tryboot;"
CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_LOG_MAX_LEVEL=8
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run doquiet; run tryboot"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; bootm 0x800000"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part rootfs; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; bootm 0x800000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_DELAY_STR="ids"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run boot_cramfs"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS;echo"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_I2C=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFF800801
+CONFIG_SYS_OR0_PRELIM=0xFF8008A7
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE1000C21
+CONFIG_SYS_OR1_PRELIM=0xFFFF87CE
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xE2000801
+CONFIG_SYS_OR2_PRELIM=0xFFFE0C74
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xE3000801
+CONFIG_SYS_OR3_PRELIM=0xFFFF8814
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3100
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run ${bootpri} ; run ${bootsec}"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run prebootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot"
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run boot${boot-mode}"
CONFIG_DEFAULT_FDT_FILE="ask"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
+CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
+CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
+CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
+CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftpboot ; bootm"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftpboot ; bootm"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftpboot ; bootm"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_LOAD_ADDR=0x7fc0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftpboot ; bootm"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_mon_${boot} run_mon; run set_name_pmmc get_pmmc_${boot} run_pmmc; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xFC000E25
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xA0000801
+CONFIG_SYS_OR3_PRELIM=0xF0000E25
+CONFIG_SYS_BR4_PRELIM_BOOL=y
+CONFIG_SYS_BR4_PRELIM=0xB0000801
+CONFIG_SYS_OR4_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xFC000E25
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xA0000801
+CONFIG_SYS_OR3_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xF8000E25
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xA0000801
+CONFIG_SYS_OR2_PRELIM=0xF0000C25
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xB0001001
+CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xF8000E25
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xA0000801
+CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xF8000E25
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xB0001001
+CONFIG_SYS_OR3_PRELIM=0xF0000050
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xF8000E25
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xA0000801
+CONFIG_SYS_OR2_PRELIM=0xF0000C25
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xB0001001
+CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="."
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run usbupd; run distro_bootcmd"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SILENT_CONSOLE_UPDATE_ON_SET is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
CONFIG_AUTOBOOT_STOP_STR="l"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if mmc rescan; then if run loadbootscr; then run bootscript; else if run loadbootenv; then echo Loaded env from ${bootenvfile};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd...;run uenvcmd;fi;if run loadimage; then run mmcargs; if run loadfdt; then echo Using ${fdtfile}...;run fdtfixup; run fdtboot; fi; run mmcboot; fi; fi; fi; run flashargs; run flashboot"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_WATCHDOG=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run qspi_bootcmd"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_FIXED=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
+CONFIG_SJA1105=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_FIXED=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
+CONFIG_SJA1105=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nand_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fsl_mc lazyapply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_QSPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="sf probe 0:0;sf read 0x80001000 0xd00000 0x100000; fsl_mc lazyapply dpl 0x80001000 && sf read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_QSPI_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="sf probe 0:0;sf read 0x80001000 0xd00000 0x100000; fsl_mc lazyapply dpl 0x80001000 && sf read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply dpl 0x80001000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply dpl 0x80001000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="mmc read 0x80200000 0x6800 0x800; fsl_mc apply dpl 0x80200000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmc_mmc"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run try_bootscript"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="mt8183-pumpkin"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_LOAD_ADDR=0x4c000000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loaduimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else echo ERR: Fail to boot from MMC; fi; fi; else exit; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_FIT=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x380000
CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x92000000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x72000000
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run doquiet; run tryboot"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPI_BOOT=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USE_IMXIMG_PLUGIN=y
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_USE_IMXIMG_PLUGIN=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_AHCI=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run sdboot;run emmcboot;run attachboot;echo"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run preboot"
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_KEYBOARD=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd ; run autoboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_TYPES=y
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_LOGLEVEL=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_LOAD_ADDR=0x87000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; "
CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_LOAD_ADDR=0x87000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; "
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run emmcboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run check_env"
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
CONFIG_IDENT_STRING=" for ORIGEN"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_TARGET_PCM052=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run bootcmd_nand"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run mmcboot;run nandboot"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_PAYLOAD="u-boot.img"
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x88500000
CONFIG_BOOTDELAY=5
+CONFIG_BOOTCOMMAND="run distro_bootcmd || run legacy_bootcmd"
CONFIG_SYS_PROMPT="dask # "
# CONFIG_CMD_SAVEENV is not set
CONFIG_LOOPW=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SPL_I2C=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
CONFIG_PHY_REALTEK=y
-CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 "
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flashboot"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 "
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flashboot"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
-CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="fbcon=rotate:3 console=tty0 console=ttyS0,115200 root=/dev/mtdblock4 mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,1664k(env),2M(linux)ro,-(root) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs $(bootargs_console); run bootcmd_usb; bootm 0x00800000 0x01100000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
CONFIG_FIT_VERBOSE=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEBUG_UART_BASE=0x9000000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_MMIO=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_TARGET_QEMU_ARM_32BIT=y
+CONFIG_DEBUG_UART_BASE=0x9000000
+CONFIG_DEBUG_UART_CLOCK=0
CONFIG_ARMV7_LPAE=y
+CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40200000
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TPM2_MMIO=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77970-eagle.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77980-condor.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77990-ebisu.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_UPDATE_TFTP=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77995-draak.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a779a0-falcon.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-salvator-x.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb"
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-ulcb.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb"
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmcboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_LOAD_ADDR=0x44800000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run mmcboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;fatload mmc 0:1 0x22000000 zImage;bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x600000; nand read 0x21000000 0x180000 0x20000; bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x180000 0x80000; sf read 0x22000000 0x200000 0x600000; bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0 0x22000000 at91-sama5d27_giantboard.dtb; fatload mmc 0 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 1 0x22000000 at91-sama5d27_som1_ek.dtb; fatload mmc 1 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0 0x22000000 at91-sama5d27_som1_ek.dtb; fatload mmc 0 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_DISPLAY_PRINT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlycon earlyprintk=serial,ttyS0, ignore_loglevel root=/dev/mmcblk0p2 memtest=0 rootfstype=ext4 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x22000000 at91-sama5d2_xplained.dtb; fatload mmc 0:1 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x22000000 at91-sama5d2_xplained.dtb; fatload mmc 1:1 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 1:0; sf read 0x22000000 0x180000 0x80000; sf read 0x23000000 0x200000 0x600000; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; ext4load mmc 0:1 0x23000000 /boot/zImage; bootz 0x23000000 - 0x22000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
+CONFIG_HEXDUMP=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774c0-ek874.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if test ${bootdev} = 'usb'; then ${bootdev} start; fi; if test ${bootdev} = 'scsi'; then ${bootdev} scan; fi; ${bootdev} info; ${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} ${loadaddr} ${bootfile}; ${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} ${ramdiskaddr} ${ramdiskfile}; zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flashboot"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_I2C_S3C24X0=y
+# CONFIG_KEYBOARD is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_I2C_S3C24X0=y
+# CONFIG_KEYBOARD is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run ubifsboot"
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="SMDKC100 # "
CONFIG_IDENT_STRING=" for SMDKC210/V310"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="fatload mmc 0 40007000 uImage; bootm 40007000"
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SYS_PROMPT="SMDKV310 # "
# CONFIG_CMD_XIMG is not set
CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; "
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_SNIPER=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x12c30000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_S5P=y
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmc_mmc"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run try_bootscript"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run mmc_mmc"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\""
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="setenv bootcmd 'bridge enable; if test ${bootnum} = 'b'; then run _fpga_loadsafe; else if test ${bootcount} -eq 4; then echo 'Switching copy...'; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; run _fpga_loaduser; fi;echo 'Booting bank $bootnum' && run userload && run userboot;' && setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && saveenv && saveenv && boot;"
CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_secu1.dtb"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run selboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; elif test -n \"$force_boottype\" ; then setenv bootdelay 1 ; setenv boottype \"$force_boottype\" ; setenv force_boottype ; saveenv ; else setenv bootdelay 5 ; setenv boottype norm ; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run boot_nor"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ENV_ADDR=0xFFF40000
CONFIG_ENV_ADDR_REDUND=0xFFF20000
CONFIG_DM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xFE001001
+CONFIG_SYS_OR0_PRELIM=0xFE000030
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xFC001001
+CONFIG_SYS_OR1_PRELIM=0xFE000030
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xC80018A1
+CONFIG_SYS_OR2_PRELIM=0xFC000000
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xC0001881
+CONFIG_SYS_OR3_PRELIM=0xFFF00000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
# CONFIG_MMC is not set
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run setfdtfile; run checkbootdev; run loadfdt;if run loadbootscript; then run bootscript; else if run loadimage; then run setbootargs; bootz ${loadaddr} - ${fdt_addr}; fi; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
-# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
-# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
+# CONFIG_SCMI_AGENT_MAILBOX is not set
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_PHY=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_FDT_SIMPLEFB=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
+# CONFIG_SCMI_AGENT_MAILBOX is not set
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0:1 50000000; sf read ${loadaddr} 0x100000 ${kern_size}; bootm ${loadaddr}"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="go 0x40040000"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_MISC_INIT_R is not set
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_MISC_INIT_F=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXTENSION is not set
-CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_DATE is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_IP_DEFRAG=y
+# CONFIG_NET is not set
# CONFIG_ACPIGEN is not set
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
-# CONFIG_UDP_FUNCTION_FASTBOOT is not set
CONFIG_SANDBOX_GPIO=y
CONFIG_PCI=y
CONFIG_PCI_SANDBOX=y
CONFIG_DM_RTC=y
CONFIG_SOUND=y
CONFIG_SYSRESET=y
+CONFIG_TIMER=y
CONFIG_I2C_EDID=y
# CONFIG_VIRTIO_MMIO is not set
# CONFIG_VIRTIO_PCI is not set
# CONFIG_VIRTIO_SANDBOX is not set
+# CONFIG_EFI_LOADER is not set
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTDELAY=5
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if part number mmc 0 vbmeta is_avb; then echo MMC with vbmeta partition detected.; echo starting Android Verified boot.; avb init 0; if avb verify; then set bootargs $bootargs $avb_bootargs; part start mmc 0 boot boot_start; part size mmc 0 boot boot_size; mmc read ${load_addr} ${boot_start} ${boot_size}; bootm ${load_addr} ${load_addr} ${fdt_addr_r}; else; echo AVB verification failed.; exit; fi; elif part number mmc 0 system is_non_avb_android; then booti ${kernel_addr_r} ${initrd_addr_r} ${fdt_addr_r};else; echo Booting FIT image.; bootm ${load_addr} ${load_addr} ${fdt_addr_r}; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AVB_VERIFY=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xF8000E25
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xA0000801
+CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
+CONFIG_SYS_BR0_PRELIM_BOOL=y
+CONFIG_SYS_BR0_PRELIM=0xF0001001
+CONFIG_SYS_OR0_PRELIM=0xF0000E55
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0xE8000801
+CONFIG_SYS_OR1_PRELIM=0xF8000E25
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0xA0000801
+CONFIG_SYS_OR2_PRELIM=0xF0000C25
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0xB0000801
+CONFIG_SYS_OR3_PRELIM=0xF0000E24
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock1 mtdparts=mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2) rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nboot 21000000 0"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x72000000
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run distro_bootcmd; setenv bootargs console=${console} ${bootargs_default}; ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; bootz ${kernel_addr_r} - ${fdt_addr_r}"
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_I2C=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_DM=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9"
-# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="if smhload ${boot_name} ${boot_addr}; then set bootargs; abootimg addr ${boot_addr}; abootimg get dtb --index=0 fdt_addr; bootm ${boot_addr} ${boot_addr} ${fdt_addr}; else; set fdt_high 0xffffffffffffffff; set initrd_high 0xffffffffffffffff; smhload ${kernel_name} ${kernel_addr}; smhload ${fdtfile} ${fdt_addr}; smhload ${initrd_name} ${initrd_addr} initrd_end; fdt addr ${fdt_addr}; fdt resize; fdt chosen ${initrd_addr} ${initrd_end}; booti $kernel_addr - $fdt_addr; fi"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_LOGLEVEL=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_LOGLEVEL=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev 0 0;mmc read ${loadaddr} ${k_offset} ${k_blksize};mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};bootz ${loadaddr} - ${oftaddr}"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=0
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_EXPERT is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
part_drv = part_driver_lookup_type(dev_desc);
if (!part_drv)
return -1;
+
+ if (!part_drv->get_info) {
+ log_debug("## Driver %s does not have the get_info() method\n",
+ part_drv->name);
+ return -ENOSYS;
+ }
+
for (i = 1; i < part_drv->max_entries; i++) {
ret = part_drv->get_info(dev_desc, i, info);
if (ret != 0) {
ext = &p[i];
}
- if (i >= 4 && !ext) {
- printf("%s: extended partition is needed for more than 4 partitions\n",
- __func__);
- return -1;
+ if (count < 4)
+ return 0;
+
+ if (!ext) {
+ log_err("extended partition is needed for more than 4 partitions\n");
+ return -EINVAL;
}
/* calculate extended volumes start and size if needed */
-------------
The USB (at least the USB UHCI) needs a frame list (4k), transfer
-descripor and queue headers which are all located in the main memory.
-The UHCI allocates every milisecond the PCI bus and reads the current
+descriptor and queue headers which are all located in the main memory.
+The UHCI allocates every millisecond the PCI bus and reads the current
frame pointer. This may cause to crash the OS during boot. So the USB
_MUST_ be stopped during OS boot. This is the reason, why the USB is
NOT automatically started during start-up. If someone needs the USB
it before booting the OS.
For USB keyboards this can be done by a script which is automatically
-started after the U-Boot is up and running. To boot an OS with a an
+started after the U-Boot is up and running. To boot an OS with a
USB keyboard another script is necessary, which first disables the
USB and then executes the boot command. If the boot command fails,
-the script can reenable the USB kbd.
+the script can re-enable the USB keyboard.
Common USB Commands:
- usb start:
- usb info [dev]: shows all USB infos of the device dev, or of all
the devices
- usb stop [f]: stops the USB. If f==1 the USB will also stop if
- an USB keyboard is assigned as stdin. The stdin
+ a USB keyboard is assigned as stdin. The stdin
is then switched to serial input.
Storage USB Commands:
-- usb scan: scans the USB for storage devices.The USB must be
+- usb scan: scans the USB for storage devices. The USB must be
running for this command (usb start)
- usb device [dev]: show or set current USB storage device
- usb part [dev]: print partition table of one or all USB storage
Config Switches:
----------------
CONFIG_CMD_USB enables basic USB support and the usb command
-CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined
+CONFIG_USB_UHCI defines the lowlevel part. A lowlevel part must be defined
if using CONFIG_CMD_USB
CONFIG_USB_KEYBOARD enables the USB Keyboard
CONFIG_USB_STORAGE enables the USB storage devices
To enable USB Host Ethernet in U-Boot, your platform must of course
support USB with CONFIG_CMD_USB enabled and working. You will need to
-add some config settings to your board config:
+add some settings to your board configuration:
CONFIG_CMD_USB=y /* the 'usb' interactive command */
CONFIG_USB_HOST_ETHER=y /* Enable USB Ethernet adapters */
You can also set the default IP address of your board and the server
as well as the default file to load when a 'bootp' command is issued.
However note that encoding these individual network settings into a
-common exectuable is discouraged, as it leads to potential conflicts,
+common executable is discouraged, as it leads to potential conflicts,
and all the parameters can either get stored in the board's external
environment, or get obtained from the bootp server if not set.
#define CONFIG_SERVERIP 10.0.0.1 (replace with your value)
#define CONFIG_BOOTFILE "uImage"
-
The 'usb start' command should identify the adapter something like this:
CrOS> usb start
Most Ethernet dongles have a built-in MAC address which is unique in the
world. This is important so that devices on the network can be
-distinguised from each other. MAC address conflicts are evil and
-generally result in strange and eratic behaviour.
+distinguished from each other. MAC address conflicts are evil and
+generally result in strange and erratic behaviour.
Some boards have USB Ethernet chips on-board, and these sometimes do not
have an assigned MAC address. In this case it is up to you to assign
efi
getopt
linker_lists
+ lmb
logging
pinctrl
rng
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Logical memory blocks
+=====================
+
+.. kernel-doc:: include/lmb.h
+ :internal:
.. code-block:: text
- $ make PLATFORM=k3-am65x CFG_ARM64_core=y CFG_TEE_CORE_LOG_LEVEL=2 CFG_CONSOLE_UART=1
+ $ make PLATFORM=k3-am65x CFG_ARM64_core=y CFG_TEE_CORE_LOG_LEVEL=2 CFG_CONSOLE_UART=1 CFG_USER_TA_TARGETS="ta_arm64"
U-Boot:
dev: eMMC alt: 15 name: mmc1_rootfs layout: RAW_ADDR
dev: eMMC alt: 16 name: mmc1_userfs layout: RAW_ADDR
dev: MTD alt: 17 name: nor0 layout: RAW_ADDR
- dev: MTD alt: 18 name: nand0 layout: RAW_ADDR
- dev: VIRT alt: 19 name: OTP layout: RAW_ADDR
- dev: VIRT alt: 20 name: PMIC layout: RAW_ADDR
+ dev: MTD alt: 18 name: nor1 layout: RAW_ADDR
+ dev: MTD alt: 19 name: nand0 layout: RAW_ADDR
+ dev: VIRT alt: 20 name: OTP layout: RAW_ADDR
+ dev: VIRT alt: 21 name: PMIC layout: RAW_ADDR
All the supported device are exported for dfu-util tool::
$> dfu-util -l
- Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="PMIC", serial="002700333338511934383330"
- Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="OTP", serial="002700333338511934383330"
- Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nand0", serial="002700333338511934383330"
+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="PMIC", serial="002700333338511934383330"
+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="OTP", serial="002700333338511934383330"
+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nand0", serial="002700333338511934383330"
+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor1", serial="002700333338511934383330"
Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor0", serial="002700333338511934383330"
Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="mmc1_userfs", serial="002700333338511934383330"
Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="mmc1_rootfs", serial="002700333338511934383330"
When the board is booting for nor0 or nand0,
only the MTD partition on the boot devices are available, for example:
-- NOR (nor0 = alt 20) & NAND (nand0 = alt 26) ::
+- NOR (nor0 = alt 20, nor1 = alt 26) & NAND (nand0 = alt 27) :
$> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1.stm32
$> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1.stm32
$> dfu-util -d 0483:5720 -a 23 -D fip-stm32mp157c-ev1.bin
- $> dfu-util -d 0483:5720 -a 27 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
+ $> dfu-util -d 0483:5720 -a 28 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
- NAND (nand0 = alt 21)::
found. All access is via the blob's tag. Blob records are zeroed when added.
+Placing the bloblist
+--------------------
+
+The bloblist is typically positioned at a fixed address by TPL, or SPL. This
+is controlled by `CONFIG_BLOBLIST_ADDR`. But in some cases it is preferable to
+allocate the bloblist in the malloc() space. Use the `CONFIG_BLOBLIST_ALLOC`
+option to enable this.
+
+The bloblist is automatically relocated as part of U-Boot relocation. Sometimes
+it is useful to expand the bloblist in U-Boot proper, since it may want to add
+information for use by Linux. Note that this does not mean that Linux needs to
+know anything about the bloblist format, just that it is convenient to use
+bloblist to place things contiguously in memory. Set
+`CONFIG_BLOBLIST_SIZE_RELOC` to define the expanded size, if needed.
+
+
Finishing the bloblist
----------------------
The I2C subsystem has supported the driver model since early 2015.
Maintainers should submit patches switching over to using CONFIG_DM_I2C and
other base driver model options in time for inclusion in the 2021.10 release.
+
+CONFIG_KEYBOARD
+---------------
+Deadline: 2022.10
+
+This is a legacy option which has been replaced by driver model.
+Maintainers should submit patches switching over to using CONFIG_DM_KEYBOARD and
+other base driver model options in time for inclusion in the 2022.10 release.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Environment implementation
+==========================
+
+See :doc:`../usage/environment` for usage information.
+
+Callback functions for environment variables
+--------------------------------------------
+
+For some environment variables, the behavior of u-boot needs to change
+when their values are changed. This functionality allows functions to
+be associated with arbitrary variables. On creation, overwrite, or
+deletion, the callback will provide the opportunity for some side
+effect to happen or for the change to be rejected.
+
+The callbacks are named and associated with a function using the
+U_BOOT_ENV_CALLBACK macro in your board or driver code.
+
+These callbacks are associated with variables in one of two ways. The
+static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+in the board configuration to a string that defines a list of
+associations. The list must be in the following format::
+
+ entry = variable_name[:callback_name]
+ list = entry[,list]
+
+If the callback name is not specified, then the callback is deleted.
+Spaces are also allowed anywhere in the list.
+
+Callbacks can also be associated by defining the ".callbacks" variable
+with the same list format above. Any association in ".callbacks" will
+override any association in the static list. You can define
+CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
+".callbacks" environment variable in the default or embedded environment.
+
+If CONFIG_REGEX is defined, the variable_name above is evaluated as a
+regular expression. This allows multiple variables to be connected to
+the same callback without explicitly listing them all out.
+
+The signature of the callback functions is::
+
+ int callback(const char *name, const char *value, enum env_op op, int flags)
+
+* name - changed environment variable
+* value - new value of the environment variable
+* op - operation (create, overwrite, or delete)
+* flags - attributes of the environment variable change, see flags H_* in
+ include/search.h
+
+The return value is 0 if the variable change is accepted and 1 otherwise.
devicetree/index
distro
driver-model/index
+ environment
global_data
logging
makefiles
Tracing in U-Boot
=================
-U-Boot supports a simple tracing feature which allows a record of excecution
+U-Boot supports a simple tracing feature which allows a record of execution
to be collected and sent to a host machine for analysis. At present the
main use for this is to profile boot time.
way of trying out tracing before you use it on your actual board. To do
this, follow these steps:
-Add the following to include/configs/sandbox.h (if not already there)
+Add the following to config/sandbox_defconfig
.. code-block:: c
- #define CONFIG_TRACE
- #define CONFIG_CMD_TRACE
- #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
- #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
- #define CONFIG_TRACE_EARLY
- #define CONFIG_TRACE_EARLY_ADDR 0x00100000
+ CONFIG_TRACE=y
Build sandbox U-Boot with tracing enabled:
no more data will be collected.
Collecting trace data has an affect on execution time/performance. You
-will notice this particularly with trvial functions - the overhead of
+will notice this particularly with trivial functions - the overhead of
recording their execution may even exceed their normal execution time.
In practice this doesn't matter much so long as you are aware of the
-effect. Once you have done your optimisations, turn off tracing before
+effect. Once you have done your optimizations, turn off tracing before
doing end-to-end timing.
The best time to start tracing is right at the beginning of U-Boot. The
variable at this point. This variable should have a short script which
collects the trace data and writes it somewhere.
-Trace data collection relies on a microsecond timer, accesed through
+Trace data collection relies on a microsecond timer, accessed through
timer_get_us(). So the first think you should do is make sure that
this produces sensible results for your board. Suitable sources for
this timer include high resolution timers, PWMs or profile timers if
Specify U-Boot map file
-p <trace_file>
- Specifiy profile/trace file
+ Specify profile/trace file
Commands:
2. Build U-Boot with tracing and run it. Note the difference in boot time
(it is common for tracing to add 10% to the time)
-3. Collect the trace information as descibed above. Use this to find where
+3. Collect the trace information as described above. Use this to find where
all the time is being spent.
-4. Take a look at that code and see if you can optimise it. Perhaps it is
- possible to speed up the initialisation of a device, or remove an unused
+4. Take a look at that code and see if you can optimize it. Perhaps it is
+ possible to speed up the initialization of a device, or remove an unused
feature.
5. Rebuild, run and collect again. Compare your results.
The scmi node with the following properties shall be under the /firmware/ node.
-- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
+- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports,
+ or "linaro,scmi-optee" for OP-TEE transport.
- mboxes: List of phandle and mailbox channel specifiers. It should contain
exactly one or two mailboxes, one for transmitting messages("tx")
and another optional for receiving the notifications("rx") if
- #size-cells : should be '0' as 'reg' property doesn't have any size
associated with it.
- arm,smc-id : SMC id required when using smc or hvc transports
+- linaro,optee-channel-id : Channel specifier required when using OP-TEE
+ transport.
Optional properties:
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
about the generic mailbox controller and client driver bindings.
-
-The mailbox is the only permitted method of calling the SCMI firmware.
Mailbox doorbell is used as a mechanism to alert the presence of a
messages and/or notification.
Each protocol supported shall have a sub-node with corresponding compatible
as described in the following sections. If the platform supports dedicated
-communication channel for a particular protocol, the 3 properties namely:
-mboxes, mbox-names and shmem shall be present in the sub-node corresponding
-to that protocol.
+communication channel for a particular protocol, properties shall be present
+in the sub-node corresponding to that protocol. These properties are:
+- mboxes, mbox-names and shmem for mailbox transport
+- arm,smc-id and shmem for smc/hvc transport
+- linaro,optee-channel-id and possibly shmem for OP-TEE transport
Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
------------------------------------------------------------
MR2
MR3
-- st,phy-cal : phy cal depending of calibration or tuning of DDR
- This parameter is optional; when it is absent the built-in PHY
- calibration is done.
- for STM32MP15x: 12 values are requested in this order
- DX0DLLCR
- DX0DQTR
- DX0DQSTR
- DX1DLLCR
- DX1DQTR
- DX1DQSTR
- DX2DLLCR
- DX2DQTR
- DX2DQSTR
- DX3DLLCR
- DX3DQTR
- DX3DQSTR
-
Example:
/ {
0x00000000 /*MR3*/
>;
- st,phy-cal = <
- 0x40000000 /*DX0DLLCR*/
- 0xFFFFFFFF /*DX0DQTR*/
- 0x3DB02000 /*DX0DQSTR*/
- 0x40000000 /*DX1DLLCR*/
- 0xFFFFFFFF /*DX1DQTR*/
- 0x3DB02000 /*DX1DQSTR*/
- 0x40000000 /*DX2DLLCR*/
- 0xFFFFFFFF /*DX2DQTR*/
- 0x3DB02000 /*DX2DQSTR*/
- 0x40000000 /*DX3DLLCR*/
- 0xFFFFFFFF /*DX3DQTR*/
- 0x3DB02000 /*DX3DQSTR*/
- >;
-
status = "okay";
};
};
--- /dev/null
+Sandbox MMC
+===========
+
+Required properties:
+- compatible : "sandbox,mmc"
+
+Optional properties:
+- filename : Name of backing file, if any. This is mapped into the MMC device
+ so can be used to provide a filesystem or other test data
+
+
+Example
+-------
+
+mmc2 {
+ compatible = "sandbox,mmc";
+ non-removable;
+};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple GPIO controller
+
+maintainers:
+ - Mark Kettenis <kettenis@openbsd.org>
+
+description: |
+ The Apple GPIO controller is a simple combined pin and GPIO
+ controller present on Apple ARM SoC platforms, including various
+ iPhone and iPad devices and the "Apple Silicon" Macs.
+
+properties:
+ compatible:
+ items:
+ - const: apple,t8103-pinctrl
+ - const: apple,pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupts:
+ description: One interrupt for each of the (up to 7) interrupt
+ groups supported by the controller sorted by interrupt group
+ number in ascending order.
+ minItems: 1
+ maxItems: 7
+
+ interrupt-controller: true
+
+patternProperties:
+ '-pins$':
+ type: object
+ $ref: pinmux-node.yaml#
+
+ properties:
+ pinmux:
+ description:
+ Values are constructed from pin number and alternate function
+ configuration number using the APPLE_PINMUX() helper macro
+ defined in include/dt-bindings/pinctrl/apple.h.
+
+ required:
+ - pinmux
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/apple-aic.h>
+ #include <dt-bindings/pinctrl/apple.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl: pinctrl@23c100000 {
+ compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x3c100000 0x0 0x100000>;
+ clocks = <&gpio_clk>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 212>;
+
+ interrupt-controller;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>;
+
+ pcie_pins: pcie-pins {
+ pinmux = <APPLE_PINMUX(150, 1)>,
+ <APPLE_PINMUX(151, 1)>,
+ <APPLE_PINMUX(32, 1)>;
+ };
+ };
+ };
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Environment Variables
+=====================
+
+U-Boot supports user configuration using environment variables which
+can be made persistent by saving to persistent storage, for example flash
+memory.
+
+Environment variables are set using "env set" (alias "setenv"), printed using
+"env print" (alias "printenv"), and saved to persistent storage using
+"env save" (alias "saveenv"). Using "env set"
+without a value can be used to delete a variable from the
+environment. As long as you don't save the environment, you are
+working with an in-memory copy. In case the Flash area containing the
+environment is erased by accident, a default environment is provided.
+
+Some configuration is controlled by Environment Variables, so that setting the
+variable can adjust the behaviour of U-Boot (e.g. autoboot delay, autoloading
+from tftp).
+
+Text-based Environment
+----------------------
+
+The default environment for a board is created using a `.env` environment file
+using a simple text format. The base filename for this is defined by
+`CONFIG_ENV_SOURCE_FILE`, or `CONFIG_SYS_BOARD` if that is empty.
+
+The file must be in the board directory and have a .env extension, so
+assuming that there is a board vendor, the resulting filename is therefore::
+
+ board/<vendor>/<board>/<CONFIG_ENV_SOURCE_FILE>.env
+
+or::
+
+ board/<vendor>/<board>/<CONFIG_SYS_BOARD>.env
+
+This is a plain text file where you can type your environment variables in
+the form `var=value`. Blank lines and multi-line variables are supported.
+The conversion script looks for a line that starts in column 1 with a string
+and has an equals sign immediately afterwards. Spaces before the = are not
+permitted. It is a good idea to indent your scripts so that only the 'var='
+appears at the start of a line.
+
+To add additional text to a variable you can use `var+=value`. This text is
+merged into the variable during the make process and made available as a
+single value to U-Boot. Variables can contain `+` characters but in the unlikely
+event that you want to have a variable name ending in plus, put a backslash
+before the `+` so that the script knows you are not adding to an existing
+variable but assigning to a new one::
+
+ maximum\+=value
+
+This file can include C-style comments. Blank lines and multi-line
+variables are supported, and you can use normal C preprocessor directives
+and CONFIG defines from your board config also.
+
+For example, for snapper9260 you would create a text file called
+`board/bluewater/snapper9260.env` containing the environment text.
+
+Example::
+
+ stdout=serial
+ #ifdef CONFIG_LCD
+ stdout+=,lcd
+ #endif
+ bootcmd=
+ /* U-Boot script for booting */
+
+ if [ -z ${tftpserverip} ]; then
+ echo "Use 'setenv tftpserverip a.b.c.d' to set IP address."
+ fi
+
+ usb start; setenv autoload n; bootp;
+ tftpboot ${tftpserverip}:
+ bootm
+ failed=
+ /* Print a message when boot fails */
+ echo CONFIG_SYS_BOARD boot failed - please check your image
+ echo Load address is CONFIG_SYS_LOAD_ADDR
+
+If CONFIG_ENV_SOURCE_FILE is empty and the default filename is not present, then
+the old-style C environment is used instead. See below.
+
+Old-style C environment
+-----------------------
+
+Traditionally, the default environment is created in `include/env_default.h`,
+and can be augmented by various `CONFIG` defines. See that file for details. In
+particular you can define `CONFIG_EXTRA_ENV_SETTINGS` in your board file
+to add environment variables.
+
+Board maintainers are encouraged to migrate to the text-based environment as it
+is easier to maintain. The distro-board script still requires the old-style
+environment but work is underway to address this.
+
+
+List of environment variables
+-----------------------------
+
+Some device configuration options can be set using environment variables. In
+many cases the value in the default environment comes from a CONFIG option - see
+`include/env_default.h`) for this.
+
+This is most-likely not complete:
+
+baudrate
+ Used to set the baudrate of the UART - it defaults to CONFIG_BAUDRATE (which
+ defaults to 115200).
+
+bootdelay
+ Delay before automatically running bootcmd. During this time the user
+ can choose to enter the shell (or the boot menu if
+ CONFIG_AUTOBOOT_MENU_SHOW=y):
+
+ - 0 to autoboot with no delay, but you can stop it by key input.
+ - -1 to disable autoboot.
+ - -2 to autoboot with no delay and not check for abort
+
+ The default value is defined by CONFIG_BOOTDELAY.
+ The value of 'bootdelay' is overridden by the /config/bootdelay value in
+ the device-tree if CONFIG_OF_CONTROL=y.
+ Does it really make sense that the devicetree overrides the user setting?
+
+bootcmd
+ The command that is run if the user does not enter the shell during the
+ boot delay.
+
+bootargs
+ Command line arguments passed when booting an operating system or binary
+ image
+
+bootfile
+ Name of the image to load with TFTP
+
+bootm_low
+ Memory range available for image processing in the bootm
+ command can be restricted. This variable is given as
+ a hexadecimal number and defines lowest address allowed
+ for use by the bootm command. See also "bootm_size"
+ environment variable. Address defined by "bootm_low" is
+ also the base of the initial memory mapping for the Linux
+ kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+ bootm_mapsize.
+
+bootm_mapsize
+ Size of the initial memory mapping for the Linux kernel.
+ This variable is given as a hexadecimal number and it
+ defines the size of the memory region starting at base
+ address bootm_low that is accessible by the Linux kernel
+ during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used
+ as the default value if it is defined, and bootm_size is
+ used otherwise.
+
+bootm_size
+ Memory range available for image processing in the bootm
+ command can be restricted. This variable is given as
+ a hexadecimal number and defines the size of the region
+ allowed for use by the bootm command. See also "bootm_low"
+ environment variable.
+
+bootstopkeysha256, bootdelaykey, bootstopkey
+ See README.autoboot
+
+updatefile
+ Location of the software update file on a TFTP server, used
+ by the automatic software update feature. Please refer to
+ documentation in doc/README.update for more details.
+
+autoload
+ if set to "no" (any string beginning with 'n'),
+ "bootp" and "dhcp" will just load perform a lookup of the
+ configuration from the BOOTP server, but not try to
+ load any image using TFTP or DHCP.
+
+autostart
+ if set to "yes", an image loaded using the "bootp", "dhcp",
+ "rarpboot", "tftpboot" or "diskboot" commands will
+ be automatically started (by internally calling
+ "bootm")
+
+ If unset, or set to "1"/"yes"/"true" (case insensitive, just the first
+ character is enough), a standalone image
+ passed to the "bootm" command will be copied to the load address
+ (and eventually uncompressed), but NOT be started.
+ This can be used to load and uncompress arbitrary
+ data.
+
+fdt_high
+ if set this restricts the maximum address that the
+ flattened device tree will be copied into upon boot.
+ For example, if you have a system with 1 GB memory
+ at physical address 0x10000000, while Linux kernel
+ only recognizes the first 704 MB as low memory, you
+ may need to set fdt_high as 0x3C000000 to have the
+ device tree blob be copied to the maximum address
+ of the 704 MB low memory, so that Linux kernel can
+ access it during the boot procedure.
+
+ If this is set to the special value 0xffffffff (32-bit machines) or
+ 0xffffffffffffffff (64-bit machines) then
+ the fdt will not be copied at all on boot. For this
+ to work it must reside in writable memory, have
+ sufficient padding on the end of it for u-boot to
+ add the information it needs into it, and the memory
+ must be accessible by the kernel.
+
+fdtcontroladdr
+ if set this is the address of the control flattened
+ device tree used by U-Boot when CONFIG_OF_CONTROL is
+ defined.
+
+initrd_high
+ restrict positioning of initrd images:
+ If this variable is not set, initrd images will be
+ copied to the highest possible address in RAM; this
+ is usually what you want since it allows for
+ maximum initrd size. If for some reason you want to
+ make sure that the initrd image is loaded below the
+ CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+ variable to a value of "no" or "off" or "0".
+ Alternatively, you can set it to a maximum upper
+ address to use (U-Boot will still check that it
+ does not overwrite the U-Boot stack and data).
+
+ For instance, when you have a system with 16 MB
+ RAM, and want to reserve 4 MB from use by Linux,
+ you can do this by adding "mem=12M" to the value of
+ the "bootargs" variable. However, now you must make
+ sure that the initrd image is placed in the first
+ 12 MB as well - this can be done with::
+
+ setenv initrd_high 00c00000
+
+ If you set initrd_high to 0xffffffff (32-bit machines) or
+ 0xffffffffffffffff (64-bit machines), this is an
+ indication to U-Boot that all addresses are legal
+ for the Linux kernel, including addresses in flash
+ memory. In this case U-Boot will NOT COPY the
+ ramdisk at all. This may be useful to reduce the
+ boot time on your system, but requires that this
+ feature is supported by your Linux kernel.
+
+ipaddr
+ IP address; needed for tftpboot command
+
+loadaddr
+ Default load address for commands like "bootp",
+ "rarpboot", "tftpboot", "loadb" or "diskboot"
+
+loads_echo
+ see CONFIG_LOADS_ECHO
+
+serverip
+ TFTP server IP address; needed for tftpboot command
+
+bootretry
+ see CONFIG_BOOT_RETRY_TIME
+
+bootdelaykey
+ see CONFIG_AUTOBOOT_DELAY_STR
+
+bootstopkey
+ see CONFIG_AUTOBOOT_STOP_STR
+
+ethprime
+ controls which network interface is used first.
+
+ethact
+ controls which interface is currently active.
+ For example you can do the following::
+
+ => setenv ethact FEC
+ => ping 192.168.0.1 # traffic sent on FEC
+ => setenv ethact SCC
+ => ping 10.0.0.1 # traffic sent on SCC
+
+ethrotate
+ When set to "no" U-Boot does not go through all
+ available network interfaces.
+ It just stays at the currently selected interface. When unset or set to
+ anything other than "no", U-Boot does go through all
+ available network interfaces.
+
+netretry
+ When set to "no" each network operation will
+ either succeed or fail without retrying.
+ When set to "once" the network operation will
+ fail when all the available network interfaces
+ are tried once without success.
+ Useful on scripts which control the retry operation
+ themselves.
+
+silent_linux
+ If set then Linux will be told to boot silently, by
+ adding 'console=' to its command line. If "yes" it will be
+ made silent. If "no" it will not be made silent. If
+ unset, then it will be made silent if the U-Boot console
+ is silent.
+
+tftpsrcp
+ If this is set, the value is used for TFTP's
+ UDP source port.
+
+tftpdstp
+ If this is set, the value is used for TFTP's UDP
+ destination port instead of the default port 69.
+
+tftpblocksize
+ Block size to use for TFTP transfers; if not set,
+ we use the TFTP server's default block size
+
+tftptimeout
+ Retransmission timeout for TFTP packets (in milli-
+ seconds, minimum value is 1000 = 1 second). Defines
+ when a packet is considered to be lost so it has to
+ be retransmitted. The default is 5000 = 5 seconds.
+ Lowering this value may make downloads succeed
+ faster in networks with high packet loss rates or
+ with unreliable TFTP servers.
+
+tftptimeoutcountmax
+ maximum count of TFTP timeouts (no
+ unit, minimum value = 0). Defines how many timeouts
+ can happen during a single file transfer before that
+ transfer is aborted. The default is 10, and 0 means
+ 'no timeouts allowed'. Increasing this value may help
+ downloads succeed with high packet loss rates, or with
+ unreliable TFTP servers or client hardware.
+
+tftpwindowsize
+ if this is set, the value is used for TFTP's
+ window size as described by RFC 7440.
+ This means the count of blocks we can receive before
+ sending ack to server.
+
+vlan
+ When set to a value < 4095 the traffic over
+ Ethernet is encapsulated/received over 802.1q
+ VLAN tagged frames.
+
+ Note: This appears not to be used in U-Boot. See `README.VLAN`.
+
+bootpretryperiod
+ Period during which BOOTP/DHCP sends retries.
+ Unsigned value, in milliseconds. If not set, the period will
+ be either the default (28000), or a value based on
+ CONFIG_NET_RETRY_COUNT, if defined. This value has
+ precedence over the valu based on CONFIG_NET_RETRY_COUNT.
+
+memmatches
+ Number of matches found by the last 'ms' command, in hex
+
+memaddr
+ Address of the last match found by the 'ms' command, in hex,
+ or 0 if none
+
+mempos
+ Index position of the last match found by the 'ms' command,
+ in units of the size (.b, .w, .l) of the search
+
+zbootbase
+ (x86 only) Base address of the bzImage 'setup' block
+
+zbootaddr
+ (x86 only) Address of the loaded bzImage, typically
+ BZIMAGE_LOAD_ADDR which is 0x100000
+
+
+Image locations
+---------------
+
+The following image location variables contain the location of images
+used in booting. The "Image" column gives the role of the image and is
+not an environment variable name. The other columns are environment
+variable names. "File Name" gives the name of the file on a TFTP
+server, "RAM Address" gives the location in RAM the image will be
+loaded to, and "Flash Location" gives the image's address in NOR
+flash or offset in NAND flash.
+
+*Note* - these variables don't have to be defined for all boards, some
+boards currently use other variables for these purposes, and some
+boards use these variables for other purposes.
+
+Also note that most of these variables are just a commonly used set of variable
+names, used in some other variable definitions, but are not hard-coded anywhere
+in U-Boot code.
+
+================= ============== ================ ==============
+Image File Name RAM Address Flash Location
+================= ============== ================ ==============
+u-boot u-boot u-boot_addr_r u-boot_addr
+Linux kernel bootfile kernel_addr_r kernel_addr
+device tree blob fdtfile fdt_addr_r fdt_addr
+ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr
+================= ============== ================ ==============
+
+
+Automatically updated variables
+-------------------------------
+
+The following environment variables may be used and automatically
+updated by the network boot commands ("bootp" and "rarpboot"),
+depending the information provided by your boot server:
+
+========= ===================================================
+Variable Notes
+========= ===================================================
+bootfile see above
+dnsip IP address of your Domain Name Server
+dnsip2 IP address of your secondary Domain Name Server
+gatewayip IP address of the Gateway (Router) to use
+hostname Target hostname
+ipaddr See above
+netmask Subnet Mask
+rootpath Pathname of the root filesystem on the NFS server
+serverip see above
+========= ===================================================
+
+
+Special environment variables
+-----------------------------
+
+There are two special Environment Variables:
+
+serial#
+ contains hardware identification information such as type string and/or
+ serial number
+ethaddr
+ Ethernet address. If CONFIG_REGEX=y, also eth*addr (where * is an integer).
+
+These variables can be set only once (usually during manufacturing of
+the board). U-Boot refuses to delete or overwrite these variables
+once they have been set, unless CONFIG_ENV_OVERWRITE is enabled in the board
+configuration.
+
+Also:
+
+ver
+ Contains the U-Boot version string as printed
+ with the "version" command. This variable is
+ readonly (see CONFIG_VERSION_VARIABLE).
+
+Please note that changes to some configuration parameters may take
+only effect after the next boot (yes, that's just like Windows).
+
+
+External environment file
+-------------------------
+
+The `CONFIG_USE_DEFAULT_ENV_FILE` option provides a way to bypass the
+environment generation in U-Boot. If enabled, then `CONFIG_DEFAULT_ENV_FILE`
+provides the name of a file which is converted into the environment,
+completely bypassing the standard environment variables in `env_default.h`.
+
+The format is the same as accepted by the mkenvimage tool, with lines containing
+key=value pairs. Blank lines and lines beginning with # are ignored.
+
+Future work may unify this feature with the text-based environment, perhaps
+moving the contents of `env_default.h` to a text file.
+
+Implementation
+--------------
+
+See :doc:`../develop/environment` for internal development details.
:maxdepth: 1
dfu
+ environment
fdt_overlays
fit
netconsole
partitions
cmdline
+ environment
Shell commands
--------------
qfw
reset
sbi
+ sf
scp03
setexpr
size
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+:
+
+sf command
+==========
+
+Synopis
+-------
+
+::
+
+ sf probe [[[<bus>:]<cs>] [<hz> [<mode>]]]
+ sf read <addr> <offset>|<partition> <len>
+ sf write <addr> <offset>|<partition> <len>
+ sf erase <offset>|<partition> <len>
+ sf update <addr> <offset>|<partition> <len>
+ sf protect lock|unlock <sector> <len>
+ sf test <offset>|<partition> <len>
+
+Description
+-----------
+
+The *sf* command is used to access SPI flash, supporting read/write/erase and
+a few other functions.
+
+Probe
+-----
+
+The flash must first be probed with *sf probe* before any of the other
+subcommands can be used. All of the parameters are optional:
+
+bus
+ SPI bus number containing the SPI-flash chip, e.g. 0. If you don't know
+ the number, you can use 'dm uclass' to see all the spi devices,
+ and check the value for 'seq' for each one (here 0 and 2)::
+
+ uclass 89: spi
+ 0 spi@0 @ 05484960, seq 0
+ 1 spi@1 @ 05484b40, seq 2
+
+cs
+ SPI chip-select to use for the chip. This is often 0 and can be omitted,
+ but in some cases multiple slaves are attached to a SPI controller,
+ selected by a chip-select line for each one.
+
+hz
+ Speed of the SPI bus in hertz. This normally defaults to 100000, i.e.
+ 100KHz, which is very slow. Note that if the device exists in the
+ device tree, there might be a speed provided there, in which case this
+ setting is ignored.
+
+mode
+ SPI mode to use:
+
+ ===== ================
+ Mode Meaning
+ ===== ================
+ 0 CPOL=0, CPHA=0
+ 1 CPOL=0, CPHA=1
+ 2 CPOL=1, CPHA=0
+ 3 CPOL=1, CPHA=1
+ ===== ================
+
+ Clock phase (CPHA) 0 means that data is transferred (sampled) on the
+ first clock edge; 1 means the second.
+
+ Clock polarity (CPOL) controls the idle state of the clock, 0 for low,
+ 1 for high.
+ The active state is the opposite of idle.
+
+ You may find this `SPI documentation`_ useful.
+
+Parameters for other subcommands (described below) are as follows:
+
+addr
+ Memory address to start transfer
+
+offset
+ Flash offset to start transfer
+
+partition
+ If the parameter is not numeric, it is assumed to be a partition
+ description in the format <dev_type><dev_num>,<part_num> which is not
+ covered here. This requires CONFIG_CMD_MTDPARTS.
+
+len
+ Number of bytes to transfer
+
+Read
+~~~~
+
+Use *sf read* to read from SPI flash to memory. The read will fail if an
+attempt is made to read past the end of the flash.
+
+
+Write
+~~~~~
+
+Use *sf write* to write from memory to SPI flash. The SPI flash should be
+erased first, since otherwise the result is undefined.
+
+The write will fail if an attempt is made to read past the end of the flash.
+
+
+Erase
+~~~~~
+
+Use *sf erase* to erase a region of SPI flash. The erase will fail if any part
+of the region to be erased is protected or lies past the end of the flash. It
+may also fail if the start offset or length are not aligned to an erase region
+(e.g. 256 bytes).
+
+
+Update
+~~~~~~
+
+Use *sf update* to automatically erase and update a region of SPI flash from
+memory. This works a sector at a time (typical 4KB or 64KB). For each
+sector it first checks if the sector already has the right data. If so it is
+skipped. If not, the sector is erased and the new data written. Note that if
+the length is not a multiple of the erase size, the space after the data in
+the last sector will be erased. If the offset does not start at the beginning
+of an erase block, the operation will fail.
+
+Speed statistics are shown including the number of bytes that were already
+correct.
+
+
+Protect
+~~~~~~~
+
+SPI-flash chips often have a protection feature where the chip is split up into
+regions which can be locked or unlocked. With *sf protect* it is possible to
+change these settings, if supported by the driver.
+
+lock|unlock
+ Selects whether to lock or unlock the sectors
+
+<sector>
+ Start sector number to lock/unlock. This may be the byte offset or some
+ other value, depending on the chip.
+
+<len>
+ Number of bytes to lock/unlock
+
+
+Test
+~~~~
+
+A convenient and fast *sf test* subcommand provides a way to check that SPI
+flash is working as expected. This works in four stages:
+
+ * erase - erases the entire region
+ * check - checks that the region is erased
+ * write - writes a test pattern to the region, consisting of the U-Boot code
+ * read - reads back the test pattern to check that it was written correctly
+
+Memory is allocated for two buffers, each <len> bytes in size. At typical
+size is 64KB to 1MB. The offset and size must be aligned to an erase boundary.
+
+Note that this test will fail if any part of the SPI flash is write-protected.
+
+
+Examples
+--------
+
+This first example uses sandbox::
+
+ => sf probe
+ SF: Detected m25p16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+ => sf read 1000 1100 80000
+ device 0 offset 0x1100, size 0x80000
+ SF: 524288 bytes @ 0x1100 Read: OK
+ => md 1000
+ 00001000: edfe0dd0 f33a0000 78000000 84250000 ......:....x..%.
+ 00001010: 28000000 11000000 10000000 00000000 ...(............
+ 00001020: 6f050000 0c250000 00000000 00000000 ...o..%.........
+ 00001030: 00000000 00000000 00000000 00000000 ................
+ 00001040: 00000000 00000000 00000000 00000000 ................
+ 00001050: 00000000 00000000 00000000 00000000 ................
+ 00001060: 00000000 00000000 00000000 00000000 ................
+ 00001070: 00000000 00000000 01000000 00000000 ................
+ 00001080: 03000000 04000000 00000000 01000000 ................
+ 00001090: 03000000 04000000 0f000000 01000000 ................
+ 000010a0: 03000000 08000000 1b000000 646e6173 ............sand
+ 000010b0: 00786f62 03000000 08000000 21000000 box............!
+ 000010c0: 646e6173 00786f62 01000000 61696c61 sandbox.....alia
+ 000010d0: 00736573 03000000 07000000 2c000000 ses............,
+ 000010e0: 6332692f 00003040 03000000 07000000 /i2c@0..........
+ 000010f0: 31000000 6963702f 00003040 03000000 ...1/pci@0......
+ => sf erase 0 80000
+ SF: 524288 bytes @ 0x0 Erased: OK
+ => sf read 1000 1100 80000
+ device 0 offset 0x1100, size 0x80000
+ SF: 524288 bytes @ 0x1100 Read: OK
+ => md 1000
+ 00001000: ffffffff ffffffff ffffffff ffffffff ................
+ 00001010: ffffffff ffffffff ffffffff ffffffff ................
+ 00001020: ffffffff ffffffff ffffffff ffffffff ................
+ 00001030: ffffffff ffffffff ffffffff ffffffff ................
+ 00001040: ffffffff ffffffff ffffffff ffffffff ................
+ 00001050: ffffffff ffffffff ffffffff ffffffff ................
+ 00001060: ffffffff ffffffff ffffffff ffffffff ................
+ 00001070: ffffffff ffffffff ffffffff ffffffff ................
+ 00001080: ffffffff ffffffff ffffffff ffffffff ................
+ 00001090: ffffffff ffffffff ffffffff ffffffff ................
+ 000010a0: ffffffff ffffffff ffffffff ffffffff ................
+ 000010b0: ffffffff ffffffff ffffffff ffffffff ................
+ 000010c0: ffffffff ffffffff ffffffff ffffffff ................
+ 000010d0: ffffffff ffffffff ffffffff ffffffff ................
+ 000010e0: ffffffff ffffffff ffffffff ffffffff ................
+ 000010f0: ffffffff ffffffff ffffffff ffffffff ................
+
+This second example is running on coral, an x86 Chromebook::
+
+ => sf probe
+ SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+ => sf erase 300000 80000
+ SF: 524288 bytes @ 0x300000 Erased: OK
+ => sf update 1110000 300000 80000
+ device 0 offset 0x300000, size 0x80000
+ 524288 bytes written, 0 bytes skipped in 0.457s, speed 1164578 B/s
+
+ # This does nothing as the flash is already updated
+ => sf update 1110000 300000 80000
+ device 0 offset 0x300000, size 0x80000
+ 0 bytes written, 524288 bytes skipped in 0.196s, speed 2684354 B/s
+ => sf test 00000 80000 # try a protected region
+ SPI flash test:
+ Erase failed (err = -5)
+ Test failed
+ => sf test 800000 80000
+ SPI flash test:
+ 0 erase: 18 ticks, 28444 KiB/s 227.552 Mbps
+ 1 check: 192 ticks, 2666 KiB/s 21.328 Mbps
+ 2 write: 227 ticks, 2255 KiB/s 18.040 Mbps
+ 3 read: 189 ticks, 2708 KiB/s 21.664 Mbps
+ Test passed
+ 0 erase: 18 ticks, 28444 KiB/s 227.552 Mbps
+ 1 check: 192 ticks, 2666 KiB/s 21.328 Mbps
+ 2 write: 227 ticks, 2255 KiB/s 18.040 Mbps
+ 3 read: 189 ticks, 2708 KiB/s 21.664 Mbps
+
+
+.. _SPI documentation:
+ https://en.wikipedia.org/wiki/Serial_Peripheral_Interface
#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-#ifndef CONFIG_SYS_ATA_PORT_ADDR
-#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
-#endif
-
#ifdef CONFIG_IDE_RESET
extern void ide_set_reset(int idereset);
__weak void ide_outb(int dev, int port, unsigned char val)
{
debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
- dev, port, val,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+ dev, port, val, ATA_CURR_BASE(dev) + port);
#if defined(CONFIG_IDE_AHB)
if (port) {
outb(val, (ATA_CURR_BASE(dev)));
}
#else
- outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+ outb(val, ATA_CURR_BASE(dev) + port);
#endif
}
#if defined(CONFIG_IDE_AHB)
val = ide_read_register(dev, port);
#else
- val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+ val = inb(ATA_CURR_BASE(dev) + port);
#endif
debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
- dev, port,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+ dev, port, ATA_CURR_BASE(dev) + port, val);
return val;
}
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_BLK
-static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES];
+static struct host_block_dev host_devices[SANDBOX_HOST_MAX_DEVICES];
static struct host_block_dev *find_host_device(int dev)
{
- if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES)
+ if (dev >= 0 && dev < SANDBOX_HOST_MAX_DEVICES)
return &host_devices[dev];
return NULL;
U_BOOT_LEGACY_BLK(sandbox_host) = {
.if_typename = "host",
.if_type = IF_TYPE_HOST,
- .max_devs = CONFIG_HOST_MAX_DEVICES,
+ .max_devs = SANDBOX_HOST_MAX_DEVICES,
.get_dev = host_get_dev_err,
};
#endif
return 0;
}
+static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ /* share the same reset control bit with ACRY */
+ reset_bit = BIT(ASPEED_RESET_HACE);
+ clkgate_bit = SCU_CLKGATE1_HACE;
+
+ /*
+ * we don't do reset assertion here as HACE
+ * shares the same reset control with ACRY
+ */
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(20);
+ writel(reset_bit, &scu->modrst_clr1);
+
+ return 0;
+}
+
+static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ /* same reset control bit with HACE */
+ reset_bit = BIT(ASPEED_RESET_HACE);
+ clkgate_bit = SCU_CLKGATE1_ACRY;
+
+ /*
+ * we don't do reset assertion here as HACE
+ * shares the same reset control with ACRY
+ */
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(20);
+ writel(reset_bit, &scu->modrst_clr1);
+
+ return 0;
+}
+
static int ast2600_clk_enable(struct clk *clk)
{
struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
case ASPEED_CLK_GATE_USBPORT2CLK:
ast2600_enable_usbbhclk(priv->scu);
break;
+ case ASPEED_CLK_GATE_YCLK:
+ ast2600_enable_haceclk(priv->scu);
+ break;
+ case ASPEED_CLK_GATE_RSACLK:
+ ast2600_enable_rsaclk(priv->scu);
+ break;
default:
pr_err("can't enable clk\n");
return -ENOENT;
/*
* Copyright (C) 2019-2020 Linaro Limited
*/
+
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
if (ret)
return log_msg_ret("child unbind", ret);
+ ret = uclass_pre_unbind_device(dev);
+ if (ret)
+ return log_msg_ret("uc", ret);
if (dev_get_flags(dev) & DM_FLAG_ALLOC_PDATA) {
free(dev_get_plat(dev));
dev_set_plat(dev, NULL);
}
if (dev->parent) {
size = dev->parent->driver->per_child_auto;
- if (!size) {
- size = dev->parent->uclass->uc_drv->
- per_child_auto;
- }
+ if (!size)
+ size = dev->parent->uclass->uc_drv->per_child_auto;
if (size) {
free(dev_get_parent_priv(dev));
dev_set_parent_priv(dev, NULL);
* is set just above. However, the PCI bus' probe() method and
* associated uclass methods have not yet been called.
*/
- if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
- pinctrl_select_state(dev, "default");
+ if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL) {
+ ret = pinctrl_select_state(dev, "default");
+ if (ret && ret != -ENOSYS)
+ log_debug("Device '%s' failed to configure default pinctrl: %d (%s)\n",
+ dev->name, ret, errno_str(ret));
+ }
if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
(device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
if (ret)
goto fail_uclass;
- if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL)
- pinctrl_select_state(dev, "default");
+ if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL) {
+ ret = pinctrl_select_state(dev, "default");
+ if (ret && ret != -ENOSYS)
+ log_debug("Device '%s' failed to configure default pinctrl: %d (%s)\n",
+ dev->name, ret, errno_str(ret));
+ }
return 0;
fail_uclass:
return -ENODEV;
}
-int device_find_child_by_name(const struct udevice *parent, const char *name,
- struct udevice **devp)
+int device_find_child_by_namelen(const struct udevice *parent, const char *name,
+ int len, struct udevice **devp)
{
struct udevice *dev;
*devp = NULL;
list_for_each_entry(dev, &parent->child_head, sibling_node) {
- if (!strcmp(dev->name, name)) {
+ if (!strncmp(dev->name, name, len) &&
+ strlen(dev->name) == len) {
*devp = dev;
return 0;
}
return -ENODEV;
}
+int device_find_child_by_name(const struct udevice *parent, const char *name,
+ struct udevice **devp)
+{
+ return device_find_child_by_namelen(parent, name, strlen(name), devp);
+}
+
int device_first_child_err(struct udevice *parent, struct udevice **devp)
{
struct udevice *dev;
const int n_ents = ll_entry_count(struct driver_info, driver_info);
bool missing_parent = false;
int result = 0;
- uint idx;
+ int idx;
/*
* Do one iteration through the driver_info records. For of-platdata,
* @propname: name of the property to be searched.
* @out_strs: output array of string pointers.
* @sz: number of array elements to read.
- * @skip: Number of strings to skip over at beginning of list.
+ * @skip: Number of strings to skip over at beginning of list (cannot be
+ * negative)
*
* Don't call this function directly. It is a utility helper for the
* of_property_read_string*() family of functions.
return true;
}
+
+bool ofnode_eth_uses_inband_aneg(ofnode eth_node)
+{
+ bool inband_aneg = false;
+ const char *managed;
+
+ managed = ofnode_read_string(eth_node, "managed");
+ if (managed && !strcmp(managed, "in-band-status"))
+ inband_aneg = true;
+
+ return inband_aneg;
+}
}
}
+int ofnode_read_string_list(ofnode node, const char *property,
+ const char ***listp)
+{
+ const char **prop;
+ int count;
+ int i;
+
+ *listp = NULL;
+ count = ofnode_read_string_count(node, property);
+ if (count < 0)
+ return count;
+ if (!count)
+ return 0;
+
+ prop = calloc(count + 1, sizeof(char *));
+ if (!prop)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++)
+ ofnode_read_string_index(node, property, i, &prop[i]);
+ prop[count] = NULL;
+ *listp = prop;
+
+ return count;
+}
+
static void ofnode_from_fdtdec_phandle_args(struct fdtdec_phandle_args *in,
struct ofnode_phandle_args *out)
{
return ofnode_read_string_count(dev_ofnode(dev), propname);
}
+int dev_read_string_list(const struct udevice *dev, const char *propname,
+ const char ***listp)
+{
+ return ofnode_read_string_list(dev_ofnode(dev), propname, listp);
+}
+
int dev_read_phandle_with_args(const struct udevice *dev, const char *list_name,
const char *cells_name, int cell_count,
int index, struct ofnode_phandle_args *out_args)
uc->priv_ = priv;
}
-enum uclass_id uclass_get_by_name(const char *name)
+enum uclass_id uclass_get_by_name_len(const char *name, int len)
{
int i;
for (i = 0; i < UCLASS_COUNT; i++) {
struct uclass_driver *uc_drv = lists_uclass_lookup(i);
- if (uc_drv && !strcmp(uc_drv->name, name))
+ if (uc_drv && !strncmp(uc_drv->name, name, len))
return i;
}
return UCLASS_INVALID;
}
+enum uclass_id uclass_get_by_name(const char *name)
+{
+ return uclass_get_by_name_len(name, strlen(name));
+}
+
int dev_get_uclass_index(struct udevice *dev, struct uclass **ucp)
{
struct udevice *iter;
}
#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
-int uclass_unbind_device(struct udevice *dev)
+int uclass_pre_unbind_device(struct udevice *dev)
{
struct uclass *uc;
int ret;
return ret;
}
+ return 0;
+}
+
+int uclass_unbind_device(struct udevice *dev)
+{
list_del(&dev->uclass_node);
+
return 0;
}
#endif
return 0;
}
+int uclass_id_count(enum uclass_id id)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int count = 0;
+
+ uclass_id_foreach_dev(id, dev, uc)
+ count++;
+
+ return count;
+}
+
UCLASS_DRIVER(nop) = {
.id = UCLASS_NOP,
.name = "nop",
source drivers/crypto/fsl/Kconfig
+source drivers/crypto/aspeed/Kconfig
+
endmenu
obj-y += rsa_mod_exp/
obj-y += fsl/
obj-y += hash/
+obj-y += aspeed/
--- /dev/null
+config ASPEED_HACE
+ bool "ASPEED Hash and Crypto Engine"
+ depends on DM_HASH
+ help
+ Select this option to enable a driver for using the SHA engine in
+ the ASPEED BMC SoCs.
+
+ Enabling this allows the use of SHA operations in hardware without
+ requiring the SHA software implementations. It also improves performance
+ and saves code size.
+
+config ASPEED_ACRY
+ bool "ASPEED RSA and ECC Engine"
+ depends on ASPEED_AST2600
+ help
+ Select this option to enable a driver for using the RSA/ECC engine in
+ the ASPEED BMC SoCs.
+
+ Enabling this allows the use of RSA/ECC operations in hardware without requiring the
+ software implementations. It also improves performance and saves code size.
--- /dev/null
+obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o
+obj-$(CONFIG_ASPEED_ACRY) += aspeed_acry.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2021 ASPEED Technology Inc.
+ */
+#include <config.h>
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/fdtaddr.h>
+#include <linux/delay.h>
+#include <u-boot/rsa-mod-exp.h>
+
+/* ACRY register offsets */
+#define ACRY_CTRL1 0x00
+#define ACRY_CTRL1_RSA_DMA BIT(1)
+#define ACRY_CTRL1_RSA_START BIT(0)
+#define ACRY_CTRL2 0x44
+#define ACRY_CTRL3 0x48
+#define ACRY_CTRL3_SRAM_AHB_ACCESS BIT(8)
+#define ACRY_CTRL3_ECC_RSA_MODE_MASK GENMASK(5, 4)
+#define ACRY_CTRL3_ECC_RSA_MODE_SHIFT 4
+#define ACRY_DMA_DRAM_SADDR 0x4c
+#define ACRY_DMA_DMEM_TADDR 0x50
+#define ACRY_DMA_DMEM_TADDR_LEN_MASK GENMASK(15, 0)
+#define ACRY_DMA_DMEM_TADDR_LEN_SHIFT 0
+#define ACRY_RSA_PARAM 0x58
+#define ACRY_RSA_PARAM_EXP_MASK GENMASK(31, 16)
+#define ACRY_RSA_PARAM_EXP_SHIFT 16
+#define ACRY_RSA_PARAM_MOD_MASK GENMASK(15, 0)
+#define ACRY_RSA_PARAM_MOD_SHIFT 0
+#define ACRY_RSA_INT_EN 0x3f8
+#define ACRY_RSA_INT_EN_RSA_READY BIT(2)
+#define ACRY_RSA_INT_EN_RSA_CMPLT BIT(1)
+#define ACRY_RSA_INT_STS 0x3fc
+#define ACRY_RSA_INT_STS_RSA_READY BIT(2)
+#define ACRY_RSA_INT_STS_RSA_CMPLT BIT(1)
+
+/* misc. constant */
+#define ACRY_ECC_MODE 2
+#define ACRY_RSA_MODE 3
+#define ACRY_CTX_BUFSZ 0x600
+
+struct aspeed_acry {
+ phys_addr_t base;
+ phys_addr_t sram_base; /* internal sram */
+ struct clk clk;
+};
+
+static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
+ struct key_prop *prop, uint8_t *out)
+{
+ int i, j;
+ u8 *ctx;
+ u8 *ptr;
+ u32 reg;
+ struct aspeed_acry *acry = dev_get_priv(dev);
+
+ ctx = memalign(16, ACRY_CTX_BUFSZ);
+ if (!ctx)
+ return -ENOMEM;
+
+ memset(ctx, 0, ACRY_CTX_BUFSZ);
+
+ ptr = (u8 *)prop->public_exponent;
+ for (i = prop->exp_len - 1, j = 0; i >= 0; --i) {
+ ctx[j] = ptr[i];
+ j++;
+ j = (j % 16) ? j : j + 32;
+ }
+
+ ptr = (u8 *)prop->modulus;
+ for (i = (prop->num_bits >> 3) - 1, j = 0; i >= 0; --i) {
+ ctx[j + 16] = ptr[i];
+ j++;
+ j = (j % 16) ? j : j + 32;
+ }
+
+ ptr = (u8 *)sig;
+ for (i = sig_len - 1, j = 0; i >= 0; --i) {
+ ctx[j + 32] = ptr[i];
+ j++;
+ j = (j % 16) ? j : j + 32;
+ }
+
+ writel((u32)ctx, acry->base + ACRY_DMA_DRAM_SADDR);
+
+ reg = (((prop->exp_len << 3) << ACRY_RSA_PARAM_EXP_SHIFT) & ACRY_RSA_PARAM_EXP_MASK) |
+ ((prop->num_bits << ACRY_RSA_PARAM_MOD_SHIFT) & ACRY_RSA_PARAM_MOD_MASK);
+ writel(reg, acry->base + ACRY_RSA_PARAM);
+
+ reg = (ACRY_CTX_BUFSZ << ACRY_DMA_DMEM_TADDR_LEN_SHIFT) & ACRY_DMA_DMEM_TADDR_LEN_MASK;
+ writel(reg, acry->base + ACRY_DMA_DMEM_TADDR);
+
+ reg = (ACRY_RSA_MODE << ACRY_CTRL3_ECC_RSA_MODE_SHIFT) & ACRY_CTRL3_ECC_RSA_MODE_MASK;
+ writel(reg, acry->base + ACRY_CTRL3);
+
+ writel(ACRY_CTRL1_RSA_DMA | ACRY_CTRL1_RSA_START, acry->base + ACRY_CTRL1);
+
+ /* polling RSA status */
+ while (1) {
+ reg = readl(acry->base + ACRY_RSA_INT_STS);
+ if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) {
+ writel(reg, ACRY_RSA_INT_STS);
+ break;
+ }
+ udelay(20);
+ }
+
+ /* grant SRAM access permission to CPU */
+ writel(0x0, acry->base + ACRY_CTRL1);
+ writel(ACRY_CTRL3_SRAM_AHB_ACCESS, acry->base + ACRY_CTRL3);
+ udelay(20);
+
+ for (i = (prop->num_bits / 8) - 1, j = 0; i >= 0; --i) {
+ out[i] = readb(acry->sram_base + (j + 32));
+ j++;
+ j = (j % 16) ? j : j + 32;
+ }
+
+ /* return SRAM access permission to ACRY */
+ writel(0, acry->base + ACRY_CTRL3);
+
+ free(ctx);
+
+ return 0;
+}
+
+static int aspeed_acry_probe(struct udevice *dev)
+{
+ struct aspeed_acry *acry = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &acry->clk);
+ if (ret < 0) {
+ debug("Can't get clock for %s: %d\n", dev->name, ret);
+ return ret;
+ }
+
+ ret = clk_enable(&acry->clk);
+ if (ret) {
+ debug("Failed to enable acry clock (%d)\n", ret);
+ return ret;
+ }
+
+ acry->base = devfdt_get_addr_index(dev, 0);
+ if (acry->base == FDT_ADDR_T_NONE) {
+ debug("Failed to get acry base\n");
+ return acry->base;
+ }
+
+ acry->sram_base = devfdt_get_addr_index(dev, 1);
+ if (acry->sram_base == FDT_ADDR_T_NONE) {
+ debug("Failed to get acry SRAM base\n");
+ return acry->sram_base;
+ }
+
+ return ret;
+}
+
+static int aspeed_acry_remove(struct udevice *dev)
+{
+ struct aspeed_acry *acry = dev_get_priv(dev);
+
+ clk_disable(&acry->clk);
+
+ return 0;
+}
+
+static const struct mod_exp_ops aspeed_acry_ops = {
+ .mod_exp = aspeed_acry_mod_exp,
+};
+
+static const struct udevice_id aspeed_acry_ids[] = {
+ { .compatible = "aspeed,ast2600-acry" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_acry) = {
+ .name = "aspeed_acry",
+ .id = UCLASS_MOD_EXP,
+ .of_match = aspeed_acry_ids,
+ .probe = aspeed_acry_probe,
+ .remove = aspeed_acry_remove,
+ .priv_auto = sizeof(struct aspeed_acry),
+ .ops = &aspeed_acry_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2021 ASPEED Technology Inc.
+ */
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <log.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <watchdog.h>
+#include <u-boot/hash.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/iopoll.h>
+
+/* register offsets*/
+#define HACE_STS 0x1C
+#define HACE_HASH_DATA_OVF BIT(23)
+#define HACE_HASH_INT BIT(9)
+#define HACE_HASH_BUSY BIT(0)
+#define HACE_HASH_DATA 0x20
+#define HACE_HASH_DIGEST 0x24
+#define HACE_HASH_HMAC_KEY 0x28
+#define HACE_HASH_DATA_LEN 0x2C
+#define HACE_HASH_CMD 0x30
+#define HACE_HASH_MODE_ACCUM BIT(8)
+#define HACE_HASH_ALGO_SHA1 BIT(5)
+#define HACE_HASH_ALGO_SHA256 (BIT(6) | BIT(4))
+#define HACE_HASH_ALGO_SHA384 (BIT(10) | BIT(6) | BIT(5))
+#define HACE_HASH_ALGO_SHA512 (BIT(6) | BIT(5))
+#define HACE_HASH_SHA_BE_EN BIT(3)
+
+/* buffer size based on SHA-512 need*/
+#define HASH_BLOCK_BUFSZ 128
+#define HASH_DIGEST_BUFSZ 64
+
+struct aspeed_hace_ctx {
+ uint8_t digest[HASH_DIGEST_BUFSZ];
+
+ uint32_t cmd;
+ enum HASH_ALGO algo;
+
+ uint32_t blk_size;
+ uint32_t pad_size;
+ uint64_t total[2];
+
+ uint8_t buf[HASH_BLOCK_BUFSZ];
+ uint32_t buf_cnt;
+} __aligned((8));
+
+struct aspeed_hace {
+ phys_addr_t base;
+ struct clk clk;
+};
+
+static const uint32_t iv_sha1[8] = {
+ 0x01234567, 0x89abcdef, 0xfedcba98, 0x76543210,
+ 0xf0e1d2c3, 0, 0, 0
+};
+
+static const uint32_t iv_sha256[8] = {
+ 0x67e6096a, 0x85ae67bb, 0x72f36e3c, 0x3af54fa5,
+ 0x7f520e51, 0x8c68059b, 0xabd9831f, 0x19cde05bUL
+};
+
+static const uint32_t iv_sha384[16] = {
+ 0x5d9dbbcb, 0xd89e05c1, 0x2a299a62, 0x07d57c36,
+ 0x5a015991, 0x17dd7030, 0xd8ec2f15, 0x39590ef7,
+ 0x67263367, 0x310bc0ff, 0x874ab48e, 0x11155868,
+ 0x0d2e0cdb, 0xa78ff964, 0x1d48b547, 0xa44ffabeUL
+};
+
+static const uint32_t iv_sha512[16] = {
+ 0x67e6096a, 0x08c9bcf3, 0x85ae67bb, 0x3ba7ca84,
+ 0x72f36e3c, 0x2bf894fe, 0x3af54fa5, 0xf1361d5f,
+ 0x7f520e51, 0xd182e6ad, 0x8c68059b, 0x1f6c3e2b,
+ 0xabd9831f, 0x6bbd41fb, 0x19cde05b, 0x79217e13UL
+};
+
+static int aspeed_hace_wait_completion(uint32_t reg, uint32_t flag, int timeout_us)
+{
+ uint32_t val;
+
+ return readl_poll_timeout(reg, val, (val & flag) == flag, timeout_us);
+}
+
+static int aspeed_hace_process(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen)
+{
+ struct aspeed_hace *hace = dev_get_priv(dev);
+ struct aspeed_hace_ctx *hace_ctx = (struct aspeed_hace_ctx *)ctx;
+ uint32_t sts = readl(hace->base + HACE_STS);
+
+ if (sts & HACE_HASH_BUSY) {
+ debug("HACE engine busy\n");
+ return -EBUSY;
+ }
+
+ writel(HACE_HASH_INT, hace->base + HACE_STS);
+
+ writel((uint32_t)ibuf, hace->base + HACE_HASH_DATA);
+ writel((uint32_t)hace_ctx->digest, hace->base + HACE_HASH_DIGEST);
+ writel((uint32_t)hace_ctx->digest, hace->base + HACE_HASH_HMAC_KEY);
+ writel(ilen, hace->base + HACE_HASH_DATA_LEN);
+ writel(hace_ctx->cmd, hace->base + HACE_HASH_CMD);
+
+ return aspeed_hace_wait_completion(hace->base + HACE_STS,
+ HACE_HASH_INT,
+ 1000 + (ilen >> 3));
+}
+
+static int aspeed_hace_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp)
+{
+ struct aspeed_hace_ctx *hace_ctx;
+
+ hace_ctx = memalign(8, sizeof(struct aspeed_hace_ctx));
+ if (!hace_ctx)
+ return -ENOMEM;
+
+ memset(hace_ctx, 0, sizeof(struct aspeed_hace_ctx));
+
+ hace_ctx->algo = algo;
+ hace_ctx->cmd = HACE_HASH_MODE_ACCUM | HACE_HASH_SHA_BE_EN;
+
+ switch (algo) {
+ case HASH_ALGO_SHA1:
+ hace_ctx->blk_size = 64;
+ hace_ctx->pad_size = 8;
+ hace_ctx->cmd |= HACE_HASH_ALGO_SHA1;
+ memcpy(hace_ctx->digest, iv_sha1, sizeof(iv_sha1));
+ break;
+ case HASH_ALGO_SHA256:
+ hace_ctx->blk_size = 64;
+ hace_ctx->pad_size = 8;
+ hace_ctx->cmd |= HACE_HASH_ALGO_SHA256;
+ memcpy(hace_ctx->digest, iv_sha256, sizeof(iv_sha256));
+ break;
+ case HASH_ALGO_SHA384:
+ hace_ctx->blk_size = 128;
+ hace_ctx->pad_size = 16;
+ hace_ctx->cmd |= HACE_HASH_ALGO_SHA384;
+ memcpy(hace_ctx->digest, iv_sha384, sizeof(iv_sha384));
+ break;
+ case HASH_ALGO_SHA512:
+ hace_ctx->blk_size = 128;
+ hace_ctx->pad_size = 16;
+ hace_ctx->cmd |= HACE_HASH_ALGO_SHA512;
+ memcpy(hace_ctx->digest, iv_sha512, sizeof(iv_sha512));
+ break;
+ default:
+ debug("Unsupported hash algorithm '%s'\n", hash_algo_name(algo));
+ goto free_n_out;
+ };
+
+ *ctxp = hace_ctx;
+
+ return 0;
+
+free_n_out:
+ free(hace_ctx);
+
+ return -EINVAL;
+}
+
+static int aspeed_hace_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen)
+{
+ int rc;
+ uint32_t left, fill;
+ struct aspeed_hace_ctx *hace_ctx = ctx;
+
+ left = hace_ctx->total[0] & (hace_ctx->blk_size - 1);
+ fill = hace_ctx->blk_size - left;
+
+ hace_ctx->total[0] += ilen;
+ if (hace_ctx->total[0] < ilen)
+ hace_ctx->total[1]++;
+
+ if (left && ilen >= fill) {
+ memcpy(hace_ctx->buf + left, ibuf, fill);
+ rc = aspeed_hace_process(dev, ctx, hace_ctx->buf, hace_ctx->blk_size);
+ if (rc) {
+ debug("failed to process hash, rc=%d\n", rc);
+ return rc;
+ }
+ ilen -= fill;
+ ibuf += fill;
+ left = 0;
+ }
+
+ while (ilen >= hace_ctx->blk_size) {
+ rc = aspeed_hace_process(dev, ctx, ibuf, hace_ctx->blk_size);
+ if (rc) {
+ debug("failed to process hash, rc=%d\n", rc);
+ return rc;
+ }
+
+ ibuf += hace_ctx->blk_size;
+ ilen -= hace_ctx->blk_size;
+ }
+
+ if (ilen)
+ memcpy(hace_ctx->buf + left, ibuf, ilen);
+
+ return 0;
+}
+
+static int aspeed_hace_finish(struct udevice *dev, void *ctx, void *obuf)
+{
+ int rc = 0;
+ uint8_t pad[HASH_BLOCK_BUFSZ * 2];
+ uint32_t last, padn;
+ uint64_t ibits_h, ibits_l;
+ uint64_t ibits_be_h, ibits_be_l;
+ struct aspeed_hace_ctx *hace_ctx = ctx;
+
+ memset(pad, 0, sizeof(pad));
+ pad[0] = 0x80;
+
+ ibits_h = (hace_ctx->total[0] >> 61) | (hace_ctx->total[1] << 3);
+ ibits_be_h = cpu_to_be64(ibits_h);
+
+ ibits_l = (hace_ctx->total[0] << 3);
+ ibits_be_l = cpu_to_be64(ibits_l);
+
+ last = hace_ctx->total[0] & (hace_ctx->blk_size - 1);
+
+ switch (hace_ctx->algo) {
+ case HASH_ALGO_SHA1:
+ case HASH_ALGO_SHA256:
+ padn = (last < 56) ? (56 - last) : (120 - last);
+
+ rc = aspeed_hace_update(dev, ctx, pad, padn);
+ if (rc) {
+ debug("failed to append padding, rc=%d\n", rc);
+ goto free_n_out;
+ }
+
+ rc = aspeed_hace_update(dev, ctx, &ibits_be_l, sizeof(ibits_be_l));
+ if (rc) {
+ debug("failed to append message bits length, rc=%d\n", rc);
+ goto free_n_out;
+ }
+
+ break;
+ case HASH_ALGO_SHA384:
+ case HASH_ALGO_SHA512:
+ padn = (last < 112) ? (112 - last) : (240 - last);
+
+ rc = aspeed_hace_update(dev, ctx, pad, padn);
+ if (rc) {
+ debug("failed to append padding, rc=%d\n", rc);
+ goto free_n_out;
+ }
+
+ rc = aspeed_hace_update(dev, ctx, &ibits_be_h, sizeof(ibits_be_h)) |
+ aspeed_hace_update(dev, ctx, &ibits_be_l, sizeof(ibits_be_l));
+ if (rc) {
+ debug("failed to append message bits length, rc=%d\n", rc);
+ goto free_n_out;
+ }
+
+ break;
+ default:
+ rc = -EINVAL;
+ break;
+ }
+
+ memcpy(obuf, hace_ctx->digest, hash_algo_digest_size(hace_ctx->algo));
+
+free_n_out:
+ free(ctx);
+
+ return rc;
+}
+
+static int aspeed_hace_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf, uint32_t chunk_sz)
+{
+ int rc;
+ void *ctx;
+ const void *cur, *end;
+ uint32_t chunk;
+
+ rc = aspeed_hace_init(dev, algo, &ctx);
+ if (rc)
+ return rc;
+
+ if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) {
+ cur = ibuf;
+ end = ibuf + ilen;
+
+ while (cur < end) {
+ chunk = end - cur;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+
+ rc = aspeed_hace_update(dev, ctx, cur, chunk);
+ if (rc)
+ return rc;
+
+ cur += chunk;
+ WATCHDOG_RESET();
+ }
+ } else {
+ rc = aspeed_hace_update(dev, ctx, ibuf, ilen);
+ if (rc)
+ return rc;
+ }
+
+ rc = aspeed_hace_finish(dev, ctx, obuf);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static int aspeed_hace_digest(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf)
+{
+ /* re-use the watchdog version with input length as the chunk_sz */
+ return aspeed_hace_digest_wd(dev, algo, ibuf, ilen, obuf, ilen);
+}
+
+static int aspeed_hace_probe(struct udevice *dev)
+{
+ int rc;
+ struct aspeed_hace *hace = dev_get_priv(dev);
+
+ rc = clk_get_by_index(dev, 0, &hace->clk);
+ if (rc < 0) {
+ debug("cannot get clock for %s: %d\n", dev->name, rc);
+ return rc;
+ }
+
+ rc = clk_enable(&hace->clk);
+ if (rc) {
+ debug("cannot enable clock for %s: %d\n", dev->name, rc);
+ return rc;
+ }
+
+ hace->base = devfdt_get_addr(dev);
+
+ return rc;
+}
+
+static int aspeed_hace_remove(struct udevice *dev)
+{
+ struct aspeed_hace *hace = dev_get_priv(dev);
+
+ clk_disable(&hace->clk);
+
+ return 0;
+}
+
+static const struct hash_ops aspeed_hace_ops = {
+ .hash_init = aspeed_hace_init,
+ .hash_update = aspeed_hace_update,
+ .hash_finish = aspeed_hace_finish,
+ .hash_digest_wd = aspeed_hace_digest_wd,
+ .hash_digest = aspeed_hace_digest,
+};
+
+static const struct udevice_id aspeed_hace_ids[] = {
+ { .compatible = "aspeed,ast2600-hace" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_hace) = {
+ .name = "aspeed_hace",
+ .id = UCLASS_HASH,
+ .of_match = aspeed_hace_ids,
+ .ops = &aspeed_hace_ops,
+ .probe = aspeed_hace_probe,
+ .remove = aspeed_hace_remove,
+ .priv_auto = sizeof(struct aspeed_hace),
+ .flags = DM_FLAG_PRE_RELOC,
+};
help
Enable driver for hashing operations in software. Currently
it support multiple hash algorithm including CRC/MD5/SHA.
+
+config HASH_ASPEED
+ bool "Enable Hash with ASPEED hash accelerator"
+ depends on DM_HASH
+ select ASPEED_HACE
+ help
+ Enable this to support HW-assisted hashing operations using ASPEED Hash
+ and Crypto engine - HACE
endif
+menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
+ depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
+
+config SYS_BR0_PRELIM_BOOL
+ bool "Define Bank 0"
+
+config SYS_BR0_PRELIM
+ hex "Preliminary value for BR0"
+ depends on SYS_BR0_PRELIM_BOOL
+
+config SYS_OR0_PRELIM
+ hex "Preliminary value for OR0"
+ depends on SYS_BR0_PRELIM_BOOL
+
+config SYS_BR1_PRELIM_BOOL
+ bool "Define Bank 1"
+
+config SYS_BR1_PRELIM
+ hex "Preliminary value for BR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_OR1_PRELIM
+ hex "Preliminary value for OR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_BR2_PRELIM_BOOL
+ bool "Define Bank 2"
+
+config SYS_BR2_PRELIM
+ hex "Preliminary value for BR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_OR2_PRELIM
+ hex "Preliminary value for OR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_BR3_PRELIM_BOOL
+ bool "Define Bank 3"
+
+config SYS_BR3_PRELIM
+ hex "Preliminary value for BR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_OR3_PRELIM
+ hex "Preliminary value for OR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_BR4_PRELIM_BOOL
+ bool "Define Bank 4"
+
+config SYS_BR4_PRELIM
+ hex "Preliminary value for BR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_OR4_PRELIM
+ hex "Preliminary value for OR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_BR5_PRELIM_BOOL
+ bool "Define Bank 5"
+
+config SYS_BR5_PRELIM
+ hex "Preliminary value for BR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_OR5_PRELIM
+ hex "Preliminary value for OR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_BR6_PRELIM_BOOL
+ bool "Define Bank 6"
+
+config SYS_BR6_PRELIM
+ hex "Preliminary value for BR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_OR6_PRELIM
+ hex "Preliminary value for OR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_BR7_PRELIM_BOOL
+ bool "Define Bank 7"
+
+config SYS_BR7_PRELIM
+ hex "Preliminary value for BR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_OR7_PRELIM
+ hex "Preliminary value for OR7"
+ depends on SYS_BR7_PRELIM_BOOL
+endmenu
+
config SYS_FSL_ERRATUM_A008378
bool
{
struct zynqmp_ipi_msg msg;
int ret;
+ u32 buffer[PAYLOAD_ARG_CNT];
+
+ if (!res)
+ res = buffer;
if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
* firmware API is limited by the SMC call size
*/
u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
+ int ret;
if (api_id == PM_FPGA_LOAD) {
/* Swap addr_hi/low because of incompatibility */
regs[2] = temp;
}
- ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT);
+ ret = ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload,
+ PAYLOAD_ARG_CNT);
+ if (ret)
+ return ret;
#else
return -EPERM;
#endif
bool "Enable SCMI support"
select FIRMWARE
select OF_TRANSLATE
- depends on SANDBOX || DM_MAILBOX || ARM_SMCCC
+ depends on SANDBOX || DM_MAILBOX || ARM_SMCCC || OPTEE
help
System Control and Management Interface (SCMI) is a communication
protocol that defines standard interfaces for power, performance
or a companion host in the CPU system.
Communications between agent (client) and the SCMI server are
- based on message exchange. Messages can be exchange over tranport
+ based on message exchange. Messages can be exchanged over transport
channels as a mailbox device or an Arm SMCCC service with some
piece of identified shared memory.
+
+config SCMI_AGENT_MAILBOX
+ bool "Enable SCMI agent mailbox"
+ depends on SCMI_FIRMWARE && DM_MAILBOX
+ default y
+ help
+ Enable the SCMI communication channel based on mailbox
+ for compatible "arm,scmi".
+
+config SCMI_AGENT_SMCCC
+ bool "Enable SCMI agent SMCCC"
+ depends on SCMI_FIRMWARE && ARM_SMCCC
+ default y
+ help
+ Enable the SCMI communication channel based on Arm SMCCC service for
+ compatible "arm,scmi-smc".
+
+config SCMI_AGENT_OPTEE
+ bool "Enable SCMI agent OP-TEE"
+ depends on SCMI_FIRMWARE && OPTEE
+ default y
+ help
+ Enable the SCMI communication channel based on OP-TEE transport
+ for compatible "linaro,scmi-optee".
obj-y += scmi_agent-uclass.o
obj-y += smt.o
-obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o
-obj-$(CONFIG_DM_MAILBOX) += mailbox_agent.o
+obj-$(CONFIG_SCMI_AGENT_SMCCC) += smccc_agent.o
+obj-$(CONFIG_SCMI_AGENT_MAILBOX) += mailbox_agent.o
+obj-$(CONFIG_SCMI_AGENT_OPTEE) += optee_agent.o
obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o
static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg)
{
- struct scmi_mbox_channel *chan = dev_get_priv(dev);
+ struct scmi_mbox_channel *chan = dev_get_plat(dev);
int ret;
ret = scmi_write_msg_to_smt(dev, &chan->smt, msg);
return ret;
}
-int scmi_mbox_probe(struct udevice *dev)
+int scmi_mbox_of_to_plat(struct udevice *dev)
{
- struct scmi_mbox_channel *chan = dev_get_priv(dev);
+ struct scmi_mbox_channel *chan = dev_get_plat(dev);
int ret;
chan->timeout_us = TIMEOUT_US_10MS;
ret = mbox_get_by_index(dev, 0, &chan->mbox);
if (ret) {
dev_err(dev, "Failed to find mailbox: %d\n", ret);
- goto out;
+ return ret;
}
ret = scmi_dt_get_smt_buffer(dev, &chan->smt);
if (ret)
dev_err(dev, "Failed to get shm resources: %d\n", ret);
-out:
- if (ret)
- devm_kfree(dev, chan);
-
return ret;
}
.name = "scmi-over-mailbox",
.id = UCLASS_SCMI_AGENT,
.of_match = scmi_mbox_ids,
- .priv_auto = sizeof(struct scmi_mbox_channel),
- .probe = scmi_mbox_probe,
+ .plat_auto = sizeof(struct scmi_mbox_channel),
+ .of_to_plat = scmi_mbox_of_to_plat,
.ops = &scmi_mbox_ops,
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 Linaro Limited.
+ */
+
+#define LOG_CATEGORY UCLASS_SCMI_AGENT
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <string.h>
+#include <tee.h>
+#include <asm/types.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/arm-smccc.h>
+#include <linux/bug.h>
+#include <linux/compat.h>
+
+#include "smt.h"
+
+#define SCMI_SHM_SIZE 128
+
+/**
+ * struct scmi_optee_channel - Description of an SCMI OP-TEE transport
+ * @channel_id: Channel identifier
+ * @smt: Shared memory buffer with synchronisation protocol
+ * @dyn_shm: True if using dynamically allocated shared memory
+ */
+struct scmi_optee_channel {
+ unsigned int channel_id;
+ struct scmi_smt smt;
+ bool dyn_shm;
+};
+
+/**
+ * struct channel_session - Aggreates SCMI service session context references
+ * @tee: OP-TEE device to invoke
+ * @tee_session: OP-TEE session identifier
+ * @tee_shm: Dynamically allocated OP-TEE shared memory, or NULL
+ * @channel_hdl: Channel handle provided by OP-TEE SCMI service
+ */
+struct channel_session {
+ struct udevice *tee;
+ u32 tee_session;
+ struct tee_shm *tee_shm;
+ u32 channel_hdl;
+};
+
+#define TA_SCMI_UUID { 0xa8cfe406, 0xd4f5, 0x4a2e, \
+ { 0x9f, 0x8d, 0xa2, 0x5d, 0xc7, 0x54, 0xc0, 0x99 } }
+
+enum optee_smci_pta_cmd {
+ /*
+ * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
+ *
+ * [out] value[0].a: Capability bit mask (enum pta_scmi_caps)
+ * [out] value[0].b: Extended capabilities or 0
+ */
+ PTA_SCMI_CMD_CAPABILITIES = 0,
+
+ /*
+ * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer
+ *
+ * [in] value[0].a: Channel handle
+ *
+ * Shared memory used for SCMI message/response exhange is expected
+ * already identified and bound to channel handle in both SCMI agent
+ * and SCMI server (OP-TEE) parts.
+ * The memory uses SMT header to carry SCMI meta-data (protocol ID and
+ * protocol message ID).
+ */
+ PTA_SCMI_CMD_PROCESS_SMT_CHANNEL = 1,
+
+ /*
+ * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE - Process SMT/SCMI message
+ *
+ * [in] value[0].a: Channel handle
+ * [in/out] memref[1]: Message/response buffer (SMT and SCMI payload)
+ *
+ * Shared memory used for SCMI message/response is a SMT buffer
+ * referenced by param[1]. It shall be 128 bytes large to fit response
+ * payload whatever message playload size.
+ * The memory uses SMT header to carry SCMI meta-data (protocol ID and
+ * protocol message ID).
+ */
+ PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE = 2,
+
+ /*
+ * PTA_SCMI_CMD_GET_CHANNEL - Get channel handle
+ *
+ * SCMI shm information are 0 if agent expects to use OP-TEE regular SHM
+ *
+ * [in] value[0].a: Channel identifier
+ * [out] value[0].a: Returned channel handle
+ * [in] value[0].b: Requested capabilities mask (enum pta_scmi_caps)
+ */
+ PTA_SCMI_CMD_GET_CHANNEL = 3,
+};
+
+/*
+ * OP-TEE SCMI service capabilities bit flags (32bit)
+ *
+ * PTA_SCMI_CAPS_SMT_HEADER
+ * When set, OP-TEE supports command using SMT header protocol (SCMI shmem) in
+ * shared memory buffers to carry SCMI protocol synchronisation information.
+ */
+#define PTA_SCMI_CAPS_NONE 0
+#define PTA_SCMI_CAPS_SMT_HEADER BIT(0)
+
+static int open_channel(struct udevice *dev, struct channel_session *sess)
+{
+ const struct tee_optee_ta_uuid uuid = TA_SCMI_UUID;
+ struct scmi_optee_channel *chan = dev_get_plat(dev);
+ struct tee_open_session_arg sess_arg = { };
+ struct tee_invoke_arg cmd_arg = { };
+ struct tee_param param[1] = { };
+ int ret;
+
+ memset(sess, 0, sizeof(sess));
+
+ sess->tee = tee_find_device(NULL, NULL, NULL, NULL);
+ if (!sess->tee)
+ return -ENODEV;
+
+ sess_arg.clnt_login = TEE_LOGIN_REE_KERNEL;
+ tee_optee_ta_uuid_to_octets(sess_arg.uuid, &uuid);
+
+ ret = tee_open_session(sess->tee, &sess_arg, 0, NULL);
+ if (ret) {
+ dev_err(dev, "can't open session: %d\n", ret);
+ return ret;
+ }
+
+ cmd_arg.func = PTA_SCMI_CMD_GET_CHANNEL;
+ cmd_arg.session = sess_arg.session;
+
+ param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT;
+ param[0].u.value.a = chan->channel_id;
+ param[0].u.value.b = PTA_SCMI_CAPS_SMT_HEADER;
+
+ ret = tee_invoke_func(sess->tee, &cmd_arg, ARRAY_SIZE(param), param);
+ if (ret || cmd_arg.ret) {
+ dev_err(dev, "Invoke failed: %d, 0x%x\n", ret, cmd_arg.ret);
+ if (!ret)
+ ret = -EPROTO;
+
+ tee_close_session(sess->tee, sess_arg.session);
+ return ret;
+ }
+
+ sess->tee_session = sess_arg.session;
+ sess->channel_hdl = param[0].u.value.a;
+
+ return 0;
+}
+
+static void close_channel(struct channel_session *sess)
+{
+ tee_close_session(sess->tee, sess->tee_session);
+}
+
+static int invoke_cmd(struct udevice *dev, struct channel_session *sess,
+ struct scmi_msg *msg)
+{
+ struct scmi_optee_channel *chan = dev_get_plat(dev);
+ struct tee_invoke_arg arg = { };
+ struct tee_param param[2] = { };
+ int ret;
+
+ scmi_write_msg_to_smt(dev, &chan->smt, msg);
+
+ arg.session = sess->tee_session;
+ param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT;
+ param[0].u.value.a = sess->channel_hdl;
+
+ if (chan->dyn_shm) {
+ arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE;
+ param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT;
+ param[1].u.memref.shm = sess->tee_shm;
+ param[1].u.memref.size = SCMI_SHM_SIZE;
+ } else {
+ arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL;
+ }
+
+ ret = tee_invoke_func(sess->tee, &arg, ARRAY_SIZE(param), param);
+ if (ret || arg.ret) {
+ if (!ret)
+ ret = -EPROTO;
+ } else {
+ ret = scmi_read_resp_from_smt(dev, &chan->smt, msg);
+ }
+
+ scmi_clear_smt_channel(&chan->smt);
+
+ return ret;
+}
+
+static int prepare_shm(struct udevice *dev, struct channel_session *sess)
+{
+ struct scmi_optee_channel *chan = dev_get_plat(dev);
+ int ret;
+
+ /* Static shm is already prepared by the firmware: nothing to do */
+ if (!chan->dyn_shm)
+ return 0;
+
+ chan->smt.size = SCMI_SHM_SIZE;
+
+ ret = tee_shm_alloc(sess->tee, chan->smt.size, 0, &sess->tee_shm);
+ if (ret) {
+ dev_err(dev, "Failed to allocated shmem: %d\n", ret);
+ return ret;
+ }
+
+ chan->smt.buf = sess->tee_shm->addr;
+
+ /* Initialize shm buffer for message exchanges */
+ scmi_clear_smt_channel(&chan->smt);
+
+ return 0;
+}
+
+static void release_shm(struct udevice *dev, struct channel_session *sess)
+{
+ struct scmi_optee_channel *chan = dev_get_plat(dev);
+
+ if (chan->dyn_shm)
+ tee_shm_free(sess->tee_shm);
+}
+
+static int scmi_optee_process_msg(struct udevice *dev, struct scmi_msg *msg)
+{
+ struct channel_session sess;
+ int ret;
+
+ ret = open_channel(dev, &sess);
+ if (ret)
+ return ret;
+
+ ret = prepare_shm(dev, &sess);
+ if (ret)
+ goto out;
+
+ ret = invoke_cmd(dev, &sess, msg);
+
+ release_shm(dev, &sess);
+
+out:
+ close_channel(&sess);
+
+ return ret;
+}
+
+static int scmi_optee_of_to_plat(struct udevice *dev)
+{
+ struct scmi_optee_channel *chan = dev_get_plat(dev);
+ int ret;
+
+ if (dev_read_u32(dev, "linaro,optee-channel-id", &chan->channel_id)) {
+ dev_err(dev, "Missing property linaro,optee-channel-id\n");
+ return -EINVAL;
+ }
+
+ if (dev_read_prop(dev, "shmem", NULL)) {
+ ret = scmi_dt_get_smt_buffer(dev, &chan->smt);
+ if (ret) {
+ dev_err(dev, "Failed to get smt resources: %d\n", ret);
+ return ret;
+ }
+ chan->dyn_shm = false;
+ } else {
+ chan->dyn_shm = true;
+ }
+
+ return 0;
+}
+
+static int scmi_optee_probe(struct udevice *dev)
+{
+ struct channel_session sess;
+ int ret;
+
+ /* Check OP-TEE service acknowledges the SCMI channel */
+ ret = open_channel(dev, &sess);
+ if (!ret)
+ close_channel(&sess);
+
+ return ret;
+}
+
+static const struct udevice_id scmi_optee_ids[] = {
+ { .compatible = "linaro,scmi-optee" },
+ { }
+};
+
+static const struct scmi_agent_ops scmi_optee_ops = {
+ .process_msg = scmi_optee_process_msg,
+};
+
+U_BOOT_DRIVER(scmi_optee) = {
+ .name = "scmi-over-optee",
+ .id = UCLASS_SCMI_AGENT,
+ .of_match = scmi_optee_ids,
+ .plat_auto = sizeof(struct scmi_optee_channel),
+ .of_to_plat = scmi_optee_of_to_plat,
+ .probe = scmi_optee_probe,
+ .flags = DM_FLAG_OS_PREPARE,
+ .ops = &scmi_optee_ops,
+};
static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg)
{
- struct scmi_smccc_channel *chan = dev_get_priv(dev);
+ struct scmi_smccc_channel *chan = dev_get_plat(dev);
struct arm_smccc_res res;
int ret;
return ret;
}
-static int scmi_smccc_probe(struct udevice *dev)
+static int scmi_smccc_of_to_plat(struct udevice *dev)
{
- struct scmi_smccc_channel *chan = dev_get_priv(dev);
+ struct scmi_smccc_channel *chan = dev_get_plat(dev);
u32 func_id;
int ret;
chan->func_id = func_id;
ret = scmi_dt_get_smt_buffer(dev, &chan->smt);
- if (ret) {
+ if (ret)
dev_err(dev, "Failed to get smt resources: %d\n", ret);
- return ret;
- }
- return 0;
+ return ret;
}
static const struct udevice_id scmi_smccc_ids[] = {
.name = "scmi-over-smccc",
.id = UCLASS_SCMI_AGENT,
.of_match = scmi_smccc_ids,
- .priv_auto = sizeof(struct scmi_smccc_channel),
- .probe = scmi_smccc_probe,
+ .plat_auto = sizeof(struct scmi_smccc_channel),
+ .of_to_plat = scmi_smccc_of_to_plat,
.ops = &scmi_smccc_ops,
};
includes methods to start/stop the device, check for available
input and update LEDs if the keyboard has them.
+config KEYBOARD
+ bool "Enable legacy keyboard support (deprecated)"
+ help
+ Enable this to enable a custom keyboard support.
+ This simply calls drv_keyboard_init() which must be
+ defined in your board-specific files. This option is deprecated
+ and is only used by novena. For new boards, use driver model
+ instead.
+
config CROS_EC_KEYB
bool "Enable Chrome OS EC keyboard support"
depends on INPUT
struct blk_desc *desc;
struct udevice *dev;
- device_find_first_child(mmc->dev, &dev);
+ device_find_first_child_by_uclass(mmc->dev, UCLASS_BLK, &dev);
if (!dev)
return NULL;
desc = dev_get_uclass_plat(dev);
{
struct udevice *bdev;
- device_find_first_child(dev, &bdev);
+ device_find_first_child_by_uclass(dev, UCLASS_BLK, &bdev);
if (bdev) {
device_remove(bdev, DM_REMOVE_NORMAL);
device_unbind(bdev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
+static int msdc_ops_wait_dat0(struct udevice *dev, int state, int timeout_us)
+{
+ struct msdc_host *host = dev_get_priv(dev);
+ int ret;
+ u32 reg;
+
+ ret = readl_poll_sleep_timeout(&host->base->msdc_ps, reg,
+ !!(reg & MSDC_PS_DAT0) == !!state,
+ 1000, /* 1 ms */
+ timeout_us);
+
+ return ret;
+}
+
static const struct dm_mmc_ops msdc_ops = {
.send_cmd = msdc_ops_send_cmd,
.set_ios = msdc_ops_set_ios,
#ifdef MMC_SUPPORTS_TUNING
.execute_tuning = msdc_execute_tuning,
#endif
+ .wait_dat0 = msdc_ops_wait_dat0,
};
static const struct msdc_compatible mt7620_compat = {
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
+#include <malloc.h>
#include <mmc.h>
+#include <os.h>
#include <asm/test.h>
struct sandbox_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
+ const char *fname;
};
-#define MMC_CSIZE 0
-#define MMC_CMULT 8 /* 8 because the card is high-capacity */
-#define MMC_BL_LEN_SHIFT 10
-#define MMC_BL_LEN BIT(MMC_BL_LEN_SHIFT)
-#define MMC_CAPACITY (((MMC_CSIZE + 1) << (MMC_CMULT + 2)) \
- * MMC_BL_LEN) /* 1 MiB */
+#define MMC_CMULT 8 /* 8 because the card is high-capacity */
+#define MMC_BL_LEN_SHIFT 10
+#define MMC_BL_LEN BIT(MMC_BL_LEN_SHIFT)
+#define SIZE_MULTIPLE ((1 << (MMC_CMULT + 2)) * MMC_BL_LEN)
struct sandbox_mmc_priv {
- u8 buf[MMC_CAPACITY];
+ char *buf;
+ int csize; /* CSIZE value to report */
+ int size;
};
/**
case MMC_CMD_SEND_CSD:
cmd->response[0] = 0;
cmd->response[1] = (MMC_BL_LEN_SHIFT << 16) |
- ((MMC_CSIZE >> 16) & 0x3f);
- cmd->response[2] = (MMC_CSIZE & 0xffff) << 16;
+ ((priv->csize >> 16) & 0x3f);
+ cmd->response[2] = (priv->csize & 0xffff) << 16;
cmd->response[3] = 0;
break;
case SD_CMD_SWITCH_FUNC: {
struct blk_desc *blk;
int ret;
+ plat->fname = dev_read_string(dev, "filename");
+
ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
static int sandbox_mmc_probe(struct udevice *dev)
{
struct sandbox_mmc_plat *plat = dev_get_plat(dev);
+ struct sandbox_mmc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (plat->fname) {
+ ret = os_map_file(plat->fname, OS_O_RDWR | OS_O_CREAT,
+ (void **)&priv->buf, &priv->size);
+ if (ret) {
+ log_err("%s: Unable to map file '%s'\n", dev->name,
+ plat->fname);
+ return ret;
+ }
+ priv->csize = priv->size / SIZE_MULTIPLE - 1;
+ } else {
+ priv->csize = 0;
+ priv->size = (priv->csize + 1) * SIZE_MULTIPLE; /* 1 MiB */
+
+ priv->buf = malloc(priv->size);
+ if (!priv->buf) {
+ log_err("%s: Not enough memory (%x bytes)\n",
+ dev->name, priv->size);
+ return -ENOMEM;
+ }
+ }
return mmc_init(&plat->mmc);
}
+static int sandbox_mmc_remove(struct udevice *dev)
+{
+ struct sandbox_mmc_plat *plat = dev_get_plat(dev);
+ struct sandbox_mmc_priv *priv = dev_get_priv(dev);
+
+ if (plat->fname)
+ os_unmap(priv->buf, priv->size);
+ else
+ free(priv->buf);
+
+ return 0;
+}
+
static int sandbox_mmc_bind(struct udevice *dev)
{
struct sandbox_mmc_plat *plat = dev_get_plat(dev);
.unbind = sandbox_mmc_unbind,
.of_to_plat = sandbox_mmc_of_to_plat,
.probe = sandbox_mmc_probe,
+ .remove = sandbox_mmc_remove,
.priv_auto = sizeof(struct sandbox_mmc_priv),
.plat_auto = sizeof(struct sandbox_mmc_plat),
};
#include <asm/bitops.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
.host_power_cycle = stm32_sdmmc2_host_power_cycle,
};
+static int stm32_sdmmc2_probe_level_translator(struct udevice *dev)
+{
+ struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+ struct gpio_desc cmd_gpio;
+ struct gpio_desc ck_gpio;
+ struct gpio_desc ckin_gpio;
+ int clk_hi, clk_lo, ret;
+
+ /*
+ * Assume the level translator is present if st,use-ckin is set.
+ * This is to cater for DTs which do not implement this test.
+ */
+ priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
+
+ ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret)
+ goto exit_cmd;
+
+ ret = gpio_request_by_name(dev, "st,ck-gpios", 0, &ck_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret)
+ goto exit_ck;
+
+ ret = gpio_request_by_name(dev, "st,ckin-gpios", 0, &ckin_gpio,
+ GPIOD_IS_IN);
+ if (ret)
+ goto exit_ckin;
+
+ /* All GPIOs are valid, test whether level translator works */
+
+ /* Sample CKIN */
+ clk_hi = !!dm_gpio_get_value(&ckin_gpio);
+
+ /* Set CK low */
+ dm_gpio_set_value(&ck_gpio, 0);
+
+ /* Sample CKIN */
+ clk_lo = !!dm_gpio_get_value(&ckin_gpio);
+
+ /* Tristate all */
+ dm_gpio_set_dir_flags(&cmd_gpio, GPIOD_IS_IN);
+ dm_gpio_set_dir_flags(&ck_gpio, GPIOD_IS_IN);
+
+ /* Level translator is present if CK signal is propagated to CKIN */
+ if (!clk_hi || clk_lo)
+ priv->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN;
+
+ dm_gpio_free(dev, &ckin_gpio);
+
+exit_ckin:
+ dm_gpio_free(dev, &ck_gpio);
+exit_ck:
+ dm_gpio_free(dev, &cmd_gpio);
+exit_cmd:
+ pinctrl_select_state(dev, "default");
+
+ return 0;
+}
+
static int stm32_sdmmc2_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
if (dev_read_bool(dev, "st,sig-dir"))
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
if (dev_read_bool(dev, "st,use-ckin"))
- priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
+ stm32_sdmmc2_probe_level_translator(dev);
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
return 0;
}
+__weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+ u32 arg3, u32 *ret_payload)
+{
+ return 0;
+}
+
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
/* Default settings for ZynqMP Clock Phases */
static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
source "drivers/net/fsl-mc/Kconfig"
+source "drivers/net/bnxt/Kconfig"
config ETH
def_bool y
This driver supports Realtek 8169 series gigabit ethernet family of
PCI/PCIe chipsets/adapters.
+config SJA1105
+ bool "NXP SJA1105 Ethernet switch family driver"
+ depends on DM_DSA && DM_SPI
+ select BITREVERSE
+ help
+ This is the driver for the NXP SJA1105 automotive Ethernet switch
+ family. These are 5-port devices and are managed over an SPI
+ interface. Probing is handled based on OF bindings. The driver
+ supports the following revisions:
+ - SJA1105E (Gen. 1, No TT-Ethernet)
+ - SJA1105T (Gen. 1, TT-Ethernet)
+ - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
+ - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
+ - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
+ - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
+
config SMC911X
bool "SMSC LAN911x and LAN921x controller driver"
This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and
on the mEMAC (which supports both Clauses 22 and 45).
+config ASPEED_MDIO
+ bool "Aspeed MDIO interface support"
+ depends on DM_MDIO
+ help
+ This driver supports the MDIO bus of Aspeed AST2600 SOC. The driver
+ currently supports Clause 22.
+
config MDIO_MUX_MMIOREG
bool "MDIO MUX accessed as a MMIO register access"
depends on DM_MDIO_MUX
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += phy/
-obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_AG7XXX) += ag7xxx.o
+obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
+obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o
obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
obj-$(CONFIG_BCMGENET) += bcmgenet.o
-obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
+obj-$(CONFIG_BNXT_ETH) += bnxt/
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
obj-$(CONFIG_CS8900) += cs8900.o
-obj-$(CONFIG_TULIP) += dc2114x.o
-obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
-obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
-obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
-obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
-obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
+obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DNET) += dnet.o
+obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
+obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
-obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
+obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
-obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
-obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
+obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
+obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
+obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
+obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
+obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
+obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
+obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
obj-$(CONFIG_FMAN_ENET) += fm/
+obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
+obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
+obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
+obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
+obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
+obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
-obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
+obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
+obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_KSZ9477) += ksz9477.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o
obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
+obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
+obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o
obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
+obj-$(CONFIG_NET_OCTEONTX) += octeontx/
+obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
obj-$(CONFIG_NS8382X) += ns8382x.o
+obj-$(CONFIG_OCTEONTX2_CGX_INTF) += octeontx2/cgx_intf.o
+obj-$(CONFIG_OCTEONTX_SMI) += octeontx/smi.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o
obj-$(CONFIG_PCNET) += pcnet.o
+obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
+obj-$(CONFIG_RENESAS_RAVB) += ravb.o
obj-$(CONFIG_RTL8139) += rtl8139.o
obj-$(CONFIG_RTL8169) += rtl8169.o
-obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
-obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
-obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
-obj-$(CONFIG_RENESAS_RAVB) += ravb.o
+obj-$(CONFIG_SJA1105) += sja1105.o
obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
+obj-$(CONFIG_SNI_AVE) += sni_ave.o
+obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
+obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
+obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_NET_OCTEONTX) += octeontx/
-obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
-obj-$(CONFIG_OCTEONTX_SMI) += octeontx/smi.o
-obj-$(CONFIG_OCTEONTX2_CGX_INTF) += octeontx2/cgx_intf.o
-obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
+obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
+obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o
obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
-obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
-obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
-obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
-obj-$(CONFIG_VSC9953) += vsc9953.o
-obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
-obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
-obj-$(CONFIG_FSL_PFE) += pfe_eth/
+obj-y += mscc_eswitch/
+obj-y += phy/
obj-y += qe/
-obj-$(CONFIG_SNI_AVE) += sni_ave.o
-obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
obj-y += ti/
-obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
-obj-y += mscc_eswitch/
-obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
-obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
-obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
-obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Aspeed MDIO driver
+ *
+ * (C) Copyright 2021 Aspeed Technology Inc.
+ *
+ * This file is inspired from the Linux kernel driver drivers/net/phy/mdio-aspeed.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <miiphy.h>
+#include <net.h>
+#include <reset.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#define ASPEED_MDIO_CTRL 0x0
+#define ASPEED_MDIO_CTRL_FIRE BIT(31)
+#define ASPEED_MDIO_CTRL_ST BIT(28)
+#define ASPEED_MDIO_CTRL_ST_C45 0
+#define ASPEED_MDIO_CTRL_ST_C22 1
+#define ASPEED_MDIO_CTRL_OP GENMASK(27, 26)
+#define MDIO_C22_OP_WRITE 0b01
+#define MDIO_C22_OP_READ 0b10
+#define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21)
+#define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16)
+#define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
+
+#define ASPEED_MDIO_DATA 0x4
+#define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24)
+#define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23)
+#define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20)
+#define ASPEED_MDIO_DATA_IDLE BIT(16)
+#define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0)
+
+#define ASPEED_MDIO_TIMEOUT_US 1000
+
+struct aspeed_mdio_priv {
+ void *base;
+};
+
+static int aspeed_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
+{
+ struct aspeed_mdio_priv *priv = dev_get_priv(mdio_dev);
+ u32 ctrl;
+ u32 data;
+ int rc;
+
+ if (devad != MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ctrl = ASPEED_MDIO_CTRL_FIRE
+ | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg);
+
+ writel(ctrl, priv->base + ASPEED_MDIO_CTRL);
+
+ rc = readl_poll_timeout(priv->base + ASPEED_MDIO_DATA, data,
+ data & ASPEED_MDIO_DATA_IDLE,
+ ASPEED_MDIO_TIMEOUT_US);
+
+ if (rc < 0)
+ return rc;
+
+ return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data);
+}
+
+static int aspeed_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
+{
+ struct aspeed_mdio_priv *priv = dev_get_priv(mdio_dev);
+ u32 ctrl;
+
+ if (devad != MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ctrl = ASPEED_MDIO_CTRL_FIRE
+ | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_WRITE)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg)
+ | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val);
+
+ writel(ctrl, priv->base + ASPEED_MDIO_CTRL);
+
+ return readl_poll_timeout(priv->base + ASPEED_MDIO_CTRL, ctrl,
+ !(ctrl & ASPEED_MDIO_CTRL_FIRE),
+ ASPEED_MDIO_TIMEOUT_US);
+}
+
+static const struct mdio_ops aspeed_mdio_ops = {
+ .read = aspeed_mdio_read,
+ .write = aspeed_mdio_write,
+};
+
+static int aspeed_mdio_probe(struct udevice *dev)
+{
+ struct aspeed_mdio_priv *priv = dev_get_priv(dev);
+ struct reset_ctl reset_ctl;
+ int ret = 0;
+
+ priv->base = dev_read_addr_ptr(dev);
+
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
+ reset_deassert(&reset_ctl);
+
+ return 0;
+}
+
+static const struct udevice_id aspeed_mdio_ids[] = {
+ { .compatible = "aspeed,ast2600-mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_mdio) = {
+ .name = "aspeed_mdio",
+ .id = UCLASS_MDIO,
+ .of_match = aspeed_mdio_ids,
+ .probe = aspeed_mdio_probe,
+ .ops = &aspeed_mdio_ops,
+ .plat_auto = sizeof(struct mdio_perdev_priv),
+ .priv_auto = sizeof(struct aspeed_mdio_priv),
+};
--- /dev/null
+config BNXT_ETH
+ bool "BNXT PCI support"
+ depends on DM_ETH
+ select PCI_INIT_R
+ help
+ This driver implements support for bnxt pci controller
+ driver of ethernet class.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019-2021 Broadcom.
+
+# Broadcom nxe Ethernet driver
+obj-y += bnxt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 Broadcom.
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <memalign.h>
+#include <net.h>
+
+#include "bnxt.h"
+#include "bnxt_dbg.h"
+
+#define bnxt_down_chip(bp) bnxt_hwrm_run(down_chip, bp, 0)
+#define bnxt_bring_chip(bp) bnxt_hwrm_run(bring_chip, bp, 1)
+
+/* Broadcom ethernet driver PCI APIs. */
+static void bnxt_bring_pci(struct bnxt *bp)
+{
+ u16 cmd_reg = 0;
+
+ dm_pci_read_config16(bp->pdev, PCI_VENDOR_ID, &bp->vendor_id);
+ dm_pci_read_config16(bp->pdev, PCI_DEVICE_ID, &bp->device_id);
+ dm_pci_read_config16(bp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &bp->subsystem_vendor);
+ dm_pci_read_config16(bp->pdev, PCI_SUBSYSTEM_ID, &bp->subsystem_device);
+ dm_pci_read_config16(bp->pdev, PCI_COMMAND, &bp->cmd_reg);
+ dm_pci_read_config8(bp->pdev, PCI_INTERRUPT_LINE, &bp->irq);
+ bp->bar0 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ bp->bar1 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
+ bp->bar2 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
+ cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */
+ dm_pci_write_config16(bp->pdev, PCI_COMMAND, cmd_reg);
+ dm_pci_read_config16(bp->pdev, PCI_COMMAND, &cmd_reg);
+ dbg_pci(bp, __func__, cmd_reg);
+}
+
+int bnxt_free_rx_iob(struct bnxt *bp)
+{
+ unsigned int i;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_RX_IOB)))
+ return STATUS_SUCCESS;
+
+ for (i = 0; i < bp->rx.buf_cnt; i++) {
+ if (bp->rx.iob[i]) {
+ free(bp->rx.iob[i]);
+ bp->rx.iob[i] = NULL;
+ }
+ }
+
+ FLAG_RESET(bp->flag_hwrm, VALID_RX_IOB);
+
+ return STATUS_SUCCESS;
+}
+
+static void set_rx_desc(u8 *buf, void *iob, u16 cons_id, u32 iob_idx)
+{
+ struct rx_prod_pkt_bd *desc;
+ u16 off = cons_id * sizeof(struct rx_prod_pkt_bd);
+
+ desc = (struct rx_prod_pkt_bd *)&buf[off];
+ desc->flags_type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
+ desc->len = MAX_ETHERNET_PACKET_BUFFER_SIZE;
+ desc->opaque = iob_idx;
+ desc->dma.addr = virt_to_bus(iob);
+}
+
+static int bnxt_alloc_rx_iob(struct bnxt *bp, u16 cons_id, u16 iob_idx)
+{
+ void *iob;
+
+ iob = memalign(BNXT_DMA_ALIGNMENT, RX_STD_DMA_ALIGNED);
+ if (!iob)
+ return -ENOMEM;
+
+ dbg_rx_iob(iob, iob_idx, cons_id);
+ set_rx_desc((u8 *)bp->rx.bd_virt, iob, cons_id, (u32)iob_idx);
+ bp->rx.iob[iob_idx] = iob;
+
+ return 0;
+}
+
+void bnxt_mm_init(struct bnxt *bp, const char *func)
+{
+ memset(bp->hwrm_addr_req, 0, REQ_BUFFER_SIZE);
+ memset(bp->hwrm_addr_resp, 0, RESP_BUFFER_SIZE);
+ memset(bp->cq.bd_virt, 0, CQ_RING_DMA_BUFFER_SIZE);
+ memset(bp->tx.bd_virt, 0, TX_RING_DMA_BUFFER_SIZE);
+ memset(bp->rx.bd_virt, 0, RX_RING_DMA_BUFFER_SIZE);
+
+ bp->data_addr_mapping = virt_to_bus(bp->hwrm_addr_data);
+ bp->req_addr_mapping = virt_to_bus(bp->hwrm_addr_req);
+ bp->resp_addr_mapping = virt_to_bus(bp->hwrm_addr_resp);
+ bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
+ bp->link_status = STATUS_LINK_DOWN;
+ bp->media_change = 1;
+ bp->mtu = MAX_ETHERNET_PACKET_BUFFER_SIZE;
+ bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
+ bp->rx.buf_cnt = NUM_RX_BUFFERS;
+ bp->rx.ring_cnt = MAX_RX_DESC_CNT;
+ bp->tx.ring_cnt = MAX_TX_DESC_CNT;
+ bp->cq.ring_cnt = MAX_CQ_DESC_CNT;
+ bp->cq.completion_bit = 0x1;
+ bp->link_set = LINK_SPEED_DRV_100G;
+ dbg_mem(bp, func);
+}
+
+void bnxt_free_mem(struct bnxt *bp)
+{
+ if (bp->cq.bd_virt) {
+ free(bp->cq.bd_virt);
+ bp->cq.bd_virt = NULL;
+ }
+
+ if (bp->rx.bd_virt) {
+ free(bp->rx.bd_virt);
+ bp->rx.bd_virt = NULL;
+ }
+
+ if (bp->tx.bd_virt) {
+ free(bp->tx.bd_virt);
+ bp->tx.bd_virt = NULL;
+ }
+
+ if (bp->hwrm_addr_resp) {
+ free(bp->hwrm_addr_resp);
+ bp->resp_addr_mapping = 0;
+ bp->hwrm_addr_resp = NULL;
+ }
+
+ if (bp->hwrm_addr_req) {
+ free(bp->hwrm_addr_req);
+ bp->req_addr_mapping = 0;
+ bp->hwrm_addr_req = NULL;
+ }
+
+ if (bp->hwrm_addr_data) {
+ free(bp->hwrm_addr_data);
+ bp->data_addr_mapping = 0;
+ bp->hwrm_addr_data = NULL;
+ }
+
+ dbg_mem_free_done(__func__);
+}
+
+int bnxt_alloc_mem(struct bnxt *bp)
+{
+ bp->hwrm_addr_data = memalign(BNXT_DMA_ALIGNMENT, DMA_BUF_SIZE_ALIGNED);
+ bp->hwrm_addr_req = memalign(BNXT_DMA_ALIGNMENT, REQ_BUF_SIZE_ALIGNED);
+ bp->hwrm_addr_resp = MEM_HWRM_RESP;
+
+ memset(&bp->tx, 0, sizeof(struct lm_tx_info_t));
+ memset(&bp->rx, 0, sizeof(struct lm_rx_info_t));
+ memset(&bp->cq, 0, sizeof(struct lm_cmp_info_t));
+
+ bp->tx.bd_virt = memalign(BNXT_DMA_ALIGNMENT, TX_RING_DMA_BUFFER_SIZE);
+ bp->rx.bd_virt = memalign(BNXT_DMA_ALIGNMENT, RX_RING_DMA_BUFFER_SIZE);
+ bp->cq.bd_virt = memalign(BNXT_DMA_ALIGNMENT, CQ_RING_DMA_BUFFER_SIZE);
+
+ if (bp->hwrm_addr_req &&
+ bp->hwrm_addr_resp &&
+ bp->hwrm_addr_data &&
+ bp->tx.bd_virt &&
+ bp->rx.bd_virt &&
+ bp->cq.bd_virt) {
+ bnxt_mm_init(bp, __func__);
+ return STATUS_SUCCESS;
+ }
+
+ dbg_mem_alloc_fail(__func__);
+ bnxt_free_mem(bp);
+
+ return -ENOMEM;
+}
+
+static void hwrm_init(struct bnxt *bp, struct input *req, u16 cmd, u16 len)
+{
+ memset(req, 0, len);
+ req->req_type = cmd;
+ req->cmpl_ring = (u16)HWRM_NA_SIGNATURE;
+ req->target_id = (u16)HWRM_NA_SIGNATURE;
+ req->resp_addr = bp->resp_addr_mapping;
+ req->seq_id = bp->seq_id++;
+}
+
+static void hwrm_write_req(struct bnxt *bp, void *req, u32 cnt)
+{
+ u32 i = 0;
+
+ for (i = 0; i < cnt; i++)
+ writel(((u32 *)req)[i], bp->bar0 + GRC_COM_CHAN_BASE + (i * 4));
+
+ writel(0x1, (bp->bar0 + GRC_COM_CHAN_BASE + GRC_COM_CHAN_TRIG));
+}
+
+static void short_hwrm_cmd_req(struct bnxt *bp, u16 len)
+{
+ struct hwrm_short_input sreq;
+
+ memset(&sreq, 0, sizeof(struct hwrm_short_input));
+ sreq.req_type = (u16)((struct input *)bp->hwrm_addr_req)->req_type;
+ sreq.signature = SHORT_REQ_SIGNATURE_SHORT_CMD;
+ sreq.size = len;
+ sreq.req_addr = bp->req_addr_mapping;
+ dbg_short_cmd((u8 *)&sreq, __func__, sizeof(struct hwrm_short_input));
+ hwrm_write_req(bp, &sreq, sizeof(struct hwrm_short_input) / 4);
+}
+
+static int wait_resp(struct bnxt *bp, u32 tmo, u16 len, const char *func)
+{
+ struct input *req = (struct input *)bp->hwrm_addr_req;
+ struct output *resp = (struct output *)bp->hwrm_addr_resp;
+ u8 *ptr = (u8 *)resp;
+ u32 idx;
+ u32 wait_cnt = HWRM_CMD_DEFAULT_MULTIPLAYER((u32)tmo);
+ u16 resp_len = 0;
+ u16 ret = STATUS_TIMEOUT;
+
+ if (len > bp->hwrm_max_req_len)
+ short_hwrm_cmd_req(bp, len);
+ else
+ hwrm_write_req(bp, req, (u32)(len / 4));
+
+ for (idx = 0; idx < wait_cnt; idx++) {
+ resp_len = resp->resp_len;
+ if (resp->seq_id == req->seq_id && resp->req_type == req->req_type &&
+ ptr[resp_len - 1] == 1) {
+ bp->last_resp_code = resp->error_code;
+ ret = resp->error_code;
+ break;
+ }
+
+ udelay(HWRM_CMD_POLL_WAIT_TIME);
+ }
+
+ dbg_hw_cmd(bp, func, len, resp_len, tmo, ret);
+
+ return (int)ret;
+}
+
+static void bnxt_db_cq(struct bnxt *bp)
+{
+ writel(CQ_DOORBELL_KEY_IDX(bp->cq.cons_idx), bp->bar1);
+}
+
+static void bnxt_db_rx(struct bnxt *bp, u32 idx)
+{
+ writel(RX_DOORBELL_KEY_RX | idx, bp->bar1);
+}
+
+static void bnxt_db_tx(struct bnxt *bp, u32 idx)
+{
+ writel((u32)(TX_DOORBELL_KEY_TX | idx), bp->bar1);
+}
+
+int iob_pad(void *packet, int length)
+{
+ if (length >= ETH_ZLEN)
+ return length;
+
+ memset(((u8 *)packet + length), 0x00, (ETH_ZLEN - length));
+
+ return ETH_ZLEN;
+}
+
+static inline u32 bnxt_tx_avail(struct bnxt *bp)
+{
+ barrier();
+
+ return TX_AVAIL(bp->tx.ring_cnt) -
+ ((bp->tx.prod_id - bp->tx.cons_id) &
+ (bp->tx.ring_cnt - 1));
+}
+
+void set_txq(struct bnxt *bp, int entry, dma_addr_t mapping, int len)
+{
+ struct tx_bd_short *prod_bd;
+
+ prod_bd = (struct tx_bd_short *)BD_NOW(bp->tx.bd_virt,
+ entry,
+ sizeof(struct tx_bd_short));
+ if (len < 512)
+ prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT512;
+ else if (len < 1024)
+ prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT1K;
+ else if (len < 2048)
+ prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT2K;
+ else
+ prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_GTE2K;
+
+ prod_bd->flags_type |= TX_BD_FLAGS;
+ prod_bd->dma.addr = mapping;
+ prod_bd->len = len;
+ prod_bd->opaque = (u32)entry;
+ dump_tx_bd(prod_bd, (u16)(sizeof(struct tx_bd_short)));
+}
+
+static void bnxt_tx_complete(struct bnxt *bp)
+{
+ bp->tx.cons_id = NEXT_IDX(bp->tx.cons_id, bp->tx.ring_cnt);
+ bp->tx.cnt++;
+ dump_tx_stat(bp);
+}
+
+int post_rx_buffers(struct bnxt *bp)
+{
+ u16 cons_id = (bp->rx.cons_idx % bp->rx.ring_cnt);
+ u16 iob_idx;
+
+ while (bp->rx.iob_cnt < bp->rx.buf_cnt) {
+ iob_idx = (cons_id % bp->rx.buf_cnt);
+ if (!bp->rx.iob[iob_idx]) {
+ if (bnxt_alloc_rx_iob(bp, cons_id, iob_idx) < 0) {
+ dbg_rx_alloc_iob_fail(iob_idx, cons_id);
+ break;
+ }
+ }
+
+ cons_id = NEXT_IDX(cons_id, bp->rx.ring_cnt);
+ bp->rx.iob_cnt++;
+ }
+
+ if (cons_id != bp->rx.cons_idx) {
+ dbg_rx_cid(bp->rx.cons_idx, cons_id);
+ bp->rx.cons_idx = cons_id;
+ bnxt_db_rx(bp, (u32)cons_id);
+ }
+
+ FLAG_SET(bp->flag_hwrm, VALID_RX_IOB);
+
+ return STATUS_SUCCESS;
+}
+
+u8 bnxt_rx_drop(struct bnxt *bp, u8 *rx_buf, struct rx_pkt_cmpl_hi *rx_cmp_hi)
+{
+ u8 chksum_err = 0;
+ u8 i;
+ u16 error_flags;
+
+ error_flags = (rx_cmp_hi->errors_v2 >>
+ RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT);
+ if (rx_cmp_hi->errors_v2 == 0x20 || rx_cmp_hi->errors_v2 == 0x21)
+ chksum_err = 1;
+
+ if (error_flags && !chksum_err) {
+ bp->rx.err++;
+ return 1;
+ }
+
+ for (i = 0; i < 6; i++) {
+ if (rx_buf[6 + i] != bp->mac_set[i])
+ break;
+ }
+
+ if (i == 6) {
+ bp->rx.dropped++;
+ return 2; /* Drop the loopback packets */
+ }
+
+ return 0;
+}
+
+static void bnxt_adv_cq_index(struct bnxt *bp, u16 count)
+{
+ u16 cons_idx = bp->cq.cons_idx + count;
+
+ if (cons_idx >= MAX_CQ_DESC_CNT) {
+ /* Toggle completion bit when the ring wraps. */
+ bp->cq.completion_bit ^= 1;
+ cons_idx = cons_idx - MAX_CQ_DESC_CNT;
+ }
+
+ bp->cq.cons_idx = cons_idx;
+}
+
+void bnxt_adv_rx_index(struct bnxt *bp, u8 *iob, u32 iob_idx)
+{
+ u16 cons_id = (bp->rx.cons_idx % bp->rx.ring_cnt);
+
+ set_rx_desc((u8 *)bp->rx.bd_virt, (void *)iob, cons_id, iob_idx);
+ cons_id = NEXT_IDX(cons_id, bp->rx.ring_cnt);
+ if (cons_id != bp->rx.cons_idx) {
+ dbg_rx_cid(bp->rx.cons_idx, cons_id);
+ bp->rx.cons_idx = cons_id;
+ bnxt_db_rx(bp, (u32)cons_id);
+ }
+}
+
+void rx_process(struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp,
+ struct rx_pkt_cmpl_hi *rx_cmp_hi)
+{
+ u32 desc_idx = rx_cmp->opaque;
+ u8 *iob = bp->rx.iob[desc_idx];
+
+ dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx);
+ bp->rx.iob_len = rx_cmp->len;
+ bp->rx.iob_rx = iob;
+ if (bnxt_rx_drop(bp, iob, rx_cmp_hi))
+ bp->rx.iob_recv = PKT_DROPPED;
+ else
+ bp->rx.iob_recv = PKT_RECEIVED;
+
+ bp->rx.rx_cnt++;
+
+ dbg_rxp(bp->rx.iob_rx, bp->rx.iob_len, bp->rx.iob_recv);
+ bnxt_adv_rx_index(bp, iob, desc_idx);
+ bnxt_adv_cq_index(bp, 2); /* Rx completion is 2 entries. */
+}
+
+static int bnxt_rx_complete(struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp)
+{
+ struct rx_pkt_cmpl_hi *rx_cmp_hi;
+ u8 completion_bit = bp->cq.completion_bit;
+
+ if (bp->cq.cons_idx == (bp->cq.ring_cnt - 1)) {
+ rx_cmp_hi = (struct rx_pkt_cmpl_hi *)bp->cq.bd_virt;
+ completion_bit ^= 0x1; /* Ring has wrapped. */
+ } else {
+ rx_cmp_hi = (struct rx_pkt_cmpl_hi *)(rx_cmp + 1);
+ }
+
+ if (!((rx_cmp_hi->errors_v2 & RX_PKT_CMPL_V2) ^ completion_bit))
+ rx_process(bp, rx_cmp, rx_cmp_hi);
+
+ return NO_MORE_CQ_BD_TO_SERVICE;
+}
+
+static int bnxt_hwrm_ver_get(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_ver_get_input);
+ struct hwrm_ver_get_input *req;
+ struct hwrm_ver_get_output *resp;
+ int rc;
+
+ req = (struct hwrm_ver_get_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_ver_get_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_VER_GET, cmd_len);
+ req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
+ req->hwrm_intf_min = HWRM_VERSION_MINOR;
+ req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
+ rc = wait_resp(bp, HWRM_CMD_DEFAULT_TIMEOUT, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ bp->hwrm_spec_code =
+ resp->hwrm_intf_maj_8b << 16 |
+ resp->hwrm_intf_min_8b << 8 |
+ resp->hwrm_intf_upd_8b;
+ bp->hwrm_cmd_timeout = (u32)resp->def_req_timeout;
+ if (!bp->hwrm_cmd_timeout)
+ bp->hwrm_cmd_timeout = (u32)HWRM_CMD_DEFAULT_TIMEOUT;
+
+ if (resp->hwrm_intf_maj_8b >= 1)
+ bp->hwrm_max_req_len = resp->max_req_win_len;
+
+ bp->chip_id =
+ resp->chip_rev << 24 |
+ resp->chip_metal << 16 |
+ resp->chip_bond_id << 8 |
+ resp->chip_platform_type;
+ bp->chip_num = resp->chip_num;
+ if ((resp->dev_caps_cfg & SHORT_CMD_SUPPORTED) &&
+ (resp->dev_caps_cfg & SHORT_CMD_REQUIRED))
+ FLAG_SET(bp->flags, BNXT_FLAG_HWRM_SHORT_CMD_SUPP);
+
+ bp->hwrm_max_ext_req_len = resp->max_ext_req_len;
+ bp->fw_maj = resp->hwrm_fw_maj_8b;
+ bp->fw_min = resp->hwrm_fw_min_8b;
+ bp->fw_bld = resp->hwrm_fw_bld_8b;
+ bp->fw_rsvd = resp->hwrm_fw_rsvd_8b;
+ print_fw_ver(resp, bp->hwrm_cmd_timeout);
+
+ return STATUS_SUCCESS;
+}
+
+/* Broadcom ethernet driver Function HW cmds APIs. */
+static int bnxt_hwrm_func_resource_qcaps(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_resource_qcaps_input);
+ struct hwrm_func_resource_qcaps_input *req;
+ struct hwrm_func_resource_qcaps_output *resp;
+ int rc;
+
+ req = (struct hwrm_func_resource_qcaps_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_func_resource_qcaps_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_RESOURCE_QCAPS, cmd_len);
+ req->fid = (u16)HWRM_NA_SIGNATURE;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc != STATUS_SUCCESS)
+ return STATUS_SUCCESS;
+
+ FLAG_SET(bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT);
+ /* VFs */
+ bp->max_vfs = resp->max_vfs;
+ bp->vf_res_strategy = resp->vf_reservation_strategy;
+ /* vNICs */
+ bp->min_vnics = resp->min_vnics;
+ bp->max_vnics = resp->max_vnics;
+ /* MSI-X */
+ bp->max_msix = resp->max_msix;
+ /* Ring Groups */
+ bp->min_hw_ring_grps = resp->min_hw_ring_grps;
+ bp->max_hw_ring_grps = resp->max_hw_ring_grps;
+ /* TX Rings */
+ bp->min_tx_rings = resp->min_tx_rings;
+ bp->max_tx_rings = resp->max_tx_rings;
+ /* RX Rings */
+ bp->min_rx_rings = resp->min_rx_rings;
+ bp->max_rx_rings = resp->max_rx_rings;
+ /* Completion Rings */
+ bp->min_cp_rings = resp->min_cmpl_rings;
+ bp->max_cp_rings = resp->max_cmpl_rings;
+ /* RSS Contexts */
+ bp->min_rsscos_ctxs = resp->min_rsscos_ctx;
+ bp->max_rsscos_ctxs = resp->max_rsscos_ctx;
+ /* L2 Contexts */
+ bp->min_l2_ctxs = resp->min_l2_ctxs;
+ bp->max_l2_ctxs = resp->max_l2_ctxs;
+ /* Statistic Contexts */
+ bp->min_stat_ctxs = resp->min_stat_ctx;
+ bp->max_stat_ctxs = resp->max_stat_ctx;
+ dbg_func_resource_qcaps(bp);
+
+ return STATUS_SUCCESS;
+}
+
+static u32 set_ring_info(struct bnxt *bp)
+{
+ u32 enables = 0;
+
+ bp->num_cmpl_rings = DEFAULT_NUMBER_OF_CMPL_RINGS;
+ bp->num_tx_rings = DEFAULT_NUMBER_OF_TX_RINGS;
+ bp->num_rx_rings = DEFAULT_NUMBER_OF_RX_RINGS;
+ bp->num_hw_ring_grps = DEFAULT_NUMBER_OF_RING_GRPS;
+ bp->num_stat_ctxs = DEFAULT_NUMBER_OF_STAT_CTXS;
+ if (bp->min_cp_rings <= DEFAULT_NUMBER_OF_CMPL_RINGS)
+ bp->num_cmpl_rings = bp->min_cp_rings;
+
+ if (bp->min_tx_rings <= DEFAULT_NUMBER_OF_TX_RINGS)
+ bp->num_tx_rings = bp->min_tx_rings;
+
+ if (bp->min_rx_rings <= DEFAULT_NUMBER_OF_RX_RINGS)
+ bp->num_rx_rings = bp->min_rx_rings;
+
+ if (bp->min_hw_ring_grps <= DEFAULT_NUMBER_OF_RING_GRPS)
+ bp->num_hw_ring_grps = bp->min_hw_ring_grps;
+
+ if (bp->min_stat_ctxs <= DEFAULT_NUMBER_OF_STAT_CTXS)
+ bp->num_stat_ctxs = bp->min_stat_ctxs;
+
+ print_num_rings(bp);
+ enables = (FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
+ FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS |
+ FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS |
+ FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS |
+ FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS);
+
+ return enables;
+}
+
+static void bnxt_hwrm_assign_resources(struct bnxt *bp)
+{
+ struct hwrm_func_cfg_input *req;
+ u32 enables = 0;
+
+ if (FLAG_TEST(bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT))
+ enables = set_ring_info(bp);
+
+ req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req;
+ req->num_cmpl_rings = bp->num_cmpl_rings;
+ req->num_tx_rings = bp->num_tx_rings;
+ req->num_rx_rings = bp->num_rx_rings;
+ req->num_stat_ctxs = bp->num_stat_ctxs;
+ req->num_hw_ring_grps = bp->num_hw_ring_grps;
+ req->enables = enables;
+}
+
+int bnxt_hwrm_nvm_flush(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_nvm_flush_input);
+ struct hwrm_nvm_flush_input *req;
+ int rc;
+
+ req = (struct hwrm_nvm_flush_input *)bp->hwrm_addr_req;
+
+ hwrm_init(bp, (void *)req, (u16)HWRM_NVM_FLUSH, cmd_len);
+
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_func_qcaps_req(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_qcaps_input);
+ struct hwrm_func_qcaps_input *req;
+ struct hwrm_func_qcaps_output *resp;
+ int rc;
+
+ req = (struct hwrm_func_qcaps_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_func_qcaps_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_QCAPS, cmd_len);
+ req->fid = (u16)HWRM_NA_SIGNATURE;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ bp->fid = resp->fid;
+ bp->port_idx = (u8)resp->port_id;
+
+ /* Get MAC address for this PF */
+ memcpy(&bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN);
+
+ memcpy(&bp->mac_set[0], &bp->mac_addr[0], ETH_ALEN);
+
+ print_func_qcaps(bp);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_func_qcfg_req(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_qcfg_input);
+ struct hwrm_func_qcfg_input *req;
+ struct hwrm_func_qcfg_output *resp;
+ int rc;
+
+ req = (struct hwrm_func_qcfg_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_func_qcfg_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_QCFG, cmd_len);
+ req->fid = (u16)HWRM_NA_SIGNATURE;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ if (resp->flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)
+ FLAG_SET(bp->flags, BNXT_FLAG_MULTI_HOST);
+
+ if (resp->port_partition_type &
+ FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0)
+ FLAG_SET(bp->flags, BNXT_FLAG_NPAR_MODE);
+
+ bp->ordinal_value = (u8)resp->pci_id & 0x0F;
+ bp->stat_ctx_id = resp->stat_ctx_id;
+ memcpy(&bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN);
+ print_func_qcfg(bp);
+ dbg_flags(__func__, bp->flags);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_func_reset_req(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_reset_input);
+ struct hwrm_func_reset_input *req;
+
+ req = (struct hwrm_func_reset_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_RESET, cmd_len);
+ req->func_reset_level = FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME;
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int bnxt_hwrm_func_cfg_req(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_cfg_input);
+ struct hwrm_func_cfg_input *req;
+
+ req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_CFG, cmd_len);
+ req->fid = (u16)HWRM_NA_SIGNATURE;
+ bnxt_hwrm_assign_resources(bp);
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_drv_rgtr_input);
+ struct hwrm_func_drv_rgtr_input *req;
+ int rc;
+
+ req = (struct hwrm_func_drv_rgtr_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_DRV_RGTR, cmd_len);
+ /* Register with HWRM */
+ req->enables = FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
+ FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD |
+ FUNC_DRV_RGTR_REQ_ENABLES_VER;
+ req->async_event_fwd[0] |= 0x01;
+ req->os_type = FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER;
+ req->ver_maj = DRIVER_VERSION_MAJOR;
+ req->ver_min = DRIVER_VERSION_MINOR;
+ req->ver_upd = DRIVER_VERSION_UPDATE;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_SET(bp->flag_hwrm, VALID_DRIVER_REG);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_drv_unrgtr_input);
+ struct hwrm_func_drv_unrgtr_input *req;
+ int rc;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_DRIVER_REG)))
+ return STATUS_SUCCESS;
+
+ req = (struct hwrm_func_drv_unrgtr_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_DRV_UNRGTR, cmd_len);
+ req->flags = FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_RESET(bp->flag_hwrm, VALID_DRIVER_REG);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_cfa_l2_filter_alloc(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_filter_alloc_input);
+ struct hwrm_cfa_l2_filter_alloc_input *req;
+ struct hwrm_cfa_l2_filter_alloc_output *resp;
+ int rc;
+ u32 flags = CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX;
+ u32 enables;
+
+ req = (struct hwrm_cfa_l2_filter_alloc_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_cfa_l2_filter_alloc_output *)bp->hwrm_addr_resp;
+ enables = CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
+ CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
+ CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK;
+
+ hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_FILTER_ALLOC, cmd_len);
+ req->flags = flags;
+ req->enables = enables;
+ memcpy((char *)&req->l2_addr[0], (char *)&bp->mac_set[0], ETH_ALEN);
+ memset((char *)&req->l2_addr_mask[0], 0xff, ETH_ALEN);
+ memcpy((char *)&req->t_l2_addr[0], (char *)&bp->mac_set[0], ETH_ALEN);
+ memset((char *)&req->t_l2_addr_mask[0], 0xff, ETH_ALEN);
+ req->src_type = CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT;
+ req->src_id = (u32)bp->port_idx;
+ req->dst_id = bp->vnic_id;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_SET(bp->flag_hwrm, VALID_L2_FILTER);
+ bp->l2_filter_id = resp->l2_filter_id;
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_cfa_l2_filter_free(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_filter_free_input);
+ struct hwrm_cfa_l2_filter_free_input *req;
+ int rc;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_L2_FILTER)))
+ return STATUS_SUCCESS;
+
+ req = (struct hwrm_cfa_l2_filter_free_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_FILTER_FREE, cmd_len);
+ req->l2_filter_id = bp->l2_filter_id;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_RESET(bp->flag_hwrm, VALID_L2_FILTER);
+
+ return STATUS_SUCCESS;
+}
+
+u32 bnxt_set_rx_mask(u32 rx_mask)
+{
+ u32 mask = 0;
+
+ if (!rx_mask)
+ return mask;
+ mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
+ if (rx_mask != RX_MASK_ACCEPT_NONE) {
+ if (rx_mask & RX_MASK_ACCEPT_MULTICAST)
+ mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
+
+ if (rx_mask & RX_MASK_ACCEPT_ALL_MULTICAST)
+ mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
+
+ if (rx_mask & RX_MASK_PROMISCUOUS_MODE)
+ mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
+ }
+
+ return mask;
+}
+
+static int bnxt_hwrm_set_rx_mask(struct bnxt *bp, u32 rx_mask)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_set_rx_mask_input);
+ struct hwrm_cfa_l2_set_rx_mask_input *req;
+ u32 mask = bnxt_set_rx_mask(rx_mask);
+
+ req = (struct hwrm_cfa_l2_set_rx_mask_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_SET_RX_MASK, cmd_len);
+ req->vnic_id = bp->vnic_id;
+ req->mask = mask;
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int bnxt_hwrm_port_mac_cfg(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_port_mac_cfg_input);
+ struct hwrm_port_mac_cfg_input *req;
+
+ req = (struct hwrm_port_mac_cfg_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_PORT_MAC_CFG, cmd_len);
+ req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp, u16 idx)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_port_phy_qcfg_input);
+ struct hwrm_port_phy_qcfg_input *req;
+ struct hwrm_port_phy_qcfg_output *resp;
+ int rc;
+
+ req = (struct hwrm_port_phy_qcfg_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_port_phy_qcfg_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_PORT_PHY_QCFG, cmd_len);
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ if (idx & SUPPORT_SPEEDS)
+ bp->support_speeds = resp->support_speeds;
+
+ if (idx & DETECT_MEDIA)
+ bp->media_detect = resp->module_status;
+
+ if (idx & PHY_SPEED)
+ bp->current_link_speed = resp->link_speed;
+
+ if (idx & PHY_STATUS) {
+ if (resp->link == PORT_PHY_QCFG_RESP_LINK_LINK)
+ bp->link_status = STATUS_LINK_ACTIVE;
+ else
+ bp->link_status = STATUS_LINK_DOWN;
+ }
+
+ return STATUS_SUCCESS;
+}
+
+u16 set_link_speed_mask(u16 link_cap)
+{
+ u16 speed_mask = 0;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_100M)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_1G)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_10G)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_25G)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_40G)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_50G)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB;
+
+ if (link_cap & SPEED_CAPABILITY_DRV_100G)
+ speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB;
+
+ return speed_mask;
+}
+
+static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_port_phy_cfg_input);
+ struct hwrm_port_phy_cfg_input *req;
+ u32 flags;
+ u32 enables = 0;
+ u16 force_link_speed = 0;
+ u16 auto_link_speed_mask = 0;
+ u8 auto_mode = 0;
+ u8 auto_pause = 0;
+ u8 auto_duplex = 0;
+
+ /*
+ * If multi_host or NPAR is set to TRUE,
+ * do not issue hwrm_port_phy_cfg
+ */
+ if (FLAG_TEST(bp->flags, PORT_PHY_FLAGS)) {
+ dbg_flags(__func__, bp->flags);
+ return STATUS_SUCCESS;
+ }
+
+ req = (struct hwrm_port_phy_cfg_input *)bp->hwrm_addr_req;
+ flags = PORT_PHY_CFG_REQ_FLAGS_FORCE |
+ PORT_PHY_CFG_REQ_FLAGS_RESET_PHY;
+
+ switch (GET_MEDIUM_SPEED(bp->medium)) {
+ case MEDIUM_SPEED_1000MBPS:
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
+ break;
+ case MEDIUM_SPEED_10GBPS:
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
+ break;
+ case MEDIUM_SPEED_25GBPS:
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
+ break;
+ case MEDIUM_SPEED_40GBPS:
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
+ break;
+ case MEDIUM_SPEED_50GBPS:
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
+ break;
+ case MEDIUM_SPEED_100GBPS:
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
+ break;
+ default:
+ /* Enable AUTONEG by default */
+ auto_mode = PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
+ flags &= ~PORT_PHY_CFG_REQ_FLAGS_FORCE;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE |
+ PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK |
+ PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX |
+ PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE;
+ auto_pause = PORT_PHY_CFG_REQ_AUTO_PAUSE_TX |
+ PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
+ auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH;
+ auto_link_speed_mask = bp->support_speeds;
+ break;
+ }
+
+ hwrm_init(bp, (void *)req, (u16)HWRM_PORT_PHY_CFG, cmd_len);
+ req->flags = flags;
+ req->enables = enables;
+ req->port_id = bp->port_idx;
+ req->force_link_speed = force_link_speed;
+ req->auto_mode = auto_mode;
+ req->auto_duplex = auto_duplex;
+ req->auto_pause = auto_pause;
+ req->auto_link_speed_mask = auto_link_speed_mask;
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int bnxt_qphy_link(struct bnxt *bp)
+{
+ u16 flag = QCFG_PHY_ALL;
+
+ /* Query Link Status */
+ if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
+ return STATUS_FAILURE;
+
+ if (bp->link_status != STATUS_LINK_ACTIVE) {
+ /*
+ * Configure link if it is not up.
+ * try to bring link up, but don't return
+ * failure if port_phy_cfg() fails
+ */
+ bnxt_hwrm_port_phy_cfg(bp);
+ /* refresh link speed values after bringing link up */
+ if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
+ return STATUS_FAILURE;
+ }
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_stat_ctx_alloc_input);
+ struct hwrm_stat_ctx_alloc_input *req;
+ struct hwrm_stat_ctx_alloc_output *resp;
+ int rc;
+
+ req = (struct hwrm_stat_ctx_alloc_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_stat_ctx_alloc_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_STAT_CTX_ALLOC, cmd_len);
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_SET(bp->flag_hwrm, VALID_STAT_CTX);
+ bp->stat_ctx_id = (u16)resp->stat_ctx_id;
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_stat_ctx_free_input);
+ struct hwrm_stat_ctx_free_input *req;
+ int rc;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_STAT_CTX)))
+ return STATUS_SUCCESS;
+
+ req = (struct hwrm_stat_ctx_free_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_STAT_CTX_FREE, cmd_len);
+ req->stat_ctx_id = (u32)bp->stat_ctx_id;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_RESET(bp->flag_hwrm, VALID_STAT_CTX);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_ring_free_grp(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_ring_grp_free_input);
+ struct hwrm_ring_grp_free_input *req;
+ int rc;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_GRP)))
+ return STATUS_SUCCESS;
+
+ req = (struct hwrm_ring_grp_free_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_RING_GRP_FREE, cmd_len);
+ req->ring_group_id = (u32)bp->ring_grp_id;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_RESET(bp->flag_hwrm, VALID_RING_GRP);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_ring_alloc_grp(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_ring_grp_alloc_input);
+ struct hwrm_ring_grp_alloc_input *req;
+ struct hwrm_ring_grp_alloc_output *resp;
+ int rc;
+
+ req = (struct hwrm_ring_grp_alloc_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_ring_grp_alloc_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_RING_GRP_ALLOC, cmd_len);
+ req->cr = bp->cq_ring_id;
+ req->rr = bp->rx_ring_id;
+ req->ar = (u16)HWRM_NA_SIGNATURE;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_SET(bp->flag_hwrm, VALID_RING_GRP);
+ bp->ring_grp_id = (u16)resp->ring_group_id;
+
+ return STATUS_SUCCESS;
+}
+
+int bnxt_hwrm_ring_free(struct bnxt *bp, u16 ring_id, u8 ring_type)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_ring_free_input);
+ struct hwrm_ring_free_input *req;
+
+ req = (struct hwrm_ring_free_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_RING_FREE, cmd_len);
+ req->ring_type = ring_type;
+ req->ring_id = ring_id;
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int bnxt_hwrm_ring_alloc(struct bnxt *bp,
+ dma_addr_t ring_map,
+ u16 length,
+ u16 ring_id,
+ u8 ring_type,
+ u8 int_mode)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_ring_alloc_input);
+ struct hwrm_ring_alloc_input *req;
+ struct hwrm_ring_alloc_output *resp;
+ int rc;
+
+ req = (struct hwrm_ring_alloc_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_ring_alloc_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_RING_ALLOC, cmd_len);
+ req->ring_type = ring_type;
+ req->page_tbl_addr = ring_map;
+ req->page_size = LM_PAGE_SIZE;
+ req->length = (u32)length;
+ req->cmpl_ring_id = ring_id;
+ req->int_mode = int_mode;
+ if (ring_type == RING_ALLOC_REQ_RING_TYPE_TX) {
+ req->queue_id = TX_RING_QID;
+ } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_RX) {
+ req->queue_id = RX_RING_QID;
+ req->enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID;
+ req->rx_buf_size = MAX_ETHERNET_PACKET_BUFFER_SIZE;
+ }
+
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ if (ring_type == RING_ALLOC_REQ_RING_TYPE_L2_CMPL) {
+ FLAG_SET(bp->flag_hwrm, VALID_RING_CQ);
+ bp->cq_ring_id = resp->ring_id;
+ } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_TX) {
+ FLAG_SET(bp->flag_hwrm, VALID_RING_TX);
+ bp->tx_ring_id = resp->ring_id;
+ } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_RX) {
+ FLAG_SET(bp->flag_hwrm, VALID_RING_RX);
+ bp->rx_ring_id = resp->ring_id;
+ }
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_ring_alloc_cq(struct bnxt *bp)
+{
+ return bnxt_hwrm_ring_alloc(bp,
+ virt_to_bus(bp->cq.bd_virt),
+ bp->cq.ring_cnt,
+ 0,
+ RING_ALLOC_REQ_RING_TYPE_L2_CMPL,
+ BNXT_CQ_INTR_MODE());
+}
+
+static int bnxt_hwrm_ring_alloc_tx(struct bnxt *bp)
+{
+ return bnxt_hwrm_ring_alloc(bp,
+ virt_to_bus(bp->tx.bd_virt),
+ bp->tx.ring_cnt, bp->cq_ring_id,
+ RING_ALLOC_REQ_RING_TYPE_TX,
+ BNXT_INTR_MODE());
+}
+
+static int bnxt_hwrm_ring_alloc_rx(struct bnxt *bp)
+{
+ return bnxt_hwrm_ring_alloc(bp,
+ virt_to_bus(bp->rx.bd_virt),
+ bp->rx.ring_cnt,
+ bp->cq_ring_id,
+ RING_ALLOC_REQ_RING_TYPE_RX,
+ BNXT_INTR_MODE());
+}
+
+static int bnxt_hwrm_ring_free_cq(struct bnxt *bp)
+{
+ int ret = STATUS_SUCCESS;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_CQ)))
+ return ret;
+
+ ret = RING_FREE(bp, bp->cq_ring_id, RING_FREE_REQ_RING_TYPE_L2_CMPL);
+ if (ret == STATUS_SUCCESS)
+ FLAG_RESET(bp->flag_hwrm, VALID_RING_CQ);
+
+ return ret;
+}
+
+static int bnxt_hwrm_ring_free_tx(struct bnxt *bp)
+{
+ int ret = STATUS_SUCCESS;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_TX)))
+ return ret;
+
+ ret = RING_FREE(bp, bp->tx_ring_id, RING_FREE_REQ_RING_TYPE_TX);
+ if (ret == STATUS_SUCCESS)
+ FLAG_RESET(bp->flag_hwrm, VALID_RING_TX);
+
+ return ret;
+}
+
+static int bnxt_hwrm_ring_free_rx(struct bnxt *bp)
+{
+ int ret = STATUS_SUCCESS;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_RX)))
+ return ret;
+
+ ret = RING_FREE(bp, bp->rx_ring_id, RING_FREE_REQ_RING_TYPE_RX);
+ if (ret == STATUS_SUCCESS)
+ FLAG_RESET(bp->flag_hwrm, VALID_RING_RX);
+
+ return ret;
+}
+
+static int bnxt_hwrm_vnic_alloc(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_vnic_alloc_input);
+ struct hwrm_vnic_alloc_input *req;
+ struct hwrm_vnic_alloc_output *resp;
+ int rc;
+
+ req = (struct hwrm_vnic_alloc_input *)bp->hwrm_addr_req;
+ resp = (struct hwrm_vnic_alloc_output *)bp->hwrm_addr_resp;
+ hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_ALLOC, cmd_len);
+ req->flags = VNIC_ALLOC_REQ_FLAGS_DEFAULT;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_SET(bp->flag_hwrm, VALID_VNIC_ID);
+ bp->vnic_id = resp->vnic_id;
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_vnic_free(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_vnic_free_input);
+ struct hwrm_vnic_free_input *req;
+ int rc;
+
+ if (!(FLAG_TEST(bp->flag_hwrm, VALID_VNIC_ID)))
+ return STATUS_SUCCESS;
+
+ req = (struct hwrm_vnic_free_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_FREE, cmd_len);
+ req->vnic_id = bp->vnic_id;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+ if (rc)
+ return STATUS_FAILURE;
+
+ FLAG_RESET(bp->flag_hwrm, VALID_VNIC_ID);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_vnic_cfg(struct bnxt *bp)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_vnic_cfg_input);
+ struct hwrm_vnic_cfg_input *req;
+
+ req = (struct hwrm_vnic_cfg_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_CFG, cmd_len);
+ req->enables = VNIC_CFG_REQ_ENABLES_MRU;
+ req->mru = bp->mtu;
+ req->enables |= VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP;
+ req->dflt_ring_grp = bp->ring_grp_id;
+ req->vnic_id = bp->vnic_id;
+
+ return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+}
+
+static int set_phy_speed(struct bnxt *bp)
+{
+ char name[20];
+ u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA;
+
+ /* Query Link Status */
+ if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
+ return STATUS_FAILURE;
+
+ switch (bp->current_link_speed) {
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_100GB:
+ sprintf(name, "%s %s", str_100, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_50GB:
+ sprintf(name, "%s %s", str_50, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_40GB:
+ sprintf(name, "%s %s", str_40, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_25GB:
+ sprintf(name, "%s %s", str_25, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_20GB:
+ sprintf(name, "%s %s", str_20, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_10GB:
+ sprintf(name, "%s %s", str_10, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB:
+ sprintf(name, "%s %s", str_2_5, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_2GB:
+ sprintf(name, "%s %s", str_2, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_1GB:
+ sprintf(name, "%s %s", str_1, str_gbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_100MB:
+ sprintf(name, "%s %s", str_100, str_mbps);
+ break;
+ case PORT_PHY_QCFG_RESP_LINK_SPEED_10MB:
+ sprintf(name, "%s %s", str_10, str_mbps);
+ break;
+ default:
+ sprintf(name, "%s %x", str_unknown, bp->current_link_speed);
+ }
+
+ dbg_phy_speed(bp, name);
+
+ return STATUS_SUCCESS;
+}
+
+static int set_phy_link(struct bnxt *bp, u32 tmo)
+{
+ int ret;
+
+ set_phy_speed(bp);
+ dbg_link_status(bp);
+ ret = STATUS_FAILURE;
+ if (bp->link_status == STATUS_LINK_ACTIVE) {
+ dbg_link_state(bp, tmo);
+ ret = STATUS_SUCCESS;
+ }
+
+ return ret;
+}
+
+static int get_phy_link(struct bnxt *bp)
+{
+ u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA;
+
+ dbg_chip_info(bp);
+ /* Query Link Status */
+ if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS)
+ return STATUS_FAILURE;
+
+ set_phy_link(bp, 100);
+
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_hwrm_set_async_event(struct bnxt *bp)
+{
+ int rc;
+ u16 cmd_len = (u16)sizeof(struct hwrm_func_cfg_input);
+ struct hwrm_func_cfg_input *req;
+
+ req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_CFG, cmd_len);
+ req->fid = (u16)HWRM_NA_SIGNATURE;
+ req->enables = FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR;
+ req->async_event_cr = bp->cq_ring_id;
+ rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__);
+
+ return rc;
+}
+
+int bnxt_hwrm_get_nvmem(struct bnxt *bp,
+ u16 data_len,
+ u16 option_num,
+ u16 dimensions,
+ u16 index_0)
+{
+ u16 cmd_len = (u16)sizeof(struct hwrm_nvm_get_variable_input);
+ struct hwrm_nvm_get_variable_input *req;
+
+ req = (struct hwrm_nvm_get_variable_input *)bp->hwrm_addr_req;
+ hwrm_init(bp, (void *)req, (u16)HWRM_NVM_GET_VARIABLE, cmd_len);
+ req->dest_data_addr = bp->data_addr_mapping;
+ req->data_len = data_len;
+ req->option_num = option_num;
+ req->dimensions = dimensions;
+ req->index_0 = index_0;
+
+ return wait_resp(bp,
+ HWRM_CMD_FLASH_MULTIPLAYER(bp->hwrm_cmd_timeout),
+ cmd_len,
+ __func__);
+}
+
+static void set_medium(struct bnxt *bp)
+{
+ switch (bp->link_set & LINK_SPEED_DRV_MASK) {
+ case LINK_SPEED_DRV_1G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_1000MBPS);
+ break;
+ case LINK_SPEED_DRV_2_5G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_2500MBPS);
+ break;
+ case LINK_SPEED_DRV_10G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_10GBPS);
+ break;
+ case LINK_SPEED_DRV_25G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_25GBPS);
+ break;
+ case LINK_SPEED_DRV_40G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_40GBPS);
+ break;
+ case LINK_SPEED_DRV_50G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_50GBPS);
+ break;
+ case LINK_SPEED_DRV_100G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_100GBPS);
+ break;
+ case LINK_SPEED_DRV_200G:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_200GBPS);
+ break;
+ case LINK_SPEED_DRV_AUTONEG:
+ bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_AUTONEG);
+ break;
+ default:
+ bp->medium = SET_MEDIUM_DUPLEX(bp, MEDIUM_FULL_DUPLEX);
+ break;
+ }
+}
+
+static int bnxt_hwrm_get_link_speed(struct bnxt *bp)
+{
+ u32 *ptr32 = (u32 *)bp->hwrm_addr_data;
+
+ if (bnxt_hwrm_get_nvmem(bp,
+ 4,
+ (u16)LINK_SPEED_DRV_NUM,
+ 1,
+ (u16)bp->port_idx) != STATUS_SUCCESS)
+ return STATUS_FAILURE;
+
+ bp->link_set = *ptr32;
+ bp->link_set &= SPEED_DRV_MASK;
+ set_medium(bp);
+
+ return STATUS_SUCCESS;
+}
+
+typedef int (*hwrm_func_t)(struct bnxt *bp);
+
+hwrm_func_t down_chip[] = {
+ bnxt_hwrm_cfa_l2_filter_free, /* Free l2 filter */
+ bnxt_free_rx_iob, /* Free rx iob */
+ bnxt_hwrm_vnic_free, /* Free vnic */
+ bnxt_hwrm_ring_free_grp, /* Free ring group */
+ bnxt_hwrm_ring_free_rx, /* Free rx ring */
+ bnxt_hwrm_ring_free_tx, /* Free tx ring */
+ bnxt_hwrm_ring_free_cq, /* Free CQ ring */
+ bnxt_hwrm_stat_ctx_free, /* Free Stat ctx */
+ bnxt_hwrm_func_drv_unrgtr, /* unreg driver */
+ NULL,
+};
+
+hwrm_func_t bring_chip[] = {
+ bnxt_hwrm_ver_get, /* HWRM_VER_GET */
+ bnxt_hwrm_func_reset_req, /* HWRM_FUNC_RESET */
+ bnxt_hwrm_func_drv_rgtr, /* HWRM_FUNC_DRV_RGTR */
+ bnxt_hwrm_func_resource_qcaps, /* HWRM_FUNC_RESOURCE_QCAPS */
+ bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
+ bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */
+ bnxt_hwrm_get_link_speed, /* HWRM_NVM_GET_VARIABLE - 203 */
+ bnxt_hwrm_port_mac_cfg, /* HWRM_PORT_MAC_CFG */
+ bnxt_qphy_link, /* HWRM_PORT_PHY_QCFG */
+ bnxt_hwrm_func_cfg_req, /* HWRM_FUNC_CFG - ring resource*/
+ bnxt_hwrm_stat_ctx_alloc, /* Allocate Stat Ctx ID */
+ bnxt_hwrm_ring_alloc_cq, /* Allocate CQ Ring */
+ bnxt_hwrm_ring_alloc_tx, /* Allocate Tx ring */
+ bnxt_hwrm_ring_alloc_rx, /* Allocate Rx Ring */
+ bnxt_hwrm_ring_alloc_grp, /* Create Ring Group */
+ post_rx_buffers, /* Post RX buffers */
+ bnxt_hwrm_set_async_event, /* ENABLES_ASYNC_EVENT_CR */
+ bnxt_hwrm_vnic_alloc, /* Alloc VNIC */
+ bnxt_hwrm_vnic_cfg, /* Config VNIC */
+ bnxt_hwrm_cfa_l2_filter_alloc, /* Alloc L2 Filter */
+ get_phy_link, /* Get Physical Link */
+ NULL,
+};
+
+int bnxt_hwrm_run(hwrm_func_t cmds[], struct bnxt *bp, int flag)
+{
+ hwrm_func_t *ptr;
+ int ret;
+ int status = STATUS_SUCCESS;
+
+ for (ptr = cmds; *ptr; ++ptr) {
+ ret = (*ptr)(bp);
+ if (ret) {
+ status = STATUS_FAILURE;
+ /* Continue till all cleanup routines are called */
+ if (flag)
+ return STATUS_FAILURE;
+ }
+ }
+
+ return status;
+}
+
+/* Broadcom ethernet driver Network interface APIs. */
+static int bnxt_start(struct udevice *dev)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+
+ if (bnxt_hwrm_set_rx_mask(bp, RX_MASK) != STATUS_SUCCESS)
+ return STATUS_FAILURE;
+
+ bp->card_en = true;
+ return STATUS_SUCCESS;
+}
+
+static int bnxt_send(struct udevice *dev, void *packet, int length)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+ int len;
+ u16 entry;
+ dma_addr_t mapping;
+
+ if (bnxt_tx_avail(bp) < 1) {
+ dbg_no_tx_bd();
+ return -ENOBUFS;
+ }
+
+ entry = bp->tx.prod_id;
+ len = iob_pad(packet, length);
+ mapping = virt_to_bus(packet);
+ set_txq(bp, entry, mapping, len);
+ entry = NEXT_IDX(entry, bp->tx.ring_cnt);
+ dump_tx_pkt(packet, mapping, len);
+ bnxt_db_tx(bp, (u32)entry);
+ bp->tx.prod_id = entry;
+ bp->tx.cnt_req++;
+ bnxt_tx_complete(bp);
+
+ return 0;
+}
+
+static void bnxt_link_evt(struct bnxt *bp, struct cmpl_base *cmp)
+{
+ struct hwrm_async_event_cmpl *evt;
+
+ evt = (struct hwrm_async_event_cmpl *)cmp;
+ switch (evt->event_id) {
+ case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
+ if (evt->event_data1 & 0x01)
+ bp->link_status = STATUS_LINK_ACTIVE;
+ else
+ bp->link_status = STATUS_LINK_DOWN;
+
+ set_phy_link(bp, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+static int bnxt_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+ struct cmpl_base *cmp;
+ u16 old_cons_idx = bp->cq.cons_idx;
+ int done = SERVICE_NEXT_CQ_BD;
+ u32 cq_type;
+
+ while (done == SERVICE_NEXT_CQ_BD) {
+ cmp = (struct cmpl_base *)BD_NOW(bp->cq.bd_virt,
+ bp->cq.cons_idx,
+ sizeof(struct cmpl_base));
+ if ((cmp->info3_v & CMPL_BASE_V) ^ bp->cq.completion_bit)
+ break;
+
+ cq_type = cmp->type & CMPL_BASE_TYPE_MASK;
+ dump_evt((u8 *)cmp, cq_type, bp->cq.cons_idx);
+ dump_CQ(cmp, bp->cq.cons_idx);
+ switch (cq_type) {
+ case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
+ bnxt_link_evt(bp, cmp);
+ fallthrough;
+ case CMPL_BASE_TYPE_TX_L2:
+ case CMPL_BASE_TYPE_STAT_EJECT:
+ bnxt_adv_cq_index(bp, 1);
+ break;
+ case CMPL_BASE_TYPE_RX_L2:
+ done = bnxt_rx_complete(bp, (struct rx_pkt_cmpl *)cmp);
+ break;
+ default:
+ done = NO_MORE_CQ_BD_TO_SERVICE;
+ break;
+ }
+ }
+
+ if (bp->cq.cons_idx != old_cons_idx)
+ bnxt_db_cq(bp);
+
+ if (bp->rx.iob_recv == PKT_RECEIVED) {
+ *packetp = bp->rx.iob_rx;
+ return bp->rx.iob_len;
+ }
+
+ return -EAGAIN;
+}
+
+static void bnxt_stop(struct udevice *dev)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+
+ if (bp->card_en) {
+ bnxt_hwrm_set_rx_mask(bp, 0);
+ bp->card_en = false;
+ }
+}
+
+static int bnxt_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+
+ dbg_rx_pkt(bp, __func__, packet, length);
+ bp->rx.iob_recv = PKT_DONE;
+ bp->rx.iob_len = 0;
+ bp->rx.iob_rx = NULL;
+
+ return 0;
+}
+
+static int bnxt_read_rom_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_plat(dev);
+ struct bnxt *bp = dev_get_priv(dev);
+
+ memcpy(plat->enetaddr, bp->mac_set, ETH_ALEN);
+
+ return 0;
+}
+
+static const struct eth_ops bnxt_eth_ops = {
+ .start = bnxt_start,
+ .send = bnxt_send,
+ .recv = bnxt_recv,
+ .stop = bnxt_stop,
+ .free_pkt = bnxt_free_pkt,
+ .read_rom_hwaddr = bnxt_read_rom_hwaddr,
+};
+
+static const struct udevice_id bnxt_eth_ids[] = {
+ { .compatible = "broadcom,nxe" },
+ { }
+};
+
+static int bnxt_eth_bind(struct udevice *dev)
+{
+ char name[20];
+
+ sprintf(name, "bnxt_eth%u", dev_seq(dev));
+
+ return device_set_name(dev, name);
+}
+
+static int bnxt_eth_probe(struct udevice *dev)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+ int ret;
+
+ ret = bnxt_alloc_mem(bp);
+ if (ret) {
+ printf("*** error: bnxt_alloc_mem failed! ***\n");
+ return ret;
+ }
+
+ bp->cardnum = dev_seq(dev);
+ bp->name = dev->name;
+ bp->pdev = (struct udevice *)dev;
+
+ bnxt_bring_pci(bp);
+
+ ret = bnxt_bring_chip(bp);
+ if (ret) {
+ printf("*** error: bnxt_bring_chip failed! ***\n");
+ return -ENODATA;
+ }
+
+ return 0;
+}
+
+static int bnxt_eth_remove(struct udevice *dev)
+{
+ struct bnxt *bp = dev_get_priv(dev);
+
+ bnxt_down_chip(bp);
+ bnxt_free_mem(bp);
+
+ return 0;
+}
+
+static struct pci_device_id bnxt_nics[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NXT_57320)},
+ {}
+};
+
+U_BOOT_DRIVER(eth_bnxt) = {
+ .name = "eth_bnxt",
+ .id = UCLASS_ETH,
+ .of_match = bnxt_eth_ids,
+ .bind = bnxt_eth_bind,
+ .probe = bnxt_eth_probe,
+ .remove = bnxt_eth_remove,
+ .ops = &bnxt_eth_ops,
+ .priv_auto = sizeof(struct bnxt),
+ .plat_auto = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ACTIVE_DMA,
+};
+
+U_BOOT_PCI_DEVICE(eth_bnxt, bnxt_nics);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019-2021 Broadcom.
+ */
+
+#ifndef _BNXT_H_
+#define _BNXT_H_
+
+#include <pci.h>
+#include <linux/if_ether.h>
+
+#include "bnxt_hsi.h"
+
+union dma_addr64_t {
+ dma_addr_t addr;
+ u64 as_u64;
+};
+
+#define DRIVER_VERSION_MAJOR 1
+#define DRIVER_VERSION_MINOR 0
+#define DRIVER_VERSION_UPDATE 0
+
+/* Broadcom ethernet driver defines. */
+#define FLAG_SET(f, b) ((f) |= (b))
+#define FLAG_TEST(f, b) ((f) & (b))
+#define FLAG_RESET(f, b) ((f) &= ~(b))
+#define BNXT_FLAG_HWRM_SHORT_CMD_SUPP BIT(0)
+#define BNXT_FLAG_HWRM_SHORT_CMD_REQ BIT(1)
+#define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT BIT(2)
+#define BNXT_FLAG_MULTI_HOST BIT(3)
+#define BNXT_FLAG_NPAR_MODE BIT(4)
+/*******************************************************************************
+ * Status codes.
+ ******************************************************************************/
+#define STATUS_SUCCESS 0
+#define STATUS_FAILURE 1
+#define STATUS_LINK_ACTIVE 4
+#define STATUS_LINK_DOWN 5
+#define STATUS_TIMEOUT 0xffff
+/*******************************************************************************
+ * Receive filter masks.
+ ******************************************************************************/
+#define RX_MASK_ACCEPT_NONE 0x0000
+#define RX_MASK_ACCEPT_MULTICAST 0x0002
+#define RX_MASK_ACCEPT_ALL_MULTICAST 0x0004
+#define RX_MASK_ACCEPT_BROADCAST 0x0008
+#define RX_MASK_PROMISCUOUS_MODE 0x10000
+/*******************************************************************************
+ * media speed.
+ ******************************************************************************/
+#define MEDIUM_SPEED_AUTONEG 0x0000L
+#define MEDIUM_SPEED_1000MBPS 0x0300L
+#define MEDIUM_SPEED_2500MBPS 0x0400L
+#define MEDIUM_SPEED_10GBPS 0x0600L
+#define MEDIUM_SPEED_25GBPS 0x0800L
+#define MEDIUM_SPEED_40GBPS 0x0900L
+#define MEDIUM_SPEED_50GBPS 0x0a00L
+#define MEDIUM_SPEED_100GBPS 0x0b00L
+#define MEDIUM_SPEED_200GBPS 0x0c00L
+#define MEDIUM_SPEED_MASK 0xff00L
+#define GET_MEDIUM_SPEED(m) ((m) & MEDIUM_SPEED_MASK)
+#define SET_MEDIUM_SPEED(bp, s) (((bp)->medium & ~MEDIUM_SPEED_MASK) | (s))
+#define MEDIUM_UNKNOWN_DUPLEX 0x00000L
+#define MEDIUM_FULL_DUPLEX 0x00000L
+#define MEDIUM_HALF_DUPLEX 0x10000L
+#define GET_MEDIUM_DUPLEX(m) ((m) & MEDIUM_HALF_DUPLEX)
+#define SET_MEDIUM_DUPLEX(bp, d) (((bp)->medium & ~MEDIUM_HALF_DUPLEX) | (d))
+#define MEDIUM_SELECTIVE_AUTONEG 0x01000000L
+#define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000L)
+#define GRC_COM_CHAN_BASE 0
+#define GRC_COM_CHAN_TRIG 0x100
+#define HWRM_CMD_DEFAULT_TIMEOUT 500 /* in Miliseconds */
+#define HWRM_CMD_POLL_WAIT_TIME 100 /* In MicroeSconds */
+#define HWRM_CMD_DEFAULT_MULTIPLAYER(a) ((a) * 10)
+#define HWRM_CMD_FLASH_MULTIPLAYER(a) ((a) * 100)
+#define HWRM_CMD_FLASH_ERASE_MULTIPLAYER(a) ((a) * 1000)
+#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536
+#define DEFAULT_NUMBER_OF_CMPL_RINGS 0x01
+#define DEFAULT_NUMBER_OF_TX_RINGS 0x01
+#define DEFAULT_NUMBER_OF_RX_RINGS 0x01
+#define DEFAULT_NUMBER_OF_RING_GRPS 0x01
+#define DEFAULT_NUMBER_OF_STAT_CTXS 0x01
+#define NUM_RX_BUFFERS 512
+#define MAX_RX_DESC_CNT 1024
+#define MAX_TX_DESC_CNT 512
+#define MAX_CQ_DESC_CNT 2048
+#define TX_RING_DMA_BUFFER_SIZE (MAX_TX_DESC_CNT * sizeof(struct tx_bd_short))
+#define RX_RING_DMA_BUFFER_SIZE \
+ (MAX_RX_DESC_CNT * sizeof(struct rx_prod_pkt_bd))
+#define CQ_RING_DMA_BUFFER_SIZE (MAX_CQ_DESC_CNT * sizeof(struct cmpl_base))
+#define BNXT_DMA_ALIGNMENT 256 //64
+#define REQ_BUFFER_SIZE 1024
+#define RESP_BUFFER_SIZE 1024
+#define DMA_BUFFER_SIZE 1024
+#define LM_PAGE_BITS 8
+#define BNXT_RX_STD_DMA_SZ 1536
+#define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1))
+#define BD_NOW(bd, entry, len) (&((u8 *)(bd))[(entry) * (len)])
+#define BNXT_CQ_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL
+#define BNXT_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL
+/* Set default link timeout period to 500 millseconds */
+#define LINK_DEFAULT_TIMEOUT 500
+#define RX_MASK \
+ (RX_MASK_ACCEPT_BROADCAST | \
+ RX_MASK_ACCEPT_ALL_MULTICAST | \
+ RX_MASK_ACCEPT_MULTICAST)
+#define TX_RING_QID ((u16)bp->port_idx * 10)
+#define RX_RING_QID 0
+#define LM_PAGE_SIZE LM_PAGE_BITS
+#define virt_to_bus(a) ((dma_addr_t)(a))
+#define REQ_BUF_SIZE_ALIGNED ALIGN(REQ_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
+#define RESP_BUF_SIZE_ALIGNED ALIGN(RESP_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
+#define DMA_BUF_SIZE_ALIGNED ALIGN(DMA_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
+#define RX_STD_DMA_ALIGNED ALIGN(BNXT_RX_STD_DMA_SZ, BNXT_DMA_ALIGNMENT)
+#define PCI_COMMAND_INTX_DISABLE 0x0400 /* Interrupt disable */
+#define TX_AVAIL(r) ((r) - 1)
+#define NO_MORE_CQ_BD_TO_SERVICE 1
+#define SERVICE_NEXT_CQ_BD 0
+#define PHY_STATUS 0x0001
+#define PHY_SPEED 0x0002
+#define DETECT_MEDIA 0x0004
+#define SUPPORT_SPEEDS 0x0008
+#define str_1 "1"
+#define str_2 "2"
+#define str_2_5 "2.5"
+#define str_10 "10"
+#define str_20 "20"
+#define str_25 "25"
+#define str_40 "40"
+#define str_50 "50"
+#define str_100 "100"
+#define str_gbps "Gbps"
+#define str_mbps "Mbps"
+#define str_unknown "Unknown"
+/* Broadcom ethernet driver nvm defines. */
+/* nvm cfg 1 - MAC settings */
+#define FUNC_MAC_ADDR_NUM 1
+/* nvm cfg 203 - u32 link_settings */
+#define LINK_SPEED_DRV_NUM 203
+#define LINK_SPEED_DRV_MASK 0x0000000F
+#define LINK_SPEED_DRV_SHIFT 0
+#define LINK_SPEED_DRV_AUTONEG 0x0
+#define LINK_SPEED_DRV_1G 0x1
+#define LINK_SPEED_DRV_10G 0x2
+#define LINK_SPEED_DRV_25G 0x3
+#define LINK_SPEED_DRV_40G 0x4
+#define LINK_SPEED_DRV_50G 0x5
+#define LINK_SPEED_DRV_100G 0x6
+#define LINK_SPEED_DRV_200G 0x7
+#define LINK_SPEED_DRV_2_5G 0xE
+#define LINK_SPEED_DRV_100M 0xF
+/* nvm cfg 201 - u32 speed_cap_mask */
+#define SPEED_CAPABILITY_DRV_1G 0x1
+#define SPEED_CAPABILITY_DRV_10G 0x2
+#define SPEED_CAPABILITY_DRV_25G 0x4
+#define SPEED_CAPABILITY_DRV_40G 0x8
+#define SPEED_CAPABILITY_DRV_50G 0x10
+#define SPEED_CAPABILITY_DRV_100G 0x20
+#define SPEED_CAPABILITY_DRV_100M 0x8000
+/* nvm cfg 202 */
+/* nvm cfg 205 */
+#define LINK_SPEED_FW_NUM 205
+/* nvm cfg 210 */
+/* nvm cfg 211 */
+/* nvm cfg 213 */
+#define SPEED_DRV_MASK LINK_SPEED_DRV_MASK
+/******************************************************************************
+ * Doorbell info.
+ *****************************************************************************/
+#define RX_DOORBELL_KEY_RX (0x1UL << 28)
+#define TX_DOORBELL_KEY_TX (0x0UL << 28)
+
+#define CMPL_DOORBELL_IDX_VALID 0x4000000UL
+#define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
+
+/******************************************************************************
+ * Transmit info.
+ *****************************************************************************/
+struct tx_bd_short {
+ u16 flags_type;
+#define TX_BD_SHORT_TYPE_TX_BD_SHORT 0x0UL
+#define TX_BD_SHORT_FLAGS_PACKET_END 0x40UL
+#define TX_BD_SHORT_FLAGS_NO_CMPL 0x80UL
+#define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
+#define TX_BD_SHORT_FLAGS_LHINT_LT512 (0x0UL << 13)
+#define TX_BD_SHORT_FLAGS_LHINT_LT1K (0x1UL << 13)
+#define TX_BD_SHORT_FLAGS_LHINT_LT2K (0x2UL << 13)
+#define TX_BD_SHORT_FLAGS_LHINT_GTE2K (0x3UL << 13)
+#define TX_BD_SHORT_FLAGS_COAL_NOW 0x8000UL
+ u16 len;
+ u32 opaque;
+ union dma_addr64_t dma;
+};
+
+struct lm_tx_info_t {
+ void *bd_virt;
+ u16 prod_id; /* Tx producer index. */
+ u16 cons_id;
+ u16 ring_cnt;
+ u32 cnt; /* Tx statistics. */
+ u32 cnt_req;
+};
+
+struct cmpl_base {
+ u16 type;
+#define CMPL_BASE_TYPE_MASK 0x3fUL
+#define CMPL_BASE_TYPE_TX_L2 0x0UL
+#define CMPL_BASE_TYPE_RX_L2 0x11UL
+#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
+#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
+ u16 info1;
+ u32 info2;
+ u32 info3_v;
+#define CMPL_BASE_V 0x1UL
+ u32 info4;
+};
+
+struct lm_cmp_info_t {
+ void *bd_virt;
+ u16 cons_idx;
+ u16 ring_cnt;
+ u8 completion_bit;
+ u8 res[3];
+};
+
+struct rx_pkt_cmpl {
+ u16 flags_type;
+ u16 len;
+ u32 opaque;
+ u8 agg_bufs_v1;
+ u8 rss_hash_type;
+ u8 payload_offset;
+ u8 unused1;
+ u32 rss_hash;
+};
+
+struct rx_pkt_cmpl_hi {
+ u32 flags2;
+ u32 metadata;
+ u16 errors_v2;
+#define RX_PKT_CMPL_V2 0x1UL
+#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ u16 cfa_code;
+ u32 reorder;
+};
+
+struct rx_prod_pkt_bd {
+ u16 flags_type;
+#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT 0x4UL
+ u16 len;
+ u32 opaque;
+ union dma_addr64_t dma;
+};
+
+struct lm_rx_info_t {
+ void *bd_virt;
+ void *iob[NUM_RX_BUFFERS];
+ void *iob_rx;
+ u16 iob_len;
+ u16 iob_recv;
+ u16 iob_cnt;
+ u16 buf_cnt; /* Total Rx buffer descriptors. */
+ u16 ring_cnt;
+ u16 cons_idx; /* Last processed consumer index. */
+ u32 rx_cnt;
+ u32 rx_buf_cnt;
+ u32 err;
+ u32 crc;
+ u32 dropped;
+};
+
+#define VALID_DRIVER_REG 0x0001
+#define VALID_STAT_CTX 0x0002
+#define VALID_RING_CQ 0x0004
+#define VALID_RING_TX 0x0008
+#define VALID_RING_RX 0x0010
+#define VALID_RING_GRP 0x0020
+#define VALID_VNIC_ID 0x0040
+#define VALID_RX_IOB 0x0080
+#define VALID_L2_FILTER 0x0100
+
+enum RX_FLAGS {
+ PKT_DONE = 0,
+ PKT_RECEIVED = 1,
+ PKT_DROPPED = 2,
+};
+
+struct bnxt {
+ struct udevice *pdev;
+ const char *name;
+ unsigned int cardnum;
+ void *hwrm_addr_req;
+ void *hwrm_addr_resp;
+ void *hwrm_addr_data;
+ dma_addr_t data_addr_mapping;
+ dma_addr_t req_addr_mapping;
+ dma_addr_t resp_addr_mapping;
+ struct lm_tx_info_t tx; /* Tx info. */
+ struct lm_rx_info_t rx; /* Rx info. */
+ struct lm_cmp_info_t cq; /* completion info. */
+ u16 last_resp_code;
+ u16 seq_id;
+ u32 flag_hwrm;
+ u32 flags;
+ u16 vendor_id;
+ u16 device_id;
+ u16 subsystem_vendor;
+ u16 subsystem_device;
+ u16 cmd_reg;
+ u8 irq;
+ void __iomem *bar0;
+ void __iomem *bar1;
+ void __iomem *bar2;
+ u16 chip_num;
+ /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+ u32 chip_id;
+ u32 hwrm_cmd_timeout;
+ u16 hwrm_spec_code;
+ u16 hwrm_max_req_len;
+ u16 hwrm_max_ext_req_len;
+ u8 fw_maj;
+ u8 fw_min;
+ u8 fw_bld;
+ u8 fw_rsvd;
+ u8 mac_addr[ETH_ALEN]; /* HW MAC address */
+ u8 mac_set[ETH_ALEN]; /* NVM Configured MAC */
+ u16 fid;
+ u8 port_idx;
+ u8 ordinal_value;
+ u16 mtu;
+ u16 ring_grp_id;
+ u16 cq_ring_id;
+ u16 tx_ring_id;
+ u16 rx_ring_id;
+ u16 current_link_speed;
+ u16 link_status;
+ u16 wait_link_timeout;
+ u64 l2_filter_id;
+ u16 vnic_id;
+ u16 stat_ctx_id;
+ u32 medium;
+ u16 support_speeds;
+ u32 link_set;
+ u8 media_detect;
+ u8 media_change;
+ u16 max_vfs;
+ u16 vf_res_strategy;
+ u16 min_vnics;
+ u16 max_vnics;
+ u16 max_msix;
+ u16 min_hw_ring_grps;
+ u16 max_hw_ring_grps;
+ u16 min_tx_rings;
+ u16 max_tx_rings;
+ u16 min_rx_rings;
+ u16 max_rx_rings;
+ u16 min_cp_rings;
+ u16 max_cp_rings;
+ u16 min_rsscos_ctxs;
+ u16 max_rsscos_ctxs;
+ u16 min_l2_ctxs;
+ u16 max_l2_ctxs;
+ u16 min_stat_ctxs;
+ u16 max_stat_ctxs;
+ u16 num_cmpl_rings;
+ u16 num_tx_rings;
+ u16 num_rx_rings;
+ u16 num_stat_ctxs;
+ u16 num_hw_ring_grps;
+ bool card_en;
+};
+
+#define SHORT_CMD_SUPPORTED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
+#define SHORT_CMD_REQUIRED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
+#define CQ_DOORBELL_KEY_IDX(a) \
+ (CMPL_DOORBELL_KEY_CMPL | \
+ CMPL_DOORBELL_IDX_VALID | \
+ (u32)(a))
+#define TX_BD_FLAGS \
+ (TX_BD_SHORT_TYPE_TX_BD_SHORT | \
+ TX_BD_SHORT_FLAGS_NO_CMPL | \
+ TX_BD_SHORT_FLAGS_COAL_NOW | \
+ TX_BD_SHORT_FLAGS_PACKET_END | \
+ (1 << TX_BD_SHORT_FLAGS_BD_CNT_SFT))
+#define MEM_HWRM_RESP memalign(BNXT_DMA_ALIGNMENT, RESP_BUF_SIZE_ALIGNED)
+#define PORT_PHY_FLAGS (BNXT_FLAG_NPAR_MODE | BNXT_FLAG_MULTI_HOST)
+#define RING_FREE(bp, rid, flag) bnxt_hwrm_ring_free(bp, rid, flag)
+#define QCFG_PHY_ALL (SUPPORT_SPEEDS | DETECT_MEDIA | PHY_SPEED | PHY_STATUS)
+
+#endif /* _BNXT_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019-2021 Broadcom.
+ */
+
+#ifndef _BXNT_DBG_H_
+#define _BXNT_DBG_H_
+
+/* Adjust commented out lines below to enable debug. */
+/* #define DEBUG_PCI */
+/* #define DEBUG_MEMORY */
+/* #define DEBUG_LINK */
+/* #define DEBUG_CHIP */
+/* #define DEBUG_FAIL */
+/* #define DEBUG_HWRM_CMDS */
+/* #define DEBUG_HWRM_DUMP */
+/* #define DEBUG_CQ */
+/* #define DEBUG_CQ_DUMP */
+/* #define DEBUG_TX */
+/* #define DEBUG_TX_DUMP */
+/* #define DEBUG_RX */
+/* #define DEBUG_RX_DUMP */
+
+#if \
+ defined(DEBUG_PCI) || \
+ defined(DEBUG_MEMORY) || \
+ defined(DEBUG_LINK) || \
+ defined(DEBUG_CHIP) || \
+ defined(DEBUG_FAIL) || \
+ defined(DEBUG_HWRM_CMDS) || \
+ defined(DEBUG_HWRM_DUMP) || \
+ defined(DEBUG_CQ) || \
+ defined(DEBUG_CQ_DUMP) || \
+ defined(DEBUG_TX) || \
+ defined(DEBUG_TX_DUMP) || \
+ defined(DEBUG_RX) || \
+ defined(DEBUG_RX_DUMP)
+#define DEBUG_DEFAULT
+#endif
+
+#if defined(DEBUG_DEFAULT)
+#define dbg_prn printf
+#define MAX_CHAR_SIZE(a) (u32)((1 << (a)) - 1)
+#define DISP_U8 0x00
+#define DISP_U16 0x01
+#define DISP_U32 0x02
+#define DISP_U64 0x03
+
+void dumpmemory1(u8 *buffer, u32 length, u8 flag)
+{
+ u32 jj = 0;
+ u8 i, c;
+
+ printf("\n %p:", buffer);
+ for (jj = 0; jj < 16; jj++) {
+ if (!(jj & MAX_CHAR_SIZE(flag)))
+ printf(" ");
+ if (jj < length)
+ printf("%02x", buffer[jj]);
+ else
+ printf(" ");
+ if ((jj & 0xF) == 0xF) {
+ printf(" ");
+ for (i = 0; i < 16; i++) {
+ if (i < length) {
+ c = buffer[jj + i - 15];
+ if (c >= 0x20 && c < 0x7F)
+ ;
+ else
+ c = '.';
+ printf("%c", c);
+ }
+ }
+ }
+ }
+}
+
+void dump_mem(u8 *buffer, u32 length, u8 flag)
+{
+ u32 length16, remlen, jj;
+
+ length16 = length & 0xFFFFFFF0;
+ remlen = length & 0xF;
+ for (jj = 0; jj < length16; jj += 16)
+ dumpmemory1((u8 *)&buffer[jj], 16, flag);
+ if (remlen)
+ dumpmemory1((u8 *)&buffer[length16], remlen, flag);
+ if (length16 || remlen)
+ printf("\n");
+}
+#endif
+
+#if defined(DEBUG_PCI)
+void dbg_pci(struct bnxt *bp, const char *func, u16 cmd_reg)
+{
+ printf("- %s()\n", func);
+ printf(" Vendor id : %04X\n", bp->vendor_id);
+ printf(" Device id : %04X\n", bp->device_id);
+ printf(" Irq : %d\n", bp->irq);
+ printf(" PCI Command Reg : %04X %04X\n", bp->cmd_reg, cmd_reg);
+ printf(" Sub Vendor id : %04X\n", bp->subsystem_vendor);
+ printf(" Sub Device id : %04X\n", bp->subsystem_device);
+ printf(" BAR (0) : %p\n", bp->bar0);
+ printf(" BAR (1) : %p\n", bp->bar1);
+ printf(" BAR (2) : %p\n", bp->bar2);
+}
+#else
+#define dbg_pci(bp, func, creg)
+#endif
+
+#if defined(DEBUG_MEMORY)
+void dbg_mem(struct bnxt *bp, const char *func)
+{
+ printf("- %s()\n", func);
+ printf(" bp Addr : %p", bp);
+ printf(" Len %4d", (u16)sizeof(struct bnxt));
+ printf(" phy %llx\n", virt_to_bus(bp));
+ printf(" bp->hwrm_req_addr : %p", bp->hwrm_addr_req);
+ printf(" Len %4d", (u16)REQ_BUFFER_SIZE);
+ printf(" phy %llx\n", bp->req_addr_mapping);
+ printf(" bp->hwrm_resp_addr : %p", bp->hwrm_addr_resp);
+ printf(" Len %4d", (u16)RESP_BUFFER_SIZE);
+ printf(" phy %llx\n", bp->resp_addr_mapping);
+ printf(" bp->tx.bd_virt : %p", bp->tx.bd_virt);
+ printf(" Len %4d", (u16)TX_RING_DMA_BUFFER_SIZE);
+ printf(" phy %llx\n", virt_to_bus(bp->tx.bd_virt));
+ printf(" bp->rx.bd_virt : %p", bp->rx.bd_virt);
+ printf(" Len %4d", (u16)RX_RING_DMA_BUFFER_SIZE);
+ printf(" phy %llx\n", virt_to_bus(bp->rx.bd_virt));
+ printf(" bp->cq.bd_virt : %p", bp->cq.bd_virt);
+ printf(" Len %4d", (u16)CQ_RING_DMA_BUFFER_SIZE);
+ printf(" phy %llx\n", virt_to_bus(bp->cq.bd_virt));
+}
+#else
+#define dbg_mem(bp, func)
+#endif
+
+#if defined(DEBUG_CHIP)
+void print_fw_ver(struct hwrm_ver_get_output *resp, u32 tmo)
+{
+ if (resp->hwrm_intf_maj_8b < 1) {
+ dbg_prn(" HWRM interface %d.%d.%d is older than 1.0.0.\n",
+ resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
+ resp->hwrm_intf_upd_8b);
+ dbg_prn(" Update FW with HWRM interface 1.0.0 or newer.\n");
+ }
+ dbg_prn(" FW Version : %d.%d.%d.%d\n",
+ resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
+ resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
+ printf(" cmd timeout : %d\n", tmo);
+}
+
+void dbg_func_resource_qcaps(struct bnxt *bp)
+{
+ /* Ring Groups */
+ printf(" min_hw_ring_grps : %d\n", bp->min_hw_ring_grps);
+ printf(" max_hw_ring_grps : %d\n", bp->max_hw_ring_grps);
+ /* TX Rings */
+ printf(" min_tx_rings : %d\n", bp->min_tx_rings);
+ printf(" max_tx_rings : %d\n", bp->max_tx_rings);
+ /* RX Rings */
+ printf(" min_rx_rings : %d\n", bp->min_rx_rings);
+ printf(" max_rx_rings : %d\n", bp->max_rx_rings);
+ /* Completion Rings */
+ printf(" min_cq_rings : %d\n", bp->min_cp_rings);
+ printf(" max_cq_rings : %d\n", bp->max_cp_rings);
+ /* Statistic Contexts */
+ printf(" min_stat_ctxs : %d\n", bp->min_stat_ctxs);
+ printf(" max_stat_ctxs : %d\n", bp->max_stat_ctxs);
+}
+
+void print_func_qcaps(struct bnxt *bp)
+{
+ printf(" Port Number : %d\n", bp->port_idx);
+ printf(" fid : 0x%04x\n", bp->fid);
+ dbg_prn(" PF MAC : %02x:%02x:%02x:%02x:%02x:%02x\n",
+ bp->mac_addr[0],
+ bp->mac_addr[1],
+ bp->mac_addr[2],
+ bp->mac_addr[3],
+ bp->mac_addr[4],
+ bp->mac_addr[5]);
+}
+
+void print_func_qcfg(struct bnxt *bp)
+{
+ printf(" ordinal_value : %d\n", bp->ordinal_value);
+ printf(" stat_ctx_id : %x\n", bp->stat_ctx_id);
+ dbg_prn(" FW MAC : %02x:%02x:%02x:%02x:%02x:%02x\n",
+ bp->mac_addr[0],
+ bp->mac_addr[1],
+ bp->mac_addr[2],
+ bp->mac_addr[3],
+ bp->mac_addr[4],
+ bp->mac_addr[5]);
+}
+
+void dbg_set_speed(u32 speed)
+{
+ u32 speed1 = ((speed & LINK_SPEED_DRV_MASK) >> LINK_SPEED_DRV_SHIFT);
+
+ printf(" Set Link Speed : ");
+ switch (speed & LINK_SPEED_DRV_MASK) {
+ case LINK_SPEED_DRV_1G:
+ printf("1 GBPS");
+ break;
+ case LINK_SPEED_DRV_10G:
+ printf("10 GBPS");
+ break;
+ case LINK_SPEED_DRV_25G:
+ printf("25 GBPS");
+ break;
+ case LINK_SPEED_DRV_40G:
+ printf("40 GBPS");
+ break;
+ case LINK_SPEED_DRV_50G:
+ printf("50 GBPS");
+ break;
+ case LINK_SPEED_DRV_100G:
+ printf("100 GBPS");
+ break;
+ case LINK_SPEED_DRV_AUTONEG:
+ printf("AUTONEG");
+ break;
+ default:
+ printf("%x", speed1);
+ break;
+ }
+ printf("\n");
+}
+
+void dbg_chip_info(struct bnxt *bp)
+{
+ printf(" Stat Ctx ID : %d\n", bp->stat_ctx_id);
+ printf(" Grp ID : %d\n", bp->ring_grp_id);
+ printf(" CQ Ring Id : %d\n", bp->cq_ring_id);
+ printf(" Tx Ring Id : %d\n", bp->tx_ring_id);
+ printf(" Rx ring Id : %d\n", bp->rx_ring_id);
+}
+
+void print_num_rings(struct bnxt *bp)
+{
+ printf(" num_cmpl_rings : %d\n", bp->num_cmpl_rings);
+ printf(" num_tx_rings : %d\n", bp->num_tx_rings);
+ printf(" num_rx_rings : %d\n", bp->num_rx_rings);
+ printf(" num_ring_grps : %d\n", bp->num_hw_ring_grps);
+ printf(" num_stat_ctxs : %d\n", bp->num_stat_ctxs);
+}
+
+void dbg_flags(const char *func, u32 flags)
+{
+ printf("- %s()\n", func);
+ printf(" bp->flags : 0x%04x\n", flags);
+}
+#else
+#define print_fw_ver(resp, tmo)
+#define dbg_func_resource_qcaps(bp)
+#define print_func_qcaps(bp)
+#define print_func_qcfg(bp)
+#define dbg_set_speed(speed)
+#define dbg_chip_info(bp)
+#define print_num_rings(bp)
+#define dbg_flags(func, flags)
+#endif
+
+#if defined(DEBUG_HWRM_CMDS) || defined(DEBUG_FAIL)
+void dump_hwrm_req(struct bnxt *bp, const char *func, u32 len, u32 tmo)
+{
+ dbg_prn("- %s(0x%04x) cmd_len %d cmd_tmo %d",
+ func, (u16)((struct input *)bp->hwrm_addr_req)->req_type,
+ len, tmo);
+#if defined(DEBUG_HWRM_DUMP)
+ dump_mem((u8 *)bp->hwrm_addr_req, len, DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+
+void debug_resp(struct bnxt *bp, const char *func, u32 resp_len, u16 err)
+{
+ dbg_prn("- %s(0x%04x) - ",
+ func, (u16)((struct input *)bp->hwrm_addr_req)->req_type);
+ if (err == STATUS_SUCCESS)
+ printf("Done");
+ else if (err != STATUS_TIMEOUT)
+ printf("Fail err 0x%04x", err);
+ else
+ printf("timedout");
+#if defined(DEBUG_HWRM_DUMP)
+ if (err != STATUS_TIMEOUT)
+ dump_mem((u8 *)bp->hwrm_addr_resp, resp_len, DISP_U8);
+ else
+ printf("\n");
+#else
+ printf("\n");
+#endif
+}
+
+void dbg_hw_cmd(struct bnxt *bp,
+ const char *func, u16 cmd_len,
+ u16 resp_len, u32 cmd_tmo, u16 err)
+{
+#if !defined(DEBUG_HWRM_CMDS)
+ if (err && err != STATUS_TIMEOUT)
+#endif
+ {
+ dump_hwrm_req(bp, func, cmd_len, cmd_tmo);
+ debug_resp(bp, func, resp_len, err);
+ }
+}
+#else
+#define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err)
+#endif
+
+#if defined(DEBUG_HWRM_CMDS)
+void dbg_short_cmd(u8 *req, const char *func, u32 len)
+{
+ struct hwrm_short_input *sreq;
+
+ sreq = (struct hwrm_short_input *)req;
+ dbg_prn("- %s(0x%04x) short_cmd_len %d",
+ func,
+ sreq->req_type,
+ (int)len);
+#if defined(DEBUG_HWRM_DUMP)
+ dump_mem((u8 *)sreq, len, DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+#else
+#define dbg_short_cmd(sreq, func, len)
+#endif
+
+#if defined(DEBUG_RX)
+void dump_rx_bd(struct rx_pkt_cmpl *rx_cmp,
+ struct rx_pkt_cmpl_hi *rx_cmp_hi,
+ u32 desc_idx)
+{
+ printf(" RX desc_idx %d\n", desc_idx);
+ printf("- rx_cmp %llx", virt_to_bus(rx_cmp));
+#if defined(DEBUG_RX_DUMP)
+ dump_mem((u8 *)rx_cmp, (u32)sizeof(struct rx_pkt_cmpl), DISP_U8);
+#else
+ printf("\n");
+#endif
+ printf("- rx_cmp_hi %llx", virt_to_bus(rx_cmp_hi));
+#if defined(DEBUG_RX_DUMP)
+ dump_mem((u8 *)rx_cmp_hi, (u32)sizeof(struct rx_pkt_cmpl_hi), DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+
+void dbg_rxp(u8 *iob, u16 rx_len, u16 flag)
+{
+ printf("- RX iob %llx Len %d ", virt_to_bus(iob), rx_len);
+ if (flag == PKT_RECEIVED)
+ printf(" PKT RECEIVED");
+ else if (flag == PKT_DROPPED)
+ printf(" PKT DROPPED");
+#if defined(DEBUG_RX_DUMP)
+ dump_mem(iob, (u32)rx_len, DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+
+void dbg_rx_cid(u16 idx, u16 cid)
+{
+ dbg_prn("- RX old cid %d new cid %d\n", idx, cid);
+}
+
+void dbg_rx_alloc_iob_fail(u16 idx, u16 cid)
+{
+ dbg_prn(" Rx alloc_iob (%d) failed", idx);
+ dbg_prn(" for cons_id %d\n", cid);
+}
+
+void dbg_rx_iob(void *iob, u16 idx, u16 cid)
+{
+ dbg_prn(" Rx alloc_iob (%d) %p bd_virt (%d)\n",
+ idx, iob, cid);
+}
+
+void dbg_rx_pkt(struct bnxt *bp, const char *func, uchar *pkt, int len)
+{
+ if (bp->rx.iob_recv == PKT_RECEIVED) {
+ dbg_prn("- %s: %llx %d\n", func,
+ virt_to_bus(pkt), len);
+ }
+}
+#else
+#define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx)
+#define dbg_rxp(iob, rx_len, flag)
+#define dbg_rx_cid(idx, cid)
+#define dbg_rx_alloc_iob_fail(idx, cid)
+#define dbg_rx_iob(iob, idx, cid)
+#define dbg_rx_pkt(bp, func, pkt, len)
+#endif
+
+#if defined(DEBUG_CQ)
+void dump_CQ(struct cmpl_base *cmp, u16 cons_idx)
+{
+ printf("- CQ Type ");
+
+ switch (cmp->type & CMPL_BASE_TYPE_MASK) {
+ case CMPL_BASE_TYPE_STAT_EJECT:
+ printf("(se)");
+ break;
+ case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
+ printf("(ae)");
+ break;
+ case CMPL_BASE_TYPE_TX_L2:
+ printf("(tx)");
+ break;
+ case CMPL_BASE_TYPE_RX_L2:
+ printf("(rx)");
+ break;
+ default:
+ printf("%04x", (u16)(cmp->type & CMPL_BASE_TYPE_MASK));
+ break;
+ }
+ printf(" cid %d", cons_idx);
+#if defined(DEBUG_CQ_DUMP)
+ dump_mem((u8 *)cmp, (u32)sizeof(struct cmpl_base), DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+#else
+#define dump_CQ(cq, id)
+#endif
+
+#if defined(DEBUG_TX)
+void dump_tx_stat(struct bnxt *bp)
+{
+ printf(" TX stats cnt %d req_cnt %d", bp->tx.cnt, bp->tx.cnt_req);
+ printf(" prod_id %d cons_id %d\n", bp->tx.prod_id, bp->tx.cons_id);
+}
+
+void dump_tx_pkt(void *packet, dma_addr_t mapping, int len)
+{
+ printf(" TX Addr %llx Size %d", mapping, len);
+#if defined(DEBUG_TX_DUMP)
+ dump_mem((u8 *)packet, len, DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+
+void dump_tx_bd(struct tx_bd_short *tx_bd, u16 len)
+{
+ printf(" Tx BD Addr %llx Size %d", virt_to_bus(tx_bd), len);
+#if defined(DEBUG_TX_DUMP)
+ dump_mem((u8 *)tx_bd, (u32)len, DISP_U8);
+#else
+ printf("\n");
+#endif
+}
+
+void dbg_no_tx_bd(void)
+{
+ printf(" Tx ring full\n");
+}
+#else
+#define dump_tx_stat(bp)
+#define dump_tx_pkt(packet, mapping, len)
+#define dump_tx_bd(prod_bd, len)
+#define dbg_no_tx_bd()
+#endif
+
+#if defined(DEBUG_MEMORY)
+void dbg_mem_free_done(const char *func)
+{
+ printf("- %s - Done\n", func);
+}
+#else
+#define dbg_mem_free_done(func)
+#endif
+
+#if defined(DEBUG_FAIL)
+void dbg_mem_alloc_fail(const char *func)
+{
+ printf("- %s() Fail\n", func);
+}
+#else
+#define dbg_mem_alloc_fail(func)
+#endif
+
+#if defined(DEBUG_LINK)
+static void dump_evt(u8 *cmp, u32 type, u16 cid)
+{
+ u32 size = sizeof(struct cmpl_base);
+ u8 c = 'C';
+
+ switch (type) {
+ case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
+ break;
+ default:
+ return;
+ }
+ dbg_prn("- %cQ Type (ae) cid %d", c, cid);
+ dump_mem(cmp, size, DISP_U8);
+}
+
+void dbg_link_status(struct bnxt *bp)
+{
+ dbg_prn(" Port(%d) : Link", bp->port_idx);
+ if (bp->link_status == STATUS_LINK_ACTIVE) {
+ dbg_prn("Up");
+ } else {
+ dbg_prn("Down\n");
+ dbg_prn(" media_detect : %x", bp->media_detect);
+ }
+ dbg_prn("\n");
+}
+
+void dbg_link_state(struct bnxt *bp, u32 tmo)
+{
+ if (bp->link_status == STATUS_LINK_ACTIVE)
+ printf(" Link wait time : %d ms\n", tmo);
+}
+
+void dbg_phy_speed(struct bnxt *bp, char *name)
+{
+ printf(" Current Speed : %s\n", name);
+}
+#else
+#define dump_evt(cmp, ty, cid)
+#define dbg_link_status(bp)
+#define dbg_link_state(bp, tmo)
+#define dbg_phy_speed(bp, name)
+#endif
+
+#endif /* _BXNT_DBG_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+ * Copyright 2019-2021 Broadcom.
+ */
+
+#ifndef _BNXT_HSI_H_
+#define _BNXT_HSI_H_
+
+/* input (size:128b/16B) */
+struct input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+};
+
+/* output (size:64b/8B) */
+struct output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+};
+
+/* hwrm_short_input (size:128b/16B) */
+struct hwrm_short_input {
+ __le16 req_type;
+ __le16 signature;
+#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
+ __le16 unused_0;
+ __le16 size;
+ __le64 req_addr;
+};
+
+#define HWRM_VER_GET 0x0UL
+#define HWRM_FUNC_RESET 0x11UL
+#define HWRM_FUNC_QCAPS 0x15UL
+#define HWRM_FUNC_QCFG 0x16UL
+#define HWRM_FUNC_CFG 0x17UL
+#define HWRM_FUNC_DRV_UNRGTR 0x1aUL
+#define HWRM_FUNC_DRV_RGTR 0x1dUL
+#define HWRM_PORT_PHY_CFG 0x20UL
+#define HWRM_PORT_MAC_CFG 0x21UL
+#define HWRM_PORT_PHY_QCFG 0x27UL
+#define HWRM_VNIC_ALLOC 0x40UL
+#define HWRM_VNIC_FREE 0x41UL
+#define HWRM_VNIC_CFG 0x42UL
+#define HWRM_RING_ALLOC 0x50UL
+#define HWRM_RING_FREE 0x51UL
+#define HWRM_RING_GRP_ALLOC 0x60UL
+#define HWRM_RING_GRP_FREE 0x61UL
+#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
+#define HWRM_CFA_L2_FILTER_FREE 0x91UL
+#define HWRM_CFA_L2_SET_RX_MASK 0x93UL
+#define HWRM_STAT_CTX_ALLOC 0xb0UL
+#define HWRM_STAT_CTX_FREE 0xb1UL
+#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
+#define HWRM_NVM_FLUSH 0xfff0UL
+#define HWRM_NVM_GET_VARIABLE 0xfff1UL
+#define HWRM_NVM_SET_VARIABLE 0xfff2UL
+
+#define HWRM_NA_SIGNATURE ((__le32)(-1))
+#define HWRM_MAX_REQ_LEN 128
+#define HWRM_VERSION_MAJOR 1
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
+
+/* hwrm_ver_get_input (size:192b/24B) */
+struct hwrm_ver_get_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ u8 hwrm_intf_maj;
+ u8 hwrm_intf_min;
+ u8 hwrm_intf_upd;
+ u8 unused_0[5];
+};
+
+/* hwrm_ver_get_output (size:1408b/176B) */
+struct hwrm_ver_get_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ u8 hwrm_intf_maj_8b;
+ u8 hwrm_intf_min_8b;
+ u8 hwrm_intf_upd_8b;
+ u8 hwrm_intf_rsvd_8b;
+ u8 hwrm_fw_maj_8b;
+ u8 hwrm_fw_min_8b;
+ u8 hwrm_fw_bld_8b;
+ u8 hwrm_fw_rsvd_8b;
+ u8 mgmt_fw_maj_8b;
+ u8 mgmt_fw_min_8b;
+ u8 mgmt_fw_bld_8b;
+ u8 mgmt_fw_rsvd_8b;
+ u8 netctrl_fw_maj_8b;
+ u8 netctrl_fw_min_8b;
+ u8 netctrl_fw_bld_8b;
+ u8 netctrl_fw_rsvd_8b;
+ __le32 dev_caps_cfg;
+#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
+#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
+ u8 roce_fw_maj_8b;
+ u8 roce_fw_min_8b;
+ u8 roce_fw_bld_8b;
+ u8 roce_fw_rsvd_8b;
+ char hwrm_fw_name[16];
+ char mgmt_fw_name[16];
+ char netctrl_fw_name[16];
+ u8 reserved2[16];
+ char roce_fw_name[16];
+ __le16 chip_num;
+ u8 chip_rev;
+ u8 chip_metal;
+ u8 chip_bond_id;
+ u8 chip_platform_type;
+ __le16 max_req_win_len;
+ __le16 max_resp_len;
+ __le16 def_req_timeout;
+ u8 flags;
+ u8 unused_0[2];
+ u8 always_1;
+ __le16 hwrm_intf_major;
+ __le16 hwrm_intf_minor;
+ __le16 hwrm_intf_build;
+ __le16 hwrm_intf_patch;
+ __le16 hwrm_fw_major;
+ __le16 hwrm_fw_minor;
+ __le16 hwrm_fw_build;
+ __le16 hwrm_fw_patch;
+ __le16 mgmt_fw_major;
+ __le16 mgmt_fw_minor;
+ __le16 mgmt_fw_build;
+ __le16 mgmt_fw_patch;
+ __le16 netctrl_fw_major;
+ __le16 netctrl_fw_minor;
+ __le16 netctrl_fw_build;
+ __le16 netctrl_fw_patch;
+ __le16 roce_fw_major;
+ __le16 roce_fw_minor;
+ __le16 roce_fw_build;
+ __le16 roce_fw_patch;
+ __le16 max_ext_req_len;
+ u8 unused_1[5];
+ u8 valid;
+};
+
+/* hwrm_async_event_cmpl (size:128b/16B) */
+struct hwrm_async_event_cmpl {
+ __le16 type;
+ __le16 event_id;
+#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
+ __le32 event_data2;
+ u8 opaque_v;
+ u8 timestamp_lo;
+ __le16 timestamp_hi;
+ __le32 event_data1;
+};
+
+/* hwrm_func_reset_input (size:192b/24B) */
+struct hwrm_func_reset_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 enables;
+ __le16 vf_id;
+ u8 func_reset_level;
+#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
+ u8 unused_0;
+};
+
+/* hwrm_func_qcaps_input (size:192b/24B) */
+struct hwrm_func_qcaps_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 fid;
+ u8 unused_0[6];
+};
+
+/* hwrm_func_qcaps_output (size:640b/80B) */
+struct hwrm_func_qcaps_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le16 fid;
+ __le16 port_id;
+ __le32 flags;
+ u8 mac_address[6];
+ __le16 max_rsscos_ctx;
+ __le16 max_cmpl_rings;
+ __le16 max_tx_rings;
+ __le16 max_rx_rings;
+ __le16 max_l2_ctxs;
+ __le16 max_vnics;
+ __le16 first_vf_id;
+ __le16 max_vfs;
+ __le16 max_stat_ctx;
+ __le32 max_encap_records;
+ __le32 max_decap_records;
+ __le32 max_tx_em_flows;
+ __le32 max_tx_wm_flows;
+ __le32 max_rx_em_flows;
+ __le32 max_rx_wm_flows;
+ __le32 max_mcast_filters;
+ __le32 max_flow_id;
+ __le32 max_hw_ring_grps;
+ __le16 max_sp_tx_rings;
+ u8 unused_0;
+ u8 valid;
+};
+
+/* hwrm_func_qcfg_input (size:192b/24B) */
+struct hwrm_func_qcfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 fid;
+ u8 unused_0[6];
+};
+
+/* hwrm_func_qcfg_output (size:704b/88B) */
+struct hwrm_func_qcfg_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le16 fid;
+ __le16 port_id;
+ __le16 vlan;
+ __le16 flags;
+#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
+ u8 mac_address[6];
+ __le16 pci_id;
+ __le16 alloc_rsscos_ctx;
+ __le16 alloc_cmpl_rings;
+ __le16 alloc_tx_rings;
+ __le16 alloc_rx_rings;
+ __le16 alloc_l2_ctx;
+ __le16 alloc_vnics;
+ __le16 mtu;
+ __le16 mru;
+ __le16 stat_ctx_id;
+ u8 port_partition_type;
+#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
+ u8 port_pf_cnt;
+ __le16 dflt_vnic_id;
+ __le16 max_mtu_configured;
+ __le32 min_bw;
+ __le32 max_bw;
+ u8 evb_mode;
+ u8 options;
+ __le16 alloc_vfs;
+ __le32 alloc_mcast_filters;
+ __le32 alloc_hw_ring_grps;
+ __le16 alloc_sp_tx_rings;
+ __le16 alloc_stat_ctx;
+ __le16 alloc_msix;
+ __le16 registered_vfs;
+ u8 unused_1[3];
+ u8 always_1;
+ __le32 reset_addr_poll;
+ u8 unused_2[3];
+ u8 valid;
+};
+
+/* hwrm_func_cfg_input (size:704b/88B) */
+struct hwrm_func_cfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 fid;
+ __le16 num_msix;
+ __le32 flags;
+ __le32 enables;
+#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
+#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
+#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
+#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
+#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
+#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
+ __le16 mtu;
+ __le16 mru;
+ __le16 num_rsscos_ctxs;
+ __le16 num_cmpl_rings;
+ __le16 num_tx_rings;
+ __le16 num_rx_rings;
+ __le16 num_l2_ctxs;
+ __le16 num_vnics;
+ __le16 num_stat_ctxs;
+ __le16 num_hw_ring_grps;
+ u8 dflt_mac_addr[6];
+ __le16 dflt_vlan;
+ __be32 dflt_ip_addr[4];
+ __le32 min_bw;
+ __le32 max_bw;
+ __le16 async_event_cr;
+ u8 vlan_antispoof_mode;
+ u8 allowed_vlan_pris;
+ u8 evb_mode;
+ u8 options;
+ __le16 num_mcast_filters;
+};
+
+/* hwrm_func_drv_rgtr_input (size:896b/112B) */
+struct hwrm_func_drv_rgtr_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+ __le32 enables;
+#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
+#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
+#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
+ __le16 os_type;
+#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
+ u8 ver_maj_8b;
+ u8 ver_min_8b;
+ u8 ver_upd_8b;
+ u8 unused_0[3];
+ __le32 timestamp;
+ u8 unused_1[4];
+ __le32 vf_req_fwd[8];
+ __le32 async_event_fwd[8];
+ __le16 ver_maj;
+ __le16 ver_min;
+ __le16 ver_upd;
+ __le16 ver_patch;
+};
+
+/* hwrm_func_drv_unrgtr_input (size:192b/24B) */
+struct hwrm_func_drv_unrgtr_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
+ u8 unused_0[4];
+};
+
+/* hwrm_func_resource_qcaps_input (size:192b/24B) */
+struct hwrm_func_resource_qcaps_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 fid;
+ u8 unused_0[6];
+};
+
+/* hwrm_func_resource_qcaps_output (size:448b/56B) */
+struct hwrm_func_resource_qcaps_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le16 max_vfs;
+ __le16 max_msix;
+ __le16 vf_reservation_strategy;
+ __le16 min_rsscos_ctx;
+ __le16 max_rsscos_ctx;
+ __le16 min_cmpl_rings;
+ __le16 max_cmpl_rings;
+ __le16 min_tx_rings;
+ __le16 max_tx_rings;
+ __le16 min_rx_rings;
+ __le16 max_rx_rings;
+ __le16 min_l2_ctxs;
+ __le16 max_l2_ctxs;
+ __le16 min_vnics;
+ __le16 max_vnics;
+ __le16 min_stat_ctx;
+ __le16 max_stat_ctx;
+ __le16 min_hw_ring_grps;
+ __le16 max_hw_ring_grps;
+ __le16 max_tx_scheduler_inputs;
+ __le16 flags;
+ u8 unused_0[5];
+ u8 valid;
+};
+
+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
+struct hwrm_func_vlan_qcfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 fid;
+ u8 unused_0[6];
+};
+
+/* hwrm_port_phy_cfg_input (size:448b/56B) */
+struct hwrm_port_phy_cfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
+#define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
+ __le32 enables;
+#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
+#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
+#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
+#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
+ __le16 port_id;
+ __le16 force_link_speed;
+#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
+#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
+#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
+#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
+#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
+#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
+ u8 auto_mode;
+#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
+ u8 auto_duplex;
+#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
+ u8 auto_pause;
+#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
+#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
+ u8 unused_0;
+ __le16 auto_link_speed;
+ __le16 auto_link_speed_mask;
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
+#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
+ u8 wirespeed;
+ u8 lpbk;
+ u8 force_pause;
+ u8 unused_1;
+ __le32 preemphasis;
+ __le16 eee_link_speed_mask;
+ u8 unused_2[2];
+ __le32 tx_lpi_timer;
+ __le32 unused_3;
+};
+
+/* hwrm_port_phy_qcfg_input (size:192b/24B) */
+struct hwrm_port_phy_qcfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 port_id;
+ u8 unused_0[6];
+};
+
+/* hwrm_port_phy_qcfg_output (size:768b/96B) */
+struct hwrm_port_phy_qcfg_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ u8 link;
+#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
+ u8 unused_0;
+ __le16 link_speed;
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
+#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
+ u8 duplex_cfg;
+ u8 pause;
+ __le16 support_speeds;
+#define PORT_QCFG_SUPPORT_SPEEDS_100MBHD 0x1UL
+#define PORT_QCFG_SUPPORT_SPEEDS_100MB 0x2UL
+#define PORT_QCFG_SUPPORT_SPEEDS_1GBHD 0x4UL
+#define PORT_QCFG_SUPPORT_SPEEDS_1GB 0x8UL
+#define PORT_QCFG_SUPPORT_SPEEDS_2GB 0x10UL
+#define PORT_QCFG_SUPPORT_SPEEDS_2_5GB 0x20UL
+#define PORT_QCFG_SUPPORT_SPEEDS_10GB 0x40UL
+#define PORT_QCFG_SUPPORT_SPEEDS_20GB 0x80UL
+#define PORT_QCFG_SUPPORT_SPEEDS_25GB 0x100UL
+#define PORT_QCFG_SUPPORT_SPEEDS_50GB 0x400UL
+#define PORT_QCFG_SUPPORT_SPEEDS_100GB 0x800UL
+#define PORT_QCFG_SUPPORT_SPEEDS_200GB 0x4000UL
+ __le16 force_link_speed;
+ u8 auto_mode;
+ u8 auto_pause;
+ __le16 auto_link_speed;
+ __le16 auto_link_speed_mask;
+ u8 wirespeed;
+ u8 lpbk;
+ u8 force_pause;
+ u8 module_status;
+ __le32 preemphasis;
+ u8 phy_maj;
+ u8 phy_min;
+ u8 phy_bld;
+ u8 phy_type;
+ u8 media_type;
+ u8 xcvr_pkg_type;
+ u8 eee_config_phy_addr;
+ u8 parallel_detect;
+ __le16 link_partner_adv_speeds;
+ u8 link_partner_adv_auto_mode;
+ u8 link_partner_adv_pause;
+ __le16 adv_eee_link_speed_mask;
+ __le16 link_partner_adv_eee_link_speed_mask;
+ __le32 xcvr_identifier_type_tx_lpi_timer;
+ __le16 fec_cfg;
+ u8 duplex_state;
+ u8 option_flags;
+ char phy_vendor_name[16];
+ char phy_vendor_partnumber[16];
+ u8 unused_2[7];
+ u8 valid;
+};
+
+/* hwrm_port_mac_cfg_input (size:320b/40B) */
+struct hwrm_port_mac_cfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+ __le32 enables;
+ __le16 port_id;
+ u8 ipg;
+ u8 lpbk;
+#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
+ u8 vlan_pri2cos_map_pri;
+ u8 reserved1;
+ u8 tunnel_pri2cos_map_pri;
+ u8 dscp2pri_map_pri;
+ __le16 rx_ts_capture_ptp_msg_type;
+ __le16 tx_ts_capture_ptp_msg_type;
+ u8 cos_field_cfg;
+ u8 unused_0[3];
+};
+
+/* hwrm_vnic_alloc_input (size:192b/24B) */
+struct hwrm_vnic_alloc_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
+ u8 unused_0[4];
+};
+
+/* hwrm_vnic_alloc_output (size:128b/16B) */
+struct hwrm_vnic_alloc_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le32 vnic_id;
+ u8 unused_0[3];
+ u8 valid;
+};
+
+/* hwrm_vnic_free_input (size:192b/24B) */
+struct hwrm_vnic_free_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 vnic_id;
+ u8 unused_0[4];
+};
+
+/* hwrm_vnic_cfg_input (size:320b/40B) */
+struct hwrm_vnic_cfg_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+ __le32 enables;
+#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
+#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
+ __le16 vnic_id;
+ __le16 dflt_ring_grp;
+ __le16 rss_rule;
+ __le16 cos_rule;
+ __le16 lb_rule;
+ __le16 mru;
+ __le16 default_rx_ring_id;
+ __le16 default_cmpl_ring_id;
+};
+
+/* hwrm_ring_alloc_input (size:704b/88B) */
+struct hwrm_ring_alloc_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 enables;
+#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
+ u8 ring_type;
+#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
+#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
+#define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
+ u8 unused_0;
+ __le16 flags;
+ __le64 page_tbl_addr;
+ __le32 fbo;
+ u8 page_size;
+ u8 page_tbl_depth;
+ u8 unused_1[2];
+ __le32 length;
+ __le16 logical_id;
+ __le16 cmpl_ring_id;
+ __le16 queue_id;
+ __le16 rx_buf_size;
+ __le16 rx_ring_id;
+ __le16 nq_ring_id;
+ __le16 ring_arb_cfg;
+ __le16 unused_3;
+ __le32 reserved3;
+ __le32 stat_ctx_id;
+ __le32 reserved4;
+ __le32 max_bw;
+ u8 int_mode;
+#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
+ u8 unused_4[3];
+ __le64 cq_handle;
+};
+
+/* hwrm_ring_alloc_output (size:128b/16B) */
+struct hwrm_ring_alloc_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le16 ring_id;
+ __le16 logical_ring_id;
+ u8 unused_0[3];
+ u8 valid;
+};
+
+/* hwrm_ring_free_input (size:192b/24B) */
+struct hwrm_ring_free_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ u8 ring_type;
+#define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
+#define RING_FREE_REQ_RING_TYPE_TX 0x1UL
+#define RING_FREE_REQ_RING_TYPE_RX 0x2UL
+ u8 unused_0;
+ __le16 ring_id;
+ u8 unused_1[4];
+};
+
+/* hwrm_ring_grp_alloc_input (size:192b/24B) */
+struct hwrm_ring_grp_alloc_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le16 cr;
+ __le16 rr;
+ __le16 ar;
+ __le16 sc;
+};
+
+/* hwrm_ring_grp_alloc_output (size:128b/16B) */
+struct hwrm_ring_grp_alloc_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le32 ring_group_id;
+ u8 unused_0[3];
+ u8 valid;
+};
+
+/* hwrm_ring_grp_free_input (size:192b/24B) */
+struct hwrm_ring_grp_free_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 ring_group_id;
+ u8 unused_0[4];
+};
+
+/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
+struct hwrm_cfa_l2_filter_alloc_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 flags;
+#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
+ __le32 enables;
+#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
+#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
+#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
+ u8 l2_addr[6];
+ u8 unused_0[2];
+ u8 l2_addr_mask[6];
+ __le16 l2_ovlan;
+ __le16 l2_ovlan_mask;
+ __le16 l2_ivlan;
+ __le16 l2_ivlan_mask;
+ u8 unused_1[2];
+ u8 t_l2_addr[6];
+ u8 unused_2[2];
+ u8 t_l2_addr_mask[6];
+ __le16 t_l2_ovlan;
+ __le16 t_l2_ovlan_mask;
+ __le16 t_l2_ivlan;
+ __le16 t_l2_ivlan_mask;
+ u8 src_type;
+#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
+ u8 unused_3;
+ __le32 src_id;
+ u8 tunnel_type;
+ u8 unused_4;
+ __le16 dst_id;
+ __le16 mirror_vnic_id;
+ u8 pri_hint;
+ u8 unused_5;
+ __le32 unused_6;
+ __le64 l2_filter_id_hint;
+};
+
+/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
+struct hwrm_cfa_l2_filter_alloc_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le64 l2_filter_id;
+ __le32 flow_id;
+ u8 unused_0[3];
+ u8 valid;
+};
+
+/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_l2_filter_free_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le64 l2_filter_id;
+};
+
+/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
+struct hwrm_cfa_l2_set_rx_mask_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 vnic_id;
+ __le32 mask;
+#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
+#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
+#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
+#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
+ __le64 mc_tbl_addr;
+ __le32 num_mc_entries;
+ u8 unused_0[4];
+ __le64 vlan_tag_tbl_addr;
+ __le32 num_vlan_tags;
+ u8 unused_1[4];
+};
+
+/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
+struct hwrm_stat_ctx_alloc_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le64 stats_dma_addr;
+ __le32 update_period_ms;
+ u8 stat_ctx_flags;
+ u8 unused_0[3];
+};
+
+/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
+struct hwrm_stat_ctx_alloc_output {
+ __le16 error_code;
+ __le16 req_type;
+ __le16 seq_id;
+ __le16 resp_len;
+ __le32 stat_ctx_id;
+ u8 unused_0[3];
+ u8 valid;
+};
+
+/* hwrm_stat_ctx_free_input (size:192b/24B) */
+struct hwrm_stat_ctx_free_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le32 stat_ctx_id;
+ u8 unused_0[4];
+};
+
+/* hwrm_nvm_flush_input (size:128b/16B) */
+struct hwrm_nvm_flush_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+};
+
+/* hwrm_nvm_get_variable_input (size:320b/40B) */
+struct hwrm_nvm_get_variable_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le64 dest_data_addr;
+ __le16 data_len;
+ __le16 option_num;
+ __le16 dimensions;
+ __le16 index_0;
+ __le16 index_1;
+ __le16 index_2;
+ __le16 index_3;
+ u8 flags;
+ u8 unused_0;
+};
+
+/* hwrm_nvm_set_variable_input (size:320b/40B) */
+struct hwrm_nvm_set_variable_input {
+ __le16 req_type;
+ __le16 cmpl_ring;
+ __le16 seq_id;
+ __le16 target_id;
+ __le64 resp_addr;
+ __le64 src_data_addr;
+ __le16 data_len;
+ __le16 option_num;
+ __le16 dimensions;
+ __le16 index_0;
+ __le16 index_1;
+ __le16 index_2;
+ __le16 index_3;
+ u8 flags;
+ u8 unused_0;
+};
+
+#endif /* _BNXT_HSI_H_ */
struct clk clk_ref;
struct clk clk_ptp;
u32 clk_rate;
- char promisc;
+ bool promisc;
};
/**
*/
#include <dm/device_compat.h>
+#include <dm/of_extra.h>
#include <linux/delay.h>
#include <net/dsa.h>
#include <asm/io.h>
#define FELIX_IS2 0x060000
#define FELIX_GMII(port) (0x100000 + (port) * 0x10000)
#define FELIX_QSYS 0x200000
-
+#define FELIX_DEVCPU_GCB 0x070000
+#define FELIX_DEVCPU_GCB_SOFT_RST (FELIX_DEVCPU_GCB + 0x00000004)
+#define SOFT_SWC_RST BIT(0)
#define FELIX_SYS_SYSTEM (FELIX_SYS + 0x00000E00)
#define FELIX_SYS_SYSTEM_EN BIT(0)
#define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x00000F24)
static void felix_start_pcs(struct udevice *dev, int port,
struct phy_device *phy, struct mii_dev *imdio)
{
- bool autoneg = true;
-
- if (phy->phy_id == PHY_FIXED_ID ||
- phy->interface == PHY_INTERFACE_MODE_2500BASEX)
- autoneg = false;
+ ofnode node = dsa_port_get_ofnode(dev, port);
+ bool inband_an = ofnode_eth_uses_inband_aneg(node);
switch (phy->interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
- felix_init_sgmii(imdio, port, autoneg);
+ felix_init_sgmii(imdio, port, inband_an);
break;
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
void *base = priv->regs_base;
int timeout = 100;
+ /* Switch core reset */
+ out_le32(base + FELIX_DEVCPU_GCB_SOFT_RST, SOFT_SWC_RST);
+ while (in_le32(base + FELIX_DEVCPU_GCB_SOFT_RST) & SOFT_SWC_RST &&
+ --timeout)
+ udelay(10);
+ if (in_le32(base + FELIX_DEVCPU_GCB_SOFT_RST) & SOFT_SWC_RST)
+ dev_err(dev, "Timeout waiting for switch core reset\n");
+ timeout = 100;
+
/* Init core memories */
out_le32(base + FELIX_SYS_RAM_CTRL, FELIX_SYS_RAM_CTRL_INIT);
while (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT &&
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
-config RTL8211E_PINE64_GIGABIT_FIX
- bool "Fix gigabit throughput on some Pine64+ models"
- depends on PHY_REALTEK
- help
- Configure the Realtek RTL8211E found on some Pine64+ models differently to
- fix throughput on Gigabit links, turning off all internal delays in the
- process. The settings that this touches are not documented in the CONFREG
- section of the RTL8211E datasheet, but come from Realtek by way of the
- Pine64 engineering team.
-
config RTL8211X_PHY_FORCE_MASTER
bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
depends on PHY_REALTEK
/* Microsemi PHY ID's */
#define PHY_ID_VSC8530 0x00070560
#define PHY_ID_VSC8531 0x00070570
+#define PHY_ID_VSC8502 0x00070630
#define PHY_ID_VSC8540 0x00070760
#define PHY_ID_VSC8541 0x00070770
#define PHY_ID_VSC8574 0x000704a0
return vsc8584_config_init(phydev);
}
+static int vsc8502_config(struct phy_device *phydev)
+{
+ bool rgmii_rx_delay = false, rgmii_tx_delay = false;
+ u16 reg = 0;
+ int ret;
+
+ /* Assume nothing needs to be done for the default GMII/MII mode */
+ if (!phy_interface_is_rgmii(phydev))
+ return 0;
+
+ /* Set Extended PHY Control 1 register to RGMII */
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_1_REG,
+ BIT(13) | BIT(12));
+
+ /* Soft reset required after changing PHY mode from the default
+ * of GMII/MII
+ */
+ ret = mscc_phy_soft_reset(phydev);
+ if (ret)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ rgmii_rx_delay = true;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ rgmii_tx_delay = true;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT2);
+
+ if (rgmii_rx_delay)
+ reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_RX_CLK_DELAY_POS;
+ if (rgmii_tx_delay)
+ reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_TX_CLK_DELAY_POS;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
static struct phy_driver VSC8530_driver = {
.name = "Microsemi VSC8530",
.uid = PHY_ID_VSC8530,
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8502_driver = {
+ .name = "Microsemi VSC8502",
+ .uid = PHY_ID_VSC8502,
+ .mask = 0x000ffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8502_config,
+ .startup = &mscc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver VSC8540_driver = {
.name = "Microsemi VSC8540",
.uid = PHY_ID_VSC8540,
{
phy_register(&VSC8530_driver);
phy_register(&VSC8531_driver);
+ phy_register(&VSC8502_driver);
phy_register(&VSC8540_driver);
phy_register(&VSC8541_driver);
phy_register(&VSC8574_driver);
#include <linux/delay.h>
#define PHY_RTL8211x_FORCE_MASTER BIT(1)
-#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
#define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4)
#define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
-#define MIIM_RTL8211E_CONFREG 0x1c
-#define MIIM_RTL8211E_CONFREG_TXD 0x0002
-#define MIIM_RTL8211E_CONFREG_RXD 0x0004
-#define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
+#define MIIM_RTL8211E_CONFREG 0x1c
+#define MIIM_RTL8211E_CTRL_DELAY BIT(13)
+#define MIIM_RTL8211E_TX_DELAY BIT(12)
+#define MIIM_RTL8211E_RX_DELAY BIT(11)
#define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
static int rtl8211e_probe(struct phy_device *phydev)
{
-#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
- phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
-#endif
-
return 0;
}
reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
}
- if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
- unsigned int reg;
-
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
- 7);
- phy_write(phydev, MDIO_DEVAD_NONE,
- MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
- reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
- /* Ensure both internal delays are turned off */
- reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
- /* Flip the magic undocumented bits */
- reg |= MIIM_RTL8211E_CONFREG_MAGIC;
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
- 0);
- }
/* read interrupt status just to clear it */
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
return 0;
}
+static int rtl8211e_config(struct phy_device *phydev)
+{
+ int reg, val;
+
+ /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ val = MIIM_RTL8211E_CTRL_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY |
+ MIIM_RTL8211E_RX_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_RX_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY;
+ break;
+ default: /* the rest of the modes imply leaving delays as is. */
+ goto default_delay;
+ }
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 7);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
+ reg &= ~(MIIM_RTL8211E_TX_DELAY | MIIM_RTL8211E_RX_DELAY);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg | val);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0);
+
+default_delay:
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static int rtl8211f_config(struct phy_device *phydev)
{
u16 reg;
.mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
.probe = &rtl8211e_probe,
- .config = &rtl8211x_config,
+ .config = &rtl8211e_config,
.startup = &rtl8211e_startup,
.shutdown = &genphy_shutdown,
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2016-2018 NXP
+ * Copyright 2018, Sensor-Technik Wiedemann GmbH
+ * Copyright 2018-2019, Vladimir Oltean <olteanv@gmail.com>
+ * Copyright 2020-2021 NXP
+ *
+ * Ported from Linux (drivers/net/dsa/sja1105/).
+ */
+
+#include <common.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/bitrev.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/if_ether.h>
+#include <linux/if_vlan.h>
+#include <linux/types.h>
+#include <net/dsa.h>
+#include <stdlib.h>
+#include <spi.h>
+#include <miiphy.h>
+#include <dm/of_extra.h>
+
+enum packing_op {
+ PACK,
+ UNPACK,
+};
+
+#define ETHER_CRC32_POLY 0x04C11DB7
+#define ETH_P_SJA1105 0xdadb
+#define SJA1105_NUM_PORTS 5
+#define SJA1110_NUM_PORTS 11
+#define SJA1105_MAX_NUM_PORTS SJA1110_NUM_PORTS
+#define SJA1105_NUM_TC 8
+#define SJA1105ET_FDB_BIN_SIZE 4
+#define SJA1105_SIZE_CGU_CMD 4
+#define SJA1105_SIZE_RESET_CMD 4
+#define SJA1105_SIZE_MDIO_CMD 4
+#define SJA1105_SIZE_SPI_MSG_HEADER 4
+#define SJA1105_SIZE_SPI_MSG_MAXLEN (64 * 4)
+#define SJA1105_SIZE_DEVICE_ID 4
+#define SJA1105_SIZE_TABLE_HEADER 12
+#define SJA1105_SIZE_L2_POLICING_ENTRY 8
+#define SJA1105_SIZE_VLAN_LOOKUP_ENTRY 8
+#define SJA1110_SIZE_VLAN_LOOKUP_ENTRY 12
+#define SJA1105_SIZE_L2_FORWARDING_ENTRY 8
+#define SJA1105_SIZE_L2_FORWARDING_PARAMS_ENTRY 12
+#define SJA1105_SIZE_XMII_PARAMS_ENTRY 4
+#define SJA1110_SIZE_XMII_PARAMS_ENTRY 8
+#define SJA1105ET_SIZE_MAC_CONFIG_ENTRY 28
+#define SJA1105ET_SIZE_GENERAL_PARAMS_ENTRY 40
+#define SJA1105PQRS_SIZE_MAC_CONFIG_ENTRY 32
+#define SJA1105PQRS_SIZE_GENERAL_PARAMS_ENTRY 44
+#define SJA1110_SIZE_GENERAL_PARAMS_ENTRY 56
+
+#define SJA1105_MAX_L2_LOOKUP_COUNT 1024
+#define SJA1105_MAX_L2_POLICING_COUNT 45
+#define SJA1110_MAX_L2_POLICING_COUNT 110
+#define SJA1105_MAX_VLAN_LOOKUP_COUNT 4096
+#define SJA1105_MAX_L2_FORWARDING_COUNT 13
+#define SJA1110_MAX_L2_FORWARDING_COUNT 19
+#define SJA1105_MAX_MAC_CONFIG_COUNT 5
+#define SJA1110_MAX_MAC_CONFIG_COUNT 11
+#define SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT 1
+#define SJA1105_MAX_GENERAL_PARAMS_COUNT 1
+#define SJA1105_MAX_XMII_PARAMS_COUNT 1
+
+#define SJA1105_MAX_FRAME_MEMORY 929
+
+#define SJA1105E_DEVICE_ID 0x9C00000Cull
+#define SJA1105T_DEVICE_ID 0x9E00030Eull
+#define SJA1105PR_DEVICE_ID 0xAF00030Eull
+#define SJA1105QS_DEVICE_ID 0xAE00030Eull
+#define SJA1110_DEVICE_ID 0xB700030Full
+
+#define SJA1105ET_PART_NO 0x9A83
+#define SJA1105P_PART_NO 0x9A84
+#define SJA1105Q_PART_NO 0x9A85
+#define SJA1105R_PART_NO 0x9A86
+#define SJA1105S_PART_NO 0x9A87
+#define SJA1110A_PART_NO 0x1110
+#define SJA1110B_PART_NO 0x1111
+#define SJA1110C_PART_NO 0x1112
+#define SJA1110D_PART_NO 0x1113
+
+#define SJA1110_ACU 0x1c4400
+#define SJA1110_RGU 0x1c6000
+#define SJA1110_CGU 0x1c6400
+
+#define SJA1110_SPI_ADDR(x) ((x) / 4)
+#define SJA1110_ACU_ADDR(x) (SJA1110_ACU + SJA1110_SPI_ADDR(x))
+#define SJA1110_CGU_ADDR(x) (SJA1110_CGU + SJA1110_SPI_ADDR(x))
+#define SJA1110_RGU_ADDR(x) (SJA1110_RGU + SJA1110_SPI_ADDR(x))
+
+#define SJA1105_RSV_ADDR 0xffffffffffffffffull
+
+#define SJA1110_PCS_BANK_REG SJA1110_SPI_ADDR(0x3fc)
+
+#define DSA_8021Q_DIR_TX BIT(11)
+#define DSA_8021Q_PORT_SHIFT 0
+#define DSA_8021Q_PORT_MASK GENMASK(3, 0)
+#define DSA_8021Q_PORT(x) (((x) << DSA_8021Q_PORT_SHIFT) & \
+ DSA_8021Q_PORT_MASK)
+
+#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
+
+/* XPCS registers */
+
+/* VR MII MMD registers offsets */
+#define DW_VR_MII_DIG_CTRL1 0x8000
+#define DW_VR_MII_AN_CTRL 0x8001
+#define DW_VR_MII_DIG_CTRL2 0x80e1
+
+/* VR_MII_DIG_CTRL1 */
+#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
+
+/* VR_MII_DIG_CTRL2 */
+#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
+
+/* VR_MII_AN_CTRL */
+#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3
+#define DW_VR_MII_TX_CONFIG_MASK BIT(3)
+#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0
+#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1
+#define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1)
+#define DW_VR_MII_PCS_MODE_C37_SGMII 0x2
+
+/* PMA registers */
+
+/* LANE_DRIVER1_0 register */
+#define SJA1110_LANE_DRIVER1_0 0x8038
+#define SJA1110_TXDRV(x) (((x) << 12) & GENMASK(14, 12))
+
+/* LANE_DRIVER2_0 register */
+#define SJA1110_LANE_DRIVER2_0 0x803a
+#define SJA1110_TXDRVTRIM_LSB(x) ((x) & GENMASK_ULL(15, 0))
+
+/* LANE_DRIVER2_1 register */
+#define SJA1110_LANE_DRIVER2_1 0x803b
+#define SJA1110_LANE_DRIVER2_1_RSV BIT(9)
+#define SJA1110_TXDRVTRIM_MSB(x) (((x) & GENMASK_ULL(23, 16)) >> 16)
+
+/* LANE_TRIM register */
+#define SJA1110_LANE_TRIM 0x8040
+#define SJA1110_TXTEN BIT(11)
+#define SJA1110_TXRTRIM(x) (((x) << 8) & GENMASK(10, 8))
+#define SJA1110_TXPLL_BWSEL BIT(7)
+#define SJA1110_RXTEN BIT(6)
+#define SJA1110_RXRTRIM(x) (((x) << 3) & GENMASK(5, 3))
+#define SJA1110_CDR_GAIN BIT(2)
+#define SJA1110_ACCOUPLE_RXVCM_EN BIT(0)
+
+/* LANE_DATAPATH_1 register */
+#define SJA1110_LANE_DATAPATH_1 0x8037
+
+/* POWERDOWN_ENABLE register */
+#define SJA1110_POWERDOWN_ENABLE 0x8041
+#define SJA1110_TXPLL_PD BIT(12)
+#define SJA1110_TXPD BIT(11)
+#define SJA1110_RXPKDETEN BIT(10)
+#define SJA1110_RXCH_PD BIT(9)
+#define SJA1110_RXBIAS_PD BIT(8)
+#define SJA1110_RESET_SER_EN BIT(7)
+#define SJA1110_RESET_SER BIT(6)
+#define SJA1110_RESET_DES BIT(5)
+#define SJA1110_RCVEN BIT(4)
+
+/* RXPLL_CTRL0 register */
+#define SJA1110_RXPLL_CTRL0 0x8065
+#define SJA1110_RXPLL_FBDIV(x) (((x) << 2) & GENMASK(9, 2))
+
+/* RXPLL_CTRL1 register */
+#define SJA1110_RXPLL_CTRL1 0x8066
+#define SJA1110_RXPLL_REFDIV(x) ((x) & GENMASK(4, 0))
+
+/* TXPLL_CTRL0 register */
+#define SJA1110_TXPLL_CTRL0 0x806d
+#define SJA1110_TXPLL_FBDIV(x) ((x) & GENMASK(11, 0))
+
+/* TXPLL_CTRL1 register */
+#define SJA1110_TXPLL_CTRL1 0x806e
+#define SJA1110_TXPLL_REFDIV(x) ((x) & GENMASK(5, 0))
+
+/* RX_DATA_DETECT register */
+#define SJA1110_RX_DATA_DETECT 0x8045
+
+/* RX_CDR_CTLE register */
+#define SJA1110_RX_CDR_CTLE 0x8042
+
+/* UM10944.pdf Page 11, Table 2. Configuration Blocks */
+enum {
+ BLKID_L2_POLICING = 0x06,
+ BLKID_VLAN_LOOKUP = 0x07,
+ BLKID_L2_FORWARDING = 0x08,
+ BLKID_MAC_CONFIG = 0x09,
+ BLKID_L2_FORWARDING_PARAMS = 0x0E,
+ BLKID_GENERAL_PARAMS = 0x11,
+ BLKID_XMII_PARAMS = 0x4E,
+};
+
+enum sja1105_blk_idx {
+ BLK_IDX_L2_POLICING = 0,
+ BLK_IDX_VLAN_LOOKUP,
+ BLK_IDX_L2_FORWARDING,
+ BLK_IDX_MAC_CONFIG,
+ BLK_IDX_L2_FORWARDING_PARAMS,
+ BLK_IDX_GENERAL_PARAMS,
+ BLK_IDX_XMII_PARAMS,
+ BLK_IDX_MAX,
+};
+
+struct sja1105_general_params_entry {
+ u64 mac_fltres1;
+ u64 mac_fltres0;
+ u64 mac_flt1;
+ u64 mac_flt0;
+ u64 casc_port;
+ u64 host_port;
+ u64 mirr_port;
+ u64 tpid;
+ u64 tpid2;
+};
+
+struct sja1105_vlan_lookup_entry {
+ u64 vmemb_port;
+ u64 vlan_bc;
+ u64 tag_port;
+ u64 vlanid;
+ u64 type_entry; /* SJA1110 only */
+};
+
+struct sja1105_l2_forwarding_entry {
+ u64 bc_domain;
+ u64 reach_port;
+ u64 fl_domain;
+};
+
+struct sja1105_l2_forwarding_params_entry {
+ u64 part_spc[SJA1105_NUM_TC];
+};
+
+struct sja1105_l2_policing_entry {
+ u64 sharindx;
+ u64 smax;
+ u64 rate;
+ u64 maxlen;
+ u64 partition;
+};
+
+struct sja1105_mac_config_entry {
+ u64 top[SJA1105_NUM_TC];
+ u64 base[SJA1105_NUM_TC];
+ u64 enabled[SJA1105_NUM_TC];
+ u64 speed;
+ u64 vlanid;
+ u64 egress;
+ u64 ingress;
+};
+
+struct sja1105_xmii_params_entry {
+ u64 phy_mac[SJA1105_MAX_NUM_PORTS];
+ u64 xmii_mode[SJA1105_MAX_NUM_PORTS];
+ u64 special[SJA1105_MAX_NUM_PORTS];
+};
+
+struct sja1105_table_header {
+ u64 block_id;
+ u64 len;
+ u64 crc;
+};
+
+struct sja1105_table_ops {
+ size_t (*packing)(void *buf, void *entry_ptr, enum packing_op op);
+ size_t unpacked_entry_size;
+ size_t packed_entry_size;
+ size_t max_entry_count;
+};
+
+struct sja1105_table {
+ const struct sja1105_table_ops *ops;
+ size_t entry_count;
+ void *entries;
+};
+
+struct sja1105_static_config {
+ u64 device_id;
+ struct sja1105_table tables[BLK_IDX_MAX];
+};
+
+struct sja1105_xpcs_cfg {
+ bool inband_an;
+ int speed;
+};
+
+struct sja1105_private {
+ struct sja1105_static_config static_config;
+ bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS];
+ bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS];
+ u16 pvid[SJA1105_MAX_NUM_PORTS];
+ struct sja1105_xpcs_cfg xpcs_cfg[SJA1105_MAX_NUM_PORTS];
+ struct mii_dev *mdio_pcs;
+ const struct sja1105_info *info;
+ struct udevice *dev;
+};
+
+typedef enum {
+ SPI_READ = 0,
+ SPI_WRITE = 1,
+} sja1105_spi_rw_mode_t;
+
+typedef enum {
+ XMII_MAC = 0,
+ XMII_PHY = 1,
+} sja1105_mii_role_t;
+
+typedef enum {
+ XMII_MODE_MII = 0,
+ XMII_MODE_RMII = 1,
+ XMII_MODE_RGMII = 2,
+ XMII_MODE_SGMII = 3,
+} sja1105_phy_interface_t;
+
+enum {
+ SJA1105_SPEED_AUTO,
+ SJA1105_SPEED_10MBPS,
+ SJA1105_SPEED_100MBPS,
+ SJA1105_SPEED_1000MBPS,
+ SJA1105_SPEED_MAX,
+};
+
+enum sja1110_vlan_type {
+ SJA1110_VLAN_INVALID = 0,
+ SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
+ SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
+ SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
+};
+
+/* Keeps the different addresses between E/T and P/Q/R/S */
+struct sja1105_regs {
+ u64 device_id;
+ u64 prod_id;
+ u64 status;
+ u64 port_control;
+ u64 rgu;
+ u64 config;
+ u64 rmii_pll1;
+ u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
+ u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
+ u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
+ u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
+ u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
+ u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
+ u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
+ u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
+ u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
+ u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
+ u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
+ u64 pcs_base[SJA1105_MAX_NUM_PORTS];
+};
+
+struct sja1105_info {
+ u64 device_id;
+ u64 part_no;
+ const struct sja1105_table_ops *static_ops;
+ const struct sja1105_regs *regs;
+ int (*reset_cmd)(struct sja1105_private *priv);
+ int (*setup_rgmii_delay)(struct sja1105_private *priv, int port);
+ int (*pcs_mdio_read)(struct mii_dev *bus, int phy, int mmd, int reg);
+ int (*pcs_mdio_write)(struct mii_dev *bus, int phy, int mmd, int reg,
+ u16 val);
+ int (*pma_config)(struct sja1105_private *priv, int port);
+ const char *name;
+ bool supports_mii[SJA1105_MAX_NUM_PORTS];
+ bool supports_rmii[SJA1105_MAX_NUM_PORTS];
+ bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
+ bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
+ const u64 port_speed[SJA1105_SPEED_MAX];
+};
+
+struct sja1105_chunk {
+ u8 *buf;
+ size_t len;
+ u64 reg_addr;
+};
+
+struct sja1105_spi_message {
+ u64 access;
+ u64 read_count;
+ u64 address;
+};
+
+/* Common structure for CFG_PAD_MIIx_RX and CFG_PAD_MIIx_TX */
+struct sja1105_cfg_pad_mii {
+ u64 d32_os;
+ u64 d32_ih;
+ u64 d32_ipud;
+ u64 d10_ih;
+ u64 d10_os;
+ u64 d10_ipud;
+ u64 ctrl_os;
+ u64 ctrl_ih;
+ u64 ctrl_ipud;
+ u64 clk_os;
+ u64 clk_ih;
+ u64 clk_ipud;
+};
+
+struct sja1105_cfg_pad_mii_id {
+ u64 rxc_stable_ovr;
+ u64 rxc_delay;
+ u64 rxc_bypass;
+ u64 rxc_pd;
+ u64 txc_stable_ovr;
+ u64 txc_delay;
+ u64 txc_bypass;
+ u64 txc_pd;
+};
+
+struct sja1105_cgu_idiv {
+ u64 clksrc;
+ u64 autoblock;
+ u64 idiv;
+ u64 pd;
+};
+
+struct sja1105_cgu_pll_ctrl {
+ u64 pllclksrc;
+ u64 msel;
+ u64 autoblock;
+ u64 psel;
+ u64 direct;
+ u64 fbsel;
+ u64 bypass;
+ u64 pd;
+};
+
+enum {
+ CLKSRC_MII0_TX_CLK = 0x00,
+ CLKSRC_MII0_RX_CLK = 0x01,
+ CLKSRC_MII1_TX_CLK = 0x02,
+ CLKSRC_MII1_RX_CLK = 0x03,
+ CLKSRC_MII2_TX_CLK = 0x04,
+ CLKSRC_MII2_RX_CLK = 0x05,
+ CLKSRC_MII3_TX_CLK = 0x06,
+ CLKSRC_MII3_RX_CLK = 0x07,
+ CLKSRC_MII4_TX_CLK = 0x08,
+ CLKSRC_MII4_RX_CLK = 0x09,
+ CLKSRC_PLL0 = 0x0B,
+ CLKSRC_PLL1 = 0x0E,
+ CLKSRC_IDIV0 = 0x11,
+ CLKSRC_IDIV1 = 0x12,
+ CLKSRC_IDIV2 = 0x13,
+ CLKSRC_IDIV3 = 0x14,
+ CLKSRC_IDIV4 = 0x15,
+};
+
+struct sja1105_cgu_mii_ctrl {
+ u64 clksrc;
+ u64 autoblock;
+ u64 pd;
+};
+
+static int get_reverse_lsw32_offset(int offset, size_t len)
+{
+ int closest_multiple_of_4;
+ int word_index;
+
+ word_index = offset / 4;
+ closest_multiple_of_4 = word_index * 4;
+ offset -= closest_multiple_of_4;
+ word_index = (len / 4) - word_index - 1;
+ return word_index * 4 + offset;
+}
+
+/* Simplified version of the "packing" function from Linux, adapted
+ * to support only sja1105's quirk: QUIRK_LSW32_IS_FIRST
+ */
+static void sja1105_packing(void *pbuf, u64 *uval, int startbit, int endbit,
+ size_t pbuflen, enum packing_op op)
+{
+ int plogical_first_u8, plogical_last_u8, box;
+
+ if (op == UNPACK)
+ *uval = 0;
+
+ plogical_first_u8 = startbit / 8;
+ plogical_last_u8 = endbit / 8;
+
+ for (box = plogical_first_u8; box >= plogical_last_u8; box--) {
+ int box_start_bit, box_end_bit, box_addr;
+ int proj_start_bit, proj_end_bit;
+ u64 proj_mask;
+ u8 box_mask;
+
+ if (box == plogical_first_u8)
+ box_start_bit = startbit % 8;
+ else
+ box_start_bit = 7;
+ if (box == plogical_last_u8)
+ box_end_bit = endbit % 8;
+ else
+ box_end_bit = 0;
+
+ proj_start_bit = ((box * 8) + box_start_bit) - endbit;
+ proj_end_bit = ((box * 8) + box_end_bit) - endbit;
+ proj_mask = GENMASK_ULL(proj_start_bit, proj_end_bit);
+ box_mask = GENMASK_ULL(box_start_bit, box_end_bit);
+
+ box_addr = pbuflen - box - 1;
+ box_addr = get_reverse_lsw32_offset(box_addr, pbuflen);
+
+ if (op == UNPACK) {
+ u64 pval;
+
+ /* Read from pbuf, write to uval */
+ pval = ((u8 *)pbuf)[box_addr] & box_mask;
+
+ pval >>= box_end_bit;
+ pval <<= proj_end_bit;
+ *uval &= ~proj_mask;
+ *uval |= pval;
+ } else {
+ u64 pval;
+
+ /* Write to pbuf, read from uval */
+ pval = (*uval) & proj_mask;
+ pval >>= proj_end_bit;
+
+ pval <<= box_end_bit;
+ ((u8 *)pbuf)[box_addr] &= ~box_mask;
+ ((u8 *)pbuf)[box_addr] |= pval;
+ }
+ }
+}
+
+static u32 crc32_add(u32 crc, u8 byte)
+{
+ u32 byte32 = bitrev32(byte);
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if ((crc ^ byte32) & BIT(31)) {
+ crc <<= 1;
+ crc ^= ETHER_CRC32_POLY;
+ } else {
+ crc <<= 1;
+ }
+ byte32 <<= 1;
+ }
+ return crc;
+}
+
+/* Little-endian Ethernet CRC32 of data packed as big-endian u32 words */
+static uint32_t sja1105_crc32(void *buf, size_t len)
+{
+ unsigned int i;
+ u64 chunk;
+ u32 crc;
+
+ /* seed */
+ crc = 0xFFFFFFFF;
+ for (i = 0; i < len; i += 4) {
+ sja1105_packing(buf + i, &chunk, 31, 0, 4, UNPACK);
+ crc = crc32_add(crc, chunk & 0xFF);
+ crc = crc32_add(crc, (chunk >> 8) & 0xFF);
+ crc = crc32_add(crc, (chunk >> 16) & 0xFF);
+ crc = crc32_add(crc, (chunk >> 24) & 0xFF);
+ }
+ return bitrev32(~crc);
+}
+
+static void sja1105_spi_message_pack(void *buf, struct sja1105_spi_message *msg)
+{
+ const int size = SJA1105_SIZE_SPI_MSG_HEADER;
+
+ memset(buf, 0, size);
+
+ sja1105_packing(buf, &msg->access, 31, 31, size, PACK);
+ sja1105_packing(buf, &msg->read_count, 30, 25, size, PACK);
+ sja1105_packing(buf, &msg->address, 24, 4, size, PACK);
+}
+
+static int sja1105_xfer_buf(const struct sja1105_private *priv,
+ sja1105_spi_rw_mode_t rw, u64 reg_addr,
+ u8 *buf, size_t len)
+{
+ struct udevice *dev = priv->dev;
+ struct sja1105_chunk chunk = {
+ .len = min_t(size_t, len, SJA1105_SIZE_SPI_MSG_MAXLEN),
+ .reg_addr = reg_addr,
+ .buf = buf,
+ };
+ int num_chunks;
+ int rc, i;
+
+ rc = dm_spi_claim_bus(dev);
+ if (rc)
+ return rc;
+
+ num_chunks = DIV_ROUND_UP(len, SJA1105_SIZE_SPI_MSG_MAXLEN);
+
+ for (i = 0; i < num_chunks; i++) {
+ u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER];
+ struct sja1105_spi_message msg;
+ u8 *rx_buf = NULL;
+ u8 *tx_buf = NULL;
+
+ /* Populate the transfer's header buffer */
+ msg.address = chunk.reg_addr;
+ msg.access = rw;
+ if (rw == SPI_READ)
+ msg.read_count = chunk.len / 4;
+ else
+ /* Ignored */
+ msg.read_count = 0;
+ sja1105_spi_message_pack(hdr_buf, &msg);
+ rc = dm_spi_xfer(dev, SJA1105_SIZE_SPI_MSG_HEADER * 8, hdr_buf,
+ NULL, SPI_XFER_BEGIN);
+ if (rc)
+ goto out;
+
+ /* Populate the transfer's data buffer */
+ if (rw == SPI_READ)
+ rx_buf = chunk.buf;
+ else
+ tx_buf = chunk.buf;
+ rc = dm_spi_xfer(dev, chunk.len * 8, tx_buf, rx_buf,
+ SPI_XFER_END);
+ if (rc)
+ goto out;
+
+ /* Calculate next chunk */
+ chunk.buf += chunk.len;
+ chunk.reg_addr += chunk.len / 4;
+ chunk.len = min_t(size_t, (ptrdiff_t)(buf + len - chunk.buf),
+ SJA1105_SIZE_SPI_MSG_MAXLEN);
+ }
+
+out:
+ dm_spi_release_bus(dev);
+
+ return rc;
+}
+
+static int sja1105et_reset_cmd(struct sja1105_private *priv)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_RESET_CMD] = {0};
+ const int size = SJA1105_SIZE_RESET_CMD;
+ u64 cold_rst = 1;
+
+ sja1105_packing(packed_buf, &cold_rst, 3, 3, size, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgu, packed_buf,
+ SJA1105_SIZE_RESET_CMD);
+}
+
+static int sja1105pqrs_reset_cmd(struct sja1105_private *priv)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_RESET_CMD] = {0};
+ const int size = SJA1105_SIZE_RESET_CMD;
+ u64 cold_rst = 1;
+
+ sja1105_packing(packed_buf, &cold_rst, 2, 2, size, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgu, packed_buf,
+ SJA1105_SIZE_RESET_CMD);
+}
+
+static int sja1110_reset_cmd(struct sja1105_private *priv)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_RESET_CMD] = {0};
+ const int size = SJA1105_SIZE_RESET_CMD;
+ u64 switch_rst = 1;
+
+ /* Only reset the switch core.
+ * A full cold reset would re-enable the BASE_MCSS_CLOCK PLL which
+ * would turn on the microcontroller, potentially letting it execute
+ * code which could interfere with our configuration.
+ */
+ sja1105_packing(packed_buf, &switch_rst, 20, 20, size, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgu, packed_buf,
+ SJA1105_SIZE_RESET_CMD);
+}
+
+static size_t sja1105et_general_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105ET_SIZE_GENERAL_PARAMS_ENTRY;
+ struct sja1105_general_params_entry *entry = entry_ptr;
+
+ sja1105_packing(buf, &entry->mac_fltres1, 311, 264, size, op);
+ sja1105_packing(buf, &entry->mac_fltres0, 263, 216, size, op);
+ sja1105_packing(buf, &entry->mac_flt1, 215, 168, size, op);
+ sja1105_packing(buf, &entry->mac_flt0, 167, 120, size, op);
+ sja1105_packing(buf, &entry->casc_port, 115, 113, size, op);
+ sja1105_packing(buf, &entry->host_port, 112, 110, size, op);
+ sja1105_packing(buf, &entry->mirr_port, 109, 107, size, op);
+ sja1105_packing(buf, &entry->tpid, 42, 27, size, op);
+ sja1105_packing(buf, &entry->tpid2, 25, 10, size, op);
+ return size;
+}
+
+static size_t sja1110_general_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ struct sja1105_general_params_entry *entry = entry_ptr;
+ const size_t size = SJA1110_SIZE_GENERAL_PARAMS_ENTRY;
+
+ sja1105_packing(buf, &entry->mac_fltres1, 438, 391, size, op);
+ sja1105_packing(buf, &entry->mac_fltres0, 390, 343, size, op);
+ sja1105_packing(buf, &entry->mac_flt1, 342, 295, size, op);
+ sja1105_packing(buf, &entry->mac_flt0, 294, 247, size, op);
+ sja1105_packing(buf, &entry->casc_port, 242, 232, size, op);
+ sja1105_packing(buf, &entry->host_port, 231, 228, size, op);
+ sja1105_packing(buf, &entry->mirr_port, 227, 224, size, op);
+ sja1105_packing(buf, &entry->tpid2, 159, 144, size, op);
+ sja1105_packing(buf, &entry->tpid, 142, 127, size, op);
+ return size;
+}
+
+static size_t
+sja1105pqrs_general_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105PQRS_SIZE_GENERAL_PARAMS_ENTRY;
+ struct sja1105_general_params_entry *entry = entry_ptr;
+
+ sja1105_packing(buf, &entry->mac_fltres1, 343, 296, size, op);
+ sja1105_packing(buf, &entry->mac_fltres0, 295, 248, size, op);
+ sja1105_packing(buf, &entry->mac_flt1, 247, 200, size, op);
+ sja1105_packing(buf, &entry->mac_flt0, 199, 152, size, op);
+ sja1105_packing(buf, &entry->casc_port, 147, 145, size, op);
+ sja1105_packing(buf, &entry->host_port, 144, 142, size, op);
+ sja1105_packing(buf, &entry->mirr_port, 141, 139, size, op);
+ sja1105_packing(buf, &entry->tpid, 74, 59, size, op);
+ sja1105_packing(buf, &entry->tpid2, 57, 42, size, op);
+ return size;
+}
+
+static size_t
+sja1105_l2_forwarding_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105_SIZE_L2_FORWARDING_PARAMS_ENTRY;
+ struct sja1105_l2_forwarding_params_entry *entry = entry_ptr;
+ int offset, i;
+
+ for (i = 0, offset = 13; i < SJA1105_NUM_TC; i++, offset += 10)
+ sja1105_packing(buf, &entry->part_spc[i],
+ offset + 9, offset + 0, size, op);
+ return size;
+}
+
+static size_t
+sja1110_l2_forwarding_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ struct sja1105_l2_forwarding_params_entry *entry = entry_ptr;
+ const size_t size = SJA1105_SIZE_L2_FORWARDING_PARAMS_ENTRY;
+ int offset, i;
+
+ for (i = 0, offset = 5; i < 8; i++, offset += 11)
+ sja1105_packing(buf, &entry->part_spc[i],
+ offset + 10, offset + 0, size, op);
+ return size;
+}
+
+static size_t sja1105_l2_forwarding_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105_SIZE_L2_FORWARDING_ENTRY;
+ struct sja1105_l2_forwarding_entry *entry = entry_ptr;
+
+ sja1105_packing(buf, &entry->bc_domain, 63, 59, size, op);
+ sja1105_packing(buf, &entry->reach_port, 58, 54, size, op);
+ sja1105_packing(buf, &entry->fl_domain, 53, 49, size, op);
+ return size;
+}
+
+static size_t sja1110_l2_forwarding_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ struct sja1105_l2_forwarding_entry *entry = entry_ptr;
+ const size_t size = SJA1105_SIZE_L2_FORWARDING_ENTRY;
+
+ sja1105_packing(buf, &entry->bc_domain, 63, 53, size, op);
+ sja1105_packing(buf, &entry->reach_port, 52, 42, size, op);
+ sja1105_packing(buf, &entry->fl_domain, 41, 31, size, op);
+ return size;
+}
+
+static size_t sja1105_l2_policing_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ struct sja1105_l2_policing_entry *entry = entry_ptr;
+ const size_t size = SJA1105_SIZE_L2_POLICING_ENTRY;
+
+ sja1105_packing(buf, &entry->sharindx, 63, 58, size, op);
+ sja1105_packing(buf, &entry->smax, 57, 42, size, op);
+ sja1105_packing(buf, &entry->rate, 41, 26, size, op);
+ sja1105_packing(buf, &entry->maxlen, 25, 15, size, op);
+ sja1105_packing(buf, &entry->partition, 14, 12, size, op);
+ return size;
+}
+
+static size_t sja1110_l2_policing_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ struct sja1105_l2_policing_entry *entry = entry_ptr;
+ const size_t size = SJA1105_SIZE_L2_POLICING_ENTRY;
+
+ sja1105_packing(buf, &entry->sharindx, 63, 57, size, op);
+ sja1105_packing(buf, &entry->smax, 56, 39, size, op);
+ sja1105_packing(buf, &entry->rate, 38, 21, size, op);
+ sja1105_packing(buf, &entry->maxlen, 20, 10, size, op);
+ sja1105_packing(buf, &entry->partition, 9, 7, size, op);
+ return size;
+}
+
+static size_t sja1105et_mac_config_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105ET_SIZE_MAC_CONFIG_ENTRY;
+ struct sja1105_mac_config_entry *entry = entry_ptr;
+ int offset, i;
+
+ for (i = 0, offset = 72; i < SJA1105_NUM_TC; i++, offset += 19) {
+ sja1105_packing(buf, &entry->enabled[i],
+ offset + 0, offset + 0, size, op);
+ sja1105_packing(buf, &entry->base[i],
+ offset + 9, offset + 1, size, op);
+ sja1105_packing(buf, &entry->top[i],
+ offset + 18, offset + 10, size, op);
+ }
+ sja1105_packing(buf, &entry->speed, 66, 65, size, op);
+ sja1105_packing(buf, &entry->vlanid, 21, 10, size, op);
+ sja1105_packing(buf, &entry->egress, 2, 2, size, op);
+ sja1105_packing(buf, &entry->ingress, 1, 1, size, op);
+ return size;
+}
+
+static size_t sja1105pqrs_mac_config_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105PQRS_SIZE_MAC_CONFIG_ENTRY;
+ struct sja1105_mac_config_entry *entry = entry_ptr;
+ int offset, i;
+
+ for (i = 0, offset = 104; i < SJA1105_NUM_TC; i++, offset += 19) {
+ sja1105_packing(buf, &entry->enabled[i],
+ offset + 0, offset + 0, size, op);
+ sja1105_packing(buf, &entry->base[i],
+ offset + 9, offset + 1, size, op);
+ sja1105_packing(buf, &entry->top[i],
+ offset + 18, offset + 10, size, op);
+ }
+ sja1105_packing(buf, &entry->speed, 98, 97, size, op);
+ sja1105_packing(buf, &entry->vlanid, 53, 42, size, op);
+ sja1105_packing(buf, &entry->egress, 32, 32, size, op);
+ sja1105_packing(buf, &entry->ingress, 31, 31, size, op);
+ return size;
+}
+
+static size_t sja1110_mac_config_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105PQRS_SIZE_MAC_CONFIG_ENTRY;
+ struct sja1105_mac_config_entry *entry = entry_ptr;
+ int offset, i;
+
+ for (i = 0, offset = 104; i < 8; i++, offset += 19) {
+ sja1105_packing(buf, &entry->enabled[i],
+ offset + 0, offset + 0, size, op);
+ sja1105_packing(buf, &entry->base[i],
+ offset + 9, offset + 1, size, op);
+ sja1105_packing(buf, &entry->top[i],
+ offset + 18, offset + 10, size, op);
+ }
+ sja1105_packing(buf, &entry->speed, 98, 96, size, op);
+ sja1105_packing(buf, &entry->vlanid, 52, 41, size, op);
+ sja1105_packing(buf, &entry->egress, 31, 31, size, op);
+ sja1105_packing(buf, &entry->ingress, 30, 30, size, op);
+ return size;
+}
+
+static size_t sja1105_vlan_lookup_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105_SIZE_VLAN_LOOKUP_ENTRY;
+ struct sja1105_vlan_lookup_entry *entry = entry_ptr;
+
+ sja1105_packing(buf, &entry->vmemb_port, 53, 49, size, op);
+ sja1105_packing(buf, &entry->vlan_bc, 48, 44, size, op);
+ sja1105_packing(buf, &entry->tag_port, 43, 39, size, op);
+ sja1105_packing(buf, &entry->vlanid, 38, 27, size, op);
+ return size;
+}
+
+static size_t sja1110_vlan_lookup_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ struct sja1105_vlan_lookup_entry *entry = entry_ptr;
+ const size_t size = SJA1110_SIZE_VLAN_LOOKUP_ENTRY;
+
+ sja1105_packing(buf, &entry->vmemb_port, 73, 63, size, op);
+ sja1105_packing(buf, &entry->vlan_bc, 62, 52, size, op);
+ sja1105_packing(buf, &entry->tag_port, 51, 41, size, op);
+ sja1105_packing(buf, &entry->type_entry, 40, 39, size, op);
+ sja1105_packing(buf, &entry->vlanid, 38, 27, size, op);
+ return size;
+}
+
+static size_t sja1105_xmii_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105_SIZE_XMII_PARAMS_ENTRY;
+ struct sja1105_xmii_params_entry *entry = entry_ptr;
+ int offset, i;
+
+ for (i = 0, offset = 17; i < SJA1105_NUM_PORTS; i++, offset += 3) {
+ sja1105_packing(buf, &entry->xmii_mode[i],
+ offset + 1, offset + 0, size, op);
+ sja1105_packing(buf, &entry->phy_mac[i],
+ offset + 2, offset + 2, size, op);
+ }
+ return size;
+}
+
+static size_t sja1110_xmii_params_entry_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1110_SIZE_XMII_PARAMS_ENTRY;
+ struct sja1105_xmii_params_entry *entry = entry_ptr;
+ int offset, i;
+
+ for (i = 0, offset = 20; i < SJA1110_NUM_PORTS; i++, offset += 4) {
+ sja1105_packing(buf, &entry->xmii_mode[i],
+ offset + 1, offset + 0, size, op);
+ sja1105_packing(buf, &entry->phy_mac[i],
+ offset + 2, offset + 2, size, op);
+ sja1105_packing(buf, &entry->special[i],
+ offset + 3, offset + 3, size, op);
+ }
+ return size;
+}
+
+static size_t sja1105_table_header_packing(void *buf, void *entry_ptr,
+ enum packing_op op)
+{
+ const size_t size = SJA1105_SIZE_TABLE_HEADER;
+ struct sja1105_table_header *entry = entry_ptr;
+
+ sja1105_packing(buf, &entry->block_id, 31, 24, size, op);
+ sja1105_packing(buf, &entry->len, 55, 32, size, op);
+ sja1105_packing(buf, &entry->crc, 95, 64, size, op);
+ return size;
+}
+
+static void
+sja1105_table_header_pack_with_crc(void *buf, struct sja1105_table_header *hdr)
+{
+ /* First pack the table as-is, then calculate the CRC, and
+ * finally put the proper CRC into the packed buffer
+ */
+ memset(buf, 0, SJA1105_SIZE_TABLE_HEADER);
+ sja1105_table_header_packing(buf, hdr, PACK);
+ hdr->crc = sja1105_crc32(buf, SJA1105_SIZE_TABLE_HEADER - 4);
+ sja1105_packing(buf + SJA1105_SIZE_TABLE_HEADER - 4, &hdr->crc,
+ 31, 0, 4, PACK);
+}
+
+static void sja1105_table_write_crc(u8 *table_start, u8 *crc_ptr)
+{
+ u64 computed_crc;
+ int len_bytes;
+
+ len_bytes = (uintptr_t)(crc_ptr - table_start);
+ computed_crc = sja1105_crc32(table_start, len_bytes);
+ sja1105_packing(crc_ptr, &computed_crc, 31, 0, 4, PACK);
+}
+
+/* The block IDs that the switches support are unfortunately sparse, so keep a
+ * mapping table to "block indices" and translate back and forth.
+ */
+static const u64 blk_id_map[BLK_IDX_MAX] = {
+ [BLK_IDX_L2_POLICING] = BLKID_L2_POLICING,
+ [BLK_IDX_VLAN_LOOKUP] = BLKID_VLAN_LOOKUP,
+ [BLK_IDX_L2_FORWARDING] = BLKID_L2_FORWARDING,
+ [BLK_IDX_MAC_CONFIG] = BLKID_MAC_CONFIG,
+ [BLK_IDX_L2_FORWARDING_PARAMS] = BLKID_L2_FORWARDING_PARAMS,
+ [BLK_IDX_GENERAL_PARAMS] = BLKID_GENERAL_PARAMS,
+ [BLK_IDX_XMII_PARAMS] = BLKID_XMII_PARAMS,
+};
+
+static void
+sja1105_static_config_pack(void *buf, struct sja1105_static_config *config)
+{
+ struct sja1105_table_header header = {0};
+ enum sja1105_blk_idx i;
+ u8 *p = buf;
+ int j;
+
+ sja1105_packing(p, &config->device_id, 31, 0, 4, PACK);
+ p += SJA1105_SIZE_DEVICE_ID;
+
+ for (i = 0; i < BLK_IDX_MAX; i++) {
+ const struct sja1105_table *table;
+ u8 *table_start;
+
+ table = &config->tables[i];
+ if (!table->entry_count)
+ continue;
+
+ header.block_id = blk_id_map[i];
+ header.len = table->entry_count *
+ table->ops->packed_entry_size / 4;
+ sja1105_table_header_pack_with_crc(p, &header);
+ p += SJA1105_SIZE_TABLE_HEADER;
+ table_start = p;
+ for (j = 0; j < table->entry_count; j++) {
+ u8 *entry_ptr = table->entries;
+
+ entry_ptr += j * table->ops->unpacked_entry_size;
+ memset(p, 0, table->ops->packed_entry_size);
+ table->ops->packing(p, entry_ptr, PACK);
+ p += table->ops->packed_entry_size;
+ }
+ sja1105_table_write_crc(table_start, p);
+ p += 4;
+ }
+ /* Final header:
+ * Block ID does not matter
+ * Length of 0 marks that header is final
+ * CRC will be replaced on-the-fly
+ */
+ header.block_id = 0;
+ header.len = 0;
+ header.crc = 0xDEADBEEF;
+ memset(p, 0, SJA1105_SIZE_TABLE_HEADER);
+ sja1105_table_header_packing(p, &header, PACK);
+}
+
+static size_t
+sja1105_static_config_get_length(const struct sja1105_static_config *config)
+{
+ unsigned int header_count;
+ enum sja1105_blk_idx i;
+ unsigned int sum;
+
+ /* Ending header */
+ header_count = 1;
+ sum = SJA1105_SIZE_DEVICE_ID;
+
+ /* Tables (headers and entries) */
+ for (i = 0; i < BLK_IDX_MAX; i++) {
+ const struct sja1105_table *table;
+
+ table = &config->tables[i];
+ if (table->entry_count)
+ header_count++;
+
+ sum += table->ops->packed_entry_size * table->entry_count;
+ }
+ /* Headers have an additional CRC at the end */
+ sum += header_count * (SJA1105_SIZE_TABLE_HEADER + 4);
+ /* Last header does not have an extra CRC because there is no data */
+ sum -= 4;
+
+ return sum;
+}
+
+/* Compatibility matrices */
+static const struct sja1105_table_ops sja1105et_table_ops[BLK_IDX_MAX] = {
+ [BLK_IDX_L2_POLICING] = {
+ .packing = sja1105_l2_policing_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_policing_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_POLICING_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_POLICING_COUNT,
+ },
+ [BLK_IDX_VLAN_LOOKUP] = {
+ .packing = sja1105_vlan_lookup_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_vlan_lookup_entry),
+ .packed_entry_size = SJA1105_SIZE_VLAN_LOOKUP_ENTRY,
+ .max_entry_count = SJA1105_MAX_VLAN_LOOKUP_COUNT,
+ },
+ [BLK_IDX_L2_FORWARDING] = {
+ .packing = sja1105_l2_forwarding_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_forwarding_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_FORWARDING_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_FORWARDING_COUNT,
+ },
+ [BLK_IDX_MAC_CONFIG] = {
+ .packing = sja1105et_mac_config_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_mac_config_entry),
+ .packed_entry_size = SJA1105ET_SIZE_MAC_CONFIG_ENTRY,
+ .max_entry_count = SJA1105_MAX_MAC_CONFIG_COUNT,
+ },
+ [BLK_IDX_L2_FORWARDING_PARAMS] = {
+ .packing = sja1105_l2_forwarding_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_forwarding_params_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_FORWARDING_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT,
+ },
+ [BLK_IDX_GENERAL_PARAMS] = {
+ .packing = sja1105et_general_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_general_params_entry),
+ .packed_entry_size = SJA1105ET_SIZE_GENERAL_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_GENERAL_PARAMS_COUNT,
+ },
+ [BLK_IDX_XMII_PARAMS] = {
+ .packing = sja1105_xmii_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_xmii_params_entry),
+ .packed_entry_size = SJA1105_SIZE_XMII_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_XMII_PARAMS_COUNT,
+ },
+};
+
+static const struct sja1105_table_ops sja1105pqrs_table_ops[BLK_IDX_MAX] = {
+ [BLK_IDX_L2_POLICING] = {
+ .packing = sja1105_l2_policing_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_policing_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_POLICING_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_POLICING_COUNT,
+ },
+ [BLK_IDX_VLAN_LOOKUP] = {
+ .packing = sja1105_vlan_lookup_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_vlan_lookup_entry),
+ .packed_entry_size = SJA1105_SIZE_VLAN_LOOKUP_ENTRY,
+ .max_entry_count = SJA1105_MAX_VLAN_LOOKUP_COUNT,
+ },
+ [BLK_IDX_L2_FORWARDING] = {
+ .packing = sja1105_l2_forwarding_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_forwarding_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_FORWARDING_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_FORWARDING_COUNT,
+ },
+ [BLK_IDX_MAC_CONFIG] = {
+ .packing = sja1105pqrs_mac_config_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_mac_config_entry),
+ .packed_entry_size = SJA1105PQRS_SIZE_MAC_CONFIG_ENTRY,
+ .max_entry_count = SJA1105_MAX_MAC_CONFIG_COUNT,
+ },
+ [BLK_IDX_L2_FORWARDING_PARAMS] = {
+ .packing = sja1105_l2_forwarding_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_forwarding_params_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_FORWARDING_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT,
+ },
+ [BLK_IDX_GENERAL_PARAMS] = {
+ .packing = sja1105pqrs_general_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_general_params_entry),
+ .packed_entry_size = SJA1105PQRS_SIZE_GENERAL_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_GENERAL_PARAMS_COUNT,
+ },
+ [BLK_IDX_XMII_PARAMS] = {
+ .packing = sja1105_xmii_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_xmii_params_entry),
+ .packed_entry_size = SJA1105_SIZE_XMII_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_XMII_PARAMS_COUNT,
+ },
+};
+
+static const struct sja1105_table_ops sja1110_table_ops[BLK_IDX_MAX] = {
+ [BLK_IDX_L2_POLICING] = {
+ .packing = sja1110_l2_policing_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_policing_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_POLICING_ENTRY,
+ .max_entry_count = SJA1110_MAX_L2_POLICING_COUNT,
+ },
+ [BLK_IDX_VLAN_LOOKUP] = {
+ .packing = sja1110_vlan_lookup_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_vlan_lookup_entry),
+ .packed_entry_size = SJA1110_SIZE_VLAN_LOOKUP_ENTRY,
+ .max_entry_count = SJA1105_MAX_VLAN_LOOKUP_COUNT,
+ },
+ [BLK_IDX_L2_FORWARDING] = {
+ .packing = sja1110_l2_forwarding_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_forwarding_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_FORWARDING_ENTRY,
+ .max_entry_count = SJA1110_MAX_L2_FORWARDING_COUNT,
+ },
+ [BLK_IDX_MAC_CONFIG] = {
+ .packing = sja1110_mac_config_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_mac_config_entry),
+ .packed_entry_size = SJA1105PQRS_SIZE_MAC_CONFIG_ENTRY,
+ .max_entry_count = SJA1110_MAX_MAC_CONFIG_COUNT,
+ },
+ [BLK_IDX_L2_FORWARDING_PARAMS] = {
+ .packing = sja1110_l2_forwarding_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_l2_forwarding_params_entry),
+ .packed_entry_size = SJA1105_SIZE_L2_FORWARDING_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT,
+ },
+ [BLK_IDX_GENERAL_PARAMS] = {
+ .packing = sja1110_general_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_general_params_entry),
+ .packed_entry_size = SJA1110_SIZE_GENERAL_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_GENERAL_PARAMS_COUNT,
+ },
+ [BLK_IDX_XMII_PARAMS] = {
+ .packing = sja1110_xmii_params_entry_packing,
+ .unpacked_entry_size = sizeof(struct sja1105_xmii_params_entry),
+ .packed_entry_size = SJA1110_SIZE_XMII_PARAMS_ENTRY,
+ .max_entry_count = SJA1105_MAX_XMII_PARAMS_COUNT,
+ },
+};
+
+static int sja1105_init_mii_settings(struct sja1105_private *priv)
+{
+ struct sja1105_table *table;
+
+ table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
+
+ table->entries = calloc(SJA1105_MAX_XMII_PARAMS_COUNT,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ /* Table will be populated at runtime */
+ table->entry_count = SJA1105_MAX_XMII_PARAMS_COUNT;
+
+ return 0;
+}
+
+static void sja1105_setup_tagging(struct sja1105_private *priv, int port)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ struct sja1105_vlan_lookup_entry *vlan;
+ int cpu = pdata->cpu_port;
+
+ /* The CPU port is implicitly configured by
+ * configuring the front-panel ports
+ */
+ if (port == cpu)
+ return;
+
+ vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
+
+ priv->pvid[port] = DSA_8021Q_DIR_TX | DSA_8021Q_PORT(port);
+
+ vlan[port].vmemb_port = BIT(port) | BIT(cpu);
+ vlan[port].vlan_bc = BIT(port) | BIT(cpu);
+ vlan[port].tag_port = BIT(cpu);
+ vlan[port].vlanid = priv->pvid[port];
+ vlan[port].type_entry = SJA1110_VLAN_D_TAG;
+}
+
+static int sja1105_init_vlan(struct sja1105_private *priv)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ struct sja1105_table *table;
+ int port;
+
+ table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
+
+ table->entries = calloc(pdata->num_ports,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ table->entry_count = pdata->num_ports;
+
+ for (port = 0; port < pdata->num_ports; port++)
+ sja1105_setup_tagging(priv, port);
+
+ return 0;
+}
+
+static void
+sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
+ int from, int to)
+{
+ l2_fwd[from].bc_domain |= BIT(to);
+ l2_fwd[from].reach_port |= BIT(to);
+ l2_fwd[from].fl_domain |= BIT(to);
+}
+
+static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ struct sja1105_l2_forwarding_entry *l2fwd;
+ struct sja1105_table *table;
+ int cpu = pdata->cpu_port;
+ int i;
+
+ table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
+
+ table->entries = calloc(SJA1105_MAX_L2_FORWARDING_COUNT,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ table->entry_count = SJA1105_MAX_L2_FORWARDING_COUNT;
+
+ l2fwd = table->entries;
+
+ /* First 5 entries define the forwarding rules */
+ for (i = 0; i < pdata->num_ports; i++) {
+ if (i == cpu)
+ continue;
+
+ sja1105_port_allow_traffic(l2fwd, i, cpu);
+ sja1105_port_allow_traffic(l2fwd, cpu, i);
+ }
+ /* Next 8 entries define VLAN PCP mapping from ingress to egress.
+ * Leave them unpopulated (implicitly 0) but present.
+ */
+ return 0;
+}
+
+static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
+{
+ struct sja1105_l2_forwarding_params_entry default_l2fwd_params = {
+ /* Use a single memory partition for all ingress queues */
+ .part_spc = { SJA1105_MAX_FRAME_MEMORY, 0, 0, 0, 0, 0, 0, 0 },
+ };
+ struct sja1105_table *table;
+
+ table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
+
+ table->entries = calloc(SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ table->entry_count = SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT;
+
+ /* This table only has a single entry */
+ ((struct sja1105_l2_forwarding_params_entry *)table->entries)[0] =
+ default_l2fwd_params;
+
+ return 0;
+}
+
+static int sja1105_init_general_params(struct sja1105_private *priv)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ struct sja1105_general_params_entry default_general_params = {
+ /* No frame trapping */
+ .mac_fltres1 = 0x0,
+ .mac_flt1 = 0xffffffffffff,
+ .mac_fltres0 = 0x0,
+ .mac_flt0 = 0xffffffffffff,
+ .host_port = pdata->num_ports,
+ /* No mirroring => specify an out-of-range port value */
+ .mirr_port = pdata->num_ports,
+ /* No link-local trapping => specify an out-of-range port value
+ */
+ .casc_port = pdata->num_ports,
+ /* Force the switch to see all traffic as untagged. */
+ .tpid = ETH_P_SJA1105,
+ .tpid2 = ETH_P_SJA1105,
+ };
+ struct sja1105_table *table;
+
+ table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
+
+ table->entries = calloc(SJA1105_MAX_GENERAL_PARAMS_COUNT,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ table->entry_count = SJA1105_MAX_GENERAL_PARAMS_COUNT;
+
+ /* This table only has a single entry */
+ ((struct sja1105_general_params_entry *)table->entries)[0] =
+ default_general_params;
+
+ return 0;
+}
+
+static void sja1105_setup_policer(struct sja1105_l2_policing_entry *policing,
+ int index, int mtu)
+{
+ policing[index].sharindx = index;
+ policing[index].smax = 65535; /* Burst size in bytes */
+ policing[index].rate = SJA1105_RATE_MBPS(1000);
+ policing[index].maxlen = mtu;
+ policing[index].partition = 0;
+}
+
+static int sja1105_init_l2_policing(struct sja1105_private *priv)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ struct sja1105_l2_policing_entry *policing;
+ struct sja1105_table *table;
+ int cpu = pdata->cpu_port;
+ int i, j, k;
+
+ table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
+
+ table->entries = calloc(SJA1105_MAX_L2_POLICING_COUNT,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ table->entry_count = SJA1105_MAX_L2_POLICING_COUNT;
+
+ policing = table->entries;
+
+ /* k sweeps through all unicast policers (0-39).
+ * bcast sweeps through policers 40-44.
+ */
+ for (i = 0, k = 0; i < pdata->num_ports; i++) {
+ int bcast = (pdata->num_ports * SJA1105_NUM_TC) + i;
+ int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
+
+ if (i == cpu)
+ mtu += VLAN_HLEN;
+
+ for (j = 0; j < SJA1105_NUM_TC; j++, k++)
+ sja1105_setup_policer(policing, k, mtu);
+
+ /* Set up this port's policer for broadcast traffic */
+ sja1105_setup_policer(policing, bcast, mtu);
+ }
+ return 0;
+}
+
+static int sja1105_init_mac_settings(struct sja1105_private *priv)
+{
+ struct sja1105_mac_config_entry default_mac = {
+ /* Enable 1 priority queue on egress. */
+ .top = {0x1FF, 0, 0, 0, 0, 0, 0},
+ .base = {0x0, 0, 0, 0, 0, 0, 0, 0},
+ .enabled = {1, 0, 0, 0, 0, 0, 0, 0},
+ /* Will be overridden in sja1105_port_enable. */
+ .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
+ .egress = true,
+ .ingress = true,
+ };
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ struct sja1105_mac_config_entry *mac;
+ struct sja1105_table *table;
+ int port;
+
+ table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
+
+ table->entries = calloc(pdata->num_ports,
+ table->ops->unpacked_entry_size);
+ if (!table->entries)
+ return -ENOMEM;
+
+ table->entry_count = pdata->num_ports;
+
+ mac = table->entries;
+
+ for (port = 0; port < pdata->num_ports; port++) {
+ mac[port] = default_mac;
+ /* Internal VLAN (pvid) to apply to untagged ingress */
+ mac[port].vlanid = priv->pvid[port];
+ }
+
+ return 0;
+}
+
+static int sja1105_static_config_init(struct sja1105_private *priv)
+{
+ struct sja1105_static_config *config = &priv->static_config;
+ const struct sja1105_table_ops *static_ops = priv->info->static_ops;
+ u64 device_id = priv->info->device_id;
+ enum sja1105_blk_idx i;
+ int rc;
+
+ *config = (struct sja1105_static_config) {0};
+
+ /* Transfer static_ops array from priv into per-table ops
+ * for handier access
+ */
+ for (i = 0; i < BLK_IDX_MAX; i++)
+ config->tables[i].ops = &static_ops[i];
+
+ config->device_id = device_id;
+
+ /* Build initial static configuration, to be fixed up during runtime */
+ rc = sja1105_init_vlan(priv);
+ if (rc < 0)
+ return rc;
+ rc = sja1105_init_mac_settings(priv);
+ if (rc < 0)
+ return rc;
+ rc = sja1105_init_mii_settings(priv);
+ if (rc < 0)
+ return rc;
+ rc = sja1105_init_l2_forwarding(priv);
+ if (rc < 0)
+ return rc;
+ rc = sja1105_init_l2_forwarding_params(priv);
+ if (rc < 0)
+ return rc;
+ rc = sja1105_init_l2_policing(priv);
+ if (rc < 0)
+ return rc;
+ rc = sja1105_init_general_params(priv);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+static void sja1105_static_config_free(struct sja1105_static_config *config)
+{
+ enum sja1105_blk_idx i;
+
+ for (i = 0; i < BLK_IDX_MAX; i++) {
+ if (config->tables[i].entry_count) {
+ free(config->tables[i].entries);
+ config->tables[i].entry_count = 0;
+ }
+ }
+}
+
+static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv,
+ enum packing_op op)
+{
+ const int size = 4;
+
+ sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op);
+ sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op);
+ sja1105_packing(buf, &idiv->idiv, 5, 2, size, op);
+ sja1105_packing(buf, &idiv->pd, 0, 0, size, op);
+}
+
+static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
+ bool enabled, int factor)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ struct sja1105_cgu_idiv idiv;
+
+ if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ if (enabled && factor != 1 && factor != 10)
+ return -ERANGE;
+
+ /* Payload for packed_buf */
+ idiv.clksrc = 0x0A; /* 25MHz */
+ idiv.autoblock = 1; /* Block clk automatically */
+ idiv.idiv = factor - 1; /* Divide by 1 or 10 */
+ idiv.pd = enabled ? 0 : 1; /* Power down? */
+ sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static void
+sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd,
+ enum packing_op op)
+{
+ const int size = 4;
+
+ sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op);
+ sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
+ sja1105_packing(buf, &cmd->pd, 0, 0, size, op);
+}
+
+static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
+ int port, sja1105_mii_role_t role)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cgu_mii_ctrl mii_tx_clk;
+ const int mac_clk_sources[] = {
+ CLKSRC_MII0_TX_CLK,
+ CLKSRC_MII1_TX_CLK,
+ CLKSRC_MII2_TX_CLK,
+ CLKSRC_MII3_TX_CLK,
+ CLKSRC_MII4_TX_CLK,
+ };
+ const int phy_clk_sources[] = {
+ CLKSRC_IDIV0,
+ CLKSRC_IDIV1,
+ CLKSRC_IDIV2,
+ CLKSRC_IDIV3,
+ CLKSRC_IDIV4,
+ };
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ int clksrc;
+
+ if (regs->mii_tx_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ if (role == XMII_MAC)
+ clksrc = mac_clk_sources[port];
+ else
+ clksrc = phy_clk_sources[port];
+
+ /* Payload for packed_buf */
+ mii_tx_clk.clksrc = clksrc;
+ mii_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
+ mii_tx_clk.pd = 0; /* Power Down off => enabled */
+ sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int
+sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ struct sja1105_cgu_mii_ctrl mii_rx_clk;
+ const int clk_sources[] = {
+ CLKSRC_MII0_RX_CLK,
+ CLKSRC_MII1_RX_CLK,
+ CLKSRC_MII2_RX_CLK,
+ CLKSRC_MII3_RX_CLK,
+ CLKSRC_MII4_RX_CLK,
+ };
+
+ if (regs->mii_rx_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload for packed_buf */
+ mii_rx_clk.clksrc = clk_sources[port];
+ mii_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
+ mii_rx_clk.pd = 0; /* Power Down off => enabled */
+ sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int
+sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cgu_mii_ctrl mii_ext_tx_clk;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ const int clk_sources[] = {
+ CLKSRC_IDIV0,
+ CLKSRC_IDIV1,
+ CLKSRC_IDIV2,
+ CLKSRC_IDIV3,
+ CLKSRC_IDIV4,
+ };
+
+ if (regs->mii_ext_tx_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload for packed_buf */
+ mii_ext_tx_clk.clksrc = clk_sources[port];
+ mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
+ mii_ext_tx_clk.pd = 0; /* Power Down off => enabled */
+ sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int
+sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cgu_mii_ctrl mii_ext_rx_clk;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ const int clk_sources[] = {
+ CLKSRC_IDIV0,
+ CLKSRC_IDIV1,
+ CLKSRC_IDIV2,
+ CLKSRC_IDIV3,
+ CLKSRC_IDIV4,
+ };
+
+ if (regs->mii_ext_rx_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload for packed_buf */
+ mii_ext_rx_clk.clksrc = clk_sources[port];
+ mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
+ mii_ext_rx_clk.pd = 0; /* Power Down off => enabled */
+ sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port,
+ sja1105_mii_role_t role)
+{
+ int rc;
+
+ rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_cgu_mii_tx_clk_config(priv, port, role);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_cgu_mii_rx_clk_config(priv, port);
+ if (rc < 0)
+ return rc;
+
+ if (role == XMII_PHY) {
+ rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port);
+ if (rc < 0)
+ return rc;
+ }
+ return 0;
+}
+
+static void
+sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd,
+ enum packing_op op)
+{
+ const int size = 4;
+
+ sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op);
+ sja1105_packing(buf, &cmd->msel, 23, 16, size, op);
+ sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
+ sja1105_packing(buf, &cmd->psel, 9, 8, size, op);
+ sja1105_packing(buf, &cmd->direct, 7, 7, size, op);
+ sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op);
+ sja1105_packing(buf, &cmd->bypass, 1, 1, size, op);
+ sja1105_packing(buf, &cmd->pd, 0, 0, size, op);
+}
+
+static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
+ int port, u64 speed)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cgu_mii_ctrl txc;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ int clksrc;
+
+ if (regs->rgmii_tx_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) {
+ clksrc = CLKSRC_PLL0;
+ } else {
+ int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2,
+ CLKSRC_IDIV3, CLKSRC_IDIV4};
+ clksrc = clk_sources[port];
+ }
+
+ /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */
+ txc.clksrc = clksrc;
+ /* Autoblock clk while changing clksrc */
+ txc.autoblock = 1;
+ /* Power Down off => enabled */
+ txc.pd = 0;
+ sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+/* AGU */
+static void
+sja1105_cfg_pad_mii_packing(void *buf, struct sja1105_cfg_pad_mii *cmd,
+ enum packing_op op)
+{
+ const int size = 4;
+
+ sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op);
+ sja1105_packing(buf, &cmd->d32_ih, 26, 26, size, op);
+ sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op);
+ sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op);
+ sja1105_packing(buf, &cmd->d10_ih, 18, 18, size, op);
+ sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op);
+ sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op);
+ sja1105_packing(buf, &cmd->ctrl_ih, 10, 10, size, op);
+ sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op);
+ sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op);
+ sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op);
+ sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op);
+}
+
+static void
+sja1110_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
+ enum packing_op op)
+{
+ const int size = SJA1105_SIZE_CGU_CMD;
+ u64 range = 4;
+
+ /* Fields RXC_RANGE and TXC_RANGE select the input frequency range:
+ * 0 = 2.5MHz
+ * 1 = 25MHz
+ * 2 = 50MHz
+ * 3 = 125MHz
+ * 4 = Automatically determined by port speed.
+ * There's no point in defining a structure different than the one for
+ * SJA1105, so just hardcode the frequency range to automatic, just as
+ * before.
+ */
+ sja1105_packing(buf, &cmd->rxc_stable_ovr, 26, 26, size, op);
+ sja1105_packing(buf, &cmd->rxc_delay, 25, 21, size, op);
+ sja1105_packing(buf, &range, 20, 18, size, op);
+ sja1105_packing(buf, &cmd->rxc_bypass, 17, 17, size, op);
+ sja1105_packing(buf, &cmd->rxc_pd, 16, 16, size, op);
+ sja1105_packing(buf, &cmd->txc_stable_ovr, 10, 10, size, op);
+ sja1105_packing(buf, &cmd->txc_delay, 9, 5, size, op);
+ sja1105_packing(buf, &range, 4, 2, size, op);
+ sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op);
+ sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op);
+}
+
+static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
+ int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cfg_pad_mii pad_mii_tx = {0};
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+
+ if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload */
+ pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */
+ /* high noise/high speed */
+ pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */
+ /* high noise/high speed */
+ pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */
+ /* plain input (default) */
+ pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */
+ /* plain input (default) */
+ pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */
+ pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */
+ pad_mii_tx.clk_os = 3; /* TX_CLK output stage */
+ pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */
+ pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */
+ sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_tx, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int sja1105_cfg_pad_rx_config(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cfg_pad_mii pad_mii_rx = {0};
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+
+ if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload */
+ pad_mii_rx.d32_ih = 0; /* RXD[3:2] input stage hysteresis: */
+ /* non-Schmitt (default) */
+ pad_mii_rx.d32_ipud = 2; /* RXD[3:2] input weak pull-up/down */
+ /* plain input (default) */
+ pad_mii_rx.d10_ih = 0; /* RXD[1:0] input stage hysteresis: */
+ /* non-Schmitt (default) */
+ pad_mii_rx.d10_ipud = 2; /* RXD[1:0] input weak pull-up/down */
+ /* plain input (default) */
+ pad_mii_rx.ctrl_ih = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */
+ /* input stage hysteresis: */
+ /* non-Schmitt (default) */
+ pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */
+ /* input stage weak pull-up/down: */
+ /* pull-down */
+ pad_mii_rx.clk_os = 2; /* RX_CLK/RXC output stage: */
+ /* medium noise/fast speed (default) */
+ pad_mii_rx.clk_ih = 0; /* RX_CLK/RXC input hysteresis: */
+ /* non-Schmitt (default) */
+ pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */
+ /* plain input (default) */
+ sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_rx, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static void
+sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
+ enum packing_op op)
+{
+ const int size = SJA1105_SIZE_CGU_CMD;
+
+ sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op);
+ sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op);
+ sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op);
+ sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op);
+ sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op);
+ sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op);
+ sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op);
+ sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op);
+}
+
+/* Valid range in degrees is an integer between 73.8 and 101.7 */
+static u64 sja1105_rgmii_delay(u64 phase)
+{
+ /* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9.
+ * To avoid floating point operations we'll multiply by 10
+ * and get 1 decimal point precision.
+ */
+ phase *= 10;
+ return (phase - 738) / 9;
+}
+
+static int sja1105pqrs_setup_rgmii_delay(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ int rc;
+
+ if (priv->rgmii_rx_delay[port])
+ pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
+ if (priv->rgmii_tx_delay[port])
+ pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
+
+ /* Stage 1: Turn the RGMII delay lines off. */
+ pad_mii_id.rxc_bypass = 1;
+ pad_mii_id.rxc_pd = 1;
+ pad_mii_id.txc_bypass = 1;
+ pad_mii_id.txc_pd = 1;
+ sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
+
+ rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+ if (rc < 0)
+ return rc;
+
+ /* Stage 2: Turn the RGMII delay lines on. */
+ if (priv->rgmii_rx_delay[port]) {
+ pad_mii_id.rxc_bypass = 0;
+ pad_mii_id.rxc_pd = 0;
+ }
+ if (priv->rgmii_tx_delay[port]) {
+ pad_mii_id.txc_bypass = 0;
+ pad_mii_id.txc_pd = 0;
+ }
+ sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int sja1110_setup_rgmii_delay(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+
+ pad_mii_id.rxc_pd = 1;
+ pad_mii_id.txc_pd = 1;
+
+ if (priv->rgmii_rx_delay[port]) {
+ pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
+ /* The "BYPASS" bit in SJA1110 is actually a "don't bypass" */
+ pad_mii_id.rxc_bypass = 1;
+ pad_mii_id.rxc_pd = 0;
+ }
+
+ if (priv->rgmii_tx_delay[port]) {
+ pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
+ pad_mii_id.txc_bypass = 1;
+ pad_mii_id.txc_pd = 0;
+ }
+
+ sja1110_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port,
+ sja1105_mii_role_t role)
+{
+ struct sja1105_mac_config_entry *mac;
+ struct udevice *dev = priv->dev;
+ u64 speed;
+ int rc;
+
+ mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
+ speed = mac[port].speed;
+
+ if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) {
+ /* 1000Mbps, IDIV disabled (125 MHz) */
+ rc = sja1105_cgu_idiv_config(priv, port, false, 1);
+ } else if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) {
+ /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */
+ rc = sja1105_cgu_idiv_config(priv, port, true, 1);
+ } else if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) {
+ /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */
+ rc = sja1105_cgu_idiv_config(priv, port, true, 10);
+ } else if (speed == priv->info->port_speed[SJA1105_SPEED_AUTO]) {
+ /* Skip CGU configuration if there is no speed available
+ * (e.g. link is not established yet)
+ */
+ dev_dbg(dev, "Speed not available, skipping CGU config\n");
+ return 0;
+ } else {
+ rc = -EINVAL;
+ }
+
+ if (rc < 0) {
+ dev_err(dev, "Failed to configure idiv\n");
+ return rc;
+ }
+ rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed);
+ if (rc < 0) {
+ dev_err(dev, "Failed to configure RGMII Tx clock\n");
+ return rc;
+ }
+ rc = sja1105_rgmii_cfg_pad_tx_config(priv, port);
+ if (rc < 0) {
+ dev_err(dev, "Failed to configure Tx pad registers\n");
+ return rc;
+ }
+
+ if (!priv->info->setup_rgmii_delay)
+ return 0;
+
+ return priv->info->setup_rgmii_delay(priv, port);
+}
+
+static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
+ int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ struct sja1105_cgu_mii_ctrl ref_clk;
+ const int clk_sources[] = {
+ CLKSRC_MII0_TX_CLK,
+ CLKSRC_MII1_TX_CLK,
+ CLKSRC_MII2_TX_CLK,
+ CLKSRC_MII3_TX_CLK,
+ CLKSRC_MII4_TX_CLK,
+ };
+
+ if (regs->rmii_ref_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload for packed_buf */
+ ref_clk.clksrc = clk_sources[port];
+ ref_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
+ ref_clk.pd = 0; /* Power Down off => enabled */
+ sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int
+sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_cgu_mii_ctrl ext_tx_clk;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+
+ if (regs->rmii_ext_tx_clk[port] == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Payload for packed_buf */
+ ext_tx_clk.clksrc = CLKSRC_PLL1;
+ ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
+ ext_tx_clk.pd = 0; /* Power Down off => enabled */
+ sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port],
+ packed_buf, SJA1105_SIZE_CGU_CMD);
+}
+
+static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
+ struct sja1105_cgu_pll_ctrl pll = {0};
+ int rc;
+
+ if (regs->rmii_pll1 == SJA1105_RSV_ADDR)
+ return 0;
+
+ /* Step 1: PLL1 setup for 50Mhz */
+ pll.pllclksrc = 0xA;
+ pll.msel = 0x1;
+ pll.autoblock = 0x1;
+ pll.psel = 0x1;
+ pll.direct = 0x0;
+ pll.fbsel = 0x1;
+ pll.bypass = 0x0;
+ pll.pd = 0x1;
+
+ sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
+ rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
+ SJA1105_SIZE_CGU_CMD);
+ if (rc < 0)
+ return rc;
+
+ /* Step 2: Enable PLL1 */
+ pll.pd = 0x0;
+
+ sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
+ rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
+ SJA1105_SIZE_CGU_CMD);
+ return rc;
+}
+
+static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port,
+ sja1105_mii_role_t role)
+{
+ int rc;
+
+ /* AH1601.pdf chapter 2.5.1. Sources */
+ if (role == XMII_MAC) {
+ /* Configure and enable PLL1 for 50Mhz output */
+ rc = sja1105_cgu_rmii_pll_config(priv);
+ if (rc < 0)
+ return rc;
+ }
+ /* Disable IDIV for this port */
+ rc = sja1105_cgu_idiv_config(priv, port, false, 1);
+ if (rc < 0)
+ return rc;
+ /* Source to sink mappings */
+ rc = sja1105_cgu_rmii_ref_clk_config(priv, port);
+ if (rc < 0)
+ return rc;
+ if (role == XMII_MAC) {
+ rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port);
+ if (rc < 0)
+ return rc;
+ }
+ return 0;
+}
+
+static int sja1105_pcs_read(struct sja1105_private *priv, int addr,
+ int devad, int regnum)
+{
+ return priv->mdio_pcs->read(priv->mdio_pcs, addr, devad, regnum);
+}
+
+static int sja1105_pcs_write(struct sja1105_private *priv, int addr,
+ int devad, int regnum, u16 val)
+{
+ return priv->mdio_pcs->write(priv->mdio_pcs, addr, devad, regnum, val);
+}
+
+/* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
+ * polarity inverted by default (PLUS is MINUS, MINUS is PLUS). To obtain
+ * normal non-inverted behavior, the TX lane polarity must be inverted in the
+ * PCS, via the DIGITAL_CONTROL_2 register.
+ */
+static int sja1105_pma_config(struct sja1105_private *priv, int port)
+{
+ return sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ DW_VR_MII_DIG_CTRL2,
+ DW_VR_MII_DIG_CTRL2_TX_POL_INV);
+}
+
+static int sja1110_pma_config(struct sja1105_private *priv, int port)
+{
+ u16 txpll_fbdiv = 0x19, txpll_refdiv = 0x1;
+ u16 rxpll_fbdiv = 0x19, rxpll_refdiv = 0x1;
+ u16 rx_cdr_ctle = 0x212a;
+ u16 val;
+ int rc;
+
+ /* Program TX PLL feedback divider and reference divider settings for
+ * correct oscillation frequency.
+ */
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0,
+ SJA1110_TXPLL_FBDIV(txpll_fbdiv));
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1,
+ SJA1110_TXPLL_REFDIV(txpll_refdiv));
+ if (rc < 0)
+ return rc;
+
+ /* Program transmitter amplitude and disable amplitude trimming */
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ SJA1110_LANE_DRIVER1_0, SJA1110_TXDRV(0x5));
+ if (rc < 0)
+ return rc;
+
+ val = SJA1110_TXDRVTRIM_LSB(0xffffffull);
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ SJA1110_LANE_DRIVER2_0, val);
+ if (rc < 0)
+ return rc;
+
+ val = SJA1110_TXDRVTRIM_MSB(0xffffffull) | SJA1110_LANE_DRIVER2_1_RSV;
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ SJA1110_LANE_DRIVER2_1, val);
+ if (rc < 0)
+ return rc;
+
+ /* Enable input and output resistor terminations for low BER. */
+ val = SJA1110_ACCOUPLE_RXVCM_EN | SJA1110_CDR_GAIN |
+ SJA1110_RXRTRIM(4) | SJA1110_RXTEN | SJA1110_TXPLL_BWSEL |
+ SJA1110_TXRTRIM(3) | SJA1110_TXTEN;
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, SJA1110_LANE_TRIM,
+ val);
+ if (rc < 0)
+ return rc;
+
+ /* Select PCS as transmitter data source. */
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ SJA1110_LANE_DATAPATH_1, 0);
+ if (rc < 0)
+ return rc;
+
+ /* Program RX PLL feedback divider and reference divider for correct
+ * oscillation frequency.
+ */
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0,
+ SJA1110_RXPLL_FBDIV(rxpll_fbdiv));
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1,
+ SJA1110_RXPLL_REFDIV(rxpll_refdiv));
+ if (rc < 0)
+ return rc;
+
+ /* Program threshold for receiver signal detector.
+ * Enable control of RXPLL by receiver signal detector to disable RXPLL
+ * when an input signal is not present.
+ */
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ SJA1110_RX_DATA_DETECT, 0x0005);
+ if (rc < 0)
+ return rc;
+
+ /* Enable TX and RX PLLs and circuits.
+ * Release reset of PMA to enable data flow to/from PCS.
+ */
+ rc = sja1105_pcs_read(priv, port, MDIO_MMD_VEND2,
+ SJA1110_POWERDOWN_ENABLE);
+ if (rc < 0)
+ return rc;
+
+ val = rc & ~(SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD |
+ SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN |
+ SJA1110_RESET_SER | SJA1110_RESET_DES);
+ val |= SJA1110_RXPKDETEN | SJA1110_RCVEN;
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2,
+ SJA1110_POWERDOWN_ENABLE, val);
+ if (rc < 0)
+ return rc;
+
+ /* Program continuous-time linear equalizer (CTLE) settings. */
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE,
+ rx_cdr_ctle);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+static int sja1105_xpcs_config_aneg_c37_sgmii(struct sja1105_private *priv,
+ int port)
+{
+ int rc;
+
+ rc = sja1105_pcs_read(priv, port, MDIO_MMD_VEND2, MDIO_CTRL1);
+ if (rc < 0)
+ return rc;
+ rc &= ~MDIO_AN_CTRL1_ENABLE;
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, MDIO_CTRL1,
+ rc);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_pcs_read(priv, port, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
+ if (rc < 0)
+ return rc;
+
+ rc &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
+ rc |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
+ DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
+ DW_VR_MII_PCS_MODE_MASK);
+ rc |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
+ DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
+ DW_VR_MII_TX_CONFIG_MASK);
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL,
+ rc);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_pcs_read(priv, port, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
+ if (rc < 0)
+ return rc;
+
+ if (priv->xpcs_cfg[port].inband_an)
+ rc |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+ else
+ rc &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+
+ rc = sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1,
+ rc);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_pcs_read(priv, port, MDIO_MMD_VEND2, MDIO_CTRL1);
+ if (rc < 0)
+ return rc;
+
+ if (priv->xpcs_cfg[port].inband_an)
+ rc |= MDIO_AN_CTRL1_ENABLE;
+ else
+ rc &= ~MDIO_AN_CTRL1_ENABLE;
+
+ return sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, MDIO_CTRL1, rc);
+}
+
+static int sja1105_xpcs_link_up_sgmii(struct sja1105_private *priv, int port)
+{
+ int val = BMCR_FULLDPLX;
+
+ if (priv->xpcs_cfg[port].inband_an)
+ return 0;
+
+ switch (priv->xpcs_cfg[port].speed) {
+ case SPEED_1000:
+ val = BMCR_SPEED1000;
+ break;
+ case SPEED_100:
+ val = BMCR_SPEED100;
+ break;
+ case SPEED_10:
+ val = BMCR_SPEED10;
+ break;
+ default:
+ dev_err(priv->dev, "Invalid PCS speed %d\n",
+ priv->xpcs_cfg[port].speed);
+ return -EINVAL;
+ }
+
+ return sja1105_pcs_write(priv, port, MDIO_MMD_VEND2, MDIO_CTRL1, val);
+}
+
+static int sja1105_sgmii_setup(struct sja1105_private *priv, int port)
+{
+ int rc;
+
+ rc = sja1105_xpcs_config_aneg_c37_sgmii(priv, port);
+ if (rc)
+ return rc;
+
+ rc = sja1105_xpcs_link_up_sgmii(priv, port);
+ if (rc)
+ return rc;
+
+ return priv->info->pma_config(priv, port);
+}
+
+static int sja1105_clocking_setup_port(struct sja1105_private *priv, int port)
+{
+ struct sja1105_xmii_params_entry *mii;
+ sja1105_phy_interface_t phy_mode;
+ sja1105_mii_role_t role;
+ int rc;
+
+ mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
+
+ /* RGMII etc */
+ phy_mode = mii->xmii_mode[port];
+ /* MAC or PHY, for applicable types (not RGMII) */
+ role = mii->phy_mac[port];
+
+ switch (phy_mode) {
+ case XMII_MODE_MII:
+ rc = sja1105_mii_clocking_setup(priv, port, role);
+ break;
+ case XMII_MODE_RMII:
+ rc = sja1105_rmii_clocking_setup(priv, port, role);
+ break;
+ case XMII_MODE_RGMII:
+ rc = sja1105_rgmii_clocking_setup(priv, port, role);
+ break;
+ case XMII_MODE_SGMII:
+ rc = sja1105_sgmii_setup(priv, port);
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (rc)
+ return rc;
+
+ /* Internally pull down the RX_DV/CRS_DV/RX_CTL and RX_ER inputs */
+ return sja1105_cfg_pad_rx_config(priv, port);
+}
+
+static int sja1105_clocking_setup(struct sja1105_private *priv)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(priv->dev);
+ int port, rc;
+
+ for (port = 0; port < pdata->num_ports; port++) {
+ rc = sja1105_clocking_setup_port(priv, port);
+ if (rc < 0)
+ return rc;
+ }
+ return 0;
+}
+
+static int sja1105_pcs_mdio_read(struct mii_dev *bus, int phy, int mmd, int reg)
+{
+ u8 packed_buf[SJA1105_SIZE_MDIO_CMD] = {0};
+ struct sja1105_private *priv = bus->priv;
+ const int size = SJA1105_SIZE_MDIO_CMD;
+ u64 addr, tmp;
+ int rc;
+
+ if (mmd == MDIO_DEVAD_NONE)
+ return -ENODEV;
+
+ if (!priv->info->supports_sgmii[phy])
+ return -ENODEV;
+
+ addr = (mmd << 16) | (reg & GENMASK(15, 0));
+
+ if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
+ return 0xffff;
+
+ rc = sja1105_xfer_buf(priv, SPI_READ, addr, packed_buf, size);
+ if (rc < 0)
+ return rc;
+
+ sja1105_packing(packed_buf, &tmp, 31, 0, size, UNPACK);
+
+ return tmp & 0xffff;
+}
+
+static int sja1105_pcs_mdio_write(struct mii_dev *bus, int phy, int mmd,
+ int reg, u16 val)
+{
+ u8 packed_buf[SJA1105_SIZE_MDIO_CMD] = {0};
+ struct sja1105_private *priv = bus->priv;
+ const int size = SJA1105_SIZE_MDIO_CMD;
+ u64 addr, tmp;
+
+ if (mmd == MDIO_DEVAD_NONE)
+ return -ENODEV;
+
+ if (!priv->info->supports_sgmii[phy])
+ return -ENODEV;
+
+ addr = (mmd << 16) | (reg & GENMASK(15, 0));
+ tmp = val;
+
+ if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
+ return -ENODEV;
+
+ sja1105_packing(packed_buf, &tmp, 31, 0, size, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, addr, packed_buf, size);
+}
+
+static int sja1110_pcs_mdio_read(struct mii_dev *bus, int phy, int mmd, int reg)
+{
+ struct sja1105_private *priv = bus->priv;
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_MDIO_CMD] = {0};
+ const int size = SJA1105_SIZE_MDIO_CMD;
+ int offset, bank;
+ u64 addr, tmp;
+ int rc;
+
+ if (mmd == MDIO_DEVAD_NONE)
+ return -ENODEV;
+
+ if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)
+ return -ENODEV;
+
+ addr = (mmd << 16) | (reg & GENMASK(15, 0));
+
+ bank = addr >> 8;
+ offset = addr & GENMASK(7, 0);
+
+ /* This addressing scheme reserves register 0xff for the bank address
+ * register, so that can never be addressed.
+ */
+ if (offset == 0xff)
+ return -ENODEV;
+
+ tmp = bank;
+
+ sja1105_packing(packed_buf, &tmp, 31, 0, size, PACK);
+
+ rc = sja1105_xfer_buf(priv, SPI_WRITE,
+ regs->pcs_base[phy] + SJA1110_PCS_BANK_REG,
+ packed_buf, size);
+ if (rc < 0)
+ return rc;
+
+ rc = sja1105_xfer_buf(priv, SPI_READ, regs->pcs_base[phy] + offset,
+ packed_buf, size);
+ if (rc < 0)
+ return rc;
+
+ sja1105_packing(packed_buf, &tmp, 31, 0, size, UNPACK);
+
+ return tmp & 0xffff;
+}
+
+static int sja1110_pcs_mdio_write(struct mii_dev *bus, int phy, int mmd,
+ int reg, u16 val)
+{
+ struct sja1105_private *priv = bus->priv;
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_MDIO_CMD] = {0};
+ const int size = SJA1105_SIZE_MDIO_CMD;
+ int offset, bank;
+ u64 addr, tmp;
+ int rc;
+
+ if (mmd == MDIO_DEVAD_NONE)
+ return -ENODEV;
+
+ if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)
+ return -ENODEV;
+
+ addr = (mmd << 16) | (reg & GENMASK(15, 0));
+
+ bank = addr >> 8;
+ offset = addr & GENMASK(7, 0);
+
+ /* This addressing scheme reserves register 0xff for the bank address
+ * register, so that can never be addressed.
+ */
+ if (offset == 0xff)
+ return -ENODEV;
+
+ tmp = bank;
+ sja1105_packing(packed_buf, &tmp, 31, 0, size, PACK);
+
+ rc = sja1105_xfer_buf(priv, SPI_WRITE,
+ regs->pcs_base[phy] + SJA1110_PCS_BANK_REG,
+ packed_buf, size);
+ if (rc < 0)
+ return rc;
+
+ tmp = val;
+ sja1105_packing(packed_buf, &tmp, 31, 0, size, PACK);
+
+ return sja1105_xfer_buf(priv, SPI_WRITE, regs->pcs_base[phy] + offset,
+ packed_buf, size);
+}
+
+static int sja1105_mdiobus_register(struct sja1105_private *priv)
+{
+ struct udevice *dev = priv->dev;
+ struct mii_dev *bus;
+ int rc;
+
+ if (!priv->info->pcs_mdio_read || !priv->info->pcs_mdio_write)
+ return 0;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return -ENOMEM;
+
+ snprintf(bus->name, MDIO_NAME_LEN, "%s-pcs", dev->name);
+ bus->read = priv->info->pcs_mdio_read;
+ bus->write = priv->info->pcs_mdio_write;
+ bus->priv = priv;
+
+ rc = mdio_register(bus);
+ if (rc) {
+ mdio_free(bus);
+ return rc;
+ }
+
+ priv->mdio_pcs = bus;
+
+ return 0;
+}
+
+static void sja1105_mdiobus_unregister(struct sja1105_private *priv)
+{
+ if (!priv->mdio_pcs)
+ return;
+
+ mdio_unregister(priv->mdio_pcs);
+ mdio_free(priv->mdio_pcs);
+}
+
+static const struct sja1105_regs sja1105et_regs = {
+ .device_id = 0x0,
+ .prod_id = 0x100BC3,
+ .status = 0x1,
+ .port_control = 0x11,
+ .config = 0x020000,
+ .rgu = 0x100440,
+ /* UM10944.pdf, Table 86, ACU Register overview */
+ .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
+ .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
+ .rmii_pll1 = 0x10000A,
+ .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
+ /* UM10944.pdf, Table 78, CGU Register overview */
+ .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F},
+ .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030},
+ .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
+ .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035},
+ .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032},
+ .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031},
+ .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
+};
+
+static const struct sja1105_regs sja1105pqrs_regs = {
+ .device_id = 0x0,
+ .prod_id = 0x100BC3,
+ .status = 0x1,
+ .port_control = 0x12,
+ .config = 0x020000,
+ .rgu = 0x100440,
+ /* UM10944.pdf, Table 86, ACU Register overview */
+ .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
+ .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
+ .pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814},
+ .rmii_pll1 = 0x10000A,
+ .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
+ /* UM11040.pdf, Table 114 */
+ .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B},
+ .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C},
+ .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
+ .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030},
+ .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E},
+ .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D},
+ .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
+};
+
+static const struct sja1105_regs sja1110_regs = {
+ .device_id = SJA1110_SPI_ADDR(0x0),
+ .prod_id = SJA1110_ACU_ADDR(0xf00),
+ .status = SJA1110_SPI_ADDR(0x4),
+ .port_control = SJA1110_SPI_ADDR(0x50), /* actually INHIB_TX */
+ .config = 0x020000,
+ .rgu = SJA1110_RGU_ADDR(0x100), /* Reset Control Register 0 */
+ /* Ports 2 and 3 are capable of xMII, but there isn't anything to
+ * configure in the CGU/ACU for them.
+ */
+ .pad_mii_tx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR},
+ .pad_mii_rx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR},
+ .pad_mii_id = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1110_ACU_ADDR(0x18), SJA1110_ACU_ADDR(0x28),
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR},
+ .rmii_pll1 = SJA1105_RSV_ADDR,
+ .cgu_idiv = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .mii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .mii_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .mii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .mii_ext_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .rgmii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .rmii_ref_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+ .rmii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR},
+ .pcs_base = {SJA1105_RSV_ADDR, 0x1c1400, 0x1c1800, 0x1c1c00, 0x1c2000,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
+ SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
+};
+
+enum sja1105_switch_id {
+ SJA1105E = 0,
+ SJA1105T,
+ SJA1105P,
+ SJA1105Q,
+ SJA1105R,
+ SJA1105S,
+ SJA1110A,
+ SJA1110B,
+ SJA1110C,
+ SJA1110D,
+ SJA1105_MAX_SWITCH_ID,
+};
+
+static const struct sja1105_info sja1105_info[] = {
+ [SJA1105E] = {
+ .device_id = SJA1105E_DEVICE_ID,
+ .part_no = SJA1105ET_PART_NO,
+ .static_ops = sja1105et_table_ops,
+ .reset_cmd = sja1105et_reset_cmd,
+ .regs = &sja1105et_regs,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 3,
+ [SJA1105_SPEED_100MBPS] = 2,
+ [SJA1105_SPEED_1000MBPS] = 1,
+ },
+ .supports_mii = {true, true, true, true, true},
+ .supports_rmii = {true, true, true, true, true},
+ .supports_rgmii = {true, true, true, true, true},
+ .name = "SJA1105E",
+ },
+ [SJA1105T] = {
+ .device_id = SJA1105T_DEVICE_ID,
+ .part_no = SJA1105ET_PART_NO,
+ .static_ops = sja1105et_table_ops,
+ .reset_cmd = sja1105et_reset_cmd,
+ .regs = &sja1105et_regs,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 3,
+ [SJA1105_SPEED_100MBPS] = 2,
+ [SJA1105_SPEED_1000MBPS] = 1,
+ },
+ .supports_mii = {true, true, true, true, true},
+ .supports_rmii = {true, true, true, true, true},
+ .supports_rgmii = {true, true, true, true, true},
+ .name = "SJA1105T",
+ },
+ [SJA1105P] = {
+ .device_id = SJA1105PR_DEVICE_ID,
+ .part_no = SJA1105P_PART_NO,
+ .static_ops = sja1105pqrs_table_ops,
+ .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
+ .reset_cmd = sja1105pqrs_reset_cmd,
+ .regs = &sja1105pqrs_regs,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 3,
+ [SJA1105_SPEED_100MBPS] = 2,
+ [SJA1105_SPEED_1000MBPS] = 1,
+ },
+ .supports_mii = {true, true, true, true, true},
+ .supports_rmii = {true, true, true, true, true},
+ .supports_rgmii = {true, true, true, true, true},
+ .name = "SJA1105P",
+ },
+ [SJA1105Q] = {
+ .device_id = SJA1105QS_DEVICE_ID,
+ .part_no = SJA1105Q_PART_NO,
+ .static_ops = sja1105pqrs_table_ops,
+ .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
+ .reset_cmd = sja1105pqrs_reset_cmd,
+ .regs = &sja1105pqrs_regs,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 3,
+ [SJA1105_SPEED_100MBPS] = 2,
+ [SJA1105_SPEED_1000MBPS] = 1,
+ },
+ .supports_mii = {true, true, true, true, true},
+ .supports_rmii = {true, true, true, true, true},
+ .supports_rgmii = {true, true, true, true, true},
+ .name = "SJA1105Q",
+ },
+ [SJA1105R] = {
+ .device_id = SJA1105PR_DEVICE_ID,
+ .part_no = SJA1105R_PART_NO,
+ .static_ops = sja1105pqrs_table_ops,
+ .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
+ .reset_cmd = sja1105pqrs_reset_cmd,
+ .regs = &sja1105pqrs_regs,
+ .pcs_mdio_read = sja1105_pcs_mdio_read,
+ .pcs_mdio_write = sja1105_pcs_mdio_write,
+ .pma_config = sja1105_pma_config,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 3,
+ [SJA1105_SPEED_100MBPS] = 2,
+ [SJA1105_SPEED_1000MBPS] = 1,
+ },
+ .supports_mii = {true, true, true, true, true},
+ .supports_rmii = {true, true, true, true, true},
+ .supports_rgmii = {true, true, true, true, true},
+ .supports_sgmii = {false, false, false, false, true},
+ .name = "SJA1105R",
+ },
+ [SJA1105S] = {
+ .device_id = SJA1105QS_DEVICE_ID,
+ .part_no = SJA1105S_PART_NO,
+ .static_ops = sja1105pqrs_table_ops,
+ .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
+ .reset_cmd = sja1105pqrs_reset_cmd,
+ .regs = &sja1105pqrs_regs,
+ .pcs_mdio_read = sja1105_pcs_mdio_read,
+ .pcs_mdio_write = sja1105_pcs_mdio_write,
+ .pma_config = sja1105_pma_config,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 3,
+ [SJA1105_SPEED_100MBPS] = 2,
+ [SJA1105_SPEED_1000MBPS] = 1,
+ },
+ .supports_mii = {true, true, true, true, true},
+ .supports_rmii = {true, true, true, true, true},
+ .supports_rgmii = {true, true, true, true, true},
+ .supports_sgmii = {false, false, false, false, true},
+ .name = "SJA1105S",
+ },
+ [SJA1110A] = {
+ .device_id = SJA1110_DEVICE_ID,
+ .part_no = SJA1110A_PART_NO,
+ .static_ops = sja1110_table_ops,
+ .setup_rgmii_delay = sja1110_setup_rgmii_delay,
+ .reset_cmd = sja1110_reset_cmd,
+ .regs = &sja1110_regs,
+ .pcs_mdio_read = sja1110_pcs_mdio_read,
+ .pcs_mdio_write = sja1110_pcs_mdio_write,
+ .pma_config = sja1110_pma_config,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 4,
+ [SJA1105_SPEED_100MBPS] = 3,
+ [SJA1105_SPEED_1000MBPS] = 2,
+ },
+ .supports_mii = {true, true, true, true, false,
+ true, true, true, true, true, true},
+ .supports_rmii = {false, false, true, true, false,
+ false, false, false, false, false, false},
+ .supports_rgmii = {false, false, true, true, false,
+ false, false, false, false, false, false},
+ .supports_sgmii = {false, true, true, true, true,
+ false, false, false, false, false, false},
+ .name = "SJA1110A",
+ },
+ [SJA1110B] = {
+ .device_id = SJA1110_DEVICE_ID,
+ .part_no = SJA1110B_PART_NO,
+ .static_ops = sja1110_table_ops,
+ .setup_rgmii_delay = sja1110_setup_rgmii_delay,
+ .reset_cmd = sja1110_reset_cmd,
+ .regs = &sja1110_regs,
+ .pcs_mdio_read = sja1110_pcs_mdio_read,
+ .pcs_mdio_write = sja1110_pcs_mdio_write,
+ .pma_config = sja1110_pma_config,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 4,
+ [SJA1105_SPEED_100MBPS] = 3,
+ [SJA1105_SPEED_1000MBPS] = 2,
+ },
+ .supports_mii = {true, true, true, true, false,
+ true, true, true, true, true, false},
+ .supports_rmii = {false, false, true, true, false,
+ false, false, false, false, false, false},
+ .supports_rgmii = {false, false, true, true, false,
+ false, false, false, false, false, false},
+ .supports_sgmii = {false, false, false, true, true,
+ false, false, false, false, false, false},
+ .name = "SJA1110B",
+ },
+ [SJA1110C] = {
+ .device_id = SJA1110_DEVICE_ID,
+ .part_no = SJA1110C_PART_NO,
+ .static_ops = sja1110_table_ops,
+ .setup_rgmii_delay = sja1110_setup_rgmii_delay,
+ .reset_cmd = sja1110_reset_cmd,
+ .regs = &sja1110_regs,
+ .pcs_mdio_read = sja1110_pcs_mdio_read,
+ .pcs_mdio_write = sja1110_pcs_mdio_write,
+ .pma_config = sja1110_pma_config,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 4,
+ [SJA1105_SPEED_100MBPS] = 3,
+ [SJA1105_SPEED_1000MBPS] = 2,
+ },
+ .supports_mii = {true, true, true, true, false,
+ true, true, true, false, false, false},
+ .supports_rmii = {false, false, true, true, false,
+ false, false, false, false, false, false},
+ .supports_rgmii = {false, false, true, true, false,
+ false, false, false, false, false, false},
+ .supports_sgmii = {false, false, false, false, true,
+ false, false, false, false, false, false},
+ .name = "SJA1110C",
+ },
+ [SJA1110D] = {
+ .device_id = SJA1110_DEVICE_ID,
+ .part_no = SJA1110D_PART_NO,
+ .static_ops = sja1110_table_ops,
+ .setup_rgmii_delay = sja1110_setup_rgmii_delay,
+ .reset_cmd = sja1110_reset_cmd,
+ .regs = &sja1110_regs,
+ .pcs_mdio_read = sja1110_pcs_mdio_read,
+ .pcs_mdio_write = sja1110_pcs_mdio_write,
+ .pma_config = sja1110_pma_config,
+ .port_speed = {
+ [SJA1105_SPEED_AUTO] = 0,
+ [SJA1105_SPEED_10MBPS] = 4,
+ [SJA1105_SPEED_100MBPS] = 3,
+ [SJA1105_SPEED_1000MBPS] = 2,
+ },
+ .supports_mii = {true, false, true, false, false,
+ true, true, true, false, false, false},
+ .supports_rmii = {false, false, true, false, false,
+ false, false, false, false, false, false},
+ .supports_rgmii = {false, false, true, false, false,
+ false, false, false, false, false, false},
+ .supports_sgmii = {false, true, true, true, true,
+ false, false, false, false, false, false},
+ .name = "SJA1110D",
+ },
+};
+
+struct sja1105_status {
+ u64 configs;
+ u64 crcchkl;
+ u64 ids;
+ u64 crcchkg;
+};
+
+static void sja1105_status_unpack(void *buf, struct sja1105_status *status)
+{
+ sja1105_packing(buf, &status->configs, 31, 31, 4, UNPACK);
+ sja1105_packing(buf, &status->crcchkl, 30, 30, 4, UNPACK);
+ sja1105_packing(buf, &status->ids, 29, 29, 4, UNPACK);
+ sja1105_packing(buf, &status->crcchkg, 28, 28, 4, UNPACK);
+}
+
+static int sja1105_status_get(struct sja1105_private *priv,
+ struct sja1105_status *status)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[4];
+ int rc;
+
+ rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4);
+ if (rc < 0)
+ return rc;
+
+ sja1105_status_unpack(packed_buf, status);
+
+ return 0;
+}
+
+/* Not const because unpacking priv->static_config into buffers and preparing
+ * for upload requires the recalculation of table CRCs and updating the
+ * structures with these.
+ */
+static int
+static_config_buf_prepare_for_upload(struct sja1105_private *priv,
+ void *config_buf, int buf_len)
+{
+ struct sja1105_static_config *config = &priv->static_config;
+ struct sja1105_table_header final_header;
+ char *final_header_ptr;
+ int crc_len;
+
+ /* Write Device ID and config tables to config_buf */
+ sja1105_static_config_pack(config_buf, config);
+ /* Recalculate CRC of the last header (right now 0xDEADBEEF).
+ * Don't include the CRC field itself.
+ */
+ crc_len = buf_len - 4;
+ /* Read the whole table header */
+ final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER;
+ sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK);
+ /* Modify */
+ final_header.crc = sja1105_crc32(config_buf, crc_len);
+ /* Rewrite */
+ sja1105_table_header_packing(final_header_ptr, &final_header, PACK);
+
+ return 0;
+}
+
+static int sja1105_static_config_upload(struct sja1105_private *priv)
+{
+ struct sja1105_static_config *config = &priv->static_config;
+ const struct sja1105_regs *regs = priv->info->regs;
+ struct sja1105_status status;
+ u8 *config_buf;
+ int buf_len;
+ int rc;
+
+ buf_len = sja1105_static_config_get_length(config);
+ config_buf = calloc(buf_len, sizeof(char));
+ if (!config_buf)
+ return -ENOMEM;
+
+ rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len);
+ if (rc < 0) {
+ printf("Invalid config, cannot upload\n");
+ rc = -EINVAL;
+ goto out;
+ }
+ /* Put the SJA1105 in programming mode */
+ rc = priv->info->reset_cmd(priv);
+ if (rc < 0) {
+ printf("Failed to reset switch\n");
+ goto out;
+ }
+ /* Wait for the switch to come out of reset */
+ udelay(1000);
+ /* Upload the static config to the device */
+ rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config,
+ config_buf, buf_len);
+ if (rc < 0) {
+ printf("Failed to upload config\n");
+ goto out;
+ }
+ /* Check that SJA1105 responded well to the config upload */
+ rc = sja1105_status_get(priv, &status);
+ if (rc < 0)
+ goto out;
+
+ if (status.ids == 1) {
+ printf("Mismatch between hardware and static config device id. "
+ "Wrote 0x%llx, wants 0x%llx\n",
+ config->device_id, priv->info->device_id);
+ rc = -EIO;
+ goto out;
+ }
+ if (status.crcchkl == 1 || status.crcchkg == 1) {
+ printf("Switch reported invalid CRC on static config\n");
+ rc = -EIO;
+ goto out;
+ }
+ if (status.configs == 0) {
+ printf("Switch reported that config is invalid\n");
+ rc = -EIO;
+ goto out;
+ }
+
+out:
+ free(config_buf);
+ return rc;
+}
+
+static int sja1105_static_config_reload(struct sja1105_private *priv)
+{
+ int rc;
+
+ rc = sja1105_static_config_upload(priv);
+ if (rc < 0) {
+ printf("Failed to load static config: %d\n", rc);
+ return rc;
+ }
+
+ /* Configure the CGU (PHY link modes and speeds) */
+ rc = sja1105_clocking_setup(priv);
+ if (rc < 0) {
+ printf("Failed to configure MII clocking: %d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int sja1105_port_probe(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ struct sja1105_private *priv = dev_get_priv(dev);
+ ofnode node = dsa_port_get_ofnode(dev, port);
+ phy_interface_t phy_mode = phy->interface;
+
+ priv->xpcs_cfg[port].inband_an = ofnode_eth_uses_inband_aneg(node);
+
+ if (phy_mode == PHY_INTERFACE_MODE_MII ||
+ phy_mode == PHY_INTERFACE_MODE_RMII) {
+ phy->supported &= PHY_BASIC_FEATURES;
+ phy->advertising &= PHY_BASIC_FEATURES;
+ } else {
+ phy->supported &= PHY_GBIT_FEATURES;
+ phy->advertising &= PHY_GBIT_FEATURES;
+ }
+
+ return phy_config(phy);
+}
+
+static int sja1105_port_enable(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ struct sja1105_private *priv = dev_get_priv(dev);
+ phy_interface_t phy_mode = phy->interface;
+ struct sja1105_xmii_params_entry *mii;
+ struct sja1105_mac_config_entry *mac;
+ int rc;
+
+ rc = phy_startup(phy);
+ if (rc)
+ return rc;
+
+ mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
+ mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ if (!priv->info->supports_mii[port])
+ goto unsupported;
+
+ mii->xmii_mode[port] = XMII_MODE_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (!priv->info->supports_rmii[port])
+ goto unsupported;
+
+ mii->xmii_mode[port] = XMII_MODE_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ if (!priv->info->supports_rgmii[port])
+ goto unsupported;
+
+ mii->xmii_mode[port] = XMII_MODE_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ if (!priv->info->supports_sgmii[port])
+ goto unsupported;
+
+ mii->xmii_mode[port] = XMII_MODE_SGMII;
+ mii->special[port] = true;
+ break;
+unsupported:
+ default:
+ dev_err(dev, "Unsupported PHY mode %d on port %d!\n",
+ phy_mode, port);
+ return -EINVAL;
+ }
+
+ /* RevMII, RevRMII not supported */
+ mii->phy_mac[port] = XMII_MAC;
+
+ /* Let the PHY handle the RGMII delays, if present. */
+ if (phy->phy_id == PHY_FIXED_ID) {
+ if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
+ phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
+ priv->rgmii_rx_delay[port] = true;
+
+ if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
+ phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
+ priv->rgmii_tx_delay[port] = true;
+
+ if ((priv->rgmii_rx_delay[port] ||
+ priv->rgmii_tx_delay[port]) &&
+ !priv->info->setup_rgmii_delay) {
+ printf("Chip does not support internal RGMII delays\n");
+ return -EINVAL;
+ }
+ }
+
+ if (mii->xmii_mode[port] == XMII_MODE_SGMII) {
+ mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
+ priv->xpcs_cfg[port].speed = phy->speed;
+ } else if (phy->speed == SPEED_1000) {
+ mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
+ } else if (phy->speed == SPEED_100) {
+ mac[port].speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
+ } else if (phy->speed == SPEED_10) {
+ mac[port].speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
+ } else {
+ printf("Invalid PHY speed %d on port %d\n", phy->speed, port);
+ return -EINVAL;
+ }
+
+ return sja1105_static_config_reload(priv);
+}
+
+static void sja1105_port_disable(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ phy_shutdown(phy);
+}
+
+static int sja1105_xmit(struct udevice *dev, int port, void *packet, int length)
+{
+ struct sja1105_private *priv = dev_get_priv(dev);
+ u8 *from = (u8 *)packet + VLAN_HLEN;
+ struct vlan_ethhdr *hdr = packet;
+ u8 *dest = (u8 *)packet;
+
+ memmove(dest, from, 2 * ETH_ALEN);
+ hdr->h_vlan_proto = htons(ETH_P_SJA1105);
+ hdr->h_vlan_TCI = htons(priv->pvid[port]);
+
+ return 0;
+}
+
+static int sja1105_rcv(struct udevice *dev, int *port, void *packet, int length)
+{
+ struct vlan_ethhdr *hdr = packet;
+ u8 *dest = packet + VLAN_HLEN;
+ u8 *from = packet;
+
+ if (ntohs(hdr->h_vlan_proto) != ETH_P_SJA1105)
+ return -EINVAL;
+
+ *port = ntohs(hdr->h_vlan_TCI) & DSA_8021Q_PORT_MASK;
+ memmove(dest, from, 2 * ETH_ALEN);
+
+ return 0;
+}
+
+static const struct dsa_ops sja1105_dsa_ops = {
+ .port_probe = sja1105_port_probe,
+ .port_enable = sja1105_port_enable,
+ .port_disable = sja1105_port_disable,
+ .xmit = sja1105_xmit,
+ .rcv = sja1105_rcv,
+};
+
+static int sja1105_init(struct sja1105_private *priv)
+{
+ int rc;
+
+ rc = sja1105_static_config_init(priv);
+ if (rc) {
+ printf("Failed to initialize static config: %d\n", rc);
+ return rc;
+ }
+
+ rc = sja1105_mdiobus_register(priv);
+ if (rc) {
+ printf("Failed to register MDIO bus: %d\n", rc);
+ goto err_mdiobus_register;
+ }
+
+ return 0;
+
+err_mdiobus_register:
+ sja1105_static_config_free(&priv->static_config);
+
+ return rc;
+}
+
+static int sja1105_check_device_id(struct sja1105_private *priv)
+{
+ const struct sja1105_regs *regs = priv->info->regs;
+ u8 packed_buf[SJA1105_SIZE_DEVICE_ID] = {0};
+ enum sja1105_switch_id id;
+ u64 device_id;
+ u64 part_no;
+ int rc;
+
+ rc = sja1105_xfer_buf(priv, SPI_READ, regs->device_id, packed_buf,
+ SJA1105_SIZE_DEVICE_ID);
+ if (rc < 0)
+ return rc;
+
+ sja1105_packing(packed_buf, &device_id, 31, 0, SJA1105_SIZE_DEVICE_ID,
+ UNPACK);
+
+ if (device_id != priv->info->device_id) {
+ printf("Expected device ID 0x%llx but read 0x%llx\n",
+ priv->info->device_id, device_id);
+ return -ENODEV;
+ }
+
+ rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, packed_buf,
+ SJA1105_SIZE_DEVICE_ID);
+ if (rc < 0)
+ return rc;
+
+ sja1105_packing(packed_buf, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID,
+ UNPACK);
+
+ for (id = 0; id < SJA1105_MAX_SWITCH_ID; id++) {
+ const struct sja1105_info *info = &sja1105_info[id];
+
+ /* Is what's been probed in our match table at all? */
+ if (info->device_id != device_id || info->part_no != part_no)
+ continue;
+
+ /* But is it what's in the device tree? */
+ if (priv->info->device_id != device_id ||
+ priv->info->part_no != part_no) {
+ printf("Device tree specifies chip %s but found %s, please fix it!\n",
+ priv->info->name, info->name);
+ /* It isn't. No problem, pick that up. */
+ priv->info = info;
+ }
+
+ return 0;
+ }
+
+ printf("Unexpected {device ID, part number}: 0x%llx 0x%llx\n",
+ device_id, part_no);
+
+ return -ENODEV;
+}
+
+static int sja1105_probe(struct udevice *dev)
+{
+ enum sja1105_switch_id id = dev_get_driver_data(dev);
+ struct sja1105_private *priv = dev_get_priv(dev);
+ int rc;
+
+ if (ofnode_valid(dev_ofnode(dev)) &&
+ !ofnode_is_available(dev_ofnode(dev))) {
+ dev_dbg(dev, "switch disabled\n");
+ return -ENODEV;
+ }
+
+ priv->info = &sja1105_info[id];
+ priv->dev = dev;
+
+ rc = sja1105_check_device_id(priv);
+ if (rc < 0) {
+ dev_err(dev, "Device ID check failed: %d\n", rc);
+ return rc;
+ }
+
+ dsa_set_tagging(dev, VLAN_HLEN, 0);
+
+ return sja1105_init(priv);
+}
+
+static int sja1105_remove(struct udevice *dev)
+{
+ struct sja1105_private *priv = dev_get_priv(dev);
+
+ sja1105_mdiobus_unregister(priv);
+ sja1105_static_config_free(&priv->static_config);
+
+ return 0;
+}
+
+static const struct udevice_id sja1105_ids[] = {
+ { .compatible = "nxp,sja1105e", .data = SJA1105E },
+ { .compatible = "nxp,sja1105t", .data = SJA1105T },
+ { .compatible = "nxp,sja1105p", .data = SJA1105P },
+ { .compatible = "nxp,sja1105q", .data = SJA1105Q },
+ { .compatible = "nxp,sja1105r", .data = SJA1105R },
+ { .compatible = "nxp,sja1105s", .data = SJA1105S },
+ { .compatible = "nxp,sja1110a", .data = SJA1110A },
+ { .compatible = "nxp,sja1110b", .data = SJA1110B },
+ { .compatible = "nxp,sja1110c", .data = SJA1110C },
+ { .compatible = "nxp,sja1110d", .data = SJA1110D },
+ { }
+};
+
+U_BOOT_DRIVER(sja1105) = {
+ .name = "sja1105",
+ .id = UCLASS_DSA,
+ .of_match = sja1105_ids,
+ .probe = sja1105_probe,
+ .remove = sja1105_remove,
+ .ops = &sja1105_dsa_ops,
+ .priv_auto = sizeof(struct sja1105_private),
+};
return 0;
}
+static int __maybe_unused tsec_set_promisc(struct udevice *dev, bool enable)
+{
+ struct tsec_private *priv = dev_get_priv(dev);
+ struct tsec __iomem *regs = priv->regs;
+
+ if (enable)
+ setbits_be32(®s->rctrl, RCTRL_PROM);
+ else
+ clrbits_be32(®s->rctrl, RCTRL_PROM);
+
+ return 0;
+}
+
/*
* Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
out_be32(®s->hash.gaddr6, 0);
out_be32(®s->hash.gaddr7, 0);
- out_be32(®s->rctrl, 0x00000000);
-
/* Init RMON mib registers */
memset((void *)®s->rmon, 0, sizeof(regs->rmon));
* of the eTSEC port initialization sequence,
* the eTSEC Rx logic may not be properly initialized.
*/
-void redundant_init(struct tsec_private *priv)
+static void redundant_init(struct tsec_private *priv)
{
struct tsec __iomem *regs = priv->regs;
uint t, count = 0;
0x71, 0x72};
/* Enable promiscuous mode */
- setbits_be32(®s->rctrl, 0x8);
+ setbits_be32(®s->rctrl, RCTRL_PROM);
/* Enable loopback mode */
setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
/* Enable transmit and receive */
if (fail)
panic("eTSEC init fail!\n");
/* Disable promiscuous mode */
- clrbits_be32(®s->rctrl, 0x8);
+ clrbits_be32(®s->rctrl, RCTRL_PROM);
/* Disable loopback mode */
clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
}
.free_pkt = tsec_free_pkt,
.stop = tsec_halt,
.mcast = tsec_mcast_addr,
+ .set_promisc = tsec_set_promisc,
};
static struct tsec_data etsec2_data = {
#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_NO_BRDC BIT(5) /* No broadcast */
#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
ZYNQ_GEM_NWCFG_FDEN | \
+ ZYNQ_GEM_NWCFG_NO_BRDC | \
ZYNQ_GEM_NWCFG_FSREM | \
ZYNQ_GEM_NWCFG_MDCCLKDIV)
#define PCIE_CONFIG_WR_TYPE0 0xa
#define PCIE_CONFIG_WR_TYPE1 0xb
-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(b, d, f) (PCI_BDF(b, d, f) << 4)
-#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
-#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
-#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
-#define PCIE_CONF_REG(reg) ((reg) & 0xffc)
-#define PCIE_CONF_ADDR(bus, devfn, where) \
- (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
- PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
-
/* PCIe Retries & Timeout definitions */
#define PIO_MAX_RETRIES 1500
#define PIO_WAIT_TIMEOUT 1000
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
+ reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
+ reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
#include <asm/io.h>
+#define TYPE_PCI 0x1
+
/**
* struct generic_ecam_pcie - generic_ecam PCIe controller state
* @cfg_base: The base address of memory mapped configuration space
void *addr;
addr = pcie->cfg_base;
- addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
- addr += PCI_DEV(bdf) << 15;
- addr += PCI_FUNC(bdf) << 12;
- addr += offset;
+
+ if (dev_get_driver_data(bus) == TYPE_PCI) {
+ addr += ((PCI_BUS(bdf) - pcie->first_busno) << 16) |
+ (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | offset;
+ } else {
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - pcie->first_busno,
+ PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+ }
*paddress = addr;
return 0;
};
static const struct udevice_id pci_generic_ecam_ids[] = {
- { .compatible = "pci-host-ecam-generic" },
+ { .compatible = "pci-host-ecam-generic" /* PCI-E */ },
+ { .compatible = "pci-host-cam-generic", .data = TYPE_PCI },
{ }
};
void *addr;
addr = pcie->cfg_base;
- addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
- addr += PCI_DEV(bdf) << 15;
- addr += PCI_FUNC(bdf) << 12;
- addr += offset;
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - pcie->first_busno,
+ PCI_DEV(bdf), PCI_FUNC(bdf), offset);
*paddress = addr;
return 0;
unsigned short capreg;
unsigned char port_type;
- addr += PCI_BUS(parent) << 20;
- addr += PCI_DEV(parent) << 15;
- addr += PCI_FUNC(parent) << 12;
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(parent), PCI_DEV(parent), PCI_FUNC(parent), 0);
pos = 0x34;
while (1) {
bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
addr = pcie->cfg_base;
- addr += PCI_BUS(bdf) << 20;
- addr += PCI_DEV(bdf) << 15;
- addr += PCI_FUNC(bdf) << 12;
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), 0);
if (bus_no > 0 && dev_no > 0) {
if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
struct phy pcie_phy;
};
-static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
-{
- unsigned int bus = PCI_BUS(bdf);
- unsigned int dev = PCI_DEV(bdf);
- unsigned int func = PCI_FUNC(bdf);
-
- return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
-}
-
static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
struct rockchip_pcie *priv = dev_get_priv(udev);
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
- int where = rockchip_pcie_off_conf(bdf, offset);
+ int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset & ~0x3);
ulong value;
if (bus == priv->first_busno && dev == 0) {
struct rockchip_pcie *priv = dev_get_priv(udev);
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
- int where = rockchip_pcie_off_conf(bdf, offset);
+ int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset & ~0x3);
ulong old;
if (bus == priv->first_busno && dev == 0) {
return -ENODEV;
addr = pcie->cfg_base;
- addr += bus << 20;
- addr += dev << 15;
- addr += func << 12;
- addr += offset;
+ addr += PCIE_ECAM_OFFSET(bus, dev, func, offset);
*paddress = addr;
return 0;
/* Going through all the available subnodes or children*/
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- /* PHY subnode name must be a 'link' */
- if (!ofnode_name_eq(child, "link"))
+ /* PHY subnode name must be a 'phy' */
+ if (!ofnode_name_eq(child, "phy"))
continue;
cdns_phy->phys[node].lnk_rst =
devm_reset_bulk_get_by_node(dev, child);
if PINCTRL || SPL_PINCTRL
+config PINCTRL_APPLE
+ bool "Apple pinctrl driver"
+ depends on DM && PINCTRL_GENERIC && ARCH_APPLE
+ default y
+ help
+ Support pin multiplexing on Apple SoCs.
+
+ The driver is controlled by a device tree node which contains
+ both the GPIO definitions and pin control functions for each
+ available multiplex function.
+
config PINCTRL_AR933X
bool "QCA/Athores ar933x pin control driver"
depends on DM && SOC_AR933X
uses Generic Pinctrl framework and is compatible with the Linux
driver, i.e. it uses the same device tree configuration.
+config ASPEED_AST2600_PINCTRL
+ bool "Aspeed AST2600 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2600
+ default y
+ help
+ Support pin multiplexing control on Aspeed ast2600 SoC. The driver
+ uses Generic Pinctrl framework and is compatible with the Linux
+ driver, i.e. it uses the same device tree configuration.
+
config PINCTRL_K210
bool "Kendryte K210 Fully-Programmable Input/Output Array driver"
depends on DM && PINCTRL_GENERIC
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_PINCTRL_APPLE) += pinctrl-apple.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
obj-$(CONFIG_ASPEED_AST2500_PINCTRL) += pinctrl_ast2500.o
+obj-$(CONFIG_ASPEED_AST2600_PINCTRL) += pinctrl_ast2600.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/pinctrl.h>
+#include <asm/arch/scu_ast2600.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+/*
+ * This driver works with very simple configuration that has the same name
+ * for group and function. This way it is compatible with the Linux Kernel
+ * driver.
+ */
+struct aspeed_sig_desc {
+ u32 offset;
+ u32 reg_set;
+ int clr;
+};
+
+struct aspeed_group_config {
+ char *group_name;
+ int ndescs;
+ struct aspeed_sig_desc *descs;
+};
+
+struct ast2600_pinctrl_priv {
+ struct ast2600_scu *scu;
+};
+
+static int ast2600_pinctrl_probe(struct udevice *dev)
+{
+ struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
+ struct udevice *clk_dev;
+ int ret = 0;
+
+ /* find SCU base address from clock device */
+ uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_ast2600_scu), &clk_dev);
+
+ if (ret)
+ return ret;
+
+ priv->scu = dev_read_addr_ptr(clk_dev);
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+
+ return 0;
+}
+
+static struct aspeed_sig_desc i2c1_link[] = {
+ { 0x418, GENMASK(9, 8), 1 },
+ { 0x4B8, GENMASK(9, 8), 0 },
+};
+
+static struct aspeed_sig_desc i2c2_link[] = {
+ { 0x418, GENMASK(11, 10), 1 },
+ { 0x4B8, GENMASK(11, 10), 0 },
+};
+
+static struct aspeed_sig_desc i2c3_link[] = {
+ { 0x418, GENMASK(13, 12), 1 },
+ { 0x4B8, GENMASK(13, 12), 0 },
+};
+
+static struct aspeed_sig_desc i2c4_link[] = {
+ { 0x418, GENMASK(15, 14), 1 },
+ { 0x4B8, GENMASK(15, 14), 0 },
+};
+
+static struct aspeed_sig_desc i2c5_link[] = {
+ { 0x418, GENMASK(17, 16), 0 },
+};
+
+static struct aspeed_sig_desc i2c6_link[] = {
+ { 0x418, GENMASK(19, 18), 0 },
+};
+
+static struct aspeed_sig_desc i2c7_link[] = {
+ { 0x418, GENMASK(21, 20), 0 },
+};
+
+static struct aspeed_sig_desc i2c8_link[] = {
+ { 0x418, GENMASK(23, 22), 0 },
+};
+
+static struct aspeed_sig_desc i2c9_link[] = {
+ { 0x418, GENMASK(25, 24), 0 },
+};
+
+static struct aspeed_sig_desc i2c10_link[] = {
+ { 0x418, GENMASK(27, 26), 0 },
+};
+
+static struct aspeed_sig_desc i2c11_link[] = {
+ { 0x410, GENMASK(1, 0), 1 },
+ { 0x4B0, GENMASK(1, 0), 0 },
+};
+
+static struct aspeed_sig_desc i2c12_link[] = {
+ { 0x410, GENMASK(3, 2), 1 },
+ { 0x4B0, GENMASK(3, 2), 0 },
+};
+
+static struct aspeed_sig_desc i2c13_link[] = {
+ { 0x410, GENMASK(5, 4), 1 },
+ { 0x4B0, GENMASK(5, 4), 0 },
+};
+
+static struct aspeed_sig_desc i2c14_link[] = {
+ { 0x410, GENMASK(7, 6), 1 },
+ { 0x4B0, GENMASK(7, 6), 0 },
+};
+
+static struct aspeed_sig_desc i2c15_link[] = {
+ { 0x414, GENMASK(29, 28), 1 },
+ { 0x4B4, GENMASK(29, 28), 0 },
+};
+
+static struct aspeed_sig_desc i2c16_link[] = {
+ { 0x414, GENMASK(31, 30), 1 },
+ { 0x4B4, GENMASK(31, 30), 0 },
+};
+
+static struct aspeed_sig_desc mac1_link[] = {
+ { 0x410, BIT(4), 0 },
+ { 0x470, BIT(4), 1 },
+};
+
+static struct aspeed_sig_desc mac2_link[] = {
+ { 0x410, BIT(5), 0 },
+ { 0x470, BIT(5), 1 },
+};
+
+static struct aspeed_sig_desc mac3_link[] = {
+ { 0x410, BIT(6), 0 },
+ { 0x470, BIT(6), 1 },
+};
+
+static struct aspeed_sig_desc mac4_link[] = {
+ { 0x410, BIT(7), 0 },
+ { 0x470, BIT(7), 1 },
+};
+
+static struct aspeed_sig_desc rgmii1[] = {
+ { 0x500, BIT(6), 0 },
+ { 0x400, GENMASK(11, 0), 0 },
+};
+
+static struct aspeed_sig_desc rgmii2[] = {
+ { 0x500, BIT(7), 0 },
+ { 0x400, GENMASK(23, 12), 0 },
+};
+
+static struct aspeed_sig_desc rgmii3[] = {
+ { 0x510, BIT(0), 0 },
+ { 0x410, GENMASK(27, 16), 0 },
+};
+
+static struct aspeed_sig_desc rgmii4[] = {
+ { 0x510, BIT(1), 0 },
+ { 0x410, GENMASK(31, 28), 1 },
+ { 0x4b0, GENMASK(31, 28), 0 },
+ { 0x474, GENMASK(7, 0), 1 },
+ { 0x414, GENMASK(7, 0), 1 },
+ { 0x4b4, GENMASK(7, 0), 0 },
+};
+
+static struct aspeed_sig_desc rmii1[] = {
+ { 0x504, BIT(6), 0 },
+ { 0x400, GENMASK(3, 0), 0 },
+ { 0x400, GENMASK(11, 6), 0 },
+};
+
+static struct aspeed_sig_desc rmii2[] = {
+ { 0x504, BIT(7), 0 },
+ { 0x400, GENMASK(15, 12), 0 },
+ { 0x400, GENMASK(23, 18), 0 },
+};
+
+static struct aspeed_sig_desc rmii3[] = {
+ { 0x514, BIT(0), 0 },
+ { 0x410, GENMASK(27, 22), 0 },
+ { 0x410, GENMASK(19, 16), 0 },
+};
+
+static struct aspeed_sig_desc rmii4[] = {
+ { 0x514, BIT(1), 0 },
+ { 0x410, GENMASK(7, 2), 1 },
+ { 0x410, GENMASK(31, 28), 1 },
+ { 0x414, GENMASK(7, 2), 1 },
+ { 0x4B0, GENMASK(31, 28), 0 },
+ { 0x4B4, GENMASK(7, 2), 0 },
+};
+
+static struct aspeed_sig_desc rmii1_rclk_oe[] = {
+ { 0x340, BIT(29), 0 },
+};
+
+static struct aspeed_sig_desc rmii2_rclk_oe[] = {
+ { 0x340, BIT(30), 0 },
+};
+
+static struct aspeed_sig_desc rmii3_rclk_oe[] = {
+ { 0x350, BIT(29), 0 },
+};
+
+static struct aspeed_sig_desc rmii4_rclk_oe[] = {
+ { 0x350, BIT(30), 0 },
+};
+
+static struct aspeed_sig_desc mdio1_link[] = {
+ { 0x430, BIT(17) | BIT(16), 0 },
+};
+
+static struct aspeed_sig_desc mdio2_link[] = {
+ { 0x470, BIT(13) | BIT(12), 1 },
+ { 0x410, BIT(13) | BIT(12), 0 },
+};
+
+static struct aspeed_sig_desc mdio3_link[] = {
+ { 0x470, BIT(1) | BIT(0), 1 },
+ { 0x410, BIT(1) | BIT(0), 0 },
+};
+
+static struct aspeed_sig_desc mdio4_link[] = {
+ { 0x470, BIT(3) | BIT(2), 1 },
+ { 0x410, BIT(3) | BIT(2), 0 },
+};
+
+static struct aspeed_sig_desc sdio2_link[] = {
+ { 0x414, GENMASK(23, 16), 1 },
+ { 0x4B4, GENMASK(23, 16), 0 },
+ { 0x450, BIT(1), 0 },
+};
+
+static struct aspeed_sig_desc sdio1_link[] = {
+ { 0x414, GENMASK(15, 8), 0 },
+};
+
+/* when sdio1 8bits, sdio2 can't use */
+static struct aspeed_sig_desc sdio1_8bit_link[] = {
+ { 0x414, GENMASK(15, 8), 0 },
+ { 0x4b4, GENMASK(21, 18), 0 },
+ { 0x450, BIT(3), 0 },
+ { 0x450, BIT(1), 1 },
+};
+
+static struct aspeed_sig_desc emmc_link[] = {
+ { 0x400, GENMASK(31, 24), 0 },
+};
+
+static struct aspeed_sig_desc emmcg8_link[] = {
+ { 0x400, GENMASK(31, 24), 0 },
+ { 0x404, GENMASK(3, 0), 0 },
+/* set SCU504 to clear the strap bits in SCU500 */
+ { 0x504, BIT(3), 0 },
+ { 0x504, BIT(5), 0 },
+};
+
+static struct aspeed_sig_desc fmcquad_link[] = {
+ { 0x438, GENMASK(5, 4), 0 },
+};
+
+static struct aspeed_sig_desc spi1_link[] = {
+ { 0x438, GENMASK(13, 11), 0 },
+};
+
+static struct aspeed_sig_desc spi1abr_link[] = {
+ { 0x438, BIT(9), 0 },
+};
+
+static struct aspeed_sig_desc spi1cs1_link[] = {
+ { 0x438, BIT(8), 0 },
+};
+
+static struct aspeed_sig_desc spi1wp_link[] = {
+ { 0x438, BIT(10), 0 },
+};
+
+static struct aspeed_sig_desc spi1quad_link[] = {
+ { 0x438, GENMASK(15, 14), 0 },
+};
+
+static struct aspeed_sig_desc spi2_link[] = {
+ { 0x434, GENMASK(29, 27) | BIT(24), 0 },
+};
+
+static struct aspeed_sig_desc spi2cs1_link[] = {
+ { 0x434, BIT(25), 0 },
+};
+
+static struct aspeed_sig_desc spi2cs2_link[] = {
+ { 0x434, BIT(26), 0 },
+};
+
+static struct aspeed_sig_desc spi2quad_link[] = {
+ { 0x434, GENMASK(31, 30), 0 },
+};
+
+static struct aspeed_sig_desc fsi1[] = {
+ { 0xd48, GENMASK(21, 20), 0 },
+};
+
+static struct aspeed_sig_desc fsi2[] = {
+ { 0xd48, GENMASK(23, 22), 0 },
+};
+
+static struct aspeed_sig_desc usb2ad_link[] = {
+ { 0x440, BIT(24), 0 },
+ { 0x440, BIT(25), 1 },
+};
+
+static struct aspeed_sig_desc usb2ah_link[] = {
+ { 0x440, BIT(24), 1 },
+ { 0x440, BIT(25), 0 },
+};
+
+static struct aspeed_sig_desc usb2bh_link[] = {
+ { 0x440, BIT(28), 1 },
+ { 0x440, BIT(29), 0 },
+};
+
+static struct aspeed_sig_desc pcie0rc_link[] = {
+ { 0x40, BIT(21), 0 },
+};
+
+static struct aspeed_sig_desc pcie1rc_link[] = {
+ { 0x40, BIT(19), 0 }, /* SSPRST# output enable */
+ { 0x500, BIT(24), 0 }, /* dedicate rc reset */
+};
+
+static const struct aspeed_group_config ast2600_groups[] = {
+ { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
+ { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
+ { "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link },
+ { "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link },
+ { "RGMII1", ARRAY_SIZE(rgmii1), rgmii1 },
+ { "RGMII2", ARRAY_SIZE(rgmii2), rgmii2 },
+ { "RGMII3", ARRAY_SIZE(rgmii3), rgmii3 },
+ { "RGMII4", ARRAY_SIZE(rgmii4), rgmii4 },
+ { "RMII1", ARRAY_SIZE(rmii1), rmii1 },
+ { "RMII2", ARRAY_SIZE(rmii2), rmii2 },
+ { "RMII3", ARRAY_SIZE(rmii3), rmii3 },
+ { "RMII4", ARRAY_SIZE(rmii4), rmii4 },
+ { "RMII1RCLK", ARRAY_SIZE(rmii1_rclk_oe), rmii1_rclk_oe },
+ { "RMII2RCLK", ARRAY_SIZE(rmii2_rclk_oe), rmii2_rclk_oe },
+ { "RMII3RCLK", ARRAY_SIZE(rmii3_rclk_oe), rmii3_rclk_oe },
+ { "RMII4RCLK", ARRAY_SIZE(rmii4_rclk_oe), rmii4_rclk_oe },
+ { "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link },
+ { "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link },
+ { "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link },
+ { "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link },
+ { "SD1", ARRAY_SIZE(sdio1_link), sdio1_link },
+ { "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link },
+ { "SD2", ARRAY_SIZE(sdio2_link), sdio2_link },
+ { "EMMC", ARRAY_SIZE(emmc_link), emmc_link },
+ { "EMMCG8", ARRAY_SIZE(emmcg8_link), emmcg8_link },
+ { "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link },
+ { "SPI1", ARRAY_SIZE(spi1_link), spi1_link },
+ { "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link },
+ { "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link },
+ { "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link },
+ { "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link },
+ { "SPI2", ARRAY_SIZE(spi2_link), spi2_link },
+ { "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link },
+ { "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link },
+ { "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link },
+ { "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link },
+ { "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link },
+ { "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link },
+ { "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link },
+ { "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link },
+ { "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link },
+ { "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link },
+ { "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link },
+ { "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link },
+ { "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link },
+ { "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link },
+ { "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link },
+ { "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link },
+ { "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link },
+ { "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link },
+ { "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link },
+ { "FSI1", ARRAY_SIZE(fsi1), fsi1 },
+ { "FSI2", ARRAY_SIZE(fsi2), fsi2 },
+ { "USB2AD", ARRAY_SIZE(usb2ad_link), usb2ad_link },
+ { "USB2AH", ARRAY_SIZE(usb2ah_link), usb2ah_link },
+ { "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link },
+ { "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link },
+ { "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link },
+};
+
+static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
+{
+ debug("PINCTRL: get_(functions/groups)_count\n");
+
+ return ARRAY_SIZE(ast2600_groups);
+}
+
+static const char *ast2600_pinctrl_get_group_name(struct udevice *dev,
+ unsigned selector)
+{
+ debug("PINCTRL: get_(function/group)_name %u\n", selector);
+
+ return ast2600_groups[selector].group_name;
+}
+
+static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector, unsigned func_selector)
+{
+ struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct aspeed_group_config *config;
+ const struct aspeed_sig_desc *descs;
+ u32 ctrl_reg = (u32)priv->scu;
+ u32 i;
+
+ debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector);
+ if (selector >= ARRAY_SIZE(ast2600_groups))
+ return -EINVAL;
+
+ config = &ast2600_groups[selector];
+ for (i = 0; i < config->ndescs; i++) {
+ descs = &config->descs[i];
+ if (descs->clr)
+ clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set);
+ else
+ setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set);
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops ast2600_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .get_groups_count = ast2600_pinctrl_get_groups_count,
+ .get_group_name = ast2600_pinctrl_get_group_name,
+ .get_functions_count = ast2600_pinctrl_get_groups_count,
+ .get_function_name = ast2600_pinctrl_get_group_name,
+ .pinmux_group_set = ast2600_pinctrl_group_set,
+};
+
+static const struct udevice_id ast2600_pinctrl_ids[] = {
+ { .compatible = "aspeed,g6-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_aspeed) = {
+ .name = "aspeed_ast2600_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = ast2600_pinctrl_ids,
+ .priv_auto = sizeof(struct ast2600_pinctrl_priv),
+ .ops = &ast2600_pinctrl_ops,
+ .probe = ast2600_pinctrl_probe,
+};
.direction_output = meson_gpio_direction_output,
};
-const struct driver meson_gx_gpio_driver = {
+U_BOOT_DRIVER(meson_gx_gpio_driver) = {
.name = "meson-gx-gpio",
.id = UCLASS_GPIO,
.probe = meson_gpio_probe,
}
extern const struct pinctrl_ops meson_gx_pinctrl_ops;
-extern const struct driver meson_gx_gpio_driver;
+extern U_BOOT_DRIVER(meson_gx_gpio_driver);
#endif /* __PINCTRL_MESON_GX_H__ */
.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
.num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
- .gpio_driver = &meson_gx_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver),
};
struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
.num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
- .gpio_driver = &meson_gx_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver),
};
static const struct udevice_id meson_gxbb_pinctrl_match[] = {
.num_groups = ARRAY_SIZE(meson_gxl_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions),
.num_banks = ARRAY_SIZE(meson_gxl_periphs_banks),
- .gpio_driver = &meson_gx_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver),
};
struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
.num_groups = ARRAY_SIZE(meson_gxl_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
.num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
- .gpio_driver = &meson_gx_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver),
};
static const struct udevice_id meson_gxl_pinctrl_match[] = {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/pinctrl/apple.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitfield.h>
+
+struct apple_pinctrl_priv {
+ void *base;
+ int pin_count;
+};
+
+#define REG_GPIO(x) (4 * (x))
+#define REG_GPIO_DATA BIT(0)
+#define REG_GPIO_MODE GENMASK(3, 1)
+#define REG_GPIO_OUT 1
+#define REG_GPIO_PERIPH GENMASK(6, 5)
+#define REG_GPIO_INPUT_ENABLE BIT(9)
+
+static void apple_pinctrl_config_pin(struct apple_pinctrl_priv *priv,
+ unsigned pin, u32 clr, u32 set)
+{
+ unsigned reg = REG_GPIO(pin);
+ u32 old, new;
+
+ old = readl(priv->base + REG_GPIO(pin));
+ new = (old & ~clr) | set;
+ writel(new, priv->base + reg);
+}
+
+static int apple_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ return !!(readl(priv->base + REG_GPIO(offset)) & REG_GPIO_DATA);
+}
+
+static int apple_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ apple_pinctrl_config_pin(priv, offset, REG_GPIO_DATA,
+ value ? REG_GPIO_DATA : 0);
+ return 0;
+}
+
+static int apple_gpio_get_direction(struct udevice *dev, unsigned offset)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+ u32 reg = readl(priv->base + REG_GPIO(offset));
+
+ if (FIELD_GET(REG_GPIO_MODE, reg) == REG_GPIO_OUT)
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static int apple_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ apple_pinctrl_config_pin(priv, offset,
+ REG_GPIO_PERIPH | REG_GPIO_MODE,
+ REG_GPIO_INPUT_ENABLE);
+ return 0;
+}
+
+static int apple_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+ u32 set = (value ? REG_GPIO_DATA : 0);
+
+ apple_pinctrl_config_pin(priv, offset, REG_GPIO_DATA |
+ REG_GPIO_PERIPH | REG_GPIO_MODE,
+ set | FIELD_PREP(REG_GPIO_MODE, REG_GPIO_OUT));
+ return 0;
+}
+
+static int apple_gpio_probe(struct udevice *dev)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "gpio";
+ uc_priv->gpio_count = priv->pin_count;
+
+ return 0;
+}
+
+static struct dm_gpio_ops apple_gpio_ops = {
+ .get_value = apple_gpio_get_value,
+ .set_value = apple_gpio_set_value,
+ .get_function = apple_gpio_get_direction,
+ .direction_input = apple_gpio_direction_input,
+ .direction_output = apple_gpio_direction_output,
+};
+
+static struct driver apple_gpio_driver = {
+ .name = "apple_gpio",
+ .id = UCLASS_GPIO,
+ .probe = apple_gpio_probe,
+ .ops = &apple_gpio_ops,
+};
+
+static int apple_pinctrl_get_pins_count(struct udevice *dev)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->pin_count;
+}
+
+static const char *apple_pinctrl_get_pin_name(struct udevice *dev,
+ unsigned selector)
+{
+ static char pin_name[PINNAME_SIZE];
+
+ snprintf(pin_name, PINNAME_SIZE, "pin%d", selector);
+ return pin_name;
+}
+
+static int apple_pinctrl_get_pin_muxing(struct udevice *dev, unsigned selector,
+ char *buf, int size)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + REG_GPIO(selector)) & REG_GPIO_PERIPH)
+ strncpy(buf, "periph", size);
+ else
+ strncpy(buf, "gpio", size);
+ return 0;
+}
+
+static int apple_pinctrl_pinmux_set(struct udevice *dev, unsigned pin_selector,
+ unsigned func_selector)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+
+ apple_pinctrl_config_pin(priv, pin_selector,
+ REG_GPIO_DATA | REG_GPIO_MODE,
+ FIELD_PREP(REG_GPIO_PERIPH, func_selector) |
+ REG_GPIO_INPUT_ENABLE);
+ return 0;
+}
+
+static int apple_pinctrl_pinmux_property_set(struct udevice *dev,
+ u32 pinmux_group)
+{
+ unsigned pin_selector = APPLE_PIN(pinmux_group);
+ unsigned func_selector = APPLE_FUNC(pinmux_group);
+ int ret;
+
+ ret = apple_pinctrl_pinmux_set(dev, pin_selector, func_selector);
+ return ret ? ret : pin_selector;
+}
+
+static int apple_pinctrl_probe(struct udevice *dev)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ struct udevice *child;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ if (!dev_read_phandle_with_args(dev, "gpio-ranges",
+ NULL, 3, 0, &args))
+ priv->pin_count = args.args[2];
+
+ device_bind(dev, &apple_gpio_driver, "apple_gpio", NULL,
+ dev_ofnode(dev), &child);
+
+ return 0;
+}
+
+static struct pinctrl_ops apple_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .get_pins_count = apple_pinctrl_get_pins_count,
+ .get_pin_name = apple_pinctrl_get_pin_name,
+ .pinmux_set = apple_pinctrl_pinmux_set,
+ .pinmux_property_set = apple_pinctrl_pinmux_property_set,
+ .get_pin_muxing = apple_pinctrl_get_pin_muxing,
+};
+
+static const struct udevice_id apple_pinctrl_ids[] = {
+ { .compatible = "apple,pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_apple) = {
+ .name = "apple_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = apple_pinctrl_ids,
+ .priv_auto = sizeof(struct apple_pinctrl_priv),
+ .ops = &apple_pinctrl_ops,
+ .probe = apple_pinctrl_probe,
+};
* Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
* based on Linux driver : pinctrl/pinctrl-stmfx.c
*/
+
+#define LOG_CATEGORY UCLASS_PINCTRL
+
#include <common.h>
#include <dm.h>
+#include <log.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <dm/device.h>
/*
* Copyright (C) 2020-2021 Linaro Limited
*/
+
+#define LOG_CATEGORY UCLASS_REGULATOR
+
#include <common.h>
#include <dm.h>
#include <errno.h>
obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += stm32mp1_interactive.o
obj-$(CONFIG_STM32MP1_DDR_TESTS) += stm32mp1_tests.o
-obj-$(CONFIG_STM32MP1_DDR_TUNING) += stm32mp1_tuning.o
ifneq ($(DDR_INTERACTIVE),)
CFLAGS_stm32mp1_interactive.o += -DCONFIG_STM32MP1_DDR_INTERACTIVE_FORCE=y
#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
-#define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
DDRPHY_REG_TIMING(mr3),
};
-#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
-static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
- DDRPHY_REG_CAL(dx0dllcr),
- DDRPHY_REG_CAL(dx0dqtr),
- DDRPHY_REG_CAL(dx0dqstr),
- DDRPHY_REG_CAL(dx1dllcr),
- DDRPHY_REG_CAL(dx1dqtr),
- DDRPHY_REG_CAL(dx1dqstr),
- DDRPHY_REG_CAL(dx2dllcr),
- DDRPHY_REG_CAL(dx2dqtr),
- DDRPHY_REG_CAL(dx2dqstr),
- DDRPHY_REG_CAL(dx3dllcr),
- DDRPHY_REG_CAL(dx3dqtr),
- DDRPHY_REG_CAL(dx3dqstr),
-};
-
/**************************************************************
* DYNAMIC REGISTERS: only used for debug purpose (read/modify)
**************************************************************/
DDRPHY_REG_DYN(zq0sr1),
DDRPHY_REG_DYN(dx0gsr0),
DDRPHY_REG_DYN(dx0gsr1),
+ DDRPHY_REG_DYN(dx0dllcr),
+ DDRPHY_REG_DYN(dx0dqtr),
+ DDRPHY_REG_DYN(dx0dqstr),
DDRPHY_REG_DYN(dx1gsr0),
DDRPHY_REG_DYN(dx1gsr1),
+ DDRPHY_REG_DYN(dx1dllcr),
+ DDRPHY_REG_DYN(dx1dqtr),
+ DDRPHY_REG_DYN(dx1dqstr),
DDRPHY_REG_DYN(dx2gsr0),
DDRPHY_REG_DYN(dx2gsr1),
+ DDRPHY_REG_DYN(dx2dllcr),
+ DDRPHY_REG_DYN(dx2dqtr),
+ DDRPHY_REG_DYN(dx2dqstr),
DDRPHY_REG_DYN(dx3gsr0),
DDRPHY_REG_DYN(dx3gsr1),
+ DDRPHY_REG_DYN(dx3dllcr),
+ DDRPHY_REG_DYN(dx3dqtr),
+ DDRPHY_REG_DYN(dx3dqstr),
};
#define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
REG_MAP,
REGPHY_REG,
REGPHY_TIMING,
- REGPHY_CAL,
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
/* dynamic registers => managed in driver or not changed,
* can be dumped in interactive mode
enum base_type base;
};
-#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
-
const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
[REG_REG] = {
"static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
"static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
[REGPHY_TIMING] = {
"timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
-[REGPHY_CAL] = {
- "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
[REG_DYN] = {
"dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
case REGPHY_TIMING:
par_addr = (u32)&config->p_timing;
break;
- case REGPHY_CAL:
- par_addr = (u32)&config->p_cal;
- break;
case REG_DYN:
case REGPHY_DYN:
case REG_TYPE_NB:
(u32)&phy->pgsr, pgsr, ret);
}
-void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
+static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
{
pir |= DDRPHYC_PIR_INIT;
writel(pir, &phy->pir);
log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
}
-void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
+static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
{
start_sw_done(ctl);
/* quasi-dynamic register update*/
wait_sw_done_ack(ctl);
}
-void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
- u32 rfshctl3, u32 pwrctl)
+static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+ u32 rfshctl3, u32 pwrctl)
{
start_sw_done(ctl);
if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
*/
set_reg(priv, REGPHY_REG, &config->p_reg);
set_reg(priv, REGPHY_TIMING, &config->p_timing);
- if (config->p_cal_present)
- set_reg(priv, REGPHY_CAL, &config->p_cal);
if (INTERACTIVE(STEP_PHY_INIT))
goto start;
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
- if (config->p_cal_present) {
- log_debug("DDR DQS training skipped.\n");
- } else {
- log_debug("DDR DQS training : ");
+ log_debug("DDR DQS training : ");
/* 8. Disable Auto refresh and power down by setting
* - RFSHCTL3.dis_au_refresh = 1
* - PWRCTL.powerdown_en = 0
* - DFIMISC.dfiinit_complete_en = 0
*/
- stm32mp1_refresh_disable(priv->ctl);
+ stm32mp1_refresh_disable(priv->ctl);
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
* not done => keep the programed value in PGCR
*/
/* 10. configure PUBL PIR register to specify which training step to run */
- /* warning : RVTRN is not supported by this PUBL */
- stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
+ /* RVTRN is excuted only on LPDDR2/LPDDR3 */
+ if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+ pir = DDRPHYC_PIR_QSTRN;
+ else
+ pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN;
+ stm32mp1_ddrphy_init(priv->phy, pir);
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
- ddrphy_idone_wait(priv->phy);
+ ddrphy_idone_wait(priv->phy);
/* 12. set back registers in step 8 to the orginal values if desidered */
- stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
- config->c_reg.pwrctl);
- } /* if (config->p_cal_present) */
+ stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
+ config->c_reg.pwrctl);
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
u32 mr3;
};
-struct stm32mp1_ddrphy_cal {
- u32 dx0dllcr;
- u32 dx0dqtr;
- u32 dx0dqstr;
- u32 dx1dllcr;
- u32 dx1dqtr;
- u32 dx1dqstr;
- u32 dx2dllcr;
- u32 dx2dqtr;
- u32 dx2dqstr;
- u32 dx3dllcr;
- u32 dx3dqtr;
- u32 dx3dqstr;
-};
-
struct stm32mp1_ddr_info {
const char *name;
u32 speed; /* in kHZ */
struct stm32mp1_ddrctrl_perf c_perf;
struct stm32mp1_ddrphy_reg p_reg;
struct stm32mp1_ddrphy_timing p_timing;
- struct stm32mp1_ddrphy_cal p_cal;
- bool p_cal_present;
};
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
-void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
-void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
-void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
- u32 rfshctl3,
- u32 pwrctl);
void stm32mp1_ddr_init(
struct ddr_info *priv,
#ifndef _RAM_STM32MP1_DDR_REGS_H
#define _RAM_STM32MP1_DDR_REGS_H
-/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
#include <linux/bitops.h>
+
+/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
struct stm32mp1_ddrctl {
u32 mstr ; /* 0x0 Master*/
u32 stat; /* 0x4 Operating Mode Status*/
#define DDRCTRL_MSTR_LPDDR2 BIT(2)
#define DDRCTRL_MSTR_LPDDR3 BIT(3)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT 12
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12)
#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
-#define DDRCTRL_DBG1_DIS_HIF BIT(1)
-
-#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
-#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
-#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
-#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
-#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
-#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
- (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
- DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
-#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
- (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
- DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
- DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
-
-#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
-
-#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
-
#define DDRCTRL_SWCTL_SW_DONE BIT(0)
#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
#define DDRPHYC_PIR_DRAMRST BIT(5)
#define DDRPHYC_PIR_DRAMINIT BIT(6)
#define DDRPHYC_PIR_QSTRN BIT(7)
+#define DDRPHYC_PIR_RVTRN BIT(8)
#define DDRPHYC_PIR_ICPC BIT(16)
#define DDRPHYC_PIR_ZCALBYP BIT(30)
-#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
-
-#define DDRPHYC_PGCR_DFTCMP BIT(2)
-#define DDRPHYC_PGCR_PDDISDX BIT(24)
-#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
#define DDRPHYC_PGSR_IDONE BIT(0)
#define DDRPHYC_PGSR_DTERR BIT(5)
#define DDRPHYC_PGSR_RVERR BIT(8)
#define DDRPHYC_PGSR_RVEIRR BIT(9)
-#define DDRPHYC_DLLGCR_BPS200 BIT(23)
-
-#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
-
-#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
-#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
-#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
-
-#define DDRPHYC_DXNGCR_DXEN BIT(0)
-
-#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
-#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
-#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
-#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
-
-#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit))
-#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0)
-#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0)
-#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2)
-
-#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20)
-#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20
-#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23)
-#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23
-#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0)
-#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0
-#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12)
-#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12
-
-#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19)
-#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19
-
-#define DDRPHYC_BISTGSR_BDDONE BIT(0)
-#define DDRPHYC_BISTGSR_BDXERR BIT(2)
-
-#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16
-
/* PWR registers */
#define PWR_CR3 0x00C
#define PWR_CR3_DDRSRDIS BIT(11)
DDR_CMD_NEXT,
DDR_CMD_GO,
DDR_CMD_TEST,
- DDR_CMD_TUNING,
DDR_CMD_UNKNOWN,
};
#ifdef CONFIG_STM32MP1_DDR_TESTS
[DDR_CMD_TEST] = "test",
#endif
-#ifdef CONFIG_STM32MP1_DDR_TUNING
- [DDR_CMD_TUNING] = "tuning",
-#endif
};
/* min and max number of argument */
const char cmd_arg[DDR_CMD_UNKNOWN][2] = {
#ifdef CONFIG_STM32MP1_DDR_TESTS
[DDR_CMD_TEST] = { 0, 255 },
#endif
-#ifdef CONFIG_STM32MP1_DDR_TUNING
- [DDR_CMD_TUNING] = { 0, 255 },
-#endif
};
int i;
"help displays help\n"
"info displays DDR information\n"
"info <param> <val> changes DDR information\n"
- " with <param> = step, name, size, speed or cal\n"
+ " with <param> = step, name, size or speed\n"
"freq displays the DDR PHY frequency in kHz\n"
"freq <freq> changes the DDR PHY frequency\n"
"param [type|reg] prints input parameters\n"
#ifdef CONFIG_STM32MP1_DDR_TESTS
"test [help] | <n> [...] lists (with help) or executes test <n>\n"
#endif
-#ifdef CONFIG_STM32MP1_DDR_TUNING
- "tuning [help] | <n> [...] lists (with help) or execute tuning <n>\n"
-#endif
"\nwith for [type|reg]:\n"
" all registers if absent\n"
" <type> = ctl, phy\n"
- " or one category (static, timing, map, perf, cal, dyn)\n"
+ " or one category (static, timing, map, perf, dyn)\n"
" <reg> = name of the register\n"
};
printf("name = %s\n", config->info.name);
printf("size = 0x%x\n", config->info.size);
printf("speed = %d kHz\n", config->info.speed);
- printf("cal = %d\n", config->p_cal_present);
return;
}
}
return;
}
- if (!strcmp(argv[1], "cal")) {
- if (strict_strtoul(argv[2], 10, &value) < 0 ||
- (value != 0 && value != 1)) {
- printf("invalid value %s\n", argv[2]);
- } else {
- config->p_cal_present = value;
- printf("cal = %d\n", config->p_cal_present);
- }
- return;
- }
printf("argument %s invalid\n", argv[1]);
}
return step;
}
-#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING)
+#if defined(CONFIG_STM32MP1_DDR_TESTS)
static const char * const s_result[] = {
[TEST_PASSED] = "Pass",
[TEST_FAILED] = "Failed",
stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb);
break;
#endif
-
-#ifdef CONFIG_STM32MP1_DDR_TUNING
- case DDR_CMD_TUNING:
- if (!stm32mp1_check_step(step, STEP_DDR_READY))
- continue;
- stm32mp1_ddr_subcmd(priv, argc, argv,
- tuning, tuning_nb);
- break;
-#endif
-
default:
break;
}
#include <asm/io.h>
#include <dm/device_compat.h>
#include "stm32mp1_ddr.h"
+#include "stm32mp1_ddr_regs.h"
+
+/* DDR subsystem configuration */
+struct stm32mp1_ddr_cfg {
+ u8 nb_bytes; /* MEMC_DRAM_DATA_WIDTH */
+};
static const char *const clkname[] = {
"ddrc1",
return dev_ofnode(dev);
}
-static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
+static int stm32mp1_ddr_setup(struct udevice *dev)
{
struct ddr_info *priv = dev_get_priv(dev);
int ret;
{ .name = x, \
.offset = offsetof(struct stm32mp1_ddr_config, y), \
.size = sizeof(config.y) / sizeof(u32), \
- .present = z, \
}
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
-#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
const struct {
const char *name; /* name in DT */
const u32 offset; /* offset in config struct */
const u32 size; /* size of parameters */
- bool * const present; /* presence indication for opt */
} param[] = {
CTL_PARAM(reg),
CTL_PARAM(timing),
CTL_PARAM(map),
CTL_PARAM(perf),
PHY_PARAM(reg),
- PHY_PARAM(timing),
- PHY_PARAM_OPT(cal)
+ PHY_PARAM(timing)
};
config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
param[idx].size);
dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
param[idx].name, param[idx].size, ret);
- if (ret &&
- (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
+ if (ret) {
dev_err(dev, "Cannot read %s, error=%d\n",
param[idx].name, ret);
return -EINVAL;
}
- if (param[idx].present) {
- /* save presence of optional parameters */
- *param[idx].present = true;
- if (ret == -FDT_ERR_NOTFOUND) {
- *param[idx].present = false;
-#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
- /* reset values if used later */
- memset((void *)((u32)&config +
- param[idx].offset),
- 0, param[idx].size * sizeof(u32));
-#endif
- }
- }
}
ret = clk_get_by_name(dev, "axidcg", &axidcg);
return 0;
}
+static u8 get_data_bus_width(struct stm32mp1_ddrctl *ctl)
+{
+ u32 reg = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
+ u8 data_bus_width = reg >> DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
+
+ return data_bus_width;
+}
+
+static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
+{
+ /* Count bank address bits */
+ u8 bits = 0;
+ u32 reg, val;
+
+ reg = readl(&ctl->addrmap1);
+ /* addrmap1.addrmap_bank_b1 */
+ val = (reg & GENMASK(5, 0)) >> 0;
+ if (val <= 31)
+ bits++;
+ /* addrmap1.addrmap_bank_b2 */
+ val = (reg & GENMASK(13, 8)) >> 8;
+ if (val <= 31)
+ bits++;
+ /* addrmap1.addrmap_bank_b3 */
+ val = (reg & GENMASK(21, 16)) >> 16;
+ if (val <= 31)
+ bits++;
+
+ return bits;
+}
+
+static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)
+{
+ u8 bits;
+ u32 reg, val;
+
+ /* Count column address bits, start at 2 for b0 and b1 (fixed) */
+ bits = 2;
+
+ reg = readl(&ctl->addrmap2);
+ /* addrmap2.addrmap_col_b2 */
+ val = (reg & GENMASK(3, 0)) >> 0;
+ if (val <= 7)
+ bits++;
+ /* addrmap2.addrmap_col_b3 */
+ val = (reg & GENMASK(11, 8)) >> 8;
+ if (val <= 7)
+ bits++;
+ /* addrmap2.addrmap_col_b4 */
+ val = (reg & GENMASK(19, 16)) >> 16;
+ if (val <= 7)
+ bits++;
+ /* addrmap2.addrmap_col_b5 */
+ val = (reg & GENMASK(27, 24)) >> 24;
+ if (val <= 7)
+ bits++;
+
+ reg = readl(&ctl->addrmap3);
+ /* addrmap3.addrmap_col_b6 */
+ val = (reg & GENMASK(3, 0)) >> 0;
+ if (val <= 7)
+ bits++;
+ /* addrmap3.addrmap_col_b7 */
+ val = (reg & GENMASK(11, 8)) >> 8;
+ if (val <= 7)
+ bits++;
+ /* addrmap3.addrmap_col_b8 */
+ val = (reg & GENMASK(19, 16)) >> 16;
+ if (val <= 7)
+ bits++;
+ /* addrmap3.addrmap_col_b9 */
+ val = (reg & GENMASK(27, 24)) >> 24;
+ if (val <= 7)
+ bits++;
+
+ reg = readl(&ctl->addrmap4);
+ /* addrmap4.addrmap_col_b10 */
+ val = (reg & GENMASK(3, 0)) >> 0;
+ if (val <= 7)
+ bits++;
+ /* addrmap4.addrmap_col_b11 */
+ val = (reg & GENMASK(11, 8)) >> 8;
+ if (val <= 7)
+ bits++;
+
+ /*
+ * column bits shift up:
+ * 1 when half the data bus is used (data_bus_width = 1)
+ * 2 when a quarter the data bus is used (data_bus_width = 2)
+ * nothing to do for full data bus (data_bus_width = 0)
+ */
+ bits += data_bus_width;
+
+ return bits;
+}
+
+static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
+{
+ /* Count row address bits */
+ u8 bits = 0;
+ u32 reg, val;
+
+ reg = readl(&ctl->addrmap5);
+ /* addrmap5.addrmap_row_b0 */
+ val = (reg & GENMASK(3, 0)) >> 0;
+ if (val <= 11)
+ bits++;
+ /* addrmap5.addrmap_row_b1 */
+ val = (reg & GENMASK(11, 8)) >> 8;
+ if (val <= 11)
+ bits++;
+ /* addrmap5.addrmap_row_b2_10 */
+ val = (reg & GENMASK(19, 16)) >> 16;
+ if (val <= 11)
+ bits += 9;
+ else
+ printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
+ /* addrmap5.addrmap_row_b11 */
+ val = (reg & GENMASK(27, 24)) >> 24;
+ if (val <= 11)
+ bits++;
+
+ reg = readl(&ctl->addrmap6);
+ /* addrmap6.addrmap_row_b12 */
+ val = (reg & GENMASK(3, 0)) >> 0;
+ if (val <= 7)
+ bits++;
+ /* addrmap6.addrmap_row_b13 */
+ val = (reg & GENMASK(11, 8)) >> 8;
+ if (val <= 7)
+ bits++;
+ /* addrmap6.addrmap_row_b14 */
+ val = (reg & GENMASK(19, 16)) >> 16;
+ if (val <= 7)
+ bits++;
+ /* addrmap6.addrmap_row_b15 */
+ val = (reg & GENMASK(27, 24)) >> 24;
+ if (val <= 7)
+ bits++;
+
+ return bits;
+}
+
+/*
+ * stm32mp1_ddr_size
+ *
+ * Get the current DRAM size from the DDR CTL registers
+ *
+ * @return: DRAM size
+ */
+u32 stm32mp1_ddr_size(struct udevice *dev)
+{
+ u8 nb_bit;
+ u32 ddr_size;
+ u8 data_bus_width;
+ struct ddr_info *priv = dev_get_priv(dev);
+ struct stm32mp1_ddrctl *ctl = priv->ctl;
+ struct stm32mp1_ddr_cfg *cfg = (struct stm32mp1_ddr_cfg *)dev_get_driver_data(dev);
+ const u8 nb_bytes = cfg->nb_bytes;
+
+ data_bus_width = get_data_bus_width(ctl);
+ nb_bit = get_nb_bank(ctl) + get_nb_col(ctl, data_bus_width) +
+ get_nb_row(ctl);
+ if (nb_bit > 32) {
+ nb_bit = 32;
+ debug("invalid DDR configuration: %d bits\n", nb_bit);
+ }
+
+ ddr_size = (nb_bytes >> data_bus_width) << nb_bit;
+ if (ddr_size > STM32_DDR_SIZE) {
+ ddr_size = STM32_DDR_SIZE;
+ debug("invalid DDR configuration: size = %x\n", ddr_size);
+ }
+
+ return ddr_size;
+}
+
static int stm32mp1_ddr_probe(struct udevice *dev)
{
struct ddr_info *priv = dev_get_priv(dev);
return log_ret(ret);
}
- ofnode node = stm32mp1_ddr_get_ofnode(dev);
- priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
+ priv->info.size = stm32mp1_ddr_size(dev);
+
return 0;
}
.get_info = stm32mp1_ddr_get_info,
};
+static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
+ .nb_bytes = 4,
+};
+
static const struct udevice_id stm32mp1_ddr_ids[] = {
- { .compatible = "st,stm32mp1-ddr" },
+ { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
{ }
};
extern const struct test_desc test[];
extern const int test_nb;
-extern const struct test_desc tuning[];
-extern const int tuning_nb;
-
#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
- */
-
-#define LOG_CATEGORY UCLASS_RAM
-
-#include <common.h>
-#include <console.h>
-#include <clk.h>
-#include <log.h>
-#include <ram.h>
-#include <rand.h>
-#include <reset.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/iopoll.h>
-
-#include "stm32mp1_ddr_regs.h"
-#include "stm32mp1_ddr.h"
-#include "stm32mp1_tests.h"
-
-#define MAX_DQS_PHASE_IDX _144deg
-#define MAX_DQS_UNIT_IDX 7
-#define MAX_GSL_IDX 5
-#define MAX_GPS_IDX 3
-
-/* Number of bytes used in this SW. ( min 1--> max 4). */
-#define NUM_BYTES 4
-
-enum dqs_phase_enum {
- _36deg = 0,
- _54deg = 1,
- _72deg = 2,
- _90deg = 3,
- _108deg = 4,
- _126deg = 5,
- _144deg = 6
-};
-
-/* BIST Result struct */
-struct BIST_result {
- /* Overall test result:
- * 0 Fail (any bit failed) ,
- * 1 Success (All bits success)
- */
- bool test_result;
- /* 1: true, all fail / 0: False, not all bits fail */
- bool all_bits_fail;
- bool bit_i_test_result[8]; /* 0 fail / 1 success */
-};
-
-/* a struct that defines tuning parameters of a byte. */
-struct tuning_position {
- u8 phase; /* DQS phase */
- u8 unit; /* DQS unit delay */
- u32 bits_delay; /* Bits deskew in this byte */
-};
-
-/* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
-const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
-
-static u8 BIST_error_max = 1;
-static u32 BIST_seed = 0x1234ABCD;
-
-static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
-{
- u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
- u8 nb_bytes = NUM_BYTES;
-
- switch (data_bus) {
- case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
- nb_bytes /= 2;
- break;
- case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
- nb_bytes /= 4;
- break;
- default:
- break;
- }
-
- return nb_bytes;
-}
-
-static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
-{
- /* Count bank address bits */
- u8 bits = 0;
- u32 reg, val;
-
- reg = readl(&ctl->addrmap1);
- /* addrmap1.addrmap_bank_b1 */
- val = (reg & GENMASK(5, 0)) >> 0;
- if (val <= 31)
- bits++;
- /* addrmap1.addrmap_bank_b2 */
- val = (reg & GENMASK(13, 8)) >> 8;
- if (val <= 31)
- bits++;
- /* addrmap1.addrmap_bank_b3 */
- val = (reg & GENMASK(21, 16)) >> 16;
- if (val <= 31)
- bits++;
-
- return bits;
-}
-
-static u8 get_nb_col(struct stm32mp1_ddrctl *ctl)
-{
- u8 bits;
- u32 reg, val;
-
- /* Count column address bits, start at 2 for b0 and b1 (fixed) */
- bits = 2;
-
- reg = readl(&ctl->addrmap2);
- /* addrmap2.addrmap_col_b2 */
- val = (reg & GENMASK(3, 0)) >> 0;
- if (val <= 7)
- bits++;
- /* addrmap2.addrmap_col_b3 */
- val = (reg & GENMASK(11, 8)) >> 8;
- if (val <= 7)
- bits++;
- /* addrmap2.addrmap_col_b4 */
- val = (reg & GENMASK(19, 16)) >> 16;
- if (val <= 7)
- bits++;
- /* addrmap2.addrmap_col_b5 */
- val = (reg & GENMASK(27, 24)) >> 24;
- if (val <= 7)
- bits++;
-
- reg = readl(&ctl->addrmap3);
- /* addrmap3.addrmap_col_b6 */
- val = (reg & GENMASK(3, 0)) >> 0;
- if (val <= 7)
- bits++;
- /* addrmap3.addrmap_col_b7 */
- val = (reg & GENMASK(11, 8)) >> 8;
- if (val <= 7)
- bits++;
- /* addrmap3.addrmap_col_b8 */
- val = (reg & GENMASK(19, 16)) >> 16;
- if (val <= 7)
- bits++;
- /* addrmap3.addrmap_col_b9 */
- val = (reg & GENMASK(27, 24)) >> 24;
- if (val <= 7)
- bits++;
-
- reg = readl(&ctl->addrmap4);
- /* addrmap4.addrmap_col_b10 */
- val = (reg & GENMASK(3, 0)) >> 0;
- if (val <= 7)
- bits++;
- /* addrmap4.addrmap_col_b11 */
- val = (reg & GENMASK(11, 8)) >> 8;
- if (val <= 7)
- bits++;
-
- return bits;
-}
-
-static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
-{
- /* Count row address bits */
- u8 bits = 0;
- u32 reg, val;
-
- reg = readl(&ctl->addrmap5);
- /* addrmap5.addrmap_row_b0 */
- val = (reg & GENMASK(3, 0)) >> 0;
- if (val <= 11)
- bits++;
- /* addrmap5.addrmap_row_b1 */
- val = (reg & GENMASK(11, 8)) >> 8;
- if (val <= 11)
- bits++;
- /* addrmap5.addrmap_row_b2_10 */
- val = (reg & GENMASK(19, 16)) >> 16;
- if (val <= 11)
- bits += 9;
- else
- printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
- /* addrmap5.addrmap_row_b11 */
- val = (reg & GENMASK(27, 24)) >> 24;
- if (val <= 11)
- bits++;
-
- reg = readl(&ctl->addrmap6);
- /* addrmap6.addrmap_row_b12 */
- val = (reg & GENMASK(3, 0)) >> 0;
- if (val <= 7)
- bits++;
- /* addrmap6.addrmap_row_b13 */
- val = (reg & GENMASK(11, 8)) >> 8;
- if (val <= 7)
- bits++;
- /* addrmap6.addrmap_row_b14 */
- val = (reg & GENMASK(19, 16)) >> 16;
- if (val <= 7)
- bits++;
- /* addrmap6.addrmap_row_b15 */
- val = (reg & GENMASK(27, 24)) >> 24;
- if (val <= 7)
- bits++;
-
- return bits;
-}
-
-static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
-{
- stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
-}
-
-/* Read DQ unit delay register and provides the retrieved value for DQS
- * We are assuming that we have the same delay when clocking
- * by DQS and when clocking by DQSN
- */
-static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
-{
- u32 index;
- u32 addr = DXNDQTR(phy, byte);
-
- /* We are assuming that we have the same delay when clocking by DQS
- * and when clocking by DQSN : use only the low bits
- */
- index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
- & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
-
- log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index);
-
- return index;
-}
-
-/* Sets the DQS phase delay for a byte lane.
- *phase delay is specified by giving the index of the desired delay
- * in the dx_dll_phase array.
- */
-static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
-{
- u8 sdphase_val = 0;
-
- /* Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
- sdphase_val = dx_dll_phase[phase_idx];
- clrsetbits_le32(DXNDLLCR(phy, byte),
- DDRPHYC_DXNDLLCR_SDPHASE_MASK,
- sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
-}
-
-/* Sets the DQS unit delay for a byte lane.
- * unit delay is specified by giving the index of the desired delay
- * for dgsdly and dqsndly (same value).
- */
-static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
- u8 byte, u8 unit_dly_idx)
-{
- /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
- clrsetbits_le32(DXNDQSTR(phy, byte),
- DDRPHYC_DXNDQSTR_DQSDLY_MASK |
- DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
- (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
- (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
-
- /* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
- * plus PIR.INIT=1) must be issued.
- */
- stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
-}
-
-/* Sets the DQ unit delay for a bit line in particular byte lane.
- * unit delay is specified by giving the desired delay
- */
-static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
- u8 byte, u8 bit,
- u8 dq_delay_index)
-{
- u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
-
- /* same value on delay for clock DQ an DQS_b */
- clrsetbits_le32(DXNDQTR(phy, byte),
- DDRPHYC_DXNDQTR_DQDLY_MASK
- << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
- dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
-}
-
-static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
- u8 byte, u8 r0dgsl_idx)
-{
- clrsetbits_le32(DXNDQSTR(phy, byte),
- DDRPHYC_DXNDQSTR_R0DGSL_MASK,
- r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
-}
-
-static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
- u8 byte, u8 r0dgps_idx)
-{
- clrsetbits_le32(DXNDQSTR(phy, byte),
- DDRPHYC_DXNDQSTR_R0DGPS_MASK,
- r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
-}
-
-/* Basic BIST configuration for data lane tests. */
-static void config_BIST(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy)
-{
- u8 nb_bank = get_nb_bank(ctl);
- u8 nb_row = get_nb_row(ctl);
- u8 nb_col = get_nb_col(ctl);
-
- /* Selects the SDRAM bank address to be used during BIST. */
- u32 bbank = 0;
- /* Selects the SDRAM row address to be used during BIST. */
- u32 brow = 0;
- /* Selects the SDRAM column address to be used during BIST. */
- u32 bcol = 0;
- /* Selects the value by which the SDRAM address is incremented
- * for each write/read access.
- */
- u32 bainc = 0x00000008;
- /* Specifies the maximum SDRAM rank to be used during BIST.
- * The default value is set to maximum ranks minus 1.
- * must be 0 with single rank
- */
- u32 bmrank = 0;
- /* Selects the SDRAM rank to be used during BIST.
- * must be 0 with single rank
- */
- u32 brank = 0;
-
- /* Specifies the maximum SDRAM bank address to be used during
- * BIST before the address & increments to the next rank.
- */
- u32 bmbank = (1 << nb_bank) - 1;
- /* Specifies the maximum SDRAM row address to be used during
- * BIST before the address & increments to the next bank.
- */
- u32 bmrow = (1 << nb_row) - 1;
- /* Specifies the maximum SDRAM column address to be used during
- * BIST before the address & increments to the next row.
- */
- u32 bmcol = (1 << nb_col) - 1;
-
- u32 bmode_conf = 0x00000001; /* DRam mode */
- u32 bdxen_conf = 0x00000001; /* BIST on Data byte */
- u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */
-
- /*Setup BIST for DRAM mode, and LFSR-random data pattern.*/
- /*Write BISTRR.BMODE = 1?b1;*/
- /*Write BISTRR.BDXEN = 1?b1;*/
- /*Write BISTRR.BDPAT = 2?b10;*/
-
- /* reset BIST */
- writel(0x3, &phy->bistrr);
-
- writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
- &phy->bistrr);
-
- /*Setup BIST Word Count*/
- /*Write BISTWCR.BWCNT = 16?b0008;*/
- writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
-
- writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
- writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
- writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
-}
-
-/* Select the Byte lane to be tested by BIST. */
-static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
-{
- clrsetbits_le32(&phy->bistrr,
- DDRPHYC_BISTRR_BDXSEL_MASK,
- datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
-
- /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
- /* Write BISTRR.BDXSEL = datx8; */
-}
-
-/* Perform BIST Write_Read test on a byte lane and return test result. */
-static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
- struct BIST_result *bist)
-{
- bool result = true; /* BIST_SUCCESS */
- u32 cnt = 0;
- u32 error = 0;
- u32 val;
- int ret;
-
- bist->test_result = true;
-
-run:
- itm_soft_reset(phy);
-
- /*Perform BIST Reset*/
- /* Write BISTRR.BINST = 3?b011; */
- clrsetbits_le32(&phy->bistrr,
- 0x00000007,
- 0x00000003);
-
- /*Re-seed LFSR*/
- /* Write BISTLSR.SEED = 32'h1234ABCD; */
- if (BIST_seed)
- writel(BIST_seed, &phy->bistlsr);
- else
- writel(rand(), &phy->bistlsr);
-
- /* some delay to reset BIST */
- udelay(10);
-
- /*Perform BIST Run*/
- clrsetbits_le32(&phy->bistrr,
- 0x00000007,
- 0x00000001);
- /* Write BISTRR.BINST = 3?b001; */
-
- /* poll on BISTGSR.BDONE and wait max 1000 us */
- ret = readl_poll_timeout(&phy->bistgsr, val,
- val & DDRPHYC_BISTGSR_BDDONE, 1000);
-
- if (ret < 0) {
- printf("warning: BIST timeout\n");
- result = false; /* BIST_FAIL; */
- /*Perform BIST Stop */
- clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002);
- } else {
- /*Check if received correct number of words*/
- /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
- if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT)
- == readl(&phy->bistwcr)) {
- /*Determine if there is a data comparison error*/
- /* if (Read BISTGSR.BDXERR = 1?b0) */
- if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
- result = false; /* BIST_FAIL; */
- else
- result = true; /* BIST_SUCCESS; */
- } else {
- result = false; /* BIST_FAIL; */
- }
- }
-
- /* loop while success */
- cnt++;
- if (result && cnt != 1000)
- goto run;
-
- if (!result)
- error++;
-
- if (error < BIST_error_max) {
- if (cnt != 1000)
- goto run;
- bist->test_result = true;
- } else {
- bist->test_result = false;
- }
-}
-
-/* After running the deskew algo, this function applies the new DQ delays
- * by reading them from the array "deskew_delay"and writing in PHY registers.
- * The bits that are not deskewed parfectly (too much skew on them,
- * or data eye very wide) are marked in the array deskew_non_converge.
- */
-static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
- u8 deskew_delay[NUM_BYTES][8],
- u8 deskew_non_converge[NUM_BYTES][8])
-{
- u8 bit_i;
- u8 index;
-
- for (bit_i = 0; bit_i < 8; bit_i++) {
- set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
- index = DQ_unit_index(phy, byte, bit_i);
- log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
- byte, bit_i, deskew_delay[byte][bit_i],
- index, index - 3);
- printf("Byte %d, bit %d, DQ delay = %d",
- byte, bit_i, deskew_delay[byte][bit_i]);
- if (deskew_non_converge[byte][bit_i] == 1)
- log_debug(" - not converged : still more skew");
- printf("\n");
- }
-}
-
-/* DQ Bit de-skew algorithm.
- * Deskews data lines as much as possible.
- * 1. Add delay to DQS line until finding the failure
- * (normally a hold time violation)
- * 2. Reduce DQS line by small steps until finding the very first time
- * we go back to "Pass" condition.
- * 3. For each DQ line, Reduce DQ delay until finding the very first failure
- * (normally a hold time fail)
- * 4. When all bits are at their first failure delay, we can consider them
- * aligned.
- * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
- * at any step)
- * TODO Provide a return Status. Improve doc
- */
-static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy, char *string)
-{
- /* New DQ delay value (index), set during Deskew algo */
- u8 deskew_delay[NUM_BYTES][8];
- /*If there is still skew on a bit, mark this bit. */
- u8 deskew_non_converge[NUM_BYTES][8];
- struct BIST_result result;
- s8 dqs_unit_delay_index = 0;
- u8 datx8 = 0;
- u8 bit_i = 0;
- s8 phase_idx = 0;
- s8 bit_i_delay_index = 0;
- u8 success = 0;
- struct tuning_position last_right_ok;
- u8 force_stop = 0;
- u8 fail_found;
- u8 error = 0;
- u8 nb_bytes = get_nb_bytes(ctl);
- /* u8 last_pass_dqs_unit = 0; */
-
- memset(deskew_delay, 0, sizeof(deskew_delay));
- memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
-
- /*Disable DQS Drift Compensation*/
- clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
- /*Disable all bytes*/
- /* Disable automatic power down of DLL and IOs when disabling
- * a byte (To avoid having to add programming and delay
- * for a DLL re-lock when later re-enabling a disabled Byte Lane)
- */
- clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
-
- /* Disable all data bytes */
- clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
-
- /* Config the BIST block */
- config_BIST(ctl, phy);
- log_debug("BIST Config done.\n");
-
- /* Train each byte */
- for (datx8 = 0; datx8 < nb_bytes; datx8++) {
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- datx8 + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- log_debug("\n======================\n");
- log_debug("Start deskew byte %d .\n", datx8);
- log_debug("======================\n");
- /* Enable Byte (DXNGCR, bit DXEN) */
- setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
-
- /* Select the byte lane for comparison of read data */
- BIST_datx8_sel(phy, datx8);
-
- /* Set all DQDLYn to maximum value. All bits within the byte
- * will be delayed with DQSTR = 2 instead of max = 3
- * to avoid inter bits fail influence
- */
- writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
-
- /* Set the DQS phase delay to 90 DEG (default).
- * What is defined here is the index of the desired config
- * in the PHASE array.
- */
- phase_idx = _90deg;
-
- /* Set DQS unit delay to the max value. */
- dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
- DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
- DQS_phase_delay(phy, datx8, phase_idx);
-
- /* Issue a DLL soft reset */
- clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
- setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
-
- /* Test this typical init condition */
- BIST_test(phy, datx8, &result);
- success = result.test_result;
-
- /* If the test pass in this typical condition,
- * start the algo with it.
- * Else, look for Pass init condition
- */
- if (!success) {
- log_debug("Fail at init condtion. Let's look for a good init condition.\n");
- success = 0; /* init */
- /* Make sure we start with a PASS condition before
- * looking for a fail condition.
- * Find the first PASS PHASE condition
- */
-
- /* escape if we find a PASS */
- log_debug("increase Phase idx\n");
- while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
- DQS_phase_delay(phy, datx8, phase_idx);
- BIST_test(phy, datx8, &result);
- success = result.test_result;
- phase_idx++;
- }
- /* if ended with success
- * ==>> Restore the fist success condition
- */
- if (success)
- phase_idx--; /* because it ended with ++ */
- }
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- datx8 + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- /* We couldn't find a successful condition, its seems
- * we have hold violation, lets try reduce DQS_unit Delay
- */
- if (!success) {
- /* We couldn't find a successful condition, its seems
- * we have hold violation, lets try reduce DQS_unit
- * Delay
- */
- log_debug("Still fail. Try decrease DQS Unit delay\n");
-
- phase_idx = 0;
- dqs_unit_delay_index = 0;
- DQS_phase_delay(phy, datx8, phase_idx);
-
- /* escape if we find a PASS */
- while (!success &&
- (dqs_unit_delay_index <=
- MAX_DQS_UNIT_IDX)) {
- DQS_unit_delay(phy, datx8,
- dqs_unit_delay_index);
- BIST_test(phy, datx8, &result);
- success = result.test_result;
- dqs_unit_delay_index++;
- }
- if (success) {
- /* Restore the first success condition*/
- dqs_unit_delay_index--;
- /* last_pass_dqs_unit = dqs_unit_delay_index;*/
- DQS_unit_delay(phy, datx8,
- dqs_unit_delay_index);
- } else {
- /* No need to continue,
- * there is no pass region.
- */
- force_stop = 1;
- }
- }
-
- /* There is an initial PASS condition
- * Look for the first failing condition by PHASE stepping.
- * This part of the algo can finish without converging.
- */
- if (force_stop) {
- printf("Result: Failed ");
- printf("[Cannot Deskew lines, ");
- printf("there is no PASS region]\n");
- error++;
- continue;
- }
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- datx8 + 1, nb_bytes, error);
- return TEST_FAILED;
- }
-
- log_debug("there is a pass region for phase idx %d\n",
- phase_idx);
- log_debug("Step1: Find the first failing condition\n");
- /* Look for the first failing condition by PHASE stepping.
- * This part of the algo can finish without converging.
- */
-
- /* escape if we find a fail (hold time violation)
- * condition at any bit or if out of delay range.
- */
- while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
- DQS_phase_delay(phy, datx8, phase_idx);
- BIST_test(phy, datx8, &result);
- success = result.test_result;
- phase_idx++;
- }
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- datx8 + 1, nb_bytes, error);
- return TEST_FAILED;
- }
-
- /* if the loop ended with a failing condition at any bit,
- * lets look for the first previous success condition by unit
- * stepping (minimal delay)
- */
- if (!success) {
- log_debug("Fail region (PHASE) found phase idx %d\n",
- phase_idx);
- log_debug("Let's look for first success by DQS Unit steps\n");
- /* This part, the algo always converge */
- phase_idx--;
-
- /* escape if we find a success condition
- * or if out of delay range.
- */
- while (!success && dqs_unit_delay_index >= 0) {
- DQS_unit_delay(phy, datx8,
- dqs_unit_delay_index);
- BIST_test(phy, datx8, &result);
- success = result.test_result;
- dqs_unit_delay_index--;
- }
- /* if the loop ended with a success condition,
- * the last delay Right OK (before hold violation)
- * condition is then defined as following:
- */
- if (success) {
- /* Hold the dely parameters of the the last
- * delay Right OK condition.
- * -1 to get back to current condition
- */
- last_right_ok.phase = phase_idx;
- /*+1 to get back to current condition */
- last_right_ok.unit = dqs_unit_delay_index + 1;
- last_right_ok.bits_delay = 0xFFFFFFFF;
- log_debug("Found %d\n", dqs_unit_delay_index);
- } else {
- /* the last OK condition is then with the
- * previous phase_idx.
- * -2 instead of -1 because at the last
- * iteration of the while(),
- * we incremented phase_idx
- */
- last_right_ok.phase = phase_idx - 1;
- /* Nominal+1. Because we want the previous
- * delay after reducing the phase delay.
- */
- last_right_ok.unit = 1;
- last_right_ok.bits_delay = 0xFFFFFFFF;
- log_debug("Not Found : try previous phase %d\n",
- phase_idx - 1);
-
- DQS_phase_delay(phy, datx8, phase_idx - 1);
- dqs_unit_delay_index = 0;
- success = true;
- while (success &&
- (dqs_unit_delay_index <
- MAX_DQS_UNIT_IDX)) {
- DQS_unit_delay(phy, datx8,
- dqs_unit_delay_index);
- BIST_test(phy, datx8, &result);
- success = result.test_result;
- dqs_unit_delay_index++;
- log_debug("dqs_unit_delay_index = %d, result = %d\n",
- dqs_unit_delay_index, success);
- }
-
- if (!success) {
- last_right_ok.unit =
- dqs_unit_delay_index - 1;
- } else {
- last_right_ok.unit = 0;
- log_debug("ERROR: failed region not FOUND");
- }
- }
- } else {
- /* we can't find a failing condition at all bits
- * ==> Just hold the last test condition
- * (the max DQS delay)
- * which is the most likely,
- * the closest to a hold violation
- * If we can't find a Fail condition after
- * the Pass region, stick at this position
- * In order to have max chances to find a fail
- * when reducing DQ delays.
- */
- last_right_ok.phase = MAX_DQS_PHASE_IDX;
- last_right_ok.unit = MAX_DQS_UNIT_IDX;
- last_right_ok.bits_delay = 0xFFFFFFFF;
- log_debug("Can't find the a fail condition\n");
- }
-
- /* step 2:
- * if we arrive at this stage, it means that we found the last
- * Right OK condition (by tweeking the DQS delay). Or we simply
- * pushed DQS delay to the max
- * This means that by reducing the delay on some DQ bits,
- * we should find a failing condition.
- */
- printf("Byte %d, DQS unit = %d, phase = %d\n",
- datx8, last_right_ok.unit, last_right_ok.phase);
- log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
- last_right_ok.unit, last_right_ok.phase,
- last_right_ok.bits_delay);
-
- /* Restore the last_right_ok condtion. */
- DQS_unit_delay(phy, datx8, last_right_ok.unit);
- DQS_phase_delay(phy, datx8, last_right_ok.phase);
- writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
-
- /* train each bit
- * reduce delay on each bit, and perform a write/read test
- * and stop at the very first time it fails.
- * the goal is the find the first failing condition
- * for each bit.
- * When we achieve this condition< for all the bits,
- * we are sure they are aligned (+/- step resolution)
- */
- fail_found = 0;
- for (bit_i = 0; bit_i < 8; bit_i++) {
- if (ctrlc()) {
- sprintf(string,
- "interrupted at byte %d/%d, error=%d",
- datx8 + 1, nb_bytes, error);
- return error;
- }
- log_debug("deskewing bit %d:\n", bit_i);
- success = 1; /* init */
- /* Set all DQDLYn to maximum value.
- * Only bit_i will be down-delayed
- * ==> if we have a fail, it will be definitely
- * from bit_i
- */
- writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
- /* Arriving at this stage,
- * we have a success condition with delay = 3;
- */
- bit_i_delay_index = 3;
-
- /* escape if bit delay is out of range or
- * if a fatil occurs
- */
- while ((bit_i_delay_index >= 0) && success) {
- set_DQ_unit_delay(phy, datx8,
- bit_i,
- bit_i_delay_index);
- BIST_test(phy, datx8, &result);
- success = result.test_result;
- bit_i_delay_index--;
- }
-
- /* if escape with a fail condition
- * ==> save this position for bit_i
- */
- if (!success) {
- /* save the delay position.
- * Add 1 because the while loop ended with a --,
- * and that we need to hold the last success
- * delay
- */
- deskew_delay[datx8][bit_i] =
- bit_i_delay_index + 2;
- if (deskew_delay[datx8][bit_i] > 3)
- deskew_delay[datx8][bit_i] = 3;
-
- /* A flag that states we found at least a fail
- * at one bit.
- */
- fail_found = 1;
- log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
- bit_i, bit_i_delay_index + 1,
- datx8, bit_i,
- deskew_delay[datx8][bit_i]);
- } else {
- /* if we can find a success condition by
- * back-delaying this bit, just set the delay
- * to 0 (the best deskew
- * possible) and mark the bit.
- */
- deskew_delay[datx8][bit_i] = 0;
- /* set a flag that will be used later
- * in the report.
- */
- deskew_non_converge[datx8][bit_i] = 1;
- log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
- bit_i, datx8, bit_i,
- deskew_delay[datx8][bit_i]);
- }
- }
- log_debug("**********byte %d tuning complete************\n",
- datx8);
- /* If we can't find any failure by back delaying DQ lines,
- * hold the default values
- */
- if (!fail_found) {
- for (bit_i = 0; bit_i < 8; bit_i++)
- deskew_delay[datx8][bit_i] = 0;
- log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
- }
-
- apply_deskew_results(phy, datx8, deskew_delay,
- deskew_non_converge);
- /* Restore nominal value for DQS delay */
- DQS_phase_delay(phy, datx8, 3);
- DQS_unit_delay(phy, datx8, 3);
- /* disable byte after byte bits deskew */
- clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
- } /* end of byte deskew */
-
- /* re-enable all data bytes */
- setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
- setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
- setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
- setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
-
- if (error) {
- sprintf(string, "error = %d", error);
- return TEST_FAILED;
- }
-
- return TEST_PASSED;
-} /* end function */
-
-/* Trim DQS timings and set it in the centre of data eye.
- * Look for a PPPPF region, then look for a FPPP region and finally select
- * the mid of the FPPPPPF region
- */
-static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy, char *string)
-{
- /*Stores the DQS trim values (PHASE index, unit index) */
- u8 eye_training_val[NUM_BYTES][2];
- u8 byte = 0;
- struct BIST_result result;
- s8 dqs_unit_delay_index = 0;
- s8 phase_idx = 0;
- s8 dqs_unit_delay_index_pass = 0;
- s8 phase_idx_pass = 0;
- u8 success = 0;
- u8 left_phase_bound_found, right_phase_bound_found;
- u8 left_unit_bound_found, right_unit_bound_found;
- u8 left_bound_found, right_bound_found;
- struct tuning_position left_bound, right_bound;
- u8 error = 0;
- u8 nb_bytes = get_nb_bytes(ctl);
-
- /*Disable DQS Drift Compensation*/
- clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
- /*Disable all bytes*/
- /* Disable automatic power down of DLL and IOs when disabling a byte
- * (To avoid having to add programming and delay
- * for a DLL re-lock when later re-enabling a disabled Byte Lane)
- */
- clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
-
- /*Disable all data bytes */
- clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
-
- /* Config the BIST block */
- config_BIST(ctl, phy);
-
- for (byte = 0; byte < nb_bytes; byte++) {
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- byte + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- right_bound.phase = 0;
- right_bound.unit = 0;
-
- left_bound.phase = 0;
- left_bound.unit = 0;
-
- left_phase_bound_found = 0;
- right_phase_bound_found = 0;
-
- left_unit_bound_found = 0;
- right_unit_bound_found = 0;
-
- left_bound_found = 0;
- right_bound_found = 0;
-
- /* Enable Byte (DXNGCR, bit DXEN) */
- setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
-
- /* Select the byte lane for comparison of read data */
- BIST_datx8_sel(phy, byte);
-
- /* Set DQS phase delay to the nominal value. */
- phase_idx = _90deg;
- phase_idx_pass = phase_idx;
-
- /* Set DQS unit delay to the nominal value. */
- dqs_unit_delay_index = 3;
- dqs_unit_delay_index_pass = dqs_unit_delay_index;
- success = 0;
-
- log_debug("STEP0: Find Init delay\n");
- /* STEP0: Find Init delay: a delay that put the system
- * in a "Pass" condition then (TODO) update
- * dqs_unit_delay_index_pass & phase_idx_pass
- */
- DQS_unit_delay(phy, byte, dqs_unit_delay_index);
- DQS_phase_delay(phy, byte, phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
- /* If we have a fail in the nominal condition */
- if (!success) {
- /* Look at the left */
- while (phase_idx >= 0 && !success) {
- phase_idx--;
- DQS_phase_delay(phy, byte, phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
- }
- }
- if (!success) {
- /* if we can't find pass condition,
- * then look at the right
- */
- phase_idx = _90deg;
- while (phase_idx <= MAX_DQS_PHASE_IDX &&
- !success) {
- phase_idx++;
- DQS_phase_delay(phy, byte,
- phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
- }
- }
- /* save the pass condition */
- if (success) {
- phase_idx_pass = phase_idx;
- } else {
- printf("Result: Failed ");
- printf("[Cannot DQS timings, ");
- printf("there is no PASS region]\n");
- error++;
- continue;
- }
-
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- byte + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- log_debug("STEP1: Find LEFT PHASE DQS Bound\n");
- /* STEP1: Find LEFT PHASE DQS Bound */
- while ((phase_idx >= 0) &&
- (phase_idx <= MAX_DQS_PHASE_IDX) &&
- !left_phase_bound_found) {
- DQS_unit_delay(phy, byte,
- dqs_unit_delay_index);
- DQS_phase_delay(phy, byte,
- phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
-
- /*TODO: Manage the case were at the beginning
- * there is already a fail
- */
- if (!success) {
- /* the last pass condition */
- left_bound.phase = ++phase_idx;
- left_phase_bound_found = 1;
- } else if (success) {
- phase_idx--;
- }
- }
- if (!left_phase_bound_found) {
- left_bound.phase = 0;
- phase_idx = 0;
- }
- /* If not found, lets take 0 */
-
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- byte + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- log_debug("STEP2: Find UNIT left bound\n");
- /* STEP2: Find UNIT left bound */
- while ((dqs_unit_delay_index >= 0) &&
- !left_unit_bound_found) {
- DQS_unit_delay(phy, byte,
- dqs_unit_delay_index);
- DQS_phase_delay(phy, byte, phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
- if (!success) {
- left_bound.unit =
- ++dqs_unit_delay_index;
- left_unit_bound_found = 1;
- left_bound_found = 1;
- } else if (success) {
- dqs_unit_delay_index--;
- }
- }
-
- /* If not found, lets take 0 */
- if (!left_unit_bound_found)
- left_bound.unit = 0;
-
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- byte + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- log_debug("STEP3: Find PHase right bound\n");
- /* STEP3: Find PHase right bound, start with "pass"
- * condition
- */
-
- /* Set DQS phase delay to the pass value. */
- phase_idx = phase_idx_pass;
-
- /* Set DQS unit delay to the pass value. */
- dqs_unit_delay_index = dqs_unit_delay_index_pass;
-
- while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
- !right_phase_bound_found) {
- DQS_unit_delay(phy, byte,
- dqs_unit_delay_index);
- DQS_phase_delay(phy, byte, phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
- if (!success) {
- /* the last pass condition */
- right_bound.phase = --phase_idx;
- right_phase_bound_found = 1;
- } else if (success) {
- phase_idx++;
- }
- }
-
- /* If not found, lets take the max value */
- if (!right_phase_bound_found) {
- right_bound.phase = MAX_DQS_PHASE_IDX;
- phase_idx = MAX_DQS_PHASE_IDX;
- }
-
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d, error=%d",
- byte + 1, nb_bytes, error);
- return TEST_FAILED;
- }
- log_debug("STEP4: Find UNIT right bound\n");
- /* STEP4: Find UNIT right bound */
- while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
- !right_unit_bound_found) {
- DQS_unit_delay(phy, byte,
- dqs_unit_delay_index);
- DQS_phase_delay(phy, byte, phase_idx);
- BIST_test(phy, byte, &result);
- success = result.test_result;
- if (!success) {
- right_bound.unit =
- --dqs_unit_delay_index;
- right_unit_bound_found = 1;
- right_bound_found = 1;
- } else if (success) {
- dqs_unit_delay_index++;
- }
- }
- /* If not found, lets take the max value */
- if (!right_unit_bound_found)
- right_bound.unit = MAX_DQS_UNIT_IDX;
-
- /* If we found a regular FAil Pass FAil pattern
- * FFPPPPPPFF
- * OR PPPPPFF Or FFPPPPP
- */
-
- if (left_bound_found || right_bound_found) {
- eye_training_val[byte][0] = (right_bound.phase +
- left_bound.phase) / 2;
- eye_training_val[byte][1] = (right_bound.unit +
- left_bound.unit) / 2;
-
- /* If we already lost 1/2PHASE Tuning,
- * let's try to recover by ++ on unit
- */
- if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
- eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
- eye_training_val[byte][1]++;
- log_debug("** found phase : %d - %d & unit %d - %d\n",
- right_bound.phase, left_bound.phase,
- right_bound.unit, left_bound.unit);
- log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
- eye_training_val[byte][0],
- eye_training_val[byte][1]);
- } else {
- /* PPPPPPPPPP, we're already good.
- * Set nominal values.
- */
- eye_training_val[byte][0] = 3;
- eye_training_val[byte][1] = 3;
- }
- DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
- DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
-
- printf("Byte %d, DQS unit = %d, phase = %d\n",
- byte,
- eye_training_val[byte][1],
- eye_training_val[byte][0]);
- }
-
- if (error) {
- sprintf(string, "error = %d", error);
- return TEST_FAILED;
- }
-
- return TEST_PASSED;
-}
-
-static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
-{
- u8 i = 0;
-
- printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n ",
- byte);
-
- for (i = 0; i < 8; i++)
- printf("%d ", DQ_unit_index(phy, byte, i));
- printf("\n");
-
- printf("dxndllcr: [%08x] val:%08x\n",
- DXNDLLCR(phy, byte),
- readl(DXNDLLCR(phy, byte)));
- printf("dxnqdstr: [%08x] val:%08x\n",
- DXNDQSTR(phy, byte),
- readl(DXNDQSTR(phy, byte)));
- printf("dxndqtr: [%08x] val:%08x\n",
- DXNDQTR(phy, byte),
- readl(DXNDQTR(phy, byte)));
-}
-
-/* analyse the dgs gating log table, and determine the midpoint.*/
-static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
- u8 dqs_gating[NUM_BYTES]
- [MAX_GSL_IDX + 1]
- [MAX_GPS_IDX + 1])
-{
- /* stores the dqs gate values (gsl index, gps index) */
- u8 dqs_gate_values[NUM_BYTES][2];
- u8 gsl_idx, gps_idx = 0;
- u8 left_bound_idx[2] = {0, 0};
- u8 right_bound_idx[2] = {0, 0};
- u8 left_bound_found = 0;
- u8 right_bound_found = 0;
- u8 intermittent = 0;
- u8 value;
-
- for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
- for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
- value = dqs_gating[byte][gsl_idx][gps_idx];
- if (value == 1 && left_bound_found == 0) {
- left_bound_idx[0] = gsl_idx;
- left_bound_idx[1] = gps_idx;
- left_bound_found = 1;
- } else if (value == 0 &&
- left_bound_found == 1 &&
- !right_bound_found) {
- if (gps_idx == 0) {
- right_bound_idx[0] = gsl_idx - 1;
- right_bound_idx[1] = MAX_GPS_IDX;
- } else {
- right_bound_idx[0] = gsl_idx;
- right_bound_idx[1] = gps_idx - 1;
- }
- right_bound_found = 1;
- } else if (value == 1 &&
- right_bound_found == 1) {
- intermittent = 1;
- }
- }
- }
-
- /* if only ppppppp is found, there is no mid region. */
- if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
- right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
- intermittent = 1;
-
- /*if we found a regular fail pass fail pattern ffppppppff
- * or pppppff or ffppppp
- */
- if (!intermittent) {
- /*if we found a regular fail pass fail pattern ffppppppff
- * or pppppff or ffppppp
- */
- if (left_bound_found || right_bound_found) {
- log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
- left_bound_found,
- right_bound_idx[0], left_bound_idx[0],
- right_bound_found,
- right_bound_idx[1], left_bound_idx[1]);
- dqs_gate_values[byte][0] =
- (right_bound_idx[0] + left_bound_idx[0]) / 2;
- dqs_gate_values[byte][1] =
- (right_bound_idx[1] + left_bound_idx[1]) / 2;
- /* if we already lost 1/2gsl tuning,
- * let's try to recover by ++ on gps
- */
- if (((right_bound_idx[0] +
- left_bound_idx[0]) % 2 == 1) &&
- dqs_gate_values[byte][1] != MAX_GPS_IDX)
- dqs_gate_values[byte][1]++;
- /* if we already lost 1/2gsl tuning and gps is on max*/
- else if (((right_bound_idx[0] +
- left_bound_idx[0]) % 2 == 1) &&
- dqs_gate_values[byte][1] == MAX_GPS_IDX) {
- dqs_gate_values[byte][1] = 0;
- dqs_gate_values[byte][0]++;
- }
- /* if we have gsl left and write limit too close
- * (difference=1)
- */
- if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
- dqs_gate_values[byte][1] = (left_bound_idx[1] +
- right_bound_idx[1] +
- 4) / 2;
- if (dqs_gate_values[byte][1] >= 4) {
- dqs_gate_values[byte][0] =
- right_bound_idx[0];
- dqs_gate_values[byte][1] -= 4;
- } else {
- dqs_gate_values[byte][0] =
- left_bound_idx[0];
- }
- }
- log_debug("*******calculating mid region: system latency: %d phase: %d********\n",
- dqs_gate_values[byte][0],
- dqs_gate_values[byte][1]);
- log_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
- }
- } else {
- /* if intermitant, restore defaut values */
- log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
- dqs_gate_values[byte][0] = 0;
- dqs_gate_values[byte][1] = 2;
- }
- set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
- set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
- printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n",
- byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]);
-
- /* return 0 if intermittent or if both left_bound
- * and right_bound are not found
- */
- return !(intermittent || (left_bound_found && right_bound_found));
-}
-
-static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy,
- char *string)
-{
- /* stores the log of pass/fail */
- u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
- u8 byte, gsl_idx, gps_idx = 0;
- struct BIST_result result;
- u8 success = 0;
- u8 nb_bytes = get_nb_bytes(ctl);
-
- memset(dqs_gating, 0x0, sizeof(dqs_gating));
-
- /*disable dqs drift compensation*/
- clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
- /*disable all bytes*/
- /* disable automatic power down of dll and ios when disabling a byte
- * (to avoid having to add programming and delay
- * for a dll re-lock when later re-enabling a disabled byte lane)
- */
- clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
-
- /* disable all data bytes */
- clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
- clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
-
- /* config the bist block */
- config_BIST(ctl, phy);
-
- for (byte = 0; byte < nb_bytes; byte++) {
- if (ctrlc()) {
- sprintf(string, "interrupted at byte %d/%d",
- byte + 1, nb_bytes);
- return TEST_FAILED;
- }
- /* enable byte x (dxngcr, bit dxen) */
- setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
-
- /* select the byte lane for comparison of read data */
- BIST_datx8_sel(phy, byte);
- for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
- for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
- if (ctrlc()) {
- sprintf(string,
- "interrupted at byte %d/%d",
- byte + 1, nb_bytes);
- return TEST_FAILED;
- }
- /* write cfg to dxndqstr */
- set_r0dgsl_delay(phy, byte, gsl_idx);
- set_r0dgps_delay(phy, byte, gps_idx);
-
- BIST_test(phy, byte, &result);
- success = result.test_result;
- if (success)
- dqs_gating[byte][gsl_idx][gps_idx] = 1;
- itm_soft_reset(phy);
- }
- }
- set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
- /* dummy reads */
- readl(0xc0000000);
- readl(0xc0000000);
- }
-
- /* re-enable drift compensation */
- /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
- return TEST_PASSED;
-}
-
-/****************************************************************
- * TEST
- ****************************************************************
- */
-static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy,
- char *string, int argc,
- char *argv[])
-{
- u32 rfshctl3 = readl(&ctl->rfshctl3);
- u32 pwrctl = readl(&ctl->pwrctl);
- u32 derateen = readl(&ctl->derateen);
- enum test_result res;
-
- writel(0x0, &ctl->derateen);
- stm32mp1_refresh_disable(ctl);
-
- res = read_dqs_gating(ctl, phy, string);
-
- stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
- writel(derateen, &ctl->derateen);
-
- return res;
-}
-
-static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy,
- char *string, int argc, char *argv[])
-{
- u32 rfshctl3 = readl(&ctl->rfshctl3);
- u32 pwrctl = readl(&ctl->pwrctl);
- u32 derateen = readl(&ctl->derateen);
- enum test_result res;
-
- writel(0x0, &ctl->derateen);
- stm32mp1_refresh_disable(ctl);
-
- res = bit_deskew(ctl, phy, string);
-
- stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
- writel(derateen, &ctl->derateen);
-
- return res;
-}
-
-static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy,
- char *string, int argc, char *argv[])
-{
- u32 rfshctl3 = readl(&ctl->rfshctl3);
- u32 pwrctl = readl(&ctl->pwrctl);
- u32 derateen = readl(&ctl->derateen);
- enum test_result res;
-
- writel(0x0, &ctl->derateen);
- stm32mp1_refresh_disable(ctl);
-
- res = eye_training(ctl, phy, string);
-
- stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
- writel(derateen, &ctl->derateen);
-
- return res;
-}
-
-static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy,
- char *string, int argc, char *argv[])
-{
- int byte;
- u8 nb_bytes = get_nb_bytes(ctl);
-
- for (byte = 0; byte < nb_bytes; byte++)
- display_reg_results(phy, byte);
-
- return TEST_PASSED;
-}
-
-static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
- struct stm32mp1_ddrphy *phy,
- char *string, int argc, char *argv[])
-{
- unsigned long value;
-
- if (argc > 0) {
- if (strict_strtoul(argv[0], 0, &value) < 0) {
- sprintf(string, "invalid nbErr %s", argv[0]);
- return TEST_FAILED;
- }
- BIST_error_max = value;
- }
- if (argc > 1) {
- if (strict_strtoul(argv[1], 0, &value) < 0) {
- sprintf(string, "invalid Seed %s", argv[1]);
- return TEST_FAILED;
- }
- BIST_seed = value;
- }
- printf("Bist.nbErr = %d\n", BIST_error_max);
- if (BIST_seed)
- printf("Bist.Seed = 0x%x\n", BIST_seed);
- else
- printf("Bist.Seed = random\n");
-
- return TEST_PASSED;
-}
-
-/****************************************************************
- * TEST Description
- ****************************************************************
- */
-
-const struct test_desc tuning[] = {
- {do_read_dqs_gating, "Read DQS gating",
- "software read DQS Gating", "", 0 },
- {do_bit_deskew, "Bit de-skew", "", "", 0 },
- {do_eye_training, "Eye Training", "or DQS training", "", 0 },
- {do_display, "Display registers", "", "", 0 },
- {do_bist_config, "Bist config", "[nbErr] [seed]",
- "configure Bist test", 2},
-};
-
-const int tuning_nb = ARRAY_SIZE(tuning);
/*
* Copyright (C) 2019-2020 Linaro Limited
*/
+
+#define LOG_CATEGORY UCLASS_RESET
+
#include <common.h>
#include <dm.h>
#include <errno.h>
*/
#define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
#define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
+#define GQSPI_IXR_TXFIFOEMPTY_MASK 0x00000100 /* QSPI TX FIFO is Empty */
#define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
#define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
#define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */
debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
- /* Dummy generic FIFO entry */
- zynqmp_qspi_fill_gen_fifo(priv, 0);
-
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
}
}
+ ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
+ GQSPI_TIMEOUT, 1);
+ if (ret) {
+ printf("%s: Timeout\n", __func__);
+ return ret;
+ }
+
priv->tx_buf += len;
return 0;
}
#define OPTEE_MSG_ATTR_CACHE_PREDEFINED 0
/*
- * Same values as TEE_LOGIN_* from TEE Internal API
- */
-#define OPTEE_MSG_LOGIN_PUBLIC 0x00000000
-#define OPTEE_MSG_LOGIN_USER 0x00000001
-#define OPTEE_MSG_LOGIN_GROUP 0x00000002
-#define OPTEE_MSG_LOGIN_APPLICATION 0x00000004
-#define OPTEE_MSG_LOGIN_APPLICATION_USER 0x00000005
-#define OPTEE_MSG_LOGIN_APPLICATION_GROUP 0x00000006
-
-/*
* Page size used in non-contiguous buffer entries
*/
#define OPTEE_MSG_NONCONTIG_PAGE_SIZE 4096
* parameters to pass the following information:
* param[0].u.value.a-b uuid of Trusted Application
* param[1].u.value.a-b uuid of Client
- * param[1].u.value.c Login class of client OPTEE_MSG_LOGIN_*
+ * param[1].u.value.c Login class of client TEE_LOGIN_*
*
* OPTEE_MSG_CMD_INVOKE_COMMAND invokes a command a previously opened
* session to a Trusted Application. struct optee_msg_arg::func is Trusted
*/
static int tpm_atmel_twi_get_desc(struct udevice *dev, char *buf, int size)
{
- return 0;
+ if (size < 50)
+ return -ENOSPC;
+
+ return snprintf(buf, size, "Atmel AT97SC3204T I2C 1.2 TPM (%s)", dev->name);
}
/*
print_buffer(0, (void *)sendbuf, 1, send_size, 0);
#endif
-#if !CONFIG_IS_ENABLED(DM_I2C)
- res = i2c_write(0x29, 0, 0, (uchar *)sendbuf, send_size);
-#else
res = dm_i2c_write(dev, 0, sendbuf, send_size);
-#endif
if (res) {
printf("i2c_write returned %d\n", res);
return -1;
}
start = get_timer(0);
-#if !CONFIG_IS_ENABLED(DM_I2C)
- while ((res = i2c_read(0x29, 0, 0, recvbuf, 10)))
-#else
+
while ((res = dm_i2c_read(dev, 0, recvbuf, 10)))
-#endif
{
/* TODO Use TIS_TIMEOUT from tpm_tis_infineon.h */
if (get_timer(start) > ATMEL_TPM_TIMEOUT_MS) {
return -1;
} else {
*recv_len = hdr_recv_len;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- res = i2c_read(0x29, 0, 0, recvbuf, *recv_len);
-#else
res = dm_i2c_read(dev, 0, recvbuf, *recv_len);
-#endif
-
}
}
if (res) {
- printf("i2c_read returned %d (rlen=%d)\n", res, *recv_len);
+ printf("i2c_read returned %d (rlen=%zu)\n", res, *recv_len);
#ifdef DEBUG
print_buffer(0, recvbuf, 1, *recv_len, 0);
#endif
static int tpm_atmel_twi_probe(struct udevice *dev)
{
+ i2c_set_chip_offset_len(dev, 0);
return 0;
}
static const struct udevice_id cdns_ti_of_match[] = {
{ .compatible = "ti,j721e-usb", },
+ { .compatible = "ti,am64-usb", },
{},
};
uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
CONFIG_VIDEO_STM32_MAX_YRES *
(CONFIG_VIDEO_STM32_MAX_BPP >> 3);
- dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size);
+ /* align framebuffer on kernel MMU_SECTION_SIZE = max 2MB for LPAE */
+ uc_plat->align = SZ_2M;
+ dev_dbg(dev, "frame buffer max size %d bytes align %x\n",
+ uc_plat->size, uc_plat->align);
return 0;
}
}
}
+bool video_is_active(void)
+{
+ struct udevice *dev;
+
+ for (uclass_find_first_device(UCLASS_VIDEO, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ if (device_active(dev))
+ return true;
+ }
+
+ return false;
+}
+
int video_get_xsize(struct udevice *dev)
{
struct video_priv *priv = dev_get_uclass_priv(dev);
config ENV_SUPPORT
def_bool y
+config ENV_SOURCE_FILE
+ string "Environment file to use"
+ default ""
+ help
+ This sets the basename to use to generate the default environment.
+ This a text file as described in doc/usage/environment.rst
+
+ The file must be in the board directory and have a .env extension, so
+ the resulting filename is typically
+ board/<vendor>/<board>/<CONFIG_ENV_SOURCE_FILE>.env
+
+ If the file is not present, an error is produced.
+
+ If this CONFIG is empty, U-Boot uses CONFIG SYS_BOARD as a default, if
+ the file board/<vendor>/<board>/<SYS_BOARD>.env exists. Otherwise the
+ environment is assumed to come from the ad-hoc
+ CONFIG_EXTRA_ENV_SETTINGS #define
+
config SAVEENV
def_bool y if CMD_SAVEENV
1 : 0;
}
+bool env_get_autostart(void)
+{
+ return env_get_yesno("autostart") == 1;
+}
+
/*
* Look up the variable from the default environment
*/
#endif
#define DEFAULT_ENV_INSTANCE_EMBEDDED
+#include <config.h>
#include <env_default.h>
#ifdef CONFIG_ENV_ADDR_REDUND
char *const argv[]);
char *usage; /* Usage message (short) */
#ifdef CONFIG_SYS_LONGHELP
- char *help; /* Help message (long) */
+ const char *help; /* Help message (long) */
#endif
#ifdef CONFIG_AUTO_COMPLETE
/* do auto completion on the arguments */
"run bootcmd_${target}; " \
"done\0"
-#ifndef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
-#endif
-
#endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
-#define CONFIG_SYS_BR1_PRELIM 0
-#define CONFIG_SYS_OR1_PRELIM 0
-#define CONFIG_SYS_BR2_PRELIM 0x30000001
-#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
-#define CONFIG_SYS_BR3_PRELIM 0
-#define CONFIG_SYS_OR3_PRELIM 0
-#define CONFIG_SYS_BR4_PRELIM 0
-#define CONFIG_SYS_OR4_PRELIM 0
-#define CONFIG_SYS_BR5_PRELIM 0
-#define CONFIG_SYS_OR5_PRELIM 0
-#define CONFIG_SYS_BR6_PRELIM 0
-#define CONFIG_SYS_OR6_PRELIM 0
-#define CONFIG_SYS_BR7_PRELIM 0x00000701
-#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
-
-/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_PACNT 0x00000000
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
-#define CONFIG_BOOTCOMMAND "bootm ffe40000"
-
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_RETRY_COUNT 5
# define CONFIG_OVERWRITE_ETHADDR_ONCE
"$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-#define NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
/*
* 32KB, 8-bit wide for ADS config reg
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8000801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_SYS_INIT_RAM_LOCK 1
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0"
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_BR0_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
- | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
-
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#else
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_BR3_PRELIM \
- (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
"fdtaddr=1e00000\0" \
"fdtfile=mpc8548cds.dtb\0"
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
/*
* 32KB, 8-bit wide for ADS config reg
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8000801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_SYS_INIT_RAM_LOCK 1
"fdtaddr=400000\0" \
"fdtfile=mpc8560ads.dtb\0"
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND
-
#endif /* __CONFIG_H */
"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
#endif
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND RAMBOOTCOMMAND
-
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */
#define CPLD_BASE_PHYS CPLD_BASE
#endif
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
"bdev=sda3\0"
-#define HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND HDBOOT
-
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */
"fdtaddr=1e00000\0" \
"bdev=sda3\0"
-#define LINUXBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
-
#include <asm/fsl_secure_boot.h>
#endif /* __T1024RDB_H */
"fdtfile=" __stringify(FDTFILE) "\0" \
"bdev=sda3\0"
-#define LINUXBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
-
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */
"cpu 7 release 0x01000000 - - -;" \
"go 0x01000000"
-#define LINUXBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
-
#include <asm/fsl_secure_boot.h>
#endif /* __T208xQDS_H */
"cpu 7 release 0x01000000 - - -;" \
"go 0x01000000"
-#define LINUXBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
-
#include <asm/fsl_secure_boot.h>
#endif /* __T2080RDB_H */
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define LINUXBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
-
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */
"echo WARNING: Could not determine device tree to use; fi; \0"
#endif
-#define CONFIG_BOOTCOMMAND \
- "run findfdt;" \
- "run mmcboot;" \
- "run nandboot;" \
- "run netboot;"
-
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#if defined CONFIG_SHC_NETBOOT
/* Network Boot */
-# define CONFIG_BOOTCOMMAND \
- "run fusecmd; " \
- "if run netboot; then " \
- "echo Booting from network; " \
- "else " \
- "echo ERROR: Cannot boot from network!; " \
- "panic; " \
- "fi; "
#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */
/* SD-Card Boot */
-# define CONFIG_BOOTCOMMAND \
- "if mmc dev 0; mmc rescan; then " \
- "run sd_setup; " \
- "else " \
- "echo ERROR: SD/MMC-Card not detected!; " \
- "panic; " \
- "fi; " \
- "if run loaduimage; then " \
- "echo Bootable SD/MMC-Card inserted, booting from it!; " \
- "run mmcboot; " \
- "else " \
- "echo ERROR: Unable to load uImage from SD/MMC-Card!; " \
- "panic; " \
- "fi; "
#elif defined CONFIG_SHC_ICT
/* ICT adapter boots only u-boot and does HW partitioning */
-# define CONFIG_BOOTCOMMAND \
- "if mmc dev 0; mmc rescan; then " \
- "run sd_setup; " \
- "else " \
- "echo ERROR: SD/MMC-Card not detected!; " \
- "panic; " \
- "fi; " \
- "run fusecmd; "
#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */
/* Regular Boot from internal eMMC */
-# define CONFIG_BOOTCOMMAND \
- "if mmc dev 1; mmc rescan; then " \
- "run emmc_setup; " \
- "else " \
- "echo ERROR: eMMC device not detected!; " \
- "panic; " \
- "fi; " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else " \
- "echo ERROR Unable to load uImage from eMMC!; " \
- "echo Performing Rollback!; " \
- "setenv _active_ ${active_root}; " \
- "setenv _inactive_ ${inactive_root}; " \
- "setenv active_root ${_inactive_}; " \
- "setenv inactive_root ${_active_}; " \
- "saveenv; " \
- "reset; " \
- "fi; "
#endif /* Regular Boot */
"nand read ${fdtaddr} aa0000 80000; " \
"bootm ${loadaddr} - ${fdtaddr}\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device $mmcdev; " \
- "if run loadbootenv; then " \
- "run importbootenv; " \
- "fi; " \
- "echo Checking if uenvcmd is set ...; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
- "fi; " \
- "echo Running default loadimage ...; " \
- "setenv bootfile zImage; " \
- "if run loadimage; then " \
- "run loadfdt; " \
- "run mmcboot; " \
- "fi; " \
- "else run nandboot; fi"
-
/* Miscellaneous configurable options */
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_MCFTMR
#define CONFIG_SYS_UART_PORT 0
-#define CONFIG_BOOTCOMMAND "bootm ffc20000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"upgrade_uboot=loady; " \
"protect off 0xffc00000 0xffc1ffff; " \
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
-#define CONFIG_BOOTCOMMAND "sf probe;" \
- "mtdparts default;" \
- "bootm 0x9f650000"
-
/* Miscellaneous configurable options */
/*
*/
#define CONFIG_SYS_NS16550_CLK 25000000
-#define CONFIG_BOOTCOMMAND "sf probe;" \
- "mtdparts default;" \
- "bootm 0x9f680000"
-
/* Miscellaneous configurable options */
/*
*/
#define CONFIG_SYS_NS16550_CLK 25000000
-#define CONFIG_BOOTCOMMAND "sf probe;" \
- "mtdparts default;" \
- "bootm 0x9f060000"
-
#define CONFIG_ENV_SPI_MAX_HZ 25000000
/* Miscellaneous configurable options */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=yes\0" \
- "spi_dma=yes\0" \
- ""
-
#endif /* __AST_COMMON_CONFIG_H */
* by external update.c; This is not included in mainline because
* it needs non-blocking CFI routines.
*/
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */
-#else
-#if ASTRO_V532
-#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
- "run xilinxload&&run alteraload&&bootm 0x80000;"\
- "update;reset"
-#else
-#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
- "run xilinxload&&bootm 0x80000;update;reset"
-#endif
-#endif
#define CONFIG_FPGA_COUNT 1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_BOOTP_BOOTFILESIZE
#ifdef CONFIG_SD_BOOT
-#define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \
- "setenv dtb_name at91-${board_name}.dtb; " \
- "fi; " \
- "fatload mmc 0:1 0x21000000 ${dtb_name}; " \
- "fatload mmc 0:1 0x22000000 zImage; " \
- "bootz 0x22000000 - 0x21000000"
-
#else
#ifdef CONFIG_NAND_BOOT
/* u-boot env in nand flash */
-#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
- "nand read 0x22000000 0x200000 0x600000;" \
- "bootz 0x22000000 - 0x21000000"
#elif CONFIG_SPI_BOOT
/* u-boot env in serial flash, by default is bus 0 and cs 0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x21000000 0x60000 0xc000; " \
- "sf read 0x22000000 0x6c000 0x394000; " \
- "bootz 0x22000000 - 0x21000000"
-#elif CONFIG_QSPI_BOOT
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x21000000 0x180000 0x80000; " \
- "sf read 0x22000000 0x200000 0x600000; " \
- "bootz 0x22000000 - 0x21000000"
#endif
#endif
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
-
-#elif CONFIG_SYS_USE_DATAFLASH_CS1
-
-#define CONFIG_BOOTCOMMAND "sf probe 0:1; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
-
#elif defined(CONFIG_SYS_USE_NANDFLASH)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
/* For FAT system, most cases it should be in the reserved sector */
-
-#define CONFIG_BOOTCOMMAND \
- "fatload mmc 0:1 0x22000000 uImage; bootm"
#endif
#endif
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
#elif CONFIG_SYS_USE_DATAFLASH_CS3
/* bootstrap + u-boot + env + linux in dataflash on CS3 */
-#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
#else /* CONFIG_SYS_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#endif
#endif
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#endif
#endif
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
-
-#define CONFIG_BOOTCOMMAND \
- "nand read 0x70000000 0x200000 0x300000;" \
- "bootm 0x70000000"
#elif CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in mmc */
-
-#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
- "fatload mmc 0:1 0x72000000 zImage; " \
- "bootz 0x72000000 - 0x71000000"
#endif
/* Defines for SPL */
#ifdef CONFIG_SPI_BOOT
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
- "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \
- "bootm 0x22000000"
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
- "nand read 0x21000000 0x180000 0x080000;" \
- "nand read 0x22000000 0x200000 0x400000;" \
- "bootm 0x22000000 - 0x21000000"
-
-#else /* CONFIG_SD_BOOT */
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \
- "fatload mmc 0:1 0x21000000 dtb;" \
- "fatload mmc 0:1 0x22000000 uImage;" \
- "bootm 0x22000000 - 0x21000000"
-
#endif
/* SPL */
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \
- "nand read 0x21000000 0x180000 0x80000; " \
- "bootz 0x22000000 - 0x21000000"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
-#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \
- "fatload mmc 0:1 0x22000000 zImage; " \
- "bootz 0x22000000 - 0x21000000"
#endif
#endif
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read " \
- "0x22000000 0x200000 0x600000; " \
- "nand read 0x21000000 0x180000 0x20000; " \
- "bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_SPI_BOOT)
/* bootstrap + u-boot + env + linux in spi flash */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x100000 0x300000; " \
- "bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_DATAFLASH)
/* bootstrap + u-boot + env + linux in data flash */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
#endif
/* SPL */
/*DFUARGS*/
#endif
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "run usbboot;" \
- "run mmcboot;" \
- "setenv mmcdev 1; " \
- "setenv bootpart 1:2; " \
- "run mmcboot;" \
- "run nandboot;"
-
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
"setenv bl_flash_pending_rfs_imgs;" \
"fi; \0"
-#define CONFIG_BOOTCOMMAND "run flash_pending_rfs_imgs;" \
- "run fastboot_nitro && "\
- "run bootcmd_mmc_fits || "\
- "run bootcmd_usb || "\
- "run bootcmd_pxe"
-
/* Flashing commands */
#define TFTP_QSPI_PARAM \
"fip_qspi_addr=0x0\0"\
"booti; " \
"fi;\0"
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
#endif /* __BEACON_RZG2M_H */
"preboot=" BK4_NET_INIT \
"if ${ncenable}; then run if_netconsole start_netconsole; fi\0"
-/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
-#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \
- "run manage_userdata; "
-
/* Enable PREBOOT variable */
/* Set ARP_TIMEOUT to 500ms */
#define CONFIG_BOARD_SIZE_LIMIT 520192
/* boot command, including the target-defined one if any */
-#define CONFIG_BOOTCOMMAND BK4_BOOTCOMMAND "run bootcmd_nand"
/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0"
#endif /* !CONFIG_SPL_BUILD*/
-#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default"
-
/* Environment */
#endif /* __CONFIG_BRXRE1_H__ */
ENV_EMMC \
ENV_NET
-#define CONFIG_BOOTCOMMAND \
- "if usrbutton; then " \
- "run flash_self_test; " \
- "reset; " \
- "fi;" \
- "run flash_self;" \
- "reset;"
-
/* Default location for tftp and bootm */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
"booti; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
"nand read ${loadaddr} NAND.kernel; " \
"bootz ${loadaddr} - ${fdt_addr}\0"
-#define CONFIG_BOOTCOMMAND \
- "run mmcboot; " \
- "run nandboot; " \
- "run netboot"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"fdt_addr=0x87800000\0" \
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_BOOTCOMMAND \
- "tpm init; tpm startup TPM2_SU_CLEAR; " \
- "read mmc 0:2 100000 0 80; setexpr loader *001004f0; " \
- "setexpr size *00100518; setexpr blocks $size / 200; " \
- "read mmc 0:2 100000 80 $blocks; setexpr setup $loader - 1000; " \
- "setexpr cmdline_ptr $loader - 2000; " \
- "setexpr.s cmdline *$cmdline_ptr; " \
- "setexpr cmdline gsub %U \\\\${uuid}; " \
- "if part uuid mmc 0:2 uuid; then " \
- "zboot start 100000 0 0 0 $setup cmdline; " \
- "zboot load; zboot setup; zboot dump; zboot go;" \
- "fi"
-
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
#undef CONFIG_SYS_AUTOLOAD
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_BOOTCOMMAND
#define CONFIG_SYS_AUTOLOAD "no"
"emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \
"emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \
-#define CONFIG_BOOTCOMMAND \
- "echo SD boot attempt ...; run sdbootscript; run sdboot; " \
- "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
- "echo USB boot attempt ...; run usbbootscript; "
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
MMCARGS \
NANDARGS
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_TIMESTAMP
"load mmc 1 ${fdtaddr} ${fdtfile} && " \
"bootz ${loadaddr} - ${fdtaddr}\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev 0; " \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "fi; " \
- "fi; " \
- "mmc dev 1; " \
- "if mmc rescan; then " \
- "run emmcboot; " \
- "fi;"
-
/* SPL defines. */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#if 0
-#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
enter a valid image address in flash */
/* User network settings */
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
- * Memory bank definitions
- *
- * Please refer also to Motorola Coldfire user manual - Chapter XXX
- * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
- */
-#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
-
-#define CONFIG_SYS_BR1_PRELIM 0
-#define CONFIG_SYS_OR1_PRELIM 0
-
-#define CONFIG_SYS_BR2_PRELIM 0
-#define CONFIG_SYS_OR2_PRELIM 0
-
-#define CONFIG_SYS_BR3_PRELIM 0
-#define CONFIG_SYS_OR3_PRELIM 0
-
-#define CONFIG_SYS_BR4_PRELIM 0
-#define CONFIG_SYS_OR4_PRELIM 0
-
-#define CONFIG_SYS_BR5_PRELIM 0
-#define CONFIG_SYS_OR5_PRELIM 0
-
-#define CONFIG_SYS_BR6_PRELIM 0
-#define CONFIG_SYS_OR6_PRELIM 0
-
-#define CONFIG_SYS_BR7_PRELIM 0x00000701
-#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
-
-/*-----------------------------------------------------------------------
* LED config
*/
#define LED_STAT_0 0xffff /*all LEDs off*/
#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND)
/* Run Distro Boot script if ubiboot fails */
-#define CONFIG_BOOTCOMMAND "run ubiboot || run distro_bootcmd;"
#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5"
#define MODULE_EXTRA_ENV_SETTINGS \
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
-#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \
- "run distro_bootcmd;"
#define MODULE_EXTRA_ENV_SETTINGS \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
UBI_BOOTCMD
/*
* Environment settings
*/
-#define CONFIG_BOOTCOMMAND \
- "if fatload mmc 0 0xa0000000 uImage; then " \
- "bootm 0xa0000000; " \
- "fi; " \
- "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
- "bootm 0xa0000000; " \
- "fi; " \
- "bootm 0xc0000;"
#define CONFIG_TIMESTAMP
/*
"ubi read ${fdt_addr_r} dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
-#define CONFIG_BOOTCOMMAND "run ubiboot || run distro_bootcmd;"
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \
- "load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
- "run boot"
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel-ver=4.4.0-22\0" \
" gpio clear ${gpio1}; gpio set ${gpio2};" \
" fi; sleep 0.12; done\0"
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
- "console=${consoledev},${baudrate} ${othbootargs}; " \
- "tftpboot ${bootfile_addr} ${bootfile}; " \
- "bootm ${bootfile_addr}"
-
-#define MMCBOOTCOMMAND \
- "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
- "console=${consoledev},${baudrate} ${othbootargs}; " \
- "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
- "bootm ${bootfile_addr}"
-
-#define CONFIG_BOOTCOMMAND \
- "if env exists keyprogram; then;" \
- " setenv keyprogram; run nfsboot;" \
- " fi;" \
- " run dobootfail"
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
#define PIXIS_BASE_PHYS PIXIS_BASE
#endif
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
"fdtfile=p4080ds/p4080ds.dtb\0" \
"bdev=sda3\0"
-#define HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND HDBOOT
-
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */
/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_BOOTCOMMAND \
- "nand read 0x70000000 0x200000 0x300000;" \
- "bootm 0x70000000"
-
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
#define CONFIG_SPL_STACK (SZ_16K)
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_BOOTCOMMAND \
- "run envboot; " \
- "run mmcboot; "
-
#define DEFAULT_LINUX_BOOT_ENV \
"loadaddr=0xc0700000\0" \
"fdtaddr=0xc0600000\0" \
"fit_addr=0x82000000\0" \
ENV_MMC
-#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
* Environment
*/
-#define CONFIG_BOOTCOMMAND \
- "dhcp; " \
- "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
- "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
- "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
- "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
- "bootm ${loadaddr} - ${dtbaddr}"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=no\0" \
"ethaddr=00:01:90:00:C0:81\0" \
"fi; " \
"else run nandboot; fi\0"
-#define CONFIG_BOOTCOMMAND "run autoboot"
-
/* Boot Argument Buffer Size */
/* Defines for SPL */
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \
- "load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
- "run boot"
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel-ver=4.4.0-24\0" \
"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
BOOTENV
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 2) \
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#ifndef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \
- "run recovery;" \
- "else if test ${BOOT_FROM} = FACTORY; then " \
- "run factory_nfs;" \
- "else " \
- "run boot_mmc;" \
- "fi;fi"
-#endif
-
#define PARTS_DEFAULT \
/* Linux partitions */ \
"partitions=" \
"altbootcmd=run recovery\0" \
"bootdelay=1\0" \
"baudrate=115200\0" \
- "bootcmd=" CONFIG_BOOTCOMMAND "\0" \
"ethact=FEC\0" \
"netdev=eth0\0" \
"boot_os=y\0" \
"setenv bootenvrootfstype ${nandrootfstype}; " \
"setenv bootenvloadimage ${nandloadimage}\0"
-#define CONFIG_BOOTCOMMAND \
- "if test -n ${bootenv} && usb start; then " \
- "if run loadbootenv; then " \
- "echo Loaded environment ${bootenv} from usb;" \
- "run importbootenv;" \
- "fi;" \
- "if test -n ${bootenvcmd}; then " \
- "echo Running bootenvcmd ...;" \
- "run bootenvcmd;" \
- "fi;" \
- "fi;" \
- "run setnandbootenv subbootcmd;"
-
#endif /* _CONFIG_DNS325_H */
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:root; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x1100000 ${initrd}; " \
- "bootm 0x800000 0x1100000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
-
-#define CONFIG_BOOTCOMMAND \
-"if dfubutton; then " \
- "run dfu_start; " \
- "reset; " \
-"fi;" \
-"run nand_boot;" \
-"run nand_boot_backup;" \
-"reset;"
-
-#else
-
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#endif /* ! __CONFIG_DRACO_H */
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "setenv ethact ethernet-controller@72000; " \
- "${x_bootcmd_ethernet}; setenv ethact ethernet-controller@76000; " \
- "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"x_bootcmd_ethernet=ping 192.168.2.1\0" \
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
- "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"x_bootcmd_ethernet=ping 192.168.1.2\0" \
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* Default Environment */
-#define CONFIG_BOOTCOMMAND \
- "sf probe; " \
- "sf read ${loadaddr} 0xd0000 0x2d0000; " \
- "sf read ${ramdisk_addr_r} 0x3a0000 0x430000; " \
- "bootm ${loadaddr} ${ramdisk_addr_r}"
#define CONFIG_EXTRA_ENV_SETTINGS \
"initrd_high=0xffffffff\0" \
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
-#define CONFIG_BOOTCOMMAND "printenv"
-
/*----------------------------------------------------------------------*
* Options *
*----------------------------------------------------------------------*/
*/
#ifdef CONFIG_IDE
#define __io
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
CONFIG_ENV_SETTINGS_V2 \
CONFIG_ENV_SETTINGS_NAND_V2
-
-#ifndef CONFIG_RESTORE_FLASH
-
-#define CONFIG_BOOTCOMMAND \
-"if dfubutton; then " \
- "run dfu_start; " \
- "reset; " \
-"fi;" \
-"run nand_boot;" \
-"run nand_boot_backup;" \
-"reset;"
-
-
-#else
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
-#endif
#endif /* CONFIG_SPL_BUILD */
#endif /* ! __CONFIG_ETAMIN_H */
/* File systems */
/* Boot command */
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
- "sf read 0x22000000 0xc6000 0x294000; " \
- "bootm 0x22000000"
/* Misc. u-boot settings */
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+/* Memory Info */
+#define CONFIG_SYS_LOAD_ADDR 0x83000000
+
+/* Misc */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ""
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+/* Memory Info */
+#define CONFIG_SYS_LOAD_ADDR 0x83000000
+
+/* Misc */
+#define STR_HELPER(s) #s
+#define STR(s) STR_HELPER(s)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootspi=fdt addr 20100000 && fdt header get fitsize totalsize && " \
+ "cp.b 20100000 ${loadaddr} ${fitsize} && bootm; " \
+ "echo Error loading kernel FIT image\0" \
+ ""
+
#endif /* __CONFIG_H */
"serverip=172.16.12.69\0" \
""
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "sf probe;" \
- "sf read 0x62000000 0x140800 0x500000;" \
- "dcache off;" \
- "go 0x62000000"
-
#endif
#define LCD_BPP LCD_COLOR16
#endif
-/* Enable keyboard */
-#define CONFIG_KEYBOARD
-
#endif
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp ${kernel_addr} $bootfile;" \
- "tftp ${fdt_addr} $fdtfile;" \
- "bootm ${kernel_addr} - ${fdt_addr}"
-
-#define MMCBOOTCOMMAND \
- "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
- "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
- "bootm ${kernel_addr} - ${fdt_addr}"
-
-#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
-
#endif /* __CONFIG_H */
"run showsplashscreen; sleep 1; " \
"run doboot; run failbootcmd;\0" \
-#define CONFIG_BOOTCOMMAND "run tryboot;"
-
#endif /* __GE_B1X5V2_CONFIG_H */
"run doboot; " \
"run failbootcmd\0" \
-#define MMCBOOTCOMMAND \
- "run doquiet; " \
- "run tryboot; " \
-
-#ifdef CONFIG_CMD_NFS
-#define CONFIG_BOOTCOMMAND NETWORKBOOTCOMMAND
-#else
-#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
-#endif
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:root; " \
- "ubifsload 0x800000 ${kernel}; " \
- "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"fi\0"
#endif
-#define CONFIG_BOOTCOMMAND \
- "for btype in ${bootdevs}; do " \
- "echo; echo Attempting ${btype} boot...; " \
- "if run ${btype}_boot; then; fi; " \
- "done"
-
#endif /* __CONFIG_H */
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part rootfs; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
#define CONFIG_LOADS_ECHO
#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTCOMMAND "run boot_cramfs"
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_JFFS2_NAND
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"\0"
-#define NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setipargs;run addmtd;" \
- "tftp ${loadaddr} ${bootfile};" \
- "tftp ${fdtaddr} ${fdtfile};" \
- "fdt addr ${fdtaddr};" \
- "bootm ${loadaddr} - ${fdtaddr}"
-
/* UBI Support */
#endif /* __CONFIG_H */
"run nandboot; " \
"fi\0"
-#define CONFIG_BOOTCOMMAND "run $modeboot"
-
/* Miscellaneous configurable options */
#ifdef CONFIG_MX6UL
"fi; " \
"fi; " \
"else run netboot; fi"
-#define CONFIG_BOOTCOMMAND \
- "run autoboot"
#define CONFIG_ARP_TIMEOUT 200UL
#undef CONFIG_SYS_AUTOLOAD
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_BOOTCOMMAND
/*
* Use:
"bootz ${loadaddr} - ${fdt_addr}; " \
"\0"
-#define CONFIG_BOOTCOMMAND "run boot${boot-mode}"
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
"fi; " \
"fi;\0"
-#ifndef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "fi;"
-#endif
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
"fi; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "fi;"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
"run loadramdisk; run ramargs; " \
"booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
"booti; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
"fi;" \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if test ${sec_boot} = yes; then " \
- "if run loadcntr; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
"booti; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
"fi;" \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if test ${sec_boot} = yes; then " \
- "if run loadcntr; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTCOMMAND ""
-
/* Flash settings */
#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
-#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_IPADDR 192.168.1.104
#define CONFIG_BOOTFILE "uImage"
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
-#ifndef CONFIG_TI_SECURE_DEVICE
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "run envboot; " \
- "run init_${boot}; " \
- "run get_mon_${boot} run_mon; " \
- "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \
- "run get_kern_${boot}; " \
- "run init_fw_rd_${boot}; " \
- "run get_fdt_${boot}; " \
- "run run_kern"
-#else
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "run envboot; " \
- "run run_mon_hs; " \
- "run init_${boot}; " \
- "run get_fit_${boot}; " \
- "bootm ${addr_fit}#${name_fdt}"
-#endif
-
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
"bootm ${loadaddr}#${fit_config}\0" \
BOOTENV
-#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
"bootm ${loadaddr}#${fit_config}\0" \
BOOTENV
-#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "dhcp && run netconsole; " \
- "if run usbload || run diskload; then bootm; fi"
#define CONFIG_EXTRA_ENV_SETTINGS \
"stdin=serial\0" \
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_SETUP_INITRD_TAG
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan; then " \
- "if run loadbootscr; then " \
- "run bootscript; " \
- "else " \
- "if run loadbootenv; then " \
- "echo Loaded env from ${bootenvfile};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadimage; then " \
- "run mmcargs; " \
- "if run loadfdt; then " \
- "echo Using ${fdtfile}...;" \
- "run fdtfixup; " \
- "run fdtboot; "\
- "fi; " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi; "\
- "run flashargs; " \
- "run flashboot"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootenvfile=uEnv.txt\0" \
"fdtfile=da850-lego-ev3.dtb\0" \
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0"
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
-#else
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#endif
#endif
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
"kernel_size=0x2800000\0" \
"bootm_size=0x10000000\0" \
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
"$kernel_start $kernel_size && "\
"bootm $kernel_load"
-#else
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
- "$kernel_start $kernel_size && "\
- "bootm $kernel_load"
#endif
/* Monitor Command Prompt */
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
#endif
#endif /* __LS1012ARDB_H__ */
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\
"env exists secureboot && esbc_halt;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\
- "env exists secureboot && esbc_halt;"
#endif
#include <asm/fsl_secure_boot.h>
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0"
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
- "env exists secureboot && esbc_halt;"
#endif
#include <asm/fsl_secure_boot.h>
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0"
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
- "env exists secureboot && esbc_halt;"
#endif
#include <asm/fsl_secure_boot.h>
"bootm $load_addr#$board\0"
#endif
-#undef CONFIG_BOOTCOMMAND
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
- "env exists secureboot && esbc_halt;"
-#endif
-
/*
* Miscellaneous configurable options
*/
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
-#undef CONFIG_BOOTCOMMAND
-
#define XSPI_NOR_BOOTCOMMAND \
"run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"
"bootm $load_addr#$board\0"
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
"env exists secureboot && esbc_halt;"
#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
"env exists secureboot && esbc_halt;"
-#else
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#endif
#endif
#endif
#endif
-#undef CONFIG_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"
#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
* Environment
*/
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
"env exists secureboot && esbc_halt;;"
"env exists secureboot && esbc_halt;;"
#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
"env exists secureboot && esbc_halt;;"
-#else
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#endif
#endif
#include <asm/fsl_secure_boot.h>
#endif
#ifndef SPL_NO_MISC
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"
#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
"env exists secureboot && esbc_halt;"
-#else
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#endif
#endif
#endif
"console=ttyAMA0,38400n8\0" \
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
-
-#ifndef CONFIG_TFABOOT
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
- "sf read 0x80001000 0xd00000 0x100000;"\
- " fsl_mc lazyapply dpl 0x80001000 &&" \
- " sf read $kernel_load $kernel_start" \
- " $kernel_size && bootm $kernel_load"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
- " fsl_mc lazyapply dpl 0x80001000 &&" \
- " mmc read $kernel_load $kernel_start" \
- " $kernel_size && bootm $kernel_load"
-#else /* NOR BOOT*/
-#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
- " cp.b $kernel_start $kernel_load" \
- " $kernel_size && bootm $kernel_load"
-#endif
-#endif /* CONFIG_TFABOOT */
#endif
/* Monitor Command Prompt */
"bootm $load_addr#$BOARD\0"
#endif /* CONFIG_TFABOOT */
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND \
"sf read 0x80001000 0xd00000 0x100000;" \
#else
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
-#define CONFIG_BOOTCOMMAND \
- "sf read 0x80001000 0xd00000 0x100000;" \
- "env exists mcinitcmd && env exists secureboot " \
- " && sf read 0x806C0000 0x6C0000 0x100000 " \
- "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
- "&& fsl_mc lazyapply dpl 0x80001000;" \
- "run distro_bootcmd;run qspi_bootcmd;" \
- "env exists secureboot && esbc_halt;"
/* Try to boot an on-SD kernel first, then do normal distro boot */
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND \
- "env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80001000 0x6800 0x800; " \
- "env exists mcinitcmd && env exists secureboot " \
- " && mmc read 0x806C0000 0x3600 0x20 " \
- "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
- "&& fsl_mc lazyapply dpl 0x80001000;" \
- "run distro_bootcmd;run sd_bootcmd;" \
- "env exists secureboot && esbc_halt;"
#endif
#endif /* CONFIG_TFABOOT */
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
-#ifndef CONFIG_TFABOOT
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
- " fsl_mc apply dpl 0x80200000 &&" \
- " mmc read $kernel_load $kernel_start" \
- " $kernel_size && bootm $kernel_load"
-#else
-#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
- " cp.b $kernel_start $kernel_load" \
- " $kernel_size && bootm $kernel_load"
-#endif
-#endif
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 64 /* max command args */
"run distro_bootcmd;run nor_bootcmd; " \
"env exists secureboot && esbc_halt;"
#else
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_QSPI_BOOT
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
-#define CONFIG_BOOTCOMMAND \
- "sf probe 0:0; " \
- "sf read 0x806c0000 0x6c0000 0x40000; " \
- "env exists mcinitcmd && env exists secureboot "\
- "&& esbc_validate 0x806C0000; " \
- "sf read 0x80d00000 0xd00000 0x100000; " \
- "env exists mcinitcmd && " \
- "fsl_mc lazyapply dpl 0x80d00000; " \
- "run distro_bootcmd;run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
/* Try to boot an on-SD kernel first, then do normal distro boot */
-#define CONFIG_BOOTCOMMAND \
- "env exists mcinitcmd && env exists secureboot "\
- "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
- "&& esbc_validate $load_addr; " \
- "env exists mcinitcmd && run mcinitcmd " \
- "&& mmc read 0x88000000 0x6800 0x800 " \
- "&& fsl_mc lazyapply dpl 0x88000000; " \
- "run distro_bootcmd;run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
#else
/* Try to boot an on-NOR kernel first, then do normal distro boot */
-#define CONFIG_BOOTCOMMAND \
- "env exists mcinitcmd && env exists secureboot "\
- "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
- "&& fsl_mc lazyapply dpl 0x580d00000;" \
- "run distro_bootcmd;run nor_bootcmd; " \
- "env exists secureboot && esbc_halt;"
#endif
#endif
#define CONFIG_SYS_FLASH_BASE 0x20000000
/* DDR */
-#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */
* Boot Linux
*/
#define CONFIG_BOOTFILE "boot/fitImage"
-#define CONFIG_BOOTCOMMAND "run mmc_mmc"
/*
* NAND SPL
"echo Fastboot forced by usb rom boot;" \
"setenv run_fastboot 1;" \
"fi;" \
- "if gpt verify mmc ${mmcdev} ${partitions}; then; " \
- "else " \
- "echo Broken MMC partition scheme;" \
- "setenv run_fastboot 1;" \
- "fi;" \
- "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
- CONTROL_PARTITION "; then " \
- "if bcb test command = bootonce-bootloader; then " \
- "echo BCB: Bootloader boot...; " \
- "bcb clear command; bcb store; " \
+ "if test \"${run_fastboot}\" -eq 0; then " \
+ "if gpt verify mmc ${mmcdev} ${partitions}; then; " \
+ "else " \
+ "echo Broken MMC partition scheme;" \
"setenv run_fastboot 1;" \
"fi; " \
- "if bcb test command = boot-fastboot; then " \
- "echo BCB: fastboot userspace boot...; " \
- "setenv force_recovery 1;" \
- "fi; " \
- "else " \
- "echo Warning: BCB is corrupted or does not exist; " \
+ "fi;" \
+ "if test \"${run_fastboot}\" -eq 0; then " \
+ "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
+ CONTROL_PARTITION "; then " \
+ "if bcb test command = bootonce-bootloader; then " \
+ "echo BCB: Bootloader boot...; " \
+ "bcb clear command; bcb store; " \
+ "setenv run_fastboot 1;" \
+ "elif bcb test command = boot-fastboot; then " \
+ "echo BCB: fastboot userspace boot...; " \
+ "setenv force_recovery 1;" \
+ "fi; " \
+ "else " \
+ "echo Warning: BCB is corrupted or does not exist; " \
+ "fi;" \
"fi;" \
"if test \"${run_fastboot}\" -eq 1; then " \
"echo Running Fastboot...;" \
"echo Running Android...;" \
BOOT_CMD \
"fi;" \
- "echo Failed to boot Android...;" \
- "reset\0"
+ "echo Failed to boot Android...;\0"
#define BOOTENV_DEV_NAME_SYSTEM(devtypeu, devtypel, instance) \
"system "
+#define BOOTENV_DEV_PANIC(devtypeu, devtypel, instance) \
+ "bootcmd_panic=" \
+ "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
+ "reset\0"
+
+#define BOOTENV_DEV_NAME_PANIC(devtypeu, devtypel, instance) \
+ "panic "
+
#define BOOT_TARGET_DEVICES(func) \
func(FASTBOOT, fastboot, na) \
func(RECOVERY, recovery, na) \
func(SYSTEM, system, na) \
+ func(PANIC, panic, na) \
#define PREBOOT_LOAD_LOGO \
"if test \"${boot_source}\" != \"usb\" && " \
"bootm; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* The rest of the configuration is shared */
#include <configs/mxs.h>
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else " \
- "echo ERR: Fail to boot from MMC; " \
- "fi; " \
- "fi; " \
- "else exit; fi"
-
/* The rest of the configuration is shared */
#include <configs/mxs.h>
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* The rest of the configuration is shared */
#include <configs/mxs.h>
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
#define CONFIG_ARP_TIMEOUT 200UL
/*
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
"video-mode=" \
"lcd:800x480-24@60,monitor=lcd\0" \
-#define MMCBOOTCOMMAND \
- "run doquiet; " \
- "run tryboot; " \
-
-#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
-
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
"echo WARNING: Could not determine dtb to use; fi; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "run findfdt;" \
- "mmc dev ${mmcdev};" \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
#define CONFIG_ARP_TIMEOUT 200UL
/* Physical Memory Map */
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"if test test $board_rev = REVA ; then " \
"setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"echo WARNING: Could not determine dtb to use; fi; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "run findfdt;" \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"bootz; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "run findfdt;" \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"bootz; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND ""
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=console=ttyS0,115200\0" \
"echo run attachboot - Boot attached kernel image.;" \
"echo"
-#define CONFIG_BOOTCOMMAND \
- "run sdboot;" \
- "run emmcboot;" \
- "run attachboot;" \
- "echo"
-
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
#define __CONFIG_H
/* System configurations */
-#define CONFIG_KEYBOARD
#include "mx6_common.h"
/* environment variables configuration */
/* default environment variables */
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
#include <linux/sizes.h>
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot"
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
"nandboot=run nandbootcommon; "\
"bootm ${loadaddr} - ${fdtaddr}\0"\
-#define CONFIG_BOOTCOMMAND \
- "run autoboot"
-
/* Miscellaneous configurable options */
/* memtest works on */
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_BOOTCOMMAND \
- "run envboot; " \
- "run mmcboot; "
#define DEFAULT_LINUX_BOOT_ENV \
"loadaddr=0xc0700000\0" \
"mmcdev=0\0" \
"mmcpart=1\0"
-#define CONFIG_USE_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "fdt addr ${fdtcontroladdr}; " \
- "fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \
- "load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \
- "booti ${kernel_addr_r} - ${fdt_addr_r}; "
-
#endif/* __CONFIG_H */
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \
CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
#define ACFG_CONSOLE_DEV ttymxc0
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
-#define CONFIG_BOOTCOMMAND "run emmcboot"
#define CONFIG_EXTRA_ENV_SETTINGS \
"env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0"
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "fi; " \
- "fi;" \
- "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
#define CONFIG_CLK_1000_400_200
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
OR_GPCM_EAD)
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#endif
-#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
-
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000"
OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
-
/* The size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
__stringify(__NAND_RST_CMD)"\0" \
__stringify(__PCIE_RST_CMD)"\0"
-#define NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw " \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define HDBOOT \
-"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"usb start;" \
-"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
-"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
#define CONFIG_USB_FAT_BOOT \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs " \
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
"bootm $norbootaddr - $norfdtaddr"
-#define RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"tftp $ramdiskaddr $ramdiskfile;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND HDBOOT
-
#endif /* __CONFIG_H */
"fit_addr=0x82000000\0" \
ENV_MMC
-#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
#define PCM052_EXTRA_ENV_SETTINGS
#endif
-/* if no target-specific boot command was defined by the target,
- define an empty one */
-#ifndef PCM052_BOOTCOMMAND
-#define PCM052_BOOTCOMMAND
-#endif
-
/* if no target-specific extra environment settings were defined by the
target, define an empty one */
#ifndef PCM052_NET_INIT
#endif
/* boot command, including the target-defined one if any */
-#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand"
/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
"optargs=rw rootwait\0" \
ENV_MMC \
ENV_NAND
-
-#define CONFIG_BOOTCOMMAND "run mmcboot;run nandboot"
#endif
#define CONSOLE_DEV "ttyO5"
#endif
-#define CONFIG_BOOTCOMMAND \
- "run eval_boot_device;" \
- "part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;" \
- "setenv bootargs console=${console} " \
- "vt.global_cursor_default=0 " \
- "root=PARTUUID=${root_fs_partuuid} " \
- "rootfstype=ext4 " \
- "rootwait " \
- "rootdelay=1;" \
- "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \
- "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \
- "bootz ${loadaddr} - ${fdtaddr}"
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"echo WARN: Cannot load the DT; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi;"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
"echo WARN: Cannot load the DT; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi;"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
CONFIG_LEGACY_BOOTCMD_ENV \
BOOTENV
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd || run legacy_bootcmd"
-
#endif /* __PIC32MZDASK_CONFIG_H */
"${get_cmd} ${loadaddr} ${image}; " \
"booti; "
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else booti ${loadaddr} - ${fdt_addr}; fi"
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x84000 0x210000; " \
- "bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#elif defined (CONFIG_SYS_USE_FLASH)
/* JFFS Partition offset set */
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
#define CONFIG_CON_ROT "fbcon=rotate:3 "
#define CONFIG_EXTRA_ENV_SETTINGS \
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x22000000 0x84000 0x294000; " \
- "bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
/* JFFS Partition offset set */
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
-#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_ROOTPATH "/ronetix/rootfs"
#define CONFIG_CON_ROT "fbcon=rotate:3 "
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
-
-#define CONFIG_BOOTCOMMAND \
- "nand read 0x70000000 0x200000 0x300000;" \
- "bootm 0x70000000"
#elif CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in mmc */
-
-#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
- "fatload mmc 0:1 0x72000000 zImage; " \
- "bootz 0x72000000 - 0x71000000"
#endif
/* Defines for SPL */
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs $(bootargs_console); " \
- "run bootcmd_usb; " \
- "bootm 0x00800000 0x01100000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
-
-#define CONFIG_BOOTCOMMAND \
- "if dfubutton; then " \
- "run dfu_start; " \
- "reset; " \
- "fi; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmc_dev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run mmc_load_uimage; then " \
- "run mmc_args;" \
- "bootm ${kloadaddr};" \
- "fi;" \
- "fi;" \
- "run nand_boot;" \
- "reset;"
-
-#else
-
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-#define CONFIG_BOOTCOMMAND \
- "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0"
-
#endif /* __QEMU_PPCE500_H */
#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
/*
* SuperH PCI Bridge Configration
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
-
-#define CONFIG_BOOTCOMMAND \
-"if dfubutton; then " \
- "run dfu_start; " \
- "reset; " \
-"fi;" \
-"run nand_boot;" \
-"run nand_boot_backup;" \
-"reset;"
-
-#else
-
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#endif /* ! __CONFIG_RASTABAN_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-#define CONFIG_BOOTCOMMAND \
- "tftp 0x48080000 Image; " \
- "tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \
- "booti 0x48080000 - 0x48000000"
-
/* SPL support */
#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965)
#define CONFIG_SPL_BSS_START_ADDR 0xe633f000
/* GPIO */
#define CONFIG_BCM2835_GPIO
/* LCD */
-#define CONFIG_LCD_DT_SIMPLEFB
#define CONFIG_VIDEO_BCM2835
/* DFU over USB/UDC */
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmc_dev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run mmc_load_uimage; then " \
- "run mmc_args;" \
- "bootm ${kloadaddr};" \
- "fi;" \
- "fi;" \
- "run nand_boot;" \
- "reset;"
-
-#else
-
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
#endif
#endif /* CONFIG_SPL_BUILD */
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
-#define CONFIG_BOOTCOMMAND "run mmcboot"
-
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \
" ${console} ${meminfo}"
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-#define CONFIG_BOOTCOMMAND "run mmcboot"
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in sd card */
-#define CONFIG_BOOTCOMMAND \
- "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \
- "fatload mmc 0:1 0x22000000 zImage;" \
- "bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_BOOTCOMMAND "nand read " \
- "0x22000000 0x200000 0x600000; " \
- "nand read 0x21000000 0x180000 0x20000; " \
- "bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_QSPI_BOOT)
/* bootstrap + u-boot + env + linux in SPI NOR flash */
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x21000000 0x180000 0x80000; " \
- "sf read 0x22000000 0x200000 0x600000; " \
- "bootz 0x22000000 - 0x21000000"
#endif
#endif
(0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 " \
- CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \
- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \
- "bootz 0x23000000 - 0x22000000"
#endif
/* SPL */
/* SPI flash */
#define CONFIG_SF_DEFAULT_SPEED 66000000
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
/* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \
- "fatload mmc 0:1 0x22000000 zImage; " \
- "bootz 0x22000000 - 0x21000000"
#endif
/* SPL */
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 at91-sama5d2_xplained.dtb; " \
- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \
- "bootz 0x23000000 - 0x22000000"
#elif CONFIG_SPI_BOOT
/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; " \
- "ext4load mmc 0:1 0x23000000 /boot/zImage; " \
- "bootz 0x23000000 - 0x22000000"
#endif
#ifdef CONFIG_QSPI_BOOT
#undef CONFIG_ENV_SPI_BUS
-#undef CONFIG_BOOTCOMMAND
#define CONFIG_ENV_SPI_BUS 1
-#define CONFIG_BOOTCOMMAND "sf probe 1:0; " \
- "sf read 0x22000000 0x180000 0x80000; " \
- "sf read 0x23000000 0x200000 0x600000; "\
- "bootz 0x23000000 - 0x22000000"
#endif
GENERATED_GBL_DATA_SIZE)
#endif
-#ifndef CONFIG_BOOTCOMMAND
-#ifdef CONFIG_SD_BOOT
-/* u-boot env in sd/mmc card */
-
-/* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \
- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \
- "bootz 0x62000000 - 0x61000000"
-#else
-#define CONFIG_BOOTCOMMAND "Place your bootcommand here"
-#endif
-
-#endif
-
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50
#define CONFIG_IO_TRACE
#endif
-#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMER_RATE 1000000
-#endif
-
-#define CONFIG_HOST_MAX_DEVICES 4
-
#define CONFIG_MALLOC_F_ADDR 0x0010000
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* turn on command-line edit/c/auto */
-
-/* SPI - enable all SPI flash types for testing purposes */
-
-#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
-
#define CONFIG_PHYSMEM
/* Size of our emulated memory */
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define BOOT_TARGET_DEVICES(func) \
- func(HOST, host, 1) \
- func(HOST, host, 0)
-
-#ifdef __ASSEMBLY__
-#define BOOTENV
-#else
-#include <config_distro_bootcmd.h>
-#endif
-
#define CONFIG_KEEP_SERVERADDR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_TIMESTAMP
#define CONFIG_SANDBOX_SDL
#endif
-/* LCD and keyboard require SDL support */
-#ifdef CONFIG_SANDBOX_SDL
-#define LCD_BPP LCD_COLOR16
-#define CONFIG_LCD_BMP_RLE8
-
-#define CONFIG_KEYBOARD
-
-#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-#else
-#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-#endif
-
-#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
- "eth2addr=00:00:11:22:33:48\0" \
- "eth3addr=00:00:11:22:33:45\0" \
- "eth4addr=00:00:11:22:33:48\0" \
- "eth5addr=00:00:11:22:33:46\0" \
- "eth6addr=00:00:11:22:33:47\0" \
- "ipaddr=1.2.3.4\0"
-
-#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0x10000000\0" \
- "kernel_addr_r=0x1000000\0" \
- "fdt_addr_r=0xc00000\0" \
- "ramdisk_addr_r=0x2000000\0" \
- "scriptaddr=0x1000\0" \
- "pxefile_addr_r=0x2000\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- SANDBOX_SERIAL_SETTINGS \
- SANDBOX_ETH_SETTINGS \
- BOOTENV \
- MEM_LAYOUT_ENV_SETTINGS
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_ATA_IDE0_OFFSET 0
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \
/*
* Override CONFIG_BOOTCOMMAND in x86-common.h
*/
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "if test ${bootdev} = \"usb\"; then ${bootdev} start; fi; " \
- "if test ${bootdev} = \"scsi\"; then ${bootdev} scan; fi; " \
- "${bootdev} info; " \
- "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \
- "${loadaddr} ${bootfile}; " \
- "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \
- "${ramdiskaddr} ${ramdiskfile}; " \
- "zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}"
#endif /* __SLIMBOOTLOADER_CONFIG_H__ */
/* BOOTP and DHCP options */
#define CONFIG_BOOTP_BOOTFILESIZE
-#define NFSBOOTCOMMAND \
- "setenv autoload yes; setenv autoboot yes; " \
- "setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
- "dhcp"
#if !defined(CONFIG_SPL_BUILD)
/* USB configuration */
#endif
/* General Boot Parameter */
-#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_SYS_CBSIZE 512
/*
#undef CONFIG_EXYNOS_FB
#undef CONFIG_EXYNOS_DP
-#undef CONFIG_KEYBOARD
#define CONFIG_BOARD_COMMON
#undef CONFIG_EXYNOS_FB
#undef CONFIG_EXYNOS_DP
-#undef CONFIG_KEYBOARD
-
#define CONFIG_BOARD_COMMON
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
/* PWM */
#define CONFIG_PWM 1
-#define CONFIG_BOOTCOMMAND "run ubifsboot"
-
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
" console=ttySAC0,115200n8" \
" mem=128M"
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x00002488
-#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
-
/* SMDKV310 has 4 bank of DRAM */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
* Boot
*/
-#define CONFIG_BOOTCOMMAND \
- "setenv boot_mmc_part ${kernel_mmc_part}; " \
- "if test reboot-${reboot-mode} = reboot-r; then " \
- "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \
- "if test reboot-${reboot-mode} = reboot-b; then " \
- "echo fastboot; fastboot 0; fi; " \
- "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
- "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
- "mmc dev ${boot_mmc_dev}; " \
- "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
- "bootm ${kernel_addr_r};"
-
#endif
/* Booting Linux */
#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_BOOTCOMMAND \
- "setenv bootcmd '" \
- "bridge enable; " \
- "if test ${bootnum} = \"b\"; " \
- "then run _fpga_loadsafe; " \
- "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \
- "run _fpga_loaduser; " \
- "fi;" \
- "echo \"Booting bank $bootnum\" && run userload && run userboot;" \
- "' && " \
- "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
- "saveenv && saveenv && boot;"
-
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* Environment settings */
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_BOOTCOMMAND "run mmc_mmc"
/* Environment is in MMC */
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_BOOTCOMMAND "run mmc_mmc"
/* Environment is in MMC */
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_BOOTCOMMAND "run selboot"
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */
/* Extra Environment */
#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
-#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
-#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
-
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
-#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
#define CONFIG_SYS_SPD_BUS_NUM 0
"bootm ${kernel_addr_r} - ${fdt_addr};" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
""
-#define CONFIG_BOOTCOMMAND "run boot_nor"
/* pass open firmware flat tree */
"run setrootmmc; " \
"run setloadmmc; " \
-#define CONFIG_BOOTCOMMAND \
- "run setfdtfile; " \
- "run checkbootdev; " \
- "run loadfdt;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run setbootargs; " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "fi; " \
- "fi"
-
/* Miscellaneous configurable options */
/* Physical Memory Map */
"env_check=if env info -p -d -q; then env save; fi\0" \
"boot_net_usb_start=true\0"
+#ifndef STM32MP_BOARD_EXTRA_ENV
+#define STM32MP_BOARD_EXTRA_ENV
+#endif
+
#include <config_distro_bootcmd.h>
/*
STM32MP_BOOTCMD \
STM32MP_PARTS_DEFAULT \
BOOTENV \
- STM32MP_EXTRA
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
#endif /* ifndef CONFIG_SPL_BUILD */
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
#ifndef __CONFIG_STM32MP15_DH_DHSOM_H__
#define __CONFIG_STM32MP15_DH_DHSOM_H__
+/* PHY needs a longer autoneg timeout */
+#define PHY_ANEG_TIMEOUT 20000
+
+#define STM32MP_BOARD_EXTRA_ENV \
+ "usb_pgood_delay=1000\0" \
+ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+ "setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
+ "load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \
+ "env set filesize1 ${filesize} && " \
+ "load mmc 0:4 ${loadaddr} /boot/u-boot.itb && " \
+ "sf probe && sf erase 0 0x200000 && " \
+ "sf update ${loadaddr1} 0 ${filesize1} && " \
+ "sf update ${loadaddr1} 0x40000 ${filesize1} && " \
+ "sf update ${loadaddr} 0x80000 ${filesize} && " \
+ "env set filesize1 && env set loadaddr1\0"
+
#include <configs/stm32mp15_common.h>
#define CONFIG_SPL_TARGET "u-boot.itb"
#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTCOMMAND \
- "sf probe 0:1 50000000; " \
- "sf read ${loadaddr} 0x100000 ${kern_size}; " \
- "bootm ${loadaddr}"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"kern_size=0x700000\0" \
"loadaddr=0x40001000\0" \
/* Misc configuration */
-#define CONFIG_BOOTCOMMAND "go 0x40040000"
-
/*
+ * QSPI support
+ */
/* #define CONFIG_SYS_PCI_64BIT 1 */
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
- "mtd mx66u51235f=u-boot.bin raw 200000 100000;" \
+ "mtd nor1=u-boot.bin raw 200000 100000;" \
"fip.bin raw 180000 78000;" \
"optee.bin raw 500000 100000\0"
/* Environment settings */
-#undef CONFIG_BOOTCOMMAND
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
-
-#define CONFIG_BOOTCOMMAND \
-"if dfubutton; then " \
- "run dfu_start; " \
- "reset; " \
-"fi;" \
-"run nand_boot;" \
-"run nand_boot_backup;" \
-"reset;"
-
-#else
-
-#define CONFIG_BOOTCOMMAND \
- "setenv autoload no; " \
- "dhcp; " \
- "if tftp 80000000 debrick.scr; then " \
- "source 80000000; " \
- "fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#endif /* ! __CONFIG_THUBAN_H */
"bootm ${loadaddr}\0" \
"fdtfile=ti814x-evm.dtb\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loaduimage; then " \
- "run mmcboot;" \
- "fi;" \
- "fi;" \
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan;" \
- "fatload mmc 0 ${loadaddr} uImage;" \
- "bootm ${loadaddr}" \
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
"mtdparts=mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
-#ifndef CONFIG_BOOTCOMMAND
-#ifndef CONFIG_TI_SECURE_DEVICE
-#define CONFIG_BOOTCOMMAND \
- "run init_${boot}; " \
- "run get_mon_${boot} run_mon; " \
- "run get_kern_${boot}; " \
- "run init_fw_rd_${boot}; " \
- "run get_fdt_${boot}; " \
- "run run_kern"
-#else
-#define CONFIG_BOOTCOMMAND \
- "run run_mon_hs; " \
- "run init_${boot}; " \
- "run get_fit_${boot}; " \
- "bootm ${addr_fit}#${name_fdt}"
-#endif
-#endif
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
"exit; " \
"fi; " \
-#define FASTBOOT_CMD \
- "echo Booting into fastboot ...; " \
- "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; "
-
#define DEFAULT_COMMON_BOOT_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
"if bcb test command = bootonce-bootloader; then " \
"echo Android: Bootloader boot...; " \
"bcb clear command; bcb store; " \
- FASTBOOT_CMD \
+ "fastboot 1; " \
"exit; " \
"elif bcb test command = boot-recovery; then " \
"echo Android: Recovery boot...; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0"
-#define CONFIG_BOOTCOMMAND \
- "if test ${dofastboot} -eq 1; then " \
- "echo Boot fastboot requested, resetting dofastboot ...;" \
- "setenv dofastboot 0; saveenv;" \
- FASTBOOT_CMD \
- "fi;" \
- "if test ${boot_fit} -eq 1; then " \
- "run update_to_fit;" \
- "fi;" \
- "run findfdt; " \
- "run finduuid; " \
- "run distro_bootcmd;" \
- "run emmc_android_boot; " \
- ""
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
EXTRA_ENV_USB \
DFU_ALT_INFO
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \
- "if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \
- "fi; fi; run $modeboot"
-
#endif /* __CONFIG_TOPIC_MIAMI_H */
* without verification (for development purposes).
* Else boot FIT image.
*/
-#define CONFIG_BOOTCOMMAND \
- "if part number mmc 0 vbmeta is_avb; then" \
- " echo MMC with vbmeta partition detected.;" \
- " echo starting Android Verified boot.;" \
- " avb init 0; " \
- " if avb verify; then " \
- " set bootargs $bootargs $avb_bootargs; " \
- " part start mmc 0 boot boot_start; " \
- " part size mmc 0 boot boot_size; " \
- " mmc read ${load_addr} ${boot_start} ${boot_size}; " \
- " bootm ${load_addr} ${load_addr} ${fdt_addr_r}; " \
- " else; " \
- " echo AVB verification failed.; " \
- " exit; " \
- " fi; " \
- "elif part number mmc 0 system is_non_avb_android; then " \
- " booti ${kernel_addr_r} ${initrd_addr_r} ${fdt_addr_r};" \
- "else;" \
- " echo Booting FIT image.;" \
- " bootm ${load_addr} ${load_addr} ${fdt_addr_r}; " \
- "fi;"
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
*/
#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_BOOTCOMMAND \
- "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
-
/*
* Command
*/
/*
* Copyright (C) 2013, 2014, 2017 Markus Niebel <Markus.Niebel@tq-group.com>
*
- * Configuration settings for the TQ Systems TQMa6<Q,D,DL,S> module.
+ * Configuration settings for the TQ-Systems TQMa6<Q,D,DL,S> module.
*/
#ifndef __CONFIG_H
"fi; fi; " \
"setenv filesize; setenv blkc \0" \
-#define CONFIG_BOOTCOMMAND \
- "run mmcboot; run netboot; run panicboot"
-
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
#define TQMA6_UBOOT_OFFSET 0x400
"setexpr offset ${fdt_start} * " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"sf read ${fdt_addr} ${offset} ${size}; " \
- "setenv size ; setenv offset\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "sf probe; run mmcboot; run netboot; run panicboot" \
-
+ "setenv size ; setenv offset\0"
#else
#error "need to define boot source"
/*
* Copyright (C) 2013 - 2017 Markus Niebel <Markus.Niebel@tq-group.com>
*
- * Configuration settings for the TQ Systems TQMa6<Q,D,DL,S> module on
+ * Configuration settings for the TQ-Systems TQMa6<Q,D,DL,S> module on
* MBa6 starter kit
*/
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-#define CONFIG_BOOTCOMMAND "run autoboot"
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-#define CONFIG_BOOTCOMMAND "run autoboot"
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_ROOTPATH "/nfs/root/path"
-#define NFSBOOTCOMMAND \
- "setenv bootargs $bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
- "run __nfsboot"
#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE "fitImage"
#endif
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_BOOTCOMMAND "nboot 21000000 0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
/* Linux boot */
#define CONFIG_HOSTNAME "usbarmory"
-#define CONFIG_BOOTCOMMAND \
- "run distro_bootcmd; " \
- "setenv bootargs console=${console} ${bootargs_default}; " \
- "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \
- "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}"
#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
"fdt_addr=0x83000000\0" \
"boot_name=boot.img\0" \
"boot_addr=0x8007f800\0"
-
-#ifndef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
- " set bootargs; " \
- " abootimg addr ${boot_addr}; " \
- " abootimg get dtb --index=0 fdt_addr; " \
- " bootm ${boot_addr} ${boot_addr} " \
- " ${fdt_addr}; " \
- "else; " \
- " set fdt_high 0xffffffffffffffff; " \
- " set initrd_high 0xffffffffffffffff; " \
- " smhload ${kernel_name} ${kernel_addr}; " \
- " smhload ${fdtfile} ${fdt_addr}; " \
- " smhload ${initrd_name} ${initrd_addr} "\
- " initrd_end; " \
- " fdt addr ${fdt_addr}; fdt resize; " \
- " fdt chosen ${initrd_addr} ${initrd_end}; " \
- " booti $kernel_addr - $fdt_addr; " \
- "fi"
-#endif
#endif
/* Monitor Command Prompt */
#include <configs/rk3288_common.h>
-#define CONFIG_KEYBOARD
-
#endif
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
/* Miscellaneous configurable options */
/* Physical memory map */
/* Use our own mapping for the VInCo platform */
/* Update the bootcommand according to our mapping for the VInCo platform */
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "mmc dev 0 0;" \
- "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \
- "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \
- "bootz ${loadaddr} - ${oftaddr}"
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_start=0x20000\0" \
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
#endif /* __CONFIG_H */
"bootz; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "run do_bootscript_hab;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
*/
#define CONFIG_SYS_NS16550_PORT_MAPPED
-#ifndef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
-#endif
-
/*
* Miscellaneous configurable options
*/
"ramdiskfile=initramfs.gz\0"
-#define RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftpboot $kernel_addr_r $bootfile;" \
- "tftpboot $ramdisk_addr_r $ramdiskfile;" \
- "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize"
-
-#define NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftpboot $kernel_addr_r $bootfile;" \
- "zboot $kernel_addr_r"
-
-
#endif /* __CONFIG_H */
/* Booting Linux */
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}"
/* Extra Environment */
#define CONFIG_HOSTNAME "xea"
#include <configs/xilinx_zynqmp.h>
/* Undef unneeded configs */
-#undef CONFIG_BOOTCOMMAND
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_SYS_INIT_SP_ADDR
*
* @parent: Parent device to search
* @name: Name to look for
+ * @len: Length of the name
+ * @devp: Returns device found, if any
+ * @return 0 if found, else -ENODEV
+ */
+int device_find_child_by_namelen(const struct udevice *parent, const char *name,
+ int len, struct udevice **devp);
+
+/**
+ * device_find_child_by_name() - Find a child by device name
+ *
+ * @parent: Parent device to search
+ * @name: Name to look for
* @devp: Returns device found, if any
* @return 0 if found, else -ENODEV
*/
*/
bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node);
+/**
+ * ofnode_eth_uses_inband_aneg() - Detect whether MAC should use in-band autoneg
+ *
+ * This function detects whether the Ethernet controller should use IEEE 802.3
+ * clause 37 in-band autonegotiation for serial protocols such as 1000base-x,
+ * SGMII, USXGMII, etc. The property is relevant when the Ethernet controller
+ * is connected to an on-board PHY or an SFP cage, and is not relevant when it
+ * has a fixed link (in that case, in-band autoneg should not be used).
+ *
+ * @param eth_node ofnode belonging to the Ethernet controller
+ * @return true if in-band autoneg should be used, false otherwise
+ */
+bool ofnode_eth_uses_inband_aneg(ofnode eth_node);
+
#endif
*
* @node: node to check
* @propname: name of the property containing the string list
- * @index: index of the string to return
+ * @index: index of the string to return (cannot be negative)
* @lenp: return location for the string length or an error code on failure
*
* @return:
- * length of string, if found or -ve error value if not found
+ * 0 if found or -ve error value if not found
*/
int ofnode_read_string_index(ofnode node, const char *propname, int index,
const char **outp);
int ofnode_read_string_count(ofnode node, const char *property);
/**
+ * ofnode_read_string_list() - read a list of strings
+ *
+ * This produces a list of string pointers with each one pointing to a string
+ * in the string list. If the property does not exist, it returns {NULL}.
+ *
+ * The data is allocated and the caller is reponsible for freeing the return
+ * value (the list of string pointers). The strings themselves may not be
+ * changed as they point directly into the devicetree property.
+ *
+ * @node: node to check
+ * @listp: returns an allocated, NULL-terminated list of strings if the return
+ * value is > 0, else is set to NULL
+ * @return number of strings in list, 0 if none, -ENOMEM if out of memory,
+ * -EINVAL if no such property, -EENODATA if property is empty
+ * @return: NULL-terminated list of strings (NULL if no property or empty)
+ */
+int ofnode_read_string_list(ofnode node, const char *property,
+ const char ***listp);
+
+/**
* ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list
*
* This function is useful to parse lists of phandles and their arguments.
static inline int pinctrl_generic_set_state(struct udevice *pctldev,
struct udevice *config)
{
- return -EINVAL;
+ return -ENOSYS;
}
#endif
static inline int pinctrl_select_state(struct udevice *dev,
const char *statename)
{
- return -EINVAL;
+ return -ENOSYS;
}
#endif
* number of strings in the list, or -ve error value if not found
*/
int dev_read_string_count(const struct udevice *dev, const char *propname);
+
+/**
+ * dev_read_string_list() - read a list of strings
+ *
+ * This produces a list of string pointers with each one pointing to a string
+ * in the string list. If the property does not exist, it returns {NULL}.
+ *
+ * The data is allocated and the caller is reponsible for freeing the return
+ * value (the list of string pointers). The strings themselves may not be
+ * changed as they point directly into the devicetree property.
+ *
+ * @dev: device to examine
+ * @propname: name of the property containing the string list
+ * @listp: returns an allocated, NULL-terminated list of strings if the return
+ * value is > 0, else is set to NULL
+ * @return number of strings in list, 0 if none, -ENOMEM if out of memory,
+ * -ENOENT if no such property
+ */
+int dev_read_string_list(const struct udevice *dev, const char *propname,
+ const char ***listp);
+
/**
* dev_read_phandle_with_args() - Find a node pointed by phandle in a list
*
return ofnode_read_string_count(dev_ofnode(dev), propname);
}
+static inline int dev_read_string_list(const struct udevice *dev,
+ const char *propname,
+ const char ***listp)
+{
+ return ofnode_read_string_list(dev_ofnode(dev), propname, listp);
+}
+
static inline int dev_read_phandle_with_args(const struct udevice *dev,
const char *list_name, const char *cells_name, int cell_count,
int index, struct ofnode_phandle_args *out_args)
*/
int uclass_bind_device(struct udevice *dev);
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+/**
+ * uclass_pre_unbind_device() - Prepare to deassociate device with a uclass
+ *
+ * Call any handled needed before uclass_unbind_device() is called
+ *
+ * @dev: Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_pre_unbind_device(struct udevice *dev);
+
/**
* uclass_unbind_device() - Deassociate device with a uclass
*
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
int uclass_unbind_device(struct udevice *dev);
+
#else
+static inline int uclass_pre_unbind_device(struct udevice *dev) { return 0; }
static inline int uclass_unbind_device(struct udevice *dev) { return 0; }
#endif
* uclass_get_by_name() - Look up a uclass by its driver name
*
* @name: Name to look up
+ * @len: Length of name
+ * @returns the associated uclass ID, or UCLASS_INVALID if not found
+ */
+enum uclass_id uclass_get_by_name_len(const char *name, int len);
+
+/**
+ * uclass_get_by_name() - Look up a uclass by its driver name
+ *
+ * @name: Name to look up
* @returns the associated uclass ID, or UCLASS_INVALID if not found
*/
enum uclass_id uclass_get_by_name(const char *name);
int uclass_probe_all(enum uclass_id id);
/**
+ * uclass_id_count() - Count the number of devices in a uclass
+ *
+ * @id: uclass ID to look up
+ * @return number of devices in that uclass (0 if none)
+ */
+int uclass_id_count(enum uclass_id id);
+
+/**
* uclass_id_foreach_dev() - Helper function to iteration through devices
*
* This creates a for() loop which works through the available devices in
#include <charset.h>
#include <pe.h>
-/* UEFI spec version 2.8 */
-#define EFI_SPECIFICATION_VERSION (2 << 16 | 80)
+/* UEFI spec version 2.9 */
+#define EFI_SPECIFICATION_VERSION (2 << 16 | 90)
/* Types and defines for EFI CreateEvent */
enum efi_timer_delay {
};
/* EFI event group GUID definitions */
+
#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
EFI_GUID(0x27abf055, 0xb1b8, 0x4c26, 0x80, 0x48, \
0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf)
+#define EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES \
+ EFI_GUID(0x8be0e274, 0x3970, 0x4b44, 0x80, 0xc5, \
+ 0x1a, 0xb9, 0x50, 0x2f, 0x3b, 0xfc)
+
#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
EFI_GUID(0x13fa7698, 0xc831, 0x49c7, 0x87, 0xea, \
0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96)
EFI_GUID(0x7ce88fb3, 0x4bd7, 0x4679, 0x87, 0xa8, \
0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b)
+#define EFI_EVENT_GROUP_AFTER_READY_TO_BOOT \
+ EFI_GUID(0x3a2a00ad, 0x98b9, 0x4cdf, 0xa4, 0x78, \
+ 0x70, 0x27, 0x77, 0xf1, 0xc1, 0xb)
+
#define EFI_EVENT_GROUP_RESET_SYSTEM \
EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \
0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b)
EFI_GUID(0x1e2ed096, 0x30e2, 0x4254, 0xbd, \
0x89, 0x86, 0x3b, 0xbe, 0xf8, 0x23, 0x25)
+/**
+ * struct efi_configuration_table - EFI Configuration Table
+ *
+ * This table contains a set of GUID/pointer pairs.
+ * The EFI Configuration Table may contain at most one instance of each table type.
+ *
+ * @guid: GUID that uniquely identifies the system configuration table
+ * @table: A pointer to the table associated with guid
+ */
struct efi_configuration_table {
efi_guid_t guid;
void *table;
#define EFI_SYSTEM_TABLE_SIGNATURE ((u64)0x5453595320494249ULL)
+/**
+ * struct efi_system_table - EFI System Table
+ *
+ * EFI System Table contains pointers to the runtime and boot services tables.
+ *
+ * @hdr: The table header for the EFI System Table
+ * @fw_vendor: A pointer to a null terminated string that identifies the vendor
+ * that produces the system firmware
+ * @fw_revision: The revision of the system firmware
+ * @con_in_handle: The handle for the active console input device
+ * @con_in: A pointer to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL interface
+ * that is associated with con_in_handle
+ * @con_out_handle: The handle for the active console output device
+ * @con_out: A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface
+ * that is associated with con_out_handle
+ * @stderr_handle: The handle for the active standard error console device
+ * @std_err: A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface
+ * that is associated with stderr_handle
+ * @runtime: A pointer to the EFI Runtime Services Table
+ * @boottime: A pointer to the EFI Boot Services Table
+ * @nr_tables: The number of system configuration tables
+ * @tables: A pointer to the system configuration tables
+ */
struct efi_system_table {
struct efi_table_hdr hdr;
u16 *fw_vendor; /* physical addr of wchar_t vendor string */
* @fields: 'fields' replaces the bit-fields defined in the EFI
* specification to to avoid possible compiler incompatibilities::
*
- * u32 length:24;
- * u32 type:8;
+ * u32 length:24;
+ * u32 type:8;
*/
struct efi_hii_package_header {
u32 fields;
0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7)
/**
- * win_certificate_uefi_guid - A certificate that encapsulates
+ * struct win_certificate_uefi_guid - A certificate that encapsulates
* a GUID-specific signature
*
* @hdr: Windows certificate header
} __attribute__((__packed__));
/**
- * efi_variable_authentication_2 - A time-based authentication method
+ * struct efi_variable_authentication_2 - A time-based authentication method
* descriptor
*
* This structure describes an authentication information for
} __attribute__((__packed__));
/**
- * efi_firmware_image_authentication - Capsule authentication method
+ * struct efi_firmware_image_authentication - Capsule authentication method
* descriptor
*
* This structure describes an authentication information for
/**
- * efi_signature_data - A format of signature
+ * struct efi_signature_data - A format of signature
*
* This structure describes a single signature in signature database.
*
} __attribute__((__packed__));
/**
- * efi_signature_list - A format of signature database
+ * struct efi_signature_list - A format of signature database
*
* This structure describes a list of signatures with the same type.
* An authenticated variable's value is a concatenation of one or more
int env_get_yesno(const char *var);
/**
+ * env_get_autostart() - Check if autostart is enabled
+ *
+ * @return true if the "autostart" env var exists and is set to "yes"
+ */
+bool env_get_autostart(void);
+
+/**
* env_set() - set an environment variable
*
* This sets or deletes the value of an environment variable. For setting the
#include <env_callback.h>
#include <linux/stringify.h>
+#ifndef USE_HOSTCC
+#include <generated/environment.h>
+#endif
+
#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = {
ENV_CRC, /* CRC Sum */
#ifdef CONFIG_BOOTCOMMAND
"bootcmd=" CONFIG_BOOTCOMMAND "\0"
#endif
-#ifdef CONFIG_RAMBOOTCOMMAND
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_NFSBOOTCOMMAND
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
#if defined(CONFIG_BOOTDELAY)
"bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
#if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0)
"bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0"
#endif
+#ifdef CONFIG_EXTRA_ENV_TEXT
+# ifdef CONFIG_EXTRA_ENV_SETTINGS
+# error "Your board uses a text-file environment, so must not define CONFIG_EXTRA_ENV_SETTINGS"
+# endif
+ /* This is created in the Makefile */
+ CONFIG_EXTRA_ENV_TEXT
+#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
#ifndef _FDT_SIMPLEFB_H_
#define _FDT_SIMPLEFB_H_
-int lcd_dt_simplefb_add_node(void *blob);
-int lcd_dt_simplefb_enable_existing_node(void *blob);
+int fdt_simplefb_add_node(void *blob);
+int fdt_simplefb_enable_existing_node(void *blob);
+int fdt_simplefb_enable_and_mem_rsv(void *blob);
#endif
/* Show arch-specific information for the 'bd' command */
void arch_print_bdinfo(void);
+int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+
#endif /* __ASSEMBLY__ */
/* Put only stuff here that the assembler can digest */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * VLAN An implementation of 802.1Q VLAN tagging.
+ *
+ * Authors: Ben Greear <greearb@candelatech.com>
+ */
+#ifndef _LINUX_IF_VLAN_H_
+#define _LINUX_IF_VLAN_H_
+
+/**
+ * struct vlan_ethhdr - vlan ethernet header (ethhdr + vlan_hdr)
+ * @h_dest: destination ethernet address
+ * @h_source: source ethernet address
+ * @h_vlan_proto: ethernet protocol
+ * @h_vlan_TCI: priority and VLAN ID
+ * @h_vlan_encapsulated_proto: packet type ID or len
+ */
+struct vlan_ethhdr {
+ unsigned char h_dest[ETH_ALEN];
+ unsigned char h_source[ETH_ALEN];
+ __be16 h_vlan_proto;
+ __be16 h_vlan_TCI;
+ __be16 h_vlan_encapsulated_proto;
+};
+
+#endif /* !(_LINUX_IF_VLAN_H_) */
/**
* struct lmb_property - Description of one region.
*
- * @base: Base address of the region.
- * @size: Size of the region
+ * @base: Base address of the region.
+ * @size: Size of the region
+ * @flags: memory region attributes
*/
struct lmb_property {
phys_addr_t base;
#endif
};
-extern void lmb_init(struct lmb *lmb);
-extern void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd,
- void *fdt_blob);
-extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
- phys_size_t size, void *fdt_blob);
-extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
-extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+void lmb_init(struct lmb *lmb);
+void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob);
+void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
+ phys_size_t size, void *fdt_blob);
+long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
/**
* lmb_reserve_flags - Reserve one region with a specific flags bitfield.
*
- * @lmb the logical memory block struct
- * @base base address of the memory region
- * @size size of the memory region
- * @flags flags for the memory region
- * @return 0 if OK, > 0 for coalesced region or a negative error code.
+ * @lmb: the logical memory block struct
+ * @base: base address of the memory region
+ * @size: size of the memory region
+ * @flags: flags for the memory region
+ * Return: 0 if OK, > 0 for coalesced region or a negative error code.
*/
long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base,
phys_size_t size, enum lmb_flags flags);
-extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
-extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
- phys_addr_t max_addr);
-extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
- phys_addr_t max_addr);
-extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base,
- phys_size_t size);
-extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
-extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
+phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
+ phys_addr_t max_addr);
+phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
+ phys_addr_t max_addr);
+phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
+int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
/**
* lmb_is_reserved_flags - test if tha address is in reserved region with a bitfield flag
*
- * @lmb the logical memory block struct
- * @addr address to be tested
- * @flags flags bitfied to be tested
- * @return 0 if not reserved or reserved without the requested flag else 1
+ * @lmb: the logical memory block struct
+ * @addr: address to be tested
+ * @flags: flags bitfied to be tested
+ * Return: if not reserved or reserved without the requested flag else 1
*/
int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags);
-extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
-extern void lmb_dump_all(struct lmb *lmb);
-extern void lmb_dump_all_force(struct lmb *lmb);
-
-static inline phys_size_t
-lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
-{
- return type->region[region_nr].size;
-}
+void lmb_dump_all(struct lmb *lmb);
+void lmb_dump_all_force(struct lmb *lmb);
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align);
-/* Low level functions */
-
-static inline bool lmb_is_nomap(struct lmb_property *m)
-{
- return m->flags & LMB_NOMAP;
-}
-
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
#ifndef __DSA_H__
#define __DSA_H__
+#include <dm/ofnode.h>
#include <phy.h>
#include <net.h>
struct udevice *dsa_get_master(struct udevice *dev);
/**
+ * dsa_port_get_ofnode() - Return a reference to the given port's OF node
+ *
+ * Can be called at driver probe time or later.
+ *
+ * @dev: DSA switch udevice pointer
+ * @port: Port index
+ * @return OF node reference if OK, NULL on error
+ */
+ofnode dsa_port_get_ofnode(struct udevice *dev, int port);
+
+/**
* dsa_port_get_pdata() - Helper that returns the platdata of an active
* (non-CPU) DSA port device.
*
*/
int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep);
+/**
+ * os_unmap() - Unmap a file previously mapped
+ *
+ * @buf: Mapped address
+ * @size: Size in bytes
+ * Return: 0 if OK, -ve on error
+ */
+int os_unmap(void *buf, int size);
+
/*
* os_find_text_base() - Find the text section in this running process
*
#include <pci_ids.h>
+/*
+ * Enhanced Configuration Access Mechanism (ECAM)
+ *
+ * See PCI Express Base Specification, Revision 5.0, Version 1.0,
+ * Section 7.2.2, Table 7-1, p. 677.
+ */
+#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
+#define PCIE_ECAM_DEV_SHIFT 15 /* Device number */
+#define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */
+
+#define PCIE_ECAM_BUS_MASK 0xff
+#define PCIE_ECAM_DEV_MASK 0x1f
+#define PCIE_ECAM_FUNC_MASK 0x7
+#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */
+
+#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
+#define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT)
+#define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT)
+#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
+
+#define PCIE_ECAM_OFFSET(bus, dev, func, where) \
+ (PCIE_ECAM_BUS(bus) | \
+ PCIE_ECAM_DEV(dev) | \
+ PCIE_ECAM_FUNC(func) | \
+ PCIE_ECAM_REG(where))
+
#ifndef __ASSEMBLY__
#include <dm/pci.h>
#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4
#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8
+#define PCI_VENDOR_ID_BROADCOM 0x14e4
+#define PCI_DEVICE_ID_NXT_57320 0x16F0
+
#define PCI_VENDOR_ID_COMPAQ 0x0e11
#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508
#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc
#ifndef __SANDBOX_BLOCK_DEV__
#define __SANDBOX_BLOCK_DEV__
+/* Maximum number of host devices - see drivers/block/sandbox.c */
+#define SANDBOX_HOST_MAX_DEVICES 4
+
struct host_block_dev {
#ifndef CONFIG_BLK
struct blk_desc blk_dev;
}
/**
- * scmi_send_and_process_msg() - send and process a SCMI message
+ * devm_scmi_process_msg() - Send and process an SCMI message
*
- * Send a message to a SCMI server through a target SCMI agent device.
+ * Send a message to an SCMI server through a target SCMI agent device.
* Caller sets scmi_msg::out_msg_sz to the output message buffer size.
* On return, scmi_msg::out_msg_sz stores the response payload size.
*
TEE_PARAM_ATTR_META)
/*
+ * Global Platform login identifiers for tee_open_session_arg::clnt_login
+ */
+#define TEE_LOGIN_PUBLIC 0x00000000
+#define TEE_LOGIN_USER 0x00000001
+#define TEE_LOGIN_GROUP 0x00000002
+#define TEE_LOGIN_APPLICATION 0x00000004
+#define TEE_LOGIN_APPLICATION_USER 0x00000005
+#define TEE_LOGIN_APPLICATION_GROUP 0x00000006
+/*
+ * Reserve use of GP implementation specific login method range
+ * (0x80000000 - 0xBFFFFFFF). This range is rather being used
+ * for REE kernel clients or TEE implementation.
+ */
+#define TEE_LOGIN_REE_KERNEL_MIN 0x80000000
+#define TEE_LOGIN_REE_KERNEL_MAX 0xBFFFFFFF
+/* Private login method for REE kernel/privileged clients */
+#define TEE_LOGIN_REE_KERNEL 0x80000000
+
+/*
* Some Global Platform error codes which has a meaning if the
* TEE_GEN_CAP_GP bit is returned by the driver in
* struct tee_version_data::gen_caps
#define TEE_ERROR_NOT_SUPPORTED 0xffff000a
#define TEE_ERROR_COMMUNICATION 0xffff000e
#define TEE_ERROR_SECURITY 0xffff000f
+#define TEE_ERROR_SHORT_BUFFER 0xffff0010
#define TEE_ERROR_OUT_OF_MEMORY 0xffff000c
#define TEE_ERROR_OVERFLOW 0xffff300f
#define TEE_ERROR_TARGET_DEAD 0xffff3024
/**
* struct tee_open_session_arg - extra arguments for tee_open_session()
* @uuid: [in] UUID of the Trusted Application
- * @clnt_uuid: [in] Normally zeroes
- * @clnt_login: [in] Normally 0
+ * @clnt_uuid: [in] UUID of client, zeroes for PUBLIC/REE_KERNEL
+ * @clnt_login: [in] Class of client TEE_LOGIN_*
* @session: [out] Session id
* @ret: [out] return value
* @ret_origin: [out] origin of the return value
#define ECNTRL_REDUCED_MII_MODE 0x00000004
#define ECNTRL_SGMII_MODE 0x00000002
+#define RCTRL_PROM 0x00000008
+
#ifndef CONFIG_SYS_TBIPA_VALUE
# define CONFIG_SYS_TBIPA_VALUE 0x1f
#endif
#endif
+/**
+ * video_is_active() - Test if one video device it active
+ *
+ * @return true if at least one video device is active, else false.
+ */
+bool video_is_active(void);
+
#ifndef CONFIG_DM_VIDEO
/* Video functions */
Support the library logical memory blocks.
config LMB_USE_MAX_REGIONS
- bool "Use a commun number of memory and reserved regions in lmb lib"
+ bool "Use a common number of memory and reserved regions in lmb lib"
depends on LMB
default y
help
DEFINE(GD_SIZE, sizeof(struct global_data));
DEFINE(GD_BD, offsetof(struct global_data, bd));
+
+ DEFINE(GD_FLAGS, offsetof(struct global_data, flags));
+
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
/* event group ExitBootServices() invoked */
const efi_guid_t efi_guid_event_group_exit_boot_services =
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES;
+/* event group before ExitBootServices() invoked */
+const efi_guid_t efi_guid_event_group_before_exit_boot_services =
+ EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES;
/* event group SetVirtualAddressMap() invoked */
const efi_guid_t efi_guid_event_group_virtual_address_change =
EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE;
if (!systab.boottime)
goto out;
+ /* Notify EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES event group. */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_before_exit_boot_services)) {
+ efi_signal_event(evt);
+ break;
+ }
+ }
+
/* Stop all timer related activities */
timers_enabled = false;
}
if (!efi_st_keep_devices) {
+ bootm_disable_interrupts();
if (IS_ENABLED(CONFIG_USB_DEVICE))
udc_disconnect();
board_quiesce_devices();
/* Fix up caches for EFI payloads if necessary */
efi_exit_caches();
- /* This stops all lingering devices */
- bootm_disable_interrupts();
-
/* Disable boot time services */
systab.con_in_handle = NULL;
systab.con_in = NULL;
}
/**
- * check_run_capsules - Check whether capsule update should run
+ * check_run_capsules() - check whether capsule update should run
*
* The spec says OsIndications must be set in order to run the capsule update
* on-disk. Since U-Boot doesn't support runtime SetVariable, allow capsules to
* run explicitly if CONFIG_EFI_IGNORE_OSINDICATIONS is selected
+ *
+ * Return: EFI_SUCCESS if update to run, EFI_NOT_FOUND otherwise
*/
-static bool check_run_capsules(void)
+static efi_status_t check_run_capsules(void)
{
u64 os_indications;
efi_uintn_t size;
- efi_status_t ret;
-
- if (IS_ENABLED(CONFIG_EFI_IGNORE_OSINDICATIONS))
- return true;
+ efi_status_t r;
size = sizeof(os_indications);
- ret = efi_get_variable_int(L"OsIndications", &efi_global_variable_guid,
- NULL, &size, &os_indications, NULL);
- if (ret == EFI_SUCCESS &&
- (os_indications
- & EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED))
- return true;
-
- return false;
+ r = efi_get_variable_int(L"OsIndications", &efi_global_variable_guid,
+ NULL, &size, &os_indications, NULL);
+ if (r != EFI_SUCCESS || size != sizeof(os_indications))
+ return EFI_NOT_FOUND;
+
+ if (os_indications &
+ EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED) {
+ os_indications &=
+ ~EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED;
+ r = efi_set_variable_int(L"OsIndications",
+ &efi_global_variable_guid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(os_indications),
+ &os_indications, false);
+ if (r != EFI_SUCCESS)
+ log_err("Setting %ls failed\n", L"OsIndications");
+ return EFI_SUCCESS;
+ } else if (IS_ENABLED(CONFIG_EFI_IGNORE_OSINDICATIONS)) {
+ return EFI_SUCCESS;
+ } else {
+ return EFI_NOT_FOUND;
+ }
}
/**
unsigned int nfiles, index, i;
efi_status_t ret;
- if (!check_run_capsules())
+ if (check_run_capsules() != EFI_SUCCESS)
return EFI_SUCCESS;
index = get_last_capsule();
log_err("Applying capsule %ls failed\n",
files[i]);
+ /* create CapsuleXXXX */
+ set_capsule_result(index, capsule, ret);
+
free(capsule);
} else {
log_err("Reading capsule %ls failed\n", files[i]);
}
- /* create CapsuleXXXX */
- set_capsule_result(index, capsule, ret);
-
/* delete a capsule either in case of success or failure */
ret = efi_capsule_delete_file(files[i]);
if (ret != EFI_SUCCESS)
&efi_block_io_guid, &diskobj->ops,
guid, NULL, NULL));
if (ret != EFI_SUCCESS)
- return ret;
+ goto error;
/*
* On partitions or whole disks without partitions install the
if (ret) {
log_err("ERROR: failure to add disk device %s, r = %lu\n",
dev->name, ret & ~EFI_ERROR_MASK);
- return ret;
+ continue;
}
disks++;
/**
- * efi_clear_os_indications() - clear OsIndications
- *
- * Clear EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED
- */
-static efi_status_t efi_clear_os_indications(void)
-{
- efi_uintn_t size;
- u64 os_indications;
- efi_status_t ret;
-
- size = sizeof(os_indications);
- ret = efi_get_variable_int(L"OsIndications", &efi_global_variable_guid,
- NULL, &size, &os_indications, NULL);
- if (ret != EFI_SUCCESS)
- os_indications = 0;
- else
- os_indications &=
- ~EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED;
- ret = efi_set_variable_int(L"OsIndications", &efi_global_variable_guid,
- EFI_VARIABLE_NON_VOLATILE |
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
- sizeof(os_indications), &os_indications,
- false);
- if (ret != EFI_SUCCESS)
- log_err("Setting %ls failed\n", L"OsIndications");
- return ret;
-}
-
-/**
* efi_init_obj_list() - Initialize and populate EFI object list
*
* Return: status code
*/
efi_status_t efi_init_obj_list(void)
{
- efi_status_t r, ret = EFI_SUCCESS;
+ efi_status_t ret = EFI_SUCCESS;
/* Initialize once only */
if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
if (IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK) &&
!IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK_EARLY))
ret = efi_launch_capsules();
-
out:
- r = efi_clear_os_indications();
- if (ret == EFI_SUCCESS)
- ret = r;
efi_obj_list_initialized = ret;
return ret;
}
#include <smbios.h>
#include <version_string.h>
#include <tpm-v2.h>
+#include <tpm_api.h>
#include <u-boot/hash-checksum.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <linux/unaligned/generic.h>
#include <hexdump.h>
+/**
+ * struct event_log_buffer - internal eventlog management structure
+ *
+ * @buffer: eventlog buffer
+ * @final_buffer: finalevent config table buffer
+ * @pos: current position of 'buffer'
+ * @final_pos: current position of 'final_buffer'
+ * @get_event_called: true if GetEventLog has been invoked at least once
+ * @ebs_called: true if ExitBootServices has been invoked
+ * @truncated: true if the 'buffer' is truncated
+ */
struct event_log_buffer {
void *buffer;
void *final_buffer;
size_t final_pos; /* final events config table position */
size_t last_event_size;
bool get_event_called;
+ bool ebs_called;
bool truncated;
};
return EFI_SUCCESS;
}
-/* tcg2_agile_log_append - Append an agile event to out eventlog
+/* put_event - Append an agile event to an eventlog
*
* @pcr_index: PCR index
* @event_type: type of event added
* @digest_list: list of digest algorithms to add
* @size: size of event
* @event: event to add
+ * @log: log buffer to append the event
*
- * @Return: status code
*/
-static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type,
- struct tpml_digest_values *digest_list,
- u32 size, u8 event[])
+static void put_event(u32 pcr_index, u32 event_type,
+ struct tpml_digest_values *digest_list, u32 size,
+ u8 event[], void *log)
{
- void *log = (void *)((uintptr_t)event_log.buffer + event_log.pos);
size_t pos;
size_t i;
u32 event_size;
- if (event_log.get_event_called)
- log = (void *)((uintptr_t)event_log.final_buffer +
- event_log.final_pos);
-
/*
* size refers to the length of event[] only, we need to check against
* the final tcg_pcr_event2 size
*/
event_size = size + tcg_event_final_size(digest_list);
- if (event_log.pos + event_size > TPM2_EVENT_LOG_SIZE ||
- event_log.final_pos + event_size > TPM2_EVENT_LOG_SIZE) {
- event_log.truncated = true;
- return EFI_VOLUME_FULL;
- }
put_unaligned_le32(pcr_index, log);
pos = offsetof(struct tcg_pcr_event2, event_type);
memcpy((void *)((uintptr_t)log + pos), event, size);
pos += size;
- /* make sure the calculated buffer is what we checked against */
+ /*
+ * make sure the calculated buffer is what we checked against
+ * This check should never fail. It checks the code above is
+ * calculating the right length for the event we are adding
+ */
if (pos != event_size)
- return EFI_INVALID_PARAMETER;
+ log_err("Appending to the EventLog failed\n");
+}
- /* if GetEventLog hasn't been called update the normal log */
- if (!event_log.get_event_called) {
- event_log.pos += pos;
- event_log.last_event_size = pos;
- } else {
- /* if GetEventLog has been called update config table log */
- struct efi_tcg2_final_events_table *final_event;
+/* tcg2_agile_log_append - Append an agile event to an eventlog
+ *
+ * @pcr_index: PCR index
+ * @event_type: type of event added
+ * @digest_list: list of digest algorithms to add
+ * @size: size of event
+ * @event: event to add
+ * @log: log buffer to append the event
+ *
+ * @Return: status code
+ */
+static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type,
+ struct tpml_digest_values *digest_list,
+ u32 size, u8 event[])
+{
+ void *log = (void *)((uintptr_t)event_log.buffer + event_log.pos);
+ u32 event_size = size + tcg_event_final_size(digest_list);
+ struct efi_tcg2_final_events_table *final_event;
+ efi_status_t ret = EFI_SUCCESS;
- final_event =
- (struct efi_tcg2_final_events_table *)(event_log.final_buffer);
- final_event->number_of_events++;
- event_log.final_pos += pos;
+ /* if ExitBootServices hasn't been called update the normal log */
+ if (!event_log.ebs_called) {
+ if (event_log.truncated ||
+ event_log.pos + event_size > TPM2_EVENT_LOG_SIZE) {
+ event_log.truncated = true;
+ return EFI_VOLUME_FULL;
+ }
+ put_event(pcr_index, event_type, digest_list, size, event, log);
+ event_log.pos += event_size;
+ event_log.last_event_size = event_size;
}
- return EFI_SUCCESS;
+ if (!event_log.get_event_called)
+ return ret;
+
+ /* if GetEventLog has been called update FinalEventLog as well */
+ if (event_log.final_pos + event_size > TPM2_EVENT_LOG_SIZE)
+ return EFI_VOLUME_FULL;
+
+ log = (void *)((uintptr_t)event_log.final_buffer + event_log.final_pos);
+ put_event(pcr_index, event_type, digest_list, size, event, log);
+
+ final_event = event_log.final_buffer;
+ final_event->number_of_events++;
+ event_log.final_pos += event_size;
+
+ return ret;
}
/**
event_log.pos = 0;
event_log.last_event_size = 0;
event_log.get_event_called = false;
+ event_log.ebs_called = false;
event_log.truncated = false;
/*
&var_data_size);
if (!bootvar) {
- log_info("%ls not found\n", boot_name);
+ log_debug("%ls not found\n", boot_name);
continue;
}
EFI_ENTRY("%p, %p", event, context);
+ event_log.ebs_called = true;
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS)
goto out;
efi_status_t ret = EFI_SUCCESS;
struct udevice *dev;
struct efi_event *event;
+ u32 err;
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS) {
return EFI_SUCCESS;
}
+ /* initialize the TPM as early as possible. */
+ err = tpm_startup(dev, TPM_ST_CLEAR);
+ if (err) {
+ log_err("TPM startup failed\n");
+ goto fail;
+ }
+
ret = efi_init_event_log();
if (ret != EFI_SUCCESS)
goto fail;
#include <efi_selftest.h>
+static efi_guid_t guid_before_exit_boot_services =
+ EFI_GUID(0x8be0e274, 0x3970, 0x4b44, 0x80, 0xc5,
+ 0x1a, 0xb9, 0x50, 0x2f, 0x3b, 0xfc);
+#define CAPACITY 4
+
+struct notification_record {
+ unsigned int count;
+ unsigned int type[CAPACITY];
+};
+
+struct notification_context {
+ struct notification_record *record;
+ unsigned int type;
+};
+
static struct efi_boot_services *boottime;
static struct efi_event *event_notify;
-static unsigned int notification_count;
+struct notification_record record;
+
+struct notification_context context_before = {
+ .record = &record,
+ .type = 1,
+};
+
+struct notification_context context = {
+ .record = &record,
+ .type = 2,
+};
/*
* Notification function, increments the notification count.
* @event notified event
* @context pointer to the notification count
*/
-static void EFIAPI notify(struct efi_event *event, void *context)
+static void EFIAPI ebs_notify(struct efi_event *event, void *context)
{
- unsigned int *count = context;
+ struct notification_context *ctx = context;
+
+ if (ctx->record->count >= CAPACITY)
+ return;
- ++*count;
+ ctx->record->type[ctx->record->count] = ctx->type;
+ ctx->record->count++;
}
/*
boottime = systable->boottime;
- notification_count = 0;
ret = boottime->create_event(EVT_SIGNAL_EXIT_BOOT_SERVICES,
- TPL_CALLBACK, notify,
- (void *)¬ification_count,
+ TPL_CALLBACK, ebs_notify,
+ &context,
&event_notify);
if (ret != EFI_SUCCESS) {
efi_st_error("could not create event\n");
return EFI_ST_FAILURE;
}
+ ret = boottime->create_event_ex(0, TPL_CALLBACK, ebs_notify,
+ &context_before,
+ &guid_before_exit_boot_services,
+ &event_notify);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not create event\n");
+ return EFI_ST_FAILURE;
+ }
+
return EFI_ST_SUCCESS;
}
*/
static int execute(void)
{
- if (notification_count != 1) {
- efi_st_error("ExitBootServices was not notified\n");
+ if (record.count != 2) {
+ efi_st_error("Incorrect event count %u\n", record.count);
+ return EFI_ST_FAILURE;
+ }
+ if (record.type[0] != 1) {
+ efi_st_error("EFI_GROUP_BEFORE_EXIT_BOOT_SERVICE not notified\n");
+ return EFI_ST_FAILURE;
+ }
+ if (record.type[1] != 2) {
+ efi_st_error("EVT_SIGNAL_EXIT_BOOT_SERVICES was not notified\n");
return EFI_ST_FAILURE;
}
efi_st_exit_boot_services();
- if (notification_count != 1) {
- efi_st_error("ExitBootServices was notified twice\n");
+ if (record.count != 2) {
+ efi_st_error("Incorrect event count %u\n", record.count);
return EFI_ST_FAILURE;
}
return EFI_ST_SUCCESS;
static const efi_guid_t fdt_guid = EFI_FDT_GUID;
static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;
-/*
- * Convert FDT value to host endianness.
+/**
+ * f2h() - convert FDT value to host endianness.
*
- * @val FDT value
- * @return converted value
+ * UEFI code is always low endian. The FDT is big endian.
+ *
+ * @val: FDT value
+ * Return: converted value
*/
static uint32_t f2h(fdt32_t val)
{
char *buf = (char *)&val;
char i;
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
/* Swap the bytes */
i = buf[0]; buf[0] = buf[3]; buf[3] = i;
i = buf[1]; buf[1] = buf[2]; buf[2] = i;
-#endif
- return *(uint32_t *)buf;
+
+ return val;
}
/**
#include <malloc.h>
#include <asm/global_data.h>
+#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
bank_end = end - 1;
lmb_reserve(lmb, sp, bank_end - sp + 1);
+
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ lmb_reserve(lmb, (phys_addr_t)(uintptr_t)_start, gd->mon_len);
+
break;
}
}
config RSA
bool "Use RSA Library"
select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
- select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
+ select RSA_ASPEED_EXP if ASPEED_ACRY
+ select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP && !RSA_ASPEED_EXP
help
RSA support. This enables the RSA algorithm used for FIT image
verification in U-Boot.
Enables driver for RSA modular exponentiation using Freescale cryptographic
accelerator - CAAM.
+config RSA_ASPEED_EXP
+ bool "Enable RSA Modular Exponentiation with ASPEED crypto accelerator"
+ depends on DM && ASPEED_ACRY
+ help
+ Enables driver for RSA modular exponentiation using ASPEED cryptographic
+ accelerator - ACRY
+
endif
unsigned int i;
/* fetch list of already loaded keys in the TPM */
- err = tpm_get_capability(dev, TPM_CAP_HANDLE, TPM_RT_KEY, buf,
+ err = tpm1_get_capability(dev, TPM_CAP_HANDLE, TPM_RT_KEY, buf,
sizeof(buf));
if (err)
return -1;
/* now search a(/ the) key which we can access with the given auth */
for (i = 0; i < key_count; ++i) {
buf_len = sizeof(buf);
- err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
+ err = tpm1_get_pub_key_oiap(dev, key_handles[i], auth, buf, &buf_len);
if (err && err != TPM_AUTHFAIL)
return -1;
if (err)
*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
#endif
- add_vci(e);
+ e = add_vci(e);
#if defined(CONFIG_BOOTP_SUBNETMASK)
*e++ = 1; /* Subnet mask request */
return 0;
}
+ofnode dsa_port_get_ofnode(struct udevice *dev, int port)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct dsa_port_pdata *port_pdata;
+ struct udevice *pdev;
+
+ if (port == pdata->cpu_port)
+ return pdata->cpu_port_node;
+
+ for (device_find_first_child(dev, &pdev);
+ pdev;
+ device_find_next_child(&pdev)) {
+ port_pdata = dev_get_parent_plat(pdev);
+ if (port_pdata->index == port)
+ return dev_ofnode(pdev);
+ }
+
+ return ofnode_null();
+}
+
/* returns the DSA master Ethernet device */
struct udevice *dsa_get_master(struct udevice *dev)
{
struct eth_ops *eth_ops = eth_get_ops(master);
if (eth_ops->set_promisc)
- eth_ops->set_promisc(master, 1);
+ eth_ops->set_promisc(master, true);
return;
}
if [ -n "${KCONFIG_IGNORE_DUPLICATES}" ] || \
! grep -q "$${line%=*}=" include/config/auto.conf; then \
echo "$$line"; \
- fi \
+ fi; \
done > $@
quiet_cmd_u_boot_cfg = CFG $@
cmd_u_boot_cfg = \
$(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
- grep 'define CONFIG_' $@.tmp > $@; \
+ grep 'define CONFIG_' $@.tmp | \
+ sed '/define CONFIG_IS_ENABLED(/d;/define CONFIG_VAL(/d;' > $@; \
rm $@.tmp; \
} || { \
rm $@.tmp; false; \
CONFIG_HIKEY_GPIO
CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
-CONFIG_HOST_MAX_DEVICES
CONFIG_HPS_ALTERAGRP_DBGATCLK
CONFIG_HPS_ALTERAGRP_MAINCLK
CONFIG_HPS_ALTERAGRP_MPUCLK
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
-CONFIG_IDE_SWAP_IO
CONFIG_IMA
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IRAM_STACK
CONFIG_IRAM_TOP
CONFIG_IRDA_BASE
-CONFIG_IS_ENABLED
CONFIG_JFFS2_DEV
CONFIG_JFFS2_LZO
CONFIG_JFFS2_NAND
CONFIG_JRSTARTR_JR0
CONFIG_JTAG_CONSOLE
CONFIG_KEEP_SERVERADDR
-CONFIG_KEYBOARD
CONFIG_KEY_REVOCATION
CONFIG_KIRKWOOD_EGIGA_INIT
CONFIG_KIRKWOOD_GPIO
CONFIG_LBDAF
CONFIG_LCD_ALIGNMENT
CONFIG_LCD_BMP_RLE8
-CONFIG_LCD_DT_SIMPLEFB
CONFIG_LCD_INFO
CONFIG_LCD_INFO_BELOW_LOGO
CONFIG_LCD_IN_PSRAM
CONFIG_NET_MULTI
CONFIG_NET_RETRY_COUNT
CONFIG_NEVER_ASSERT_ODT_TO_CPU
-CONFIG_NFSBOOTCOMMAND
CONFIG_NFS_TIMEOUT
CONFIG_NOBQFMAN
CONFIG_NON_SECURE
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI
CONFIG_QUOTA
-CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOT_NAND
CONFIG_RAMBOOT_SPIFLASH
CONFIG_RAMBOOT_TEXT_BASE
CONFIG_SYS_ATA_DATA_OFFSET
CONFIG_SYS_ATA_IDE0_OFFSET
CONFIG_SYS_ATA_IDE1_OFFSET
-CONFIG_SYS_ATA_PORT_ADDR
CONFIG_SYS_ATA_REG_OFFSET
CONFIG_SYS_ATA_STRIDE
CONFIG_SYS_ATMEL_CPU_NAME
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
CONFIG_SYS_FAULT_MII_ADDR
CONFIG_SYS_FDT_BASE
-CONFIG_SYS_FDT_LOAD_ADDR
CONFIG_SYS_FDT_PAD
CONFIG_SYS_FEC0_IOBASE
CONFIG_SYS_FEC1_IOBASE
CONFIG_UTBIPAR_INIT_TBIPA
CONFIG_U_BOOT_HDR_ADDR
CONFIG_U_BOOT_HDR_SIZE
-CONFIG_VAL
CONFIG_VAR_SIZE_SPL
CONFIG_VERY_BIG_RAM
CONFIG_VIDEO_BCM2835
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2021 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Awk script to parse a text file containing an environment and convert it
+# to a C string which can be compiled into U-Boot.
+
+# The resulting output is:
+#
+# #define CONFIG_EXTRA_ENV_TEXT "<environment here>"
+#
+# If the input is empty, this script outputs a comment instead.
+
+BEGIN {
+ # env holds the env variable we are currently processing
+ env = "";
+ ORS = ""
+}
+
+# Skip empty lines, as these are generated by the clang preprocessor
+NF {
+ do_output = 0
+
+ # Quote quotes
+ gsub("\"", "\\\"")
+
+ # Avoid using the non-POSIX third parameter to match(), by splitting
+ # the work into several steps.
+ has_var = match($0, "^([^ \t=][^ =]*)=(.*)$")
+
+ # Is this the start of a new environment variable?
+ if (has_var) {
+ if (length(env) != 0) {
+ # Record the value of the variable now completed
+ vars[var] = env
+ do_output = 1
+ }
+
+ # Collect the variable name. The value follows the '='
+ match($0, "^([^ \t=][^ =]*)=")
+ var = substr($0, 1, RLENGTH - 1)
+ env = substr($0, RLENGTH + 1)
+
+ # Deal with += which concatenates the new string to the existing
+ # variable. Again we are careful to use POSIX match()
+ if (length(env) != 0 && match(var, "^(.*)[+]$")) {
+ plusname = substr(var, RSTART, RLENGTH - 1)
+ # Allow var\+=val to indicate that the variable name is
+ # var+ and this is not actually a concatenation
+ if (substr(plusname, length(plusname)) == "\\") {
+ # Drop the backslash
+ sub(/\\[+]$/, "+", var)
+ } else {
+ var = plusname
+ env = vars[var] env
+ }
+ }
+ } else {
+ # Change newline to space
+ gsub(/^[ \t]+/, "")
+
+ # Don't keep leading spaces generated by the previous blank line
+ if (length(env) == 0) {
+ env = $0
+ } else {
+ env = env " " $0
+ }
+ }
+}
+
+END {
+ # Record the value of the variable now completed. If the variable is
+ # empty it is not set.
+ if (length(env) != 0) {
+ vars[var] = env
+ do_output = 1
+ }
+
+ if (do_output) {
+ printf("%s", "#define CONFIG_EXTRA_ENV_TEXT \"")
+
+ # Print out all the variables
+ for (var in vars) {
+ env = vars[var]
+ print var "=" vars[var] "\\0"
+ }
+ print "\"\n"
+ }
+}
#
abandonning||abandoning
abigious||ambiguous
+abitrary||arbitrary
abitrate||arbitrate
+abnornally||abnormally
+abnrormal||abnormal
+abord||abort
+aboslute||absolute
abov||above
abreviated||abbreviated
absense||absence
absoulte||absolute
acccess||access
acceess||access
+accelaration||acceleration
acceleratoin||acceleration
accelleration||acceleration
accesing||accessing
accesss||access
accidentaly||accidentally
accidentually||accidentally
+acclerated||accelerated
accoding||according
accomodate||accommodate
accomodates||accommodates
accquire||acquire
accquired||acquired
accross||across
+accumalate||accumulate
+accumalator||accumulator
acessable||accessible
acess||access
+acessing||accessing
achitecture||architecture
acient||ancient
acitions||actions
actived||activated
actualy||actually
acumulating||accumulating
+acumulative||accumulative
acumulator||accumulator
+acutally||actually
adapater||adapter
addional||additional
additionaly||additionally
adddress||address
addreses||addresses
addresss||address
+addrress||address
aditional||additional
aditionally||additionally
aditionaly||additionally
adminstrative||administrative
adress||address
adresses||addresses
+adrresses||addresses
+advertisment||advertisement
adviced||advised
afecting||affecting
againt||against
agaist||against
aggreataon||aggregation
aggreation||aggregation
+ajust||adjust
albumns||albums
alegorical||allegorical
algined||aligned
algorithmical||algorithmically
algoritm||algorithm
algoritms||algorithms
+algorithmn||algorithm
algorrithm||algorithm
algorritm||algorithm
aligment||alignment
allocatote||allocate
allocatrd||allocated
allocte||allocate
+allocted||allocated
allpication||application
alocate||allocate
alogirhtms||algorithms
alot||a lot
alow||allow
alows||allows
+alreay||already
+alredy||already
altough||although
alue||value
ambigious||ambiguous
+ambigous||ambiguous
amoung||among
amout||amount
+amplifer||amplifier
+amplifyer||amplifier
an union||a union
an user||a user
an userspace||a userspace
architechture||architecture
arguement||argument
arguements||arguments
+arithmatic||arithmetic
aritmetic||arithmetic
arne't||aren't
arraival||arrival
asign||assign
asser||assert
assertation||assertion
+assertting||asserting
+assgined||assigned
assiged||assigned
assigment||assignment
assigments||assignments
assistent||assistant
+assocaited||associated
+assocating||associating
assocation||association
associcated||associated
assotiated||associated
+asssert||assert
assum||assume
assumtpion||assumption
asuming||assuming
asycronous||asynchronous
asynchnous||asynchronous
+asynchromous||asynchronous
+asymetric||asymmetric
+asymmeric||asymmetric
+atleast||at least
atomatically||automatically
atomicly||atomically
atempt||attempt
+atrributes||attributes
attachement||attachment
+attatch||attach
attched||attached
+attemp||attempt
attemps||attempts
attemping||attempting
+attepmpt||attempt
+attnetion||attention
attruibutes||attributes
authentification||authentication
+authenicated||authenticated
automaticaly||automatically
automaticly||automatically
automatize||automate
availabe||available
availabled||available
availablity||availability
+availaible||available
availale||available
availavility||availability
availble||available
borad||board
boundry||boundary
brievely||briefly
+brigde||bridge
+broadcase||broadcast
broadcat||broadcast
+bufer||buffer
+bufufer||buffer
cacluated||calculated
+caculate||calculate
caculation||calculation
+cadidate||candidate
+cahces||caches
calender||calendar
calescing||coalescing
calle||called
callibration||calibration
+callled||called
+callser||caller
calucate||calculate
calulate||calculate
cancelation||cancellation
cancle||cancel
+canot||cannot
capabilites||capabilities
+capabilties||capabilities
capabilty||capability
capabitilies||capabilities
+capablity||capability
capatibilities||capabilities
capapbilities||capabilities
+caputure||capture
carefuly||carefully
cariage||carriage
catagory||category
cehck||check
challange||challenge
challanges||challenges
+chache||cache
chanell||channel
changable||changeable
chanined||chained
charcter||character
chcek||check
chck||check
+checksumed||checksummed
checksuming||checksumming
childern||children
childs||children
clared||cleared
closeing||closing
clustred||clustered
+cnfiguration||configuration
coexistance||coexistence
+colescing||coalescing
collapsable||collapsible
colorfull||colorful
comand||command
commited||committed
commiting||committing
committ||commit
+commnunication||communication
commoditiy||commodity
comsume||consume
comsumer||consumer
comsuming||consuming
compability||compatibility
compaibility||compatibility
+comparsion||comparison
compatability||compatibility
compatable||compatible
+compatibililty||compatibility
compatibiliy||compatibility
compatibilty||compatibility
compatiblity||compatibility
complient||compliant
componnents||components
compoment||component
+comppatible||compatible
compres||compress
compresion||compression
comression||compression
+comunicate||communicate
comunication||communication
conbination||combination
conditionaly||conditionally
+conditon||condition
+condtion||condition
conected||connected
-connecetd||connected
+conector||connector
+configration||configuration
+configred||configured
configuartion||configuration
+configuation||configuration
+configued||configured
configuratoin||configuration
configuraton||configuration
configuretion||configuration
configutation||configuration
conider||consider
conjuction||conjunction
+connecetd||connected
connectinos||connections
+connetor||connector
connnection||connection
connnections||connections
consistancy||consistency
contaisn||contains
contant||contact
contence||contents
+contiguos||contiguous
continious||continuous
continous||continuous
continously||continuously
continueing||continuing
contraints||constraints
+contruct||construct
contol||control
contoller||controller
controled||controlled
curently||currently
cylic||cyclic
dafault||default
+deactive||deactivate
deafult||default
deamon||daemon
+debouce||debounce
+decendant||descendant
+decendants||descendants
decompres||decompress
+decsribed||described
decription||description
dectected||detected
defailt||default
+deferal||deferral
+deffered||deferred
defferred||deferred
definate||definite
definately||definitely
+definiation||definition
defintion||definition
defintions||definitions
defualt||default
delares||declares
delaring||declaring
delemiter||delimiter
+delievered||delivered
demodualtor||demodulator
demension||dimension
dependancies||dependencies
dependancy||dependency
dependant||dependent
+dependend||dependent
depreacted||deprecated
depreacte||deprecate
desactivate||deactivate
desciptor||descriptor
desciptors||descriptors
+descripto||descriptor
descripton||description
descrition||description
descritptor||descriptor
desctiptor||descriptor
desriptor||descriptor
desriptors||descriptors
+desination||destination
destionation||destination
+destoried||destroyed
destory||destroy
destoryed||destroyed
destorys||destroys
destroied||destroyed
detabase||database
deteced||detected
+detectt||detect
develope||develop
developement||development
developped||developed
deveolpment||development
devided||divided
deviece||device
+devision||division
diable||disable
+diabled||disabled
+dicline||decline
dictionnary||dictionary
didnt||didn't
diferent||different
differrence||difference
diffrent||different
+differenciate||differentiate
diffrentiate||differentiate
difinition||definition
+digial||digital
+dimention||dimension
dimesions||dimensions
+diconnected||disconnected
+disabed||disabled
+disble||disable
+disgest||digest
+disired||desired
+dispalying||displaying
diplay||display
+directon||direction
+direcly||directly
direectly||directly
+diregard||disregard
disassocation||disassociation
disapear||disappear
disapeared||disappeared
disappared||disappeared
+disbale||disable
+disbaled||disabled
disble||disable
disbled||disabled
disconnet||disconnect
discontinous||discontinuous
+disharge||discharge
+disnabled||disabled
dispertion||dispersion
dissapears||disappears
+dissconect||disconnect
distiction||distinction
+divisable||divisible
+divsiors||divisors
docuentation||documentation
documantation||documentation
documentaion||documentation
documment||document
doesnt||doesn't
+donwload||download
+donwloading||downloading
dorp||drop
dosen||doesn
downlad||download
downlads||downloads
+droped||dropped
+droput||dropout
druing||during
+dyanmic||dynamic
dynmaic||dynamic
+eanable||enable
+eanble||enable
easilly||easily
ecspecially||especially
edditable||editable
editting||editing
efective||effective
+effectivness||effectiveness
efficently||efficiently
ehther||ether
eigth||eight
eletronic||electronic
embeded||embedded
enabledi||enabled
+enbale||enable
+enble||enable
enchanced||enhanced
encorporating||incorporating
encrupted||encrypted
encrypiton||encryption
encryptio||encryption
endianess||endianness
+enpoint||endpoint
enhaced||enhanced
enlightnment||enlightenment
+enqueing||enqueuing
+entires||entries
+entites||entities
entrys||entries
enocded||encoded
+enought||enough
enterily||entirely
enviroiment||environment
enviroment||environment
equivilant||equivalent
eror||error
errorr||error
+errror||error
estbalishment||establishment
etsablishment||establishment
etsbalishment||establishment
+evalute||evaluate
+evalutes||evaluates
+evalution||evaluation
excecutable||executable
exceded||exceeded
+exceds||exceeds
+exceeed||exceed
excellant||excellent
+execeeded||exceeded
+execeeds||exceeds
exeed||exceed
+exeeds||exceeds
+exeuction||execution
existance||existence
existant||existent
exixt||exist
exlcusive||exclusive
exmaple||example
expecially||especially
+experies||expires
explicite||explicit
explicitely||explicitly
explict||explicit
expresion||expression
exprimental||experimental
extened||extended
+exteneded||extended
extensability||extensibility
extention||extension
+extenstion||extension
extracter||extractor
-falied||failed
+faied||failed
+faield||failed
faild||failed
+failded||failed
+failer||failure
faill||fail
failied||failed
faillure||failure
fetaure||feature
fetaures||features
fileystem||filesystem
+fimrware||firmware
fimware||firmware
+firmare||firmware
+firmaware||firmware
firware||firmware
+firwmare||firmware
finanize||finalize
findn||find
finilizes||finalizes
forse||force
fortan||fortran
forwardig||forwarding
+frambuffer||framebuffer
framming||framing
framwork||framework
+frequence||frequency
frequncy||frequency
+frequancy||frequency
frome||from
fucntion||function
fuction||function
fuctions||functions
+fullill||fulfill
+funcation||function
funcion||function
functionallity||functionality
functionaly||functionally
furthur||further
futhermore||furthermore
futrue||future
+gatable||gateable
+gateing||gating
+gauage||gauge
gaurenteed||guaranteed
generiously||generously
genereate||generate
+genereted||generated
genric||generic
globel||global
grabing||grabbing
grahical||graphical
grahpical||graphical
+granularty||granularity
grapic||graphic
grranted||granted
guage||gauge
halfs||halves
hander||handler
handfull||handful
+hanlde||handle
hanled||handled
happend||happened
+hardare||hardware
harware||hardware
+havind||having
heirarchically||hierarchically
+heirarchy||hierarchy
helpfull||helpful
+hearbeat||heartbeat
+heterogenous||heterogeneous
+hexdecimal||hexadecimal
hybernate||hibernate
hierachy||hierarchy
hierarchie||hierarchy
+homogenous||homogeneous
howver||however
hsould||should
hypervior||hypervisor
identidier||identifier
iligal||illegal
illigal||illegal
+illgal||illegal
+iomaped||iomapped
imblance||imbalance
immeadiately||immediately
immedaite||immediate
+immedate||immediate
immediatelly||immediately
immediatly||immediately
immidiate||immediate
+immutible||immutable
impelentation||implementation
impementated||implemented
implemantation||implementation
incomming||incoming
incompatabilities||incompatibilities
incompatable||incompatible
+incompatble||incompatible
inconsistant||inconsistent
increas||increase
incremeted||incremented
incrment||increment
+incuding||including
+inculde||include
indendation||indentation
indended||intended
independant||independent
indiate||indicate
indicat||indicate
inexpect||inexpected
+inferface||interface
+infinit||infinite
infomation||information
informatiom||information
informations||information
initation||initiation
initators||initiators
initialiazation||initialization
+initializationg||initialization
initializiation||initialization
+initialze||initialize
initialzed||initialized
+initialzing||initializing
initilization||initialization
initilize||initialize
+initliaze||initialize
+initilized||initialized
inofficial||unofficial
+inrerface||interface
insititute||institute
+instace||instance
instal||install
+instanciate||instantiate
instanciated||instantiated
+instuments||instruments
+insufficent||insufficient
inteface||interface
integreated||integrated
integrety||integrity
interchangable||interchangeable
interferring||interfering
interger||integer
+intergrated||integrated
intermittant||intermittent
internel||internal
interoprability||interoperability
interuupt||interrupt
+interupt||interrupt
+interupts||interrupts
interrface||interface
interrrupt||interrupt
interrup||interrupt
interrups||interrupts
interruptted||interrupted
interupted||interrupted
-interupt||interrupt
+intiailized||initialized
intial||initial
intialisation||initialisation
intialised||initialised
intialized||initialized
intialize||initialize
intregral||integral
+intrerrupt||interrupt
intrrupt||interrupt
intterrupt||interrupt
intuative||intuitive
+inavlid||invalid
invaid||invalid
+invaild||invalid
+invailid||invalid
invald||invalid
invalde||invalid
invalide||invalid
invididual||individual
invokation||invocation
invokations||invocations
+ireelevant||irrelevant
irrelevent||irrelevant
isnt||isn't
isssue||issue
+issus||issues
+iteraions||iterations
iternations||iterations
itertation||iteration
itslef||itself
jave||java
jeffies||jiffies
+jumpimng||jumping
juse||just
jus||just
kown||known
langugage||language
lauch||launch
layed||laid
+legnth||length
leightweight||lightweight
lengh||length
lenght||length
librairies||libraries
libraris||libraries
licenceing||licencing
+limted||limited
+logaritmic||logarithmic
loggging||logging
loggin||login
logile||logfile
+loobpack||loopback
loosing||losing
losted||lost
+maangement||management
machinary||machinery
+maibox||mailbox
maintainance||maintenance
maintainence||maintenance
maintan||maintain
makeing||making
+mailformed||malformed
malplaced||misplaced
malplace||misplace
managable||manageable
+managament||management
managment||management
mangement||management
+manger||manager
manoeuvering||maneuvering
+manufaucturing||manufacturing
mappping||mapping
+maping||mapping
+matchs||matches
mathimatical||mathematical
mathimatic||mathematic
mathimatics||mathematics
+maximium||maximum
maxium||maximum
mechamism||mechanism
meetign||meeting
+memeory||memory
+memmber||member
+memoery||memory
+memroy||memory
ment||meant
mergable||mergeable
mesage||message
messgaes||messages
messsage||message
messsages||messages
+metdata||metadata
micropone||microphone
microprocesspr||microprocessor
+migrateable||migratable
milliseonds||milliseconds
minium||minimum
minimam||minimum
+miniumum||minimum
minumum||minimum
misalinged||misaligned
miscelleneous||miscellaneous
mispelt||misspelt
mising||missing
mismactch||mismatch
+missign||missing
missmanaged||mismanaged
missmatch||mismatch
+misssing||missing
miximum||maximum
mmnemonic||mnemonic
mnay||many
+modfiy||modify
+modifer||modifier
modulues||modules
momery||memory
memomry||memory
+monitring||monitoring
monochorome||monochrome
monochromo||monochrome
monocrome||monochrome
mopdule||module
mroe||more
+multipler||multiplier
mulitplied||multiplied
multidimensionnal||multidimensional
+multipe||multiple
multple||multiple
mumber||number
muticast||multicast
nescessary||necessary
nessessary||necessary
noticable||noticeable
+notication||notification
notications||notifications
+notifcations||notifications
notifed||notified
+notity||notify
+nubmer||number
numebr||number
numner||number
obtaion||obtain
+obusing||abusing
occassionally||occasionally
occationally||occasionally
occurance||occurrence
occurances||occurrences
+occurd||occurred
occured||occurred
occurence||occurrence
occure||occurred
-occured||occurred
occuring||occurring
+offser||offset
offet||offset
+offlaod||offload
+offloded||offloaded
+offseting||offsetting
omited||omitted
omiting||omitting
omitt||omit
ommitted||omitted
onself||oneself
ony||only
+openning||opening
operatione||operation
opertaions||operations
+opportunies||opportunities
optionnal||optional
optmizations||optimizations
orientatied||orientated
orientied||oriented
orignal||original
+originial||original
otherise||otherwise
ouput||output
oustanding||outstanding
overaall||overall
overhread||overhead
overlaping||overlapping
+overflw||overflow
+overlfow||overflow
overide||override
overrided||overridden
overriden||overridden
+overrrun||overrun
overun||overrun
overwritting||overwriting
overwriten||overwritten
packge||package
packtes||packets
pakage||package
+paket||packet
pallette||palette
paln||plan
paramameters||parameters
parametised||parametrised
paramter||parameter
paramters||parameters
+parmaters||parameters
particuarly||particularly
particularily||particularly
+partion||partition
+partions||partitions
partiton||partition
pased||passed
passin||passing
pathes||paths
+pattrns||patterns
pecularities||peculiarities
peformance||performance
+peforming||performing
peice||piece
pendantic||pedantic
peprocessor||preprocessor
+perfomance||performance
perfoming||performing
+perfomring||performing
+periperal||peripheral
+peripherial||peripheral
permissons||permissions
peroid||period
persistance||persistence
persistant||persistent
+phoneticly||phonetically
plalform||platform
+platfoem||platform
platfrom||platform
plattform||platform
pleaes||please
posible||possible
positon||position
possibilites||possibilities
+potocol||protocol
powerfull||powerful
+pramater||parameter
+preamle||preamble
preample||preamble
preapre||prepare
preceeded||preceded
preemptable||preemptible
prefered||preferred
prefferably||preferably
+prefitler||prefilter
+preform||perform
premption||preemption
prepaired||prepared
+prepate||prepare
+preperation||preparation
+preprare||prepare
pressre||pressure
+presuambly||presumably
+previosuly||previously
primative||primitive
princliple||principle
priorty||priority
privilage||privilege
priviledge||privilege
priviledges||privileges
+privleges||privileges
probaly||probably
procceed||proceed
proccesors||processors
processsing||processing
procteted||protected
prodecure||procedure
+progamming||programming
progams||programs
progess||progress
+programable||programmable
programers||programmers
programm||program
programms||programs
progresss||progress
+prohibitted||prohibited
+prohibitting||prohibiting
promiscous||promiscuous
promps||prompts
pronnounced||pronounced
propery||property
propigate||propagate
propigation||propagation
+propogation||propagation
propogate||propagate
prosess||process
protable||portable
protcol||protocol
protecion||protection
+protedcted||protected
protocoll||protocol
promixity||proximity
psudo||pseudo
psuedo||pseudo
psychadelic||psychedelic
+purgable||purgeable
pwoer||power
+queing||queuing
quering||querying
+queus||queues
randomally||randomly
raoming||roaming
reasearcher||researcher
reasearchers||researchers
reasearch||research
+receieve||receive
recepient||recipient
+recevied||received
receving||receiving
+recievd||received
recieved||received
recieve||receive
reciever||receiver
recieves||receives
+recieving||receiving
recogniced||recognised
recognizeable||recognizable
recommanded||recommended
recyle||recycle
redircet||redirect
redirectrion||redirection
+redundacy||redundancy
reename||rename
refcounf||refcount
refence||reference
refernces||references
refernnce||reference
refrence||reference
+registed||registered
registerd||registered
+registeration||registration
registeresd||registered
registerred||registered
registes||registers
reigstration||registration
releated||related
relevent||relevant
+reloade||reload
remoote||remote
remore||remote
removeable||removable
reponse||response
representaion||representation
reqeust||request
+reqister||register
+requed||requeued
requestied||requested
requiere||require
requirment||requirement
requred||required
requried||required
requst||request
+requsted||requested
+reregisteration||reregistration
reseting||resetting
+reseved||reserved
+reseverd||reserved
resizeable||resizable
resouce||resource
resouces||resources
resoures||resources
responce||response
+resrouce||resource
ressizes||resizes
ressource||resource
ressources||resources
+restesting||retesting
+resumbmitting||resubmitting
retransmited||retransmitted
retreived||retrieved
retreive||retrieve
+retreiving||retrieving
retrive||retrieve
+retrived||retrieved
+retrun||return
+retun||return
retuned||returned
reudce||reduce
reuest||request
safly||safely
safty||safety
savable||saveable
+scaleing||scaling
scaned||scanned
scaning||scanning
scarch||search
+schdule||schedule
seach||search
searchs||searches
+secion||section
secquence||sequence
secund||second
segement||segment
+seleted||selected
+semaphone||semaphore
+senario||scenario
senarios||scenarios
sentivite||sensitive
separatly||separately
sepcify||specify
-sepc||spec
seperated||separated
seperately||separately
seperate||separate
seperatly||separately
seperator||separator
sepperate||separate
+seqeunce||sequence
+seqeuncer||sequencer
+seqeuencer||sequencer
sequece||sequence
+sequemce||sequence
sequencial||sequential
+serivce||service
serveral||several
+servive||service
setts||sets
settting||setting
+shapshot||snapshot
shotdown||shutdown
shoud||should
shouldnt||shouldn't
shrinked||shrunk
siginificantly||significantly
signabl||signal
+significanly||significantly
similary||similarly
similiar||similar
simlar||similar
singal||signal
singed||signed
sleeped||slept
+sliped||slipped
+softwade||software
softwares||software
+soley||solely
+souce||source
speach||speech
specfic||specific
+specfield||specified
speciefied||specified
specifc||specific
specifed||specified
specificatin||specification
specificaton||specification
+specificed||specified
specifing||specifying
+specifiy||specify
specifiying||specifying
speficied||specified
speicify||specify
standardss||standards
standartization||standardization
standart||standard
+standy||standby
+stardard||standard
staticly||statically
+statuss||status
stoped||stopped
+stoping||stopping
stoppped||stopped
straming||streaming
struc||struct
subdirectoires||subdirectories
suble||subtle
substract||subtract
+submited||submitted
submition||submission
+succeded||succeeded
+suceed||succeed
succesfully||successfully
succesful||successful
successed||succeeded
successfull||successful
successfuly||successfully
sucessfully||successfully
+sucessful||successful
sucess||success
superflous||superfluous
superseeded||superseded
suppoted||supported
suppported||supported
suppport||support
+supprot||support
supress||suppress
surpressed||suppressed
surpresses||suppresses
susbsystem||subsystem
suspeneded||suspended
+suspsend||suspend
suspicously||suspiciously
swaping||swapping
switchs||switches
swithed||switched
swithing||switching
swtich||switch
+syfs||sysfs
symetric||symmetric
synax||syntax
synchonized||synchronized
+synchronuously||synchronously
syncronize||synchronize
syncronized||synchronized
syncronizing||synchronizing
sytem||system
sythesis||synthesis
taht||that
+tansmit||transmit
targetted||targeted
targetting||targeting
+taskelt||tasklet
teh||the
temorary||temporary
temproarily||temporarily
+temperture||temperature
+thead||thread
therfore||therefore
thier||their
threds||threads
+threee||three
threshhold||threshold
thresold||threshold
throught||through
+trackling||tracking
troughput||throughput
+trys||tries
thses||these
+tiggers||triggers
tiggered||triggered
tipically||typically
+timeing||timing
timout||timeout
tmis||this
+toogle||toggle
torerable||tolerable
+traget||target
+traking||tracking
tramsmitted||transmitted
tramsmit||transmit
tranasction||transaction
+tranceiver||transceiver
tranfer||transfer
+tranmission||transmission
+transcevier||transceiver
transciever||transceiver
transferd||transferred
transfered||transferred
trasfer||transfer
trasmission||transmission
treshold||threshold
+triggerd||triggered
+trigerred||triggered
trigerring||triggering
trun||turn
tunning||tuning
tyep||type
udpate||update
uesd||used
+uknown||unknown
+usccess||success
uncommited||uncommitted
+uncompatible||incompatible
unconditionaly||unconditionally
+undeflow||underflow
underun||underrun
unecessary||unnecessary
unexecpted||unexpected
unexpexted||unexpected
unfortunatelly||unfortunately
unifiy||unify
+uniterrupted||uninterrupted
unintialized||uninitialized
+unitialized||uninitialized
unkmown||unknown
unknonw||unknown
+unknouwn||unknown
unknow||unknown
unkown||unknown
+unamed||unnamed
+uneeded||unneeded
unneded||unneeded
unneccecary||unnecessary
unneccesary||unnecessary
unneedingly||unnecessarily
unnsupported||unsupported
unmached||unmatched
+unprecise||imprecise
unregester||unregister
unresgister||unregister
unrgesiter||unregister
unsuccessfull||unsuccessful
unsuported||unsupported
untill||until
+ununsed||unused
unuseful||useless
+unvalid||invalid
upate||update
+upsupported||unsupported
usefule||useful
usefull||useful
usege||usage
usera||users
usualy||usually
+usupported||unsupported
utilites||utilities
utillities||utilities
utilties||utilities
varient||variant
vaule||value
verbse||verbose
+veify||verify
+veriosn||version
verisons||versions
verison||version
verson||version
virtiual||virtual
visiters||visitors
vitual||virtual
+vunerable||vulnerable
wakeus||wakeups
+wathdog||watchdog
wating||waiting
wiat||wait
wether||whether
wirte||write
withing||within
wnat||want
+wont||won't
workarould||workaround
writeing||writing
writting||writing
+wtih||with
zombe||zombie
zomebie||zombie
return 0;
}
DM_TEST(dm_test_ofnode_for_each_compatible_node, UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_string(struct unit_test_state *uts)
+{
+ const char **val;
+ const char *out;
+ ofnode node;
+
+ node = ofnode_path("/a-test");
+ ut_assert(ofnode_valid(node));
+
+ /* single string */
+ ut_asserteq(1, ofnode_read_string_count(node, "str-value"));
+ ut_assertok(ofnode_read_string_index(node, "str-value", 0, &out));
+ ut_asserteq_str("test string", out);
+ ut_asserteq(0, ofnode_stringlist_search(node, "str-value",
+ "test string"));
+ ut_asserteq(1, ofnode_read_string_list(node, "str-value", &val));
+ ut_asserteq_str("test string", val[0]);
+ ut_assertnull(val[1]);
+ free(val);
+
+ /* list of strings */
+ ut_asserteq(5, ofnode_read_string_count(node, "mux-control-names"));
+ ut_assertok(ofnode_read_string_index(node, "mux-control-names", 0,
+ &out));
+ ut_asserteq_str("mux0", out);
+ ut_asserteq(0, ofnode_stringlist_search(node, "mux-control-names",
+ "mux0"));
+ ut_asserteq(5, ofnode_read_string_list(node, "mux-control-names",
+ &val));
+ ut_asserteq_str("mux0", val[0]);
+ ut_asserteq_str("mux1", val[1]);
+ ut_asserteq_str("mux2", val[2]);
+ ut_asserteq_str("mux3", val[3]);
+ ut_asserteq_str("mux4", val[4]);
+ ut_assertnull(val[5]);
+ free(val);
+
+ ut_assertok(ofnode_read_string_index(node, "mux-control-names", 4,
+ &out));
+ ut_asserteq_str("mux4", out);
+ ut_asserteq(4, ofnode_stringlist_search(node, "mux-control-names",
+ "mux4"));
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_string, 0);
+
+static int dm_test_ofnode_string_err(struct unit_test_state *uts)
+{
+ const char **val;
+ const char *out;
+ ofnode node;
+
+ /*
+ * Test error codes only on livetree, as they are different with
+ * flattree
+ */
+ node = ofnode_path("/a-test");
+ ut_assert(ofnode_valid(node));
+
+ /* non-existent property */
+ ut_asserteq(-EINVAL, ofnode_read_string_count(node, "missing"));
+ ut_asserteq(-EINVAL, ofnode_read_string_index(node, "missing", 0,
+ &out));
+ ut_asserteq(-EINVAL, ofnode_read_string_list(node, "missing", &val));
+
+ /* empty property */
+ ut_asserteq(-ENODATA, ofnode_read_string_count(node, "bool-value"));
+ ut_asserteq(-ENODATA, ofnode_read_string_index(node, "bool-value", 0,
+ &out));
+ ut_asserteq(-ENODATA, ofnode_read_string_list(node, "bool-value",
+ &val));
+
+ /* badly formatted string list */
+ ut_asserteq(-EILSEQ, ofnode_read_string_count(node, "int64-value"));
+ ut_asserteq(-EILSEQ, ofnode_read_string_index(node, "int64-value", 0,
+ &out));
+ ut_asserteq(-EILSEQ, ofnode_read_string_list(node, "int64-value",
+ &val));
+
+ /* out of range / not found */
+ ut_asserteq(-ENODATA, ofnode_read_string_index(node, "str-value", 1,
+ &out));
+ ut_asserteq(-ENODATA, ofnode_stringlist_search(node, "str-value",
+ "other"));
+
+ /* negative value for index is not allowed, so don't test for that */
+
+ ut_asserteq(-ENODATA, ofnode_read_string_index(node,
+ "mux-control-names", 5,
+ &out));
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_string_err, UT_TESTF_LIVE_TREE);
#include <test/test.h>
#include <test/ut.h>
+static inline bool lmb_is_nomap(struct lmb_property *m)
+{
+ return m->flags & LMB_NOMAP;
+}
+
static int check_lmb(struct unit_test_state *uts, struct lmb *lmb,
phys_addr_t ram_base, phys_size_t ram_size,
unsigned long num_reserved,
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
};
char str[40];
+ int ret;
sprintf(str, "%pUb", guid);
ut_assertok(strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str));
ut_assertok(strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str));
sprintf(str, "%pUL", guid);
ut_assertok(strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str));
+ ret = snprintf(str, 4, "%pUL", guid);
+ ut_asserteq(0, str[3]);
+ ut_asserteq(36, ret);
return 0;
}
}
PRINT_TEST(print_itoa, 0);
+static int snprint(struct unit_test_state *uts)
+{
+ char buf[10] = "xxxxxxxxx";
+ int ret;
+
+ ret = snprintf(buf, 4, "%s:%s", "abc", "def");
+ ut_asserteq(0, buf[3]);
+ ut_asserteq(7, ret);
+ ret = snprintf(buf, 4, "%s:%d", "abc", 9999);
+ ut_asserteq(8, ret);
+ return 0;
+}
+PRINT_TEST(snprint, 0);
+
static int print_xtoa(struct unit_test_state *uts)
{
ut_asserteq_str("7f", simple_xtoa(127));
import u_boot_console_exec_attach
console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig)
-re_ut_test_list = re.compile(r'[^a-zA-Z0-9_]_u_boot_list_2_ut_(.*)_test_2_\1_test_(.*)\s*$')
+re_ut_test_list = re.compile(r'[^a-zA-Z0-9_]_u_boot_list_2_ut_(.*)_test_2_(.*)\s*$')
def generate_ut_subtest(metafunc, fixture_name, sym_path):
"""Provide parametrization for a ut_subtest fixture.
# Copyright (c) 2015 Stephen Warren
# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
-# Generate an HTML-formatted log file containing multiple streams of data,
-# each represented in a well-delineated/-structured fashion.
+"""
+Generate an HTML-formatted log file containing multiple streams of data,
+each represented in a well-delineated/-structured fashion.
+"""
import datetime
import html
"""Clean up any resources managed by this object."""
pass
- def run(self, cmd, cwd=None, ignore_errors=False):
+ def run(self, cmd, cwd=None, ignore_errors=False, stdin=None):
"""Run a command as a sub-process, and log the results.
The output is available at self.output which can be useful if there is
function will simply return if the command cannot be executed
or exits with an error code, otherwise an exception will be
raised if such problems occur.
+ stdin: Input string to pass to the command as stdin (or None)
Returns:
The output as a string.
try:
p = subprocess.Popen(cmd, cwd=cwd,
- stdin=None, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
- (stdout, stderr) = p.communicate()
+ stdin=subprocess.PIPE if stdin else None,
+ stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ (stdout, stderr) = p.communicate(input=stdin)
if stdout is not None:
stdout = stdout.decode('utf-8')
if stderr is not None:
if output and not output.endswith('\n'):
output += '\n'
if exit_status and not exception and not ignore_errors:
- exception = Exception('Exit code: ' + str(exit_status))
+ exception = ValueError('Exit code: ' + str(exit_status))
if exception:
output += str(exception) + '\n'
self.logfile.write(self, output)
raise exception
return output
-class SectionCtxMgr(object):
+class SectionCtxMgr:
"""A context manager for Python's "with" statement, which allows a certain
portion of test code to be logged to a separate section of the log file.
Objects of this type should be created by factory functions in the Logfile
def __exit__(self, extype, value, traceback):
self.log.end_section(self.marker)
-class Logfile(object):
+class Logfile:
"""Generates an HTML-formatted log file containing multiple streams of
data, each represented in a well-delineated/-structured fashion."""
# The set of characters that should be represented as hexadecimal codes in
# the log file.
_nonprint = {ord('%')}
- _nonprint.update({c for c in range(0, 32) if c not in (9, 10)})
- _nonprint.update({c for c in range(127, 256)})
+ _nonprint.update(c for c in range(0, 32) if c not in (9, 10))
+ _nonprint.update(range(127, 256))
def _escape(self, data):
"""Render data format suitable for inclusion in an HTML document.
# Test efi loader implementation
-import pytest
-import u_boot_utils
-
"""
Note: This test relies on boardenv_* containing configuration values to define
which network environment is available for testing. Without this, the parts
}
"""
+import pytest
+import u_boot_utils
+
net_set_up = False
def test_efi_pre_commands(u_boot_console):
env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
if not env_vars:
pytest.skip('No DHCP server available')
- return None
+ return
u_boot_console.run_command('setenv autoload no')
output = u_boot_console.run_command('dhcp')
check_smbios = u_boot_console.config.env.get('env__efi_loader_check_smbios', False)
if check_smbios:
u_boot_console.wait_for('grub>')
- output = u_boot_console.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
+ u_boot_console.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
u_boot_console.wait_for('SMBIOS')
# Then exit cleanly
This function calls the text input EFI selftest.
"""
u_boot_console.run_command(cmd='setenv efi_selftest text input')
- output = u_boot_console.run_command(cmd='bootefi selftest',
- wait_for_prompt=False)
+ u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
m = u_boot_console.p.expect([r'To terminate type \'x\''])
if m != 0:
raise Exception('No prompt for \'text input\' test')
This function calls the extended text input EFI selftest.
"""
u_boot_console.run_command(cmd='setenv efi_selftest extended text input')
- output = u_boot_console.run_command(cmd='bootefi selftest',
- wait_for_prompt=False)
+ u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
m = u_boot_console.p.expect([r'To terminate type \'CTRL\+x\''])
if m != 0:
raise Exception('No prompt for \'text input\' test')
import os
import os.path
from subprocess import call, check_call, CalledProcessError
+import tempfile
import pytest
import u_boot_utils
finally:
if fs_img:
call('rm -f %s' % fs_img, shell=True)
+
+def test_env_text(u_boot_console):
+ """Test the script that converts the environment to a text file"""
+
+ def check_script(intext, expect_val):
+ """Check a test case
+
+ Args:
+ intext: Text to pass to the script
+ expect_val: Expected value of the CONFIG_EXTRA_ENV_TEXT string, or
+ None if we expect it not to be defined
+ """
+ with tempfile.TemporaryDirectory() as path:
+ fname = os.path.join(path, 'infile')
+ with open(fname, 'w') as inf:
+ print(intext, file=inf)
+ result = u_boot_utils.run_and_log(cons, ['awk', '-f', script, fname])
+ if expect_val is not None:
+ expect = '#define CONFIG_EXTRA_ENV_TEXT "%s"\n' % expect_val
+ assert result == expect
+ else:
+ assert result == ''
+
+ cons = u_boot_console
+ script = os.path.join(cons.config.source_dir, 'scripts', 'env2string.awk')
+
+ # simple script with a single var
+ check_script('fred=123', 'fred=123\\0')
+
+ # no vars
+ check_script('', None)
+
+ # two vars
+ check_script('''fred=123
+ernie=456''', 'fred=123\\0ernie=456\\0')
+
+ # blank lines
+ check_script('''fred=123
+
+
+ernie=456
+
+''', 'fred=123\\0ernie=456\\0')
+
+ # append
+ check_script('''fred=123
+ernie=456
+fred+= 456''', 'fred=123 456\\0ernie=456\\0')
+
+ # append from empty
+ check_script('''fred=
+ernie=456
+fred+= 456''', 'fred= 456\\0ernie=456\\0')
+
+ # variable with + in it
+ check_script('fred+ernie=123', 'fred+ernie=123\\0')
+
+ # ignores variables that are empty
+ check_script('''fred=
+fred+=
+ernie=456''', 'ernie=456\\0')
+
+ # single-character env name
+ check_script('''f=123
+e=456
+f+= 456''', 'e=456\\0f=123 456\\0')
+
+ # contains quotes
+ check_script('''fred="my var"
+ernie=another"''', 'fred=\\"my var\\"\\0ernie=another\\"\\0')
+
+ # variable name ending in +
+ check_script('''fred\\+=my var
+fred++= again''', 'fred+=my var again\\0')
+
+ # variable name containing +
+ check_script('''fred+jane=both
+fred+jane+=again
+ernie=456''', 'fred+jane=bothagain\\0ernie=456\\0')
+
+ # multi-line vars - new vars always start at column 1
+ check_script('''fred=first
+ second
+\tthird with tab
+
+ after blank
+ confusing=oops
+ernie=another"''', 'fred=first second third with tab after blank confusing=oops\\0ernie=another\\"\\0')
+
+ # real-world example
+ check_script('''ubifs_boot=
+ env exists bootubipart ||
+ env set bootubipart UBI;
+ env exists bootubivol ||
+ env set bootubivol boot;
+ if ubi part ${bootubipart} &&
+ ubifsmount ubi${devnum}:${bootubivol};
+ then
+ devtype=ubi;
+ run scan_dev_for_boot;
+ fi
+''',
+ 'ubifs_boot=env exists bootubipart || env set bootubipart UBI; '
+ 'env exists bootubivol || env set bootubivol boot; '
+ 'if ubi part ${bootubipart} && ubifsmount ubi${devnum}:${bootubivol}; '
+ 'then devtype=ubi; run scan_dev_for_boot; fi\\0')
# Copyright (c) 2015 Stephen Warren
# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
-# Logic to interact with U-Boot running on real hardware, typically via a
-# physical serial port.
+"""
+Logic to interact with U-Boot running on real hardware, typically via a
+physical serial port.
+"""
import sys
from u_boot_spawn import Spawn
# Copyright (c) 2015 Stephen Warren
# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
-# Logic to interact with the sandbox port of U-Boot, running as a sub-process.
+"""
+Logic to interact with the sandbox port of U-Boot, running as a sub-process.
+"""
import time
from u_boot_spawn import Spawn
# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
-# Logic to spawn a sub-process and interact with its stdio.
+"""
+Logic to spawn a sub-process and interact with its stdio.
+"""
import os
import re
import signal
import select
import time
+import traceback
class Timeout(Exception):
"""An exception sub-class that indicates that a timeout occurred."""
- pass
-class Spawn(object):
+class Spawn:
"""Represents the stdio of a freshly created sub-process. Commands may be
sent to the process, and responses waited for.
os.execvp(args[0], args)
except:
print('CHILD EXECEPTION:')
- import traceback
traceback.print_exc()
finally:
os._exit(255)
try:
self.poll = select.poll()
- self.poll.register(self.fd, select.POLLIN | select.POLLPRI | select.POLLERR | select.POLLHUP | select.POLLNVAL)
+ self.poll.register(self.fd, select.POLLIN | select.POLLPRI | select.POLLERR |
+ select.POLLHUP | select.POLLNVAL)
except:
self.close()
raise
elif os.WIFSIGNALED(status):
signum = os.WTERMSIG(status)
self.exit_code = -signum
- self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum))
+ self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum).name)
self.waited = True
return False, self.exit_code, self.exit_info
# shouldn't and explain why. This is much more friendly than
# just dying with an I/O error
if err.errno == 5: # Input/output error
- alive, exit_code, info = self.checkalive()
+ alive, _, info = self.checkalive()
if alive:
- raise
- else:
- raise ValueError('U-Boot exited with %s' % info)
- else:
- raise
+ raise err
+ raise ValueError('U-Boot exited with %s' % info)
+ raise err
if self.logfile_read:
self.logfile_read.write(c)
self.buf += c
"""
os.close(self.fd)
- for i in range(100):
+ for _ in range(100):
if not self.isalive():
break
time.sleep(0.1)
# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
-# Utility code shared across multiple tests.
+"""
+Utility code shared across multiple tests.
+"""
import hashlib
import inspect
import os
import os.path
-import pytest
+import pathlib
import signal
import sys
import time
import re
+import pytest
def md5sum_data(data):
"""Calculate the MD5 hash of some data.
data = fh.read(*params)
return md5sum_data(data)
-class PersistentRandomFile(object):
+class PersistentRandomFile:
"""Generate and store information about a persistent file containing
random data."""
Nothing.
"""
- for i in range(100):
+ for _ in range(100):
fh = attempt_to_open_file(fn)
if not fh:
return
return
raise Exception('File can still be opened')
-def run_and_log(u_boot_console, cmd, ignore_errors=False):
+def run_and_log(u_boot_console, cmd, ignore_errors=False, stdin=None):
"""Run a command and log its output.
Args:
will simply return if the command cannot be executed or exits with
an error code, otherwise an exception will be raised if such
problems occur.
+ stdin: Input string to pass to the command as stdin (or None)
Returns:
The output as a string.
if isinstance(cmd, str):
cmd = cmd.split()
runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
- output = runner.run(cmd, ignore_errors=ignore_errors)
+ output = runner.run(cmd, ignore_errors=ignore_errors, stdin=stdin)
runner.close()
return output
try:
runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
runner.run(cmd)
- except Exception as e:
- assert(retcode == runner.exit_status)
- assert(msg in runner.output)
+ except Exception:
+ assert retcode == runner.exit_status
+ assert msg in runner.output
else:
raise Exception("Expected an exception with retcode %d message '%s',"
"but it was not raised" % (retcode, msg))
if filename_timestamp < self.module_timestamp:
self.log.action('Removing stale generated file ' +
self.filename)
- os.unlink(self.filename)
+ pathlib.Path(self.filename).unlink()
def __exit__(self, extype, value, traceback):
if extype:
try:
- os.path.unlink(self.filename)
- except:
+ pathlib.Path(self.filename).unlink()
+ except Exception:
pass
return
logged = False
- for i in range(20):
+ for _ in range(20):
filename_timestamp = os.path.getmtime(self.filename)
if filename_timestamp > self.module_timestamp:
break
u-boot-dtb 180 108 u-boot-dtb 80 3b5
image-header bf8 8 image-header bf8
+If an older version of binman is used to list images created by a newer one, it
+is possible that it will contain entry types that are not supported. These still
+show with the correct type, but binman just sees them as blobs (plain binary
+data). Any special features of that etype are not supported by the old binman.
+
Extracting files from images
----------------------------
$ binman extract -i image.bin "*u-boot*" -O outdir
+Some entry types have alternative formats, for example fdtmap which allows
+extracted just the devicetree binary without the fdtmap header::
+
+ $ binman extract -i /tmp/b/odroid-c4/image.bin -f out.dtb -F fdt fdtmap
+ $ fdtdump out.dtb
+ /dts-v1/;
+ // magic: 0xd00dfeed
+ // totalsize: 0x8ab (2219)
+ // off_dt_struct: 0x38
+ // off_dt_strings: 0x82c
+ // off_mem_rsvmap: 0x28
+ // version: 17
+ // last_comp_version: 2
+ // boot_cpuid_phys: 0x0
+ // size_dt_strings: 0x7f
+ // size_dt_struct: 0x7f4
+
+ / {
+ image-node = "binman";
+ image-pos = <0x00000000>;
+ size = <0x0011162b>;
+ ...
+
+Use `-F list` to see what alternative formats are available::
+
+ $ binman extract -i /tmp/b/odroid-c4/image.bin -F list
+ Flag (-F) Entry type Description
+ fdt fdtmap Extract the devicetree blob from the fdtmap
+
Replacing files in an image
---------------------------
You can replace files in an existing firmware image created by binman, provided
-that there is an 'fdtmap' entry in the image. For example:
+that there is an 'fdtmap' entry in the image. For example::
$ binman replace -i image.bin section/cbfs/u-boot
aren't given, it will also try to derive target-specific versions from the
CROSS_COMPILE environment variable during a cross-compilation.
+If the tool is not available in the path you can use BINMAN_TOOLPATHS to specify
+a space-separated list of paths to search, e.g.::
+
+ BINMAN_TOOLPATHS="/tools/g12a /tools/tegra" binman ...
+
+
+External blobs
+--------------
+
+Binary blobs, even if the source code is available, complicate building
+firmware. The instructions can involve multiple steps and the binaries may be
+hard to build or obtain. Binman at least provides a unified description of how
+to build the final image, no matter what steps are needed to get there.
+
+Binman also provides a `blob-ext` entry type that pulls in a binary blob from an
+external file. If the file is missing, binman can optionally complete the build
+and just report a warning. Use the `-M/--allow-missing` option to enble this.
+This is useful in CI systems which want to check that everything is correct but
+don't have access to the blobs.
+
+If the blobs are in a different directory, you can specify this with the `-I`
+option.
+
+For U-Boot, you can use set the BINMAN_INDIRS environment variable to provide a
+space-separated list of directories to search for binary blobs::
+
+ BINMAN_INDIRS="odroid-c4/fip/g12a \
+ odroid-c4/build/board/hardkernel/odroidc4/firmware \
+ odroid-c4/build/scp_task" binman ...
Code coverage
-------------
# Copyright (c) 2016 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
#
-# Command-line parser for binman
-#
+"""Command-line parser for binman"""
+
+import argparse
from argparse import ArgumentParser
+import state
+
+def make_extract_parser(subparsers):
+ """make_extract_parser: Make a subparser for the 'extract' command
+
+ Args:
+ subparsers (ArgumentParser): parser to add this one to
+ """
+ extract_parser = subparsers.add_parser('extract',
+ help='Extract files from an image')
+ extract_parser.add_argument('-F', '--format', type=str,
+ help='Select an alternative format for extracted data')
+ extract_parser.add_argument('-i', '--image', type=str, required=True,
+ help='Image filename to extract')
+ extract_parser.add_argument('-f', '--filename', type=str,
+ help='Output filename to write to')
+ extract_parser.add_argument('-O', '--outdir', type=str, default='',
+ help='Path to directory to use for output files')
+ extract_parser.add_argument('paths', type=str, nargs='*',
+ help='Paths within file to extract (wildcard)')
+ extract_parser.add_argument('-U', '--uncompressed', action='store_true',
+ help='Output raw uncompressed data for compressed entries')
+
+
+#pylint: disable=R0903
+class BinmanVersion(argparse.Action):
+ """Handles the -V option to binman
+
+ This reads the version information from a file called 'version' in the same
+ directory as this file.
+
+ If not present it assumes this is running from the U-Boot tree and collects
+ the version from the Makefile.
+
+ The format of the version information is three VAR = VALUE lines, for
+ example:
+
+ VERSION = 2022
+ PATCHLEVEL = 01
+ EXTRAVERSION = -rc2
+ """
+ def __init__(self, nargs=0, **kwargs):
+ super().__init__(nargs=nargs, **kwargs)
+
+ def __call__(self, parser, namespace, values, option_string=None):
+ parser._print_message(f'Binman {state.GetVersion()}\n')
+ parser.exit()
+
def ParseArgs(argv):
"""Parse the binman command-line arguments
Args:
- argv: List of string arguments
+ argv (list of str): List of string arguments
+
Returns:
- Tuple (options, args) with the command-line options and arugments.
+ tuple: (options, args) with the command-line options and arugments.
options provides access to the options (e.g. option.debug)
args is a list of string arguments
"""
parser.add_argument('-v', '--verbosity', default=1,
type=int, help='Control verbosity: 0=silent, 1=warnings, 2=notices, '
'3=info, 4=detail, 5=debug')
+ parser.add_argument('-V', '--version', nargs=0, action=BinmanVersion)
subparsers = parser.add_subparsers(dest='cmd')
subparsers.required = True
build_parser.add_argument('--update-fdt-in-elf', type=str,
help='Update an ELF file with the output dtb: infile,outfile,begin_sym,end_sym')
- entry_parser = subparsers.add_parser('entry-docs',
- help='Write out entry documentation (see entries.rst)')
+ subparsers.add_parser(
+ 'entry-docs', help='Write out entry documentation (see entries.rst)')
list_parser = subparsers.add_parser('ls', help='List files in an image')
list_parser.add_argument('-i', '--image', type=str, required=True,
list_parser.add_argument('paths', type=str, nargs='*',
help='Paths within file to list (wildcard)')
- extract_parser = subparsers.add_parser('extract',
- help='Extract files from an image')
- extract_parser.add_argument('-i', '--image', type=str, required=True,
- help='Image filename to extract')
- extract_parser.add_argument('-f', '--filename', type=str,
- help='Output filename to write to')
- extract_parser.add_argument('-O', '--outdir', type=str, default='',
- help='Path to directory to use for output files')
- extract_parser.add_argument('paths', type=str, nargs='*',
- help='Paths within file to extract (wildcard)')
- extract_parser.add_argument('-U', '--uncompressed', action='store_true',
- help='Output raw uncompressed data for compressed entries')
+ make_extract_parser(subparsers)
replace_parser = subparsers.add_parser('replace',
help='Replace entries in an image')
return entry.ReadData(decomp)
+def ShowAltFormats(image):
+ """Show alternative formats available for entries in the image
+
+ This shows a list of formats available.
+
+ Args:
+ image (Image): Image to check
+ """
+ alt_formats = {}
+ image.CheckAltFormats(alt_formats)
+ print('%-10s %-20s %s' % ('Flag (-F)', 'Entry type', 'Description'))
+ for name, val in alt_formats.items():
+ entry, helptext = val
+ print('%-10s %-20s %s' % (name, entry.etype, helptext))
+
+
def ExtractEntries(image_fname, output_fname, outdir, entry_paths,
- decomp=True):
+ decomp=True, alt_format=None):
"""Extract the data from one or more entries and write it to files
Args:
"""
image = Image.FromFile(image_fname)
+ if alt_format == 'list':
+ ShowAltFormats(image)
+ return
+
# Output an entry to a single file, as a special case
if output_fname:
if not entry_paths:
if len(entry_paths) != 1:
raise ValueError('Must specify exactly one entry path to write with -f')
entry = image.FindEntryPath(entry_paths[0])
- data = entry.ReadData(decomp)
+ data = entry.ReadData(decomp, alt_format)
tools.WriteFile(output_fname, data)
tout.Notice("Wrote %#x bytes to file '%s'" % (len(data), output_fname))
return
tout.Notice('%d entries match and will be written' % len(einfos))
for einfo in einfos:
entry = einfo.entry
- data = entry.ReadData(decomp)
+ data = entry.ReadData(decomp, alt_format)
path = entry.GetPath()[1:]
fname = os.path.join(outdir, path)
Returns:
List of EntryInfo records that were written
"""
+ image_fname = os.path.abspath(image_fname)
image = Image.FromFile(image_fname)
# Replace an entry from a single file, as a special case
if args.cmd == 'extract':
ExtractEntries(args.image, args.filename, args.outdir, args.paths,
- not args.uncompressed)
+ not args.uncompressed, args.format)
if args.cmd == 'replace':
ReplaceEntries(args.image, args.filename, args.indir, args.paths,
+Entry: blob-ext-list: List of externally built binary blobs
+-----------------------------------------------------------
+
+This is like blob-ext except that a number of blobs can be provided,
+typically with some sort of relationship, e.g. all are DDC parameters.
+
+If any of the external files needed by this llist is missing, binman can
+optionally ignore it and produce a broken image with a warning.
+
+Args:
+ filenames: List of filenames to read and include
+
+
+
Entry: blob-named-by-arg: A blob entry which gets its filename property from its subclass
-----------------------------------------------------------------------------------------
If allow-repack is used then 'orig-offset' and 'orig-size' properties are
added as necessary. See the binman README.
+When extracting files, an alternative 'fdt' format is available for fdtmaps.
+Use `binman extract -F fdt ...` to use this. It will export a devicetree,
+without the fdtmap header, so it can be viewed with `fdtdump`.
+
Entry: files: A set of files arranged in a section
Entry: section: Entry that contains other entries
-------------------------------------------------
-Properties / Entry arguments: (see binman README for more information):
- pad-byte: Pad byte to use when padding
- sort-by-offset: True if entries should be sorted by offset, False if
- they must be in-order in the device tree description
-
- end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
-
- skip-at-start: Number of bytes before the first entry starts. These
- effectively adjust the starting offset of entries. For example,
- if this is 16, then the first entry would start at 16. An entry
- with offset = 20 would in fact be written at offset 4 in the image
- file, since the first 16 bytes are skipped when writing.
- name-prefix: Adds a prefix to the name of every entry in the section
- when writing out the map
- align_default: Default alignment for this section, if no alignment is
- given in the entry
-
-Properties:
- allow_missing: True if this section permits external blobs to be
- missing their contents. The second will produce an image but of
- course it will not work.
-
-Properties:
- _allow_missing: True if this section permits external blobs to be
- missing their contents. The second will produce an image but of
- course it will not work.
+A section is an entry which can contain other entries, thus allowing
+hierarchical images to be created. See 'Sections and hierarchical images'
+in the binman README for more information.
+
+The base implementation simply joins the various entries together, using
+various rules about alignment, etc.
+
+Subclassing
+~~~~~~~~~~~
+
+This class can be subclassed to support other file formats which hold
+multiple entries, such as CBFS. To do this, override the following
+functions. The documentation here describes what your function should do.
+For example code, see etypes which subclass `Entry_section`, or `cbfs.py`
+for a more involved example::
+
+ $ grep -l \(Entry_section tools/binman/etype/*.py
+
+ReadNode()
+ Call `super().ReadNode()`, then read any special properties for the
+ section. Then call `self.ReadEntries()` to read the entries.
+
+ Binman calls this at the start when reading the image description.
+
+ReadEntries()
+ Read in the subnodes of the section. This may involve creating entries
+ of a particular etype automatically, as well as reading any special
+ properties in the entries. For each entry, entry.ReadNode() should be
+ called, to read the basic entry properties. The properties should be
+ added to `self._entries[]`, in the correct order, with a suitable name.
+
+ Binman calls this at the start when reading the image description.
+
+BuildSectionData(required)
+ Create the custom file format that you want and return it as bytes.
+ This likely sets up a file header, then loops through the entries,
+ adding them to the file. For each entry, call `entry.GetData()` to
+ obtain the data. If that returns None, and `required` is False, then
+ this method must give up and return None. But if `required` is True then
+ it should assume that all data is valid.
+
+ Binman calls this when packing the image, to find out the size of
+ everything. It is called again at the end when building the final image.
+
+SetImagePos(image_pos):
+ Call `super().SetImagePos(image_pos)`, then set the `image_pos` values
+ for each of the entries. This should use the custom file format to find
+ the `start offset` (and `image_pos`) of each entry. If the file format
+ uses compression in such a way that there is no offset available (other
+ than reading the whole file and decompressing it), then the offsets for
+ affected entries can remain unset (`None`). The size should also be set
+ if possible.
+
+ Binman calls this after the image has been packed, to update the
+ location that all the entries ended up at.
+
+ReadChildData(child, decomp, alt_format):
+ The default version of this may be good enough, if you are able to
+ implement SetImagePos() correctly. But that is a bit of a bypass, so
+ you can override this method to read from your custom file format. It
+ should read the entire entry containing the custom file using
+ `super().ReadData(True)`, then parse the file to get the data for the
+ given child, then return that data.
+
+ If your file format supports compression, the `decomp` argument tells
+ you whether to return the compressed data (`decomp` is False) or to
+ uncompress it first, then return the uncompressed data (`decomp` is
+ True). This is used by the `binman extract -U` option.
+
+ If your entry supports alternative formats, the alt_format provides the
+ alternative format that the user has selected. Your function should
+ return data in that format. This is used by the 'binman extract -l'
+ option.
+
+ Binman calls this when reading in an image, in order to populate all the
+ entries with the data from that image (`binman ls`).
+
+WriteChildData(child):
+ Binman calls this after `child.data` is updated, to inform the custom
+ file format about this, in case it needs to do updates.
+
+ The default version of this does nothing and probably needs to be
+ overridden for the 'binman replace' command to work. Your version should
+ use `child.data` to update the data for that child in the custom file
+ format.
+
+ Binman calls this when updating an image that has been read in and in
+ particular to update the data for a particular entry (`binman replace`)
+
+Properties / Entry arguments
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+See :ref:`develop/package/binman:Image description format` for more
+information.
+
+align-default
+ Default alignment for this section, if no alignment is given in the
+ entry
+
+pad-byte
+ Pad byte to use when padding
+
+sort-by-offset
+ True if entries should be sorted by offset, False if they must be
+ in-order in the device tree description
+
+end-at-4gb
+ Used to build an x86 ROM which ends at 4GB (2^32)
+
+name-prefix
+ Adds a prefix to the name of every entry in the section when writing out
+ the map
+
+skip-at-start
+ Number of bytes before the first entry starts. These effectively adjust
+ the starting offset of entries. For example, if this is 16, then the
+ first entry would start at 16. An entry with offset = 20 would in fact
+ be written at offset 4 in the image file, since the first 16 bytes are
+ skipped when writing.
Since a section is also an entry, it inherits all the properies of entries
too.
-A section is an entry which can contain other entries, thus allowing
-hierarchical images to be created. See 'Sections and hierarchical images'
-in the binman README for more information.
+Note that the `allow_missing` member controls whether this section permits
+external blobs to be missing their contents. The option will produce an
+image but of course it will not work. It is useful to make sure that
+Continuous Integration systems can build without the binaries being
+available. This is set by the `SetAllowMissing()` method, if
+`--allow-missing` is passed to binman.
self.pad_after = 0
self.offset_unset = False
self.image_pos = None
- self._expand_size = False
+ self.expand_size = False
self.compress = 'none'
self.missing = False
self.external = False
self.allow_missing = False
@staticmethod
- def Lookup(node_path, etype, expanded):
+ def FindEntryClass(etype, expanded):
"""Look up the entry class for a node.
Args:
Returns:
The entry class object if found, else None if not found and expanded
- is True
-
- Raise:
- ValueError if expanded is False and the class is not found
+ is True, else a tuple:
+ module name that could not be found
+ exception received
"""
# Convert something like 'u-boot@0' to 'u_boot' since we are only
# interested in the type.
except ImportError as e:
if expanded:
return None
- raise ValueError("Unknown entry type '%s' in node '%s' (expected etype/%s.py, error '%s'" %
- (etype, node_path, module_name, e))
+ return module_name, e
modules[module_name] = module
# Look up the expected class name
return getattr(module, 'Entry_%s' % module_name)
@staticmethod
- def Create(section, node, etype=None, expanded=False):
+ def Lookup(node_path, etype, expanded, missing_etype=False):
+ """Look up the entry class for a node.
+
+ Args:
+ node_node (str): Path name of Node object containing information
+ about the entry to create (used for errors)
+ etype (str): Entry type to use
+ expanded (bool): Use the expanded version of etype
+ missing_etype (bool): True to default to a blob etype if the
+ requested etype is not found
+
+ Returns:
+ The entry class object if found, else None if not found and expanded
+ is True
+
+ Raise:
+ ValueError if expanded is False and the class is not found
+ """
+ # Convert something like 'u-boot@0' to 'u_boot' since we are only
+ # interested in the type.
+ cls = Entry.FindEntryClass(etype, expanded)
+ if cls is None:
+ return None
+ elif isinstance(cls, tuple):
+ if missing_etype:
+ cls = Entry.FindEntryClass('blob', False)
+ if isinstance(cls, tuple): # This should not fail
+ module_name, e = cls
+ raise ValueError(
+ "Unknown entry type '%s' in node '%s' (expected etype/%s.py, error '%s'" %
+ (etype, node_path, module_name, e))
+ return cls
+
+ @staticmethod
+ def Create(section, node, etype=None, expanded=False, missing_etype=False):
"""Create a new entry for a node.
Args:
- section: Section object containing this node
- node: Node object containing information about the entry to
- create
- etype: Entry type to use, or None to work it out (used for tests)
- expanded: True to use expanded versions of entries, where available
+ section (entry_Section): Section object containing this node
+ node (Node): Node object containing information about the entry to
+ create
+ etype (str): Entry type to use, or None to work it out (used for
+ tests)
+ expanded (bool): Use the expanded version of etype
+ missing_etype (bool): True to default to a blob etype if the
+ requested etype is not found
Returns:
A new Entry object of the correct type (a subclass of Entry)
"""
if not etype:
etype = fdt_util.GetString(node, 'type', node.name)
- obj = Entry.Lookup(node.path, etype, expanded)
+ obj = Entry.Lookup(node.path, etype, expanded, missing_etype)
if obj and expanded:
# Check whether to use the expanded entry
new_etype = etype + '-expanded'
else:
obj = None
if not obj:
- obj = Entry.Lookup(node.path, etype, False)
+ obj = Entry.Lookup(node.path, etype, False, missing_etype)
# Call its constructor to get the object we want.
return obj(section, etype, node)
self.AddEntryInfo(entries, indent, self.name, self.etype, self.size,
self.image_pos, self.uncomp_size, self.offset, self)
- def ReadData(self, decomp=True):
+ def ReadData(self, decomp=True, alt_format=None):
"""Read the data for an entry from the image
This is used when the image has been read in and we want to extract the
# although compressed sections are currently not supported
tout.Debug("ReadChildData section '%s', entry '%s'" %
(self.section.GetPath(), self.GetPath()))
- data = self.section.ReadChildData(self, decomp)
+ data = self.section.ReadChildData(self, decomp, alt_format)
return data
- def ReadChildData(self, child, decomp=True):
+ def ReadChildData(self, child, decomp=True, alt_format=None):
"""Read the data for a particular child entry
This reads data from the parent and extracts the piece that relates to
the given child.
Args:
- child: Child entry to read data for (must be valid)
- decomp: True to decompress any compressed data before returning it;
- False to return the raw, uncompressed data
+ child (Entry): Child entry to read data for (must be valid)
+ decomp (bool): True to decompress any compressed data before
+ returning it; False to return the raw, uncompressed data
+ alt_format (str): Alternative format to read in, or None
Returns:
Data for the child (bytes)
self.ProcessContentsUpdate(data)
self.Detail('Loaded data size %x' % len(data))
+ def GetAltFormat(self, data, alt_format):
+ """Read the data for an extry in an alternative format
+
+ Supported formats are list in the documentation for each entry. An
+ example is fdtmap which provides .
+
+ Args:
+ data (bytes): Data to convert (this should have been produced by the
+ entry)
+ alt_format (str): Format to use
+
+ """
+ pass
+
def GetImage(self):
"""Get the image containing this entry
"""Handle writing the data in a child entry
This should be called on the child's parent section after the child's
- data has been updated. It
+ data has been updated. It should update any data structures needed to
+ validate that the update is successful.
This base-class implementation does nothing, since the base Entry object
does not have any children.
Returns:
True if the section could be updated successfully, False if the
- data is such that the section could not updat
+ data is such that the section could not update
"""
return True
tout.Info("Node '%s': etype '%s': %s selected" %
(node.path, etype, new_etype))
return True
+
+ def CheckAltFormats(self, alt_formats):
+ """Add any alternative formats supported by this entry type
+
+ Args:
+ alt_formats (dict): Dict to add alt_formats to:
+ key: Name of alt format
+ value: Help text
+ """
+ pass
import unittest
from binman import entry
+from binman.etype.blob import Entry_blob
from dtoc import fdt
from dtoc import fdt_util
from patman import tools
self.assertIn("Unknown entry type 'missing' in node '/binman/u-boot'",
str(e.exception))
+ def testMissingEtype(self):
+ """Test use of a blob etype when the requested one is not available"""
+ ent = entry.Entry.Create(None, self.GetNode(), 'missing',
+ missing_etype=True)
+ self.assertTrue(isinstance(ent, Entry_blob))
+ self.assertEquals('missing', ent.etype)
+
+
if __name__ == "__main__":
unittest.main()
self.ReadBlobContents()
return True
- def ReadBlobContents(self):
+ def ReadFileContents(self, pathname):
"""Read blob contents into memory
- This function compresses the data before storing if needed.
+ This function compresses the data before returning if needed.
We assume the data is small enough to fit into memory. If this
is used for large filesystem image that might not be true.
new Entry method which can read in chunks. Then we could copy
the data in chunks and avoid reading it all at once. For now
this seems like an unnecessary complication.
+
+ Args:
+ pathname (str): Pathname to read from
+
+ Returns:
+ bytes: Data read
"""
state.TimingStart('read')
- indata = tools.ReadFile(self._pathname)
+ indata = tools.ReadFile(pathname)
state.TimingAccum('read')
state.TimingStart('compress')
data = self.CompressData(indata)
state.TimingAccum('compress')
+ return data
+
+ def ReadBlobContents(self):
+ data = self.ReadFileContents(self._pathname)
self.SetContents(data)
return True
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for a list of external blobs, not built by U-Boot
+#
+
+import os
+
+from binman.etype.blob import Entry_blob
+from dtoc import fdt_util
+from patman import tools
+from patman import tout
+
+class Entry_blob_ext_list(Entry_blob):
+ """List of externally built binary blobs
+
+ This is like blob-ext except that a number of blobs can be provided,
+ typically with some sort of relationship, e.g. all are DDC parameters.
+
+ If any of the external files needed by this llist is missing, binman can
+ optionally ignore it and produce a broken image with a warning.
+
+ Args:
+ filenames: List of filenames to read and include
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+ self.external = True
+
+ def ReadNode(self):
+ super().ReadNode()
+ self._filenames = fdt_util.GetStringList(self._node, 'filenames')
+ self._pathnames = []
+
+ def ObtainContents(self):
+ missing = False
+ pathnames = []
+ for fname in self._filenames:
+ pathname = tools.GetInputFilename(
+ fname, self.external and self.section.GetAllowMissing())
+ # Allow the file to be missing
+ if not pathname:
+ missing = True
+ pathnames.append(pathname)
+ self._pathnames = pathnames
+
+ if missing:
+ self.SetContents(b'')
+ self.missing = True
+ return True
+
+ data = bytearray()
+ for pathname in pathnames:
+ data += self.ReadFileContents(pathname)
+
+ self.SetContents(data)
+ return True
subnode = state.AddSubnode(self._node, name)
# Read entries again, now that we have some
- self._ReadEntries()
+ self.ReadEntries()
from binman import state
super().__init__(section, etype, node)
- self._cbfs_arg = fdt_util.GetString(node, 'cbfs-arch', 'x86')
self.align_default = None
- self._cbfs_entries = OrderedDict()
- self._ReadSubnodes()
+ self._entries = OrderedDict()
self.reader = None
- def ObtainContents(self, skip=None):
- arch = cbfs_util.find_arch(self._cbfs_arg)
- if arch is None:
- self.Raise("Invalid architecture '%s'" % self._cbfs_arg)
- if self.size is None:
- self.Raise("'cbfs' entry must have a size property")
- cbfs = CbfsWriter(self.size, arch)
- for entry in self._cbfs_entries.values():
- # First get the input data and put it in a file. If not available,
- # try later.
- if entry != skip and not entry.ObtainContents():
- return False
- data = entry.GetData()
- cfile = None
- if entry._type == 'raw':
- cfile = cbfs.add_file_raw(entry._cbfs_name, data,
- entry._cbfs_offset,
- entry._cbfs_compress)
- elif entry._type == 'stage':
- cfile = cbfs.add_file_stage(entry._cbfs_name, data,
- entry._cbfs_offset)
- else:
- entry.Raise("Unknown cbfs-type '%s' (use 'raw', 'stage')" %
- entry._type)
- if cfile:
- entry._cbfs_file = cfile
- data = cbfs.get_data()
- self.SetContents(data)
- return True
+ def ReadNode(self):
+ """Read properties from the atf-fip node"""
+ super().ReadNode()
+ self._cbfs_arg = fdt_util.GetString(self._node, 'cbfs-arch', 'x86')
+ self.ReadEntries()
- def _ReadSubnodes(self):
+ def ReadEntries(self):
"""Read the subnodes to find out what should go in this CBFS"""
for node in self._node.subnodes:
entry = Entry.Create(self, node)
if entry._cbfs_compress is None:
self.Raise("Invalid compression in '%s': '%s'" %
(node.name, compress))
- self._cbfs_entries[entry._cbfs_name] = entry
+ self._entries[entry._cbfs_name] = entry
+
+ def ObtainCfile(self, cbfs, entry):
+ # First get the input data and put it in a file. If not available,
+ # try later.
+ data = entry.GetData()
+ cfile = None
+ if entry._type == 'raw':
+ cfile = cbfs.add_file_raw(entry._cbfs_name, data,
+ entry._cbfs_offset,
+ entry._cbfs_compress)
+ elif entry._type == 'stage':
+ cfile = cbfs.add_file_stage(entry._cbfs_name, data,
+ entry._cbfs_offset)
+ else:
+ entry.Raise("Unknown cbfs-type '%s' (use 'raw', 'stage')" %
+ entry._type)
+ return cfile
+
+ def ObtainContents(self, skip_entry=None):
+ arch = cbfs_util.find_arch(self._cbfs_arg)
+ if arch is None:
+ self.Raise("Invalid architecture '%s'" % self._cbfs_arg)
+ if self.size is None:
+ self.Raise("'cbfs' entry must have a size property")
+ cbfs = CbfsWriter(self.size, arch)
+ for entry in self._entries.values():
+ if entry != skip_entry and not entry.ObtainContents():
+ return False
+ cfile = self.ObtainCfile(cbfs, entry)
+ if cfile:
+ entry._cbfs_file = cfile
+ data = cbfs.get_data()
+ self.SetContents(data)
+ return True
def SetImagePos(self, image_pos):
"""Override this function to set all the entry properties from CBFS
super().SetImagePos(image_pos)
# Now update the entries with info from the CBFS entries
- for entry in self._cbfs_entries.values():
+ for entry in self._entries.values():
cfile = entry._cbfs_file
entry.size = cfile.data_len
entry.offset = cfile.calced_cbfs_offset
def AddMissingProperties(self, have_image_pos):
super().AddMissingProperties(have_image_pos)
- for entry in self._cbfs_entries.values():
+ for entry in self._entries.values():
entry.AddMissingProperties(have_image_pos)
if entry._cbfs_compress:
state.AddZeroProp(entry._node, 'uncomp-size')
def SetCalculatedProperties(self):
"""Set the value of device-tree properties calculated by binman"""
super().SetCalculatedProperties()
- for entry in self._cbfs_entries.values():
+ for entry in self._entries.values():
state.SetInt(entry._node, 'offset', entry.offset)
state.SetInt(entry._node, 'size', entry.size)
state.SetInt(entry._node, 'image-pos', entry.image_pos)
def ListEntries(self, entries, indent):
"""Override this method to list all files in the section"""
super().ListEntries(entries, indent)
- for entry in self._cbfs_entries.values():
+ for entry in self._entries.values():
entry.ListEntries(entries, indent + 1)
def GetEntries(self):
- return self._cbfs_entries
+ return self._entries
- def ReadData(self, decomp=True):
- data = super().ReadData(True)
+ def ReadData(self, decomp=True, alt_format=None):
+ data = super().ReadData(True, alt_format)
return data
- def ReadChildData(self, child, decomp=True):
+ def ReadChildData(self, child, decomp=True, alt_format=None):
if not self.reader:
- data = super().ReadData(True)
+ data = super().ReadData(True, alt_format)
self.reader = cbfs_util.CbfsReader(data)
reader = self.reader
cfile = reader.files.get(child.name)
return cfile.data if decomp else cfile.orig_data
def WriteChildData(self, child):
- self.ObtainContents(skip=child)
+ # Recreate the data structure, leaving the data for this child alone,
+ # so that child.data is used to pack into the FIP.
+ self.ObtainContents(skip_entry=child)
return True
If allow-repack is used then 'orig-offset' and 'orig-size' properties are
added as necessary. See the binman README.
+
+ When extracting files, an alternative 'fdt' format is available for fdtmaps.
+ Use `binman extract -F fdt ...` to use this. It will export a devicetree,
+ without the fdtmap header, so it can be viewed with `fdtdump`.
"""
def __init__(self, section, etype, node):
# Put these here to allow entry-docs and help to work without libfdt
from dtoc.fdt import Fdt
super().__init__(section, etype, node)
+ self.alt_formats = ['fdt']
+
+ def CheckAltFormats(self, alt_formats):
+ alt_formats['fdt'] = self, 'Extract the devicetree blob from the fdtmap'
def _GetFdtmap(self):
"""Build an FDT map from the entries in the current image
processing, e.g. the image-pos properties.
"""
return self.ProcessContentsUpdate(self._GetFdtmap())
+
+ def GetAltFormat(self, data, alt_format):
+ if alt_format == 'fdt':
+ return data[FDTMAP_HDR_LEN:]
state.AddInt(subnode, 'align', self._files_align)
# Read entries again, now that we have some
- self._ReadEntries()
+ self.ReadEntries()
str)])[0]
def ReadNode(self):
- self._ReadSubnodes()
+ self.ReadEntries()
super().ReadNode()
- def _ReadSubnodes(self):
+ def ReadEntries(self):
def _AddNode(base_node, depth, node):
"""Add a node to the FIT
self._ifwi_entries = OrderedDict()
def ReadNode(self):
- self._ReadSubnodes()
+ self.ReadEntries()
super().ReadNode()
def _BuildIfwi(self):
same = orig_data == self.data
return same
- def _ReadSubnodes(self):
+ def ReadEntries(self):
"""Read the subnodes to find out what should go in this IFWI"""
for node in self._node.subnodes:
entry = Entry.Create(self.section, node)
self._args = fdt_util.GetString(self._node, 'args').split(' ')
self._mkimage_entries = OrderedDict()
self.align_default = None
- self._ReadSubnodes()
+ self.ReadEntries()
def ObtainContents(self):
data = b''
self.SetContents(tools.ReadFile(output_fname))
return True
- def _ReadSubnodes(self):
+ def ReadEntries(self):
"""Read the subnodes to find out what should go in this image"""
for node in self._node.subnodes:
entry = Entry.Create(self, node)
class Entry_section(Entry):
"""Entry that contains other entries
- Properties / Entry arguments: (see binman README for more information):
- pad-byte: Pad byte to use when padding
- sort-by-offset: True if entries should be sorted by offset, False if
- they must be in-order in the device tree description
-
- end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
-
- skip-at-start: Number of bytes before the first entry starts. These
- effectively adjust the starting offset of entries. For example,
- if this is 16, then the first entry would start at 16. An entry
- with offset = 20 would in fact be written at offset 4 in the image
- file, since the first 16 bytes are skipped when writing.
- name-prefix: Adds a prefix to the name of every entry in the section
- when writing out the map
- align_default: Default alignment for this section, if no alignment is
- given in the entry
-
- Properties:
- allow_missing: True if this section permits external blobs to be
- missing their contents. The second will produce an image but of
- course it will not work.
+ A section is an entry which can contain other entries, thus allowing
+ hierarchical images to be created. See 'Sections and hierarchical images'
+ in the binman README for more information.
+
+ The base implementation simply joins the various entries together, using
+ various rules about alignment, etc.
+
+ Subclassing
+ ~~~~~~~~~~~
+
+ This class can be subclassed to support other file formats which hold
+ multiple entries, such as CBFS. To do this, override the following
+ functions. The documentation here describes what your function should do.
+ For example code, see etypes which subclass `Entry_section`, or `cbfs.py`
+ for a more involved example::
+
+ $ grep -l \(Entry_section tools/binman/etype/*.py
+
+ ReadNode()
+ Call `super().ReadNode()`, then read any special properties for the
+ section. Then call `self.ReadEntries()` to read the entries.
+
+ Binman calls this at the start when reading the image description.
+
+ ReadEntries()
+ Read in the subnodes of the section. This may involve creating entries
+ of a particular etype automatically, as well as reading any special
+ properties in the entries. For each entry, entry.ReadNode() should be
+ called, to read the basic entry properties. The properties should be
+ added to `self._entries[]`, in the correct order, with a suitable name.
+
+ Binman calls this at the start when reading the image description.
+
+ BuildSectionData(required)
+ Create the custom file format that you want and return it as bytes.
+ This likely sets up a file header, then loops through the entries,
+ adding them to the file. For each entry, call `entry.GetData()` to
+ obtain the data. If that returns None, and `required` is False, then
+ this method must give up and return None. But if `required` is True then
+ it should assume that all data is valid.
+
+ Binman calls this when packing the image, to find out the size of
+ everything. It is called again at the end when building the final image.
+
+ SetImagePos(image_pos):
+ Call `super().SetImagePos(image_pos)`, then set the `image_pos` values
+ for each of the entries. This should use the custom file format to find
+ the `start offset` (and `image_pos`) of each entry. If the file format
+ uses compression in such a way that there is no offset available (other
+ than reading the whole file and decompressing it), then the offsets for
+ affected entries can remain unset (`None`). The size should also be set
+ if possible.
+
+ Binman calls this after the image has been packed, to update the
+ location that all the entries ended up at.
+
+ ReadChildData(child, decomp, alt_format):
+ The default version of this may be good enough, if you are able to
+ implement SetImagePos() correctly. But that is a bit of a bypass, so
+ you can override this method to read from your custom file format. It
+ should read the entire entry containing the custom file using
+ `super().ReadData(True)`, then parse the file to get the data for the
+ given child, then return that data.
+
+ If your file format supports compression, the `decomp` argument tells
+ you whether to return the compressed data (`decomp` is False) or to
+ uncompress it first, then return the uncompressed data (`decomp` is
+ True). This is used by the `binman extract -U` option.
+
+ If your entry supports alternative formats, the alt_format provides the
+ alternative format that the user has selected. Your function should
+ return data in that format. This is used by the 'binman extract -l'
+ option.
+
+ Binman calls this when reading in an image, in order to populate all the
+ entries with the data from that image (`binman ls`).
+
+ WriteChildData(child):
+ Binman calls this after `child.data` is updated, to inform the custom
+ file format about this, in case it needs to do updates.
+
+ The default version of this does nothing and probably needs to be
+ overridden for the 'binman replace' command to work. Your version should
+ use `child.data` to update the data for that child in the custom file
+ format.
+
+ Binman calls this when updating an image that has been read in and in
+ particular to update the data for a particular entry (`binman replace`)
+
+ Properties / Entry arguments
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ See :ref:`develop/package/binman:Image description format` for more
+ information.
+
+ align-default
+ Default alignment for this section, if no alignment is given in the
+ entry
+
+ pad-byte
+ Pad byte to use when padding
+
+ sort-by-offset
+ True if entries should be sorted by offset, False if they must be
+ in-order in the device tree description
+
+ end-at-4gb
+ Used to build an x86 ROM which ends at 4GB (2^32)
+
+ name-prefix
+ Adds a prefix to the name of every entry in the section when writing out
+ the map
+
+ skip-at-start
+ Number of bytes before the first entry starts. These effectively adjust
+ the starting offset of entries. For example, if this is 16, then the
+ first entry would start at 16. An entry with offset = 20 would in fact
+ be written at offset 4 in the image file, since the first 16 bytes are
+ skipped when writing.
Since a section is also an entry, it inherits all the properies of entries
too.
- A section is an entry which can contain other entries, thus allowing
- hierarchical images to be created. See 'Sections and hierarchical images'
- in the binman README for more information.
+ Note that the `allow_missing` member controls whether this section permits
+ external blobs to be missing their contents. The option will produce an
+ image but of course it will not work. It is useful to make sure that
+ Continuous Integration systems can build without the binaries being
+ available. This is set by the `SetAllowMissing()` method, if
+ `--allow-missing` is passed to binman.
"""
def __init__(self, section, etype, node, test=False):
if not test:
self._skip_at_start = 0
self._name_prefix = fdt_util.GetString(self._node, 'name-prefix')
self.align_default = fdt_util.GetInt(self._node, 'align-default', 0)
- filename = fdt_util.GetString(self._node, 'filename')
- if filename:
- self._filename = filename
- self._ReadEntries()
+ self.ReadEntries()
- def _ReadEntries(self):
+ def ReadEntries(self):
for node in self._node.subnodes:
if node.name.startswith('hash') or node.name.startswith('signature'):
continue
entry = Entry.Create(self, node,
- expanded=self.GetImage().use_expanded)
+ expanded=self.GetImage().use_expanded,
+ missing_etype=self.GetImage().missing_etype)
entry.ReadNode()
entry.SetPrefix(self._name_prefix)
self._entries[node.name] = entry
"""Raises an error for this section
Args:
- msg: Error message to use in the raise string
+ msg (str): Error message to use in the raise string
Raises:
- ValueError()
+ ValueError: always
"""
raise ValueError("Section '%s': %s" % (self._node.path, msg))
for entry in self._entries.values():
entry.AddMissingProperties(have_image_pos)
- def ObtainContents(self):
- return self.GetEntryContents()
+ def ObtainContents(self, skip_entry=None):
+ return self.GetEntryContents(skip_entry=skip_entry)
def GetPaddedDataForEntry(self, entry, entry_data):
"""Get the data for an entry including any padding
return data
- def _BuildSectionData(self, required):
+ def BuildSectionData(self, required):
"""Build the contents of a section
This places all entries at the right place, dealing with padding before
pad-before and pad-after properties in the section items) since that is
handled by the parent section.
+ This should be overridden by subclasses which want to build their own
+ data structure for the section.
+
Args:
required: True if the data must be present, False if it is OK to
return None
for entry in self._entries.values():
entry_data = entry.GetData(required)
+
+ # This can happen when this section is referenced from a collection
+ # earlier in the image description. See testCollectionSection().
if not required and entry_data is None:
return None
data = self.GetPaddedDataForEntry(entry, entry_data)
This excludes any padding. If the section is compressed, the
compressed data is returned
"""
- data = self._BuildSectionData(required)
+ data = self.BuildSectionData(required)
if data is None:
return None
self.SetContents(data)
self._SortEntries()
self._ExpandEntries()
- data = self._BuildSectionData(True)
+ data = self.BuildSectionData(True)
self.SetContents(data)
self.CheckSize()
return entry
return None
- def GetEntryContents(self):
+ def GetEntryContents(self, skip_entry=None):
"""Call ObtainContents() for each entry in the section
"""
def _CheckDone(entry):
- if not entry.ObtainContents():
- next_todo.append(entry)
+ if entry != skip_entry:
+ if not entry.ObtainContents():
+ next_todo.append(entry)
return entry
todo = self._entries.values()
def ListEntries(self, entries, indent):
"""List the files in the section"""
- Entry.AddEntryInfo(entries, indent, self.name, 'section', self.size,
+ Entry.AddEntryInfo(entries, indent, self.name, self.etype, self.size,
self.image_pos, None, self.offset, self)
for entry in self._entries.values():
entry.ListEntries(entries, indent + 1)
"""
return self._sort
- def ReadData(self, decomp=True):
+ def ReadData(self, decomp=True, alt_format=None):
tout.Info("ReadData path='%s'" % self.GetPath())
- parent_data = self.section.ReadData(True)
+ parent_data = self.section.ReadData(True, alt_format)
offset = self.offset - self.section._skip_at_start
data = parent_data[offset:offset + self.size]
tout.Info(
self.size, len(data)))
return data
- def ReadChildData(self, child, decomp=True):
- tout.Debug("ReadChildData for child '%s'" % child.GetPath())
- parent_data = self.ReadData(True)
+ def ReadChildData(self, child, decomp=True, alt_format=None):
+ tout.Debug(f"ReadChildData for child '{child.GetPath()}'")
+ parent_data = self.ReadData(True, alt_format)
offset = child.offset - self._skip_at_start
tout.Debug("Extract for child '%s': offset %#x, skip_at_start %#x, result %#x" %
(child.GetPath(), child.offset, self._skip_at_start, offset))
tout.Info("%s: Decompressing data size %#x with algo '%s' to data size %#x" %
(child.GetPath(), len(indata), child.compress,
len(data)))
+ if alt_format:
+ new_data = child.GetAltFormat(data, alt_format)
+ if new_data is not None:
+ data = new_data
return data
def WriteChildData(self, child):
nothing.
Args:
- missing: List of missing properties / entry args, each a string
+ entry (Entry): Entry to raise the error on
+ missing (list of str): List of missing properties / entry args, each
+ a string
"""
if not self._ignore_missing:
- entry.Raise('Missing required properties/entry args: %s' %
- (', '.join(missing)))
+ missing = ', '.join(missing)
+ entry.Raise(f'Missing required properties/entry args: {missing}')
+
+ def CheckAltFormats(self, alt_formats):
+ for entry in self._entries.values():
+ entry.CheckAltFormats(alt_formats)
self._DoReadFile('107_cbfs_no_size.dts')
self.assertIn('entry must have a size property', str(e.exception))
- def testCbfsNoCOntents(self):
+ def testCbfsNoContents(self):
"""Test handling of a CBFS entry which does not provide contentsy"""
with self.assertRaises(ValueError) as e:
self._DoReadFile('108_cbfs_no_contents.dts')
def testCollectionSection(self):
"""Test a collection where a section must be built first"""
# Sections never have their contents when GetData() is called, but when
- # _BuildSectionData() is called with required=True, a section will force
+ # BuildSectionData() is called with required=True, a section will force
# building the contents, producing an error is anything is still
# missing.
data = self._DoReadFile('199_collection_section.dts')
str(e.exception),
"Not enough space in '.*u_boot_binman_embed_sm' for data length.*")
+ def testVersion(self):
+ """Test we can get the binman version"""
+ version = '(unreleased)'
+ self.assertEqual(version, state.GetVersion(self._indir))
+
+ with self.assertRaises(SystemExit):
+ with test_util.capture_sys_output() as (_, stderr):
+ self._DoBinman('-V')
+ self.assertEqual('Binman %s\n' % version, stderr.getvalue())
+
+ # Try running the tool too, just to be safe
+ result = self._RunBinman('-V')
+ self.assertEqual('Binman %s\n' % version, result.stderr)
+
+ # Set up a version file to make sure that works
+ version = 'v2025.01-rc2'
+ tools.WriteFile(os.path.join(self._indir, 'version'), version,
+ binary=False)
+ self.assertEqual(version, state.GetVersion(self._indir))
+
+ def testAltFormat(self):
+ """Test that alternative formats can be used to extract"""
+ self._DoReadFileRealDtb('213_fdtmap_alt_format.dts')
+
+ try:
+ tmpdir, updated_fname = self._SetupImageInTmpdir()
+ with test_util.capture_sys_output() as (stdout, _):
+ self._DoBinman('extract', '-i', updated_fname, '-F', 'list')
+ self.assertEqual(
+ '''Flag (-F) Entry type Description
+fdt fdtmap Extract the devicetree blob from the fdtmap
+''',
+ stdout.getvalue())
+
+ dtb = os.path.join(tmpdir, 'fdt.dtb')
+ self._DoBinman('extract', '-i', updated_fname, '-F', 'fdt', '-f',
+ dtb, 'fdtmap')
+
+ # Check that we can read it and it can be scanning, meaning it does
+ # not have a 16-byte fdtmap header
+ data = tools.ReadFile(dtb)
+ dtb = fdt.Fdt.FromData(data)
+ dtb.Scan()
+
+ # Now check u-boot which has no alt_format
+ fname = os.path.join(tmpdir, 'fdt.dtb')
+ self._DoBinman('extract', '-i', updated_fname, '-F', 'dummy',
+ '-f', fname, 'u-boot')
+ data = tools.ReadFile(fname)
+ self.assertEqual(U_BOOT_DATA, data)
+
+ finally:
+ shutil.rmtree(tmpdir)
+
+ def testExtblobList(self):
+ """Test an image with an external blob list"""
+ data = self._DoReadFile('215_blob_ext_list.dts')
+ self.assertEqual(REFCODE_DATA + FSP_M_DATA, data)
+
+ def testExtblobListMissing(self):
+ """Test an image with a missing external blob"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('216_blob_ext_list_missing.dts')
+ self.assertIn("Filename 'missing-file' not found in input path",
+ str(e.exception))
+
+ def testExtblobListMissingOk(self):
+ """Test an image with an missing external blob that is allowed"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self._DoTestFile('216_blob_ext_list_missing.dts',
+ allow_missing=True)
+ err = stderr.getvalue()
+ self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
+
if __name__ == "__main__":
unittest.main()
to ignore 'u-boot-bin' in this case, and build it ourselves in
binman with 'u-boot-dtb.bin' and 'u-boot.dtb'. See
Entry_u_boot_expanded and Entry_blob_phase for details.
+ missing_etype: Use a default entry type ('blob') if the requested one
+ does not exist in binman. This is useful if an image was created by
+ binman a newer version of binman but we want to list it in an older
+ version which does not support all the entry types.
"""
def __init__(self, name, node, copy_to_orig=True, test=False,
- ignore_missing=False, use_expanded=False):
+ ignore_missing=False, use_expanded=False, missing_etype=False):
super().__init__(None, 'section', node, test=test)
self.copy_to_orig = copy_to_orig
self.name = 'main-section'
self.fdtmap_data = None
self.allow_repack = False
self._ignore_missing = ignore_missing
+ self.missing_etype = missing_etype
self.use_expanded = use_expanded
self.test_section_timeout = False
if not test:
# Return an Image with the associated nodes
root = dtb.GetRoot()
- image = Image('image', root, copy_to_orig=False, ignore_missing=True)
+ image = Image('image', root, copy_to_orig=False, ignore_missing=True,
+ missing_etype=True)
image.image_node = fdt_util.GetString(root, 'image-node', 'image')
image.fdtmap_dtb = dtb
entries = entry.GetEntries()
return entry
- def ReadData(self, decomp=True):
+ def ReadData(self, decomp=True, alt_format=None):
tout.Debug("Image '%s' ReadData(), size=%#x" %
(self.GetPath(), len(self._data)))
return self._data
from patman import tools
from patman import tout
+OUR_PATH = os.path.dirname(os.path.realpath(__file__))
+
# Map an dtb etype to its expected filename
DTB_TYPE_FNAME = {
'u-boot-spl-dtb': 'spl/u-boot-spl.dtb',
for name, seconds in duration.items():
print('%10s: %10.1fms' % (name, seconds * 1000))
+
+def GetVersion(path=OUR_PATH):
+ """Get the version string for binman
+
+ Args:
+ path: Path to 'version' file
+
+ Returns:
+ str: String version, e.g. 'v2021.10'
+ """
+ version_fname = os.path.join(path, 'version')
+ if os.path.exists(version_fname):
+ version = tools.ReadFile(version_fname, binary=False)
+ else:
+ version = '(unreleased)'
+ return version
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ fdtmap {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ blob-ext-list {
+ filenames = "refcode.bin", "fsp_m.bin";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ blob-ext-list {
+ filenames = "refcode.bin", "missing-file";
+ };
+ };
+};
"""
return struct.unpack('>I', val)[0]
+def fdt64_to_cpu(val):
+ """Convert a device tree cell to an integer
+
+ Args:
+ val (list): Value to convert (list of 2 4-character strings representing
+ the cell value)
+
+ Return:
+ int: A native-endian integer value
+ """
+ return fdt32_to_cpu(val[0]) << 32 | fdt32_to_cpu(val[1])
+
def fdt_cells_to_cpu(val, cells):
"""Convert one or two cells to a long integer
value = fdt32_to_cpu(prop.value)
return value
+def GetInt64(node, propname, default=None):
+ """Get a 64-bit integer from a property
+
+ Args:
+ node (Node): Node object to read from
+ propname (str): property name to read
+ default (int): Default value to use if the node/property do not exist
+
+ Returns:
+ int: value read, or default if none
+
+ Raises:
+ ValueError: Property is not of the correct size
+ """
+ prop = node.props.get(propname)
+ if not prop:
+ return default
+ if not isinstance(prop.value, list) or len(prop.value) != 2:
+ raise ValueError("Node '%s' property '%s' should be a list with 2 items for 64-bit values" %
+ (node.name, propname))
+ value = fdt64_to_cpu(prop.value)
+ return value
+
def GetString(node, propname, default=None):
"""Get a string from a property
"a single string" % (node.name, propname))
return value
+def GetStringList(node, propname, default=None):
+ """Get a string list from a property
+
+ Args:
+ node (Node): Node object to read from
+ propname (str): property name to read
+ default (list of str): Default value to use if the node/property do not
+ exist, or None
+
+ Returns:
+ String value read, or default if none
+ """
+ prop = node.props.get(propname)
+ if not prop:
+ return default
+ value = prop.value
+ if not isinstance(value, list):
+ strval = GetString(node, propname)
+ return [strval]
+ return value
+
def GetBool(node, propname, default=False):
"""Get an boolean from a property
(node.name, propname, len(value), 1))
return ord(value[0])
+def GetBytes(node, propname, size, default=None):
+ """Get a set of bytes from a property
+
+ Args:
+ node (Node): Node object to read from
+ propname (str): property name to read
+ size (int): Number of bytes to expect
+ default (bytes): Default value or None
+
+ Returns:
+ bytes: Bytes value read, or default if none
+ """
+ prop = node.props.get(propname)
+ if not prop:
+ return default
+ if len(prop.bytes) != size:
+ raise ValueError("Node '%s' property '%s' has length %d, expecting %d" %
+ (node.name, propname, len(prop.bytes), size))
+ return prop.bytes
+
def GetPhandleList(node, propname):
"""Get a list of phandles from a property
boolval;
maybe-empty-int = <>;
intval = <1>;
+ int64val = /bits/ 64 <0x123456789abcdef0>;
intarray = <2 3 4>;
byteval = [05];
bytearray = [06];
\tbool\t\tboolval;
\tunsigned char\tbytearray[3];
\tunsigned char\tbyteval;
+\tfdt32_t\t\tint64val[2];
\tfdt32_t\t\tintarray[3];
\tfdt32_t\t\tintval;
\tunsigned char\tlongbytearray[9];
\t.boolval\t\t= true,
\t.bytearray\t\t= {0x6, 0x0, 0x0},
\t.byteval\t\t= 0x5,
+\t.int64val\t\t= {0x12345678, 0x9abcdef0},
\t.intarray\t\t= {0x2, 0x3, 0x4},
\t.intval\t\t\t= 0x1,
\t.longbytearray\t\t= {0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,
our_path = os.path.dirname(os.path.realpath(__file__))
sys.path.insert(1, os.path.join(our_path, '..'))
+# Bring in the libfdt module
+sys.path.insert(2, 'scripts/dtc/pylibfdt')
+sys.path.insert(2, os.path.join(our_path, '../../scripts/dtc/pylibfdt'))
+sys.path.insert(2, os.path.join(our_path,
+ '../../build-sandbox_spl/scripts/dtc/pylibfdt'))
+
from dtoc import fdt
from dtoc import fdt_util
-from dtoc.fdt_util import fdt32_to_cpu
+from dtoc.fdt_util import fdt32_to_cpu, fdt64_to_cpu
from fdt import Type, BytesToValue
import libfdt
from patman import command
node = self.dtb.GetNode('/spl-test')
props = self.dtb.GetProps(node)
self.assertEqual(['boolval', 'bytearray', 'byteval', 'compatible',
- 'intarray', 'intval', 'longbytearray',
+ 'int64val', 'intarray', 'intval', 'longbytearray',
'maybe-empty-int', 'notstring', 'stringarray',
'stringval', 'u-boot,dm-pre-reloc'],
sorted(props.keys()))
self.assertEqual(Type.INT, prop.type)
self.assertEqual(1, fdt32_to_cpu(prop.value))
+ prop = self._ConvertProp('int64val')
+ self.assertEqual(Type.INT, prop.type)
+ self.assertEqual(0x123456789abcdef0, fdt64_to_cpu(prop.value))
+
prop = self._ConvertProp('intarray')
self.assertEqual(Type.INT, prop.type)
val = [fdt32_to_cpu(val) for val in prop.value]
self.assertEqual(3, fdt_util.GetInt(self.node, 'missing', 3))
with self.assertRaises(ValueError) as e:
- self.assertEqual(3, fdt_util.GetInt(self.node, 'intarray'))
+ fdt_util.GetInt(self.node, 'intarray')
self.assertIn("property 'intarray' has list value: expecting a single "
'integer', str(e.exception))
+ def testGetInt64(self):
+ self.assertEqual(0x123456789abcdef0,
+ fdt_util.GetInt64(self.node, 'int64val'))
+ self.assertEqual(3, fdt_util.GetInt64(self.node, 'missing', 3))
+
+ with self.assertRaises(ValueError) as e:
+ fdt_util.GetInt64(self.node, 'intarray')
+ self.assertIn(
+ "property 'intarray' should be a list with 2 items for 64-bit values",
+ str(e.exception))
+
def testGetString(self):
self.assertEqual('message', fdt_util.GetString(self.node, 'stringval'))
self.assertEqual('test', fdt_util.GetString(self.node, 'missing',
self.assertIn("property 'stringarray' has list value: expecting a "
'single string', str(e.exception))
+ def testGetStringList(self):
+ self.assertEqual(['message'],
+ fdt_util.GetStringList(self.node, 'stringval'))
+ self.assertEqual(
+ ['multi-word', 'message'],
+ fdt_util.GetStringList(self.node, 'stringarray'))
+ self.assertEqual(['test'],
+ fdt_util.GetStringList(self.node, 'missing', ['test']))
+
def testGetBool(self):
self.assertEqual(True, fdt_util.GetBool(self.node, 'boolval'))
self.assertEqual(False, fdt_util.GetBool(self.node, 'missing'))
self.assertIn("property 'intval' has length 4, expecting 1",
str(e.exception))
+ def testGetBytes(self):
+ self.assertEqual(bytes([5]), fdt_util.GetBytes(self.node, 'byteval', 1))
+ self.assertEqual(None, fdt_util.GetBytes(self.node, 'missing', 3))
+ self.assertEqual(
+ bytes([3]), fdt_util.GetBytes(self.node, 'missing', 3, bytes([3])))
+
+ with self.assertRaises(ValueError) as e:
+ fdt_util.GetBytes(self.node, 'longbytearray', 7)
+ self.assertIn(
+ "Node 'spl-test' property 'longbytearray' has length 9, expecting 7",
+ str(e.exception))
+
+ self.assertEqual(
+ bytes([0, 0, 0, 1]), fdt_util.GetBytes(self.node, 'intval', 4))
+ self.assertEqual(
+ bytes([3]), fdt_util.GetBytes(self.node, 'missing', 3, bytes([3])))
+
def testGetPhandleList(self):
dtb = fdt.FdtScan(find_dtb_file('dtoc_test_phandle.dts'))
node = dtb.GetNode('/phandle-source2')
usage "Invalid number of arguments"
fi
-for nc in netcat nc ; do
+for nc in socat netcat nc ; do
type ${nc} >/dev/null 2>&1 && break
done
# see if ncb is in $PATH
exec ncb ${board_out_port}
+elif [ "${nc}" = "socat" ] ; then
+ # socat does support broadcast
+ while ${nc} STDIO "UDP4-LISTEN:${board_out_port}"; do :; done
+
elif [ -x ${0%/*}/ncb ] ; then
# maybe it's in the same dir as the netconsole script
exec ${0%/*}/ncb ${board_out_port}
fi
) &
pid=$!
-${nc} -u ${ip} ${board_in_port}
+if [ "${nc}" = "socat" ] ; then
+ ${nc} - "UDP4:${ip}:${board_in_port}"
+else
+ ${nc} -u ${ip} ${board_in_port}
+fi
kill ${pid} 2>/dev/null
{
FILE *f;
int i, num;
- uint64_t rela_start, rela_end, text_base;
+ uint64_t rela_start, rela_end, text_base, file_size;
if (argc != 5) {
fprintf(stderr, "Statically apply ELF rela relocations\n");
return 3;
}
- if (rela_start > rela_end || rela_start < text_base ||
- (rela_end - rela_start) % sizeof(Elf64_Rela)) {
+ if (rela_start > rela_end || rela_start < text_base) {
fprintf(stderr, "%s: bad rela bounds\n", argv[0]);
return 3;
}
rela_start -= text_base;
rela_end -= text_base;
+ fseek(f, 0, SEEK_END);
+ file_size = ftell(f);
+ rewind(f);
+
+ if (rela_end > file_size) {
+ // Most likely compiler inserted some section that didn't get
+ // objcopy-ed into the final binary
+ rela_end = file_size;
+ }
+
+ if ((rela_end - rela_start) % sizeof(Elf64_Rela)) {
+ fprintf(stderr, "%s: rela size isn't a multiple of Elf64_Rela\n", argv[0]);
+ return 3;
+ }
+
num = (rela_end - rela_start) / sizeof(Elf64_Rela);
for (i = 0; i < num; i++) {
projects / platform / kernel / u-boot.git / commitdiff