m68k: rename CONFIG_MCFTMR to CFG_MCFTMR
authorAngelo Dureghello <angelo@kernel-space.org>
Sat, 25 Feb 2023 22:25:26 +0000 (23:25 +0100)
committerAngelo Dureghello <angelo@kernel-space.org>
Wed, 15 Mar 2023 00:41:57 +0000 (01:41 +0100)
This is not a Kconfig option so changing to _CFG.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
41 files changed:
arch/m68k/cpu/mcf523x/interrupts.c
arch/m68k/cpu/mcf52x2/interrupts.c
arch/m68k/cpu/mcf532x/interrupts.c
arch/m68k/cpu/mcf5445x/interrupts.c
arch/m68k/include/asm/immap.h
arch/m68k/lib/time.c
board/freescale/m53017evb/README
board/freescale/m5373evb/README
configs/M5208EVBE_defconfig
configs/M5235EVB_Flash32_defconfig
configs/M5235EVB_defconfig
configs/M5249EVB_defconfig
configs/M5253DEMO_defconfig
configs/M5272C3_defconfig
configs/M5275EVB_defconfig
configs/M5282EVB_defconfig
configs/M53017EVB_defconfig
configs/M5329AFEE_defconfig
configs/M5329BFEE_defconfig
configs/M5373EVB_defconfig
configs/amcore_defconfig
configs/astro_mcf5373l_defconfig
configs/cobra5272_defconfig
configs/eb_cpu5282_defconfig
configs/eb_cpu5282_internal_defconfig
configs/stmark2_defconfig
include/configs/M5208EVBE.h
include/configs/M5235EVB.h
include/configs/M5249EVB.h
include/configs/M5253DEMO.h
include/configs/M5272C3.h
include/configs/M5275EVB.h
include/configs/M5282EVB.h
include/configs/M53017EVB.h
include/configs/M5329EVB.h
include/configs/M5373EVB.h
include/configs/amcore.h
include/configs/astro_mcf5373l.h
include/configs/cobra5272.h
include/configs/eb_cpu5282.h
include/configs/stmark2.h

index 331288e..b02ea29 100644 (file)
@@ -22,7 +22,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
index e8a1e13..e787c76 100644 (file)
@@ -34,7 +34,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
        intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
        clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
        setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
-#endif                         /* CONFIG_MCFTMR */
+#endif                         /* CFG_MCFTMR */
 #endif                         /* CONFIG_M5272 */
 
 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@@ -63,7 +63,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
        clrbits_be32(&intp->imrl0, 0x00000001);
        clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
-#endif                         /* CONFIG_MCFTMR */
+#endif                         /* CFG_MCFTMR */
 #endif                         /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -83,11 +83,11 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
        mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
        mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
-#endif                         /* CONFIG_MCFTMR */
+#endif                         /* CFG_MCFTMR */
 #endif                         /* CONFIG_M5249 || CONFIG_M5253 */
index 64e0466..bbe823c 100644 (file)
@@ -23,7 +23,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
index ea0cf87..fb80a87 100644 (file)
@@ -26,7 +26,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
index 8207c8d..74516cc 100644 (file)
@@ -16,7 +16,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -38,7 +38,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -63,7 +63,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (mbar_readLong(MCFSIM_IPR))
@@ -86,7 +86,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (mbar_readLong(MCFSIM_IPR))
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_TMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_TMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
 #define CFG_SYS_NUM_IRQS               (192)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
 #define CFG_SYS_NUM_IRQS               (128)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
 #define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile intctrl_t *) \
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
 #define MMAP_DSPI                      MMAP_DSPI0
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG     (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
index 2ce6908..ca8c039 100644 (file)
@@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
 #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 #ifndef CFG_SYS_UDELAY_BASE
 #      error   "uDelay base not defined!"
 #endif
@@ -111,7 +111,7 @@ ulong get_timer(ulong base)
        return (timestamp - base);
 }
 
-#endif                         /* CONFIG_MCFTMR */
+#endif                         /* CFG_MCFTMR */
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).
index 34f05f3..5d5c5e7 100644 (file)
@@ -87,7 +87,7 @@ CONFIG_SYS_FEC0_PINMUX                -- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE                -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP               -- set FEC timeout loop
 
-CONFIG_MCFTMR                  -- define to use DMA timer
+CFG_MCFTMR                     -- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL             -- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT            -- define for I2C bit-banged
index 7240648..e8bf75f 100644 (file)
@@ -86,7 +86,7 @@ CONFIG_SYS_FEC0_PINMUX                -- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE        -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP       -- set FEC timeout loop
 
-CONFIG_MCFTMR          -- define to use DMA timer
+CFG_MCFTMR             -- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL     -- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT    -- define for I2C bit-banged
index 263e57f..3263414 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x2000
 CONFIG_TARGET_M5208EVBE=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
index 88c1116..0b92456 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5235EVB=y
 CONFIG_NORFLASH_PS32BIT=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xFFC00400
 CONFIG_BOOTDELAY=1
index 255f3b9..fbd3e08 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5235EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=1
index de7f141..78f1f4f 100644 (file)
@@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
 CONFIG_SYS_LOAD_ADDR=0x200000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5249EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 # CONFIG_AUTOBOOT is not set
index ea07997..e6ab998 100644 (file)
@@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
 CONFIG_SYS_LOAD_ADDR=0x100000
 CONFIG_ENV_ADDR=0xFF804000
 CONFIG_TARGET_M5253DEMO=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xFF800400
 CONFIG_BOOTDELAY=5
index 324daa0..1c51c4a 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5272C3=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
index d84d9d9..ca1c184 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x800000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5275EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
index 7988d25..2b053e3 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5282EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
index d7c07aa..c70964f 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x40000
 CONFIG_TARGET_M53017EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
index 989af92..455eea2 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5329EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
index 7be2a27..0251444 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5329EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
index 4b278a5..eec95da 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5373EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
index 6775379..0b1a4e8 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_SYS_PROMPT="amcore $ "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFC1F000
 CONFIG_TARGET_AMCORE=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=126976
 CONFIG_SYS_MONITOR_BASE=0xFFC00400
 CONFIG_BOOTDELAY=1
index a1a2562..827ebfe 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="URMEL > "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0x1FF8000
 CONFIG_TARGET_ASTRO_MCF5373L=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
index 377781f..6d6380f 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="COBRA > "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_COBRA5272=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
index 7304b49..6f0882f 100644 (file)
@@ -7,7 +7,6 @@ CONFIG_SYS_PROMPT="\nEB+CPU5282> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFF040000
 CONFIG_TARGET_EB_CPU5282=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_BARGSIZE=1024
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFF000400
index 5ecdda4..5f4ec93 100644 (file)
@@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFF040000
 CONFIG_TARGET_EB_CPU5282=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_BARGSIZE=1024
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xF0000418
index ae7a9cf..ee75709 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="stmark2"
 CONFIG_SYS_PROMPT="stmark2 $ "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_TARGET_STMARK2=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_BARGSIZE=256
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_TIMESTAMP=y
index a4fda55..4b89f31 100644 (file)
 #define CFG_SYS_CS0_MASK               0x007F0001
 #define CFG_SYS_CS0_CTRL               0x00001FA0
 
+#define CFG_MCFTMR
+
 #endif                         /* _M5208EVBE_H */
index 8939c8e..14d4617 100644 (file)
 #      define CFG_SYS_CS0_CTRL 0x00001D80
 #endif
 
+#define CFG_MCFTMR
+
 #endif                         /* _M5329EVB_H */
index 4fd539c..b240423 100644 (file)
 #define        CFG_SYS_GPIO1_OUT               0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led                     */
 
+#define CFG_MCFTMR
+
 #endif /* M5249 */
index a6349fc..008c725 100644 (file)
 #define CFG_SYS_GPIO1_OUT              0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led */
 
+#define CFG_MCFTMR
+
 #endif                         /* _M5253DEMO_H */
index 33c2fc0..49cf3e8 100644 (file)
 #define CFG_SYS_PBDDR          0x0000
 #define CFG_SYS_PBDAT          0x0000
 #define CFG_SYS_PDCNT          0x00000000
+
+#define CFG_MCFTMR
+
 #endif                         /* _M5272C3_H */
index 607c5de..965327d 100644 (file)
 #define CFG_SYS_CS1_CTRL               0x00001900
 #define CFG_SYS_CS1_MASK               0x00070001
 
+#define CFG_MCFTMR
+
 #endif /* _M5275EVB_H */
index 31699a4..f04d9b1 100644 (file)
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
+#define CFG_MCFTMR
+
 #endif                         /* _CONFIG_M5282EVB_H */
index 6359915..04c456f 100644 (file)
 #define CFG_SYS_CS1_MASK               0x00070001
 #define CFG_SYS_CS1_CTRL               0x00001FA0
 
+#define CFG_MCFTMR
+
 #endif                         /* _M53017EVB_H */
index 456135b..0aa1ffd 100644 (file)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 #endif
 
+#define CFG_MCFTMR
+
 #endif                         /* _M5329EVB_H */
index 4e8dcb5..8b9e65d 100644 (file)
 #define CFG_SYS_CS2_MASK               (16 << 20)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 
+#define CFG_MCFTMR
+
 #endif                         /* _M5373EVB_H */
index 37c45e7..35f09b4 100644 (file)
@@ -10,7 +10,7 @@
 
 #define CFG_SYS_UART_PORT              0
 
-#define CONFIG_MCFTMR
+#define CFG_MCFTMR
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           0
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
index 6522432..80f8c41 100644 (file)
 #define CFG_SYS_CACHE_ICACR            (CF_CACR_EC | CF_CACR_CINVA | \
                                         CF_CACR_DCM_P)
 
+#define CFG_MCFTMR
+
 #endif /* _CONFIG_ASTRO_MCF5373L_H */
index cd50ffe..276ecc3 100644 (file)
@@ -184,4 +184,6 @@ configuration */
 #define CFG_SYS_PBDAT          0x0000                  /* PortB value reg. */
 #define CFG_SYS_PDCNT          0x00000000              /* PortD control reg. */
 
+#define CFG_MCFTMR
+
 #endif /* _CONFIG_COBRA5272_H */
index 26e4ade..9503ab6 100644 (file)
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
+#define CFG_MCFTMR
+
 #endif /* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/
index 19589be..05de376 100644 (file)
@@ -95,4 +95,6 @@
 #define CACR_STATUS                    (CFG_SYS_INIT_RAM_ADDR + \
                                        CFG_SYS_INIT_RAM_SIZE - 12)
 
+#define CFG_MCFTMR
+
 #endif /* __STMARK2_CONFIG_H */