This is not a Kconfig option so changing to _CFG.
Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
41 files changed:
-#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
-#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
void dtimer_intr_setup(void)
{
intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
}
clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
}
-#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
#endif /* CONFIG_M5272 */
#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
-#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
clrbits_be32(&intp->imrl0, 0x00000001);
clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
}
clrbits_be32(&intp->imrl0, 0x00000001);
clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
}
-#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
-#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
}
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
}
-#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
-#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
-#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
#define CFG_SYS_TMR_BASE (MMAP_TMR3)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
#define CFG_SYS_TMR_BASE (MMAP_TMR3)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
#define CFG_SYS_NUM_IRQS (192)
/* Timer */
#define CFG_SYS_NUM_IRQS (192)
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_NUM_IRQS (128)
/* Timer */
#define CFG_SYS_NUM_IRQS (128)
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define MMAP_DSPI MMAP_DSPI0
/* Timer */
#define MMAP_DSPI MMAP_DSPI0
/* Timer */
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
-#if defined(CONFIG_MCFTMR)
#ifndef CFG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
#ifndef CFG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
return (timestamp - base);
}
return (timestamp - base);
}
-#endif /* CONFIG_MCFTMR */
/*
* This function is derived from PowerPC code (read timebase as long long).
/*
* This function is derived from PowerPC code (read timebase as long long).
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_MCFTMR -- define to use DMA timer
+CFG_MCFTMR -- define to use DMA timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_MCFTMR -- define to use DMA timer
+CFG_MCFTMR -- define to use DMA timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x2000
CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x2000
CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_NORFLASH_PS32BIT=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_NORFLASH_PS32BIT=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xFF804000
CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xFF804000
CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFF800400
CONFIG_BOOTDELAY=5
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFF800400
CONFIG_BOOTDELAY=5
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5272C3=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5272C3=y
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x40000
CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x40000
CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFC1F000
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFC1F000
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_MONITOR_LEN=126976
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=126976
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0x1FF8000
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0x1FF8000
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_BARGSIZE=1024
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFF000400
CONFIG_SYS_BARGSIZE=1024
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFF000400
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_BARGSIZE=1024
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xF0000418
CONFIG_SYS_BARGSIZE=1024
CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xF0000418
CONFIG_SYS_PROMPT="stmark2 $ "
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_TARGET_STMARK2=y
CONFIG_SYS_PROMPT="stmark2 $ "
CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_TARGET_STMARK2=y
CONFIG_SYS_BARGSIZE=256
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_TIMESTAMP=y
CONFIG_SYS_BARGSIZE=256
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_TIMESTAMP=y
#define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
#define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
#endif /* _M5208EVBE_H */
#endif /* _M5208EVBE_H */
# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253DEMO_H */
#endif /* _M5253DEMO_H */
#define CFG_SYS_PBDDR 0x0000
#define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000
#define CFG_SYS_PBDDR 0x0000
#define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000
#define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */
#endif /* _CONFIG_M5282EVB_H */
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0
#endif /* _M53017EVB_H */
#endif /* _M53017EVB_H */
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
#define CFG_SYS_UART_PORT 0
#define CFG_SYS_UART_PORT 0
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#endif /* _CONFIG_ASTRO_MCF5373L_H */
#endif /* _CONFIG_ASTRO_MCF5373L_H */
#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#endif /* _CONFIG_COBRA5272_H */
#endif /* _CONFIG_COBRA5272_H */
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 12)
#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 12)
#endif /* __STMARK2_CONFIG_H */
#endif /* __STMARK2_CONFIG_H */