mpc83xx: Kconfig: Migrate HRCW to Kconfig

The HRCW (hardware reset configuration word) is a constant that must be
hard-coded into the boot loader image. So, it must be available at
compile time, and cannot be migrated to the DT mechanism, but has to be
kept in Kconfig.

Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index bd4e5c1..1206c68 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -177,30 +177,79 @@ config TARGET_STRIDER
 
 endchoice
 
+config MPC83XX_QUICC_ENGINE
+       bool
+
+# TODO: Imply MPC83xx PCI driver
+config MPC83XX_PCI_SUPPORT
+       bool
+
+# TODO: Imply TSEC driver
+config MPC83XX_TSEC1_SUPPORT
+       bool
+
+config MPC83XX_TSEC2_SUPPORT
+       bool
+
+config MPC83XX_PCIE1_SUPPORT
+       bool
+
+config MPC83XX_PCIE2_SUPPORT
+       bool
+
+config MPC83XX_SDHC_SUPPORT
+       bool
+
+config MPC83XX_SATA_SUPPORT
+       bool
+
+config MPC83XX_SECOND_I2C_SUPPORT
+       bool
+
+config MPC83XX_LDP_PIN
+       bool
+
 config ARCH_MPC830X
        bool
+       select MPC83XX_SDHC_SUPPORT
 
 config ARCH_MPC8308
        bool
        select ARCH_MPC830X
+       select MPC83XX_TSEC1_SUPPORT
+       select MPC83XX_TSEC2_SUPPORT
+       select MPC83XX_PCIE1_SUPPORT
+       select MPC83XX_SECOND_I2C_SUPPORT
 
 config ARCH_MPC8309
        bool
        select ARCH_MPC830X
+       select MPC83XX_QUICC_ENGINE
+       select MPC83XX_PCI_SUPPORT
+       select MPC83XX_SECOND_I2C_SUPPORT
 
 config ARCH_MPC831X
        bool
+       select MPC83XX_PCI_SUPPORT
+       select MPC83XX_TSEC1_SUPPORT
+       select MPC83XX_TSEC2_SUPPORT
 
 config ARCH_MPC8313
        bool
        select ARCH_MPC831X
+       select MPC83XX_SECOND_I2C_SUPPORT
 
 config ARCH_MPC8315
        bool
        select ARCH_MPC831X
+       select MPC83XX_PCIE1_SUPPORT
+       select MPC83XX_PCIE2_SUPPORT
+       select MPC83XX_SATA_SUPPORT
 
 config ARCH_MPC832X
        bool
+       select MPC83XX_QUICC_ENGINE
+       select MPC83XX_PCI_SUPPORT
 
 config ARCH_MPC834X
        bool
@@ -208,12 +257,32 @@ config ARCH_MPC834X
 config ARCH_MPC8349
        bool
        select ARCH_MPC834X
+       select MPC83XX_PCI_SUPPORT
+       select MPC83XX_TSEC1_SUPPORT
+       select MPC83XX_TSEC2_SUPPORT
+       select MPC83XX_LDP_PIN
+       select MPC83XX_SECOND_I2C_SUPPORT
 
 config ARCH_MPC8360
        bool
+       select MPC83XX_QUICC_ENGINE
+       select MPC83XX_PCI_SUPPORT
+       select MPC83XX_LDP_PIN
+       select MPC83XX_SECOND_I2C_SUPPORT
 
 config ARCH_MPC837X
        bool
+       select MPC83XX_PCI_SUPPORT
+       select MPC83XX_TSEC1_SUPPORT
+       select MPC83XX_TSEC2_SUPPORT
+       select MPC83XX_PCIE1_SUPPORT
+       select MPC83XX_PCIE2_SUPPORT
+       select MPC83XX_SDHC_SUPPORT
+       select MPC83XX_SATA_SUPPORT
+       select MPC83XX_LDP_PIN
+       select MPC83XX_SECOND_I2C_SUPPORT
+
+source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
 
 menu "Legacy options"
 

diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
new file mode 100644 (file)
index 0000000..c657a47
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -0,0 +1,816 @@
+menu "Reset Configuration Word"
+
+choice
+       prompt "Local bus memory controller clock mode"
+
+config LBMC_CLOCK_MODE_1_1
+       bool "1 : 1"
+
+config LBMC_CLOCK_MODE_1_2
+       depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+       bool "1 : 2"
+
+endchoice
+
+choice
+       prompt "DDR SDRAM memory controller clock mode"
+
+config DDR_MC_CLOCK_MODE_1_2
+       bool "1 : 2"
+
+config DDR_MC_CLOCK_MODE_1_1
+       depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+       bool "1 : 1"
+
+endchoice
+
+if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
+
+choice
+       prompt "System PLL VCO division"
+
+config SYSTEM_PLL_VCO_DIV_1
+       depends on !ARCH_MPC837X
+       bool "1"
+
+config SYSTEM_PLL_VCO_DIV_2
+       bool "2"
+
+config SYSTEM_PLL_VCO_DIV_4
+       depends on !ARCH_MPC831X
+       bool "4"
+
+config SYSTEM_PLL_VCO_DIV_8
+       depends on !ARCH_MPC831X
+       bool "8"
+
+endchoice
+
+endif
+
+choice
+       prompt "System PLL multiplication factor"
+
+config SYSTEM_PLL_FACTOR_2_1
+       bool "2 : 1"
+
+config SYSTEM_PLL_FACTOR_3_1
+       bool "3 : 1"
+
+config SYSTEM_PLL_FACTOR_4_1
+       bool "4 : 1"
+
+config SYSTEM_PLL_FACTOR_5_1
+       bool "5 : 1"
+
+config SYSTEM_PLL_FACTOR_6_1
+       bool "6 : 1"
+
+config SYSTEM_PLL_FACTOR_7_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "7 : 1"
+
+config SYSTEM_PLL_FACTOR_8_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "8 : 1"
+
+config SYSTEM_PLL_FACTOR_9_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "9 : 1"
+
+config SYSTEM_PLL_FACTOR_10_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "10 : 1"
+
+config SYSTEM_PLL_FACTOR_11_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "11 : 1"
+
+config SYSTEM_PLL_FACTOR_12_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "12 : 1"
+
+config SYSTEM_PLL_FACTOR_13_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "13 : 1"
+
+config SYSTEM_PLL_FACTOR_14_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "14 : 1"
+
+config SYSTEM_PLL_FACTOR_15_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+       bool "15 : 1"
+
+config SYSTEM_PLL_FACTOR_16_1
+       depends on ARCH_MPC8349 || ARCH_MPV8360
+       bool "16 : 1"
+
+endchoice
+
+config CORE_PLL_BYPASS
+       bool "Core PLL bypassed"
+
+if !CORE_PLL_BYPASS
+
+choice
+       prompt "Core PLL Ratio"
+
+config CORE_PLL_RATIO_1_1
+       bool "1 : 1"
+
+config CORE_PLL_RATIO_15_1
+       bool "1.5 : 1"
+
+config CORE_PLL_RATIO_2_1
+       bool "2 : 1"
+
+config CORE_PLL_RATIO_25_1
+       bool "2.5 : 1"
+
+config CORE_PLL_RATIO_3_1
+       bool "3 : 1"
+
+endchoice
+
+choice
+       prompt "Core PLL VCO Divider"
+
+config CORE_PLL_VCO_DIVIDER_2
+       bool "2"
+
+config CORE_PLL_VCO_DIVIDER_4
+       bool "4"
+
+config CORE_PLL_VCO_DIVIDER_8
+       depends on !ARCH_MPC8315
+       bool "8"
+
+endchoice
+
+endif
+
+if MPC83XX_QUICC_ENGINE
+
+choice
+       prompt "QUICC Engine PLL VCO Divider"
+
+config QUICC_VCO_DIVIDER_2
+       bool "2"
+
+config QUICC_VCO_DIVIDER_4
+       bool "4"
+
+config QUICC_VCO_DIVIDER_8
+       depends on ARCH_MPC8309
+       bool "8"
+
+endchoice
+
+choice
+       prompt "QUICC Engine PLL division factor"
+
+config QUICC_DIV_FACTOR_1
+       bool "1"
+
+config QUICC_DIV_FACTOR_2
+       bool "2"
+
+endchoice
+
+choice
+       prompt "QUICC Engine PLL multiplication factor"
+
+config QUICC_MULT_FACTOR_2
+       bool "2"
+
+config QUICC_MULT_FACTOR_3
+       bool "3"
+
+config QUICC_MULT_FACTOR_4
+       bool "4"
+
+config QUICC_MULT_FACTOR_5
+       bool "5"
+
+config QUICC_MULT_FACTOR_6
+       bool "6"
+
+config QUICC_MULT_FACTOR_7
+       bool "7"
+
+config QUICC_MULT_FACTOR_8
+       bool "8"
+
+config QUICC_MULT_FACTOR_9
+       depends on ARCH_MPC8360
+       bool "9"
+
+config QUICC_MULT_FACTOR_10
+       depends on ARCH_MPC8360
+       bool "10"
+
+config QUICC_MULT_FACTOR_11
+       depends on ARCH_MPC8360
+       bool "11"
+
+config QUICC_MULT_FACTOR_12
+       depends on ARCH_MPC8360
+       bool "12"
+
+config QUICC_MULT_FACTOR_13
+       depends on ARCH_MPC8360
+       bool "13"
+
+config QUICC_MULT_FACTOR_14
+       depends on ARCH_MPC8360
+       bool "14"
+
+config QUICC_MULT_FACTOR_15
+       depends on ARCH_MPC8360
+       bool "15"
+
+config QUICC_MULT_FACTOR_16
+       depends on ARCH_MPC8360
+       bool "16"
+
+config QUICC_MULT_FACTOR_17
+       depends on ARCH_MPC8360
+       bool "17"
+
+config QUICC_MULT_FACTOR_18
+       depends on ARCH_MPC8360
+       bool "18"
+
+config QUICC_MULT_FACTOR_19
+       depends on ARCH_MPC8360
+       bool "19"
+
+config QUICC_MULT_FACTOR_20
+       depends on ARCH_MPC8360
+       bool "20"
+
+config QUICC_MULT_FACTOR_21
+       depends on ARCH_MPC8360
+       bool "21"
+
+config QUICC_MULT_FACTOR_22
+       depends on ARCH_MPC8360
+       bool "22"
+
+config QUICC_MULT_FACTOR_23
+       depends on ARCH_MPC8360
+       bool "23"
+
+config QUICC_MULT_FACTOR_24
+       depends on ARCH_MPC8360
+       bool "24"
+
+config QUICC_MULT_FACTOR_25
+       depends on ARCH_MPC8360
+       bool "25"
+
+config QUICC_MULT_FACTOR_26
+       depends on ARCH_MPC8360
+       bool "26"
+
+config QUICC_MULT_FACTOR_27
+       depends on ARCH_MPC8360
+       bool "27"
+
+config QUICC_MULT_FACTOR_28
+       depends on ARCH_MPC8360
+       bool "28"
+
+config QUICC_MULT_FACTOR_29
+       depends on ARCH_MPC8360
+       bool "29"
+
+config QUICC_MULT_FACTOR_30
+       depends on ARCH_MPC8360
+       bool "30"
+
+config QUICC_MULT_FACTOR_31
+       depends on ARCH_MPC8360
+       bool "31"
+
+endchoice
+
+endif
+
+if MPC83XX_PCI_SUPPORT
+
+choice
+       prompt "PCI host mode"
+
+config PCI_HOST_MODE_DISABLE
+       bool "Disabled"
+
+config PCI_HOST_MODE_ENABLE
+       bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+       prompt "PCI 64-bit mode"
+
+config PCI_64BIT_MODE_DISABLE
+       bool "Disabled"
+
+config PCI_64BIT_MODE_ENABLE
+       bool "Enabled"
+
+endchoice
+
+endif
+
+choice
+       prompt "PCI internal arbiter 1 mode"
+
+config PCI_INT_ARBITER1_DISABLE
+       bool "Disabled"
+
+config PCI_INT_ARBITER1_ENABLE
+       bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+       prompt "PCI internal arbiter 2 mode"
+
+config PCI_INT_ARBITER2_DISABLE
+       bool "Disabled"
+
+config PCI_INT_ARBITER2_ENABLE
+       bool "Enabled"
+
+endchoice
+
+endif
+
+if ARCH_MPC8360
+
+choice
+       prompt "PCI clock output drive"
+
+config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+       bool "Disabled"
+
+config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
+       bool "Enabled"
+
+endchoice
+
+endif
+
+endif
+
+choice
+       prompt "Core disable mode"
+
+config CORE_DISABLE_MODE_OFF
+       bool "Off"
+
+config CORE_DISABLE_MODE_ON
+       bool "On"
+
+endchoice
+
+choice
+       prompt "Boot Memory Space"
+
+config BOOT_MEMORY_SPACE_HIGH
+       bool "High"
+
+config BOOT_MEMORY_SPACE_LOW
+       bool "Low"
+
+endchoice
+
+choice
+       prompt "Boot Sequencer Configuration"
+
+config BOOT_SEQUENCER_DISABLED
+       bool "Disabled"
+
+config BOOT_SEQUENCER_NORMAL_I2C
+       bool "Normal I2C"
+
+config BOOT_SEQUENCER_EXTENDED_I2C
+       bool "Extended I2C"
+
+endchoice
+
+choice
+       prompt "Software Watchdog"
+
+config SOFTWARE_WATCHDOG_DISABLED
+       bool "Disabled"
+
+config SOFTWARE_WATCHDOG_ENABLED
+       bool "Enabled"
+
+endchoice
+
+choice
+       prompt "Boot ROM interface location"
+
+config BOOT_ROM_INTERFACE_DDR_SDRAM
+       bool "DDR_SDRAM"
+
+config BOOT_ROM_INTERFACE_PCI1
+       depends on MPC83XX_PCI_SUPPORT
+       bool "PCI1"
+
+config BOOT_ROM_INTERFACE_PCI2
+       depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
+       bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+       depends on ARCH_MPC837X
+       bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ESDHC
+       depends on ARCH_MPC8309
+       bool "eSDHC"
+
+config BOOT_ROM_INTERFACE_SPI
+       depends on ARCH_MPC8309
+       bool "SPI"
+
+config BOOT_ROM_INTERFACE_GPCM_8BIT
+       bool "Local bus GPCM - 8-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_16BIT
+       bool "Local bus GPCM - 16-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_32BIT
+       depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+       bool "Local bus GPCM - 32-bit ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+       depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+       bool "Local bus NAND Flash- 8-bit small page ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+       depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+       bool "Local bus NAND Flash- 8-bit large page ROM"
+
+endchoice
+
+if MPC83XX_TSEC1_SUPPORT
+
+choice
+       prompt "TSEC1 mode"
+
+config TSEC1_MODE_MII
+       depends on !ARCH_MPC8349
+       bool "MII"
+
+config TSEC1_MODE_RMII
+       depends on ARCH_MPC831X && !ARCH_MPC8349
+       bool "RMII"
+
+config TSEC1_MODE_RGMII
+       bool "RGMII"
+
+config TSEC1_MODE_RTBI
+       depends on ARCH_MPC831X || ARCH_MPC837X
+       bool "RTBI"
+
+config TSEC1_MODE_GMII
+       depends on ARCH_MPC8349
+       bool "GMII"
+
+config TSEC1_MODE_TBI
+       depends on ARCH_MPC8349
+       bool "TBI"
+
+config TSEC1_MODE_SGMII
+       depends on ARCH_MPC831X || ARCH_MPC837X
+       bool "SGMII"
+
+endchoice
+
+endif
+
+if MPC83XX_TSEC2_SUPPORT
+
+choice
+       prompt "TSEC2 mode"
+
+config TSEC2_MODE_MII
+       depends on !ARCH_MPC8349
+       bool "MII"
+
+config TSEC2_MODE_RMII
+       depends on ARCH_MPC831X && !ARCH_MPC8349
+       bool "RMII"
+
+config TSEC2_MODE_RGMII
+       bool "RGMII"
+
+config TSEC2_MODE_RTBI
+       depends on ARCH_MPC831X || ARCH_MPC837X
+       bool "RTBI"
+
+config TSEC2_MODE_GMII
+       depends on ARCH_MPC8349
+       bool "GMII"
+
+config TSEC2_MODE_TBI
+       depends on ARCH_MPC8349
+       bool "TBI"
+
+config TSEC2_MODE_SGMII
+       depends on ARCH_MPC831X || ARCH_MPC837X
+       bool "SGMII"
+
+endchoice
+
+endif
+
+choice
+       prompt "True litle-endian mode"
+
+config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+       bool "Big-endian"
+
+config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+       bool "Little-endian"
+
+endchoice
+
+if ARCH_MPC8360
+
+choice
+       prompt "Secondary DDR IO"
+
+config SECONDARY_DDR_IO_DISABLE
+       bool "Disable"
+
+config SECONDARY_DDR_IO_ENABLE
+       bool "Enable"
+
+endchoice
+
+endif
+
+if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
+
+choice
+       prompt "LALE timing"
+
+config LALE_TIMING_NORMAL
+       bool "Normal"
+
+config LALE_TIMING_EARLIER
+       bool "Earlier"
+
+endchoice
+
+endif
+
+if MPC83XX_LDP_PIN
+
+choice
+       prompt "LDP pin mux state"
+
+config LDP_PIN_MUX_STATE_1
+       bool "Inital value 1"
+
+config LDP_PIN_MUX_STATE_0
+       bool "Inital value 0"
+
+endchoice
+
+endif
+
+endmenu
+
+config LBMC_CLOCK_MODE
+       int
+       default 0 if LBMC_CLOCK_MODE_1_1
+       default 1 if LBMC_CLOCK_MODE_1_2
+
+config DDR_MC_CLOCK_MODE
+       int
+       default 1 if DDR_MC_CLOCK_MODE_1_2
+       default 0 if DDR_MC_CLOCK_MODE_1_1
+
+config SYSTEM_PLL_VCO_DIV
+       int
+       default 0 if ARCH_MPC8349 || ARCH_MPC832X
+       default 2 if ARCH_MPC8313
+       default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
+       default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
+       default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
+       default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
+       default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
+       default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
+       default 3 if SYSTEM_PLL_VCO_DIV_1
+
+config SYSTEM_PLL_FACTOR
+       int
+       default 2 if SYSTEM_PLL_FACTOR_2_1
+       default 3 if SYSTEM_PLL_FACTOR_3_1
+       default 4 if SYSTEM_PLL_FACTOR_4_1
+       default 5 if SYSTEM_PLL_FACTOR_5_1
+       default 6 if SYSTEM_PLL_FACTOR_6_1
+       default 7 if SYSTEM_PLL_FACTOR_7_1
+       default 8 if SYSTEM_PLL_FACTOR_8_1
+       default 9 if SYSTEM_PLL_FACTOR_9_1
+       default 10 if SYSTEM_PLL_FACTOR_10_1
+       default 11 if SYSTEM_PLL_FACTOR_11_1
+       default 12 if SYSTEM_PLL_FACTOR_12_1
+       default 13 if SYSTEM_PLL_FACTOR_13_1
+       default 14 if SYSTEM_PLL_FACTOR_14_1
+       default 15 if SYSTEM_PLL_FACTOR_15_1
+       default 0 if SYSTEM_PLL_FACTOR_16_1
+
+config CORE_PLL_RATIO
+       hex
+       default 0x0 if CORE_PLL_BYPASS
+       default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
+       default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
+       default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
+       default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
+       default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
+       default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
+       default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
+       default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
+       default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
+       default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
+       default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
+       default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
+       default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
+       default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
+       default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
+
+config CORE_DISABLE_MODE
+       int
+       default 0 if CORE_DISABLE_MODE_OFF
+       default 1 if CORE_DISABLE_MODE_ON
+
+config BOOT_MEMORY_SPACE
+       int
+       default 0 if BOOT_MEMORY_SPACE_LOW
+       default 1 if BOOT_MEMORY_SPACE_HIGH
+
+config BOOT_SEQUENCER
+       int
+       default 0 if BOOT_SEQUENCER_DISABLED
+       default 1 if BOOT_SEQUENCER_NORMAL_I2C
+       default 2 if BOOT_SEQUENCER_EXTENDED_I2C
+
+config SOFTWARE_WATCHDOG
+       int
+       default 0 if SOFTWARE_WATCHDOG_DISABLED
+       default 1 if SOFTWARE_WATCHDOG_ENABLED
+
+config BOOT_ROM_INTERFACE
+       hex
+       default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
+       default 0x4 if BOOT_ROM_INTERFACE_PCI1
+       default 0x8 if BOOT_ROM_INTERFACE_PCI2
+       default 0x8 if BOOT_ROM_INTERFACE_ESDHC
+       default 0xc if BOOT_ROM_INTERFACE_SPI
+       default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+       default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
+       default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
+       default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
+       default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+       default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+
+config TSEC1_MODE
+       hex
+       default 0x0 if !MPC83XX_TSEC1_SUPPORT
+       default 0x0 if TSEC1_MODE_MII
+       default 0x1 if TSEC1_MODE_RMII
+       default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
+       default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
+       default 0x6 if TSEC1_MODE_SGMII
+       default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
+       default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
+       default 0x2 if TSEC1_MODE_GMII
+       default 0x3 if TSEC1_MODE_TBI
+
+config TSEC2_MODE
+       hex
+       default 0x0 if !MPC83XX_TSEC2_SUPPORT
+       default 0x0 if TSEC2_MODE_MII
+       default 0x1 if TSEC2_MODE_RMII
+       default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
+       default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
+       default 0x6 if TSEC2_MODE_SGMII
+       default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
+       default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
+       default 0x2 if TSEC2_MODE_GMII
+       default 0x3 if TSEC2_MODE_TBI
+
+config SECONDARY_DDR_IO
+       int
+       default 0 if !ARCH_MPC8360
+       default 0 if SECONDARY_DDR_IO_DISABLE
+       default 1 if SECONDARY_DDR_IO_ENABLE
+
+config TRUE_LITTLE_ENDIAN
+       int
+       default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+       default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+
+config LALE_TIMING
+       int
+       default 0 if ARCH_MPC830X || ARCH_MPC837X
+       default 0 if LALE_TIMING_NORMAL
+       default 1 if LALE_TIMING_EARLIER
+
+config LDP_PIN_MUX_STATE
+       int
+       default 0 if !MPC83XX_LDP_PIN
+       default 0 if LDP_PIN_MUX_STATE_1
+       default 1 if LDP_PIN_MUX_STATE_0
+
+config QUICC_VCO_DIVIDER
+       int
+       default 0 if !MPC83XX_QUICC_ENGINE
+       default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
+       default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
+       default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
+       default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
+       default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
+       default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
+
+config QUICC_DIV_FACTOR
+       int
+       default 0 if !MPC83XX_QUICC_ENGINE
+       default 0 if QUICC_DIV_FACTOR_1
+       default 1 if QUICC_DIV_FACTOR_2
+
+config QUICC_MULT_FACTOR
+       int
+       default 0 if !MPC83XX_QUICC_ENGINE
+       default 2 if QUICC_MULT_FACTOR_2
+       default 3 if QUICC_MULT_FACTOR_3
+       default 4 if QUICC_MULT_FACTOR_4
+       default 5 if QUICC_MULT_FACTOR_5
+       default 6 if QUICC_MULT_FACTOR_6
+       default 7 if QUICC_MULT_FACTOR_7
+       default 8 if QUICC_MULT_FACTOR_8
+       default 9 if QUICC_MULT_FACTOR_9
+       default 10 if QUICC_MULT_FACTOR_10
+       default 11 if QUICC_MULT_FACTOR_11
+       default 12 if QUICC_MULT_FACTOR_12
+       default 13 if QUICC_MULT_FACTOR_13
+       default 14 if QUICC_MULT_FACTOR_14
+       default 15 if QUICC_MULT_FACTOR_15
+       default 16 if QUICC_MULT_FACTOR_16
+       default 17 if QUICC_MULT_FACTOR_17
+       default 18 if QUICC_MULT_FACTOR_18
+       default 19 if QUICC_MULT_FACTOR_19
+       default 20 if QUICC_MULT_FACTOR_20
+       default 21 if QUICC_MULT_FACTOR_21
+       default 22 if QUICC_MULT_FACTOR_22
+       default 23 if QUICC_MULT_FACTOR_23
+       default 24 if QUICC_MULT_FACTOR_24
+       default 25 if QUICC_MULT_FACTOR_25
+       default 26 if QUICC_MULT_FACTOR_26
+       default 27 if QUICC_MULT_FACTOR_27
+       default 28 if QUICC_MULT_FACTOR_28
+       default 29 if QUICC_MULT_FACTOR_29
+       default 30 if QUICC_MULT_FACTOR_30
+       default 31 if QUICC_MULT_FACTOR_31
+
+config PCI_HOST_MODE
+       int
+       default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+       default 0 if PCI_HOST_MODE_DISABLE
+       default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_64BIT_MODE
+       int
+       default 0 if !ARCH_MPC8349
+       default 0 if PCI_64BIT_MODE_DISABLE
+       default 1 if PCI_64BIT_MODE_ENABLE
+
+config PCI_INT_ARBITER1
+       int
+       default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+       default 0 if PCI_INT_ARBITER1_DISABLE
+       default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_INT_ARBITER2
+       int
+       default 0 if !ARCH_MPC8349
+       default 0 if PCI_INT_ARBITER2_DISABLE
+       default 1 if PCI_INT_ARBITER2_ENABLE
+
+config PCI_CLOCK_OUTPUT_DRIVE
+       int
+       default 0 if !ARCH_MPC8360
+       default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+       default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE

diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
new file mode 100644 (file)
index 0000000..7d66ba7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
@@ -0,0 +1,37 @@
+#ifdef CONFIG_ARCH_MPC8349
+#define TSEC1_MODE_SHIFT 17
+#define TSEC2_MODE_SHIFT 19
+#else
+#define TSEC1_MODE_SHIFT 18
+#define TSEC2_MODE_SHIFT 21
+#endif
+
+#define CONFIG_SYS_HRCW_LOW (\
+       (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
+       (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
+       (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
+       (CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
+       (CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
+       (CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
+       (CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
+       (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
+       )
+
+#define CONFIG_SYS_HRCW_HIGH (\
+       (CONFIG_PCI_HOST_MODE << (31 - 0)) |\
+       (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
+       (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
+       (CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
+       (CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
+       (CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
+       (CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
+       (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
+       (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
+       (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
+       (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
+       (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
+       (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
+       (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
+       (CONFIG_LALE_TIMING << (31 - 29)) |\
+       (CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
+       )

diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index c00bb31..77170a7 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -24,6 +24,8 @@
 #include <asm/mmu.h>
 #include <asm/u-boot.h>
 
+#include "hrcw/hrcw.h"
+
 /* We don't want the  MMU yet.
  */
 #undef MSR_KERNEL

diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
index 5a67b40..cdac1ac 100644 (file)
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ b/board/freescale/mpc8315erdb/MAINTAINERS
@@ -4,3 +4,4 @@ S:      Orphan (since 2018-05)
 F:     board/freescale/mpc8315erdb/
 F:     include/configs/MPC8315ERDB.h
 F:     configs/MPC8315ERDB_defconfig
+F:     configs/MPC8315ERDB_NANDSPL_defconfig

diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
index 0719225..a8f26a9 100644 (file)
--- a/board/freescale/mpc8349emds/MAINTAINERS
+++ b/board/freescale/mpc8349emds/MAINTAINERS
@@ -5,4 +5,5 @@ F:      board/freescale/mpc8349emds/
 F:     include/configs/MPC8349EMDS.h
 F:     configs/MPC8349EMDS_defconfig
 F:     configs/MPC8349EMDS_SDRAM_defconfig
+F:     configs/MPC8349EMDS_PCI64_defconfig
 F:     configs/MPC8349EMDS_SLAVE_defconfig

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index d905533..c4bec09 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -19,6 +19,8 @@
 #include <linux/libfdt.h>
 #endif
 
+#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SPD_EEPROM

diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS
index 8386aa7..ce9c446 100644 (file)
--- a/board/freescale/mpc837xemds/MAINTAINERS
+++ b/board/freescale/mpc837xemds/MAINTAINERS
@@ -4,4 +4,5 @@ S:      Orphan (since 2018-05)
 F:     board/freescale/mpc837xemds/
 F:     include/configs/MPC837XEMDS.h
 F:     configs/MPC837XEMDS_defconfig
+F:     configs/MPC837XEMDS_SLAVE_defconfig
 F:     configs/MPC837XEMDS_HOST_defconfig

diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 59dde13..042f6aa 100644 (file)
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308RDB=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y

diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 4851611..c99d739 100644 (file)
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB_NOR=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"

diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index fb4fdde..c1eb49a 100644 (file)
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB_NOR=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"

diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 80ed52b..adec951 100644 (file)
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -5,6 +5,13 @@ CONFIG_SPL=y
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB_NAND=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"

diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index d0d84d4..6c75faa 100644 (file)
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -5,6 +5,12 @@ CONFIG_SPL=y
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB_NAND=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"

diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index 15dbbe3..cb3f206 100644 (file)
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8315ERDB=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index c43ae8c..cdc559a 100644 (file)
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8323ERDB=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index a40f16d..5f14da4 100644 (file)
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"

diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 1031dd6..41245a3 100644 (file)
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"

diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 416e0e9..ea90bea 100644 (file)
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"

diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 29b8f1a..4944694 100644 (file)
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"

diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 2a15e5c..d04292a 100644 (file)
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig
new file mode 100644 (file)
index 0000000..db06982
--- /dev/null
+++ b/configs/MPC8349EMDS_PCI64_defconfig
@@ -0,0 +1,35 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y

diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig
index d4f6587..8465cc6 100644 (file)
--- a/configs/MPC8349EMDS_SDRAM_defconfig
+++ b/configs/MPC8349EMDS_SDRAM_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS_SDRAM=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig
index 11e3b14..b0cb93b 100644 (file)
--- a/configs/MPC8349EMDS_SLAVE_defconfig
+++ b/configs/MPC8349EMDS_SLAVE_defconfig
@@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
@@ -19,7 +28,8 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y

diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 9a6eebf..ecded68 100644 (file)
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index c7f465e..13312e0 100644 (file)
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"

diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 7dbde32..221edf9 100644 (file)
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index d3ab1ea..46c9085 100644 (file)
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFEF00000
 CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 15d60a2..1b88b59 100644 (file)
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig
new file mode 100644 (file)
index 0000000..8a50ff1
--- /dev/null
+++ b/configs/MPC837XEMDS_SLAVE_defconfig
@@ -0,0 +1,35 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y

diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index d5d42ab..da908c7 100644 (file)
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
index 8c2389c..e145504 100644 (file)
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"

diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 090b9e5..4b9a7de 100644 (file)
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCIE"

diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 8f68804..1e873c3 100644 (file)
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0x80000000
 CONFIG_SYS_CLK_FREQ=66666000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TQM834X=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 2d2d64d..29ec5e0 100644 (file)
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_CADDY2=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 2a7b932..97fe0e0 100644 (file)
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon 0.01"
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_HRCON=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 3b1fbca..83dd6bf 100644 (file)
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon dh 0.01"
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_HRCON=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 7223af1..482b51e 100644 (file)
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_IDS8313=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_IMAGE_FORMAT_LEGACY=y

diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index beac453..7f22fa3 100644 (file)
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMCOGE5NE=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_4=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_6=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 2bf2c40..600a1ad 100644 (file)
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMETER1=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_4=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_6=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 1b63b42..6486c6a 100644 (file)
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMOPTI2=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index df1bfae..20df9f3 100644 (file)
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMSUPX5=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index 7187af7..c1d30cd 100644 (file)
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMTEGR1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"

diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index bbd13b8..ed8bc32 100644 (file)
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMTEPR2=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index 98dd9e2..66b3cd3 100644 (file)
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KMVECT1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"

diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 1e50782..cb24c97 100644 (file)
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xFC000000
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308_P1M=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=5

diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index eca22be..7fc0edd 100644 (file)
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_CLK_FREQ=33000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_8_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_PCI_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index fa1ec51..80cdd64 100644 (file)
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_PCI_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index d70332c..1141b79 100644 (file)
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 194cebd..c2faf38 100644 (file)
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con 0.01"
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index 4e72582..cff81f4 100644 (file)
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con dp 0.01"
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index c633e03..f72bec4 100644 (file)
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu 0.01"
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index e1d08e7..0e43049 100644 (file)
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu dp 0.01"
 CONFIG_SYS_CLK_FREQ=33333333
 CONFIG_MPC83xx=y
 CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index 4744122..9b36aa0 100644 (file)
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SUVD3=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SUVD3"

diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 349b1d0..3467b7e 100644 (file)
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUGE1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index a6654c9..f67e3b8 100644 (file)
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUXX1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y

diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 084b1bd..f09c83d 100644 (file)
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000
 CONFIG_SYS_CLK_FREQ=32000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_VE8313=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index aae2214..271e690 100644 (file)
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_TARGET_VME8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
 CONFIG_PCI_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 77c3009..db28357 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -28,38 +28,6 @@
 #define CONFIG_VSC7385_ENET
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 103ace2..e14652a 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -424,44 +424,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000     /* PCIHOST  */
 
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-       0x20000000 /* reserved, must be set */ |\
-       HRCWL_DDRCM |\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-       0x20000000 /* reserved, must be set */ |\
-       HRCWL_DDRCM |\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_CSB_TO_CLKIN_5X1 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN)
-
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-                      HRCWH_FROM_0XFFF00100 |\
-                      HRCWH_ROM_LOC_NAND_SP_8BIT |\
-                      HRCWH_RL_EXT_NAND)
 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 
 /* System IO Config */

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 64b289a..b550a8d 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -398,46 +398,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000     /* PCIHOST  */
 
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-       0x20000000 /* reserved, must be set */ |\
-       HRCWL_DDRCM |\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-       0x20000000 /* reserved, must be set */ |\
-       HRCWL_DDRCM |\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_CSB_TO_CLKIN_5X1 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN)
-
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-                      HRCWH_FROM_0X00000100 |\
-                      HRCWH_ROM_LOC_LOCAL_16BIT |\
-                      HRCWH_RL_EXT_LEGACY)
 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 
 /* System IO Config */

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 53a02f4..446c98b 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -24,40 +24,6 @@
 #define CONFIG_E300            1 /* E300 family */
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
-       HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-                      HRCWH_FROM_0XFFF00100 |\
-                      HRCWH_ROM_LOC_NAND_SP_8BIT |\
-                      HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-                      HRCWH_FROM_0X00000100 |\
-                      HRCWH_ROM_LOC_LOCAL_16BIT |\
-                      HRCWH_RL_EXT_LEGACY)
-#endif
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH               0x00000000

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index ee4eeec..7dbbb4e 100644 (file)
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -16,30 +16,6 @@
 #define CONFIG_QE              1       /* Has QE */
 
 /*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
-       HRCWL_CORE_TO_CSB_2_5X1 |\
-       HRCWL_CE_PLL_VCO_DIV_2 |\
-       HRCWL_CE_PLL_DIV_1X1 |\
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LALE_NORMAL)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRL               0x00000000

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 0ba6477..dad8407 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -13,43 +13,6 @@
 #define CONFIG_QE              1       /* Has QE */
 
 /*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
-       HRCWL_CORE_TO_CSB_2X1 |\
-       HRCWL_CE_PLL_VCO_DIV_2 |\
-       HRCWL_CE_PLL_DIV_1X1 |\
-       HRCWL_CE_TO_PLL_1X3)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT |\
-       HRCWH_PCI1_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0XFFF00100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LALE_NORMAL)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LALE_NORMAL)
-#endif
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRL               0x00000000

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 4c9ee76..2159454 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -17,12 +17,6 @@
  */
 #define CONFIG_E300            1       /* E300 Family */
 
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
-#elif CONFIG_SYS_CLK_FREQ == 33000000
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR                0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
@@ -363,86 +357,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_DISABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif /* CONFIG_PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
 /*
  * System performance
  */

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index b9710b6..a19e732 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -17,12 +17,6 @@
  */
 #define CONFIG_E300            1       /* E300 Family */
 
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
-#elif CONFIG_SYS_CLK_FREQ == 33000000
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR                0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
@@ -435,86 +429,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_DISABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif /* CONFIG_PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
 /*
  * System performance
  */

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index e170271..6860c72 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -39,10 +39,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
 /*
  * High Level Configuration Options
  */
@@ -461,41 +457,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20)
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0XFFF00100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /*
  * System performance
  */

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 33c485a..8c562fd 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -12,48 +12,6 @@
  */
 #define CONFIG_E300            1 /* E300 family */
 
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66MHz, then
- * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_6X1 |\
-       HRCWL_CORE_TO_CSB_1_5X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT |\
-       HRCWH_PCI1_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0XFFF00100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LDP_CLEAR)
-#endif
-
 /* Arbiter Configuration Register */
 #define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth is 4 */
 #define CONFIG_SYS_ACR_RPTCNT  3       /* Arbiter repeat count is 4 */

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 806b0f3..055a30e 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -20,46 +20,6 @@
  */
 #define CONFIG_VSC7385_ENET
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_5X1 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT |\
-       HRCWH_PCI1_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0XFFF00100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LDP_CLEAR)
-#endif
-
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 58c3015..be1c289 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -260,41 +260,6 @@
                                /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20)
 
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH       0
 #define CONFIG_SYS_SICRL       SICRL_LDP_A

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index 68fb989..5e88bd7 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -25,12 +25,6 @@
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
-#ifdef CONFIG_PCI_66M
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR                0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
@@ -290,41 +284,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 8eb12b7..c1fe6b4 100644 (file)
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -17,38 +17,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC83xx_ESDHC_ADDR
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0XFFF00100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_RGMII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index eff0add..4e5927e 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -25,27 +25,6 @@
 #define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
 
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.000MHz, then
- * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
- */
-#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
-                            HRCWL_DDR_TO_SCB_CLK_2X1 |\
-                            HRCWL_CSB_TO_CLKIN_2X1 |\
-                            HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_HRCW_HIGH   (HRCWH_PCI_HOST |\
-                                HRCWH_CORE_ENABLE |\
-                                HRCWH_FROM_0XFFF00100 |\
-                                HRCWH_BOOTSEQ_DISABLE |\
-                                HRCWH_SW_WATCHDOG_DISABLE |\
-                                HRCWH_ROM_LOC_LOCAL_8BIT |\
-                                HRCWH_RL_EXT_LEGACY |\
-                                HRCWH_TSEC1M_IN_MII |\
-                                HRCWH_TSEC2M_IN_MII |\
-                                HRCWH_BIG_ENDIAN)
-
 #define CONFIG_SYS_SICRH       0x00000000
 #define CONFIG_SYS_SICRL       (SICRL_LBC | SICRL_SPI_D)
 

diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index ec65a42..7e579db 100644 (file)
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -318,25 +318,6 @@
  */
 #define CONFIG_SYS_SICRH               (SICRH_UC1EOBI | SICRH_UC2E1OBI)
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_CSB_TO_CLKIN_4X1 | \
-       HRCWL_CORE_TO_CSB_2X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_EARLY | \
-       HRCWH_LDP_CLEAR)
-
 /**
  * DDR RAM settings
  */

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 2280f00..3a98f94 100644 (file)
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -304,25 +304,6 @@
  */
 #define CONFIG_SYS_SICRH               (SICRH_UC1EOBI | SICRH_UC2E1OBI)
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_CSB_TO_CLKIN_4X1 | \
-       HRCWL_CORE_TO_CSB_2X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_EARLY | \
-       HRCWH_LDP_CLEAR)
-
 /**
  * DDR RAM settings
  */

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index fa12d41..4494475 100644 (file)
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index 30898c0..7c008f8 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index 329a5cf..95b16ca 100644 (file)
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -374,28 +374,6 @@
 #define CONFIG_SYS_GP2DIR 0xFF000000
 #define CONFIG_SYS_GP2ODR 0x00000000
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 02b72c8..5191f2c 100644 (file)
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index c21b9ba..cc88f07 100644 (file)
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -366,28 +366,6 @@
 #define CONFIG_SYS_GP2DIR 0xFF000000
 #define CONFIG_SYS_GP2ODR 0x00000000
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index fd59471..2822aa3 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -22,38 +22,6 @@
 #define CONFIG_TSEC2
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_MII |\
-       HRCWH_TSEC2M_IN_MII |\
-       HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 2520a77..fd67aca 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -22,12 +22,6 @@
 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
-#ifdef CONFIG_PCI_33M
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
-#else  /* 66M */
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
-#endif
-
 #define CONFIG_SYS_IMMR                0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
@@ -374,71 +368,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X4 |\
-       HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A

diff --git a/include/configs/strider.h b/include/configs/strider.h
index 8c9acfb..ef33eae 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -17,38 +17,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC83xx_ESDHC_ADDR
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0XFFF00100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_MII |\
-       HRCWH_TSEC2M_IN_RGMII |\
-       HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 87f7390..c84c7c0 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -320,28 +320,6 @@
  */
 #define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 1cd0985..8f60db3 100644 (file)
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index d476a75..58c6089 100644 (file)
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL       SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-       HRCWL_DDR_TO_SCB_CLK_2X1 | \
-       HRCWL_CSB_TO_CLKIN_2X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1 | \
-       HRCWL_CE_PLL_VCO_DIV_2 | \
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_AGENT | \
-       HRCWH_PCI_ARBITER_DISABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE | \
-       HRCWH_SW_WATCHDOG_DISABLE | \
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
        DDRCDR_EN | \
        DDRCDR_PZ_MAXZ | \

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 2ef6f88..c4bdfe5 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -308,25 +308,6 @@
                                /* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20)
 
-/* 0x64050000 */
-#define CONFIG_SYS_HRCW_LOW (\
-       0x20000000 /* reserved, must be set */ |\
-       HRCWL_DDRCM |\
-       HRCWL_CSB_TO_CLKIN_4X1 | \
-       HRCWL_CORE_TO_CSB_2_5X1)
-
-/* 0xa0600004 */
-#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
-       HRCWH_PCI_ARBITER_ENABLE | \
-       HRCWH_CORE_ENABLE | \
-       HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT | \
-       HRCWH_TSEC1M_IN_MII | \
-       HRCWH_BIG_ENDIAN | \
-       HRCWH_LALE_EARLY)
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH       (0x01000000 | \
                                SICRH_ETSEC2_B | \

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index c508695..ca6233a 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -25,14 +25,6 @@
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
-#define CONFIG_PCI_66M
-
-#ifdef CONFIG_PCI_66M
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR                0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
@@ -292,41 +284,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_64_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_DISABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_32_BIT_PCI |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_PCI2_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A