include/configs/MPC8349EMDS_SDRAM.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2010
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * mpc8349emds board configuration file
   9  *
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 Family */
  19
  20 #define CONFIG_SYS_IMMR         0xE0000000
  21
  22 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  23 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  24 #define CONFIG_SYS_MEMTEST_END          0x00100000
  25
  26 /*
  27  * DDR Setup
  28  */
  29 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  30 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  31 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  32
  33 /*
  34  * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  35  * unselect it to use old spd_sdram.c
  36  */
  37 #define CONFIG_SYS_SPD_BUS_NUM  0
  38 #define SPD_EEPROM_ADDRESS1     0x52
  39 #define SPD_EEPROM_ADDRESS2     0x51
  40 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  41 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  42 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  43 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  44
  45 /*
  46  * 32-bit data path mode.
  47  *
  48  * Please note that using this mode for devices with the real density of 64-bit
  49  * effectively reduces the amount of available memory due to the effect of
  50  * wrapping around while translating address to row/columns, for example in the
  51  * 256MB module the upper 128MB get aliased with contents of the lower
  52  * 128MB); normally this define should be used for devices with real 32-bit
  53  * data path.
  54  */
  55 #undef CONFIG_DDR_32BIT
  56
  57 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  58 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  60 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  61                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  62 #undef  CONFIG_DDR_2T_TIMING
  63
  64 /*
  65  * DDRCDR - DDR Control Driver Register
  66  */
  67 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  68
  69 #if defined(CONFIG_SPD_EEPROM)
  70 /*
  71  * Determine DDR configuration from I2C interface.
  72  */
  73 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  74 #else
  75 /*
  76  * Manually set up DDR parameters
  77  */
  78 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  79 #if defined(CONFIG_DDR_II)
  80 #define CONFIG_SYS_DDRCDR               0x80080001
  81 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
  82 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
  83 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
  84 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
  85 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
  86 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  87 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
  88 #define CONFIG_SYS_DDR_MODE             0x47d00432
  89 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  90 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
  91 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  92 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  93 #else
  94 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  95                                 | CSCONFIG_ROW_BIT_13 \
  96                                 | CSCONFIG_COL_BIT_10)
  97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  99 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 101
 102 #if defined(CONFIG_DDR_32BIT)
 103 /* set burst length to 8 for 32-bit data path */
 104                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 105 #define CONFIG_SYS_DDR_MODE     0x00000023
 106 #else
 107 /* the default burst length is 4 - for 64-bit data path */
 108                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 109 #define CONFIG_SYS_DDR_MODE     0x00000022
 110 #endif
 111 #endif
 112 #endif
 113
 114 /*
 115  * SDRAM on the Local Bus
 116  */
 117 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 118 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 119
 120 /*
 121  * FLASH on the Local Bus
 122  */
 123 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 124 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 125
 126 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 127                                 | BR_PS_16      /* 16 bit port  */ \
 128                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 129                                 | BR_V)         /* valid */
 130 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 131                                 | OR_UPM_XAM \
 132                                 | OR_GPCM_CSNT \
 133                                 | OR_GPCM_ACS_DIV2 \
 134                                 | OR_GPCM_XACS \
 135                                 | OR_GPCM_SCY_15 \
 136                                 | OR_GPCM_TRLX_SET \
 137                                 | OR_GPCM_EHTR_SET \
 138                                 | OR_GPCM_EAD)
 139
 140                                         /* window base at flash base */
 141 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 142 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 143
 144 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 145 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 146
 147 #undef CONFIG_SYS_FLASH_CHECKSUM
 148 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 149 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 150
 151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 152
 153 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 154 #define CONFIG_SYS_RAMBOOT
 155 #else
 156 #undef  CONFIG_SYS_RAMBOOT
 157 #endif
 158
 159 /*
 160  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 161  */
 162 #define CONFIG_SYS_BCSR                 0xE2400000
 163                                         /* Access window base at BCSR base */
 164 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 165 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 166 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 167                                         | BR_PS_8 \
 168                                         | BR_MS_GPCM \
 169                                         | BR_V)
 170                                         /* 0x00000801 */
 171 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 172                                         | OR_GPCM_XAM \
 173                                         | OR_GPCM_CSNT \
 174                                         | OR_GPCM_SCY_15 \
 175                                         | OR_GPCM_TRLX_CLEAR \
 176                                         | OR_GPCM_EHTR_CLEAR)
 177                                         /* 0xFFFFE8F0 */
 178
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 182
 183 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 184                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 185 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 186
 187 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 188 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 189
 190 /*
 191  * Local Bus LCRR and LBCR regs
 192  *    LCRR:  DLL bypass, Clock divider is 4
 193  * External Local Bus rate is
 194  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 195  */
 196 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 197 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 198 #define CONFIG_SYS_LBC_LBCR     0x00000000
 199
 200 /*
 201  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 202  */
 203
 204 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 205 /*
 206  * Base Register 2 and Option Register 2 configure SDRAM.
 207  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 208  *
 209  * For BR2, need:
 210  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 211  *    port-size = 32-bits = BR2[19:20] = 11
 212  *    no parity checking = BR2[21:22] = 00
 213  *    SDRAM for MSEL = BR2[24:26] = 011
 214  *    Valid = BR[31] = 1
 215  *
 216  * 0    4    8    12   16   20   24   28
 217  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 218  */
 219
 220 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 221                                         | BR_PS_32      /* 32-bit port */ \
 222                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
 223                                         | BR_V)         /* Valid */
 224                                         /* 0xF0001861 */
 225 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 226 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 227
 228 /*
 229  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 230  *
 231  * For OR2, need:
 232  *    64MB mask for AM, OR2[0:7] = 1111 1100
 233  *                 XAM, OR2[17:18] = 11
 234  *    9 columns OR2[19-21] = 010
 235  *    13 rows   OR2[23-25] = 100
 236  *    EAD set for extra time OR[31] = 1
 237  *
 238  * 0    4    8    12   16   20   24   28
 239  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 240  */
 241
 242 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 243                         | OR_SDRAM_XAM \
 244                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 245                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 246                         | OR_SDRAM_EAD)
 247                         /* 0xFC006901 */
 248
 249                                 /* LB sdram refresh timer, about 6us */
 250 #define CONFIG_SYS_LBC_LSRT     0x32000000
 251                                 /* LB refresh timer prescal, 266MHz/32 */
 252 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 253
 254 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 255                                 | LSDMR_BSMA1516        \
 256                                 | LSDMR_RFCR8           \
 257                                 | LSDMR_PRETOACT6       \
 258                                 | LSDMR_ACTTORW3        \
 259                                 | LSDMR_BL8             \
 260                                 | LSDMR_WRC3            \
 261                                 | LSDMR_CL3)
 262
 263 /*
 264  * SDRAM Controller configuration sequence.
 265  */
 266 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 267 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 268 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 269 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 270 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 271
 272 /*
 273  * Serial Port
 274  */
 275 #define CONFIG_SYS_NS16550_SERIAL
 276 #define CONFIG_SYS_NS16550_REG_SIZE    1
 277 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 278
 279 #define CONFIG_SYS_BAUDRATE_TABLE  \
 280                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 281
 282 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 283 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 284
 285 /* I2C */
 286 #define CONFIG_SYS_I2C
 287 #define CONFIG_SYS_I2C_FSL
 288 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 289 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 290 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 291 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 292 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 293 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 294 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 295
 296 /* SPI */
 297 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 298
 299 /* GPIOs.  Used as SPI chip selects */
 300 #define CONFIG_SYS_GPIO1_PRELIM
 301 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 302 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 303
 304 /* TSEC */
 305 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 306 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 307 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 308 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 309
 310 /* USB */
 311 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 312
 313 /*
 314  * General PCI
 315  * Addresses are mapped 1-1.
 316  */
 317 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 318 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 319 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 320 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 321 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 322 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 323 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 324 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 325 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 326
 327 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 328 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 329 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 330 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 331 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 332 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 333 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 334 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 335 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 336
 337 #if defined(CONFIG_PCI)
 338
 339 #define CONFIG_83XX_PCI_STREAMING
 340
 341 #undef CONFIG_EEPRO100
 342 #undef CONFIG_TULIP
 343
 344 #if !defined(CONFIG_PCI_PNP)
 345         #define PCI_ENET0_IOADDR        0xFIXME
 346         #define PCI_ENET0_MEMADDR       0xFIXME
 347         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 348 #endif
 349
 350 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 351 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 352
 353 #endif  /* CONFIG_PCI */
 354
 355 /*
 356  * TSEC configuration
 357  */
 358
 359 #if defined(CONFIG_TSEC_ENET)
 360
 361 #define CONFIG_GMII             1       /* MII PHY management */
 362 #define CONFIG_TSEC1            1
 363 #define CONFIG_TSEC1_NAME       "TSEC0"
 364 #define CONFIG_TSEC2            1
 365 #define CONFIG_TSEC2_NAME       "TSEC1"
 366 #define TSEC1_PHY_ADDR          0
 367 #define TSEC2_PHY_ADDR          1
 368 #define TSEC1_PHYIDX            0
 369 #define TSEC2_PHYIDX            0
 370 #define TSEC1_FLAGS             TSEC_GIGABIT
 371 #define TSEC2_FLAGS             TSEC_GIGABIT
 372
 373 /* Options are: TSEC[0-1] */
 374 #define CONFIG_ETHPRIME         "TSEC0"
 375
 376 #endif  /* CONFIG_TSEC_ENET */
 377
 378 /*
 379  * Configure on-board RTC
 380  */
 381 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 382 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 383
 384 /*
 385  * Environment
 386  */
 387 #ifndef CONFIG_SYS_RAMBOOT
 388         #define CONFIG_ENV_ADDR         \
 389                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 390         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 391         #define CONFIG_ENV_SIZE         0x2000
 392
 393 /* Address and size of Redundant Environment Sector     */
 394 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 395 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 396
 397 #else
 398         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 399         #define CONFIG_ENV_SIZE         0x2000
 400 #endif
 401
 402 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 404
 405 /*
 406  * BOOTP options
 407  */
 408 #define CONFIG_BOOTP_BOOTFILESIZE
 409
 410 /*
 411  * Command line configuration.
 412  */
 413
 414 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 415
 416 /*
 417  * Miscellaneous configurable options
 418  */
 419 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 420
 421 /*
 422  * For booting Linux, the board info and command line data
 423  * have to be in the first 256 MB of memory, since this is
 424  * the maximum mapped by the Linux kernel during initialization.
 425  */
 426                                 /* Initial Memory map for Linux*/
 427 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 428 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 429
 430 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 431
 432 /*
 433  * System performance
 434  */
 435 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 436 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 437 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 438 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 439 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 440 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 441
 442 /* System IO Config */
 443 #define CONFIG_SYS_SICRH 0
 444 #define CONFIG_SYS_SICRL SICRL_LDP_A
 445
 446 #define CONFIG_SYS_HID0_INIT    0x000000000
 447 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 448                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 449
 450 /* #define CONFIG_SYS_HID0_FINAL        (\
 451         HID0_ENABLE_INSTRUCTION_CACHE |\
 452         HID0_ENABLE_M_BIT |\
 453         HID0_ENABLE_ADDRESS_BROADCAST) */
 454
 455 #define CONFIG_SYS_HID2 HID2_HBE
 456 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 457
 458 /* DDR @ 0x00000000 */
 459 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 460                                 | BATL_PP_RW \
 461                                 | BATL_MEMCOHERENCE)
 462 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 463                                 | BATU_BL_256M \
 464                                 | BATU_VS \
 465                                 | BATU_VP)
 466
 467 /* PCI @ 0x80000000 */
 468 #ifdef CONFIG_PCI
 469 #define CONFIG_PCI_INDIRECT_BRIDGE
 470 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 471                                 | BATL_PP_RW \
 472                                 | BATL_MEMCOHERENCE)
 473 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 474                                 | BATU_BL_256M \
 475                                 | BATU_VS \
 476                                 | BATU_VP)
 477 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 478                                 | BATL_PP_RW \
 479                                 | BATL_CACHEINHIBIT \
 480                                 | BATL_GUARDEDSTORAGE)
 481 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 482                                 | BATU_BL_256M \
 483                                 | BATU_VS \
 484                                 | BATU_VP)
 485 #else
 486 #define CONFIG_SYS_IBAT1L       (0)
 487 #define CONFIG_SYS_IBAT1U       (0)
 488 #define CONFIG_SYS_IBAT2L       (0)
 489 #define CONFIG_SYS_IBAT2U       (0)
 490 #endif
 491
 492 #ifdef CONFIG_MPC83XX_PCI2
 493 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 494                                 | BATL_PP_RW \
 495                                 | BATL_MEMCOHERENCE)
 496 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 497                                 | BATU_BL_256M \
 498                                 | BATU_VS \
 499                                 | BATU_VP)
 500 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 501                                 | BATL_PP_RW \
 502                                 | BATL_CACHEINHIBIT \
 503                                 | BATL_GUARDEDSTORAGE)
 504 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 505                                 | BATU_BL_256M \
 506                                 | BATU_VS \
 507                                 | BATU_VP)
 508 #else
 509 #define CONFIG_SYS_IBAT3L       (0)
 510 #define CONFIG_SYS_IBAT3U       (0)
 511 #define CONFIG_SYS_IBAT4L       (0)
 512 #define CONFIG_SYS_IBAT4U       (0)
 513 #endif
 514
 515 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 516 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 517                                 | BATL_PP_RW \
 518                                 | BATL_CACHEINHIBIT \
 519                                 | BATL_GUARDEDSTORAGE)
 520 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 521                                 | BATU_BL_256M \
 522                                 | BATU_VS \
 523                                 | BATU_VP)
 524
 525 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 526 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 527                                 | BATL_PP_RW \
 528                                 | BATL_MEMCOHERENCE \
 529                                 | BATL_GUARDEDSTORAGE)
 530 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 531                                 | BATU_BL_256M \
 532                                 | BATU_VS \
 533                                 | BATU_VP)
 534
 535 #define CONFIG_SYS_IBAT7L       (0)
 536 #define CONFIG_SYS_IBAT7U       (0)
 537
 538 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 539 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 540 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 541 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 542 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 543 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 544 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 545 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 546 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 547 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 548 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 549 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 550 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 551 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 552 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 553 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 554
 555 #if defined(CONFIG_CMD_KGDB)
 556 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 557 #endif
 558
 559 /*
 560  * Environment Configuration
 561  */
 562 #define CONFIG_ENV_OVERWRITE
 563
 564 #if defined(CONFIG_TSEC_ENET)
 565 #define CONFIG_HAS_ETH1
 566 #define CONFIG_HAS_ETH0
 567 #endif
 568
 569 #define CONFIG_HOSTNAME         "mpc8349emds"
 570 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 571 #define CONFIG_BOOTFILE         "uImage"
 572
 573 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 574
 575 #define CONFIG_PREBOOT  "echo;" \
 576         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 577         "echo"
 578
 579 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 580         "netdev=eth0\0"                                                 \
 581         "hostname=mpc8349emds\0"                                        \
 582         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 583                 "nfsroot=${serverip}:${rootpath}\0"                     \
 584         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 585         "addip=setenv bootargs ${bootargs} "                            \
 586                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 587                 ":${hostname}:${netdev}:off panic=1\0"                  \
 588         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 589         "flash_nfs=run nfsargs addip addtty;"                           \
 590                 "bootm ${kernel_addr}\0"                                \
 591         "flash_self=run ramargs addip addtty;"                          \
 592                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 593         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 594                 "bootm\0"                                               \
 595         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 596         "update=protect off fe000000 fe03ffff; "                        \
 597                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 598         "upd=run load update\0"                                         \
 599         "fdtaddr=780000\0"                                              \
 600         "fdtfile=mpc834x_mds.dtb\0"                                     \
 601         ""
 602
 603 #define CONFIG_NFSBOOTCOMMAND                                           \
 604         "setenv bootargs root=/dev/nfs rw "                             \
 605                 "nfsroot=$serverip:$rootpath "                          \
 606                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 607                                                         "$netdev:off "  \
 608                 "console=$consoledev,$baudrate $othbootargs;"           \
 609         "tftp $loadaddr $bootfile;"                                     \
 610         "tftp $fdtaddr $fdtfile;"                                       \
 611         "bootm $loadaddr - $fdtaddr"
 612
 613 #define CONFIG_RAMBOOTCOMMAND                                           \
 614         "setenv bootargs root=/dev/ram rw "                             \
 615                 "console=$consoledev,$baudrate $othbootargs;"           \
 616         "tftp $ramdiskaddr $ramdiskfile;"                               \
 617         "tftp $loadaddr $bootfile;"                                     \
 618         "tftp $fdtaddr $fdtfile;"                                       \
 619         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 620
 621 #define CONFIG_BOOTCOMMAND      "run flash_self"
 622
 623 #endif  /* __CONFIG_H */