include/configs/caddy2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1       /* E300 Family */
  24
  25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  26 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  27
  28 #ifdef CONFIG_PCI_66M
  29 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  30 #else
  31 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  32 #endif
  33
  34 #define CONFIG_SYS_IMMR         0xE0000000
  35
  36 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  37 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  38 #define CONFIG_SYS_MEMTEST_END          0x00100000
  39
  40 /*
  41  * DDR Setup
  42  */
  43 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  44 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  45 #define CONFIG_SPD_EEPROM
  46 #define SPD_EEPROM_ADDRESS              0x54
  47 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  48 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  49
  50 /*
  51  * 32-bit data path mode.
  52  *
  53  * Please note that using this mode for devices with the real density of 64-bit
  54  * effectively reduces the amount of available memory due to the effect of
  55  * wrapping around while translating address to row/columns, for example in the
  56  * 256MB module the upper 128MB get aliased with contents of the lower
  57  * 128MB); normally this define should be used for devices with real 32-bit
  58  * data path.
  59  */
  60 #undef CONFIG_DDR_32BIT
  61
  62 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  63 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  64 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  65 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  66                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  67 #define CONFIG_DDR_2T_TIMING
  68 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  69                                         | DDRCDR_ODT \
  70                                         | DDRCDR_Q_DRN)
  71                                         /* 0x80080001 */
  72
  73 /*
  74  * FLASH on the Local Bus
  75  */
  76 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  77 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  78 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
  79                                          BR_PS_16 |     /*  16bit */ \
  80                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
  81                                          BR_V)          /* valid */
  82
  83 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  84                                         | OR_GPCM_XAM \
  85                                         | OR_GPCM_CSNT \
  86                                         | OR_GPCM_ACS_DIV2 \
  87                                         | OR_GPCM_XACS \
  88                                         | OR_GPCM_SCY_15 \
  89                                         | OR_GPCM_TRLX_SET \
  90                                         | OR_GPCM_EHTR_SET \
  91                                         | OR_GPCM_EAD)
  92                                         /* 0xffc06ff7 */
  93 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
  94 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_4MB)
  95
  96 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
  97 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
  98                                         | BR_PS_32 \
  99                                         | BR_MS_GPCM \
 100                                         | BR_V)
 101                                         /* 0xF0001801 */
 102 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
 103                                         | OR_GPCM_SETA)
 104                                         /* 0xfffc0208 */
 105 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_WINDOW1_BASE
 106 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 107
 108 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 109 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 110
 111 #undef CONFIG_SYS_FLASH_CHECKSUM
 112 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 113 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 114
 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 116
 117 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 118 #define CONFIG_SYS_RAMBOOT
 119 #else
 120 #undef CONFIG_SYS_RAMBOOT
 121 #endif
 122
 123 #define CONFIG_SYS_INIT_RAM_LOCK        1
 124 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 125 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 126
 127 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 128                                          GENERATED_GBL_DATA_SIZE)
 129 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 130
 131 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 132 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 133
 134 /*
 135  * Local Bus LCRR and LBCR regs
 136  *    LCRR:  no DLL bypass, Clock divider is 4
 137  * External Local Bus rate is
 138  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 139  */
 140 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 141 #define CONFIG_SYS_LBC_LBCR     0x00000000
 142
 143 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 144
 145 /*
 146  * Serial Port
 147  */
 148 #define CONFIG_SYS_NS16550_SERIAL
 149 #define CONFIG_SYS_NS16550_REG_SIZE     1
 150 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 151
 152 #define CONFIG_SYS_BAUDRATE_TABLE  \
 153                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 154
 155 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 156 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 157
 158 /* I2C */
 159 #define CONFIG_SYS_I2C
 160 #define CONFIG_SYS_I2C_FSL
 161 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 162 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 163 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 164 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 165 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 166 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 167 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 168 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 169
 170 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 171
 172 /* TSEC */
 173 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 174 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 175 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 176 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 177
 178 /*
 179  * General PCI
 180  * Addresses are mapped 1-1.
 181  */
 182 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 183 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 184 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 185 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 186 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 187 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 188 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 189 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 190 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 191
 192 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 193 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 194 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 195 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 196 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 197 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 198 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 199 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 200 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 201
 202 #if defined(CONFIG_PCI)
 203
 204 #undef CONFIG_EEPRO100
 205 #undef CONFIG_TULIP
 206
 207 #if !defined(CONFIG_PCI_PNP)
 208         #define PCI_ENET0_IOADDR        0xFIXME
 209         #define PCI_ENET0_MEMADDR       0xFIXME
 210         #define PCI_IDSEL_NUMBER        0xFIXME
 211 #endif
 212
 213 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 214 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 215
 216 #endif  /* CONFIG_PCI */
 217
 218 /*
 219  * TSEC configuration
 220  */
 221
 222 #if defined(CONFIG_TSEC_ENET)
 223
 224 #define CONFIG_GMII                     /* MII PHY management */
 225 #define CONFIG_TSEC1
 226 #define CONFIG_TSEC1_NAME       "TSEC0"
 227 #define CONFIG_TSEC2
 228 #define CONFIG_TSEC2_NAME       "TSEC1"
 229 #define CONFIG_PHY_M88E1111
 230 #define TSEC1_PHY_ADDR          0x08
 231 #define TSEC2_PHY_ADDR          0x10
 232 #define TSEC1_PHYIDX            0
 233 #define TSEC2_PHYIDX            0
 234 #define TSEC1_FLAGS             TSEC_GIGABIT
 235 #define TSEC2_FLAGS             TSEC_GIGABIT
 236
 237 /* Options are: TSEC[0-1] */
 238 #define CONFIG_ETHPRIME         "TSEC0"
 239
 240 #endif  /* CONFIG_TSEC_ENET */
 241
 242 /*
 243  * Environment
 244  */
 245 #ifndef CONFIG_SYS_RAMBOOT
 246         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 247         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 248         #define CONFIG_ENV_SIZE         0x2000
 249
 250 /* Address and size of Redundant Environment Sector     */
 251 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 252 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 253
 254 #else
 255         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 256         #define CONFIG_ENV_SIZE         0x2000
 257 #endif
 258
 259 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 260 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 261
 262 /*
 263  * BOOTP options
 264  */
 265 #define CONFIG_BOOTP_BOOTFILESIZE
 266
 267 /*
 268  * Command line configuration.
 269  */
 270 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 271 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 272 #define CONFIG_RTC_RX8025
 273
 274 /* Pass Ethernet MAC to VxWorks */
 275 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 276
 277 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 278
 279 /*
 280  * Miscellaneous configurable options
 281  */
 282 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 283
 284 /*
 285  * For booting Linux, the board info and command line data
 286  * have to be in the first 256 MB of memory, since this is
 287  * the maximum mapped by the Linux kernel during initialization.
 288  */
 289 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 290
 291 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 292
 293 #define CONFIG_SYS_HRCW_LOW (\
 294         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 295         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 296         HRCWL_CSB_TO_CLKIN |\
 297         HRCWL_VCO_1X2 |\
 298         HRCWL_CORE_TO_CSB_2X1)
 299
 300 #if defined(PCI_64BIT)
 301 #define CONFIG_SYS_HRCW_HIGH (\
 302         HRCWH_PCI_HOST |\
 303         HRCWH_64_BIT_PCI |\
 304         HRCWH_PCI1_ARBITER_ENABLE |\
 305         HRCWH_PCI2_ARBITER_DISABLE |\
 306         HRCWH_CORE_ENABLE |\
 307         HRCWH_FROM_0X00000100 |\
 308         HRCWH_BOOTSEQ_DISABLE |\
 309         HRCWH_SW_WATCHDOG_DISABLE |\
 310         HRCWH_ROM_LOC_LOCAL_16BIT |\
 311         HRCWH_TSEC1M_IN_GMII |\
 312         HRCWH_TSEC2M_IN_GMII)
 313 #else
 314 #define CONFIG_SYS_HRCW_HIGH (\
 315         HRCWH_PCI_HOST |\
 316         HRCWH_32_BIT_PCI |\
 317         HRCWH_PCI1_ARBITER_ENABLE |\
 318         HRCWH_PCI2_ARBITER_ENABLE |\
 319         HRCWH_CORE_ENABLE |\
 320         HRCWH_FROM_0X00000100 |\
 321         HRCWH_BOOTSEQ_DISABLE |\
 322         HRCWH_SW_WATCHDOG_DISABLE |\
 323         HRCWH_ROM_LOC_LOCAL_16BIT |\
 324         HRCWH_TSEC1M_IN_GMII |\
 325         HRCWH_TSEC2M_IN_GMII)
 326 #endif
 327
 328 /* System IO Config */
 329 #define CONFIG_SYS_SICRH 0
 330 #define CONFIG_SYS_SICRL SICRL_LDP_A
 331
 332 #define CONFIG_SYS_HID0_INIT    0x000000000
 333 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 334                                  HID0_ENABLE_INSTRUCTION_CACHE)
 335
 336 #define CONFIG_SYS_HID2         HID2_HBE
 337
 338 #define CONFIG_SYS_GPIO1_PRELIM
 339 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 340 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 341
 342 #define CONFIG_SYS_GPIO2_PRELIM
 343 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 344 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 345
 346 #define CONFIG_HIGH_BATS                /* High BATs supported */
 347
 348 /* DDR @ 0x00000000 */
 349 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 350                                  BATL_MEMCOHERENCE)
 351 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 352                                  BATU_VS | BATU_VP)
 353
 354 /* PCI @ 0x80000000 */
 355 #ifdef CONFIG_PCI
 356 #define CONFIG_PCI_INDIRECT_BRIDGE
 357 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
 358                                  BATL_MEMCOHERENCE)
 359 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
 360                                  BATU_VS | BATU_VP)
 361 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
 362                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 363 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
 364                                  BATU_VS | BATU_VP)
 365 #else
 366 #define CONFIG_SYS_IBAT1L       (0)
 367 #define CONFIG_SYS_IBAT1U       (0)
 368 #define CONFIG_SYS_IBAT2L       (0)
 369 #define CONFIG_SYS_IBAT2U       (0)
 370 #endif
 371
 372 #ifdef CONFIG_MPC83XX_PCI2
 373 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
 374                                  BATL_MEMCOHERENCE)
 375 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
 376                                  BATU_VS | BATU_VP)
 377 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
 378                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 379 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
 380                                  BATU_VS | BATU_VP)
 381 #else
 382 #define CONFIG_SYS_IBAT3L       (0)
 383 #define CONFIG_SYS_IBAT3U       (0)
 384 #define CONFIG_SYS_IBAT4L       (0)
 385 #define CONFIG_SYS_IBAT4U       (0)
 386 #endif
 387
 388 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 389 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 390                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 391 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | \
 392                                  BATU_VS | BATU_VP)
 393
 394 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
 395 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 396
 397 #if (CONFIG_SYS_DDR_SIZE == 512)
 398 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 399                                  BATL_PP_RW | BATL_MEMCOHERENCE)
 400 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 401                                  BATU_BL_256M | BATU_VS | BATU_VP)
 402 #else
 403 #define CONFIG_SYS_IBAT7L       (0)
 404 #define CONFIG_SYS_IBAT7U       (0)
 405 #endif
 406
 407 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 408 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 409 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 410 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 411 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 412 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 413 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 414 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 415 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 416 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 417 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 418 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 419 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 420 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 421 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 422 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 423
 424 #if defined(CONFIG_CMD_KGDB)
 425 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 426 #endif
 427
 428 /*
 429  * Environment Configuration
 430  */
 431 #define CONFIG_ENV_OVERWRITE
 432
 433 #if defined(CONFIG_TSEC_ENET)
 434 #define CONFIG_HAS_ETH0
 435 #define CONFIG_HAS_ETH1
 436 #endif
 437
 438 #define CONFIG_HOSTNAME         "VME8349"
 439 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 440 #define CONFIG_BOOTFILE         "uImage"
 441
 442 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 443
 444 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 445         "netdev=eth0\0"                                                 \
 446         "hostname=vme8349\0"                                            \
 447         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 448                 "nfsroot=${serverip}:${rootpath}\0"                     \
 449         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 450         "addip=setenv bootargs ${bootargs} "                            \
 451                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 452                 ":${hostname}:${netdev}:off panic=1\0"                  \
 453         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 454         "flash_nfs=run nfsargs addip addtty;"                           \
 455                 "bootm ${kernel_addr}\0"                                \
 456         "flash_self=run ramargs addip addtty;"                          \
 457                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 458         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 459                 "bootm\0"                                               \
 460         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 461         "update=protect off fff00000 fff3ffff; "                        \
 462                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 463         "upd=run load update\0"                                         \
 464         "fdtaddr=780000\0"                                              \
 465         "fdtfile=vme8349.dtb\0"                                         \
 466         ""
 467
 468 #define CONFIG_NFSBOOTCOMMAND                                           \
 469         "setenv bootargs root=/dev/nfs rw "                             \
 470                 "nfsroot=$serverip:$rootpath "                          \
 471                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 472                                                         "$netdev:off "  \
 473                 "console=$consoledev,$baudrate $othbootargs;"           \
 474         "tftp $loadaddr $bootfile;"                                     \
 475         "tftp $fdtaddr $fdtfile;"                                       \
 476         "bootm $loadaddr - $fdtaddr"
 477
 478 #define CONFIG_RAMBOOTCOMMAND                                           \
 479         "setenv bootargs root=/dev/ram rw "                             \
 480                 "console=$consoledev,$baudrate $othbootargs;"           \
 481         "tftp $ramdiskaddr $ramdiskfile;"                               \
 482         "tftp $loadaddr $bootfile;"                                     \
 483         "tftp $fdtaddr $fdtfile;"                                       \
 484         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 485
 486 #define CONFIG_BOOTCOMMAND      "run flash_self"
 487
 488 #ifndef __ASSEMBLY__
 489 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 490                      unsigned char *buffer, int len);
 491 #endif
 492
 493 #endif  /* __CONFIG_H */