include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25
  26 /*
  27  * Hardware Reset Configuration Word
  28  * if CLKIN is 66.66MHz, then
  29  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  30  */
  31 #define CONFIG_SYS_HRCW_LOW (\
  32         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  33         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  34         HRCWL_SVCOD_DIV_2 |\
  35         HRCWL_CSB_TO_CLKIN_2X1 |\
  36         HRCWL_CORE_TO_CSB_3X1)
  37 #define CONFIG_SYS_HRCW_HIGH_BASE (\
  38         HRCWH_PCI_HOST |\
  39         HRCWH_PCI1_ARBITER_ENABLE |\
  40         HRCWH_CORE_ENABLE |\
  41         HRCWH_BOOTSEQ_DISABLE |\
  42         HRCWH_SW_WATCHDOG_DISABLE |\
  43         HRCWH_TSEC1M_IN_RGMII |\
  44         HRCWH_TSEC2M_IN_RGMII |\
  45         HRCWH_BIG_ENDIAN |\
  46         HRCWH_LALE_NORMAL)
  47
  48 #ifdef CONFIG_NAND_SPL
  49 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  50                        HRCWH_FROM_0XFFF00100 |\
  51                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
  52                        HRCWH_RL_EXT_NAND)
  53 #else
  54 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  55                        HRCWH_FROM_0X00000100 |\
  56                        HRCWH_ROM_LOC_LOCAL_16BIT |\
  57                        HRCWH_RL_EXT_LEGACY)
  58 #endif
  59
  60 /*
  61  * System IO Config
  62  */
  63 #define CONFIG_SYS_SICRH                0x00000000
  64 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  65
  66 #define CONFIG_HWCONFIG
  67
  68 /*
  69  * IMMR new address
  70  */
  71 #define CONFIG_SYS_IMMR         0xE0000000
  72
  73 /*
  74  * Arbiter Setup
  75  */
  76 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  77 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  78 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  79
  80 /*
  81  * DDR Setup
  82  */
  83 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  84 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  86 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  87 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  88                                 | DDRCDR_PZ_LOZ \
  89                                 | DDRCDR_NZ_LOZ \
  90                                 | DDRCDR_ODT \
  91                                 | DDRCDR_Q_DRN)
  92                                 /* 0x7b880001 */
  93 /*
  94  * Manually set up DDR parameters
  95  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  96  */
  97 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  98 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  99 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 100                                 | CSCONFIG_ODT_RD_NEVER \
 101                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 102                                 | CSCONFIG_ROW_BIT_13 \
 103                                 | CSCONFIG_COL_BIT_10)
 104                                 /* 0x80010102 */
 105 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 106 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 107                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 108                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 109                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 110                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 111                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 112                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 113                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 114                                 /* 0x00220802 */
 115 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 116                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 117                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 118                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 119                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 120                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 121                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 122                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 123                                 /* 0x27256222 */
 124 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 125                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 126                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 127                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 128                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 129                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 130                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 131                                 /* 0x121048c5 */
 132 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 133                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 134                                 /* 0x03600100 */
 135 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 136                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 137                                 | SDRAM_CFG_DBW_32)
 138                                 /* 0x43080000 */
 139 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 140 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 141                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 142                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 143 #define CONFIG_SYS_DDR_MODE2    0x00000000
 144
 145 /*
 146  * Memory test
 147  */
 148 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 149 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 150 #define CONFIG_SYS_MEMTEST_END          0x00140000
 151
 152 /*
 153  * The reserved memory
 154  */
 155 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 156 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 157
 158 /*
 159  * Initial RAM Base Address Setup
 160  */
 161 #define CONFIG_SYS_INIT_RAM_LOCK        1
 162 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 163 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 164 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 165                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 166
 167 /*
 168  * Local Bus Configuration & Clock Setup
 169  */
 170 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 171 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 172 #define CONFIG_SYS_LBC_LBCR             0x00040000
 173 #define CONFIG_FSL_ELBC         1
 174
 175 /*
 176  * FLASH on the Local Bus
 177  */
 178 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 179
 180 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 181 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 182
 183                                         /* Window base at flash base */
 184 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 185 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 186
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 188 /* 127 64KB sectors and 8 8KB top sectors per device */
 189 #define CONFIG_SYS_MAX_FLASH_SECT       135
 190
 191 #undef CONFIG_SYS_FLASH_CHECKSUM
 192 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 193 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 194
 195 /*
 196  * NAND Flash on the Local Bus
 197  */
 198
 199 #ifdef CONFIG_NAND_SPL
 200 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 201 #else
 202 #define CONFIG_SYS_NAND_BASE            0xE0600000
 203 #endif
 204
 205 #define CONFIG_MTD_PARTITION
 206
 207 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 208 #define CONFIG_NAND_FSL_ELBC            1
 209 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 210 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 211
 212 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 213 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 214 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 215 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 216 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 217
 218 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
 219                                         | BR_PS_16      /* 16 bit port */ \
 220                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 221                                         | BR_V)         /* valid */
 222 #define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
 223                                         | OR_UPM_XAM \
 224                                         | OR_GPCM_CSNT \
 225                                         | OR_GPCM_ACS_DIV2 \
 226                                         | OR_GPCM_XACS \
 227                                         | OR_GPCM_SCY_15 \
 228                                         | OR_GPCM_TRLX_SET \
 229                                         | OR_GPCM_EHTR_SET \
 230                                         | OR_GPCM_EAD)
 231 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
 232                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 233                                 | BR_PS_8               /* 8 bit port */ \
 234                                 | BR_MS_FCM             /* MSEL = FCM */ \
 235                                 | BR_V)                 /* valid */
 236 #define CONFIG_SYS_OR1_PRELIM \
 237                                 (OR_AM_32KB \
 238                                 | OR_FCM_CSCT \
 239                                 | OR_FCM_CST \
 240                                 | OR_FCM_CHT \
 241                                 | OR_FCM_SCY_1 \
 242                                 | OR_FCM_TRLX \
 243                                 | OR_FCM_EHTR)
 244                                 /* 0xFFFF8396 */
 245
 246 /* Still needed for spl_minimal.c */
 247 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 248 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 249
 250 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 251 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 252
 253 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 254 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 255
 256 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 257         !defined(CONFIG_NAND_SPL)
 258 #define CONFIG_SYS_RAMBOOT
 259 #else
 260 #undef CONFIG_SYS_RAMBOOT
 261 #endif
 262
 263 /*
 264  * Serial Port
 265  */
 266 #define CONFIG_SYS_NS16550_SERIAL
 267 #define CONFIG_SYS_NS16550_REG_SIZE     1
 268 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 269
 270 #define CONFIG_SYS_BAUDRATE_TABLE  \
 271                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 272
 273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 275
 276 /* I2C */
 277 #define CONFIG_SYS_I2C
 278 #define CONFIG_SYS_I2C_FSL
 279 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 280 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 281 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 282 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 283
 284 /*
 285  * Board info - revision and where boot from
 286  */
 287 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 288
 289 /*
 290  * Config on-board RTC
 291  */
 292 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 293 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 294
 295 /*
 296  * General PCI
 297  * Addresses are mapped 1-1.
 298  */
 299 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 300 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 301 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 302 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 303 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 304 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 305 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 306 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 307 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 308
 309 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 310 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 311 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 312
 313 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 314 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 315 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 316 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 317 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 318 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 319 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 320 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 321 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 322
 323 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 324 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 325 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 326 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 327 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 328 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 329 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 330 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 331 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 332
 333 #define CONFIG_PCI_INDIRECT_BRIDGE
 334 #define CONFIG_PCIE
 335
 336 #define CONFIG_EEPRO100
 337 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 338 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 339
 340 #define CONFIG_HAS_FSL_DR_USB
 341 #define CONFIG_SYS_SCCR_USBDRCM         3
 342
 343 #define CONFIG_USB_EHCI_FSL
 344 #define CONFIG_USB_PHY_TYPE     "utmi"
 345 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 346
 347 /*
 348  * TSEC
 349  */
 350 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 351 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 352 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 353 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 354
 355 /*
 356  * TSEC ethernet configuration
 357  */
 358 #define CONFIG_TSEC1            1
 359 #define CONFIG_TSEC1_NAME       "eTSEC0"
 360 #define CONFIG_TSEC2            1
 361 #define CONFIG_TSEC2_NAME       "eTSEC1"
 362 #define TSEC1_PHY_ADDR          0
 363 #define TSEC2_PHY_ADDR          1
 364 #define TSEC1_PHYIDX            0
 365 #define TSEC2_PHYIDX            0
 366 #define TSEC1_FLAGS             TSEC_GIGABIT
 367 #define TSEC2_FLAGS             TSEC_GIGABIT
 368
 369 /* Options are: eTSEC[0-1] */
 370 #define CONFIG_ETHPRIME         "eTSEC1"
 371
 372 /*
 373  * SATA
 374  */
 375 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 376 #define CONFIG_SATA1
 377 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 378 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 379 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 380 #define CONFIG_SATA2
 381 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 382 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 383 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 384
 385 #ifdef CONFIG_FSL_SATA
 386 #define CONFIG_LBA48
 387 #endif
 388
 389 /*
 390  * Environment
 391  */
 392 #if !defined(CONFIG_SYS_RAMBOOT)
 393         #define CONFIG_ENV_ADDR         \
 394                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 395         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 396         #define CONFIG_ENV_SIZE         0x2000
 397 #else
 398         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 399         #define CONFIG_ENV_SIZE         0x2000
 400 #endif
 401
 402 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 404
 405 /*
 406  * BOOTP options
 407  */
 408 #define CONFIG_BOOTP_BOOTFILESIZE
 409
 410 /*
 411  * Command line configuration.
 412  */
 413
 414 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 415
 416 /*
 417  * Miscellaneous configurable options
 418  */
 419 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 420
 421 /*
 422  * For booting Linux, the board info and command line data
 423  * have to be in the first 256 MB of memory, since this is
 424  * the maximum mapped by the Linux kernel during initialization.
 425  */
 426 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 427 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 428
 429 /*
 430  * Core HID Setup
 431  */
 432 #define CONFIG_SYS_HID0_INIT    0x000000000
 433 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 434                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 435                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 436 #define CONFIG_SYS_HID2         HID2_HBE
 437
 438 /*
 439  * MMU Setup
 440  */
 441 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 442
 443 /* DDR: cache cacheable */
 444 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 445                                 | BATL_PP_RW \
 446                                 | BATL_MEMCOHERENCE)
 447 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 448                                 | BATU_BL_128M \
 449                                 | BATU_VS \
 450                                 | BATU_VP)
 451 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 452 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 453
 454 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 455 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 456                                 | BATL_PP_RW \
 457                                 | BATL_CACHEINHIBIT \
 458                                 | BATL_GUARDEDSTORAGE)
 459 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 460                                 | BATU_BL_8M \
 461                                 | BATU_VS \
 462                                 | BATU_VP)
 463 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 464 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 465
 466 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 467 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 468                                 | BATL_PP_RW \
 469                                 | BATL_MEMCOHERENCE)
 470 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 471                                 | BATU_BL_32M \
 472                                 | BATU_VS \
 473                                 | BATU_VP)
 474 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 475                                 | BATL_PP_RW \
 476                                 | BATL_CACHEINHIBIT \
 477                                 | BATL_GUARDEDSTORAGE)
 478 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 479
 480 /* Stack in dcache: cacheable, no memory coherence */
 481 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 482 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR \
 483                                 | BATU_BL_128K \
 484                                 | BATU_VS \
 485                                 | BATU_VP)
 486 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 487 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 488
 489 /* PCI MEM space: cacheable */
 490 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS \
 491                                 | BATL_PP_RW \
 492                                 | BATL_MEMCOHERENCE)
 493 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS \
 494                                 | BATU_BL_256M \
 495                                 | BATU_VS \
 496                                 | BATU_VP)
 497 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 498 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 499
 500 /* PCI MMIO space: cache-inhibit and guarded */
 501 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS \
 502                                 | BATL_PP_RW \
 503                                 | BATL_CACHEINHIBIT \
 504                                 | BATL_GUARDEDSTORAGE)
 505 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS \
 506                                 | BATU_BL_256M \
 507                                 | BATU_VS \
 508                                 | BATU_VP)
 509 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 510 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 511
 512 #define CONFIG_SYS_IBAT6L       0
 513 #define CONFIG_SYS_IBAT6U       0
 514 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 515 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 516
 517 #define CONFIG_SYS_IBAT7L       0
 518 #define CONFIG_SYS_IBAT7U       0
 519 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 520 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 521
 522 #if defined(CONFIG_CMD_KGDB)
 523 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 524 #endif
 525
 526 /*
 527  * Environment Configuration
 528  */
 529
 530 #define CONFIG_ENV_OVERWRITE
 531
 532 #if defined(CONFIG_TSEC_ENET)
 533 #define CONFIG_HAS_ETH0
 534 #define CONFIG_HAS_ETH1
 535 #endif
 536
 537 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 538
 539 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 540         "netdev=eth0\0"                                                 \
 541         "consoledev=ttyS0\0"                                            \
 542         "ramdiskaddr=1000000\0"                                         \
 543         "ramdiskfile=ramfs.83xx\0"                                      \
 544         "fdtaddr=780000\0"                                              \
 545         "fdtfile=mpc8315erdb.dtb\0"                                     \
 546         "usb_phy_type=utmi\0"                                           \
 547         ""
 548
 549 #define CONFIG_NFSBOOTCOMMAND                                           \
 550         "setenv bootargs root=/dev/nfs rw "                             \
 551                 "nfsroot=$serverip:$rootpath "                          \
 552                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 553                                                         "$netdev:off "  \
 554                 "console=$consoledev,$baudrate $othbootargs;"           \
 555         "tftp $loadaddr $bootfile;"                                     \
 556         "tftp $fdtaddr $fdtfile;"                                       \
 557         "bootm $loadaddr - $fdtaddr"
 558
 559 #define CONFIG_RAMBOOTCOMMAND                                           \
 560         "setenv bootargs root=/dev/ram rw "                             \
 561                 "console=$consoledev,$baudrate $othbootargs;"           \
 562         "tftp $ramdiskaddr $ramdiskfile;"                               \
 563         "tftp $loadaddr $bootfile;"                                     \
 564         "tftp $fdtaddr $fdtfile;"                                       \
 565         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 566
 567 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 568
 569 #endif  /* __CONFIG_H */