boards with QUICC Engines require OF_QE to set UCC MAC
addresses
- CONFIG_OF_BOARD_SETUP
-
- Board code has addition modification that it wants to make
- to the flat device tree before handing it off to the kernel
-
CONFIG_OF_SYSTEM_SETUP
Other code has addition modification that it wants to make
Note: If a "bootargs" environment is defined, it will override
the defaults discussed just above.
-- Cache Configuration:
- CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
-
- Cache Configuration for ARM:
CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
controller
SPI EEPROM, also an instance works with Crystal A/D and
D/As on the SACSng board)
- CONFIG_SOFT_SPI
-
- Enables a software (bit-bang) SPI driver rather than
- using hardware support. This is a general purpose
- driver that only requires three general I/O port pins
- (two outputs, one input) to function. If this is
- defined, the board configuration must define several
- SPI configuration items (port pins to use, etc). For
- an example, see include/configs/sacsng.h.
-
CONFIG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */
Time to wait after FPGA configuration. The default is
200 ms.
-- Configuration Management:
-
- CONFIG_IDENT_STRING
-
- If defined, this string will be added to the U-Boot
- version information (U_BOOT_VERSION)
-
- Vendor Parameter Protection:
U-Boot considers the values of the environment
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
- Partition on the MMC to load U-Boot from when the MMC is being
- used in raw mode
-
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
Sector to load kernel uImage from when MMC is being
used in raw mode (for Falcon mode)
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select FSL_TZASC_1
+ select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZPC_BP147
select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZPC_BP147
select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
config SYS_MALLOC_F_LEN
default 0x4000
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default SYS_TEXT_BASE
+
endif
config IMXRT
bool
+ select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
bool
endchoice
+config SYS_PLLFIN
+ int
+
+config TIMER_SYS_TICK_CH
+ int
+
config SYS_BOARD
default "nanopi2"
config SYS_CONFIG_NAME
default "s5p4418_nanopi2"
-endmenu
-
config SYS_PLLFIN
- int
+ default 24000000
config TIMER_SYS_TICK_CH
- int
+ default 0
+
+endmenu
source "board/friendlyarm/Kconfig"
bool
select FSL_LAW
select SYS_CACHE_SHIFT_5
+ select SYS_HAS_SERDES
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
config SYS_FSL_ERRATUM_USB14
bool
+config SYS_HAS_SERDES
+ bool
+
config SYS_P4080_ERRATUM_CPU22
bool
F: include/configs/capricorn-common.h
F: include/configs/deneb.h
F: include/configs/giedi.h
-F: include/configs/siemens-ccp-common.h
F: include/configs/siemens-env-common.h
F: configs/deneb_defconfig
F: configs/giedi_defconfig
config SYS_CONFIG_NAME
default "xenguest_arm64"
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default SYS_LOAD_ADDR
+
endif
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
+CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
+CONFIG_MVGBE=y
CONFIG_MII=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0x280000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x380000
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0x10400
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x130000
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0xEFF10000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
+CONFIG_SYS_NS16550=y
# CONFIG_EFI_LOADER is not set
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_BCMSTB_SPI=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
# CONFIG_SPL_BANNER_PRINT is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c
CONFIG_SPL_MMC_TINY=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_JZ4780_EFUSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_IDENT_STRING=" ##v01.06"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DMA_LPC32XX=y
+CONFIG_LPC32XX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x61000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_IDENT_STRING=" ##v01.07"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
CONFIG_SPL_DMA=y
CONFIG_SPL_MMC_TINY=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_FUSE=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
# CONFIG_MMC is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
# CONFIG_MMC is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_AHCI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg"
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
# CONFIG_SPL_BLK is not set
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
# CONFIG_SPL_BLK is not set
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SUPPORT_PASSING_ATAGS=y
CONFIG_CMDLINE_TAG=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x81000100
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=1026
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=1026
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x44800000
CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_MTD=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX8998=y
+CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Samsung"
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DM_GPIO=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SPL_GPIO=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x63300000
CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
CONFIG_SYS_TEXT_BASE=0x60800000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MACB=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_LPC32XX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x40080000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
+CONFIG_NR_DRAM_BANKS=1
CONFIG_IDENT_STRING=" xenguest"
CONFIG_SYS_LOAD_ADDR=0x40000000
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_PROMPT="xenguest# "
# CONFIG_CMD_BDI is not set
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_SYS_MALLOC_LEN=0x8000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_SYS_MALLOC_LEN=0x1000
*/
#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_NETDEV "eth1"
#endif
/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
#endif
#endif
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#ifdef CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#endif
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_U_QE
-
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
* USB
*/
#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#endif
* USB
*/
#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#endif
/*
* USB
*/
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_USBD_HS
/* Framebuffer and LCD */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_SYS_SDRAM_BASE 0x880000000
-#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_TEXT_BASE
-
/* Environment */
#define ENV_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.
*/
-#define CONFIG_SYS_FDT_SAVE_ADDRESS 0x1f00000
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
*/
#define V_NS16550_CLK 81000000
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Flash configuration.
*/
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_MACRONIX
/*
* Filesystem configuration.
#include <asm/arch/imx-regs.h>
#include "siemens-env-common.h"
-#include "siemens-ccp-common.h"
/* SPL config */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_FACTORYSET
-#undef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
-
#define CONFIG_REMAKE_ELF
/* ENET Config */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_REMAKE_ELF
/* Flat Device Tree Definitions */
-#define CONFIG_OF_BOARD_SETUP
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
/* Miscellaneous configuration options */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
-
#endif /* __CONFIG_CI20_H__ */
#include "mx6_common.h"
/* Machine config */
-#define CONFIG_SYS_LITTLE_ENDIAN
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_USBD_HS
/* Framebuffer and LCD */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#include "capricorn-common.h"
-#undef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "06")
-
/* DDR3 board total DDR is 2 GB */
#undef PHYS_SDRAM_1_SIZE
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/*
* GPIO
*/
-#define CONFIG_LPC32XX_GPIO
/*
* Ethernet
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
*/
/* nedded by compliance test in read mode */
-#if defined(CONFIG_SPL_CMT)
-#define CONFIG_SYS_DCACHE_OFF
-#endif
/* Define own nand partitions */
#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
#endif
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* Memory Info */
-#define CONFIG_SYS_LOAD_ADDR 0x83000000
-
/* Misc */
#define CONFIG_EXTRA_ENV_SETTINGS \
""
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* Memory Info */
-#define CONFIG_SYS_LOAD_ADDR 0x83000000
-
/* Misc */
#define STR_HELPER(s) #s
#define STR(s) STR_HELPER(s)
#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
-#define CONFIG_DEBUG_UART_CLOCK 132710400
-
-#define CONFIG_PREBOOT \
-"echo Read pressed buttons status;" \
-"KEY_VOLUMEUP=gpa20;" \
-"KEY_HOME=gpa17;" \
-"KEY_VOLUMEDOWN=gpa21;" \
-"KEY_POWER=gpa00;" \
-"PRESSED=0;" \
-"RELEASED=1;" \
-"if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; " \
-"else setenv VOLUME_UP $RELEASED; fi;" \
-"if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; " \
-"else setenv VOLUME_DOWN $RELEASED; fi;" \
-"if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;" \
-"if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
-
#ifndef MEM_LAYOUT_ENV_SETTINGS
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
#include "capricorn-common.h"
-#undef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
-
/* DDR3 board total DDR is 1 GB */
#undef PHYS_SDRAM_1_SIZE
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_IDE */
-/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_IB62x0_H */
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x187FF0
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_OF_SYSTEM_SETUP
-
#endif
#define CONFIG_SPL_MAX_SIZE (172 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_OF_SYSTEM_SETUP
-
#endif
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_REMAKE_ELF
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_BOARD_SETUP
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_REMAKE_ELF
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_BOARD_SETUP
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define CONFIG_SYS_BOOTM_LEN (SZ_64M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#define PHYS_SDRAM 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#define PHYS_SDRAM 0x80000000
* Retain non-DM serial port for debug purposes.
*/
#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
/* I2C */
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#include "ls1012a_common.h"
-#undef CONFIG_SYS_BOARD
-#define CONFIG_SYS_BOARD "ls1012afrwy"
-
/* Board Rev*/
#define BOARD_REV_A_B 0x0
#define BOARD_REV_C 0x00080000
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_SST /* cs1 */
#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_EON /* cs3 */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define SDRAM_CFG_BI 0x00000001
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
-
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_SPL_PAD_TO 0x1c000
CONFIG_SYS_SCSI_MAX_LUN)
/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
/*
* eTSEC
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
#include <asm/fsl_secure_boot.h>
#endif
*/
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
*/
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define __L1028A_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_MP
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#endif
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* IFC */
#ifndef SPL_NO_IFC
#endif
/* DSPI */
-#ifndef SPL_NO_DSPI
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
-#define CONFIG_SPI_FLASH_SST /* cs1 */
-#define CONFIG_SPI_FLASH_EON /* cs2 */
-#endif
-#endif
/* FMan ucode */
#ifndef SPL_NO_FMAN
#endif
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#define CPU_RELEASE_ADDR secondary_boot_addr
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#if !defined(CONFIG_TFABOOT) && \
!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#endif
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
-#endif
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
/*
* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
*/
#define RTC
#define CONFIG_RTC_DS3231 1
-#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#if defined(CONFIG_FSL_DSPI)
-#define CONFIG_SPI_FLASH_STMICRO
-#endif
/*
* RTC configuration
#include <asm/arch/soc.h>
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_MEMAC
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#endif
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#define CONFIG_IOMUX_LPSR
-#define CONFIG_SOFT_SPI
-
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
/*
* High Level Configuration Options
*/
-#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_LBA48
#endif /* CONFIG_SATA */
-/* RTC driver configuration */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_NSA310S_H */
#ifndef __OCTEONTX2_COMMON_H__
#define __OCTEONTX2_COMMON_H__
-#define CONFIG_SUPPORT_RAW_INITRD
-
/** Maximum size of image supported for bootm (and bootable FIT images) */
#define CONFIG_SYS_BOOTM_LEN (256 << 20)
# define CONFIG_SYS_64BIT_LBA
#endif
-/***** SPI Defines *********/
-#ifdef CONFIG_DM_SPI_FLASH
-# define CONFIG_SF_DEFAULT_BUS 0
-# define CONFIG_SF_DEFAULT_CS 0
-#endif
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
* Need to override existing one (smdk5420) with odroid so set_board_info will
* use proper prefix when creating full board_name (SYS_BOARD + type)
*/
-#undef CONFIG_SYS_BOARD
-#define CONFIG_SYS_BOARD "odroid"
/* Define new extra env settings, including DFU settings */
#undef CONFIG_EXTRA_ENV_SETTINGS
#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
#endif
#endif
/* Environment at end of QSPI, in the VER partition */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#define CONFIG_PREBOOT
-
#define BOARD_EXTRA_ENV_SETTINGS \
"preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
"load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_OF_SYSTEM_SETUP
-
#define CONFIG_SYS_BOOTM_LEN SZ_128M
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_SUPPORT_RAW_INITRD
-
#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
#define CONFIG_SYS_BOOTM_LEN 0x00c00000
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
/* spl size 32kb sram - 2kb bootrom */
#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
-#define CONFIG_ROCKCHIP_SERIAL 1
#define CONFIG_SPL_STACK 0x10087fff
#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_NS16550_MEM32
(void *)PHY_BASEADDR_UART3}
/*-----------------------------------------------------------------------
- * PLL
- */
-#define CONFIG_SYS_PLLFIN 24000000UL
-
-/*-----------------------------------------------------------------------
- * Timer
- */
-#define CONFIG_TIMER_SYS_TICK_CH 0
-
-/*-----------------------------------------------------------------------
* BACKLIGHT
*/
#ifndef CONFIG_S5P4418_ONEWIRE
#define CONFIG_TIZEN /* TIZEN lib */
/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_L2CACHE_OFF 1
/* Universal has 2 banks of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-/*
- * SPI Settings
- */
-#define CONFIG_SOFT_SPI
-
#ifndef __ASSEMBLY__
void universal_spi_scl(int bit);
void universal_spi_sda(int bit);
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-/* NAND flash */
-
-/* SPI flash */
-#define CONFIG_SF_DEFAULT_SPEED 66000000
-
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
#define FAT_ENV_INTERFACE "mmc"
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/* Be very careful updating CONFIG_IDENT_STRING
- * This string will control the update flow whether an U-Boot should be
- * updated or not. If the version of installed U-Boot (in flash) is smaller
- * than the version to be installed (from update file), an update will
- * be performed.
- *
- * General rules:
- * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number
- * to identify the following strings after easily. Don't change them!
- *
- * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version
- * change, e.g. from 2015.04 to 2018.03
- *
- * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade
- * U-Boot within an U-Boot version.
- */
-#define CCP_IDENT_MAGIC " ##v"
-#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV \
BOOTENV_SF
-
-#define CONFIG_PREBOOT \
- "setenv fdt_addr ${fdtcontroladdr};" \
- "fdt addr ${fdtcontroladdr};"
#endif
#endif /* __CONFIG_H */
"partitions=" PARTS_DEFAULT "\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
-
-#define CONFIG_PREBOOT \
- "setenv fdt_addr ${fdtcontroladdr};" \
- "fdt addr ${fdtcontroladdr};"
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_TFTP_PORT
-/* MMC */
-#define CONFIG_GENERIC_ATMEL_MCI
-
/* LCD */
#define CONFIG_ATMEL_LCD
#define CONFIG_GURNARD_SPLASH
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#else
-#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
-#endif
#endif
/* SPL QSPI boot support */
/* Flash device info */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif /* CONFIG_SPL_BUILD */
/*
* High Level Configuration Options
*/
-#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#include <asm/arch/tegra.h> /* get chip and board defs */
#define CONFIG_TIZEN /* TIZEN lib */
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
#define CONFIG_TIZEN /* TIZEN lib */
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Board info register */
#define SYS_ID V2M_SYSREGS
-#define CONFIG_SYS_L2CACHE_OFF 1
-
#define SCTL_BASE V2M_SYSCTL
#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_STMICRO
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI 0xfc000000
#define CONFIG_SYS_MMC_CLK_OD 500000
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM3 0xb0000e00
-#define CONFIG_CONS_INDEX 3
/* RAM */
* GPIO
*/
-#define CONFIG_LPC32XX_GPIO
-
/*
* Environment
*/
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200)
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (SZ_1M / 0x200)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_MTD
-#endif
-
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
#define CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_NR_DRAM_BANKS
#undef CONFIG_SYS_SDRAM_BASE
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*
- * This can be any arbitrary address as we are using PIE, but
- * please note, that CONFIG_SYS_TEXT_BASE must match the below.
- */
-#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_OF_SYSTEM_SETUP
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \
#define CONFIG_REMAKE_ELF
/* Cache options */
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
# define CONFIG_SYS_PL310_BASE 0xf8f02000
projects / platform / kernel / u-boot.git / commitdiff