8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
51 select SYS_CACHE_SHIFT_5
53 config TARGET_P1010RDB_PA
54 bool "Support P1010RDB_PA"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 config TARGET_P1010RDB_PB
64 bool "Support P1010RDB_PB"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 config TARGET_P1020RDB_PC
74 bool "Support P1020RDB-PC"
82 config TARGET_P1020RDB_PD
83 bool "Support P1020RDB-PD"
91 config TARGET_P2020RDB
92 bool "Support P2020RDB-PC"
100 config TARGET_P2041RDB
101 bool "Support P2041RDB"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_QEMU_PPCE500
109 bool "Support qemu-ppce500"
110 select ARCH_QEMU_E500
112 imply OF_HAS_PRIOR_STAGE
114 config TARGET_T1024RDB
115 bool "Support T1024RDB"
117 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 select FSL_DDR_INTERACTIVE
124 config TARGET_T1042RDB
125 bool "Support T1042RDB"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
131 config TARGET_T1042D4RDB
132 bool "Support T1042D4RDB"
134 select BOARD_LATE_INIT if CHAIN_OF_TRUST
139 config TARGET_T1042RDB_PI
140 bool "Support T1042RDB_PI"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_T2080QDS
148 bool "Support T2080QDS"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
153 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
154 select FSL_DDR_INTERACTIVE
157 config TARGET_T2080RDB
158 bool "Support T2080RDB"
160 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_T4240RDB
167 bool "Support T4240RDB"
171 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
175 config TARGET_KMP204X
176 bool "Support kmp204x"
179 config TARGET_KMCENT2
180 bool "Support kmcent2"
190 select SYS_FSL_DDR_VER_47
191 select SYS_FSL_ERRATUM_A004477
192 select SYS_FSL_ERRATUM_A005871
193 select SYS_FSL_ERRATUM_A006379
194 select SYS_FSL_ERRATUM_A006384
195 select SYS_FSL_ERRATUM_A006475
196 select SYS_FSL_ERRATUM_A006593
197 select SYS_FSL_ERRATUM_A007075
198 select SYS_FSL_ERRATUM_A007186
199 select SYS_FSL_ERRATUM_A007212
200 select SYS_FSL_ERRATUM_A009942
201 select SYS_FSL_HAS_DDR3
202 select SYS_FSL_HAS_SEC
203 select SYS_FSL_QORIQ_CHASSIS2
204 select SYS_FSL_SEC_BE
205 select SYS_FSL_SEC_COMPAT_4
217 select SYS_FSL_DDR_VER_47
218 select SYS_FSL_ERRATUM_A004477
219 select SYS_FSL_ERRATUM_A005871
220 select SYS_FSL_ERRATUM_A006379
221 select SYS_FSL_ERRATUM_A006384
222 select SYS_FSL_ERRATUM_A006475
223 select SYS_FSL_ERRATUM_A006593
224 select SYS_FSL_ERRATUM_A007075
225 select SYS_FSL_ERRATUM_A007186
226 select SYS_FSL_ERRATUM_A007212
227 select SYS_FSL_ERRATUM_A007907
228 select SYS_FSL_ERRATUM_A009942
229 select SYS_FSL_HAS_DDR3
230 select SYS_FSL_HAS_SEC
231 select SYS_FSL_QORIQ_CHASSIS2
232 select SYS_FSL_SEC_BE
233 select SYS_FSL_SEC_COMPAT_4
243 select SYS_FSL_DDR_VER_44
244 select SYS_FSL_ERRATUM_A004477
245 select SYS_FSL_ERRATUM_A005125
246 select SYS_FSL_ERRATUM_ESDHC111
247 select SYS_FSL_HAS_DDR3
248 select SYS_FSL_HAS_SEC
249 select SYS_FSL_SEC_BE
250 select SYS_FSL_SEC_COMPAT_4
259 select SYS_FSL_DDR_VER_46
260 select SYS_FSL_ERRATUM_A004477
261 select SYS_FSL_ERRATUM_A005125
262 select SYS_FSL_ERRATUM_A005434
263 select SYS_FSL_ERRATUM_ESDHC111
264 select SYS_FSL_ERRATUM_I2C_A004447
265 select SYS_FSL_ERRATUM_IFC_A002769
266 select FSL_PCIE_RESET
267 select SYS_FSL_HAS_DDR3
268 select SYS_FSL_HAS_SEC
269 select SYS_FSL_SEC_BE
270 select SYS_FSL_SEC_COMPAT_4
271 select SYS_PPC_E500_USE_DEBUG_TLB
282 select SYS_FSL_DDR_VER_46
283 select SYS_FSL_ERRATUM_A005125
284 select SYS_FSL_ERRATUM_ESDHC111
285 select FSL_PCIE_RESET
286 select SYS_FSL_HAS_DDR3
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_6
290 select SYS_PPC_E500_USE_DEBUG_TLB
299 select SYS_FSL_ERRATUM_A004508
300 select SYS_FSL_ERRATUM_A005125
301 select FSL_PCIE_RESET
302 select SYS_FSL_HAS_DDR2
303 select SYS_FSL_HAS_DDR3
304 select SYS_FSL_HAS_SEC
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_2
307 select SYS_PPC_E500_USE_DEBUG_TLB
316 select SYS_FSL_HAS_DDR1
321 select SYS_CACHE_SHIFT_5
322 select SYS_FSL_ERRATUM_A005125
323 select FSL_PCIE_RESET
324 select SYS_FSL_HAS_DDR2
325 select SYS_FSL_HAS_SEC
326 select SYS_FSL_SEC_BE
327 select SYS_FSL_SEC_COMPAT_2
328 select SYS_PPC_E500_USE_DEBUG_TLB
334 select SYS_FSL_ERRATUM_A005125
335 select SYS_FSL_ERRATUM_NMG_DDR120
336 select SYS_FSL_ERRATUM_NMG_LBC103
337 select SYS_FSL_ERRATUM_NMG_ETSEC129
338 select SYS_FSL_ERRATUM_I2C_A004447
339 select FSL_PCIE_RESET
340 select SYS_FSL_HAS_DDR2
341 select SYS_FSL_HAS_DDR1
342 select SYS_FSL_HAS_SEC
343 select SYS_FSL_SEC_BE
344 select SYS_FSL_SEC_COMPAT_2
345 select SYS_PPC_E500_USE_DEBUG_TLB
351 select SYS_FSL_HAS_DDR1
356 select SYS_CACHE_SHIFT_5
357 select SYS_HAS_SERDES
358 select SYS_FSL_ERRATUM_A004477
359 select SYS_FSL_ERRATUM_A004508
360 select SYS_FSL_ERRATUM_A005125
361 select SYS_FSL_ERRATUM_A005275
362 select SYS_FSL_ERRATUM_A006261
363 select SYS_FSL_ERRATUM_A007075
364 select SYS_FSL_ERRATUM_ESDHC111
365 select SYS_FSL_ERRATUM_I2C_A004447
366 select SYS_FSL_ERRATUM_IFC_A002769
367 select SYS_FSL_ERRATUM_P1010_A003549
368 select SYS_FSL_ERRATUM_SEC_A003571
369 select SYS_FSL_ERRATUM_IFC_A003399
370 select FSL_PCIE_RESET
371 select SYS_FSL_HAS_DDR3
372 select SYS_FSL_HAS_SEC
373 select SYS_FSL_SEC_BE
374 select SYS_FSL_SEC_COMPAT_4
375 select SYS_PPC_E500_USE_DEBUG_TLB
388 select SYS_FSL_ERRATUM_A004508
389 select SYS_FSL_ERRATUM_A005125
390 select SYS_FSL_ERRATUM_ELBC_A001
391 select SYS_FSL_ERRATUM_ESDHC111
392 select FSL_PCIE_DISABLE_ASPM
393 select SYS_FSL_HAS_DDR3
394 select SYS_FSL_HAS_SEC
395 select SYS_FSL_SEC_BE
396 select SYS_FSL_SEC_COMPAT_2
397 select SYS_PPC_E500_USE_DEBUG_TLB
403 select SYS_CACHE_SHIFT_5
404 select SYS_FSL_ERRATUM_A004508
405 select SYS_FSL_ERRATUM_A005125
406 select SYS_FSL_ERRATUM_ELBC_A001
407 select SYS_FSL_ERRATUM_ESDHC111
408 select FSL_PCIE_DISABLE_ASPM
409 select FSL_PCIE_RESET
410 select SYS_FSL_HAS_DDR3
411 select SYS_FSL_HAS_SEC
412 select SYS_FSL_SEC_BE
413 select SYS_FSL_SEC_COMPAT_2
414 select SYS_PPC_E500_USE_DEBUG_TLB
425 select SYS_FSL_ERRATUM_A004508
426 select SYS_FSL_ERRATUM_A005125
427 select SYS_FSL_ERRATUM_ELBC_A001
428 select SYS_FSL_ERRATUM_ESDHC111
429 select FSL_PCIE_DISABLE_ASPM
430 select FSL_PCIE_RESET
431 select SYS_FSL_HAS_DDR3
432 select SYS_FSL_HAS_SEC
433 select SYS_FSL_SEC_BE
434 select SYS_FSL_SEC_COMPAT_2
435 select SYS_PPC_E500_USE_DEBUG_TLB
446 select SYS_FSL_ERRATUM_A004508
447 select SYS_FSL_ERRATUM_A005125
448 select SYS_FSL_ERRATUM_I2C_A004447
449 select FSL_PCIE_RESET
450 select SYS_FSL_HAS_DDR3
451 select SYS_FSL_HAS_SEC
452 select SYS_FSL_SEC_BE
453 select SYS_FSL_SEC_COMPAT_4
459 select SYS_FSL_ERRATUM_A004508
460 select SYS_FSL_ERRATUM_A005125
461 select SYS_FSL_ERRATUM_ELBC_A001
462 select SYS_FSL_ERRATUM_ESDHC111
463 select FSL_PCIE_DISABLE_ASPM
464 select FSL_PCIE_RESET
465 select SYS_FSL_HAS_DDR3
466 select SYS_FSL_HAS_SEC
467 select SYS_FSL_SEC_BE
468 select SYS_FSL_SEC_COMPAT_2
469 select SYS_PPC_E500_USE_DEBUG_TLB
481 select SYS_FSL_ERRATUM_A004508
482 select SYS_FSL_ERRATUM_A005125
483 select SYS_FSL_ERRATUM_ELBC_A001
484 select SYS_FSL_ERRATUM_ESDHC111
485 select FSL_PCIE_DISABLE_ASPM
486 select FSL_PCIE_RESET
487 select SYS_FSL_HAS_DDR3
488 select SYS_FSL_HAS_SEC
489 select SYS_FSL_SEC_BE
490 select SYS_FSL_SEC_COMPAT_2
491 select SYS_PPC_E500_USE_DEBUG_TLB
499 select SYS_CACHE_SHIFT_5
500 select SYS_FSL_ERRATUM_A004477
501 select SYS_FSL_ERRATUM_A004508
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ESDHC111
504 select SYS_FSL_ERRATUM_ESDHC_A001
505 select FSL_PCIE_RESET
506 select SYS_FSL_HAS_DDR3
507 select SYS_FSL_HAS_SEC
508 select SYS_FSL_SEC_BE
509 select SYS_FSL_SEC_COMPAT_2
510 select SYS_PPC_E500_USE_DEBUG_TLB
520 select SYS_CACHE_SHIFT_6
521 select SYS_FSL_ERRATUM_A004510
522 select SYS_FSL_ERRATUM_A004849
523 select SYS_FSL_ERRATUM_A005275
524 select SYS_FSL_ERRATUM_A006261
525 select SYS_FSL_ERRATUM_CPU_A003999
526 select SYS_FSL_ERRATUM_DDR_A003
527 select SYS_FSL_ERRATUM_DDR_A003474
528 select SYS_FSL_ERRATUM_ESDHC111
529 select SYS_FSL_ERRATUM_I2C_A004447
530 select SYS_FSL_ERRATUM_NMG_CPU_A011
531 select SYS_FSL_ERRATUM_SRIO_A004034
532 select SYS_FSL_ERRATUM_USB14
533 select SYS_FSL_HAS_DDR3
534 select SYS_FSL_HAS_SEC
535 select SYS_FSL_QORIQ_CHASSIS1
536 select SYS_FSL_SEC_BE
537 select SYS_FSL_SEC_COMPAT_4
545 select SYS_CACHE_SHIFT_6
546 select SYS_FSL_DDR_VER_44
547 select SYS_FSL_ERRATUM_A004510
548 select SYS_FSL_ERRATUM_A004849
549 select SYS_FSL_ERRATUM_A005275
550 select SYS_FSL_ERRATUM_A005812
551 select SYS_FSL_ERRATUM_A006261
552 select SYS_FSL_ERRATUM_CPU_A003999
553 select SYS_FSL_ERRATUM_DDR_A003
554 select SYS_FSL_ERRATUM_DDR_A003474
555 select SYS_FSL_ERRATUM_ESDHC111
556 select SYS_FSL_ERRATUM_I2C_A004447
557 select SYS_FSL_ERRATUM_NMG_CPU_A011
558 select SYS_FSL_ERRATUM_SRIO_A004034
559 select SYS_FSL_ERRATUM_USB14
560 select SYS_FSL_HAS_DDR3
561 select SYS_FSL_HAS_SEC
562 select SYS_FSL_QORIQ_CHASSIS1
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_4
575 select SYS_CACHE_SHIFT_6
576 select SYS_FSL_DDR_VER_44
577 select SYS_FSL_ERRATUM_A004510
578 select SYS_FSL_ERRATUM_A004580
579 select SYS_FSL_ERRATUM_A004849
580 select SYS_FSL_ERRATUM_A005812
581 select SYS_FSL_ERRATUM_A007075
582 select SYS_FSL_ERRATUM_CPC_A002
583 select SYS_FSL_ERRATUM_CPC_A003
584 select SYS_FSL_ERRATUM_CPU_A003999
585 select SYS_FSL_ERRATUM_DDR_A003
586 select SYS_FSL_ERRATUM_DDR_A003474
587 select SYS_FSL_ERRATUM_ELBC_A001
588 select SYS_FSL_ERRATUM_ESDHC111
589 select SYS_FSL_ERRATUM_ESDHC13
590 select SYS_FSL_ERRATUM_ESDHC135
591 select SYS_FSL_ERRATUM_I2C_A004447
592 select SYS_FSL_ERRATUM_NMG_CPU_A011
593 select SYS_FSL_ERRATUM_SRIO_A004034
594 select SYS_P4080_ERRATUM_CPU22
595 select SYS_P4080_ERRATUM_PCIE_A003
596 select SYS_P4080_ERRATUM_SERDES8
597 select SYS_P4080_ERRATUM_SERDES9
598 select SYS_P4080_ERRATUM_SERDES_A001
599 select SYS_P4080_ERRATUM_SERDES_A005
600 select SYS_FSL_HAS_DDR3
601 select SYS_FSL_HAS_SEC
602 select SYS_FSL_QORIQ_CHASSIS1
603 select SYS_FSL_SEC_BE
604 select SYS_FSL_SEC_COMPAT_4
614 select SYS_CACHE_SHIFT_6
615 select SYS_FSL_DDR_VER_44
616 select SYS_FSL_ERRATUM_A004510
617 select SYS_FSL_ERRATUM_A004699
618 select SYS_FSL_ERRATUM_A005275
619 select SYS_FSL_ERRATUM_A005812
620 select SYS_FSL_ERRATUM_A006261
621 select SYS_FSL_ERRATUM_DDR_A003
622 select SYS_FSL_ERRATUM_DDR_A003474
623 select SYS_FSL_ERRATUM_ESDHC111
624 select SYS_FSL_ERRATUM_USB14
625 select SYS_FSL_HAS_DDR3
626 select SYS_FSL_HAS_SEC
627 select SYS_FSL_QORIQ_CHASSIS1
628 select SYS_FSL_SEC_BE
629 select SYS_FSL_SEC_COMPAT_4
636 config ARCH_QEMU_E500
638 select SYS_CACHE_SHIFT_5
644 select SYS_CACHE_SHIFT_6
645 select SYS_FSL_DDR_VER_50
646 select SYS_FSL_ERRATUM_A008378
647 select SYS_FSL_ERRATUM_A008109
648 select SYS_FSL_ERRATUM_A009663
649 select SYS_FSL_ERRATUM_A009942
650 select SYS_FSL_ERRATUM_ESDHC111
651 select SYS_FSL_HAS_DDR3
652 select SYS_FSL_HAS_DDR4
653 select SYS_FSL_HAS_SEC
654 select SYS_FSL_QORIQ_CHASSIS2
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_5
667 select SYS_CACHE_SHIFT_6
668 select SYS_FSL_DDR_VER_50
669 select SYS_FSL_ERRATUM_A008044
670 select SYS_FSL_ERRATUM_A008378
671 select SYS_FSL_ERRATUM_A008109
672 select SYS_FSL_ERRATUM_A009663
673 select SYS_FSL_ERRATUM_A009942
674 select SYS_FSL_ERRATUM_ESDHC111
675 select SYS_FSL_HAS_DDR3
676 select SYS_FSL_HAS_DDR4
677 select SYS_FSL_HAS_SEC
678 select SYS_FSL_QORIQ_CHASSIS2
679 select SYS_FSL_SEC_BE
680 select SYS_FSL_SEC_COMPAT_5
690 select SYS_CACHE_SHIFT_6
691 select SYS_FSL_DDR_VER_50
692 select SYS_FSL_ERRATUM_A008044
693 select SYS_FSL_ERRATUM_A008378
694 select SYS_FSL_ERRATUM_A008109
695 select SYS_FSL_ERRATUM_A009663
696 select SYS_FSL_ERRATUM_A009942
697 select SYS_FSL_ERRATUM_ESDHC111
698 select SYS_FSL_HAS_DDR3
699 select SYS_FSL_HAS_DDR4
700 select SYS_FSL_HAS_SEC
701 select SYS_FSL_QORIQ_CHASSIS2
702 select SYS_FSL_SEC_BE
703 select SYS_FSL_SEC_COMPAT_5
714 select SYS_CACHE_SHIFT_6
715 select SYS_FSL_DDR_VER_47
716 select SYS_FSL_ERRATUM_A006379
717 select SYS_FSL_ERRATUM_A006593
718 select SYS_FSL_ERRATUM_A007186
719 select SYS_FSL_ERRATUM_A007212
720 select SYS_FSL_ERRATUM_A007815
721 select SYS_FSL_ERRATUM_A007907
722 select SYS_FSL_ERRATUM_A008109
723 select SYS_FSL_ERRATUM_A009942
724 select SYS_FSL_ERRATUM_ESDHC111
725 select FSL_PCIE_RESET
726 select SYS_FSL_HAS_DDR3
727 select SYS_FSL_HAS_SEC
728 select SYS_FSL_QORIQ_CHASSIS2
729 select SYS_FSL_SEC_BE
730 select SYS_FSL_SEC_COMPAT_4
744 select SYS_CACHE_SHIFT_6
745 select SYS_FSL_DDR_VER_47
746 select SYS_FSL_ERRATUM_A004468
747 select SYS_FSL_ERRATUM_A005871
748 select SYS_FSL_ERRATUM_A006261
749 select SYS_FSL_ERRATUM_A006379
750 select SYS_FSL_ERRATUM_A006593
751 select SYS_FSL_ERRATUM_A007186
752 select SYS_FSL_ERRATUM_A007798
753 select SYS_FSL_ERRATUM_A007815
754 select SYS_FSL_ERRATUM_A007907
755 select SYS_FSL_ERRATUM_A008109
756 select SYS_FSL_ERRATUM_A009942
757 select SYS_FSL_HAS_DDR3
758 select SYS_FSL_HAS_SEC
759 select SYS_FSL_QORIQ_CHASSIS2
760 select SYS_FSL_SEC_BE
761 select SYS_FSL_SEC_COMPAT_4
769 config MPC85XX_HAVE_RESET_VECTOR
770 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
781 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
787 Enble PowerPC E500MC core
792 Enable PowerPC E6500 core
797 Use Freescale common code for Local Access Window
802 Enable Freescale Secure Boot feature. Normally selected
803 by defconfig. If unsure, do not change.
806 int "Maximum number of CPUs permitted for MPC85xx"
807 default 12 if ARCH_T4240
808 default 8 if ARCH_P4080
809 default 4 if ARCH_B4860 || \
816 default 2 if ARCH_B4420 || \
827 Set this number to the maximum number of possible CPUs in the SoC.
828 SoCs may have multiple clusters with each cluster may have multiple
829 ports. If some ports are reserved but higher ports are used for
830 cores, count the reserved ports. This will allocate enough memory
831 in spin table to properly handle all cores.
833 config SYS_CCSRBAR_DEFAULT
834 hex "Default CCSRBAR address"
835 default 0xff700000 if ARCH_BSC9131 || \
850 default 0xff600000 if ARCH_P1023
851 default 0xfe000000 if ARCH_B4420 || \
862 default 0xe0000000 if ARCH_QEMU_E500
864 Default value of CCSRBAR comes from power-on-reset. It
865 is fixed on each SoC. Some SoCs can have different value
866 if changed by pre-boot regime. The value here must match
867 the current value in SoC. If not sure, do not change.
869 config SYS_FSL_ERRATUM_A004468
872 config SYS_FSL_ERRATUM_A004477
875 config SYS_FSL_ERRATUM_A004508
878 config SYS_FSL_ERRATUM_A004580
881 config SYS_FSL_ERRATUM_A004699
884 config SYS_FSL_ERRATUM_A004849
887 config SYS_FSL_ERRATUM_A004510
890 config SYS_FSL_ERRATUM_A004510_SVR_REV
892 depends on SYS_FSL_ERRATUM_A004510
893 default 0x20 if ARCH_P4080
896 config SYS_FSL_ERRATUM_A004510_SVR_REV2
898 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
901 config SYS_FSL_ERRATUM_A005125
904 config SYS_FSL_ERRATUM_A005434
907 config SYS_FSL_ERRATUM_A005812
910 config SYS_FSL_ERRATUM_A005871
913 config SYS_FSL_ERRATUM_A005275
916 config SYS_FSL_ERRATUM_A006261
919 config SYS_FSL_ERRATUM_A006379
922 config SYS_FSL_ERRATUM_A006384
925 config SYS_FSL_ERRATUM_A006475
928 config SYS_FSL_ERRATUM_A006593
931 config SYS_FSL_ERRATUM_A007075
934 config SYS_FSL_ERRATUM_A007186
937 config SYS_FSL_ERRATUM_A007212
940 config SYS_FSL_ERRATUM_A007815
943 config SYS_FSL_ERRATUM_A007798
946 config SYS_FSL_ERRATUM_A007907
949 config SYS_FSL_ERRATUM_A008044
952 config SYS_FSL_ERRATUM_CPC_A002
955 config SYS_FSL_ERRATUM_CPC_A003
958 config SYS_FSL_ERRATUM_CPU_A003999
961 config SYS_FSL_ERRATUM_ELBC_A001
964 config SYS_FSL_ERRATUM_I2C_A004447
967 config SYS_FSL_A004447_SVR_REV
969 depends on SYS_FSL_ERRATUM_I2C_A004447
970 default 0x00 if ARCH_MPC8548
971 default 0x10 if ARCH_P1010
972 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
973 default 0x20 if ARCH_P3041 || ARCH_P4080
975 config SYS_FSL_ERRATUM_IFC_A002769
978 config SYS_FSL_ERRATUM_IFC_A003399
981 config SYS_FSL_ERRATUM_NMG_CPU_A011
984 config SYS_FSL_ERRATUM_NMG_ETSEC129
987 config SYS_FSL_ERRATUM_NMG_LBC103
990 config SYS_FSL_ERRATUM_P1010_A003549
993 config SYS_FSL_ERRATUM_SATA_A001
996 config SYS_FSL_ERRATUM_SEC_A003571
999 config SYS_FSL_ERRATUM_SRIO_A004034
1002 config SYS_FSL_ERRATUM_USB14
1005 config SYS_HAS_SERDES
1008 config SYS_P4080_ERRATUM_CPU22
1011 config SYS_P4080_ERRATUM_PCIE_A003
1014 config SYS_P4080_ERRATUM_SERDES8
1017 config SYS_P4080_ERRATUM_SERDES9
1020 config SYS_P4080_ERRATUM_SERDES_A001
1023 config SYS_P4080_ERRATUM_SERDES_A005
1026 config FSL_PCIE_DISABLE_ASPM
1029 config FSL_PCIE_RESET
1032 config SYS_FSL_QORIQ_CHASSIS1
1035 config SYS_FSL_QORIQ_CHASSIS2
1038 config SYS_FSL_NUM_LAWS
1039 int "Number of local access windows"
1041 default 32 if ARCH_B4420 || \
1049 default 16 if ARCH_T1024 || \
1052 default 12 if ARCH_BSC9131 || \
1064 default 10 if ARCH_MPC8544 || \
1066 default 8 if ARCH_MPC8540 || \
1069 Number of local access windows. This is fixed per SoC.
1070 If not sure, do not change.
1072 config SYS_FSL_THREADS_PER_CORE
1077 config SYS_NUM_TLBCAMS
1078 int "Number of TLB CAM entries"
1079 default 64 if E500MC
1082 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1083 16 for other E500 SoCs.
1088 config SYS_PPC_E500_USE_DEBUG_TLB
1094 config SYS_PPC_E500_DEBUG_TLB
1095 int "Temporary TLB entry for external debugger"
1096 depends on SYS_PPC_E500_USE_DEBUG_TLB
1097 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1098 default 1 if ARCH_MPC8536
1099 default 2 if ARCH_P1011 || \
1105 default 3 if ARCH_P1010 || \
1109 Select a temporary TLB entry to be used during boot to work
1110 around limitations in e500v1 and e500v2 external debugger
1111 support. This reduces the portions of the boot code where
1112 breakpoints and single stepping do not work. The value of this
1113 symbol should be set to the TLB1 entry to be used for this
1114 purpose. If unsure, do not change.
1116 config SYS_FSL_IFC_CLK_DIV
1117 int "Divider of platform clock"
1119 default 2 if ARCH_B4420 || \
1127 Defines divider of platform clock(clock input to
1130 config SYS_FSL_LBC_CLK_DIV
1131 int "Divider of platform clock"
1132 depends on FSL_ELBC || ARCH_MPC8540 || \
1136 default 2 if ARCH_P2041 || \
1143 Defines divider of platform clock(clock input to
1149 source "board/emulation/qemu-ppce500/Kconfig"
1150 source "board/freescale/corenet_ds/Kconfig"
1151 source "board/freescale/mpc8548cds/Kconfig"
1152 source "board/freescale/p1010rdb/Kconfig"
1153 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1154 source "board/freescale/p2041rdb/Kconfig"
1155 source "board/freescale/t102xrdb/Kconfig"
1156 source "board/freescale/t104xrdb/Kconfig"
1157 source "board/freescale/t208xqds/Kconfig"
1158 source "board/freescale/t208xrdb/Kconfig"
1159 source "board/freescale/t4rdb/Kconfig"
1160 source "board/keymile/Kconfig"
1161 source "board/socrates/Kconfig"