#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
-
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_CMD_PCI
-
/*
* PCI Windows
* Memory space is mapped 1-1, but I/O space must start from 0.
#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
#endif
-
/* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
#define CONFIG_CMD_PCI
-
/*
* PCI Windows
* Memory space is mapped 1-1, but I/O space must start from 0.
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
-
/*
* Command line configuration.
*/
*/
#undef CONFIG_SYS_LONGHELP /* undef to save memory */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
-
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text)
-
/*
* BOOTP options
*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
-
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_MII 1
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
/***********************************************************
* Note that it may also be a MIP405T board which is a subset of the
* MIP405
***********************************************************/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#if !defined(CONFIG_MIP405T)
#endif
-
/**************************************************************
* I2C Stuff:
* the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
/* last 6 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in On Chip SRAM)
*/
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
#endif
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* 8 bit port */ \
#define TSEC2_PHYIDX 0
#endif
-
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC1"
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
HID0_ENABLE_M_BIT |\
HID0_ENABLE_ADDRESS_BROADCAST) */
-
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
-
/*
* Environment Configuration
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map -- xxx -this is wrong, needs updating
*
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
/*
* 32KB, 8-bit wide for ADS config reg
*/
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
-
#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#endif /* CONFIG_TSEC_ENET */
-
/*
* Environment
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
-
/*
* Environment Configuration
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
-
/*
* SDRAM on the Local Bus
*/
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
*
*/
-
/*
* Local Bus Definitions
*/
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
#define CONFIG_FSL_VIA
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
-
/*
* SDRAM on the Local Bus
*/
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
/*
* 32KB, 8-bit wide for ADS config reg
*/
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_TSEC_ENET
#ifndef CONFIG_MII
#endif
-
/*
* Environment
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
-
/*
* Environment Configuration
*/
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
-
/*
* SDRAM on the LocalBus
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
/*Chip select 2 - SDRAM*/
#define CONFIG_SYS_BR2_PRELIM 0xf0001861
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
"ramargs=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs\0" \
-
#define CONFIG_NFSBOOTCOMMAND \
"run nfsargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-
#define CONFIG_RAMBOOTCOMMAND \
"run ramargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_MMC 1
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
-
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
/* video */
#define CONFIG_FSL_DIU_FB
#endif
-
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
#define CONFIG_SYS_FLASH_BASE2 0xf8000000
#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
-
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
-
#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
-
/*
* Environment
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_EXT2
#endif
-
#define CONFIG_WATCHDOG /* watchdog enabled */
#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
-
/*
* These are used when DDR doesn't use SPD.
*/
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#endif /* CONFIG_TSEC_ENET */
-
#ifdef CONFIG_PHYS_64BIT
#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_EXT2
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
"maxcpus=2"
-
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
#define CONFIG_CMD_PCI
-
/*
* PCI Windows
* Memory space is mapped 1-1, but I/O space must start from 0.
#endif /* CONFIG_TSEC_ENET */
-
/* SATA */
#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
-
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
-
/*
* Memory map
*
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
/* Serial Console Configuration */
#define CONFIG_5xx_CONS_SCI1
#undef CONFIG_5xx_CONS_SCI2
#define CONFIG_BAUDRATE 9600
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IRQ
-
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
/*-----------------------------------------------------------------------
* FLASH organization
*-----------------------------------------------------------------------
#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
#endif
-
#define CONFIG_SPI 1
#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
*/
#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
-
#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
/*-----------------------------------------------------------------------
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
/***********************************************************
* Clock
***********************************************************/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
/* last 6 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
/***************************************************************
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
**************************************************************/
#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
-
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
-
#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
#define CONFIG_PORT_ADDR 0xF4000000
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in On Chip SRAM)
*/
#define CONFIG_ISO_STRING "MEV-10066-001"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
-
#endif /* __CONFIG_H */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#define CONFIG_BAUDRATE 115200
#define __USB_PHY_TYPE utmi
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
"setenv loadaddr 0x1000000;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
#define I2C_MUX_PCA_ADDR 0x77
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-
/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH_DIU 0xC
#endif
#endif
-
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
#endif
-
/*
* Dynamic MTD Partition support with mtdparts
*/
#define FM1_10GEC4_PHY_ADDR 0x01
#endif
-
#ifdef CONFIG_FMAN_ENET
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC3"
#define CONFIG_SYS_RAMBOOT
#endif
-
/* I2C */
#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
-
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define FM2_10GEC2_PHY_ADDR 0x3
#endif
-
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LIBATA
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
-
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_HVBOOT \
#define CONFIG_SYS_RAMBOOT
#endif
-
/* I2C */
#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
-
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
#endif
-
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LIBATA
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif /* #ifndef CONFIG_TQM5200S */
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_DIAG
#endif
-
#define CONFIG_TIMESTAMP /* display image timestamps */
#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_BMP
#endif
-
#define CONFIG_NETCONSOLE
/*
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
-
#define CONFIG_NETCONSOLE
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
/*
* Command line configuration.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_TIMESTAMP /* but print image timestmps */
-
/*
* Command line configuration.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-
#define MACH_TYPE_MPL_VCMA9 227
/*
#define CONFIG_SYS_TEXT_BASE 0x0
-
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (VCMA9 has 12MHz input clock) */
/* RTC */
#define CONFIG_RTC_S3C24X0
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
* +- 31 0 PSC1
*/
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
/*
* Various low-level settings
*/
CLOCK_SCCR2_DIU_EN | \
CLOCK_SCCR2_I2C_EN)
-
#define CONFIG_CMDLINE_EDITING 1 /* command line history */
/* I2C */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#ifndef __AMCC_COMMON_H
#define __AMCC_COMMON_H
-
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_PREBOOT "run check_flash check_env;"
-
/*
* Boot Linux
*/
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
/* Environment */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_USB_STORAGE
#endif
-
/* RTC */
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_PCF8563
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMDLINE_EDITING
-
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_CMD_BOOTZ
-
/*
* Memory Configuration
*/
#undef CONFIG_FB_ADDR
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-
/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED AT91_PIN_PD14 /* this is the power led */
* NB: in this case, USB 1.1 devices won't be recognized.
*/
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
-
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_CMD_MMC
#define CONFIG_CMD_MII
-
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
-
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
"run mmcboot;" \
"run nandboot;"
-
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf536-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
#define CONFIG_SCLK_DIV 3
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
-
/*
* SDRAM Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_ROOTPATH "/romfs/brettl2"
#endif
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 135
-
/*
* Env Storage Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf506-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (4 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024)
-
/*
* Flash Settings
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x400
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf518-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#endif
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SDH Settings
*/
#define CONFIG_BFIN_SDH
#endif
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf526-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
/*
* NAND Settings
* (can't be used same time as ethernet)
#define CONFIG_CMD_NAND
#endif
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#endif
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* USB Settings
*/
#define CONFIG_USB_MUSB_TIMEOUT 100000
#endif
-
/*
* Misc Settings
*/
/* #define STATUS_LED_BIT2 GPIO_PG12 */
#endif
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
/*
* NAND Settings
* (can't be used same time as ethernet)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SPI_MMC Settings
*/
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
/*
* NAND Settings
* (can't be used same time as ethernet)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* USB Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
#define CONFIG_PLL_CTL_VAL 0x2a00
#define CONFIG_VR_CTL_VAL 0x7090
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
-
/*
* SPI Settings
*/
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH_ALL
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
} while (0)
#define CONFIG_HOSTNAME bf533-ezkit
-
/*
* Flash Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x10000
#define FLASH_TOT_SECT 40
-
/*
* I2C Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
} while (0)
#define CONFIG_HOSTNAME bf533-stamp
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
#endif
-
/*
* Misc Settings
*/
/* define to enable splash screen support */
/* #define CONFIG_VIDEO */
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (128 << 10)
-
/*
* Network Settings
*/
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH "/romfs"
-
/*
* Flash Settings
*/
/* We don't have a parallel flash chip there */
#define CONFIG_SYS_NO_FLASH
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C settings
*/
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* NAND Settings
*/
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
-
/*
* I2C settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (384 << 10)
-
/*
* Network Settings
*/
/* We don't have a parallel flash chip there */
#define CONFIG_SYS_NO_FLASH
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C settings
*/
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CONFIG_SYS_MAX_FLASH_SECT 71
-
/*
* SPI Settings
*/
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH_ALL
-
/*
* Env Storage Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SPI_MMC Settings
*/
#endif
-
/*
* Misc Settings
*/
#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
#endif
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf538-0.4
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SMC91111_BASE 0x20310300
#define CONFIG_HOSTNAME bf538f-ezkit
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
-
/*
* SPI Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf548-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME bf548-ezkit
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SATA
*/
#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
#endif
-
/*
* SDH Settings
*/
#define CONFIG_BFIN_SDH
#endif
-
/*
* USB Settings
*/
#define CONFIG_USB_MUSB_TIMEOUT 100000
#endif
-
/*
* Misc Settings
*/
#define CONFIG_SYS_POST_FLASH_END 127
#endif
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* RTC Settings
*/
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3*/
-
/*
* Network Settings
*/
#define CONFIG_HOSTNAME bf561-acvilon
-
/*
* Flash Settings
*/
#define CONFIG_SYS_NO_FLASH
-
/*
* I2C Settings
*/
#define CONFIG_PCA9564_I2C
#define CONFIG_PCA9564_BASE 0x2c000000
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_SF_DEFAULT_SPEED 10000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
#define CONFIG_ENV_SIZE (8 * 1056)
-
/*
* NAND Settings
* We're using NAND_PLAT driver to make things simplier
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 6
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SMC_USE_32_BIT 1
#define CONFIG_HOSTNAME bf561-ezkit
-
/*
* Flash Settings
*/
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE 0x2000
-
/*
* I2C Settings
*/
*/
/* #define CONFIG_CORE1_RUN 1 */
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_BFIN_CPU bf609-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/* For ez-board version 1.0, else undef this */
#define CONFIG_BFIN_BOARD_VERSION_1_0
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
*/
#define CONFIG_SYS_NO_FLASH /* We have no parallel FLASH */
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* NAND Settings
*/
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
-
/* additional features on charon board */
#define CONFIG_RESET_PHY_R
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* NAND Settings
* (can't be used sametime as ethernet)
#define CONFIG_CMD_NAND
#endif
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SMC91111_BASE 0x20200300
#define CONFIG_HOSTNAME cm-bf533
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 16
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x10000
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 35
-
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
-
/*
* Env Storage Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SPI_MMC Settings
*/
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 35
-
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
-
/*
* Env Storage Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SPI_MMC Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf548-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf548
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
#endif
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf561
-
/*
* Flash Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* Misc Settings
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-
#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
-
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#undef CONFIG_SYS_LOWBOOT
#endif
-
/*
* Chip selects configuration
*/
"nboot ${loadaddr} nand0 900000; " \
"bootm ${loadaddr}\0"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=82000000\0" \
"console=ttyO0,115200n8\0" \
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
"run emmcboot; " \
"fi;"
-
#define CONFIG_CONS_INDEX 1
/* SPL defines. */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
to -1 disables delay, setting to 0 will too prevent access to u-boot command
interface: u-boot then has to reflashed */
-
/* The following settings will be contained in the environment block ; if you
want to use a neutral environment all those settings can be manually set in
u-boot: 'set' command */
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP /* support multiple processors */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
/*
* Memory map
*
*/
#define CONFIG_HARD_SPI
-
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#endif
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-
#ifndef CONFIG_TRAILBLAZER
/*
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
-
#define CONFIG_MMC
#define CONFIG_SDCARD
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
#endif
-
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
-
#define CONFIG_SYS_MMC_MAX_DEVICE 1
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_OR0_PRELIM 0xfff00010
#define CONFIG_SYS_OR1_PRELIM 0xfff00010
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_USE_SPIFLASH
#endif
-
/*
* SoC Configuration
*/
#define CONFIG_BOOTCOMMAND "bootp;bootm"
#endif /* CONFIG_DBAU1550 */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#endif
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_NR_DRAM_BANKS 2
-
#ifdef CONFIG_DBAU1550
#define MEM_SIZE 192
#else
"fi; " \
"else run nandboot; fi\0"
-
#define CONFIG_BOOTCOMMAND "run autoboot"
/* Boot Argument Buffer Size */
#ifndef _CONFIG_DOCKSTAR_H
#define _CONFIG_DOCKSTAR_H
-
/*
* Version number information
*/
#define CONFIG_ENV_SIZE_REDUND 0x2000
#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
-
#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V2
#ifndef CONFIG_SPL_BUILD
"run nand_boot_backup;" \
"reset;"
-
#else
#define CONFIG_BOOTDELAY 0
"tftp $loadaddr "#file" && " \
"mmc write $loadaddr $start $size && "
-
#define CONFIG_ENV_REFLASH \
"mmc dev 0 && "\
"usb start && "\
#define CONFIG_SYS_ENABLE_PADS_ALL
-
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#define CONFIG_VIDEO
#define CONFIG_PREBOOT
-
/*
* SoC Configuration
*/
#define CONFIG_SYS_NO_FLASH
#endif
-
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_CFB_CONSOLE
"mtdparts="MTDPARTS_DEFAULT"\0" \
"serverip=192.168.142.60\0"
-
#endif /* __CONFIG_H */
#error "no board defined"
#endif
-
/* Initial environment and monitor configuration options. */
#define CONFIG_BOOTDELAY 2
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
#define CONFIG_BOOTFILE "edb93xx.img"
-
-
#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
#ifdef CONFIG_EDB9301
#error "no SDCS configuration for this board"
#endif
-
#if defined(CONFIG_EDB93XX_SDCS3)
#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
-
/* Must match kernel config */
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#include <asm/hardware.h>
-
/* The first stage boot loader expects u-boot running at this address. */
#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
-
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Enable Time Command */
-
/* USB */
#define CONFIG_USB_STORAGE
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
/*
* Ethernet on SOC (FEC)
*/
#ifndef _CONFIG_GOFLEXHOME_H
#define _CONFIG_GOFLEXHOME_H
-
/*
* Version number information
*/
#undef CONFIG_SYS_SRAM_BASE
#undef CONFIG_SYS_SRAM_SIZE
-
/* Always Run U-Boot from SDRAM */
#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#ifndef _CONFIG_GURUPLUG_H
#define _CONFIG_GURUPLUG_H
-
/*
* Version number information
*/
#define CONFIG_USB_DEV_PULLUP_GPIO 33
/* USB VBUS GPIO 3 */
-
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTCOMMAND \
"setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_SYS_64BIT_LBA
-
/*-----------------------------------------------------------------------
* Physical Memory Map
* The DRAM is already setup, so do not touch the DT node later.
"initrd_high=0xffffffffffffffff\0" \
BOOTENV
-
/* Preserve enviroment on sd card */
#define CONFIG_COMMAND_HISTORY
#define CONFIG_IDENT_STRING " hrcon 0.01"
#endif
-
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
-
#endif /* __CONFIG_H */
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define AX88180_BASE 0x2c000000
#define CONFIG_HOSTNAME ibf-dsp561
-
/*
* Flash Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
*/
#define CONFIG_UART_CONSOLE 0
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#ifndef _CONFIG_ICONNECT_H
#define _CONFIG_ICONNECT_H
-
/*
* Version number information
*/
#define CONFIG_MPC8313
#define CONFIG_IDS8313
-
#define CONFIG_FSL_ELBC
#define CONFIG_MISC_INIT_R
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
#define CONFIG_NETDEV eth1
#define CONFIG_HOSTNAME ids8313
#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
"sync:1241513985,vmode:0\0"
-
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0xa8000000
#define CONFIG_SMC911X_32_BIT
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
*/
/* #define SKIP_CONFIG_RELOCATE_UBOOT */
-
/*
* Physical Memory Map
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
/*-----------------------------------------------------------------------
* There are various dependencies on the core module (CM) fitted
* Users should refer to their CM user guide
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
/*
* External Bus Controller (EBC) Setup
*/
* 0xfc00.0000 -> 4.cc00.0000
*/
-
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x10055e00
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf532-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 3
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
-
/*
* Flash Settings
*/
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_NO_FLASH /* we have only NAND */
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
-
/*
* NAND Settings
*/
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
-
/*
* Misc Settings
*/
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_BOOTCOMMAND "run nandboot"
-
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
-
#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
(13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
DAVINCI_ABCR_TA(0) | \
DAVINCI_ABCR_ASIZE_8BIT)
-
/*
* Serial Driver info
*/
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CODFIG_CMD_PCI
#endif
-
/*
* Autobooting
*/
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_I2C_MULTI_BUS
-
/*
* Flash
*/
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
#ifdef CONFIG_KMCOGE5NE
/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (\
#undef CONFIG_KIRKWOOD_PCIE_INIT
#endif
-
#endif /* _CONFIG_KM_KIRKWOOD */
#define CONFIG_SYS_TEXT_BASE 0xc1080000
-
/*
* Memory Info
*/
#define CONFIG_CLOCKS
#endif
-
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
-
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H
-
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH3
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
-
#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
#endif /* __LS2_COMMON_H */
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
#ifndef _CONFIG_LSXL_H
#define _CONFIG_LSXL_H
-
/*
* Version number information
*/
#undef CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-
/*
* Environment variables configurations
*/
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
-
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_HOSTNAME lwmon5
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_VIDEO
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define CONFIG_CMD_SATA
#define CONFIG_VIDEO
-
/*
* Memory configurations
*/
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_BOARD_LATE_INIT
-
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
CLOCK_SCCR2_I2C_EN)
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* I2C */
* Command line configuration.
*/
-
#ifdef CONFIG_SYS_USE_NANDFLASH
#define CONFIG_CMD_NAND
#endif
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
-
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
"1m(u-boot);" \
"mpc5121.nand:-(data)"
-
#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
/* FLASH */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#ifndef _CONFIG_MARVELL_PLUG_H
#define _CONFIG_MARVELL_PLUG_H
-
/*
* High Level Configuration Options (easy to change)
*/
/* High Level Configuration Options */
#define CONFIG_MX31 1 /* This is a mx31 */
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* High Level Configuration Options */
#define CONFIG_MX31 /* This is a mx31 */
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-
/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP 0x074B0BF5
#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
-
/*
* PMIC Configs
*/
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
-
#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
#define MX53ARD_CS1RCR2 RBEN(2)
"echo WARNING: Could not determine dtb to use; fi; " \
"fi;\0" \
-
#define CONFIG_BOOTCOMMAND \
"run findfdt;" \
"mmc dev ${mmcdev};" \
* SPDX-License-Identifier: GPL-2.0+
*/
-
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_IMX_THERMAL
-
#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_FSL_QSPI_AHB
* SPDX-License-Identifier: GPL-2.0+
*/
-
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_IMX_THERMAL
-
-
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_FSL_QSPI_LE
#define CONFIG_SYS_FSL_QSPI_AHB
#ifndef __MX6UL_14X14_EVK_CONFIG_H
#define __MX6UL_14X14_EVK_CONFIG_H
-
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
#ifndef __CONFIG_H
#define __CONFIG_H
-
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
#define CONFIG_NEO 1 /* on a Neo board */
#define CONFIG_PCIE_IMX
#endif
-
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND
-
/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
#include <config_distro_bootcmd.h>
-
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_DEVICE_SETTINGS \
MEM_LAYOUT_SETTINGS \
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-
/* SMSC922x Ethernet */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#endif
-
#undef CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_UBOOT_ENABLE_PADS_ALL
-
#include <configs/ti_omap4_common.h>
/* GPIO */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
#endif /* __CONFIG_H */
#define CONFIG_LIBATA
#endif
-
/* SPL */
#ifdef CONFIG_SPL
#include "imx6_spl.h"
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xef000000
#endif
-
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#else
#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
-
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
#define CONFIG_NR_DRAM_BANKS 2
-
#define CONFIG_MEMSIZE_IN_BYTES
-
/*---USB -------------------------------------------*/
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
/* even with bootdelay=0 */
#undef CONFIG_BOOTARGS
-
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
"mount root filesystem over NFS;" \
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
-
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define CONFIG_SYS_NAND_ECCSTEPS 8
/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-
-
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_ASKENV /* monitor functions : ask for env variable */
#include <asm/hardware.h>
/* ARM asynchronous clock */
-
#define CONFIG_DISPLAY_BOARDINFO
#define MASTER_PLL_DIV 15
*/
#include <asm/hardware.h>
-
/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
*/
#include <asm/hardware.h>
-
#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
#ifndef _CONFIG_POGO_E02_H
#define _CONFIG_POGO_E02_H
-
/*
* Machine type definition and ID
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_HOSTNAME pr1
#define CONFIG_TFTP_BLOCKSIZE 4404
-
/*
* Flash Settings
*/
#define CONFIG_SYS_NO_FLASH /* We have no parallel FLASH */
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* NAND Settings
*/
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
#undef CONFIG_SPL_NET_SUPPORT
#define CONFIG_FACTORYSET
-
/* Watchdog */
#define CONFIG_OMAP_WATCHDOG
#define CONFIG_SYS_IDE_MAXDEVICE 4
-
/*
* Miscellaneous configurable options
*/
# define CONFIG_SMC911X_BASE (0x84000000)
#endif
-
/* I2C */
#define CONFIG_SH_SH7734_I2C 1
#define CONFIG_HARD_I2C 1
#define CONFIG_ENV_SIZE_REDUND 0x2000
#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
-
-
#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V3
#ifndef CONFIG_SPL_BUILD
"run nand_boot_backup;" \
"reset;"
-
#else
#define CONFIG_BOOTDELAY 0
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_SPEED 20000000
-
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
-
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#define CONFIG_FACTORYSET
-
/* Watchdog */
#define WATCHDOG_TRIGGER_GPIO 14
#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7
#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_MD5SUM
-
#define CONFIG_CMD_GPT
#define CONFIG_PARTITION_UUIDS
#define CONFIG_AMIGA_PARTITION
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
HID0_ENABLE_M_BIT |\
HID0_ENABLE_ADDRESS_BROADCAST) */
-
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#ifndef __CONFIG_H
#define __CONFIG_H
-
/*
* Top level Makefile configuration choices
*/
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
#ifndef __CONFIG_H
#define __CONFIG_H
-
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
#define BANK_INTERLEAVING 0x22000000
#define SUPER_BANK_INTERLEAVING 0x23000000
-
#define CONFIG_ALTIVEC 1
/*
#define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
#define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
-
#endif
/* #define CONFIG_ID_EEPROM 1
"stdout=serial\0" \
"stderr=serial\0"
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-
#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(SH7785LCR_SDRAM_SIZE) - \
#ifndef _CONFIG_SHEEVAPLUG_H
#define _CONFIG_SHEEVAPLUG_H
-
/*
* Version number information
*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
-
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#ifndef CONFIG_SPL_BUILD
#define CONFIG_ROOTPATH "/opt/eldk"
"512k(mtdoops)," \
"-(rootfs)"
-
#define DFU_ALT_INFO_NAND_V2 \
"spl part 0 1;" \
"spl.backup1 part 0 2;" \
"512k(mtdoops)," \
"-(configuration)"
-
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif
-
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SYS_TEXT_BASE 0x0
-
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
************************************************************/
#define CONFIG_RTC_S3C24X0
-
#define CONFIG_BAUDRATE 115200
/*
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-
/* MMC SPL */
#define CONFIG_SKIP_LOWLEVEL_INIT
#define COPY_BL2_FNPTR_ADDR 0x00002488
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_I2C_MULTI_BUS
-
/*
* Flash
*/
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
-
/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
/*
* I2C
*/
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
-
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TIMESTAMP /* Print image info with ts */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#endif
-
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
* Common configurations used for both spear3xx as well as spear6xx
*/
-
/* U-Boot Load Address */
#define CONFIG_SYS_TEXT_BASE 0x00700000
"console=ttyAMA0,115200 $(othbootargs);" \
CONFIG_BOOTCOMMAND
-
#define CONFIG_ENV_SIZE 0x02000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
-
#endif /* __CONFIG_H */
#define CONFIG_SUNXI_USB_PHYS 2
#endif
-
#ifndef CONFIG_MACH_SUN8I_A83T
#define CONFIG_ARMV7_PSCI 1
#if defined(CONFIG_MACH_SUN8I_A23)
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
/*
* External Bus Controller (EBC) Setup
*/
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
-
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
-
#define CONFIG_BAUDRATE 115200
#define CONFIG_HVBOOT \
"fi;" \
"else echo U-Boot not downloaded..exiting;fi\0" \
-
/*
* this is common code for all TAM3517 boards.
* MAC address is stored from manufacturer in
#include <asm/hardware.h>
#include <linux/sizes.h>
-
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_ICACHE_OFF
* hex number here!
*/
-
#define CONFIG_SYS_TEXT_BASE 0x21000000
/* ARM asynchronous clock */
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-
#define CONFIG_SPL_ATMEL_SIZE
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf518-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 19
-
/*
* SPI Settings
*/
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-
/*
* Env Storage Settings
*/
#define CONFIG_ENV_SECT_SIZE 0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* Misc Settings
*/
#include <asm/config-pre.h>
-
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
-
/*
* Memory Settings
*/
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
/*
* Network Settings
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
-
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
-
/*
* Env Storage Settings
*/
common/env_embedded.o (.text*);
#endif
-
/*
* I2C Settings
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
-
/*
* SPI_MMC Settings
*/
*/
#include <configs/bfin_adi_common.h>
-
#endif
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
#define CONFIG_ENV_SIZE_REDUND 0x2000
#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
-
#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V2
#ifndef CONFIG_SPL_BUILD
"run nand_boot_backup;" \
"reset;"
-
#else
#define CONFIG_BOOTDELAY 0
#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_IDENT_STRING \
" for Cavium Thunder CN88XX ARM v8 Multi-Core"
#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
/* SMP Spin Table Definitions */
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
-
#define CONFIG_SYS_MEMTEST_START MEM_BASE
#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
#define CONFIG_TI816X_USE_EMIF0 1
#define CONFIG_TI816X_USE_EMIF1 1
-
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(64 << 20))
-
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SYS_NAND_BASE 0x30000000
DFUARGS \
NETARGS \
-
#define CONFIG_BOOTCOMMAND \
"if test ${dofastboot} -eq 1; then " \
"echo Boot fastboot requested, resetting dofastboot ...;" \
""
#endif
-
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x40300000 and 0x4031E000 as a download area for OMAP5
"sf read ${${fdt_addr}} ${offset} ${size}; " \
"setenv size ; setenv offset\0" \
-
#define CONFIG_BOOTCOMMAND \
"sf probe; run mmcboot; run netboot; run panicboot" \
#define CONFIG_SYS_RTC_DS1337_NOOSC
#define CONFIG_CMD_DATE
-
/* LED */
#define CONFIG_CMD_LED
#define CONFIG_STATUS_LED
#define CONFIG_TRATS
-
#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_L2CACHE_OFF
/* I2C */
#include <asm/arch/gpio.h>
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
/* I2C */
#include <asm/arch/gpio.h>
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_DATE
#define CONFIG_CMD_FAT
-
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_IS_IN_FLASH 1
-
#endif /* __VEXPRESS_AEMV8A_H */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x4000000
-
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
#endif
-
/* MMC */
#define CONFIG_CMD_MMC
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_RNDIS
-
#ifdef CONFIG_SYS_USE_SERIALFLASH
/* bootstrap + u-boot + env + linux in serial flash */
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define CONFIG_RTC_MC13XXX
-
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
/*
* Ethernet on SOC (FEC)
*/
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_BOOTDELAY 3
-
/*
* U-Boot Environment placing definitions.
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/* Default environment */
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_HOSTNAME x86
#ifndef __CONFIG_XLX_H
#define __CONFIG_XLX_H
-
/*
#define DEBUG
#define ET_DEBUG
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
/*
* Networking options
*/
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
*/
#define CONFIG_CMD_FAT
-
/*
* USB
*/
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
-
#endif /* __CONFIG_ZYNQ_COMMON_H */
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