b270d9d655415f594c626259c70e76ef210e7978
[platform/kernel/u-boot.git] / include / configs / tam3517-common.h
1 /*
2  * Copyright (C) 2011
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * Copyright (C) 2009 TechNexion Ltd.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_OMAP             /* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
23
24 #define CONFIG_SYS_TEXT_BASE 0x80008000
25
26 #define CONFIG_SYS_CACHELINE_SIZE       64
27
28 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
29
30 #include <asm/arch/cpu.h>               /* get chip and board defs */
31 #include <asm/arch/omap.h>
32
33 /*
34  * Display CPU and Board information
35  */
36 #define CONFIG_DISPLAY_CPUINFO
37 #define CONFIG_DISPLAY_BOARDINFO
38
39 /* Clock Defines */
40 #define V_OSCK                  26000000        /* Clock output from T2 */
41 #define V_SCLK                  (V_OSCK >> 1)
42
43 #define CONFIG_MISC_INIT_R
44
45 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
46 #define CONFIG_SETUP_MEMORY_TAGS
47 #define CONFIG_INITRD_TAG
48 #define CONFIG_REVISION_TAG
49
50 /*
51  * Size of malloc() pool
52  */
53 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
54 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10) + \
55                                         2 * 1024 * 1024)
56 /*
57  * DDR related
58  */
59 #define CONFIG_OMAP3_MICRON_DDR         /* Micron DDR */
60 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
61
62 /*
63  * Hardware drivers
64  */
65
66 /*
67  * NS16550 Configuration
68  */
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
71 #define CONFIG_SYS_NS16550_CLK          48000000        /* 48MHz (APLL96/2) */
72
73 /*
74  * select serial console configuration
75  */
76 #define CONFIG_CONS_INDEX               1
77 #define CONFIG_SYS_NS16550_COM1         OMAP34XX_UART1
78 #define CONFIG_SERIAL1                  /* UART1 */
79
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE                 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
84                                         115200}
85 #define CONFIG_MMC
86 #define CONFIG_OMAP_HSMMC
87 #define CONFIG_GENERIC_MMC
88 #define CONFIG_DOS_PARTITION
89
90 /* EHCI */
91 #define CONFIG_OMAP3_GPIO_5
92 #define CONFIG_USB_EHCI
93 #define CONFIG_USB_EHCI_OMAP
94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        25
95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
96 #define CONFIG_USB_STORAGE
97
98 /* commands to include */
99 #define CONFIG_CMD_CACHE
100 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
101 #define CONFIG_CMD_FAT          /* FAT support                  */
102 #define CONFIG_CMD_MII
103 #define CONFIG_CMD_MMC          /* MMC support                  */
104 #define CONFIG_CMD_NAND         /* NAND support                 */
105 #define CONFIG_CMD_EEPROM
106
107 #define CONFIG_SYS_NO_FLASH
108 #define CONFIG_SYS_I2C
109 #define CONFIG_SYS_OMAP24_I2C_SPEED     400000
110 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
111 #define CONFIG_SYS_I2C_OMAP34XX
112 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* base address */
113 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* bytes of address */
114 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
115
116 /*
117  * Board NAND Info.
118  */
119 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
120                                                         /* to access */
121                                                         /* nand at CS0 */
122
123 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
124                                                         /* NAND devices */
125
126 #define CONFIG_AUTO_COMPLETE
127
128 /*
129  * Miscellaneous configurable options
130  */
131 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
132 #define CONFIG_CMDLINE_EDITING
133 #define CONFIG_AUTO_COMPLETE
134 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
135
136 /* Print Buffer Size */
137 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
138                                         sizeof(CONFIG_SYS_PROMPT) + 16)
139 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
140                                                 /* args */
141 /* Boot Argument Buffer Size */
142 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
143 /* memtest works on */
144 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
145 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
146                                         0x01F00000) /* 31MB */
147
148 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
149                                                                 /* address */
150
151 /*
152  * AM3517 has 12 GP timers, they can be driven by the system clock
153  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
154  * This rate is divided by a local divisor.
155  */
156 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
157 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
158
159 /*
160  * Physical Memory Map
161  */
162 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
163 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
164 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
165
166 /*
167  * FLASH and environment organization
168  */
169
170 /* **** PISMO SUPPORT *** */
171 #define CONFIG_NAND
172 #define CONFIG_NAND_OMAP_GPMC
173 #define CONFIG_ENV_IS_IN_NAND
174 #define SMNAND_ENV_OFFSET               0x180000 /* environment starts here */
175
176 /* Redundant Environment */
177 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
178 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
179 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
180 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
181                                                 2 * CONFIG_SYS_ENV_SECT_SIZE)
182 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
183
184 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
185 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
186 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
187 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
188                                          CONFIG_SYS_INIT_RAM_SIZE - \
189                                          GENERATED_GBL_DATA_SIZE)
190
191 /*
192  * ethernet support, EMAC
193  *
194  */
195 #define CONFIG_DRIVER_TI_EMAC
196 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
197 #define CONFIG_MII
198 #define CONFIG_EMAC_MDIO_PHY_NUM        0
199 #define CONFIG_BOOTP_DNS
200 #define CONFIG_BOOTP_DNS2
201 #define CONFIG_BOOTP_SEND_HOSTNAME
202 #define CONFIG_NET_RETRY_COUNT 10
203
204 /* Defines for SPL */
205 #define CONFIG_SPL_FRAMEWORK
206 #define CONFIG_SPL_BOARD_INIT
207 #define CONFIG_SPL_CONSOLE
208 #define CONFIG_SPL_NAND_SIMPLE
209 #define CONFIG_SPL_NAND_SOFTECC
210 #define CONFIG_SPL_NAND_WORKSPACE       0x8f07f000 /* below BSS */
211
212 #define CONFIG_SPL_LIBCOMMON_SUPPORT
213 #define CONFIG_SPL_LIBDISK_SUPPORT
214 #define CONFIG_SPL_I2C_SUPPORT
215 #define CONFIG_SPL_LIBGENERIC_SUPPORT
216 #define CONFIG_SPL_SERIAL_SUPPORT
217 #define CONFIG_SPL_GPIO_SUPPORT
218 #define CONFIG_SPL_POWER_SUPPORT
219 #define CONFIG_SPL_NAND_SUPPORT
220 #define CONFIG_SPL_NAND_BASE
221 #define CONFIG_SPL_NAND_DRIVERS
222 #define CONFIG_SPL_NAND_ECC
223 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
224
225 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
226 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
227
228 #define CONFIG_SYS_SPL_MALLOC_START     0x8f000000
229 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
230 #define CONFIG_SPL_BSS_START_ADDR       0x8f080000 /* end of RAM */
231 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
232
233 /* NAND boot config */
234 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
235 #define CONFIG_SYS_NAND_PAGE_COUNT      64
236 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
237 #define CONFIG_SYS_NAND_OOBSIZE         64
238 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
239 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
240 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
241 #define CONFIG_SYS_NAND_ECCPOS          {40, 41, 42, 43, 44, 45, 46, 47,\
242                                          48, 49, 50, 51, 52, 53, 54, 55,\
243                                          56, 57, 58, 59, 60, 61, 62, 63}
244 #define CONFIG_SYS_NAND_ECCSIZE         256
245 #define CONFIG_SYS_NAND_ECCBYTES        3
246 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_SW
247 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
248
249 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
250
251 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
252 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x80000
253
254 #define CONFIG_CMD_UBI
255 #define CONFIG_CMD_UBIFS
256 #define CONFIG_RBTREE
257 #define CONFIG_LZO
258 #define CONFIG_MTD_PARTITIONS
259 #define CONFIG_MTD_DEVICE
260 #define CONFIG_CMD_MTDPARTS
261
262 /* Setup MTD for NAND on the SOM */
263 #define MTDIDS_DEFAULT          "nand0=omap2-nand.0"
264 #define MTDPARTS_DEFAULT        "mtdparts=omap2-nand.0:512k(MLO)," \
265                                 "1m(u-boot),256k(env1)," \
266                                 "256k(env2),6m(kernel),-(rootfs)"
267
268 #define CONFIG_TAM3517_SETTINGS                                         \
269         "netdev=eth0\0"                                                 \
270         "nandargs=setenv bootargs root=${nandroot} "                    \
271                 "rootfstype=${nandrootfstype}\0"                        \
272         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
273                 "nfsroot=${serverip}:${rootpath}\0"                     \
274         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
275         "addip_sta=setenv bootargs ${bootargs} "                        \
276                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
277                 ":${hostname}:${netdev}:off panic=1\0"                  \
278         "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"               \
279         "addip=if test -n ${ipdyn};then run addip_dyn;"                 \
280                 "else run addip_sta;fi\0"                               \
281         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
282         "addtty=setenv bootargs ${bootargs}"                            \
283                 " console=ttyO0,${baudrate}\0"                          \
284         "addmisc=setenv bootargs ${bootargs} ${misc}\0"                 \
285         "loadaddr=82000000\0"                                           \
286         "kernel_addr_r=82000000\0"                                      \
287         "hostname=" __stringify(CONFIG_HOSTNAME) "\0"                   \
288         "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"            \
289         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
290                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
291         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
292                 "bootm ${kernel_addr}\0"                                \
293         "nandboot=run nandargs addip addtty addmtd addmisc;"            \
294                 "nand read ${kernel_addr_r} kernel\0"                   \
295                 "bootm ${kernel_addr_r}\0"                              \
296         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
297                 "run nfsargs addip addtty addmtd addmisc;"              \
298                 "bootm ${kernel_addr_r}\0"                              \
299         "net_self=if run net_self_load;then "                           \
300                 "run ramargs addip addtty addmtd addmisc;"              \
301                 "bootm ${kernel_addr_r} ${ramdisk_addr_r};"             \
302                 "else echo Images not loades;fi\0"                      \
303         "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"          \
304         "load=tftp ${loadaddr} ${u-boot}\0"                             \
305         "loadmlo=tftp ${loadaddr} ${mlo}\0"                             \
306         "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"                    \
307         "uboot_addr=0x80000\0"                                          \
308         "update=nandecc sw;nand erase ${uboot_addr} 100000;"            \
309                 "nand write ${loadaddr} ${uboot_addr} 80000\0"          \
310         "updatemlo=nandecc hw;nand erase 0 20000;"                      \
311                 "nand write ${loadaddr} 0 20000\0"                      \
312         "upd=if run load;then echo Updating u-boot;if run update;"      \
313                 "then echo U-Boot updated;"                             \
314                         "else echo Error updating u-boot !;"            \
315                         "echo Board without bootloader !!;"             \
316                 "fi;"                                                   \
317                 "else echo U-Boot not downloaded..exiting;fi\0"         \
318
319
320 /*
321  * this is common code for all TAM3517 boards.
322  * MAC address is stored from manufacturer in
323  * I2C EEPROM
324  */
325 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
326 /*
327  * The I2C EEPROM on the TAM3517 contains
328  * mac address and production data
329  */
330 struct tam3517_module_info {
331         char customer[48];
332         char product[48];
333
334         /*
335          * bit 0~47  : sequence number
336          * bit 48~55 : week of year, from 0.
337          * bit 56~63 : year
338          */
339         unsigned long long sequence_number;
340
341         /*
342          * bit 0~7   : revision fixed
343          * bit 8~15  : revision major
344          * bit 16~31 : TNxxx
345          */
346         unsigned int revision;
347         unsigned char eth_addr[4][8];
348         unsigned char _rev[100];
349 };
350
351 #define TAM3517_READ_EEPROM(info, ret) \
352 do {                                                            \
353         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
354         if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,          \
355                 (void *)info, sizeof(*info)))                   \
356                 ret = 1;                                        \
357         else                                                    \
358                 ret = 0;                                        \
359 } while (0)
360
361 #define TAM3517_READ_MAC_FROM_EEPROM(info)                      \
362 do {                                                            \
363         char buf[80], ethname[20];                              \
364         int i;                                                  \
365         memset(buf, 0, sizeof(buf));                            \
366         for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {   \
367                 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",   \
368                         (info)->eth_addr[i][5],                 \
369                         (info)->eth_addr[i][4],                 \
370                         (info)->eth_addr[i][3],                 \
371                         (info)->eth_addr[i][2],                 \
372                         (info)->eth_addr[i][1],                 \
373                         (info)->eth_addr[i][0]);                        \
374                                                                 \
375                 if (i)                                          \
376                         sprintf(ethname, "eth%daddr", i);       \
377                 else                                            \
378                         strcpy(ethname, "ethaddr");             \
379                 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
380                 setenv(ethname, buf);                           \
381         }                                                       \
382 } while (0)
383
384 /* The following macros are taken from Technexion's documentation */
385 #define TAM3517_sequence_number(info) \
386         ((info)->sequence_number % 0x1000000000000LL)
387 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
388 #define TAM3517_year(info) ((info)->sequence_number >> 56)
389 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
390 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
391 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
392
393 #define TAM3517_PRINT_SOM_INFO(info)                            \
394 do {                                                            \
395         printf("Vendor:%s\n", (info)->customer);                \
396         printf("SOM:   %s\n", (info)->product);                 \
397         printf("SeqNr: %02llu%02llu%012llu\n",                  \
398                 TAM3517_year(info),                             \
399                 TAM3517_week_of_year(info),                     \
400                 TAM3517_sequence_number(info));                 \
401         printf("Rev:   TN%u %u.%u\n",                           \
402                 TAM3517_revision_tn(info),                      \
403                 TAM3517_revision_major(info),                   \
404                 TAM3517_revision_fixed(info));                  \
405 } while (0)
406
407 #endif
408
409 #endif /* __TAM3517_H */