# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet
# addresses are __aligned(2)".
--ignore PREFER_ETHER_ADDR_COPY
+
+# A bit shorter of a description is OK with us.
+--min-conf-desc-length=2
- grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- mkdir ~/grub2-arm
- ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
+ - mkdir ~/grub2-arm64
+ - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
env:
global:
- export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
+ cp ~/grub2-arm64/usr/lib/grub2/arm64-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi;
if [[ "${TEST_PY_BD}" != "" ]]; then
./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
-k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^qemu_arm$"
- env:
+ - TEST_PY_BD="qemu_arm64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="aarch64-softmmu"
+ BUILDMAN="^qemu_arm64$"
+ - env:
- TEST_PY_BD="qemu_mips"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips-softmmu"
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
+config SYS_BOOT_GET_CMDLINE
+ bool "Enable kernel command line setup"
+ help
+ Enables allocating and saving kernel cmdline in space between
+ "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+config SYS_BOOT_GET_KBD
+ bool "Enable kernel board information setup"
+ help
+ Enables allocating and saving a kernel copy of the bd_info in
+ space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM
F: arch/arm/mach-at91/
ARM BROADCOM BCM283X
-#M: Stephen Warren <swarren@wwwdotorg.org>
-S: Orphaned (Since 2017-07)
+M: Alexander Graf <agraf@suse.de>
+S: Maintained
F: arch/arm/mach-bcm283x/
F: drivers/gpio/bcm2835_gpio.c
F: drivers/mmc/bcm2835_sdhci.c
+F: drivers/mmc/bcm2835_sdhost.c
F: drivers/serial/serial_bcm283x_mu.c
+F: drivers/serial/serial_bcm283x_pl011.c
F: drivers/video/bcm2835.c
F: include/dm/platform_data/serial_bcm283x_mu.h
+F: drivers/pinctrl/broadcom/
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Alexander Graf <agraf@suse.de>
S: Maintained
T: git git://github.com/agraf/u-boot.git
+F: doc/README.iscsi
F: include/efi*
-F: lib/efi*
+F: lib/efi*/
F: test/py/tests/test_efi*
F: cmd/bootefi.c
+F: tools/file2include.c
FLATTENED DEVICE TREE
M: Simon Glass <sjg@chromium.org>
#
VERSION = 2018
-PATCHLEVEL = 01
+PATCHLEVEL = 03
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
+ $(BOARD_SIZE_CHECK)
u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
+ select SYS_BOOT_GET_CMDLINE
+ select SYS_BOOT_GET_KBD
config MICROBLAZE
bool "MicroBlaze architecture"
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
+ select SYS_BOOT_GET_CMDLINE
+ select SYS_BOOT_GET_KBD
config RISCV
bool "riscv architecture"
};
};
+ cgu_clk: cgu-clk@f0000000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
uart0: serial0@f0005000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
#define ARC_AUX_SLC_INVALIDATE 0x905
#define ARC_AUX_SLC_IVDL 0x910
#define ARC_AUX_SLC_FLDL 0x912
+#define ARC_AUX_SLC_RGN_START 0x914
+#define ARC_AUX_SLC_RGN_START1 0x915
+#define ARC_AUX_SLC_RGN_END 0x916
+#define ARC_AUX_SLC_RGN_END1 0x917
#define ARC_BCR_CLUSTER 0xcf
+/* MMU Management regs */
+#define ARC_AUX_MMU_BCR 0x06f
+
/* IO coherency related auxiliary registers */
#define ARC_AUX_IO_COH_ENABLE 0x500
#define ARC_AUX_IO_COH_PARTIAL 0x501
#include <asm/cache.h>
/* Bit values in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE (1 << 0)
+#define IC_CTRL_CACHE_DISABLE BIT(0)
/* Bit values in DC_CTRL */
-#define DC_CTRL_CACHE_DISABLE (1 << 0)
-#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
-#define DC_CTRL_FLUSH_STATUS (1 << 8)
+#define DC_CTRL_CACHE_DISABLE BIT(0)
+#define DC_CTRL_INV_MODE_FLUSH BIT(6)
+#define DC_CTRL_FLUSH_STATUS BIT(8)
#define CACHE_VER_NUM_MASK 0xF
-#define SLC_CTRL_SB (1 << 2)
#define OP_INV 0x1
#define OP_FLUSH 0x2
#define OP_INV_IC 0x3
+/* Bit val in SLC_CONTROL */
+#define SLC_CTRL_DIS 0x001
+#define SLC_CTRL_IM 0x040
+#define SLC_CTRL_BUSY 0x100
+#define SLC_CTRL_RGN_OP_INV 0x200
+
/*
* By default that variable will fall into .bss section.
* But .bss section is not relocated and so it will be initilized before
int slc_line_sz __section(".data");
bool slc_exists __section(".data") = false;
bool ioc_exists __section(".data") = false;
+bool pae_exists __section(".data") = false;
+
+/* To force enable IOC set ioc_enable to 'true' */
+bool ioc_enable __section(".data") = false;
-static unsigned int __before_slc_op(const int op)
+void read_decode_mmu_bcr(void)
{
- unsigned int reg = reg;
+ /* TODO: should we compare mmu version from BCR and from CONFIG? */
+#if (CONFIG_ARC_MMU_VER >= 4)
+ u32 tmp;
- if (op == OP_INV) {
- /*
- * IM is set by default and implies Flush-n-inv
- * Clear it here for vanilla inv
- */
- reg = read_aux_reg(ARC_AUX_SLC_CTRL);
- write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
- }
+ tmp = read_aux_reg(ARC_AUX_MMU_BCR);
- return reg;
-}
+ struct bcr_mmu_4 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+ n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+ /* DTLB ITLB JES JE JA */
+ unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+ pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif /* CONFIG_CPU_BIG_ENDIAN */
+ } *mmu4;
-static void __after_slc_op(const int op, unsigned int reg)
-{
- if (op & OP_FLUSH) { /* flush / flush-n-inv both wait */
- /*
- * Make sure "busy" bit reports correct status,
- * see STAR 9001165532
- */
- read_aux_reg(ARC_AUX_SLC_CTRL);
- while (read_aux_reg(ARC_AUX_SLC_CTRL) &
- DC_CTRL_FLUSH_STATUS)
- ;
- }
+ mmu4 = (struct bcr_mmu_4 *)&tmp;
- /* Switch back to default Invalidate mode */
- if (op == OP_INV)
- write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
+ pae_exists = !!mmu4->pae;
+#endif /* (CONFIG_ARC_MMU_VER >= 4) */
}
-static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
- const int op)
+static void __slc_entire_op(const int op)
{
- unsigned int aux_cmd;
- int num_lines;
+ unsigned int ctrl;
-#define SLC_LINE_MASK (~(slc_line_sz - 1))
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
- aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
+ if (!(op & OP_FLUSH)) /* i.e. OP_INV */
+ ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
+ else
+ ctrl |= SLC_CTRL_IM;
- sz += paddr & ~SLC_LINE_MASK;
- paddr &= SLC_LINE_MASK;
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
- num_lines = DIV_ROUND_UP(sz, slc_line_sz);
+ if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
+ write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
+ else
+ write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
- while (num_lines-- > 0) {
- write_aux_reg(aux_cmd, paddr);
- paddr += slc_line_sz;
- }
+ /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+ read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ /* Important to wait for flush to complete */
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
}
-static inline void __slc_entire_op(const int cacheop)
+static void slc_upper_region_init(void)
{
- int aux;
- unsigned int ctrl_reg = __before_slc_op(cacheop);
+ /*
+ * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
+ * as we don't use PAE40.
+ */
+ write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
+ write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
+}
- if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
- aux = ARC_AUX_SLC_INVALIDATE;
+static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
+{
+ unsigned int ctrl;
+ unsigned long end;
+
+ /*
+ * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
+ * - b'000 (default) is Flush,
+ * - b'001 is Invalidate if CTRL.IM == 0
+ * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
+ */
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ /* Don't rely on default value of IM bit */
+ if (!(op & OP_FLUSH)) /* i.e. OP_INV */
+ ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
else
- aux = ARC_AUX_SLC_FLUSH;
+ ctrl |= SLC_CTRL_IM;
- write_aux_reg(aux, 0x1);
+ if (op & OP_INV)
+ ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
+ else
+ ctrl &= ~SLC_CTRL_RGN_OP_INV;
- __after_slc_op(cacheop, ctrl_reg);
-}
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
-static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
- const int cacheop)
-{
- unsigned int ctrl_reg = __before_slc_op(cacheop);
- __slc_line_loop(paddr, sz, cacheop);
- __after_slc_op(cacheop, ctrl_reg);
+ /*
+ * Lower bits are ignored, no need to clip
+ * END needs to be setup before START (latter triggers the operation)
+ * END can't be same as START, so add (l2_line_sz - 1) to sz
+ */
+ end = paddr + sz + slc_line_sz - 1;
+
+ /*
+ * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
+ * are always == 0 as we don't use PAE40, so we only setup lower ones
+ * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
+ */
+ write_aux_reg(ARC_AUX_SLC_RGN_END, end);
+ write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
+
+ /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+ read_aux_reg(ARC_AUX_SLC_CTRL);
+
+ while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
}
-#else
-#define __slc_entire_op(cacheop)
-#define __slc_line_op(paddr, sz, cacheop)
-#endif
+#endif /* CONFIG_ISA_ARCV2 */
#ifdef CONFIG_ISA_ARCV2
static void read_decode_cache_bcr_arcv2(void)
} cbcr;
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
- if (cbcr.fields.c)
+ if (cbcr.fields.c && ioc_enable)
ioc_exists = true;
}
#endif
}
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
- if (dbcr.fields.ver){
+ if (dbcr.fields.ver) {
dcache_exists = true;
l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
if (!dc_line_sz)
* so setting 0x11 implies 512M, 0x12 implies 1G...
*/
write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
- order_base_2(ap_size/1024) - 2);
-
+ order_base_2(ap_size / 1024) - 2);
/* IOC Aperture start must be aligned to the size of the aperture */
if (ap_base % ap_size != 0)
write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
-
}
-#endif
+
+ read_decode_mmu_bcr();
+
+ /*
+ * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
+ * only if PAE exists in current HW. So we had to check pae_exist
+ * before using them.
+ */
+ if (slc_exists && pae_exists)
+ slc_upper_region_init();
+#endif /* CONFIG_ISA_ARCV2 */
}
int icache_status(void)
IC_CTRL_CACHE_DISABLE);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
void invalidate_icache_all(void)
{
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
__builtin_arc_nop();
read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
}
-}
-#else
-void invalidate_icache_all(void)
-{
-}
+
+#ifdef CONFIG_ISA_ARCV2
+ if (slc_exists)
+ __slc_entire_op(OP_INV);
#endif
+}
int dcache_status(void)
{
static void __after_dc_op(const int op, unsigned int reg)
{
if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
/* Switch back to default Invalidate mode */
if (op == OP_INV)
const int cacheop)
{
unsigned int ctrl_reg = __before_dc_op(cacheop);
+
__cache_line_loop(paddr, sz, cacheop);
__after_dc_op(cacheop, ctrl_reg);
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
+ if (start >= end)
+ return;
+
#ifdef CONFIG_ISA_ARCV2
if (!ioc_exists)
#endif
#ifdef CONFIG_ISA_ARCV2
if (slc_exists && !ioc_exists)
- __slc_line_op(start, end - start, OP_INV);
+ __slc_rgn_op(start, end - start, OP_INV);
#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
+ if (start >= end)
+ return;
+
#ifdef CONFIG_ISA_ARCV2
if (!ioc_exists)
#endif
#ifdef CONFIG_ISA_ARCV2
if (slc_exists && !ioc_exists)
- __slc_line_op(start, end - start, OP_FLUSH);
+ __slc_rgn_op(start, end - start, OP_FLUSH);
#endif
}
#endif
sr r5, [ARC_AUX_IC_CTRL]
+ mov r5, 1
+ sr r5, [ARC_AUX_IC_IVIC]
+ ; As per ARC HS databook (see chapter 5.3.3.2)
+ ; it is required to add 3 NOPs after each write to IC_IVIC.
+ nop
+ nop
+ nop
+
1:
; Disable/enable D-cache according to configuration
lr r5, [ARC_BCR_DC_BUILD]
#endif
sr r5, [ARC_AUX_DC_CTRL]
+ mov r5, 1
+ sr r5, [ARC_AUX_DC_IVDC]
+
+
1:
#ifdef CONFIG_ISA_ARCV2
; Disable System-Level Cache (SLC)
config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
+ select PL010_SERIAL
config TARGET_ASPENITE
bool "Support aspenite"
bool "Support apx4devkit"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config TARGET_XFI3
bool "Support xfi3"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config TARGET_M28EVK
bool "Support m28evk"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config TARGET_MX23EVK
bool "Support mx23evk"
select CPU_ARM926EJS
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select PL011_SERIAL
config TARGET_MX28EVK
bool "Support mx28evk"
select CPU_ARM926EJS
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select PL011_SERIAL
config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
select CPU_ARM926EJS
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select PL011_SERIAL
config TARGET_BG0900
bool "Support bg0900"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+ select PL011_SERIAL
config TARGET_SPEAR310
bool "Support spear310"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+ select PL011_SERIAL
config TARGET_SPEAR320
bool "Support spear320"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+ select PL011_SERIAL
config TARGET_SPEAR600
bool "Support spear600"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+ select PL011_SERIAL
config TARGET_STV0991
bool "Support stv0991"
select DM_SPI
select DM_SPI_FLASH
select SPI_FLASH
+ select PL01X_SERIAL
config TARGET_X600
bool "Support x600"
select BOARD_LATE_INIT
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore_eet"
select DM_SERIAL
select DM_GPIO
select OF_CONTROL
+ select PL01X_SERIAL
+ select SERIAL_SEARCH_ALL
imply FAT_WRITE
config TARGET_VEXPRESS_CA15_TC2
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select PL011_SERIAL
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
select CPU_V7
+ select PL011_SERIAL
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7
+ select PL011_SERIAL
config TARGET_BCM23550_W1D
bool "Support bcm23550_w1d"
config ARCH_HIGHBANK
bool "Calxeda Highbank"
select CPU_V7
+ select PL011_SERIAL
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
select DM
select DM_SERIAL
+ select PL01X_SERIAL
config ARCH_KEYSTONE
bool "TI Keystone"
config ARCH_QEMU
bool "QEMU Virtual Platform"
- select CPU_V7
- select ARCH_SUPPORT_PSCI
select DM
select DM_SERIAL
select OF_CONTROL
+ select PL01X_SERIAL
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select USE_TINY_PRINTF
imply CMD_GPT
imply FAT_WRITE
+ imply OF_LIBFDT_OVERLAY
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
bool "Support TS4600"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select PL011_SERIAL
config ARCH_VF610
bool "Freescale Vybrid"
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select ARM64
+ select PL01X_SERIAL
config TARGET_VEXPRESS64_BASE_FVP
bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
select SEMIHOSTING
+ select PL01X_SERIAL
config TARGET_VEXPRESS64_BASE_FVP_DRAM
bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
select ARM64
+ select PL01X_SERIAL
help
This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
the default config to allow the user to load the images directly into
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
+ select PL01X_SERIAL
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
select DM_GPIO
select DM_SERIAL
select OF_CONTROL
+ select PL01X_SERIAL
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
select OF_CONTROL
select DM_SERIAL
select DM_USB
+ select PL01X_SERIAL
help
Support for Poplar 96boards EE platform. It features a HI3798cv200
SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012A2G5RDB
+ bool "Support ls1012a2g5rdb"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ help
+ Support for Freescale LS1012A2G5RDB platform.
+ The LS1012A 2G5 Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
select ARCH_LS1012A
select ARM64
select OF_CONTROL
select SYS_CACHE_SHIFT_7
+ select PL01X_SERIAL
config ARCH_ASPEED
bool "Support Aspeed SoCs"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/creative/xfi3/Kconfig"
+source "board/eets/pdu001/Kconfig"
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
default y
- depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+ depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
- !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && \
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
out_le32(cltbenr, 0xf);
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable
serdes_prtcl_map[NONE] = 1;
}
+__weak int get_serdes_volt(void)
+{
+ return -1;
+}
+
+__weak int set_serdes_volt(int svdd)
+{
+ return -1;
+}
+
+#define LNAGCR0_RT_RSTB 0x00600000
+
+#define RSTCTL_RESET_MASK 0x000000E0
+
+#define RSTCTL_RSTREQ 0x80000000
+#define RSTCTL_RST_DONE 0x40000000
+#define RSTCTL_RSTERR 0x20000000
+
+#define RSTCTL_SDEN 0x00000020
+#define RSTCTL_SDRST_B 0x00000040
+#define RSTCTL_PLLRST_B 0x00000080
+
+#define TCALCR_CALRST_B 0x08000000
+
+struct serdes_prctl_info {
+ u32 id;
+ u32 mask;
+ u32 shift;
+};
+
+struct serdes_prctl_info srds_prctl_info[] = {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ {.id = 1,
+ .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+ .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
+ },
+
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ {.id = 2,
+ .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+ .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
+ },
+#endif
+ {} /* NULL ENTRY */
+};
+
+static int get_serdes_prctl_info_idx(u32 serdes_id)
+{
+ int pos = 0;
+ struct serdes_prctl_info *srds_info;
+
+ /* loop until NULL ENTRY defined by .id=0 */
+ for (srds_info = srds_prctl_info; srds_info->id != 0;
+ srds_info++, pos++) {
+ if (srds_info->id == serdes_id)
+ return pos;
+ }
+
+ return -1;
+}
+
+static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base,
+ bool cmplt)
+{
+ int i, pos;
+ u32 cfg_tmp;
+
+ pos = get_serdes_prctl_info_idx(serdes_id);
+ if (pos == -1) {
+ printf("invalid serdes_id %d\n", serdes_id);
+ return;
+ }
+
+ cfg_tmp = cfg & srds_prctl_info[pos].mask;
+ cfg_tmp >>= srds_prctl_info[pos].shift;
+
+ for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
+ if (cmplt)
+ setbits_le32(&serdes_base->lane[i].gcr0,
+ LNAGCR0_RT_RSTB);
+ else
+ clrbits_le32(&serdes_base->lane[i].gcr0,
+ LNAGCR0_RT_RSTB);
+ }
+}
+
+static void do_pll_reset(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+
+ for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+ clrbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RESET_MASK);
+ udelay(1);
+
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RSTREQ);
+ }
+ udelay(1);
+}
+
+static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
+{
+ clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+ clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+}
+
+static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ if (!(cfg == 0x3 && i == 1)) {
+ udelay(1);
+ setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+ setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+ }
+ udelay(1);
+}
+
+static void do_pll_reset_done(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+ u32 reg = 0;
+
+ for (i = 0; i < 2; i++) {
+ reg = in_le32(&serdes_base->bank[i].pllcr0);
+ if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RST_DONE);
+ }
+ }
+}
+
+static void do_serdes_enable(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+
+ for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+ setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
+ udelay(1);
+
+ setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
+ udelay(1);
+ /* Take the Rx/Tx calibration out of reset */
+ do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
+ }
+}
+
+static void do_pll_lock(u32 cfg,
+ struct ccsr_serdes __iomem *serdes_base)
+{
+ int i;
+ u32 reg = 0;
+
+ for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+ /* if the PLL is not locked, set RST_ERR */
+ reg = in_le32(&serdes_base->bank[i].pllcr0);
+ if (!((reg >> 23) & 0x1)) {
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_RSTERR);
+ } else {
+ udelay(1);
+ setbits_le32(&serdes_base->bank[i].rstctl,
+ RSTCTL_SDRST_B);
+ udelay(1);
+ }
+ }
+}
+
+int setup_serdes_volt(u32 svdd)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_serdes __iomem *serdes1_base =
+ (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+ u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ struct ccsr_serdes __iomem *serdes2_base =
+ (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+ u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+#endif
+ u32 cfg_tmp;
+ int svdd_cur, svdd_tar;
+ int ret = 1;
+
+ /* Only support switch SVDD to 900mV */
+ if (svdd != 900)
+ return -EINVAL;
+
+ /* Scale up to the LTC resolution is 1/4096V */
+ svdd = (svdd * 4096) / 1000;
+
+ svdd_tar = svdd;
+ svdd_cur = get_serdes_volt();
+ if (svdd_cur < 0)
+ return -EINVAL;
+
+ debug("%s: current SVDD: %x; target SVDD: %x\n",
+ __func__, svdd_cur, svdd_tar);
+ if (svdd_cur == svdd_tar)
+ return 0;
+
+ /* Put the all enabled lanes in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
+#endif
+
+ /* Put the all enabled PLL in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_pll_reset(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_pll_reset(cfg_tmp, serdes2_base);
+#endif
+
+ /* Put the Rx/Tx calibration into reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ do_rx_tx_cal_reset(serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ do_rx_tx_cal_reset(serdes2_base);
+#endif
+
+ ret = set_serdes_volt(svdd);
+ if (ret < 0) {
+ printf("could not change SVDD\n");
+ ret = -1;
+ }
+
+ /* For each PLL that’s not disabled via RCW enable the SERDES */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_serdes_enable(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_serdes_enable(cfg_tmp, serdes2_base);
+#endif
+
+ /* Wait for at at least 625us, ensure the PLLs being reset are locked */
+ udelay(800);
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_pll_lock(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_pll_lock(cfg_tmp, serdes2_base);
+#endif
+ /* Take the all enabled lanes out of reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
+#endif
+
+ /* For each PLL being reset, and achieved PLL lock set RST_DONE */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ cfg_tmp = cfg_rcwsrds1 & 0x3;
+ do_pll_reset_done(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ cfg_tmp = cfg_rcwsrds1 & 0xC;
+ cfg_tmp >>= 2;
+ do_pll_reset_done(cfg_tmp, serdes2_base);
+#endif
+
+ return ret;
+}
+
void fsl_serdes_init(void)
{
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
}
#endif
+/* Get VDD in the unit mV from voltage ID */
+int get_core_volt_from_fuse(void)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int vdd;
+ u32 fusesr;
+ u8 vid;
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_le32(&gur->dcfg_fusesr);
+ debug("%s: fusesr = 0x%x\n", __func__, fusesr);
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
+ debug("%s: VID = 0x%x\n", __func__, vid);
+ switch (vid) {
+ case 0x00: /* VID isn't supported */
+ vdd = -EINVAL;
+ debug("%s: The VID feature is not supported\n", __func__);
+ break;
+ case 0x08: /* 0.9V silicon */
+ vdd = 900;
+ break;
+ case 0x10: /* 1.0V silicon */
+ vdd = 1000;
+ break;
+ default: /* Other core voltage */
+ vdd = -EINVAL;
+ debug("%s: The VID(%x) isn't supported\n", __func__, vid);
+ break;
+ }
+ debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
+
+ return vdd;
+}
+
#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
+#ifdef CONFIG_VID
+ init_func_vid();
+#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
am335x-bonegreen.dtb \
am335x-icev2.dtb \
am335x-pxm50.dtb \
- am335x-rut.dtb
+ am335x-rut.dtb \
+ am335x-pdu001.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am43x-epos-evm.dtb \
am437x-idk-evm.dtb
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
am57xx-beagle-x15-revc.dtb \
+ am574x-idk.dtb \
am572x-idk.dtb \
am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
+ stm32429i-eval.dtb \
stm32f469-disco.dtb
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
omap3-evm-37xx.dtb \
omap3-evm.dtb
+dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
+ omap3-beagle-xm-ab.dtb \
+ omap3-beagle-xm.dtb \
+ omap3-beagle.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
--- /dev/null
+/*
+ * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&l4_wkup {
+ u-boot,dm-pre-reloc;
+};
+
+&scm {
+ u-boot,dm-pre-reloc;
+};
+
+&am33xx_pinmux {
+ u-boot,dm-pre-reloc;
+};
+
+&uart3_pins {
+ u-boot,dm-pre-reloc;
+};
+
+&uart3 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc1_pins {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc2_pins {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * pdu001.dts
+ *
+ * EETS GmbH PDU001 board device tree file
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/leds-pca9532.h>
+
+/ {
+ model = "EETS,PDU001";
+ compatible = "eets,pdu001", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ };
+
+ lis3_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lis3_reg";
+ regulator-boot-on;
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins_s0>;
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <16>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+
+ display-timings {
+ 240x320p16 {
+ clock-frequency = <6500000>;
+ hactive = <240>;
+ vactive = <320>;
+ hfront-porch = <6>;
+ hback-porch = <6>;
+ hsync-len = <1>;
+ vback-porch = <6>;
+ vfront-porch = <6>;
+ vsync-len = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <1>;
+ de-active = <0>;
+ };
+ };
+ };
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
+ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */
+ >;
+ };
+
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
+ AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
+ AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
+ AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */
+ AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Port 1 (emac0) */
+ AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */
+ AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */
+ AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */
+ AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+ AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */
+ AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
+ AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
+ AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
+
+ /* Port 2 (emac1) */
+ AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */
+ AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */
+ AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */
+ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */
+ AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */
+ AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
+ AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
+ AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
+ AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
+ AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
+ AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */
+ AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */
+ AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ /* eMMC */
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ /* SD cardcage */
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ /* card change signal for frontpanel SD cardcage */
+ AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+ >;
+ };
+
+ lcd_pins_s0: lcd_pins_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
+ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
+ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
+ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
+ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
+ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
+ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
+ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
+ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
+ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
+ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
+ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
+ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
+ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
+ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
+ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
+ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
+ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+ dcan0_pins: pinmux_dcan0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
+ AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ rs485-rts-active-high;
+ rs485-rts-delay = <0 0>;
+ linux,rs485-enabled-at-boot-time;
+
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+
+ m2_eeprom: m2_eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ status = "okay";
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+ clock-frequency = <100000>;
+
+ board_24aa025e48: board_24aa025e48@50 {
+ compatible = "microchip,24aa025e48";
+ reg = <0x50>;
+ };
+
+ backplane_24aa025e48: backplane_24aa025e48@53 {
+ compatible = "microchip,24aa025e48";
+ reg = <0x53>;
+ };
+
+ pca9532: pca9532@60 {
+ compatible = "nxp,pca9532";
+ reg = <0x60>;
+ psc0 = <0x97>;
+ pwm0 = <0x80>;
+ psc1 = <0x97>;
+ pwm1 = <0x10>;
+
+ run.red@0 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ run.green@1 {
+ type = <PCA9532_TYPE_LED>;
+ default-state = "on";
+ };
+ s2.red@2 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ s2.green@3 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ s1.yellow@4 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ s1.green@5 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ };
+
+ pca9530: pca9530@61 {
+ compatible = "nxp,pca9530";
+ reg = <0x61>;
+
+ tft-panel@0 {
+ type = <PCA9532_TYPE_LED>;
+ linux,default-trigger = "backlight";
+ default-state = "on";
+ };
+ };
+
+ mcp79400: mcp79400@6f {
+ compatible = "microchip,mcp7940x";
+ reg = <0x6f>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ ti,pindir-d0-out-d1-in;
+ status = "okay";
+
+ cfaf240320a032t {
+ compatible = "orise,otm3225a";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ // SPI mode 3
+ spi-cpol;
+ spi-cpha;
+ status = "okay";
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+/*
+ * Disable soc's rtc as we have no VBAT for it. This makes the board
+ * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
+ */
+&rtc {
+ status = "disabled";
+};
+
+&lcdc {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-name = "ldo_vrtc";
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-name = "buck_vdd_ddr";
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits */
+ regulator-name = "buck_vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits */
+ regulator-name = "buck_vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-name = "boost_res";
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-name = "ldo_vdig1";
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-name = "ldo_vdig2";
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-name = "ldo_vpll";
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-name = "ldo_vdac";
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-name = "ldo_vaux1";
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-name = "ldo_vaux2";
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-name = "ldo_vaux33";
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-name = "ldo_vmmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vbb_reg: regulator@13 {
+ regulator-name = "bat_vbb";
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+ dual_emac; /* no switch, two distinct MACs */
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <2>;
+};
+
+&tscadc {
+ status = "okay";
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,coordinate-readouts = <5>;
+ ti,wire-config = <0x01 0x10 0x22 0x33>;
+ ti,charge-delay = <0x400>;
+ };
+
+ adc {
+ ti,adc-channels = <4 5 6 7>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ non-removable;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&dcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan0_pins>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ status-leds {
+ compatible = "gpio-leds";
+ cpu0-led {
+ label = "status0:red:cpu0";
+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ usr0-led {
+ label = "status0:green:usr";
+ gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat-led {
+ label = "status0:blue:heartbeat";
+ gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ cpu1-led {
+ label = "status1:red:cpu1";
+ gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu1";
+ };
+
+ usr1-led {
+ label = "status1:green:usr";
+ gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ mmc0-led {
+ label = "status1:blue:mmc0";
+ gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+ };
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&extcon_usb2 {
+ id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+};
+
+&sn65hvs882 {
+ load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
/dts-v1/;
#include "dra74x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "am572x-idk-common.dtsi"
#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
model = "TI AM5728 IDK";
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x80000000>;
- };
-
- status-leds {
- compatible = "gpio-leds";
- cpu0-led {
- label = "status0:red:cpu0";
- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "cpu0";
- };
-
- usr0-led {
- label = "status0:green:usr";
- gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- heartbeat-led {
- label = "status0:blue:heartbeat";
- gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
- };
-
- cpu1-led {
- label = "status1:red:cpu1";
- gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "cpu1";
- };
-
- usr1-led {
- label = "status1:green:usr";
- gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- mmc0-led {
- label = "status1:blue:mmc0";
- gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "mmc0";
- };
- };
};
&mmc1 {
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
-
-&omap_dwc3_2 {
- extcon = <&extcon_usb2>;
-};
-
-&extcon_usb2 {
- id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
-};
-
-&sn65hvs882 {
- load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
-};
-
-&pcie1_rc {
- status = "okay";
- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
-};
-
-&pcie1_ep {
- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
-};
-
-&mailbox5 {
- status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+
+/dts-v1/;
+
+#include "dra76x.dtsi"
+#include "am572x-idk-common.dtsi"
+
+/ {
+ model = "TI AM5748 IDK";
+ compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
+};
+
+&qspi {
+ spi-max-frequency = <96000000>;
+ m25p80@0 {
+ spi-max-frequency = <96000000>;
+ };
+};
+// SPDX-License-Identifier: GPL-2.0
&cpu_alert0 {
temperature = <80000>; /* milliCelsius */
};
+// SPDX-License-Identifier: GPL-2.0
&cpu_alert0 {
temperature = <90000>; /* milliCelsius */
};
skip-init;
u-boot,dm-pre-reloc;
};
+
+&gpio {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * NXP ls1012a 2G5RDB board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A 2G5RDB Board";
+
+ aliases {
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = &duart0;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
*
* Copyright 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1012a.dtsi"
/*
* Copyright 2016 Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
/*
* Copyright 2016 Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1012a.dtsi"
*
* Copyright 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2016, Freescale Semiconductor
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1012a.dtsi"
/*
* Copyright 2016 Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton64.dtsi"
*
* Copyright (C) 2015, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright (C) 2015, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1043a.dtsi"
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton64.dtsi"
*
* Copyright (C) 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright (C) 2016, Freescale Semiconductor
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <Mingkai.hu@nxp.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "fsl-ls1046a.dtsi"
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton64.dtsi"
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/ {
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/ {
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
*
* Copyright 2017 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
&qspi {
status = "okay";
- flash0: m25p80@0 {
- compatible = "s25fl512s","spi-flash";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- tshsl-ns = <392>;
- tsd2d-ns = <392>;
- tchsh-ns = <100>;
- tslch-ns = <100>;
+ flash0: m25p80@0 {
+ compatible = "s25fl512s","spi-flash";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <96000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cdns,tshsl-ns = <392>;
+ cdns,tsd2d-ns = <392>;
+ cdns,tchsh-ns = <100>;
+ cdns,tslch-ns = <100>;
block-size = <18>;
-
- partition@0 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001C0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.file-system";
- reg = <0x009C0000 0x3640000>;
- };
- };
+ partition@0 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00000000 0x00100000>;
+ };
+ partition@1 {
+ label = "QSPI.u-boot-env";
+ reg = <0x00100000 0x00040000>;
+ };
+ partition@2 {
+ label = "QSPI.skern";
+ reg = <0x00140000 0x0040000>;
+ };
+ partition@3 {
+ label = "QSPI.pmmc-firmware";
+ reg = <0x00180000 0x0040000>;
+ };
+ partition@4 {
+ label = "QSPI.kernel";
+ reg = <0x001C0000 0x0800000>;
+ };
+ partition@5 {
+ label = "QSPI.file-system";
+ reg = <0x009C0000 0x3640000>;
+ };
+ };
};
&mmc0 {
<0x24000000 0x4000000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
num-cs = <4>;
- fifo-depth = <256>;
- sram-size = <256>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x24000000>;
status = "disabled";
};
--- /dev/null
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
--- /dev/null
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-beagle-xm.dts"
+
+/ {
+ /* HS USB Port 2 Power enable was inverted with the xM C */
+ hsusb2_power: hsusb2_power_reg {
+ enable-active-high;
+ };
+};
--- /dev/null
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+
+/ {
+ model = "TI OMAP3 BeagleBoard xM";
+ compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vcc>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ aliases {
+ display0 = &dvi0;
+ display1 = &tv0;
+ ethernet = ðernet;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "beagleboard::usr0";
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "beagleboard::usr1";
+ gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+
+ pmu_stat {
+ label = "beagleboard::pmu_stat";
+ pwms = <&twl_pwmled 1 7812500>;
+ max-brightness = <127>;
+ };
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3beagle";
+
+ ti,mcbsp = <&mcbsp2>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ user {
+ label = "user";
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x114>;
+ wakeup-source;
+ };
+
+ };
+
+ /* HS USB Port 2 Power */
+ hsusb2_power: hsusb2_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb2_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
+ startup-delay-us = <70000>;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
+ vcc-supply = <&hsusb2_power>;
+ #phy-cells = <0>;
+ };
+
+ tfp410: encoder0 {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
+
+ /* XXX pinctrl from twl */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ dvi0: connector0 {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ tv0: connector1 {
+ compatible = "svideo-connector";
+ label = "tv";
+
+ port {
+ tv_connector_in: endpoint {
+ remote-endpoint = <&venc_out>;
+ };
+ };
+ };
+
+ etb@5401b000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0x5401b000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm_out>;
+ };
+ };
+ };
+
+ etm@54010000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x54010000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etm_out: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
+ };
+};
+
+&omap3_pmx_wkup {
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
+ >;
+ };
+
+ dss_dpi_pins2: pinmux_dss_dpi_pins1 {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
+ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
+ OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
+ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
+ OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
+ OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
+ >;
+ };
+};
+
+&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_pins
+ >;
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+ >;
+ };
+
+ hsusb2_pins: pinmux_hsusb2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
+ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
+ >;
+ };
+
+ dss_dpi_pins1: pinmux_dss_dpi_pins2 {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
+ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
+ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
+ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
+
+ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
+ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
+ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
+ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
+ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
+ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
+ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
+ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
+ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
+ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
+ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
+ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
+
+ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
+ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
+ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
+ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
+ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
+ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_2_pins
+ >;
+
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
+ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
+ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ twl_audio: audio {
+ compatible = "ti,twl4030-audio";
+ codec {
+ };
+ };
+
+ twl_power: power {
+ compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
+ ti,use_poweroff;
+ };
+ };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc1>;
+ vqmmc-supply = <&vsim>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&twl_gpio {
+ ti,use-leds;
+ /* pullups: BIT(1) */
+ ti,pullups = <0x000002>;
+ /*
+ * pulldowns:
+ * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+ * BIT(15), BIT(16), BIT(17)
+ */
+ ti,pulldowns = <0x03a1c4>;
+};
+
+&usb_otg_hs {
+ interface-type = <0>;
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ mode = <3>;
+ power = <50>;
+};
+
+&uart3 {
+ interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_pins>;
+};
+
+&usbhshost {
+ port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@2 {
+ compatible = "usb424,9514";
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
+
+&vaux2 {
+ regulator-name = "usb_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
+
+&mcbsp2 {
+ status = "okay";
+};
+
+&dss {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &dss_dpi_pins1
+ &dss_dpi_pins2
+ >;
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&venc {
+ status = "ok";
+
+ vdda-supply = <&vdac>;
+
+ port {
+ venc_out: endpoint {
+ remote-endpoint = <&tv_connector_in>;
+ ti,channels = <2>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+
+/ {
+ model = "TI OMAP3 BeagleBoard";
+ compatible = "ti,omap3-beagle", "ti,omap3";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vcc>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ aliases {
+ display0 = &dvi0;
+ display1 = &tv0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pmu_stat {
+ label = "beagleboard::pmu_stat";
+ gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
+ };
+
+ heartbeat {
+ label = "beagleboard::usr0";
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc {
+ label = "beagleboard::usr1";
+ gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ /* HS USB Port 2 Power */
+ hsusb2_power: hsusb2_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb2_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
+ startup-delay-us = <70000>;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
+ vcc-supply = <&hsusb2_power>;
+ #phy-cells = <0>;
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "omap3beagle";
+
+ ti,mcbsp = <&mcbsp2>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ user {
+ label = "user";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x114>;
+ wakeup-source;
+ };
+
+ };
+
+ tfp410: encoder0 {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tfp410_pins>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ dvi0: connector0 {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ tv0: connector1 {
+ compatible = "svideo-connector";
+ label = "tv";
+
+ port {
+ tv_connector_in: endpoint {
+ remote-endpoint = <&venc_out>;
+ };
+ };
+ };
+
+ etb@540000000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0x5401b000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm_out>;
+ };
+ };
+ };
+
+ etm@54010000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x54010000 0x1000>;
+
+ clocks = <&emu_src_ck>;
+ clock-names = "apb_pclk";
+ port {
+ etm_out: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
+ };
+};
+
+&omap3_pmx_wkup {
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
+ >;
+ };
+};
+
+&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_pins
+ >;
+
+ hsusb2_pins: pinmux_hsusb2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
+ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+ >;
+ };
+
+ tfp410_pins: pinmux_tfp410_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
+ >;
+ };
+
+ dss_dpi_pins: pinmux_dss_dpi_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
+ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
+ OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
+ OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
+ OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
+ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
+ OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
+ OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
+ OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
+ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
+ OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
+ OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
+ OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
+ OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
+ OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
+ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
+ OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
+ OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
+ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
+ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
+ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
+ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
+ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
+ OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
+ OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
+ OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
+ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
+ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb2_2_pins
+ >;
+
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+ OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
+ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
+ OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ twl: twl@48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ twl_audio: audio {
+ compatible = "ti,twl4030-audio";
+ codec {
+ };
+ };
+ };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&i2c3 {
+ clock-frequency = <100000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc1>;
+ vqmmc-supply = <&vsim>;
+ bus-width = <8>;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&usbhshost {
+ port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+ ti,use-leds;
+ /* pullups: BIT(1) */
+ ti,pullups = <0x000002>;
+ /*
+ * pulldowns:
+ * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+ * BIT(15), BIT(16), BIT(17)
+ */
+ ti,pulldowns = <0x03a1c4>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_pins>;
+};
+
+&usb_otg_hs {
+ interface-type = <0>;
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ mode = <3>;
+ power = <50>;
+};
+
+&vaux2 {
+ regulator-name = "vdd_ehci";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
+
+&mcbsp2 {
+ status = "okay";
+};
+
+/* Needed to power the DPI pins */
+&vpll2 {
+ regulator-always-on;
+};
+
+&dss {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_dpi_pins>;
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&venc {
+ status = "ok";
+
+ vdda-supply = <&vdac>;
+
+ port {
+ venc_out: endpoint {
+ remote-endpoint = <&tv_connector_in>;
+ ti,channels = <2>;
+ };
+ };
+};
+
+&gpmc {
+ status = "ok";
+ ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */
+
+ /* Chip select 0 */
+ nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* NAND I/O window, 4 bytes */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ ti,nand-ecc-opt = "ham1";
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ nand-bus-width = <16>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpmc,device-width = <2>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <36>;
+ gpmc,cs-wr-off-ns = <36>;
+ gpmc,adv-on-ns = <6>;
+ gpmc,adv-rd-off-ns = <24>;
+ gpmc,adv-wr-off-ns = <36>;
+ gpmc,oe-on-ns = <6>;
+ gpmc,oe-off-ns = <48>;
+ gpmc,we-on-ns = <6>;
+ gpmc,we-off-ns = <30>;
+ gpmc,rd-cycle-ns = <72>;
+ gpmc,wr-cycle-ns = <72>;
+ gpmc,access-ns = <54>;
+ gpmc,wr-access-ns = <30>;
+
+ partition@0 {
+ label = "X-Loader";
+ reg = <0 0x80000>;
+ };
+ partition@80000 {
+ label = "U-Boot";
+ reg = <0x80000 0x1e0000>;
+ };
+ partition@1c0000 {
+ label = "U-Boot Env";
+ reg = <0x260000 0x20000>;
+ };
+ partition@280000 {
+ label = "Kernel";
+ reg = <0x280000 0x400000>;
+ };
+ partition@780000 {
+ label = "Filesystem";
+ reg = <0x680000 0xf980000>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Lager board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7790-lager.dts"
+#include "r8a7790-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Lager board
+ *
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
+ * Copyright (C) 2015-2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ * 2: CN22
+ * 3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
+/dts-v1/;
+#include "r8a7790.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Lager";
+ compatible = "renesas,lager", "renesas,r8a7790";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scifa1;
+ i2c8 = &gpioi2c1;
+ i2c10 = &i2cexio0;
+ i2c11 = &i2cexio1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory@140000000 {
+ device_type = "memory";
+ reg = <1 0x40000000 0 0xc0000000>;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ keyboard {
+ compatible = "gpio-keys";
+
+ one {
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ };
+ two {
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ };
+ three {
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ };
+ four {
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led6 {
+ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ };
+ led7 {
+ gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+ };
+ led8 {
+ gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ fixedregulator3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi2: regulator-vcc-sdhi2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ rsnd_ak4643: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4643>;
+ clocks = <&audio_clock>;
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ x2_clk: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ x13_clk: x13-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ gpioi2c1: i2c-8 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
+ &gpio1 16 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
+ * We use the I2C demuxer, so the desired IP core can be selected at runtime
+ * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
+ * Note: For testing the I2C slave feature, it is convenient to connect this
+ * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
+ * instantiate the slave device at runtime according to the documentation.
+ * You can then communicate with the slave via IIC3.
+ *
+ * IIC0/I2C0 does not appear to support fallback to GPIO.
+ */
+ i2cexio0: i2c-10 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic0>, <&i2c0>;
+ i2c-bus-name = "i2c-exio0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /*
+ * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
+ * This is similar to the arangement described for i2cexio0 (above)
+ * with a fallback to GPIO also provided.
+ */
+ i2cexio1: i2c-11 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
+ i2c-bus-name = "i2c-exio1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
+ <&x13_clk>, <&x2_clk>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
+ "dclkin.0", "dclkin.1";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ port@1 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ port@2 {
+ lvds_connector: endpoint {
+ };
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ du_pins: du {
+ groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
+ function = "du";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq0";
+ function = "intc";
+ };
+
+ scifa1_pins: scifa1 {
+ groups = "scifa1_data";
+ function = "scifa1";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ mmc1_pins: mmc1 {
+ groups = "mmc1_data8", "mmc1_ctrl";
+ function = "mmc1";
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+
+ msiof1_pins: msiof1 {
+ groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
+ "msiof1_tx";
+ function = "msiof1";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ iic0_pins: iic0 {
+ groups = "iic0";
+ function = "iic0";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ iic1_pins: iic1 {
+ groups = "iic1";
+ function = "iic1";
+ };
+
+ iic2_pins: iic2 {
+ groups = "iic2";
+ function = "iic2";
+ };
+
+ iic3_pins: iic3 {
+ groups = "iic3";
+ function = "iic3";
+ };
+
+ hsusb_pins: hsusb {
+ groups = "usb0_ovc_vbus";
+ function = "usb0";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ usb2_pins: usb2 {
+ groups = "usb2";
+ function = "usb2";
+ };
+
+ vin0_pins: vin0 {
+ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+ function = "vin0";
+ };
+
+ vin1_pins: vin1 {
+ groups = "vin1_data8", "vin1_clk";
+ function = "vin1";
+ };
+
+ sound_pins: sound {
+ groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a";
+ function = "audio_clk";
+ };
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&cmt0 {
+ status = "okay";
+};
+
+&mmcif1 {
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&fixedregulator3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpha;
+ spi-cpol;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "user";
+ reg = <0x00040000 0x00400000>;
+ read-only;
+ };
+ partition@440000 {
+ label = "flash";
+ reg = <0x00440000 0x03bc0000>;
+ };
+ };
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scifa1 {
+ pinctrl-0 = <&scifa1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&msiof1 {
+ pinctrl-0 = <&msiof1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ pmic: pmic@0 {
+ compatible = "renesas,r2a11302ft";
+ reg = <0>;
+ spi-max-frequency = <6000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_dvfs>;
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "i2c-exio0";
+};
+
+&iic0 {
+ pinctrl-0 = <&iic0_pins>;
+ pinctrl-names = "i2c-exio0";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "i2c-exio1";
+};
+
+&iic1 {
+ pinctrl-0 = <&iic1_pins>;
+ pinctrl-names = "i2c-exio1";
+};
+
+&iic2 {
+ status = "okay";
+ pinctrl-0 = <&iic2_pins>;
+ pinctrl-names = "default";
+
+ clock-frequency = <100000>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep0>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
+ };
+ };
+ };
+ };
+};
+
+&iic3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&iic3_pins>;
+ status = "okay";
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ wdt {
+ compatible = "dlg,da9063-watchdog";
+ };
+ };
+
+ vdd_dvfs: regulator@68 {
+ compatible = "dlg,da9210";
+ reg = <0x68>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&pci1 {
+ status = "okay";
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+};
+
+&xhci {
+ status = "okay";
+ pinctrl-0 = <&usb2_pins>;
+ pinctrl-names = "default";
+};
+
+&pci2 {
+ status = "okay";
+ pinctrl-0 = <&usb2_pins>;
+ pinctrl-names = "default";
+};
+
+&hsusb {
+ status = "okay";
+ pinctrl-0 = <&hsusb_pins>;
+ pinctrl-names = "default";
+ renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+};
+
+&usbphy {
+ status = "okay";
+};
+
+/* HDMI video input */
+&vin0 {
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ port {
+ vin0ep2: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ bus-width = <24>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ data-active = <1>;
+ };
+ };
+};
+
+/* composite video input */
+&vin1 {
+ pinctrl-0 = <&vin1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin1ep0: endpoint {
+ remote-endpoint = <&adv7180>;
+ bus-width = <8>;
+ };
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src2 &dvc0>;
+ capture = <&ssi1 &src3 &dvc1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Stout board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7790-stout.dts"
+#include "r8a7790-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Stout board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+#include "r8a7790.dtsi"
+
+/ {
+ model = "Stout";
+ compatible = "renesas,stout", "renesas,r8a7790";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7790 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&usb_extal_clk {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a7790 SoC
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7790-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7790";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &iic0;
+ i2c5 = &iic1;
+ i2c6 = &iic2;
+ i2c7 = &iic3;
+ spi0 = &qspi;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ spi3 = &msiof2;
+ spi4 = &msiof3;
+ vin0 = &vin0;
+ vin1 = &vin1;
+ vin2 = &vin2;
+ vin3 = &vin3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "renesas,apmu";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1300000000>;
+ voltage-tolerance = <1>; /* 1% */
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+ power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1300000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <1300000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clock-frequency = <1300000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ capacity-dmips-mhz = <539>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+ next-level-cache = <&L2_CA7>;
+ capacity-dmips-mhz = <539>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+ next-level-cache = <&L2_CA7>;
+ capacity-dmips-mhz = <539>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+ next-level-cache = <&L2_CA7>;
+ capacity-dmips-mhz = <539>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7790_PD_CA15_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA7: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7790_PD_CA7_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
+ apmu@e6151000 {
+ compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ renesas,channels-mask = <0x60>;
+
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ renesas,channels-mask = <0xff>;
+
+ status = "disabled";
+ };
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ iic0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ iic1: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
+
+ iic2: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6520000 0 0x425>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+ <&dmac1 0x69>, <&dmac1 0x6a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
+ iic3: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ mmcif1: mmc@ee220000 {
+ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+ reg = <0 0xee220000 0 0x80>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 305>;
+ dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+ <&dmac1 0xe1>, <&dmac1 0xe2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 305>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7790";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7790";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee120000 {
+ compatible = "renesas,sdhi-r8a7790";
+ reg = <0 0xee120000 0 0x328>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+ <&dmac1 0xc9>, <&dmac1 0xca>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7790";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi3: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7790";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7790",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7790",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7790",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7790",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7790",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7790",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e56000 {
+ compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e56000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7790",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7790",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7790";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7790",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x2000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x2000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 814>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 814>;
+ status = "disabled";
+ };
+
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7790",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+ };
+
+ vsp@fe920000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 130>;
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7790";
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfeb90000 0 0x1c>,
+ <0 0xfeb94000 0 0x1c>;
+ reg-names = "du", "lvds.0", "lvds.1";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+ <&cpg CPG_MOD 725>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ jpu: jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 106>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 106>;
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7790-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7790-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7790-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 205>;
+ dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ <&dmac1 0x41>, <&dmac1 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 205>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c90000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6c90000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 215>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+ <&dmac1 0x45>, <&dmac1 0x46>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 215>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pci1: pci@ee0b0000 {
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0b0000 0 0xc00>,
+ <0 0xee0a0000 0 0x1100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci2: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <2 2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x20800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x21000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7790_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6", "src.5",
+ "src.4", "src.3", "src.2", "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+ reg = <0 0xffc80000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Koelsch board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7791-koelsch.dts"
+#include "r8a7791-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Koelsch board
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ * 2: CN22
+ * 3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
+/dts-v1/;
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Koelsch";
+ compatible = "renesas,koelsch", "renesas,r8a7791";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif1;
+ i2c9 = &gpioi2c1;
+ i2c12 = &i2cexio1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory@200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ keyboard {
+ compatible = "gpio-keys";
+
+ key-1 {
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "SW30";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "SW31";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "SW32";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-d {
+ gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_D>;
+ label = "SW33";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-e {
+ gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_E>;
+ label = "SW34";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-f {
+ gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F>;
+ label = "SW35";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-g {
+ gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_G>;
+ label = "SW36";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led6 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ label = "LED6";
+ };
+ led7 {
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ label = "LED7";
+ };
+ led8 {
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ label = "LED8";
+ };
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi2: regulator-vcc-sdhi2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ rsnd_ak4643: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4643>;
+ clocks = <&audio_clock>;
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ x2_clk: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x13_clk: x13-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ gpioi2c1: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
+ &gpio7 15 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
+ * A fallback to GPIO is provided.
+ */
+ i2cexio1: i2c-12 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c1>, <&gpioi2c1>;
+ i2c-bus-name = "i2c-exio1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
+ <&x13_clk>, <&x2_clk>;
+ clock-names = "du.0", "du.1", "lvds.0",
+ "dclkin.0", "dclkin.1";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ port@1 {
+ lvds_connector: endpoint {
+ };
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ scif1_pins: scif1 {
+ groups = "scif1_data_d";
+ function = "scif1";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq0";
+ function = "intc";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+
+ msiof0_pins: msiof0 {
+ groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
+ "msiof0_tx";
+ function = "msiof0";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ vin0_pins: vin0 {
+ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+ function = "vin0";
+ };
+
+ vin1_pins: vin1 {
+ groups = "vin1_data8", "vin1_clk";
+ function = "vin1";
+ };
+
+ sound_pins: sound {
+ groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a";
+ function = "audio_clk";
+ };
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&cmt0 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpha;
+ spi-cpol;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "user";
+ reg = <0x00080000 0x00580000>;
+ read-only;
+ };
+ partition@600000 {
+ label = "flash";
+ reg = <0x00600000 0x03a00000>;
+ };
+ };
+ };
+};
+
+&msiof0 {
+ pinctrl-0 = <&msiof0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ pmic: pmic@0 {
+ compatible = "renesas,r2a11302ft";
+ reg = <0>;
+ spi-max-frequency = <6000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "i2c-exio1";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+
+ cec_clock: cec-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
+ };
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "renesas,24c02", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ wdt {
+ compatible = "dlg,da9063-watchdog";
+ };
+ };
+
+ vdd_dvfs: regulator@68 {
+ compatible = "dlg,da9210";
+ reg = <0x68>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&pci1 {
+ status = "okay";
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+};
+
+&hsusb {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+ renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_dvfs>;
+};
+
+/* HDMI video input */
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep2: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ bus-width = <24>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ data-active = <1>;
+ };
+ };
+};
+
+/* composite video input */
+&vin1 {
+ status = "okay";
+ pinctrl-0 = <&vin1_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin1ep: endpoint {
+ remote-endpoint = <&adv7180>;
+ bus-width = <8>;
+ };
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src2 &dvc0>;
+ capture = <&ssi1 &src3 &dvc1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Porter board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7791-porter.dts"
+#include "r8a7791-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Porter board
+ *
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * SSI-AK4642
+ *
+ * JP3: 2-1: AK4642
+ * 2-3: ADV7511
+ *
+ * This command is required before playback/capture:
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ */
+
+/dts-v1/;
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Porter";
+ compatible = "renesas,porter", "renesas,r8a7791";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory@200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi2: regulator-vcc-sdhi2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ x3_clk: x3-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ x16_clk: x16-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x14_clk: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&soundcodec>;
+ simple-audio-card,frame-master = <&soundcodec>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ soundcodec: simple-audio-card,codec {
+ sound-dai = <&ak4642>;
+ clocks = <&x14_clk>;
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq0";
+ function = "intc";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ vin0_pins: vin0 {
+ groups = "vin0_data8", "vin0_clk";
+ function = "vin0";
+ };
+
+ can0_pins: can0 {
+ groups = "can0_data";
+ function = "can0";
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ ssi_pins: sound {
+ groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ audio_clk_pins: audio_clk {
+ groups = "audio_clk_a";
+ function = "audio_clk";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader_prg";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "user_prg";
+ reg = <0x00040000 0x00400000>;
+ read-only;
+ };
+ partition@440000 {
+ label = "flash_fs";
+ reg = <0x00440000 0x03bc0000>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ak4642: codec@12 {
+ compatible = "asahi-kasei,ak4642";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin0>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+/* composite video input */
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep: endpoint {
+ remote-endpoint = <&adv7180>;
+ bus-width = <8>;
+ };
+ };
+};
+
+&pci0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pci1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&hsusb {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec {
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
+ <&x3_clk>, <&x16_clk>;
+ clock-names = "du.0", "du.1", "lvds.0",
+ "dclkin.0", "dclkin.1";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&ssi_pins &audio_clk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0>;
+ capture = <&ssi1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7791 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&usb_extal_clk {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a7791 SoC
+ *
+ * Copyright (C) 2013-2015 Renesas Electronics Corporation
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7791-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7791";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ spi0 = &qspi;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ spi3 = &msiof2;
+ vin0 = &vin0;
+ vin1 = &vin1;
+ vin2 = &vin2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "renesas,apmu";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ voltage-tolerance = <1>; /* 1% */
+ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+ power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
+ power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7791_PD_CA15_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
+ };
+
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7791",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ renesas,channels-mask = <0x60>;
+
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ renesas,channels-mask = <0xff>;
+
+ status = "disabled";
+ };
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7791", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ /* The memory map in the User's Manual maps the cores to bus numbers */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@e60b0000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7791";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7791";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7791";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7791";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1106>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1107>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1108>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7791",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7791",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7791",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ adc: adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ reg = <0 0xe6e54000 0 64>;
+ clocks = <&cpg CPG_MOD 901>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 901>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7791",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7791",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7791",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7791";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7791",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x2000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x2000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 814>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 814>;
+ status = "disabled";
+ };
+
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7791",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7791";
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfeb90000 0 0x1c>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 726>;
+ clock-names = "du.0", "du.1", "lvds.0";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ };
+ };
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ jpu: jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 106>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 106>;
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7791-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7791-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7791-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 000>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 205>;
+ dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ <&dmac1 0x41>, <&dmac1 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 205>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xffc80000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7791_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6", "src.5",
+ "src.4", "src.3", "src.2", "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Blanche board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7792-blanche.dts"
+#include "r8a7792-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Blanche board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+#include "r8a7792.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Blanche";
+ compatible = "renesas,blanche", "renesas,r8a7792";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif3;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ d3_3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "D3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ethernet@18000000 {
+ compatible = "smsc,lan89218", "smsc,lan9115";
+ reg = <0 0x18000000 0 0x100>;
+ phy-mode = "mii";
+ interrupt-parent = <&irqc>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ smsc,irq-push-pull;
+ reg-io-width = <4>;
+ vddvario-supply = <&d3_3v>;
+ vdd33a-supply = <&d3_3v>;
+
+ pinctrl-0 = <&lan89218_pins>;
+ pinctrl-names = "default";
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ x1_clk: x1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x2_clk: x2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <65000000>;
+ };
+
+ keyboard {
+ compatible = "gpio-keys";
+
+ key-1 {
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+ };
+ key-2 {
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ };
+ key-3 {
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ };
+ key-4 {
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ };
+ key-a {
+ linux,code = <KEY_A>;
+ label = "SW24";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ };
+ key-b {
+ linux,code = <KEY_B>;
+ label = "SW25";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led17 {
+ gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
+ };
+ led18 {
+ gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
+ };
+ led19 {
+ gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
+ };
+ led20 {
+ gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&can_clk {
+ clock-frequency = <48000000>;
+};
+
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif3_pins: scif3 {
+ groups = "scif3_data";
+ function = "scif3";
+ };
+
+ lan89218_pins: lan89218 {
+ intc {
+ groups = "intc_irq0";
+ function = "intc";
+ };
+ lbsc {
+ groups = "lbsc_ex_cs0";
+ function = "lbsc";
+ };
+ };
+
+ can0_pins: can0 {
+ groups = "can0_data", "can_clk";
+ function = "can0";
+ };
+
+ sdhi0_pins: sdhi0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ };
+
+ du0_pins: du0 {
+ groups = "du0_rgb888", "du0_sync", "du0_disp";
+ function = "du0";
+ };
+
+ du1_pins: du1 {
+ groups = "du1_rgb666", "du1_sync", "du1_disp";
+ function = "du1";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&irqc>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du0_pins &du1_pins>;
+ pinctrl-names = "default";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ port@1 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7792 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the r8a7792 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7792-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7792";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ spi0 = &qspi;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ vin0 = &vin0;
+ vin1 = &vin1;
+ vin2 = &vin2;
+ vin3 = &vin3;
+ vin4 = &vin4;
+ vin5 = &vin5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "renesas,apmu";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
+ power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
+ power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7792_PD_CA15_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7792-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7792-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7792-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7792";
+ reg = <0 0xe6060000 0 0x144>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 29>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 23>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 28>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055100 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055100 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
+
+ gpio7: gpio@e6055200 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055200 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
+ };
+
+ gpio8: gpio@e6055300 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055300 0 0x50>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 256 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 921>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 921>;
+ };
+
+ gpio9: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 288 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ };
+
+ gpio10: gpio@e6055500 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055500 0 0x50>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 320 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 914>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+ };
+
+ gpio11: gpio@e6055600 {
+ compatible = "renesas,gpio-r8a7792",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055600 0 0x50>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 352 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 913>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 913>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7792",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7792",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7792";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ clocks = <&cpg CPG_MOD 314>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ jpu: jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7792",
+ "renesas,rcar-gen2-jpu";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 106>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 106>;
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7792",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* I2C doesn't need pinmux */
+ i2c0: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7792", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7792",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 000>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7792",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7792";
+ reg = <0 0xfeb00000 0 0x40000>;
+ reg-names = "du";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb0: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_rgb1: endpoint {
+ };
+ };
+ };
+ };
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7792",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7792",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7792",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7792",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7792",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a7792",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a7792",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a7792",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7792-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Gose board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7793-gose.dts"
+#include "r8a7793-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Gose board
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ * 2: CN22
+ * 3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
+/dts-v1/;
+#include "r8a7793.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Gose";
+ compatible = "renesas,gose", "renesas,r8a7793";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-1 {
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "SW30";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "SW31";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "SW32";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-d {
+ gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_D>;
+ label = "SW33";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-e {
+ gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_E>;
+ label = "SW34";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-f {
+ gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F>;
+ label = "SW35";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-g {
+ gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_G>;
+ label = "SW36";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led6 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ label = "LED6";
+ };
+ led7 {
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ label = "LED7";
+ };
+ led8 {
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ label = "LED8";
+ };
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi2: regulator-vcc-sdhi2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ rsnd_ak4643: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4643>;
+ clocks = <&audio_clock>;
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ composite-in {
+ compatible = "composite-video-connector";
+
+ port {
+ composite_con_in: endpoint {
+ remote-endpoint = <&adv7180_in>;
+ };
+ };
+ };
+
+ x2_clk: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x13_clk: x13-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
+ <&x13_clk>, <&x2_clk>;
+ clock-names = "du.0", "du.1", "lvds.0",
+ "dclkin.0", "dclkin.1";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ port@1 {
+ lvds_connector: endpoint {
+ };
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ scif1_pins: scif1 {
+ groups = "scif1_data_d";
+ function = "scif1";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq0";
+ function = "intc";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+
+ sound_pins: sound {
+ groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a";
+ function = "audio_clk";
+ };
+
+ vin0_pins: vin0 {
+ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+ function = "vin0";
+ };
+
+ vin1_pins: vin1 {
+ groups = "vin1_data8", "vin1_clk";
+ function = "vin1";
+ };
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&cmt0 {
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "user";
+ reg = <0x00040000 0x00400000>;
+ read-only;
+ };
+ partition@440000 {
+ label = "flash";
+ reg = <0x00440000 0x03bc0000>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180cp";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7180_in: endpoint {
+ remote-endpoint = <&composite_con_in>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ adv7180_out: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
+ };
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "renesas,r1ex24002", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ wdt {
+ compatible = "dlg,da9063-watchdog";
+ };
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src2 &dvc0>;
+ capture = <&ssi1 &src3 &dvc1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+/* HDMI video input */
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep2: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ bus-width = <24>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ data-active = <1>;
+ };
+ };
+};
+
+/* composite video input */
+&vin1 {
+ pinctrl-0 = <&vin1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin1ep: endpoint {
+ remote-endpoint = <&adv7180_out>;
+ bus-width = <8>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7793 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&usb_extal_clk {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a7793 SoC
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7793-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7793-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7793";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ spi0 = &qspi;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "renesas,apmu";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ voltage-tolerance = <1>; /* 1% */
+ clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+ power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
+ power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7793_PD_CA15_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
+ };
+
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7793",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ renesas,channels-mask = <0x60>;
+
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ renesas,channels-mask = <0xff>;
+
+ status = "disabled";
+ };
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7793", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ /* The memory map in the User's Manual maps the cores to bus numbers */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@e60b0000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7793";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1106>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1107>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1108>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7793",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7793",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7793",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7793",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7793",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7793",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7793";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7793";
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfeb90000 0 0x1c>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 726>;
+ clock-names = "du.0", "du.1", "lvds.0";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ };
+ };
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* Special CPG clocks */
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7793-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7793-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7793-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xffc80000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7793_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6", "src.5",
+ "src.4", "src.3", "src.2", "src.1", "src.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Alt board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7794-alt.dts"
+#include "r8a7794-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the Alt board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Alt";
+ compatible = "renesas,alt", "renesas,r8a7794";
+
+ aliases {
+ serial0 = &scif2;
+ i2c10 = &gpioi2c4;
+ i2c12 = &i2cexio4;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ d3_3v: regulator-d3-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "D3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ x2_clk: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x13_clk: x13-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ gpioi2c4: i2c-10 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
+ &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
+ * A fallback to GPIO is provided.
+ */
+ i2cexio4: i2c-14 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c4>, <&gpioi2c4>;
+ i2c-bus-name = "i2c-exio4";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ <&x13_clk>, <&x2_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ du_pins: du {
+ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+ function = "du1";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data";
+ function = "scif2";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq8";
+ function = "intc";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ i2c4_pins: i2c4 {
+ groups = "i2c4";
+ function = "i2c4";
+ };
+
+ vin0_pins: vin0 {
+ groups = "vin0_data8", "vin0_clk";
+ function = "vin0";
+ };
+
+ mmcif0_pins: mmcif0 {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
+ };
+};
+
+&cmt0 {
+ status = "okay";
+};
+
+&pfc {
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&mmcif0 {
+ pinctrl-0 = <&mmcif0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&d3_3v>;
+ vqmmc-supply = <&d3_3v>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin0>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "i2c-exio4";
+};
+
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep: endpoint {
+ remote-endpoint = <&adv7180>;
+ bus-width = <8>;
+ };
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "system";
+ reg = <0x00040000 0x00040000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "user";
+ reg = <0x00080000 0x03f80000>;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Silk board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7794-silk.dts"
+#include "r8a7794-u-boot.dtsi"
--- /dev/null
+/*
+ * Device Tree Source for the SILK board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014-2015 Renesas Solutions Corp.
+ * Copyright (C) 2014-2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 2-1: AK4643
+ * 2-3: ADV7511
+ *
+ * This command is required before playback/capture:
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "SILK";
+ compatible = "renesas,silk", "renesas,r8a7794";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ d3_3v: regulator-d3-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "D3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ x2_clk: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ x3_clk: x3-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x9_clk: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&soundcodec>;
+ simple-audio-card,frame-master = <&soundcodec>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ soundcodec: simple-audio-card,codec {
+ sound-dai = <&ak4643>;
+ clocks = <&x9_clk>;
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ scif2_pins: scif2 {
+ groups = "scif2_data";
+ function = "scif2";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq8";
+ function = "intc";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ mmcif0_pins: mmcif0 {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+
+ vin0_pins: vin0 {
+ groups = "vin0_data8", "vin0_clk";
+ function = "vin0";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ du0_pins: du0 {
+ groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
+ function = "du0";
+ };
+
+ du1_pins: du1 {
+ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+ function = "du1";
+ };
+
+ ssi_pins: sound {
+ groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ audio_clk_pins: audio_clk {
+ groups = "audio_clkc";
+ function = "audio_clk";
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin0>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&mmcif0 {
+ pinctrl-0 = <&mmcif0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&d3_3v>;
+ vqmmc-supply = <&d3_3v>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "user";
+ reg = <0x00040000 0x00400000>;
+ read-only;
+ };
+ partition@440000 {
+ label = "flash";
+ reg = <0x00440000 0x03bc0000>;
+ };
+ };
+ };
+};
+
+/* composite video input */
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep: endpoint {
+ remote-endpoint = <&adv7180>;
+ bus-width = <8>;
+ };
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&pci1 {
+ status = "okay";
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&du {
+ pinctrl-0 = <&du0_pins &du1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ <&x2_clk>, <&x3_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ port@1 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&ssi_pins &audio_clk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0>;
+ capture = <&ssi1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7794 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&usb_extal_clk {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a7794 SoC
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014 Ulrich Hecht
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7794-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7794";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ spi0 = &qspi;
+ vin0 = &vin0;
+ vin1 = &vin1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
+ power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
+ power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA7: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7794_PD_CA7_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 28>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,cmt-48-gen2";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ renesas,channels-mask = <0x60>;
+
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,cmt-48-gen2";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ renesas,channels-mask = <0xff>;
+
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7794", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7794";
+ reg = <0 0xe6060000 0 0x11c>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+ "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1106>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1107>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1108>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7794",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7794",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7794",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7794",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7794",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7794",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7794";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7794",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* The memory map in the User's Manual maps the cores to bus numbers */
+ i2c0: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@e6500000 {
+ compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@e6510000 {
+ compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7794";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7794";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7794";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
+
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7794",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7794";
+ reg = <0 0xfeb00000 0 0x40000>;
+ reg-names = "du";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb0: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_rgb1: endpoint {
+ };
+ };
+ };
+ };
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed
+ * frequency clocks by default. Boards that provide audio
+ * clocks should override them.
+ */
+ audio_clka: audio_clka {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clkb: audio_clkb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clkc: audio_clkc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7794-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7794-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7794-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7794",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+ <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+ <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+ <&cpg CPG_CORE R8A7794_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.6", "src.5", "src.4", "src.3", "src.2",
+ "src.1",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma0 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma0 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src-0 {
+ status = "disabled";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma0 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma0 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma0 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma0 0x02>,
+ <&audma0 0x15>, <&audma0 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma0 0x04>,
+ <&audma0 0x49>, <&audma0 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma0 0x06>,
+ <&audma0 0x63>, <&audma0 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma0 0x08>,
+ <&audma0 0x6f>, <&audma0 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma0 0x0a>,
+ <&audma0 0x71>, <&audma0 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+ <&audma0 0x73>, <&audma0 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+ <&audma0 0x75>, <&audma0 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma0 0x10>,
+ <&audma0 0x79>, <&audma0 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma0 0x12>,
+ <&audma0 0x7b>, <&audma0 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma0 0x14>,
+ <&audma0 0x7d>, <&audma0 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the ULCB board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7795-h3ulcb.dts"
+#include "r8a7795-u-boot.dtsi"
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795.dtsi"
#include "ulcb.dtsi"
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&versaclock5 3>,
+ <&versaclock5 4>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Salvator-X board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7795-salvator-x.dts"
+#include "r8a7795-u-boot.dtsi"
*
* Copyright (C) 2015 Renesas Electronics Corp.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795.dtsi"
#include "salvator-x.dtsi"
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7795 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
*
* Copyright (C) 2015 Renesas Electronics Corp.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
+
/ {
compatible = "renesas,r8a7795";
#address-cells = <2>;
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
/*
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
};
};
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ renesas,bonding = <&drif01>;
+ status = "disabled";
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ renesas,bonding = <&drif00>;
+ status = "disabled";
+ };
+
+ drif10: rif@e6f60000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f60000 0 0x64>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 513>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 513>;
+ renesas,bonding = <&drif11>;
+ status = "disabled";
+ };
+
+ drif11: rif@e6f70000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f70000 0 0x64>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 512>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 512>;
+ renesas,bonding = <&drif10>;
+ status = "disabled";
+ };
+
+ drif20: rif@e6f80000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f80000 0 0x64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 511>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 511>;
+ renesas,bonding = <&drif21>;
+ status = "disabled";
+ };
+
+ drif21: rif@e6f90000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f90000 0 0x64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 510>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 510>;
+ renesas,bonding = <&drif20>;
+ status = "disabled";
+ };
+
+ drif30: rif@e6fa0000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fa0000 0 0x64>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 509>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 509>;
+ renesas,bonding = <&drif31>;
+ status = "disabled";
+ };
+
+ drif31: rif@e6fb0000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fb0000 0 0x64>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 508>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 508>;
+ renesas,bonding = <&drif30>;
+ status = "disabled";
+ };
+
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a7795",
"renesas,rcar-gen3-hscif",
status = "disabled";
};
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+ <&dmac2 0x41>, <&dmac2 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+ <&dmac2 0x43>, <&dmac2 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-scif", "renesas,scif";
};
sata: sata@ee300000 {
- compatible = "renesas,sata-r8a7795";
+ compatible = "renesas,sata-r8a7795",
+ "renesas,rcar-gen3-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
dma-channels = <2>;
};
+ usb_dmac2: dma-controller@e6460000 {
+ compatible = "renesas,r8a7795-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe6460000 0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 326>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 326>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac3: dma-controller@e6470000 {
+ compatible = "renesas,r8a7795-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe6470000 0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 329>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7795";
reg = <0 0xee100000 0 0x2000>;
status = "disabled";
};
+ usb2_phy3: usb-phy@ee0e0200 {
+ compatible = "renesas,usb2-phy-r8a7795",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee0e0200 0 0x700>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 700>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 700>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
+ companion = <&ohci0>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ companion = <&ohci1>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
clocks = <&cpg CPG_MOD 701>;
phys = <&usb2_phy2>;
phy-names = "usb";
+ companion = <&ohci2>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 701>;
status = "disabled";
};
+ ehci3: usb@ee0e0100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee0e0100 0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 700>;
+ phys = <&usb2_phy3>;
+ phy-names = "usb";
+ companion = <&ohci3>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 700>;
+ status = "disabled";
+ };
+
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
status = "disabled";
};
+ ohci3: usb@ee0e0000 {
+ compatible = "generic-ohci";
+ reg = <0 0xee0e0000 0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 700>;
+ phys = <&usb2_phy3>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 700>;
+ status = "disabled";
+ };
+
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs";
status = "disabled";
};
+ hsusb3: usb@e659c000 {
+ compatible = "renesas,usbhs-r8a7795",
+ "renesas,rcar-gen3-usbhs";
+ reg = <0 0xe659c000 0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 705>;
+ dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
+ <&usb_dmac3 0>, <&usb_dmac3 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <&usb2_phy3>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 705>;
+ status = "disabled";
+ };
+
pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a7795",
"renesas,pcie-rcar-gen3";
status = "disabled";
};
+ imr-lx4@fe860000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe860000 0 0x2000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 823>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 823>;
+ };
+
+ imr-lx4@fe870000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe870000 0 0x2000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 822>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 822>;
+ };
+
+ imr-lx4@fe880000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe880000 0 0x2000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 821>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 821>;
+ };
+
+ imr-lx4@fe890000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe890000 0 0x2000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 820>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 820>;
+ };
+
vspbc: vsp@fe920000 {
compatible = "renesas,vsp2";
reg = <0 0xfe920000 0 0x8000>;
};
du: display@feb00000 {
+ compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
status = "disabled";
ports {
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the ULCB board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7796-m3ulcb.dts"
+#include "r8a7796-u-boot.dtsi"
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
-
/dts-v1/;
#include "r8a7796.dtsi"
#include "ulcb.dtsi"
reg = <0x6 0x00000000 0x0 0x40000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&versaclock5 3>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2";
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Salvator-X board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a7796-salvator-x.dts"
+#include "r8a7796-u-boot.dtsi"
*
* Copyright (C) 2016 Renesas Electronics Corp.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
-
/dts-v1/;
#include "r8a7796.dtsi"
#include "salvator-x.dtsi"
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&x21_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2";
+};
+
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A7796 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
*
* Copyright (C) 2016 Renesas Electronics Corp.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>
+#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
+
/ {
compatible = "renesas,r8a7796";
#address-cells = <2>;
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
/*
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
};
};
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ renesas,bonding = <&drif01>;
+ status = "disabled";
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ renesas,bonding = <&drif00>;
+ status = "disabled";
+ };
+
+ drif10: rif@e6f60000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f60000 0 0x64>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 513>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 513>;
+ renesas,bonding = <&drif11>;
+ status = "disabled";
+ };
+
+ drif11: rif@e6f70000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f70000 0 0x64>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 512>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 512>;
+ renesas,bonding = <&drif10>;
+ status = "disabled";
+ };
+
+ drif20: rif@e6f80000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f80000 0 0x64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 511>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 511>;
+ renesas,bonding = <&drif21>;
+ status = "disabled";
+ };
+
+ drif21: rif@e6f90000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f90000 0 0x64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 510>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 510>;
+ renesas,bonding = <&drif20>;
+ status = "disabled";
+ };
+
+ drif30: rif@e6fa0000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fa0000 0 0x64>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 509>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 509>;
+ renesas,bonding = <&drif31>;
+ status = "disabled";
+ };
+
+ drif31: rif@e6fb0000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fb0000 0 0x64>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 508>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 508>;
+ renesas,bonding = <&drif30>;
+ status = "disabled";
+ };
+
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7796",
"renesas,etheravb-rcar-gen3";
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx";
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx";
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
dma-channels = <16>;
};
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7796-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7796-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
};
xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a7796", "renesas,rcar-gen3-xhci";
+ compatible = "renesas,xhci-r8a7796",
+ "renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
};
ohci0: usb@ee080000 {
- /* placeholder */
+ compatible = "generic-ohci";
+ reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
};
ehci0: usb@ee080100 {
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
+ companion= <&ohci0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ohci1: usb@ee0a0000 {
- /* placeholder */
+ compatible = "generic-ohci";
+ reg = <0 0xee0a0000 0 0x100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 702>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
+ status = "disabled";
};
ehci1: usb@ee0a0100 {
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ companion= <&ohci1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
/* placeholder */
};
+ fcpf0: fcp@fe950000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe950000 0 0x200>;
+ clocks = <&cpg CPG_MOD 615>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 615>;
+ };
+
+ vspb: vsp@fe960000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 626>;
+
+ renesas,fcp = <&fcpvb0>;
+ };
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 607>;
+ };
+
+ vspi0: vsp@fe9a0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9a0000 0 0x8000>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 631>;
+
+ renesas,fcp = <&fcpvi0>;
+ };
+
+ fcpvi0: fcp@fe9af000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9af000 0 0x200>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 611>;
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x4000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x4000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ };
+
+ vspd2: vsp@fea30000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea30000 0 0x4000>;
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 621>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 621>;
+
+ renesas,fcp = <&fcpvd2>;
+ };
+
+ fcpvd2: fcp@fea37000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea37000 0 0x200>;
+ clocks = <&cpg CPG_MOD 601>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 601>;
+ };
+
+ hdmi0: hdmi@fead0000 {
+ compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0 0xfead0000 0 0x10000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 729>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
du: display@feb00000 {
- /* placeholder */
+ compatible = "renesas,du-r8a7796";
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfeb90000 0 0x14>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 727>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0";
+ status = "disabled";
+
+ vsps = <&vspd0 &vspd1 &vspd2>;
ports {
#address-cells = <1>;
du_out_rgb: endpoint {
};
};
+ port@1 {
+ reg = <1>;
+ du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds0: endpoint {
+ };
+ };
};
};
+
+ imr-lx4@fe860000 {
+ compatible = "renesas,r8a7796-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe860000 0 0x2000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 823>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 823>;
+ };
+
+ imr-lx4@fe870000 {
+ compatible = "renesas,r8a7796-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe870000 0 0x2000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 822>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 822>;
+ };
};
};
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Eagle board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a77970-eagle.dts"
+#include "r8a77970-u-boot.dtsi"
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77970 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/interrupt-controller/irq.h>
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
/* External SCIF clock - to be overridden by boards that provide it */
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
dmac1: dma-controller@e7300000 {
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot for the Draak board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a77995-draak.dts"
+#include "r8a77995-u-boot.dtsi"
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77995 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
- u-boot,dm-pre-reloc;
};
scif_clk: scif {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
- u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
--- /dev/null
+/*
+ * Device Tree Source extras for U-Boot on RCar Gen3
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cpg {
+ u-boot,dm-pre-reloc;
+};
+
+&extal_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&prr {
+ u-boot,dm-pre-reloc;
+};
pwm0: pwm0@20050000 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
pwm1: pwm1@20050010 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
pwm2: pwm2@20050020 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
pwm3: pwm3@20050030 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
- <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
- assigned-clock-rates = <0>, <0>,
- <594000000>, <400000000>,
+ assigned-clock-rates = <594000000>, <400000000>,
<500000000>, <300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
<75000000>;
- assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
};
grf: syscon@ff770000 {
stdout-path = &uart2;
};
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&saradc {
status = "okay";
};
+&gmac2io {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
status = "disabled";
};
+ gmac2io: ethernet@ff540000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff540000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
+ <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
+ <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
+ <&cru PCLK_MAC2IO>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_GMAC2IO_A>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
assigned-clock-parents = <&clkin_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x10>;
- rx_delay = <0x10>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
status = "okay";
};
brightness-levels = <256 128 64 16 8 4 0>;
default-brightness-level = <6>;
+ power-supply = <®_12v>;
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
};
regulator-always-on;
};
+ reg_12v: regulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
rsnd_ak4613: sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
status = "okay";
phy0: ethernet-phy@0 {
remote-endpoint = <&adv7123_in>;
};
};
- port@3 {
- lvds_connector: endpoint {
- };
- };
};
};
clocks = <&qspi_clk>;
ext-decoder = <0>; /* external decoder */
num-cs = <4>;
- fifo-depth = <128>;
- sram-size = <128>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
bus-num = <2>;
status = "disabled";
};
clocks = <&l4_main_clk>;
ext-decoder = <0>; /* external decoder */
num-chipselect = <4>;
- fifo-depth = <128>;
- sram-size = <512>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
bus-num = <2>;
status = "disabled";
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
flash1: n25q00@1 {
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- read-delay = <4>; /* delay value in read data capture register */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ pin-controller {
+ u-boot,dm-pre-reloc;
+ };
+
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+ st,syscfg = <&syscfg>;
+ pinctrl-0 = <&fmc_pins_d32>;
+ pinctrl-names = "default";
+ st,mem_remap = <4>;
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Memory configuration from sdram
+ * MICRON MT48LC4M32B2B5-7
+ */
+ bank0: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_9
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_2
+ TXSR_6
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2
+ TRCD_2>;
+ st,sdram-refcount = < 2812 >;
+ };
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+ u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ usart1_pins_a: usart1@0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fmc_pins_d32: fmc_d32@0 {
+ u-boot,dm-pre-reloc;
+ pins
+ {
+ pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
+ <STM32_PINMUX('I', 9, AF12)>, /* D30 */
+ <STM32_PINMUX('I', 7, AF12)>, /* D29 */
+ <STM32_PINMUX('I', 6, AF12)>, /* D28 */
+ <STM32_PINMUX('I', 3, AF12)>, /* D27 */
+ <STM32_PINMUX('I', 2, AF12)>, /* D26 */
+ <STM32_PINMUX('I', 1, AF12)>, /* D25 */
+ <STM32_PINMUX('I', 0, AF12)>, /* D24 */
+ <STM32_PINMUX('H',15, AF12)>, /* D23 */
+ <STM32_PINMUX('H',14, AF12)>, /* D22 */
+ <STM32_PINMUX('H',13, AF12)>, /* D21 */
+ <STM32_PINMUX('H',12, AF12)>, /* D20 */
+ <STM32_PINMUX('H',11, AF12)>, /* D19 */
+ <STM32_PINMUX('H',10, AF12)>, /* D18 */
+ <STM32_PINMUX('H', 9, AF12)>, /* D17 */
+ <STM32_PINMUX('H', 8, AF12)>, /* D16 */
+
+ <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D09 */
+ <STM32_PINMUX('E',11, AF12)>, /* D08 */
+ <STM32_PINMUX('E',10, AF12)>, /* D07 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+ <STM32_PINMUX('D',15, AF12)>, /* D01 */
+ <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+ <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
+ <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
+
+ <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */
+ <STM32_PINMUX('G', 3, AF12)>, /* A13 */
+ <STM32_PINMUX('G', 2, AF12)>, /* A12 */
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A09 */
+ <STM32_PINMUX('F',14, AF12)>, /* A08 */
+ <STM32_PINMUX('F',13, AF12)>, /* A07 */
+ <STM32_PINMUX('F',12, AF12)>, /* A06 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+ <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+ <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+ slew-rate = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "STMicroelectronics STM32429i-EVAL board";
+ compatible = "st,stm32429i-eval", "st,stm32f429";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x00000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ dma-ranges = <0xc0000000 0x0 0x10000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_vref: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vref";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ green {
+ gpios = <&gpiog 6 1>;
+ linux,default-trigger = "heartbeat";
+ };
+ orange {
+ gpios = <&gpiog 7 1>;
+ };
+ red {
+ gpios = <&gpiog 10 1>;
+ };
+ blue {
+ gpios = <&gpiog 12 1>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "Wake up";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpioa 0 0>;
+ };
+ button@1 {
+ label = "Tamper";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioc 13 0>;
+ };
+ };
+
+ usbotg_hs_phy: usbphy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
+ clock-names = "main_clk";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "ampire,am-480272h3tmqw-t01h";
+ status = "okay";
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc3_in8_pin>;
+ vref-supply = <®_vref>;
+ status = "okay";
+ adc3: adc@200 {
+ st,adc-channels = <8>;
+ status = "okay";
+ };
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&crc {
+ status = "okay";
+};
+
+&dcmi {
+ status = "okay";
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&ov2640_0>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ov2640: camera@30 {
+ compatible = "ovti,ov2640";
+ reg = <0x30>;
+ resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xvclk";
+ status = "okay";
+
+ port {
+ ov2640_0: endpoint {
+ remote-endpoint = <&dcmi_0>;
+ };
+ };
+ };
+
+ stmpe1600: stmpe1600@42 {
+ compatible = "st,stmpe1600";
+ reg = <0x42>;
+ interrupts = <8 3>;
+ interrupt-parent = <&gpioi>;
+ interrupt-controller;
+ wakeup-source;
+
+ stmpegpio: stmpe_gpio {
+ compatible = "st,stmpe-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
+
+&iwdg {
+ status = "okay";
+ timeout-sec = <32>;
+};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <<dc_pins>;
+ pinctrl-names = "default";
+ dma-ranges;
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
+&mac {
+ status = "okay";
+ pinctrl-0 = <ðernet_mii>;
+ pinctrl-names = "default";
+ phy-mode = "mii";
+ phy-handle = <&phy1>;
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
+&timers1 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "host";
+ phys = <&usbotg_hs_phy>;
+ phy-names = "usb2-phy";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
&pwrcfg {
u-boot,dm-pre-reloc;
};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
compatible = "st,stm32-dwmac";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
+ <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
+ <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
snps,pbl = <8>;
reg = <0x80203000 0x100>,
<0x40000000 0x1000000>;
clocks = <3750000>;
- sram-size = <256>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x40000000>;
status = "okay";
flash0: n25q32@0 {
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
- tshsl-ns = <50>;
- tsd2d-ns = <50>;
- tchsh-ns = <4>;
- tslch-ns = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
};
};
};
clock-frequency = <11289600>;
};
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ };
+ };
+ };
+
keyboard {
compatible = "gpio-keys";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
+
+ x23_clk: x23-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&audio_clk_a {
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
status = "okay";
phy0: ethernet-phy@0 {
clock-frequency = <32768>;
};
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+};
+
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
};
};
+&i2c4 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ versaclock5: clock-generator@6a {
+ compatible = "idt,5p49v5925";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ clocks = <&x23_clk>;
+ clock-names = "xin";
+ };
+};
+
&i2c_dvfs {
status = "okay";
};
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x48060100
-#define OMAP_HSMMC2_BASE 0x481D8100
+#define OMAP_HSMMC1_BASE 0x48060000
+#define OMAP_HSMMC2_BASE 0x481D8000
#if defined(CONFIG_TI814X)
#undef MMC_CLOCK_REFERENCE
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
+#endif
#ifdef CONFIG_SYS_HAS_SERDES
/* Get the volt of SVDD in unit mV */
int get_serdes_volt(void);
/* The target volt of SVDD in unit mV */
int setup_serdes_volt(u32 svdd);
#endif
-#endif
#endif /* __FSL_SERDES_H__ */
u32 gpporcr3;
u32 gpporcr4;
u8 res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
+#if defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#else
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
+#endif
u32 dcfg_fusesr; /* Fuse status register */
u8 res_064[0x70-0x64];
u32 devdisr; /* Device disable control 1 */
u32 ip_rev2; /* 0xbfc */
};
+struct ccsr_serdes {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+ u32 pllcr0; /* PLL Control Register 0 */
+ u32 pllcr1; /* PLL Control Register 1 */
+ u32 pllcr2; /* PLL Control Register 2 */
+ u32 pllcr3; /* PLL Control Register 3 */
+ u32 pllcr4; /* PLL Control Register 4 */
+ u32 pllcr5; /* PLL Control Register 5 */
+ u8 res[0x20 - 0x1c];
+ } bank[2];
+ u8 res1[0x90 - 0x40];
+ u32 srdstcalcr; /* TX Calibration Control */
+ u32 srdstcalcr1; /* TX Calibration Control1 */
+ u8 res2[0xa0 - 0x98];
+ u32 srdsrcalcr; /* RX Calibration Control */
+ u32 srdsrcalcr1; /* RX Calibration Control1 */
+ u8 res3[0xb0 - 0xa8];
+ u32 srdsgr0; /* General Register 0 */
+ u8 res4[0x800 - 0xb4];
+ struct serdes_lane {
+ u32 gcr0; /* General Control Register 0 */
+ u32 gcr1; /* General Control Register 1 */
+ u32 gcr2; /* General Control Register 2 */
+ u32 ssc0; /* Speed Switch Control 0 */
+ u32 rec0; /* Receive Equalization Control 0 */
+ u32 rec1; /* Receive Equalization Control 1 */
+ u32 tec0; /* Transmit Equalization Control 0 */
+ u32 ssc1; /* Speed Switch Control 1 */
+ u8 res1[0x840 - 0x820];
+ } lane[8];
+ u8 res5[0x19fc - 0xa00];
+};
+
#endif /*__ASSEMBLY__*/
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
+int get_core_volt_from_fuse(void);
#elif defined(CONFIG_FSL_LSCH2)
void fsl_lsch2_early_init_f(void);
int setup_chip_volt(void);
#define KWSPI_TXLSBF (1 << 13)
#define KWSPI_RXLSBF (1 << 14)
+/* Timing Parameters 1 Register */
+#define KW_SPI_TMISO_SAMPLE_OFFSET 6
+#define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET)
+#define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET)
+#define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET)
+
#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x4809C100
-#define OMAP_HSMMC2_BASE 0x480B4100
-#define OMAP_HSMMC3_BASE 0x480AD100
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x4809C100
-#define OMAP_HSMMC2_BASE 0x480B4100
-#define OMAP_HSMMC3_BASE 0x480AD100
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */
#define NMIN_DSP 0x460
#define RSTOUTN 0x464
+#define MCAN_SEL_ALT_MASK 0x6000
+#define MCAN_SEL 0x2000
+
#endif /* _MUX_DRA7XX_H_ */
#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
+#define DRA762_ABZ_PACKAGE 0x2
+#define DRA762_ACD_PACKAGE 0x3
+
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
u32 cortex_rev(void);
void save_omap_boot_params(void);
void init_omap_revision(void);
+void init_package_revision(void);
void do_io_settings(void);
void sri2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
CLK_SARADC_DIV_CON_WIDTH = 8,
/* CLKSEL43_CON */
+ GMAC_DIV_CON_SHIFT = 0x0,
+ GMAC_DIV_CON_MASK = GENMASK(4, 0),
+ GMAC_PLL_SHIFT = 6,
+ GMAC_PLL_MASK = GENMASK(7, 6),
+ GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
+ GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
+ GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
GMAC_MUX_SEL_EXTCLK = BIT(8),
/* CLKSEL51_CON */
unsigned int busdmac_con[4];
};
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A7_SHIFT = 14,
- GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
- GPIO0A7_GPIO = 0,
- GPIO0A7_I2C3_SDA,
- GPIO0A7_HDMI_DDCSDA,
-
- GPIO0A6_SHIFT = 12,
- GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
- GPIO0A6_GPIO = 0,
- GPIO0A6_I2C3_SCL,
- GPIO0A6_HDMI_DDCSCL,
-
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO = 0,
- GPIO0A3_I2C1_SDA,
- GPIO0A3_SDIO_CMD,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO = 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO = 0,
- GPIO0A1_I2C0_SDA,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO = 0,
- GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B7_SHIFT = 14,
- GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
- GPIO0B7_GPIO = 0,
- GPIO0B7_HDMI_HDP,
-
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO = 0,
- GPIO0B6_I2S_SDI,
- GPIO0B6_SPI_CSN0,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO = 0,
- GPIO0B5_I2S_SDO,
- GPIO0B5_SPI_RXD,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO = 0,
- GPIO0B3_I2S1_LRCKRX,
- GPIO0B3_SPI_TXD,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO = 0,
- GPIO0B1_I2S_SCLK,
- GPIO0B1_SPI_CLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK = 3,
- GPIO0B0_GPIO = 0,
- GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO = 0,
- GPIO0C4_HDMI_CECSDA,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO = 0,
- GPIO0C1_UART0_RSTN,
- GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDIO_PWREN,
- GPIO0D6_PWM11,
-
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO = 0,
- GPIO0D4_PWM2,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO = 0,
- GPIO0D3_PWM1,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO = 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK = 1,
- GPIO1A7_GPIO = 0,
- GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_SDMMC_CMD,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_SDMMC_PWREN,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_SPI_CSN1,
- GPIO1B4_PWM12,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_UART1_RSTN,
- GPIO1B3_PWM13,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART1_SIN,
- GPIO1B2_UART21_SIN,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART1_SOUT,
- GPIO1B1_UART21_SOUT,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_NAND_CS3,
- GPIO1C7_EMMC_RSTNOUT,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_NAND_CS2,
- GPIO1C6_EMMC_CMD,
-
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_SDMMC_D3,
- GPIO1C5_JTAG_TMS,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_SDMMC_D2,
- GPIO1C4_JTAG_TCK,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_SDMMC_D1,
- GPIO1C3_UART2_SIN,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
- GPIO1C2_GPIO = 0,
- GPIO1C2_SDMMC_D0,
- GPIO1C2_UART2_SOUT,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_SDMMC_DETN,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
- GPIO1C0_GPIO = 0,
- GPIO1C0_SDMMC_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_NAND_D7,
- GPIO1D7_EMMC_D7,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_NAND_D6,
- GPIO1D6_EMMC_D6,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_NAND_D5,
- GPIO1D5_EMMC_D5,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_NAND_D4,
- GPIO1D4_EMMC_D4,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_NAND_D3,
- GPIO1D3_EMMC_D3,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_NAND_D2,
- GPIO1D2_EMMC_D2,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_NAND_D1,
- GPIO1D1_EMMC_D1,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
- GPIO1D0_GPIO = 0,
- GPIO1D0_NAND_D0,
- GPIO1D0_EMMC_D0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_NAND_DQS,
- GPIO2A7_EMMC_CLKOUT,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_NAND_WP,
- GPIO2A5_EMMC_PWREN,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_NAND_RDY,
- GPIO2A4_EMMC_CMD,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_NAND_RDN,
- GPIO2A4_SPI1_CSN1,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_NAND_WRN,
- GPIO2A4_SPI1_CSN0,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_NAND_CLE,
- GPIO2A1_SPI1_TXD,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_NAND_ALE,
- GPIO2A0_SPI1_RXD,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_GMAC_RXER,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_GMAC_CLK,
- GPIO2B6_MAC_LINK,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_GMAC_TXEN,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_GMAC_MDIO,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_GMAC_RXCLK,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_GMAC_CRS,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_GMAC_TXCLK,
-
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_GMAC_RXDV,
- GPIO2B0_MAC_SPEED_IOUT,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
- GPIO2C7_SHIFT = 14,
- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
- GPIO2C7_GPIO = 0,
- GPIO2C7_GMAC_TXD3,
-
- GPIO2C6_SHIFT = 12,
- GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
- GPIO2C6_GPIO = 0,
- GPIO2C6_GMAC_TXD2,
-
- GPIO2C5_SHIFT = 10,
- GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
- GPIO2C5_GPIO = 0,
- GPIO2C5_I2C2_SCL,
- GPIO2C5_GMAC_RXD2,
-
- GPIO2C4_SHIFT = 8,
- GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
- GPIO2C4_GPIO = 0,
- GPIO2C4_I2C2_SDA,
- GPIO2C4_GMAC_RXD3,
-
- GPIO2C3_SHIFT = 6,
- GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
- GPIO2C3_GPIO = 0,
- GPIO2C3_GMAC_TXD0,
-
- GPIO2C2_SHIFT = 4,
- GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
- GPIO2C2_GPIO = 0,
- GPIO2C2_GMAC_TXD1,
-
- GPIO2C1_SHIFT = 2,
- GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
- GPIO2C1_GPIO = 0,
- GPIO2C1_GMAC_RXD0,
-
- GPIO2C0_SHIFT = 0,
- GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
- GPIO2C0_GPIO = 0,
- GPIO2C0_GMAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_GMAC_MDC,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_GMAC_COL,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_DRV_VBUS1,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_PWM10,
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
- GPIO3C1_GPIO = 0,
- GPIO3C1_DRV_VBUS,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
- GPIO3D2_GPIO = 0,
- GPIO3D2_PWM3,
-};
-
-/* GRF_CON_IOMUX */
-enum {
- CON_IOMUX_GMAC_SHIFT = 15,
- CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
- CON_IOMUX_UART1SEL_SHIFT = 11,
- CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
- CON_IOMUX_UART2SEL_SHIFT = 8,
- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
- CON_IOMUX_UART2SEL_2 = 0,
- CON_IOMUX_UART2SEL_21,
- CON_IOMUX_EMMCSEL_SHIFT = 7,
- CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
- CON_IOMUX_PWM3SEL_SHIFT = 3,
- CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
- CON_IOMUX_PWM2SEL_SHIFT = 2,
- CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
- CON_IOMUX_PWM1SEL_SHIFT = 1,
- CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
- CON_IOMUX_PWM0SEL_SHIFT = 0,
- CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
-};
-
/* GRF_MACPHY_CON0 */
enum {
MACPHY_CFG_ENABLE_SHIFT = 0,
};
check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
-enum {
- /* GPIO0A_IOMUX */
- GPIO0A5_SEL_SHIFT = 10,
- GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
- GPIO0A5_I2C3_SCL = 2,
-
- GPIO0A6_SEL_SHIFT = 12,
- GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
- GPIO0A6_I2C3_SDA = 2,
-
- GPIO0A7_SEL_SHIFT = 14,
- GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
- GPIO0A7_EMMC_DATA0 = 2,
-
- /* GPIO0D_IOMUX*/
- GPIO0D6_SEL_SHIFT = 12,
- GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDMMC0_PWRENM1 = 3,
-
- /* GPIO1A_IOMUX */
- GPIO1A0_SEL_SHIFT = 0,
- GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
-
- /* GPIO2A_IOMUX */
- GPIO2A0_SEL_SHIFT = 0,
- GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
- GPIO2A0_UART2_TX_M1 = 1,
-
- GPIO2A1_SEL_SHIFT = 2,
- GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
- GPIO2A1_UART2_RX_M1 = 1,
-
- GPIO2A2_SEL_SHIFT = 4,
- GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
- GPIO2A2_PWM_IR = 1,
-
- GPIO2A4_SEL_SHIFT = 8,
- GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
- GPIO2A4_PWM_0 = 1,
- GPIO2A4_I2C1_SDA,
-
- GPIO2A5_SEL_SHIFT = 10,
- GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
- GPIO2A5_PWM_1 = 1,
- GPIO2A5_I2C1_SCL,
-
- GPIO2A6_SEL_SHIFT = 12,
- GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
- GPIO2A6_PWM_2 = 1,
-
- GPIO2A7_SEL_SHIFT = 14,
- GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_PWRENM0,
-
- /* GPIO2BL_IOMUX */
- GPIO2BL0_SEL_SHIFT = 0,
- GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
- GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
-
- GPIO2BL3_SEL_SHIFT = 6,
- GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
- GPIO2BL3_SPI_CSN0_M0 = 1,
-
- GPIO2BL4_SEL_SHIFT = 8,
- GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
- GPIO2BL4_SPI_CSN1_M0 = 1,
-
- GPIO2BL5_SEL_SHIFT = 10,
- GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
- GPIO2BL5_I2C2_SDA = 1,
-
- GPIO2BL6_SEL_SHIFT = 12,
- GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
- GPIO2BL6_I2C2_SCL = 1,
-
- /* GPIO2D_IOMUX */
- GPIO2D0_SEL_SHIFT = 0,
- GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
- GPIO2D0_I2C0_SCL = 1,
-
- GPIO2D1_SEL_SHIFT = 2,
- GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
- GPIO2D1_I2C0_SDA = 1,
-
- GPIO2D4_SEL_SHIFT = 8,
- GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
- GPIO2D4_EMMC_DATA1234 = 0xaa,
-
- /* GPIO3C_IOMUX */
- GPIO3C0_SEL_SHIFT = 0,
- GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
-
- /* COM_IOMUX */
- IOMUX_SEL_UART2_SHIFT = 0,
- IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
- IOMUX_SEL_UART2_M0 = 0,
- IOMUX_SEL_UART2_M1,
-
- IOMUX_SEL_SPI_SHIFT = 4,
- IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
- IOMUX_SEL_SPI_M0 = 0,
- IOMUX_SEL_SPI_M1,
- IOMUX_SEL_SPI_M2,
-
- IOMUX_SEL_SDMMC_SHIFT = 7,
- IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
- IOMUX_SEL_SDMMC_M0 = 0,
- IOMUX_SEL_SDMMC_M1,
-};
-
#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
u32 reserved14[2];
u32 dma_con0;
u32 dma_con1;
- u32 reserved15[539];
+ u32 reserved15[59];
u32 uoc_status;
+ u32 reserved16[2];
u32 host_status;
+ u32 reserved17[59];
u32 gmac_con0;
+ u32 reserved18[191];
u32 chip_id;
};
-check_member(rv1108_grf, chip_id, 0xf90);
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO = 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO = 0,
- GPIO1C2_LCDC_EN,
- GPIO1C2_I2S_SDIO3_M0,
- GPIO1C2_GMAC_RXER,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_LCDC_D10,
- GPIO1C1_I2S_SDI_M0,
- GPIO1C1_PWM4,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3,
- GPIO1C0_GPIO = 0,
- GPIO1C0_LCDC_D11,
- GPIO1C0_I2S_LRCLKRX_M0,
-};
-
-/* GRF_GPIO1D_OIMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_HDMI_CEC,
- GPIO1D7_DSP_RTCK,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_HDMI_HPD_M0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_UART2_RTSN,
- GPIO1D5_HDMI_SDA_M0,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_UART2_CTSN,
- GPIO1D4_HDMI_SCL_M0,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_UART0_SOUT,
- GPIO1D3_SPI_TXD_M0,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_UART0_SIN,
- GPIO1D2_SPI_RXD_M0,
- GPIO1D2_DSP_TDI,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_UART0_RTSN,
- GPIO1D1_SPI_CSN0_M0,
- GPIO1D1_DSP_TMS,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3,
- GPIO1D0_GPIO = 0,
- GPIO1D0_UART0_CTSN,
- GPIO1D0_SPI_CLK_M0,
- GPIO1D0_DSP_TCK,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_FLASH_D7,
- GPIO2A7_EMMC_D7,
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
- GPIO2A6_GPIO = 0,
- GPIO2A6_FLASH_D6,
- GPIO2A6_EMMC_D6,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_FLASH_D5,
- GPIO2A5_EMMC_D5,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_D4,
- GPIO2A4_EMMC_D4,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_D3,
- GPIO2A3_EMMC_D3,
- GPIO2A3_SFC_HOLD_IO3,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_D2,
- GPIO2A2_EMMC_D2,
- GPIO2A2_SFC_WP_IO2,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_D1,
- GPIO2A1_EMMC_D1,
- GPIO2A1_SFC_SO_IO1,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_D0,
- GPIO2A0_EMMC_D0,
- GPIO2A0_SFC_SI_IO0,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_FLASH_CS1,
- GPIO2B7_SFC_CLK,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_EMMC_CLKO,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_FLASH_CS0,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_FLASH_RDY,
- GPIO2B4_EMMC_CMD,
- GPIO2B4_SFC_CSN0,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_FLASH_RDN,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_FLASH_WRN,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_FLASH_CLE,
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_FLASH_ALE,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO_D0,
-
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO_CMD,
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO_CLKO,
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
- GPIO2D4_GPIO = 0,
- GPIO2D4_I2C1_SCL,
-
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
- GPIO2D3_GPIO = 0,
- GPIO2D3_I2C1_SDA,
-
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART2_SOUT_M0,
- GPIO2D2_JTAG_TCK,
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART2_SIN_M0,
- GPIO2D1_JTAG_TMS,
- GPIO2D1_DSP_TMS,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_CTSN,
- GPIO2D0_SPI_CLK_M0,
- GPIO2D0_DSP_TCK,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
- GPIO3A7_SHIFT = 14,
- GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
- GPIO3A7_GPIO = 0,
-
- GPIO3A6_SHIFT = 12,
- GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
- GPIO3A6_GPIO = 0,
- GPIO3A6_UART1_SOUT,
-
- GPIO3A5_SHIFT = 10,
- GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
- GPIO3A5_GPIO = 0,
- GPIO3A5_UART1_SIN,
-
- GPIO3A4_SHIFT = 8,
- GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
- GPIO3A4_GPIO = 0,
- GPIO3A4_UART1_CTSN,
-
- GPIO3A3_SHIFT = 6,
- GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
- GPIO3A3_GPIO = 0,
- GPIO3A3_UART1_RTSN,
-
- GPIO3A2_SHIFT = 4,
- GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
- GPIO3A2_GPIO = 0,
- GPIO3A2_SDIO_D3,
-
- GPIO3A1_SHIFT = 2,
- GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
- GPIO3A1_GPIO = 0,
- GPIO3A1_SDIO_D2,
-
- GPIO3A0_SHIFT = 0,
- GPIO3A0_MASK = 1,
- GPIO3A0_GPIO = 0,
- GPIO3A0_SDIO_D1,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
- GPIO3C7_GPIO = 0,
- GPIO3C7_CIF_CLKI,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_CIF_VSYNC,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_SDMMC_CMD,
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
- GPIO3C4_GPIO = 0,
- GPIO3C4_SDMMC_CLKO,
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
- GPIO3C3_GPIO = 0,
- GPIO3C3_SDMMC_D0,
- GPIO3C3_UART2_SOUT_M1,
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
- GPIO3C2_GPIO = 0,
- GPIO3C2_SDMMC_D1,
- GPIO3C2_UART2_SIN_M1,
-
- GPIOC1_SHIFT = 2,
- GPIOC1_MASK = 1 << GPIOC1_SHIFT,
- GPIOC1_GPIO = 0,
- GPIOC1_SDMMC_D2,
-
- GPIOC0_SHIFT = 0,
- GPIOC0_MASK = 1,
- GPIO3C0_GPIO = 0,
- GPIO3C0_SDMMC_D3,
-};
+check_member(rv1108_grf, chip_id, 0x0c00);
#endif
};
enum periph_clock {
- SYSCFG_CLOCK_CFG,
TIMER2_CLOCK_CFG,
- STMMAC_CLOCK_CFG,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */
#include <asm/io.h>
/* Base address */
+#ifndef EMIF1_BASE
#define EMIF1_BASE 0x4c000000
+#endif
#define EMIF2_BASE 0x4d000000
#define EMIF_4D 0x4
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
+/* EMIF ECC CTRL reg */
+#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31
+#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31)
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30)
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29)
+#define EMIF_ECC_REG_RMW_EN_SHIFT 28
+#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0)
+
+/* EMIF ECC ADDRESS RANGE */
+#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16
+#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16)
+#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0
+#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0)
+
+/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5)
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4)
+#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3
+#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3)
+
/* Reg mapping structure */
struct emif_reg_struct {
u32 emif_mod_id_rev;
u32 emif_prio_class_serv_map;
u32 emif_connect_id_serv_1_map;
u32 emif_connect_id_serv_2_map;
- u32 padding8[5];
+ u32 padding8;
+ u32 emif_ecc_ctrl_reg;
+ u32 emif_ecc_address_range_1;
+ u32 emif_ecc_address_range_2;
+ u32 padding8_1;
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE)
+ u32 padding9[2];
+ u32 emif_1b_ecc_err_cnt;
+ u32 emif_1b_ecc_err_thrush;
+ u32 emif_1b_ecc_err_dist_1;
+ u32 emif_1b_ecc_err_addr_log;
+ u32 emif_2b_ecc_err_addr_log;
+ u32 emif_ddr_phy_status[28];
+ u32 padding10[19];
+#else
u32 padding9[6];
u32 emif_ddr_phy_status[28];
u32 padding10[20];
+#endif
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
u32 emif_connect_id_serv_1_map;
u32 emif_connect_id_serv_2_map;
u32 emif_cos_config;
+ u32 emif_ecc_ctrl_reg;
+ u32 emif_ecc_address_range_1;
+ u32 emif_ecc_address_range_2;
};
struct lpddr2_mr_regs {
extern struct dplls const **dplls_data;
extern struct dplls dra7xx_dplls;
extern struct dplls dra72x_dplls;
+extern struct dplls dra76x_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA76X;
}
+
+static inline u8 is_dra76x_abz(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 3;
+}
#endif
/*
#define DRA722_ES2_0 0x07220200
#define DRA722_ES2_1 0x07220210
+#define DRA762_ABZ_ES1_0 0x07620102
+#define DRA762_ACD_ES1_0 0x07620103
/*
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
#include <mmc.h>
struct hsmmc {
+#ifndef CONFIG_OMAP34XX
+ unsigned int hl_rev;
+ unsigned int hl_hwinfo;
+ unsigned int hl_sysconfig;
+ unsigned char res0[0xf4];
+#endif
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
+ unsigned char res5[0x10];
+ unsigned int admaes; /* 0x154 */
+ unsigned int admasal; /* 0x158 */
};
struct omap_hsmmc_plat {
/*
* OMAP HS MMC Bit definitions
*/
+#define MADMA_EN (0x1 << 0)
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
+#define DMA_MASTER (0x1 << 20)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
+#define DE_ENABLE (0x1 << 0)
#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
+#define ACEN_ENABLE (0x1 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
+#define DMA_SELECT (0x2 << 3)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
+#define IE_ADMAE (0x01 << 25)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
enum edma3_sync_dimension sync_mode);
void edma3_transfer(unsigned long edma3_base_addr, unsigned int
edma_slot_num, void *dst, void *src, size_t len);
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len);
#endif
CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
int arch_fixup_fdt(void *blob)
{
- int ret = 0;
+ __maybe_unused int ret = 0;
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
bd_t *bd = gd->bd;
int bank;
unsigned long base;
};
-int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned gpio);
-
#endif /* _BCM2835_GPIO_H_ */
config TARGET_IPAM390
bool "IPAM390 board"
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
select SUPPORT_SPL
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
config TARGET_DA850EVM
bool "DA850 EVM board"
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
select SUPPORT_SPL
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
config TARGET_EA20
bool "EA20 board"
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
select BOARD_LATE_INIT
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
+ select SOC_DA850
select SUPPORT_SPL
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
config TARGET_CALIMAIN
bool "Calimain board"
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
+ select SOC_DA850
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
- select SYS_DA850_PLL_INIT
- select SYS_DA850_DDR_INIT
+ select MACH_DAVINCI_DA850_EVM
+ select SOC_DA850
endchoice
config SYS_SOC
default "davinci"
+config DA850_LOWLEVEL
+ bool "Enable Lowlevel DA850 initialization"
+ depends on SOC_DA850
+
config SYS_DA850_PLL_INIT
bool
config SYS_DA850_DDR_INIT
bool
+config SOC_DA850
+ bool
+ select SOC_DA8XX
+ select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+
+config SOC_DA8XX
+ bool
+ select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+
+config MACH_DAVINCI_DA850_EVM
+ bool
+
+if SYS_DA850_PLL_INIT
+comment "DA850 PLL Initialization Parameters"
+
+config SYS_DV_CLKMODE
+ int "PLLCTL Clock Mode"
+ default 0 if SOC_DA850
+ help
+ Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
+
+config SYS_DA850_PLL0_POSTDIV
+ int "PLLC0 PLL Post-Divider"
+ default 1 if SOC_DA850
+ help
+ Value written to PLLC0 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL0_PLLDIV1
+ hex "PLLC0 Divider 1"
+ default 0x8000 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 1 register
+
+config SYS_DA850_PLL0_PLLDIV2
+ hex "PLLC0 Divider 2"
+ default 0x8001 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 2 register
+
+config SYS_DA850_PLL0_PLLDIV3
+ hex "PLLC0 Divider 3"
+ default 0x8002 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 3 register
+
+config SYS_DA850_PLL0_PLLDIV4
+ hex "PLLC0 Divider 4"
+ default 0x8003 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 4 register
+
+config SYS_DA850_PLL0_PLLDIV5
+ hex "PLLC0 Divider 5"
+ default 0x8002 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 5 register
+
+config SYS_DA850_PLL0_PLLDIV6
+ hex "PLLC0 Divider 6"
+ default 0x8000 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 6 register
+
+config SYS_DA850_PLL0_PLLDIV7
+ hex "PLLC0 Divider 7"
+ default 0x8005 if SOC_DA850
+ help
+ Value written to PLLC0 Divider 7 register
+
+config SYS_DA850_PLL1_POSTDIV
+ hex "PLLC1 PLL Post-Divider"
+ default 1 if SOC_DA850
+ help
+ Value written to PLLC1 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL1_PLLDIV1
+ hex "PLLC1 Divider 2"
+ default 0x8000 if SOC_DA850
+ help
+ Value written to PLLC1 Divider 1 register
+
+config SYS_DA850_PLL1_PLLDIV2
+ hex "PLLC1 Divider 2"
+ default 0x8001 if SOC_DA850
+ help
+ Value written to PLLC1 Divider 2 register
+
+config SYS_DA850_PLL1_PLLDIV3
+ hex "PLLC1 Divider 3"
+ default 0x8002 if SOC_DA850
+ help
+ Value written to PLLC1 Divider 3 register
+
+endif
+
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
/* Reset data FIFOs twice. */
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
}
static void precharge_all(const bool cs0_enable, const bool cs1_enable)
*/
if (cs0_enable) { /* CS0 */
writel(0x04008050, &mmdc0->mdscr);
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
if (cs1_enable) { /* CS1 */
writel(0x04008058, &mmdc0->mdscr);
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
}
* 7. Upon completion of this process the MMDC de-asserts
* the MPWLGCR[HW_WL_EN]
*/
- wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
/*
* 8. check for any errors: check both PHYs for x64 configuration,
writel(0x00008028, &mmdc0->mdscr);
/* poll to make sure the con_ack bit was asserted */
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
/*
* Check MDMISC register CALIB_PER_CS to see which CS calibration
* this bit until it clears to indicate completion of the write access.
*/
setbits_le32(&mmdc0->mpswdar0, 1);
- wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
/* Set the RD_DL_ABS# bits to their default values
* (will be calibrated later in the read delay-line calibration).
setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
/* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
/*
* Check to see if any errors were encountered during calibration
* setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
* no error bits were set.
*/
- wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
/* check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
* by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
* Also, ensure that no error bits were set.
*/
- wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
writel(0x0, &mmdc0->mdscr); /* CS0 */
/* Poll to make sure the con_ack bit is clear */
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
+ wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
/*
* Print out the registers that were updated as a result
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2G_EVM
select BOARD_LATE_INIT
select SPL_BOARD_INIT if SPL
select TI_I2C_BOARD_DETECT
+ select CMD_DDR3
imply DM_I2C
endchoice
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += cmd_poweroff.o
-obj-y += cmd_ddr3.o
endif
obj-y += msmc.o
obj-y += ddr3.o
#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
#define KS2_DDR3A_DDRPHYC 0x02329000
+#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
#define CPU_66AK2Lx 0xb9a7
#define CPU_66AK2Gx 0xbb06
+/* Variant definitions */
+#define CPU_66AK2G1x 0x08
+
/* DEVSPEED register */
#define DEVSPEED_DEVSPEED_SHIFT 16
#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x23000100
-#define OMAP_HSMMC2_BASE 0x23100100
+#define OMAP_HSMMC1_BASE 0x23000000
+#define OMAP_HSMMC2_BASE 0x23100000
#endif /* K2G_MMC_HOST_DEF_H */
puts("66AK2Ex SR");
break;
case CPU_66AK2Gx:
- puts("66AK2Gx SR");
+ puts("66AK2Gx");
+#ifdef CONFIG_SOC_K2G
+ {
+ int speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ puts("-100 ");
+ else if (speed == SPD600)
+ puts("-60 ");
+ else
+ puts("-xx ");
+ }
+#endif
+ puts("SR");
break;
default:
puts("Unknown\n");
puts("1.1\n");
else if (rev == 0)
puts("1.0\n");
-
+ else if (rev == 8)
+ puts("1.0\n");
return 0;
}
#endif
select DM_SERIAL
select DM_GPIO
+config TARGET_PDU001
+ bool "Support PDU001"
+ select DM
+ select DM_SERIAL
+ help
+ Support for PDU001 platform developed by EETS GmbH.
+ The PDU001 is a processor and display unit developed around
+ the Computing-Module m2 from bytes at work AG.
+
endchoice
endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
do_board_detect();
#endif
+#ifdef CONFIG_SPL_BUILD
+ spl_early_init();
+#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
{505, 15, 2, -1, -1, -1, -1}, /*19.2*/
{101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
- {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
- {303, 12, 2, -1, 4, -1, -1} /* 26 MHz */
+ {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
+ {303, 12, 2, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
- {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
- {200, 12, 1, -1, 4, -1, -1} /* 26 MHz */
+ {16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
+ {200, 12, 1, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
{665, 47, 1, -1, -1, -1, -1}, /*19.2*/
{133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
- {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
- {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
+ {266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
+ {133, 12, 1, -1, -1, -1, -1} /* 26 MHz */
};
__weak const struct dpll_params *get_dpll_mpu_params(void)
#include <asm/omap_sec_common.h>
#include <asm/utils.h>
#include <linux/compiler.h>
+#include <asm/ti-common/ti-edma3.h>
static int emif1_enabled = -1, emif2_enabled = -1;
u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
u32 reg, i, phy;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
phy = readl(&emif->emif_ddr_phy_ctrl_1);
/* Update PHY_REG_RDDQS_RATIO */
/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
reg = readl(emif_phy_status++);
/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
reg = readl(emif_phy_status++);
update_hwleveling_output(base, regs);
}
+static void dra7_reset_ddr_data(u32 base, u32 size)
+{
+#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
+ enable_edma3_clocks();
+
+ edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size);
+
+ disable_edma3_clocks();
+#else
+ memset((void *)base, 0, size);
+#endif
+}
+
+static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 rgn, size;
+
+ /* ECC available only on dra76x EMIF1 */
+ if ((base != EMIF1_BASE) || !is_dra76x())
+ return;
+
+ if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
+ writel(regs->emif_ecc_address_range_1,
+ &emif->emif_ecc_address_range_1);
+ writel(regs->emif_ecc_address_range_2,
+ &emif->emif_ecc_address_range_2);
+ writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
+
+ /* Set region1 memory with 0 */
+ rgn = ((regs->emif_ecc_address_range_1 &
+ EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) +
+ CONFIG_SYS_SDRAM_BASE;
+ size = (regs->emif_ecc_address_range_1 &
+ EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000;
+
+ if (regs->emif_ecc_ctrl_reg &
+ EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
+ dra7_reset_ddr_data(rgn, size);
+
+ /* Set region2 memory with 0 */
+ rgn = ((regs->emif_ecc_address_range_2 &
+ EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) +
+ CONFIG_SYS_SDRAM_BASE;
+ size = (regs->emif_ecc_address_range_2 &
+ EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000;
+
+ if (regs->emif_ecc_ctrl_reg &
+ EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
+ dra7_reset_ddr_data(rgn, size);
+
+#ifdef CONFIG_DRA7XX
+ /* Clear the status flags and other history */
+ writel(readl(&emif->emif_1b_ecc_err_cnt),
+ &emif->emif_1b_ecc_err_cnt);
+ writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
+ writel(0x1, &emif->emif_2b_ecc_err_addr_log);
+ writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
+ EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
+ EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
+ &emif->emif_irqstatus_sys);
+#endif
+ }
+}
+
static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
- if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
+ if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) {
+ /*
+ * Perform Dummy ECC setup just to allow hardware
+ * leveling of ECC memories
+ */
+ if (is_dra76x() && (base == EMIF1_BASE) &&
+ (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) {
+ writel(0, &emif->emif_ecc_address_range_1);
+ writel(0, &emif->emif_ecc_address_range_2);
+ writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK |
+ EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK,
+ &emif->emif_ecc_ctrl_reg);
+ }
+
dra7_ddr3_leveling(base, regs);
+
+ /* Disable ECC */
+ if (is_dra76x())
+ writel(0, &emif->emif_ecc_ctrl_reg);
+ }
+
+ /* Enable ECC as necessary */
+ dra7_enable_ecc(base, regs);
}
static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- const char *sec_s;
+ const char *sec_s, *package = NULL;
switch (get_device_type()) {
case TST_DEVICE:
sec_s = "?";
}
+#if defined(CONFIG_DRA7XX)
+ if (is_dra76x()) {
+ switch (omap_rev & 0xF) {
+ case DRA762_ABZ_PACKAGE:
+ package = "ABZ";
+ break;
+ case DRA762_ACD_PACKAGE:
+ default:
+ package = "ACD";
+ break;
+ }
+ }
+#endif
+
if (soc_variant)
printf("OMAP");
else
printf("DRA");
- printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
+ printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
+ if (package)
+ printf(" %s package\n", package);
+ else
+ puts("\n");
}
#ifdef CONFIG_SPL_BUILD
}
/**
+ * init_package_revision() - Initialize package revision
+ *
+ * Function to get the pacakage information. This is expected to be
+ * overridden in the SoC family file where desired.
+ */
+void __weak init_package_revision(void)
+{
+}
+
+/**
* early_system_init - Does Early system initialization.
*
* Does early system init of watchdog, muxing, andclocks
{
init_omap_revision();
hw_data_init();
+ init_package_revision();
#ifdef CONFIG_SPL_BUILD
if (warm_reset())
select BOARD_LATE_INIT
select DRA7XX
select TI_I2C_BOARD_DETECT
+ select CMD_DDR3
imply SCSI
imply SPL_THERMAL
imply DM_THERMAL
*ctrl = &omap5_ctrl;
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra76x_dplls;
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA762_ES1_0:
+ case DRA762_ACD_ES1_0:
+ case DRA762_ABZ_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
init_cpu_configuration();
}
+void init_package_revision(void)
+{
+ unsigned int die_id[4] = { 0 };
+ u8 package;
+
+ omap_die_id(die_id);
+ package = (die_id[2] >> 16) & 0x3;
+
+ if (is_dra76x()) {
+ switch (package) {
+ case DRA762_ABZ_PACKAGE:
+ *omap_si_rev = DRA762_ABZ_ES1_0;
+ break;
+ case DRA762_ACD_PACKAGE:
+ default:
+ *omap_si_rev = DRA762_ACD_ES1_0;
+ break;
+ }
+ }
+}
+
void omap_die_id(unsigned int *die_id)
{
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
case DRA762_ES1_0:
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA722_ES2_0:
case DRA722_ES2_1:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
u32 tee_arg0; /* argument to TEE jump function, in r0 */
};
-static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN);
+static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN) __section(".data");
u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...)
{
*size = sig_addr - cert_addr; /* Subtract out the signature size */
/* Subtract header if present */
if (strncmp((char *)sig_addr, "CERT_ISW_", 9) == 0)
- *size = ((u32 *)*image)[HEADER_SIZE_OFFSET];
+ *size -= ((u32 *)*image)[HEADER_SIZE_OFFSET];
cert_size = *size;
/* Check if image load address is 32-bit aligned */
}
/*
- * Output notification of successful authentication as well the name of
- * the signing certificate used to re-assure the user that the secure
- * code is being processed as expected. However suppress any such log
- * output in case of building for SPL and booting via YMODEM. This is
- * done to avoid disturbing the YMODEM serial protocol transactions.
+ * Output notification of successful authentication to re-assure the
+ * user that the secure code is being processed as expected. However
+ * suppress any such log output in case of building for SPL and booting
+ * via YMODEM. This is done to avoid disturbing the YMODEM serial
+ * protocol transactions.
*/
if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
spl_boot_device() == BOOT_DEVICE_UART))
- printf("Authentication passed: %s\n", (char *)sig_addr);
+ printf("Authentication passed\n");
return result;
}
default "qemu-arm"
endif
+
+config TARGET_QEMU_ARM_32BIT
+ bool "Support qemu_arm"
+ depends on ARCH_QEMU
+ select CPU_V7
+ select ARCH_SUPPORT_PSCI
+
+config TARGET_QEMU_ARM_64BIT
+ bool "Support qemu_arm64"
+ depends on ARCH_QEMU
+ select ARM64
if RCAR_32
+config RCAR_GEN2
+ bool "Renesas RCar Gen2"
+
+config R8A7740
+ bool "Renesas SoC R8A7740"
+
+config R8A7790
+ bool "Renesas SoC R8A7790"
+ select RCAR_GEN2
+
+config R8A7791
+ bool "Renesas SoC R8A7791"
+ select RCAR_GEN2
+
+config R8A7792
+ bool "Renesas SoC R8A7792"
+ select RCAR_GEN2
+
+config R8A7793
+ bool "Renesas SoC R8A7793"
+ select RCAR_GEN2
+
+config R8A7794
+ bool "Renesas SoC R8A7794"
+ select RCAR_GEN2
+
choice
prompt "Renesas ARM SoCs board select"
optional
select CPU_V7
select SUPPORT_SPL
select SPL
+ imply USB_FUNCTION_ROCKUSB
+ imply CMD_ROCKUSB
help
The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
void board_debug_uart_init(void)
{
-static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART1_SIN,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+ };
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT= 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ };
+
/* Enable early UART2 channel 1 on the RK322x */
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,
/* Enable early UART2 channel 1 on the RK322x */
#define GRF_BASE 0x11000000
struct rk322x_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+ };
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT= 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ };
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,
- CLKMGR_STAT_BUSY, false, 20000, false);
+ return wait_for_bit_le32(&clock_manager_base->stat,
+ CLKMGR_STAT_BUSY, false, 20000, false);
}
int set_cpu_clk_info(void)
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
#include <common.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
}
/* function to write a clock register that has phase information */
-static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
+static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
{
int ret;
/* poll until phase is zero */
- ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
- false, 20000, false);
+ ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
if (ret)
return ret;
writel(value, reg_address);
- return wait_for_bit(__func__, (const u32 *)reg_address, mask,
- false, 20000, false);
+ return wait_for_bit_le32(reg_address, mask, false, 20000, false);
}
/*
* are aligned nicely; so we can change any phase.
*/
ret = cm_write_with_phase(cfg->ddrdqsclk,
- (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
+ &clock_manager_base->sdr_pll.ddrdqsclk,
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
if (ret)
return ret;
/* SDRAM DDR2XDQSCLK */
ret = cm_write_with_phase(cfg->ddr2xdqsclk,
- (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
+ &clock_manager_base->sdr_pll.ddr2xdqsclk,
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
if (ret)
return ret;
ret = cm_write_with_phase(cfg->ddrdqclk,
- (u32)&clock_manager_base->sdr_pll.ddrdqclk,
+ &clock_manager_base->sdr_pll.ddrdqclk,
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
if (ret)
return ret;
ret = cm_write_with_phase(cfg->s2fuser2clk,
- (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
+ &clock_manager_base->sdr_pll.s2fuser2clk,
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
if (ret)
return ret;
return clock;
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
- return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
- false, 1000, false);
+ return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
+ false, 1000, false);
}
void socfpga_reset_assert_fpga_connected_peripherals(void)
writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
/* Poll until all idleack to 1 */
- ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack,
- ALT_SYSMGR_NOC_H2F_SET_MSK |
- ALT_SYSMGR_NOC_LWH2F_SET_MSK |
- ALT_SYSMGR_NOC_F2H_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- true, 10000, false);
+ ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
+ ALT_SYSMGR_NOC_H2F_SET_MSK |
+ ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+ ALT_SYSMGR_NOC_F2H_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+ true, 10000, false);
if (ret)
return ret;
/* Poll until all idlestatus to 1 */
- ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus,
- ALT_SYSMGR_NOC_H2F_SET_MSK |
- ALT_SYSMGR_NOC_LWH2F_SET_MSK |
- ALT_SYSMGR_NOC_F2H_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- true, 10000, false);
+ ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
+ ALT_SYSMGR_NOC_H2F_SET_MSK |
+ ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+ ALT_SYSMGR_NOC_F2H_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+ true, 10000, false);
if (ret)
return ret;
config STM32F4
bool "stm32f4 family"
+ select CLK
+ select DM_GPIO
+ select DM_RESET
+ select MISC
+ select PINCTRL
+ select PINCTRL_STM32
+ select RAM
+ select STM32_SDRAM
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
config STM32F7
bool "stm32f7 family"
+ select CLK
+ select DM_GPIO
+ select DM_RESET
+ select MISC
+ select PINCTRL
+ select PINCTRL_STM32
+ select RAM
+ select STM32_SDRAM
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
select SUPPORT_SPL
select SPL
+ select SPL_BOARD_INIT
select SPL_CLK
select SPL_DM
select SPL_DM_SEQ_ALIAS
select STM32_SDRAM
select STM32_RCC
select STM32_RESET
- select STM32X7_SERIAL
+ select STM32_SERIAL
select SYSCON
source "arch/arm/mach-stm32/stm32f4/Kconfig"
config TARGET_STM32F429_DISCOVERY
bool "STM32F429 Discovery board"
+config TARGET_STM32F429_EVALUATION
+ bool "STM32F429 Evaluation board"
+
config TARGET_STM32F469_DISCOVERY
bool "STM32F469 Discovery board"
source "board/st/stm32f429-discovery/Kconfig"
+source "board/st/stm32f429-evaluation/Kconfig"
source "board/st/stm32f469-discovery/Kconfig"
endif
u32 num_aes_blocks)
{
u8 tmp_data[AES_KEY_LENGTH];
+ u8 iv[AES_KEY_LENGTH] = {0};
u8 left[AES_KEY_LENGTH];
u8 k1[AES_KEY_LENGTH];
u8 *cbc_chain_data;
for (i = 0; i < AES_KEY_LENGTH; i++)
tmp_data[i] = 0;
- aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1);
+ aes_cbc_encrypt_blocks(key_schedule, iv, tmp_data, left, 1);
left_shift_vector(left, k1, sizeof(left));
{
u32 num_aes_blocks;
u8 key_schedule[AES_EXPAND_KEY_LENGTH];
+ u8 iv[AES_KEY_LENGTH] = {0};
debug("encrypt_and_sign: length = %d\n", length);
if (oper & SECURITY_ENCRYPT) {
/* Perform this in place, resulting in src being encrypted. */
debug("encrypt_and_sign: begin encryption\n");
- aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks);
+ aes_cbc_encrypt_blocks(key_schedule, iv, src, src,
+ num_aes_blocks);
debug("encrypt_and_sign: end encryption\n");
}
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
return 0;
}
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf1[32], buf2[32];
strmhz(buf2, gd->bus_clk));
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
#endif /* #ifdef CONFIG_M5208 */
#ifdef CONFIG_M5271
+#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
* determine which one we are running on, based on the Chip Identification
* Register (CIR).
*/
-int checkcpu(void)
+int print_cpuinfo(void)
{
char buf[32];
unsigned short cir; /* Chip Identification Register */
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
uchar msk;
printf("Freescale MCF5272 %s\n", suf);
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
strmhz(buf, CONFIG_SYS_CLK));
return 0;
};
-
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
#endif /* #ifdef CONFIG_M5275 */
#ifdef CONFIG_M5282
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
unsigned char resetsource = MCFRESET_RSR;
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#endif
#ifdef CONFIG_M5249
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#endif
#ifdef CONFIG_M5253
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
}
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return 0;
}
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
char buf[32];
strmhz(buf, CONFIG_SYS_CPU_CLK));
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
#endif
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
return 0;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
return 1;
};
-int checkcpu(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
{
siu_t *siu = (siu_t *) MMAP_SIU;
u16 id = 0;
return 0;
};
+#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_HW_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define CONFIG_SYS_BOOT_GET_CMDLINE
-#define CONFIG_SYS_BOOT_GET_KBD
#endif
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb
dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
+dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
/ {
compatible = "brcm,bcm3380";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0x14e00000 0x4>;
#address-cells = <1>;
status = "disabled";
};
+ spi: spi@14e02000 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x14e02000 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk0 BCM3380_CLK0_SPI>;
+ resets = <&periph_rst0 BCM3380_RST0_SPI>;
+ spi-max-frequency = <25000000>;
+ num-cs = <6>;
+
+ status = "disabled";
+ };
+
leds: led-controller@14e00f00 {
compatible = "brcm,bcm6328-leds";
reg = <0x14e00f00 0x1c>;
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6318-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power-domain/bcm6318-power-domain.h>
+#include <dt-bindings/reset/bcm6318-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6318";
+
+ aliases {
+ spi0 = &spi;
+ };
+
+ cpus {
+ reg = <0x10000000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk: periph-clk {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x10000004 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_rst: reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog@10000068 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x10000068 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ pll_cntl: syscon@10000074 {
+ compatible = "syscon";
+ reg = <0x10000074 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ gpio1: gpio-controller@10000080 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10000080 0x4>, <0x10000088 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <18>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@10000084 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@10000100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@10000200 {
+ compatible = "brcm,bcm6328-leds";
+ reg = <0x10000200 0x28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ periph_pwr: power-controller@100008e8 {
+ compatible = "brcm,bcm6328-power-domain";
+ reg = <0x100008e8 0x4>;
+ #power-domain-cells = <1>;
+ };
+
+ spi: spi@10003000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10003000 0x600>;
+ clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ resets = <&periph_rst BCM6318_RST_SPI>;
+ spi-max-frequency = <33333334>;
+ num-cs = <3>;
+
+ status = "disabled";
+ };
+
+ memory-controller@10004000 {
+ compatible = "brcm,bcm6318-mc";
+ reg = <0x10004000 0x38>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
/ {
compatible = "brcm,bcm63268";
+ aliases {
+ spi0 = &lsspi;
+ spi1 = &hsspi;
+ };
+
cpus {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
#power-domain-cells = <1>;
};
+ lsspi: spi@10000800 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x10000800 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM63268_CLK_SPI>;
+ resets = <&periph_rst BCM63268_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
+ hsspi: spi@10001000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10001000 0x600>;
+ clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ resets = <&periph_rst BCM63268_RST_SPI>;
+ spi-max-frequency = <50000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
leds: led-controller@10001900 {
compatible = "brcm,bcm6328-leds";
reg = <0x10001900 0x24>;
/ {
compatible = "brcm,bcm6328";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133333333>;
+ };
+
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
status = "disabled";
};
+ spi: spi@10001000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10001000 0x600>;
+ clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ resets = <&periph_rst BCM6328_RST_SPI>;
+ spi-max-frequency = <33333334>;
+ num-cs = <3>;
+
+ status = "disabled";
+ };
+
periph_pwr: power-controller@10001848 {
compatible = "brcm,bcm6328-power-domain";
reg = <0x10001848 0x4>;
/ {
compatible = "brcm,bcm6338";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
status = "disabled";
};
+ spi: spi@fffe0c00 {
+ compatible = "brcm,bcm6348-spi";
+ reg = <0xfffe0c00 0xc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6338_CLK_SPI>;
+ resets = <&periph_rst BCM6338_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe3100 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe3100 0x38>;
/ {
compatible = "brcm,bcm6348";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
status = "disabled";
};
+ spi: spi@fffe0c00 {
+ compatible = "brcm,bcm6348-spi";
+ reg = <0xfffe0c00 0xc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6348_CLK_SPI>;
+ resets = <&periph_rst BCM6348_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe2300 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe2300 0x38>;
/ {
compatible = "brcm,bcm6358";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
status = "disabled";
};
+ spi: spi@fffe0800 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0xfffe0800 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6358_CLK_SPI>;
+ resets = <&periph_rst BCM6358_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe1200 {
compatible = "brcm,bcm6358-mc";
reg = <0xfffe1200 0x4c>;
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6368-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6368-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6368";
+
+ aliases {
+ spi0 = &spi;
+ };
+
+ cpus {
+ reg = <0x10000000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk: periph-clk {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x10000004 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pflash: nor@18000000 {
+ compatible = "cfi-flash";
+ reg = <0x18000000 0x2000000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ pll_cntl: syscon@10000008 {
+ compatible = "syscon";
+ reg = <0x10000008 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ periph_rst: reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog@1000005c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x1000005c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ gpio1: gpio-controller@10000080 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10000080 0x4>, <0x10000088 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <6>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@10000084 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@100000d0 {
+ compatible = "brcm,bcm6358-leds";
+ reg = <0x100000d0 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@10000100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@10000120 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000120 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ spi: spi@10000800 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x10000800 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6368_CLK_SPI>;
+ resets = <&periph_rst BCM6368_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <6>;
+
+ status = "disabled";
+ };
+
+ memory-controller@10001200 {
+ compatible = "brcm,bcm6358-mc";
+ reg = <0x10001200 0x4c>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6318.dtsi"
+
+/ {
+ model = "Comtrend AR-5315u";
+ compatible = "comtrend,ar5315-un", "brcm,bcm6318";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&leds {
+ status = "okay";
+
+ led@0 {
+ reg = <0>;
+ active-low;
+ label = "AR-5315u:green:wps";
+ };
+
+ led@1 {
+ reg = <1>;
+ active-low;
+ label = "AR-5315u:green:power";
+ };
+
+ led@2 {
+ reg = <2>;
+ active-low;
+ label = "AR-5315u:green:usb";
+ };
+
+ led@8 {
+ reg = <8>;
+ active-low;
+ label = "AR-5315u:green:inet";
+ };
+
+ led@9 {
+ reg = <9>;
+ active-low;
+ label = "AR-5315u:red:inet";
+ };
+
+ led@10 {
+ reg = <10>;
+ active-low;
+ label = "AR-5315u:green:dsl";
+ };
+
+ led@11 {
+ reg = <11>;
+ active-low;
+ label = "AR-5315u:red:power";
+ };
+};
+
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <62500000>;
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
};
};
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <33333334>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6368.dtsi"
+
+/ {
+ model = "Comtrend WAP-5813n";
+ compatible = "comtrend,wap-5813n", "brcm,bcm6368";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ inet_green {
+ label = "WAP-5813n:green:inet";
+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_green {
+ label = "WAP-5813n:green:power";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ wps_green {
+ label = "WAP-5813n:green:wps";
+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ };
+
+ power_red {
+ label = "WAP-5813n:red:power";
+ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ };
+
+ inet_red {
+ label = "WAP-5813n:red:inet";
+ gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&pflash {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
status = "okay";
};
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
status = "okay";
};
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
setbits_be32(pll_reg_base + 0x8, BIT(30));
udelay(5);
- wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+ wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
clrbits_be32(pll_reg_base + 0x8, BIT(30));
udelay(5);
menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
+config SYS_MALLOC_F_LEN
+ default 0x1000
+
config SYS_SOC
default "bcm3380" if SOC_BMIPS_BCM3380
+ default "bcm6318" if SOC_BMIPS_BCM6318
default "bcm6328" if SOC_BMIPS_BCM6328
default "bcm6338" if SOC_BMIPS_BCM6338
default "bcm6348" if SOC_BMIPS_BCM6348
default "bcm6358" if SOC_BMIPS_BCM6358
+ default "bcm6368" if SOC_BMIPS_BCM6368
default "bcm63268" if SOC_BMIPS_BCM63268
choice
help
This supports BMIPS BCM3380 family.
+config SOC_BMIPS_BCM6318
+ bool "BMIPS BCM6318 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6318 family.
+
config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family"
select SUPPORTS_BIG_ENDIAN
help
This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+config SOC_BMIPS_BCM6368
+ bool "BMIPS BCM6368 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
+
config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family"
select SUPPORTS_BIG_ENDIAN
choice
prompt "Board select"
+config BOARD_COMTREND_AR5315U
+ bool "Comtrend AR-5315u"
+ depends on SOC_BMIPS_BCM6318
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Comtrend AR-5315u boards have a BCM6318 SoC with 64 MB of RAM and 16
+ MB of flash (SPI).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
+ a BCM43217 (PCIe).
+
config BOARD_COMTREND_AR5387UN
bool "Comtrend AR-5387un"
depends on SOC_BMIPS_BCM6328
ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
and a BCM6362 (integrated).
+config BOARD_COMTREND_WAP5813N
+ bool "Comtrend WAP-5813n board"
+ depends on SOC_BMIPS_BCM6368
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Comtrend WAP-5813n boards have a BCM6369 SoC with 64 MB of RAM and
+ 8 MB of flash (CFI).
+ Between its different peripherals there's a BCM53115 switch with 5
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
+ and a BCM4322 (miniPCI).
+
config BOARD_HUAWEI_HG556A
bool "Huawei EchoLife HG556a"
depends on SOC_BMIPS_BCM6358
config BMIPS_SUPPORTS_BOOT_RAM
bool
+source "board/comtrend/ar5315u/Kconfig"
source "board/comtrend/ar5387un/Kconfig"
source "board/comtrend/ct5361/Kconfig"
source "board/comtrend/vr3032u/Kconfig"
+source "board/comtrend/wap5813n/Kconfig"
source "board/huawei/hg556a/Kconfig"
source "board/netgear/cg3100d/Kconfig"
source "board/sagem/f@st1704/Kconfig"
#include <asm/mpc85xx_gpio.h>
#endif
-struct mpc85xx_gpio_plat {
+struct mpc8xxx_gpio_plat {
ulong addr;
unsigned long size;
uint ngpios;
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define CONFIG_SYS_BOOT_GET_CMDLINE
-#define CONFIG_SYS_BOOT_GET_KBD
#ifndef CONFIG_MAX_MEM_MAPPED
#if defined(CONFIG_E500) || \
#endif
-#ifndef CONFIG_MACH_SPECIFIC
-extern int _machine;
-extern int have_of;
-#endif /* CONFIG_MACH_SPECIFIC */
-
/* what kind of prep workstation we are */
extern int _prep_type;
/*
#endif /* ndef ASSEMBLY*/
-#ifdef CONFIG_MACH_SPECIFIC
-#if defined(CONFIG_WALNUT)
-#define _machine _MACH_walnut
-#define have_of 0
-#else
-#error "Machine not defined correctly"
-#endif
-#endif /* CONFIG_MACH_SPECIFIC */
-
#if defined(CONFIG_MPC85xx)
#define EPAPR_MAGIC (0x45504150)
#else
#include "hte.h"
#include "smc.h"
-/* t_rfc values (in picoseconds) per density */
-static const uint32_t t_rfc[5] = {
- 90000, /* 512Mb */
- 110000, /* 1Gb */
- 160000, /* 2Gb */
- 300000, /* 4Gb */
- 350000, /* 8Gb */
-};
-
/* t_ck clock period in picoseconds per speed index 800, 1066, 1333 */
static const uint32_t t_ck[3] = {
2500,
/* Global variables */
static const uint16_t ddr_wclk[] = {193, 158};
+#ifdef BACKUP_WCTL
static const uint16_t ddr_wctl[] = {1, 217};
+#endif
+#ifdef BACKUP_WCMD
static const uint16_t ddr_wcmd[] = {1, 220};
+#endif
#ifdef BACKUP_RCVN
static const uint16_t ddr_rcvn[] = {129, 498};
ulong write_acpi_tables(ulong start);
/**
+ * acpi_get_rsdp_addr() - get ACPI RSDP table address
+ *
+ * This routine returns the ACPI RSDP table address in the system memory.
+ *
+ * @return: ACPI RSDP table address
+ */
+ulong acpi_get_rsdp_addr(void);
+
+/**
* acpi_find_fadt() - find ACPI FADT table in the sytem memory
*
* This routine parses the ACPI table to locate the ACPI FADT table.
Return (STA_VISIBLE)
}
- Method (_CRS, 0, NotSerialized)
+ Method (_CRS, 0, Serialized)
{
Name (RBUF, ResourceTemplate ()
{
__u64 pref_address;
__u32 init_size;
__u32 handover_offset;
+ __u64 acpi_rsdp_addr;
} __attribute__((packed));
struct sys_desc_table {
*/
extern const unsigned char AmlCode[];
+/* ACPI RSDP address to be used in boot parameters */
+static ulong acpi_rsdp_addr;
+
static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
struct acpi_xsdt *xsdt)
{
}
/*
- * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/acpi_table.c
+ * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c
*/
ulong write_acpi_tables(ulong start)
{
debug("current = %x\n", current);
+ acpi_rsdp_addr = (unsigned long)rsdp;
debug("ACPI: done\n");
/* Don't touch ACPI hardware on HW reduced platforms */
return current;
}
+ulong acpi_get_rsdp_addr(void)
+{
+ return acpi_rsdp_addr;
+}
+
static struct acpi_rsdp *acpi_valid_rsdp(struct acpi_rsdp *rsdp)
{
if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0)
*/
#include <common.h>
+#include <asm/acpi_table.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/zimage.h>
hdr->setup_move_size = 0x9100;
}
-#if defined(CONFIG_INTEL_MID)
- hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
-#endif
-
/* build command line at COMMAND_LINE_OFFSET */
build_command_line(cmd_line, auto_boot);
}
+#ifdef CONFIG_INTEL_MID
+ if (bootproto >= 0x0207)
+ hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
+#endif
+
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+ if (bootproto >= 0x020e)
+ hdr->acpi_rsdp_addr = acpi_get_rsdp_addr();
+#endif
+
setup_video(&setup_base->screen_info);
return 0;
goto outahere;
}
if (chip1 == TMO) {
- rc = ERR_TIMOUT;
+ rc = ERR_TIMEOUT;
goto outahere;
}
--- /dev/null
+if BOARD_COMTREND_AR5315U
+
+config SYS_BOARD
+ default "ar5315u"
+
+config SYS_VENDOR
+ default "comtrend"
+
+config SYS_CONFIG_NAME
+ default "comtrend_ar5315u"
+
+endif
--- /dev/null
+COMTREND AR-5315U BOARD
+M: Álvaro Fernández Rojas <noltari@gmail.com>
+S: Maintained
+F: board/comtrend/ar-5315u/
+F: include/configs/comtrend_ar5315u.h
+F: configs/comtrend_ar5315u_ram_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ar-5315u.o
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
--- /dev/null
+if BOARD_COMTREND_WAP5813N
+
+config SYS_BOARD
+ default "wap5813n"
+
+config SYS_VENDOR
+ default "comtrend"
+
+config SYS_CONFIG_NAME
+ default "comtrend_wap5813n"
+
+endif
--- /dev/null
+COMTREND WAP-5813N BOARD
+M: Álvaro Fernández Rojas <noltari@gmail.com>
+S: Maintained
+F: board/comtrend/wap-5813n/
+F: include/configs/comtrend_wap-5813n.h
+F: configs/comtrend_wap5813n_ram_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wap-5813n.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
--- /dev/null
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_PDU001
+
+config SYS_BOARD
+ default "pdu001"
+
+config SYS_VENDOR
+ default "eets"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "pdu001"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 4
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. The best choice for the
+ PDU001 is UART3 as it is wired to the header K2; enter 4 here to
+ use UART3. UART0 is connected to the EIA-485 transceiver. If you
+ really need to use it, you are advised to remove the transceiver U14
+ from the board. UART1 is wired to the backplane and therefore
+ accessible from there or by the backplane connector K1 of the PDU.
+ Any other UART then UART3 (enter 4 here), UART1 (enter 2 here) or
+ UART0 (enter 1 here) are not sensible since they are not wired to
+ any connector and therefore difficult to access.
+
+choice
+ prompt "State of Run LED"
+ default PDU001_RUN_LED_RED
+ help
+ The PDU001 has a bi-color (red/green) LED labeled 'Run' which
+ can be used to indicate the operating state of the board. By
+ default it will be lit red by U-Boot. Later in the start-up
+ process it can be changed to green (or heartbeat or anything else)
+ by the kernel or some other software.
+
+config RUN_LED_RED
+ bool
+ prompt "Red"
+ help
+ Lit Run LED red.
+
+config RUN_LED_GREEN
+ bool
+ prompt "Green"
+ help
+ Lit Run LED green.
+
+config RUN_LED_OFF
+ bool
+ prompt "Off"
+ help
+ Do not lit Run LED.
+
+endchoice
+
+endif
--- /dev/null
+PDU001 BOARD
+M: Felix Brack <fb@ltec.ch>
+S: Maintained
+F: board/eets/pdu001/
+F: include/configs/pdu001.h
+F: configs/am335x_pdu001_defconfig
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Summary
+=======
+
+This document covers the PDU001 target.
+
+Hardware
+========
+
+The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
+manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
+SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
+AM3352 SOC from TI (http://www.ti.com).
+
+Customization
+=============
+
+As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice
+is 4 here since UART3 is wired to the connector K2.
+The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED
+or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn
+off the Run LED.
+
+Booting
+=======
+
+The system boots from either eMMC or SD card cage. It will first try to boot
+from the SD card cage. If this fails (missing or unbootable SD card) it will
+try to boot from the internal eMMC. The root file system is always expected to
+be located in the second partition of the device (eMMC or SD card) that pro-
+vided the boot loader.
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for EETS PDU001 board
+ *
+ * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <i2c.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <debug_uart.h>
+#include <dm/ofnode.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_ADDR_NODE_ID 0x50
+#define I2C_REG_NODE_ID_BASE 0xfa
+#define NODE_ID_BYTE_COUNT 6
+
+#define I2C_ADDR_LEDS 0x60
+#define I2C_REG_RUN_LED 0x06
+#define RUN_LED_OFF 0x0
+#define RUN_LED_RED 0x1
+#define RUN_LED_GREEN (0x1 << 2)
+
+#define VDD_MPU_REGULATOR "regulator@2"
+#define VDD_CORE_REGULATOR "regulator@3"
+#define DEFAULT_CORE_VOLTAGE 1137500
+
+/*
+ * boot device save register
+ * -------------------------
+ * The boot device can be quired by 'spl_boot_device()' in
+ * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
+ * environment here. In turn 'spl_boot_device' can't be called in
+ * 'board_late_init' which allows writing to u-boot environment.
+ * To get the boot device from 'am33xx_spl_board_init' to
+ * 'board_late_init' we therefore use a scratch register from the RTC.
+ */
+#define CONFIG_SYS_RTC_SCRATCH0 0x60
+#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
+
+#ifdef CONFIG_SPL_BUILD
+static void save_boot_device(void)
+{
+ *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
+}
+#endif
+
+u32 boot_device(void)
+{
+ return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
+}
+
+/* Store the boot device in the environment variable 'boot_device' */
+static void env_set_boot_device(void)
+{
+ switch (boot_device()) {
+ case BOOT_DEVICE_MMC1: {
+ env_set("boot_device", "emmc");
+ break;
+ }
+ case BOOT_DEVICE_MMC2: {
+ env_set("boot_device", "sdcard");
+ break;
+ }
+ default: {
+ env_set("boot_device", "unknown");
+ break;
+ }
+ }
+}
+
+static void set_run_led(struct udevice *dev)
+{
+ int val = RUN_LED_OFF;
+
+ if (IS_ENABLED(CONFIG_RUN_LED_RED))
+ val = RUN_LED_RED;
+ else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
+ val = RUN_LED_GREEN;
+
+ dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
+}
+
+/* Set 'serial#' to the EUI-48 value of board node ID chip */
+static void env_set_serial(struct udevice *dev)
+{
+ int val;
+ char serial[2 * NODE_ID_BYTE_COUNT + 1];
+ int n;
+
+ for (n = 0; n < sizeof(serial); n += 2) {
+ val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
+ sprintf(serial + n, "%02X", val);
+ }
+ serial[2 * NODE_ID_BYTE_COUNT] = '\0';
+ env_set("serial#", serial);
+}
+
+static void set_mpu_and_core_voltage(void)
+{
+ int mpu_vdd;
+ int sil_rev;
+ struct udevice *dev;
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ /*
+ * The PDU001 (more precisely the computing module m2) uses a
+ * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
+ * voltage of 1.1375V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+
+ /*
+ * Depending on MPU clock and PG we will need a different VDD
+ * to drive at that speed.
+ */
+ sil_rev = readl(&cdev->deviceid) >> 28;
+ mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
+
+ /* first update the MPU voltage */
+ if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
+ if (regulator_set_value(dev, mpu_vdd))
+ debug("failed to set MPU voltage\n");
+ } else {
+ debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
+ }
+
+ /* second update the CORE voltage */
+ if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
+ if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
+ debug("failed to set CORE voltage\n");
+ } else {
+ debug("invalid CORE voltage ragulator %s\n",
+ VDD_CORE_REGULATOR);
+ }
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#define OSC (V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC - 1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC - 1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+ /* save boot device for later use by 'board_late_init' */
+ save_boot_device();
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ return &dpll_ddr;
+}
+
+void set_mux_conf_regs(void)
+{
+ /* done first by the ROM and afterwards by the pin controller driver */
+ enable_i2c0_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifdef CONFIG_DEBUG_UART
+void board_debug_uart_init(void)
+{
+ /* done by pin controller driver if not debugging */
+ enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ struct udevice *dev;
+
+ set_mpu_and_core_voltage();
+ env_set_boot_device();
+
+ /* second I2C bus connects to node ID and front panel LED chip */
+ if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
+ set_run_led(dev);
+ if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
+ env_set_serial(dev);
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * board.h
+ *
+ * EETS GmbH PDU001 board information header
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have two pin mux functions that must exist. First we need I2C0 to
+ * access the TPS65910 PMIC located on the M2 computing module.
+ * Second, if we want low-level debugging or a early UART (ie. before the
+ * pin controller driver is running), we need one of the UART ports UART0 to
+ * UART5 (usually UART3 since it is wired to K2).
+ * In case of I2C0 access we explicitly don't rely on the the ROM but we could
+ * do so as we use the primary mode (mode 0) for I2C0.
+ * All other multiplexing and pin configuration is done by the DT once it
+ * gets parsed by the pin controller driver.
+ * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
+ * as MMC1 (microSD card-cage) since these are our boot devices.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_uart_pin_mux(u32 addr);
+void enable_i2c0_pin_mux(void);
+
+#endif
--- /dev/null
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_uart_pin_mux(u32 addr)
+{
+ switch (addr) {
+ case CONFIG_SYS_NS16550_COM1:
+ enable_uart0_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM2:
+ enable_uart1_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM3:
+ enable_uart2_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM4:
+ enable_uart3_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM5:
+ enable_uart4_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM6:
+ enable_uart5_pin_mux();
+ break;
+ }
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
F: board/emulation/qemu-arm/
F: include/configs/qemu-arm.h
F: configs/qemu_arm_defconfig
+F: configs/qemu_arm64_defconfig
#include <common.h>
#include <fdtdec.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region qemu_arm64_mem_map[] = {
+ {
+ /* Flash */
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x08000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Peripherals */
+ .virt = 0x08000000UL,
+ .phys = 0x08000000UL,
+ .size = 0x38000000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0xc0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = qemu_arm64_mem_map;
+#endif
+
int board_init(void)
{
return 0;
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
+ select CMD_EXT4 if ARM
+ select CMD_EXT4_WRITE if ARM
bool
default y
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
+
+config VOL_MONITOR_LTC3882_READ
+ depends on VID
+ bool "Enable the LTC3882 voltage monitor read"
+ default n
+ help
+ This option enables LTC3882 voltage monitor read
+ functionality. It is used by common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+ depends on VID
+ bool "Enable the LTC3882 voltage monitor set"
+ default n
+ help
+ This option enables LTC3882 voltage monitor set
+ functionality. It is used by common VID driver.
obj-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
-obj-$(CONFIG_VID) += vid.o
endif
+obj-$(CONFIG_VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
ifndef CONFIG_SPL_BUILD
return 0;
}
+#ifndef CONFIG_SPL_BUILD
static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
"Put the core in spin loop (Secure Boot Only)",
""
);
+#endif
#include <common.h>
#include <command.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <linux/time.h>
#include <i2c.h>
#include "qixis.h"
}
#endif
-void qixis_reset(void)
+#ifndef CONFIG_SPL_BUILD
+static void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
}
-void qixis_bank_reset(void)
+static void qixis_bank_reset(void)
{
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
}
-static void __qixis_dump_switch(void)
+void __weak qixis_dump_switch(void)
{
puts("Reverse engineering switch is not implemented for this board\n");
}
-void qixis_dump_switch(void)
- __attribute__((weak, alias("__qixis_dump_switch")));
-
-int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
#else
printf("Not implemented\n");
#endif
+ } else if (strcmp(argv[1], "ifc") == 0) {
+#ifdef QIXIS_LBMAP_IFC
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_IFC);
+ set_rcw_src(QIXIS_RCW_SRC_IFC);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "emmc") == 0) {
+#ifdef QIXIS_LBMAP_EMMC
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_EMMC);
+ set_rcw_src(QIXIS_RCW_SRC_EMMC);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf("Not implemented\n");
+#endif
} else if (strcmp(argv[1], "sd_qspi") == 0) {
#ifdef QIXIS_LBMAP_SD_QSPI
QIXIS_WRITE(rst_ctl, 0x30);
"qixis_reset dump - display the QIXIS registers\n"
"qixis_reset switch - display switch\n"
);
+#endif
}
/*
+ * Board specific settings for specific voltage value
+ */
+int __weak board_adjust_vdd(int vdd)
+{
+ return 0;
+}
+
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
+/*
* Get the i2c address configuration for the IR regulator chip
*
* There are some variance in the RDB HW regarding the I2C address configuration
}
return -1;
}
+#endif
/* Maximum loop count waiting for new voltage to take effect */
#define MAX_LOOP_WAIT_NEW_VOL 100
}
#endif
+#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
+/* read the current value of the LTC Regulator Voltage */
+static int read_voltage_from_LTC(int i2caddress)
+{
+ int ret, vcode = 0;
+ u8 chan = PWM_CHANNEL0;
+
+ /* select the PAGE 0 using PMBus commands PAGE for VDD*/
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_PAGE, 1, &chan, 1);
+ if (ret) {
+ printf("VID: failed to select VDD Page 0\n");
+ return ret;
+ }
+
+ /*read the output voltage using PMBus command READ_VOUT*/
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+
+ /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */
+ vcode = DIV_ROUND_UP(vcode * 1000, 4096);
+
+ return vcode;
+}
+#endif
+
static int read_voltage(int i2caddress)
{
int voltage_read;
voltage_read = read_voltage_from_INA220(i2caddress);
#elif defined CONFIG_VOL_MONITOR_IR36021_READ
voltage_read = read_voltage_from_IR(i2caddress);
+#elif defined CONFIG_VOL_MONITOR_LTC3882_READ
+ voltage_read = read_voltage_from_LTC(i2caddress);
#else
return -1;
#endif
return voltage_read;
}
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
/*
* We need to calculate how long before the voltage stops to drop
* or increase. It returns with the loop count. Each loop takes
return vdd_current;
}
-#ifdef CONFIG_VOL_MONITOR_IR36021_SET
/* Set the voltage to the IR chip */
static int set_voltage_to_IR(int i2caddress, int vdd)
{
debug("VID: Current voltage is %d mV\n", vdd_last);
return vdd_last;
}
+
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
+/* this function sets the VDD and returns the value set */
+static int set_voltage_to_LTC(int i2caddress, int vdd)
+{
+ int ret, vdd_last, vdd_target = vdd;
+
+ /* Scale up to the LTC resolution is 1/4096V */
+ vdd = (vdd * 4096) / 1000;
+
+ /* 5-byte buffer which needs to be sent following the
+ * PMBus command PAGE_PLUS_WRITE.
+ */
+ u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
+ vdd & 0xFF, (vdd & 0xFF00) >> 8};
+
+ /* Write the desired voltage code to the regulator */
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+ if (ret) {
+ printf("VID: I2C failed to write to the volatge regulator\n");
+ return -1;
+ }
+
+ /* Wait for the volatge to get to the desired value */
+ do {
+ vdd_last = read_voltage_from_LTC(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjust\n");
+ return -1;
+ }
+ } while (vdd_last != vdd_target);
+
+ return vdd_last;
+}
#endif
static int set_voltage(int i2caddress, int vdd)
#ifdef CONFIG_VOL_MONITOR_IR36021_SET
vdd_last = set_voltage_to_IR(i2caddress, vdd);
+#elif defined CONFIG_VOL_MONITOR_LTC3882_SET
+ vdd_last = set_voltage_to_LTC(i2caddress, vdd);
#else
#error Specific voltage monitor must be defined
#endif
int re_enable = disable_interrupts();
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 fusesr;
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
u8 vid, buf;
+#else
+ u8 vid;
+#endif
int vdd_target, vdd_current, vdd_last;
int ret, i2caddress;
unsigned long vdd_string_override;
char *vdd_string;
+#ifdef CONFIG_ARCH_LS1088A
+ static const uint16_t vdd[32] = {
+ 10250,
+ 9875,
+ 9750,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 9000,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+
+#else
static const uint16_t vdd[32] = {
10500,
0, /* reserved */
0, /* reserved */
0, /* reserved */
};
+#endif
struct vdd_drive {
u8 vid;
unsigned voltage;
ret = -1;
goto exit;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
ret = -1;
goto exit;
}
+#endif
/* get the voltage ID from fuse status register */
fusesr = in_le32(&gur->dcfg_fusesr);
}
vdd_current = vdd_last;
debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+
+#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
+ /* Set the target voltage */
+ vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
+#else
/*
* Adjust voltage to at or one step above target.
* As measurements are less precise than setting the values
vdd_last = set_voltage(i2caddress, vdd_current);
}
+#endif
+ if (board_adjust_vdd(vdd_target) < 0) {
+ ret = -1;
+ goto exit;
+ }
+
if (vdd_last > 0)
printf("VID: Core voltage after adjustment is at %d mV\n",
vdd_last);
ret = -1;
goto exit;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
ret = -1;
goto exit;
}
+#endif
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
debug("VID : I2c failed to switch channel\n");
return -1;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
+#endif
/*
* Read voltage monitor to check real voltage.
source "board/freescale/common/Kconfig"
endif
+
+if TARGET_LS1012A2G5RDB
+
+config SYS_BOARD
+ default "ls1012ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012a2g5rdb"
+
+source "board/freescale/common/Kconfig"
+
+endif
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+LS1012A2G5RDB BOARD
+M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+S: Maintained
+F: board/freescale/ls1012ardb/
+F: include/configs/ls1012a2g5rdb.h
+F: configs/ls1012a2g5rdb_qspi_defconfig
U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
+
+LS1012A2G5RDB board Overview
+-----------------------
+ - SERDES Connections, 3 lanes supporting:
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+ - QSPI NOR flash memory
+ - USB 3.0
+ - one high-speed USB 2.0/3.0 port.
+ - SDIO WiFi, SPI
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - The LS1012A processor consists of two UART controllers,
+ out of which only UART1 is used on 2G5RDB.
+ - ARM JTAG support
+
+Major Difference between LS1012ARDB and LS1012A-2G5RDB
+------------------------------------------------------
+1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
+2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
+ of LS1012ARDB
+3. LS1012A-2G5RDB is not having Arduino header
+4. LS1012A-2G5RDB doesn't have PCI slot
+
+Booting Options
+---------------
+QSPI Flash
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4030_0000
+PPA FIT image | 2MB | 0x4040_0000
+PFE firmware | 20K | 0x00a0_0000
+Linux ITB | ~53MB | 0x4100_0000
int checkboard(void)
{
+#ifdef CONFIG_TARGET_LS1012ARDB
u8 in1;
puts("Board: LS1012ARDB ");
puts(": bank2\n");
else
puts("unknown\n");
+#else
+ puts("Board: LS1012A2G5RDB ");
+#endif
return 0;
}
return 0;
}
+#ifdef CONFIG_TARGET_LS1012ARDB
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc1_path[] = "/soc/esdhc@1580000";
if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
sdhc2_en = true;
}
-
if (sdhc2_en)
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
sizeof("okay"), 1);
sizeof("disabled"), 1);
return 0;
}
+#endif
int ft_board_setup(void *blob, bd_t *bd)
{
};
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-static void convert_serdes_mux(int type, int need_reset);
-
-void cpld_show(void)
+static void cpld_show(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
}
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+static void convert_serdes_mux(int type, int need_reset)
+{
+ char current_serdes;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ current_serdes = cpld_data->serdes_mux;
+
+ switch (type) {
+ case LANEB_SATA:
+ current_serdes &= ~MASK_LANE_B;
+ break;
+ case LANEB_SGMII1:
+ current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+ break;
+ case LANEC_SGMII1:
+ current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+ break;
+ case LANED_SGMII2:
+ current_serdes |= MASK_LANE_D;
+ break;
+ case LANEC_PCIEX1:
+ current_serdes |= MASK_LANE_C;
+ break;
+ case (LANED_PCIEX2 | LANEC_PCIEX1):
+ current_serdes |= MASK_LANE_C;
+ current_serdes &= ~MASK_LANE_D;
+ break;
+ default:
+ printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
+ return;
+ }
+
+ cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
+ cpld_data->serdes_mux = current_serdes;
+
+ if (need_reset == 1) {
+ printf("Reset board to enable configuration\n");
+ cpld_data->system_rst = CONFIG_RESET;
+ }
+}
+
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
+ && !defined(CONFIG_SPL_BUILD)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
);
-static void convert_serdes_mux(int type, int need_reset)
-{
- char current_serdes;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- current_serdes = cpld_data->serdes_mux;
-
- switch (type) {
- case LANEB_SATA:
- current_serdes &= ~MASK_LANE_B;
- break;
- case LANEB_SGMII1:
- current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
- break;
- case LANEC_SGMII1:
- current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
- break;
- case LANED_SGMII2:
- current_serdes |= MASK_LANE_D;
- break;
- case LANEC_PCIEX1:
- current_serdes |= MASK_LANE_C;
- break;
- case (LANED_PCIEX2 | LANEC_PCIEX1):
- current_serdes |= MASK_LANE_C;
- current_serdes &= ~MASK_LANE_D;
- break;
- default:
- printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
- return;
- }
-
- cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
- cpld_data->serdes_mux = current_serdes;
-
- if (need_reset == 1) {
- printf("Reset board to enable configuration\n");
- cpld_data->system_rst = CONFIG_RESET;
- }
-}
-
-void print_serdes_mux(void)
+static void print_serdes_mux(void)
{
char current_serdes;
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
+{
+ int vdd;
+
+ vdd = get_core_volt_from_fuse();
+ /* Nothing to do for silicons doesn't support VID */
+ if (vdd < 0)
+ return;
+
+ if (vdd == 900) {
+ popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
+ debug("VID: configure DDR to support 900 mV\n");
+ }
+}
+#endif
+
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
popts->addr_hash = 1;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ fsl_ddr_setup_0v9_volt(popts);
+#endif
+
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
}
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
+#include "../common/vid.h"
+#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+#if defined(CONFIG_VID)
+int init_func_vid(void)
+{
+ if (adjust_vdd(0) < 0)
+ printf("core voltage not adjusted\n");
+
+ return 0;
+}
+#endif
+
#if !defined(CONFIG_SPL_BUILD)
int checkboard(void)
{
return 66666666;
}
+#endif
int select_i2c_ch_pca9547(u8 ch)
{
return 0;
}
+#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)
{
u8 reg;
return 0;
}
#endif
+#endif
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+/* read the current value(SVDD) of the LTM Regulator Voltage */
+int get_serdes_volt(void)
+{
+ int ret, vcode = 0;
+ u8 chan = PWM_CHANNEL0;
+
+ /* Select the PAGE 0 using PMBus commands PAGE for VDD */
+ ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
+ PMBUS_CMD_PAGE, 1, &chan, 1);
+ if (ret) {
+ printf("VID: failed to select VDD Page 0\n");
+ return ret;
+ }
+
+ /* Read the output voltage using PMBus command READ_VOUT */
+ ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
+ PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+
+ return vcode;
+}
+
+int set_serdes_volt(int svdd)
+{
+ int ret, vdd_last;
+ u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
+ svdd & 0xFF, (svdd & 0xFF00) >> 8};
+
+ /* Write the desired voltage code to the SVDD regulator */
+ ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
+ PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+ if (ret) {
+ printf("VID: I2C failed to write to the volatge regulator\n");
+ return -1;
+ }
+ /* Wait for the volatge to get to the desired value */
+ do {
+ vdd_last = get_serdes_volt();
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjust\n");
+ return -1;
+ }
+ } while (vdd_last != svdd);
+
+ return 1;
+}
+#else
+int get_serdes_volt(void)
+{
+ return 0;
+}
+
+int set_serdes_volt(int svdd)
+{
+ int ret;
+ u8 brdcfg4;
+
+ printf("SVDD changing of RDB\n");
+
+ /* Read the BRDCFG54 via CLPD */
+ ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+ QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+ if (ret) {
+ printf("VID: I2C failed to read the CPLD BRDCFG4\n");
+ return -1;
+ }
+
+ brdcfg4 = brdcfg4 | 0x08;
+
+ /* Write to the BRDCFG4 */
+ ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+ QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+ if (ret) {
+ debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
+ return -1;
+ }
+
+ /* Wait for the volatge to get to the desired value */
+ udelay(10000);
+
+ return 1;
+}
+#endif
+
+/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
+int board_adjust_vdd(int vdd)
+{
+ int ret = 0;
+
+ debug("%s: vdd = %d\n", __func__, vdd);
+
+ /* Special settings to be performed when voltage is 900mV */
+ if (vdd == 900) {
+ ret = setup_serdes_volt(vdd);
+ if (ret < 0) {
+ ret = -1;
+ goto exit;
+ }
+ }
+exit:
+ return ret;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
int board_init(void)
{
init_final_memctl_regs();
#ifdef CONFIG_TARGET_LS2081ARDB
#ifdef CONFIG_FSL_QIXIS
sw = QIXIS_READ(arch);
- printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, ", (sw & 0xf) + 'A');
sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+ sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
switch (sw) {
case 0:
puts("boot from QSPI DEV#0\n");
printf("invalid setting of SW%u\n", sw);
break;
}
+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif
puts("SERDES1 Reference : ");
printf("Clock1 = 100MHz ");
1.2 Configuration settings for M52277EVB Development Board
CONFIG_MCF5227x -- define for all MCF5227x CPUs
CONFIG_M52277 -- define for all Freescale MCF52277 CPUs
-CONFIG_M52277EVB -- define for M52277EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
CONFIG_MCF52x2 Processor family
CONFIG_MCF5253 MCF5253 specific
- CONFIG_M5253EVBE Amadeus Plus board specific
CONFIG_SYS_CLK Define Amadeus Plus CPU Clock
CONFIG_SYS_MBAR MBAR base address
CONFIG_SYS_MBAR2 MBAR2 base address
CONFIG_MPC83xx MPC83xx family
CONFIG_MPC8349 MPC8349 specific
CONFIG_MPC8349ITX MPC8349E-mITX
- CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
5. Compilation
return 0;
}
+#ifndef CONFIG_SPL_BUILD
static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
"configure multiplexing pin for IFC/SDHC bus in runtime",
"bus_type (e.g. mux sdhc)"
);
+#endif
config TARGET_CHROMEBOX_PANTHER
bool "Chromebox panther (not available)"
- select n
help
Note: At present this must be used with coreboot. See README.x86
for instructions.
#
quiet_cmd_srec_cat = SRECCAT $@
- cmd_srec_cat = srec_cat -output $@ -$2 $< -binary -offset $3
+ cmd_srec_cat = srec_cat -output $@ -$2 \
+ $< -binary \
+ -fill 0x00 -within $< -binary -range-pad 16 \
+ -offset $3
u-boot.mcs: u-boot.bin
$(call cmd,srec_cat,intel,0x7c00000)
DECLARE_GLOBAL_DATA_PTR;
-/* This is only needed until SPL gets OF support */
-#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata omap3logic_serial = {
- .base = OMAP34XX_UART1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(omap3logic_uart) = {
- "ns16550_serial",
- &omap3logic_serial
-};
-#endif
-
/*
* two dimensional array of strucures containining board name and Linux
* machine IDs; row it selected based on CPU column is slected based
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
+ MUX_VAL(CP(I2C1_SCL), (IEN | EN | M0)); /*I2C1_SCL*/
+ MUX_VAL(CP(I2C1_SDA), (IEN | EN | M0)); /*I2C1_SDA*/
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
+ MUX_VAL(CP(I2C2_SCL), (IEN | EN | M0)); /*I2C2_SCL*/
+ MUX_VAL(CP(I2C2_SDA), (IEN | EN | M0)); /*I2C2_SDA*/
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
+ MUX_VAL(CP(I2C3_SCL), (IEN | EN | M0)); /*I2C3_SCL*/
+ MUX_VAL(CP(I2C3_SDA), (IEN | EN | M0)); /*I2C3_SDA*/
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /*I2C4_SCL*/
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /*I2C4_SDA*/
+ MUX_VAL(CP(I2C4_SCL), (IEN | EN | M0)); /*I2C4_SCL*/
+ MUX_VAL(CP(I2C4_SDA), (IEN | EN | M0)); /*I2C4_SDA*/
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/
#include <asm/armv8/mmu.h>
#endif
#include <watchdog.h>
+#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
printf("RPI %s (0x%x)\n", model->name, revision);
}
-#ifndef CONFIG_PL01X_SERIAL
-static bool rpi_is_serial_active(void)
-{
- int serial_gpio = 15;
- struct udevice *dev;
-
- /*
- * The RPi3 disables the mini uart by default. The easiest way to find
- * out whether it is available is to check if the RX pin is muxed.
- */
-
- if (uclass_first_device(UCLASS_GPIO, &dev) || !dev)
- return true;
-
- if (bcm2835_gpio_get_func_id(dev, serial_gpio) != BCM2835_GPIO_ALT5)
- return false;
-
- return true;
-}
-
-/* Disable mini-UART I/O if it's not pinmuxed to our pins.
- * The firmware only enables it if explicitly done in config.txt: enable_uart=1
- */
-static void rpi_disable_inactive_uart(void)
-{
- struct udevice *dev;
- struct bcm283x_mu_serial_platdata *plat;
-
- if (uclass_get_device_by_driver(UCLASS_SERIAL,
- DM_GET_DRIVER(serial_bcm283x_mu),
- &dev) || !dev)
- return;
-
- if (!rpi_is_serial_active()) {
- plat = dev_get_platdata(dev);
- plat->disabled = true;
- }
-}
-#endif
-
int board_init(void)
{
#ifdef CONFIG_HW_WATCHDOG
hw_watchdog_init();
#endif
-#ifndef CONFIG_PL01X_SERIAL
- rpi_disable_inactive_uart();
-#endif
get_board_rev();
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := porter.o qos.o ../rcar-common/common.o
+obj-y := porter.o qos.o
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI2_MSTP311 (1 << 11)
-#define SCIF0_MSTP721 (1 << 21)
-#define ETHER_MSTP813 (1 << 13)
+#define TMU0_MSTP125 BIT(25)
#define SD2CKCR 0xE615026C
#define SD_97500KHZ 0x7
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* SDHI */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311);
-
/*
* SD0 clock is set to 97.5MHz by default.
* Set SD2 to the 97.5MHz as well.
return 0;
}
-/* LSI pin pull-up control */
-#define PUPR5 0xe6060114
-#define PUPR5_ETH 0x3FFC0000
-#define PUPR5_ETH_MAGIC (1 << 27)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7791_pinmux_init();
-
- /* Ether Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
-
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
- gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
-
- gpio_direction_output(GPIO_GP_5_22, 0);
- mdelay(20);
- gpio_set_value(GPIO_GP_5_22, 1);
- udelay(1);
-
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
-#ifdef CONFIG_SH_ETHER
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
-
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- return ret;
-#else
return 0;
-#endif
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DATA0, NULL);
- gpio_request(GPIO_FN_SD0_DATA1, NULL);
- gpio_request(GPIO_FN_SD0_DATA2, NULL);
- gpio_request(GPIO_FN_SD0_DATA3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DATA0, NULL);
- gpio_request(GPIO_FN_SD2_DATA1, NULL);
- gpio_request(GPIO_FN_SD2_DATA2, NULL);
- gpio_request(GPIO_FN_SD2_DATA3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
-
- /* SDHI 0 */
- gpio_request(GPIO_GP_2_12, NULL);
- gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI 2 */
- gpio_request(GPIO_GP_2_26, NULL);
- gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
-}
-
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ fdtdec_setup_memory_banksize();
return 0;
}
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}
-
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = CONFIG_P_CLK_FREQ,
-};
-
-U_BOOT_DEVICE(porter_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
{
int node;
struct rv1108_grf *grf;
+ enum {
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
+
+ GPIO2D2_SHIFT = 4,
+ GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
+ GPIO2D2_GPIO = 0,
+ GPIO2D2_UART2_SOUT_M0,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART2_SIN_M0,
+ };
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
/* start auto calibration */
setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
- ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+ ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
if (ret)
goto adc_exit;
writel(0, b + ADCx_HC0);
/* wait for conversion */
- ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+ ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
if (ret)
goto adc_exit;
--- /dev/null
+if TARGET_STM32F429_EVALUATION
+
+config SYS_BOARD
+ string
+ default "stm32f429-evaluation"
+
+config SYS_VENDOR
+ string
+ default "st"
+
+config SYS_SOC
+ string
+ default "stm32f4"
+
+config SYS_CONFIG_NAME
+ string
+ default "stm32f429-evaluation"
+
+endif
--- /dev/null
+STM32F429-EVALUATION BOARD
+M: Patrice Chotard <patrice.chotard@st.com>
+S: Maintained
+F: board/st/stm32f429-evaluation/
+F: include/configs/stm32f429-evaluation.h
+F: configs/stm32f429-evaluation_defconfig
--- /dev/null
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := stm32f429-evaluation.o
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+ if (fdtdec_setup_memory_size() != 0)
+ rv = -EINVAL;
+
+ return rv;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char serialno[25];
+ u32 u_id_low, u_id_mid, u_id_high;
+
+ if (!env_get("serial#")) {
+ u_id_low = readl(&STM32_U_ID->u_id_low);
+ u_id_mid = readl(&STM32_U_ID->u_id_mid);
+ u_id_high = readl(&STM32_U_ID->u_id_high);
+ sprintf(serialno, "%08x%08x%08x",
+ u_id_high, u_id_mid, u_id_low);
+ env_set("serial#", serialno);
+ }
+
+ return 0;
+}
+#endif
return 0;
}
-#ifdef CONFIG_ETH_DESIGNWARE
-static int stmmac_setup(void)
-{
- clock_setup(SYSCFG_CLOCK_CFG);
- /* Set >RMII mode */
- STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
- clock_setup(STMMAC_CLOCK_CFG);
-
- return 0;
-}
-
int board_early_init_f(void)
{
- stmmac_setup();
-
return 0;
}
-#endif
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+#ifdef CONFIG_ETH_DESIGNWARE
+ /* Set >RMII mode */
+ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
+#endif
+
return 0;
}
#endif
}
+#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ switch (prio) {
+ case 0:
+ return ENVL_FAT;
+
+ case 1:
+ return ENVL_MMC;
+
+ default:
+ return ENVL_UNKNOWN;
+ }
+}
+#endif
+
/* add board specific code here */
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
+ /*
+ * Call this to initialize *ctrl again
+ */
+ hw_data_init();
+
/* Clear all important bits for DSS errata that may need to be tweaked*/
mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
MREQPRIO_0_SAB_INIT0_MASK;
#define board_is_am572x_evm_reva3() \
(board_ti_is("AM572PM_") && \
!strncmp("A.30", board_ti_get_rev(), 3))
+#define board_is_am574x_idk() board_ti_is("AM574IDK")
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
.is_ma_present = 0x1
};
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+ .dmm_lisa_map_2 = 0xc0600200,
+ .dmm_lisa_map_3 = 0x80600100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
if (board_is_am571x_idk())
*dmm_lisa_regs = &am571x_idk_lisa_regs;
+ else if (board_is_am574x_idk())
+ *dmm_lisa_regs = &am574x_idk_lisa_regs;
else
*dmm_lisa_regs = &beagle_x15_lisa_regs;
}
.ref_ctrl = 0x0000514d,
.ref_ctrl_final = 0x0000144a,
.sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
+ .sdram_tim2 = 0x30b37fe3,
+ .sdram_tim3 = 0x409f8ad8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
+ .sdram_config_init = 0x61863332,
+ .sdram_config = 0x61863332,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x0000514d,
+ .ref_ctrl_final = 0x0000144a,
+ .sdram_tim1 = 0xd333887c,
+ .sdram_tim2 = 0x30b37fe3,
+ .sdram_tim3 = 0x409f8ad8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400f,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400f,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305,
+ .emif_ecc_ctrl_reg = 0xD0000001,
+ .emif_ecc_address_range_1 = 0x3FFF0000,
+ .emif_ecc_address_range_2 = 0x00000000
+};
+
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
if (board_is_am571x_idk())
*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+ else if (board_is_am574x_idk())
+ *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
else
*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
break;
case 2:
- *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ if (board_is_am574x_idk())
+ *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+ else
+ *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
break;
}
}
bname = "BeagleBoard X15";
else if (board_is_am572x_evm())
bname = "AM572x EVM";
+ else if (board_is_am574x_idk())
+ bname = "AM574x IDK";
else if (board_is_am572x_idk())
bname = "AM572x IDK";
else if (board_is_am571x_idk())
name = "am57xx_evm_reva3";
else
name = "am57xx_evm";
+ } else if (board_is_am574x_idk()) {
+ name = "am574x_idk";
} else if (board_is_am572x_idk()) {
name = "am572x_idk";
} else if (board_is_am571x_idk()) {
void vcores_init(void)
{
- if (board_is_am572x_idk())
+ if (board_is_am572x_idk() || board_is_am574x_idk())
*omap_vcores = &am572x_idk_volts;
else if (board_is_am571x_idk())
*omap_vcores = &am571x_idk_volts;
*prcm = &dra7xx_prcm;
if (is_dra72x())
*dplls_data = &dra72x_dplls;
+ else if (is_dra76x())
+ *dplls_data = &dra76x_dplls;
else
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
iod = iodelay_cfg_array_am572x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+ } else if (board_is_am574x_idk()) {
+ pconf = core_padconf_array_essential_am574x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
+ iod = iodelay_cfg_array_am574x_idk;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
} else if (board_is_am571x_idk()) {
pconf = core_padconf_array_essential_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
writel(ctrl_val, (*ctrl)->control_core_control_io1);
/* The phy address for the AM57xx IDK are different than x15 */
- if (board_is_am572x_idk() || board_is_am571x_idk()) {
+ if (board_is_am572x_idk() || board_is_am571x_idk() ||
+ board_is_am574x_idk()) {
cpsw_data.slave_data[0].phy_addr = 0;
cpsw_data.slave_data[1].phy_addr = 1;
}
return 0;
} else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
return 0;
+ } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
+ return 0;
} else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
return 0;
}
{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
};
+const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = {
+ {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
+ {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
+ {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
+ {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
+ {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
+ {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
+ {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
+ {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
+ {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
+ {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
+ {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
+ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR4, (M14 | PIN_INPUT)}, /* mcasp2_axr4.gpio1_4 */
+ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
+ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
+ {MCASP2_AXR7, (M14 | PIN_INPUT)}, /* mcasp2_axr7.gpio1_5 */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
+ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
+ {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
+ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
+ {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
+ {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
+ {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
+ {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
+ {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
+ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
+ {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
+};
+
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
{0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */
};
+const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = {
+ {0x0114, 2199, 621}, /* CFG_GPMC_A0_IN */
+ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2133, 859}, /* CFG_GPMC_A11_IN */
+ {0x0138, 2258, 562}, /* CFG_GPMC_A12_IN */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0198, 1989, 612}, /* CFG_GPMC_A1_IN */
+ {0x0204, 2218, 912}, /* CFG_GPMC_A2_IN */
+ {0x0210, 2168, 963}, /* CFG_GPMC_A3_IN */
+ {0x021C, 2196, 813}, /* CFG_GPMC_A4_IN */
+ {0x0228, 2082, 782}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2098, 407}, /* CFG_GPMC_A6_IN */
+ {0x0240, 2343, 585}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2030, 685}, /* CFG_GPMC_A8_IN */
+ {0x0258, 2116, 832}, /* CFG_GPMC_A9_IN */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0590, 1000, 3900}, /* CFG_MCASP5_ACLKX_OUT */
+ {0x05AC, 1000, 3800}, /* CFG_MCASP5_FSX_IN */
+ {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
+ {0x0B30, 0, 200}, /* CFG_VIN2A_D5_OUT */
+ {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
+ {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
+ {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
+ {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
+ {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
+ {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
+ {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
+ {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
+ {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
+ {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
+ {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
+ {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
+ {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
+ {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
+ {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
+ {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
+ {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
+ {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
+ {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
+ {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
+ {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
+ {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
+ {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
+ {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
+ {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
+ {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
+ {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
+ {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
+};
+
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
{0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */
{0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
return 0;
}
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
/*
* Routine: get_board_revision
* Description: Detect if we are running on a Beagle revision Ax/Bx,
break;
}
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
if (emif_nr == 1)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
name = "dra71x";
else
name = "dra72x";
- } else if (is_dra76x()) {
- name = "dra76x";
+ } else if (is_dra76x_abz()) {
+ name = "dra76x_abz";
+ } else if (is_dra76x_acd()) {
+ name = "dra76x_acd";
} else {
name = "dra7xx";
}
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
break;
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
pads = dra76x_core_padconf_array;
npads = ARRAY_SIZE(dra76x_core_padconf_array);
break;
default:
case DRA752_ES2_0:
+ case DRA762_ABZ_ES1_0:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
do_set_mux32((*ctrl)->control_padconf_core_base,
delta_pads, delta_npads);
+ if (is_dra76x())
+ /* Set mux for MCAN instead of DCAN1 */
+ clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
+ MCAN_SEL_ALT_MASK, MCAN_SEL);
+
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
- } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+ } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
return 0;
- } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
+ } else if (!is_dra72x() && !is_dra76x_acd() &&
+ !strcmp(name, "dra7-evm")) {
return 0;
}
{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
{WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
{WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
- {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */
+ {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */
{WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
};
{
return board_ti_is("66AK2GGP");
}
+static inline int board_is_k2g_g1(void)
+{
+ return board_ti_is("66AK2GG1");
+}
static inline int board_is_k2g_ice(void)
{
return board_ti_is("66AK2GIC");
return clk_freq;
}
-static int arm_speeds[DEVSPEED_NUMSPDS] = {
+int speeds[DEVSPEED_NUMSPDS] = {
SPD400,
SPD600,
SPD800,
[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
};
-static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
+static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
};
+static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
+ [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
+ [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
+ [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
+ [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
+};
+
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
data = &main_pll_config[sysclk_index][speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed(arm_speeds);
+ speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[sysclk_index][speed];
break;
case NSS_PLL:
data = &uart_pll_config[sysclk_index];
break;
case DDR3_PLL:
- data = &ddr3_pll_config[sysclk_index];
+ if (cpu_revision() & CPU_66AK2G1x) {
+ speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ data = &ddr3_pll_config_1066[sysclk_index];
+ else
+ data = &ddr3_pll_config_800[sysclk_index];
+ } else {
+ data = &ddr3_pll_config_800[sysclk_index];
+ }
break;
default:
data = NULL;
return -1;
}
- if (board_is_k2g_gp())
+ if (board_is_k2g_gp() || board_is_k2g_g1())
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
return 0;
- else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+ else if (!strcmp(name, "keystone-k2g-evm") &&
+ (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
return 0;
else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
return 0;
k2g_reset_mux_config();
- if (board_is_k2g_gp()) {
+ if (board_is_k2g_gp() || board_is_k2g_g1()) {
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (board_is_k2g_gp())
env_set("board_name", "66AK2GGP\0");
+ else if (board_is_k2g_g1())
+ env_set("board_name", "66AK2GG1\0");
else if (board_is_k2g_ice())
env_set("board_name", "66AK2GIC\0");
#endif
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
#include "board.h"
/* K2G GP EVM DDR3 Configuration */
-struct ddr3_phy_config ddr3phy_800_2g = {
+static struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.pir_v2 = 0x00000F81ul,
};
-struct ddr3_emif_config ddr3_800_2g = {
+static struct ddr3_phy_config ddr3phy_1066_2g = {
+ .pllcr = 0x000DC000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0,
+ .ptr3 = 0x0904111Dul,
+ .ptr4 = 0x0859A072ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x6D147744ul,
+ .dtpr1 = 0x32845A80ul,
+ .dtpr2 = 0x50023600ul,
+ .mr0 = 0x00001830ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000000ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F05159ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
+ .pir_v2 = 0x00000F81ul,
+};
+
+static struct ddr3_emif_config ddr3_800_2g = {
.sdcfg = 0x62005662ul,
.sdtim1 = 0x0A385033ul,
.sdtim2 = 0x00001CA5ul,
.sdrfc = 0x00000C34ul,
};
+static struct ddr3_emif_config ddr3_1066_2g = {
+ .sdcfg = 0x62005662ul,
+ .sdtim1 = 0x0E4C6843ul,
+ .sdtim2 = 0x00001CC6ul,
+ .sdtim3 = 0x323DFF32ul,
+ .sdtim4 = 0x533F08AFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001044ul,
+};
+
/* K2G ICE evm DDR3 Configuration */
-struct ddr3_phy_config ddr3phy_800_512mb = {
+static struct ddr3_phy_config ddr3phy_800_512mb = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
.pir_v2 = 0x00000F81ul,
};
-struct ddr3_emif_config ddr3_800_512mb = {
+static struct ddr3_emif_config ddr3_800_512mb = {
.sdcfg = 0x62006662ul,
.sdtim1 = 0x0A385033ul,
.sdtim2 = 0x00001CA5ul,
{
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
-
- if (board_is_k2g_gp()) {
+ if (board_is_k2g_g1()) {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
+ } else if (board_is_k2g_gp()) {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
} else if (board_is_k2g_ice()) {
{
if (!board_ti_was_eeprom_read()) {
configure_pin_mux(k2g_generic_pin_cfg);
- } else if (board_is_k2g_gp()) {
+ } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
configure_pin_mux(k2g_evm_pin_cfg);
} else if (board_is_k2g_ice()) {
configure_pin_mux(k2g_ice_evm_pin_cfg);
config CMD_CRC32
bool "crc32"
select HASH
+ default n if ARCH_SUNXI
default y
help
Compute CRC32.
config CMD_UNZIP
bool "unzip"
+ default n if ARCH_SUNXI
default y if CMD_BOOTI
help
Uncompress a zip-compressed memory region.
config CMD_LOADB
bool "loadb"
+ default n if ARCH_SUNXI
default y
help
Load a binary file over serial line.
config CMD_LOADS
bool "loads"
+ default n if ARCH_SUNXI
default y
help
Load an S-Record file over serial line
# TODO: rename to CMD_SLEEP
config CMD_MISC
bool "sleep"
+ default n if ARCH_SUNXI
default y
help
Delay execution for some time
endmenu
+source "cmd/ti/Kconfig"
+
config CMD_BOOTSTAGE
bool "Enable the 'bootstage' command"
depends on BOOTSTAGE
config CMD_EXT2
bool "ext2 command support"
+ select FS_EXT4
help
Enables EXT2 FS command
config CMD_EXT4
bool "ext4 command support"
+ select FS_EXT4
help
Enables EXT4 FS command
config CMD_EXT4_WRITE
depends on CMD_EXT4
bool "ext4 write command support"
+ select EXT4_WRITE
help
Enables EXT4 FS write command
obj-y += nvedit.o
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
+obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
*/
static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- uint32_t key_addr, src_addr, dst_addr, len;
- uint8_t *key_ptr, *src_ptr, *dst_ptr;
+ uint32_t key_addr, iv_addr, src_addr, dst_addr, len;
+ uint8_t *key_ptr, *iv_ptr, *src_ptr, *dst_ptr;
uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
uint32_t aes_blocks;
int enc;
- if (argc != 6)
+ if (argc != 7)
return CMD_RET_USAGE;
if (!strncmp(argv[1], "enc", 3))
return CMD_RET_USAGE;
key_addr = simple_strtoul(argv[2], NULL, 16);
- src_addr = simple_strtoul(argv[3], NULL, 16);
- dst_addr = simple_strtoul(argv[4], NULL, 16);
- len = simple_strtoul(argv[5], NULL, 16);
+ iv_addr = simple_strtoul(argv[3], NULL, 16);
+ src_addr = simple_strtoul(argv[4], NULL, 16);
+ dst_addr = simple_strtoul(argv[5], NULL, 16);
+ len = simple_strtoul(argv[6], NULL, 16);
key_ptr = (uint8_t *)key_addr;
+ iv_ptr = (uint8_t *)iv_addr;
src_ptr = (uint8_t *)src_addr;
dst_ptr = (uint8_t *)dst_addr;
aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
if (enc)
- aes_cbc_encrypt_blocks(key_exp, src_ptr, dst_ptr, aes_blocks);
+ aes_cbc_encrypt_blocks(key_exp, iv_ptr, src_ptr, dst_ptr,
+ aes_blocks);
else
- aes_cbc_decrypt_blocks(key_exp, src_ptr, dst_ptr, aes_blocks);
+ aes_cbc_decrypt_blocks(key_exp, iv_ptr, src_ptr, dst_ptr,
+ aes_blocks);
return 0;
}
/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char aes_help_text[] =
- "enc key src dst len - Encrypt block of data $len bytes long\n"
- " at address $src using a key at address\n"
- " $key and store the result at address\n"
- " $dst. The $len size must be multiple of\n"
- " 16 bytes and $key must be 16 bytes long.\n"
- "aes dec key src dst len - Decrypt block of data $len bytes long\n"
- " at address $src using a key at address\n"
- " $key and store the result at address\n"
- " $dst. The $len size must be multiple of\n"
- " 16 bytes and $key must be 16 bytes long.";
+ "enc key iv src dst len - Encrypt block of data $len bytes long\n"
+ " at address $src using a key at address\n"
+ " $key with initialization vector at address\n"
+ " $iv. Store the result at address $dst.\n"
+ " The $len size must be multiple of 16 bytes.\n"
+ " The $key and $iv must be 16 bytes long.\n"
+ "aes dec key iv src dst len - Decrypt block of data $len bytes long\n"
+ " at address $src using a key at address\n"
+ " $key with initialization vector at address\n"
+ " $iv. Store the result at address $dst.\n"
+ " The $len size must be multiple of 16 bytes.\n"
+ " The $key and $iv must be 16 bytes long.";
#endif
U_BOOT_CMD(
- aes, 6, 1, do_aes,
+ aes, 7, 1, do_aes,
"AES 128 CBC encryption",
aes_help_text
);
print_bi_dram(bd);
+ print_num("relocaddr", gd->relocaddr);
+ print_num("reloc off", gd->reloc_off);
#if defined(CONFIG_CMD_NET)
print_eth_ip_addr();
print_mhz("ethspeed", bd->bi_ethspeed);
{
efi_obj_list_initalized = 1;
+ /* Initialize EFI driver uclass */
+ efi_driver_init();
+
efi_console_register();
#ifdef CONFIG_PARTITIONS
efi_disk_register();
/* Safe fdt location is at 128MB */
new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size;
- if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+ if (efi_allocate_pages(1, EFI_RUNTIME_SERVICES_DATA, fdt_pages,
&new_fdt_addr) != EFI_SUCCESS) {
/* If we can't put it there, put it somewhere */
new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size);
- if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+ if (efi_allocate_pages(1, EFI_RUNTIME_SERVICES_DATA, fdt_pages,
&new_fdt_addr) != EFI_SUCCESS) {
printf("ERROR: Failed to reserve space for FDT\n");
return NULL;
}
static efi_status_t efi_do_enter(
- void *image_handle, struct efi_system_table *st,
- asmlinkage ulong (*entry)(void *image_handle,
- struct efi_system_table *st))
+ efi_handle_t image_handle, struct efi_system_table *st,
+ EFIAPI efi_status_t (*entry)(
+ efi_handle_t image_handle,
+ struct efi_system_table *st))
{
efi_status_t ret = EFI_LOAD_ERROR;
}
#ifdef CONFIG_ARM64
-static efi_status_t efi_run_in_el2(asmlinkage ulong (*entry)(
- void *image_handle, struct efi_system_table *st),
- void *image_handle, struct efi_system_table *st)
+static efi_status_t efi_run_in_el2(EFIAPI efi_status_t (*entry)(
+ efi_handle_t image_handle, struct efi_system_table *st),
+ efi_handle_t image_handle, struct efi_system_table *st)
{
/* Enable caches again */
dcache_enable();
struct efi_device_path *memdp = NULL;
ulong ret;
- ulong (*entry)(void *image_handle, struct efi_system_table *st)
- asmlinkage;
+ EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
+ struct efi_system_table *st);
ulong fdt_pages, fdt_size, fdt_start, fdt_end;
const efi_guid_t fdt_guid = EFI_FDT_GUID;
bootm_headers_t img = { 0 };
saddr = argv[1];
addr = simple_strtoul(saddr, NULL, 16);
+ /* Check that a numeric value was passed */
+ if (!addr && *saddr != '0')
+ return CMD_RET_USAGE;
if (argc > 2) {
sfdt = argv[2];
* from the VxWorks BSP header files.
* This will vary from board to board
*/
-#if defined(CONFIG_WALNUT)
- tmp = (char *)CONFIG_SYS_NVRAM_BASE_ADDR + 0x500;
- eth_env_get_enetaddr("ethaddr", (uchar *)build_buf);
- memcpy(tmp, &build_buf[3], 3);
-#elif defined(CONFIG_SYS_VXWORKS_MAC_PTR)
+#if defined(CONFIG_SYS_VXWORKS_MAC_PTR)
tmp = (char *)CONFIG_SYS_VXWORKS_MAC_PTR;
eth_env_get_enetaddr("ethaddr", (uchar *)build_buf);
memcpy(tmp, build_buf, 6);
static int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct env_driver *env = env_driver_lookup_default();
-
- printf("Saving Environment to %s...\n", env->name);
-
return env_save() ? 1 : 0;
}
}
U_BOOT_CMD(pmic, CONFIG_SYS_MAXARGS, 1, do_pmic,
- " operations",
+ "PMIC sub-system",
"list - list pmic devices\n"
"pmic dev [name] - show or [set] operating PMIC device\n"
"pmic dump - dump registers\n"
--- /dev/null
+menu "TI specific command line interface"
+
+config CMD_DDR3
+ bool "command for verifying DDR features"
+ help
+ Support for testing ddr3 on TI platforms. This command
+ supports memory verification, memory comapre and ecc
+ verification if supported.
+
+endmenu
--- /dev/null
+# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj- += dummy.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_DDR3) += ddr3.o
+endif
/*
- * Keystone2: DDR3 test commands
+ * EMIF: DDR3 test commands
*
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
+ * Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/hardware.h>
-#include <asm/arch/ddr3.h>
+#include <asm/cache.h>
+#include <asm/emif.h>
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_ARCH_KEYSTONE
+#include <asm/arch/ddr3.h>
#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
#define STACKSIZE (512 << 10) /* 512 KiB */
#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
STACKSIZE) >> 17) - 2)
+#endif
#define DDR_TEST_BURST_SIZE 1024
return 0;
}
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
+static void ddr_check_ecc_status(void)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt);
+ u32 int_status = readl(&emif->emif_irqstatus_raw_sys);
+ int ecc_test = 0;
+ char *env;
+
+ env = env_get("ecc_test");
+ if (env)
+ ecc_test = simple_strtol(env, NULL, 0);
+
+ puts("ECC test Status:\n");
+ if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK)
+ puts("\tECC test: DDR ECC write error interrupted\n");
+
+ if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK)
+ if (!ecc_test)
+ panic("\tECC test: DDR ECC 2-bit error interrupted");
+
+ if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK)
+ puts("\tECC test: DDR ECC 1-bit error interrupted\n");
+
+ if (err_1b)
+ printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b);
+}
+
+static int ddr_memory_ecc_err(u32 addr, u32 ecc_err)
{
- u32 value1, value2, value3;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
+ u32 val1, val2, val3;
+
+ debug("Disabling D-Cache before ECC test\n");
+ dcache_disable();
+ invalidate_dcache_all();
- puts("Disabling DDR ECC ...\n");
- ddr3_disable_ecc(base);
+ puts("Testing DDR ECC:\n");
+ puts("\tECC test: Disabling DDR ECC ...\n");
+ writel(0, &emif->emif_ecc_ctrl_reg);
- value1 = __raw_readl(address);
- value2 = value1 ^ ecc_err;
- __raw_writel(value2, address);
+ val1 = readl(addr);
+ val2 = val1 ^ ecc_err;
+ writel(val2, addr);
- value3 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
- address, value1, value2, ecc_err, value3);
+ val3 = readl(addr);
+ printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+ addr, val1, val2, ecc_err, val3);
- __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
- base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+ puts("\tECC test: Enabling DDR ECC ...\n");
+#ifdef CONFIG_ARCH_KEYSTONE
+ ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
+ writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+ ddr3_enable_ecc(EMIF1_BASE, 1);
+#else
+ writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
+#endif
- puts("Enabling DDR ECC ...\n");
- ddr3_enable_ecc(base, 1);
+ val1 = readl(addr);
+ printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);
- value1 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
+ ddr_check_ecc_status();
+
+ debug("Enabling D-cache back after ECC test\n");
+ enable_caches();
- ddr3_check_ecc_int(base);
return 0;
}
+static int is_addr_valid(u32 addr)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 start_addr, end_addr, range, ecc_ctrl;
+
+#ifdef CONFIG_ARCH_KEYSTONE
+ ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK;
+ range = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
+#else
+ ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
+ range = readl(&emif->emif_ecc_address_range_1);
+#endif
+
+ /* Check in ecc address range 1 */
+ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
+ start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
+ + CONFIG_SYS_SDRAM_BASE;
+ end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
+ + 0xFFFF;
+ if ((addr >= start_addr) && (addr <= end_addr))
+ /* addr within ecc address range 1 */
+ return 1;
+ }
+
+ /* Check in ecc address range 2 */
+ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
+ range = readl(&emif->emif_ecc_address_range_2);
+ start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
+ + CONFIG_SYS_SDRAM_BASE;
+ end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
+ + 0xFFFF;
+ if ((addr >= start_addr) && (addr <= end_addr))
+ /* addr within ecc address range 2 */
+ return 1;
+ }
+
+ return 0;
+}
+
+static int is_ecc_enabled(void)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
+
+ return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) &&
+ (ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK);
+}
+
static int do_ddr_test(cmd_tbl_t *cmdtp,
int flag, int argc, char * const argv[])
{
u32 start_addr, end_addr, size, ecc_err;
if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
- if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
- puts("ECC RMW isn't supported for this SOC\n");
- return 1;
+ if (!is_ecc_enabled()) {
+ puts("ECC not enabled. Please Enable ECC any try again\n");
+ return CMD_RET_FAILURE;
}
start_addr = simple_strtoul(argv[2], NULL, 16);
ecc_err = simple_strtoul(argv[3], NULL, 16);
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1))) {
- puts("Invalid address!\n");
- return cmd_usage(cmdtp);
+ if (!is_addr_valid(start_addr)) {
+ puts("Invalid address. Please enter ECC supported address!\n");
+ return CMD_RET_FAILURE;
}
- ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
- start_addr, ecc_err);
+ ddr_memory_ecc_err(start_addr, ecc_err);
return 0;
}
if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
(start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
+ get_effective_memsize() - 1)) ||
(end_addr < CONFIG_SYS_SDRAM_BASE) ||
(end_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
+ get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
puts("Invalid start or end address!\n");
return cmd_usage(cmdtp);
}
config DISPLAY_CPUINFO
bool "Display information about the CPU during start up"
- default y if ARM || NIOS2 || X86 || XTENSA
+ default y if ARM || NIOS2 || X86 || XTENSA || M68K
help
Display information about the CPU that U-Boot is running on
when U-Boot starts up. The function print_cpuinfo() is called
const char *algo_name = "sha256";
u_int presskey_len = 0;
int abort = 0;
- int size;
+ int size = sizeof(sha);
int ret;
if (sha_env_str == NULL)
#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
#undef XTRN_DECLARE_GLOBAL_DATA_PTR
#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
-DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
+DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
#else
DECLARE_GLOBAL_DATA_PTR;
#endif
#endif
debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
- text_base, bss_start, bss_end);
+ text_base, bss_start, bss_end);
#endif
return 0;
}
#endif
+#if defined(CONFIG_VID)
+__weak int init_func_vid(void)
+{
+ return 0;
+}
+#endif
+
#if defined(CONFIG_HARD_SPI)
static int init_func_spi(void)
{
{
gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
debug("Reserving %dk for malloc() at: %08lx\n",
- TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
+ TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
return 0;
}
gd->start_addr_sp -= sizeof(gd_t);
gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
- sizeof(gd_t), gd->start_addr_sp);
+ sizeof(gd_t), gd->start_addr_sp);
return 0;
}
console_init_f, /* stage 1 init of console */
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \
- defined(CONFIG_X86)
+#if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
checkcpu,
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
#if defined(CONFIG_SYS_I2C)
init_func_i2c,
#endif
+#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
+ init_func_vid,
+#endif
#if defined(CONFIG_HARD_SPI)
init_func_spi,
#endif
#endif
#ifdef CONFIG_OF_EMBED
/*
- * The fdt_blob needs to be moved to new relocation address
- * incase of FDT blob is embedded with in image
- */
+ * The fdt_blob needs to be moved to new relocation address
+ * incase of FDT blob is embedded with in image
+ */
gd->fdt_blob += gd->reloc_off;
#endif
#ifdef CONFIG_EFI_LOADER
print_size(flash_size, "");
#ifdef CONFIG_SYS_FLASH_CHECKSUM
/*
- * Compute and print flash CRC if flashchecksum is set to 'y'
- *
- * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
- */
+ * Compute and print flash CRC if flashchecksum is set to 'y'
+ *
+ * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
+ */
if (env_get_yesno("flashchecksum") == 1) {
+ const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE;
+
printf(" CRC: %08X", crc32(0,
- (const unsigned char *) CONFIG_SYS_FLASH_BASE,
- flash_size));
+ flash_base,
+ flash_size));
}
#endif /* CONFIG_SYS_FLASH_CHECKSUM */
putc('\n');
update_flash_size(flash_size);
#endif
-
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
ulong pram = 0;
char memsz[32];
-# ifdef CONFIG_PRAM
pram = env_get_ulong("pram", 10, CONFIG_PRAM);
-# endif
- sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram));
+ sprintf(memsz, "%ldk", (long int)((gd->ram_size / 1024) - pram));
env_set("mem", memsz);
return 0;
initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
* A temporary mapping of IFC high region is since removed,
- * so environmental variables in NOR flash is not availble
+ * so environmental variables in NOR flash is not available
* until board_init() is called below to remap IFC to high
* region.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do early PCI configuration _before_ the flash gets initialised,
- * because PCU ressources are crucial for flash access on some boards.
+ * because PCU resources are crucial for flash access on some boards.
*/
initr_pci,
#endif
* and no protected sectors are hit.
* Returns:
* ERR_OK 0 - OK
- * ERR_TIMOUT 1 - write timeout
+ * ERR_TIMEOUT 1 - write timeout
* ERR_NOT_ERASED 2 - Flash not erased
* ERR_PROTECTED 4 - target range includes protected sectors
* ERR_INVAL 8 - target address not in Flash memory
switch (err) {
case ERR_OK:
break;
- case ERR_TIMOUT:
+ case ERR_TIMEOUT:
puts ("Timeout writing to Flash\n");
break;
case ERR_NOT_ERASED:
if (multi_hash()) {
struct hash_algo *algo;
- uint8_t output[HASH_MAX_DIGEST_SIZE];
+ u8 *output;
uint8_t vsum[HASH_MAX_DIGEST_SIZE];
void *buf;
return 1;
}
+ output = memalign(ARCH_DMA_MINALIGN,
+ sizeof(uint32_t) * HASH_MAX_DIGEST_SIZE);
+
buf = map_sysmem(addr, len);
algo->hash_func_ws(buf, len, output, algo->chunk_size);
unmap_sysmem(buf);
store_result(algo, output, *argv,
flags & HASH_FLAG_ENV);
}
+ unmap_sysmem(output);
+
}
/* Horrible code size hack for boards that just want crc32 */
location is used. Normally we put the device tree at the end of BSS
but with this option enabled, it goes at _image_binary_end.
+config SPL_DISABLE_BANNER_PRINT
+ bool "Disable output of the SPL banner 'U-Boot SPL ...'"
+ help
+ If this option is enabled, SPL will not print the banner with version
+ info. Selecting this option could be useful to reduce SPL boot time
+ (e.g. approx. 6 ms slower, when output on i.MX6 with 115200 baud).
+
config SPL_DISPLAY_PRINT
bool "Display a board-specific message in SPL"
help
if TPL
+config TPL_BOARD_INIT
+ bool "Call board-specific initialization in TPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_board_init() from board_init_r(). This function should be
+ provided by the board.
+
config TPL_LDSCRIPT
string "Linker script for the TPL stage"
depends on TPL
timer_init();
#endif
-#ifdef CONFIG_SPL_BOARD_INIT
+#if CONFIG_IS_ENABLED(BOARD_INIT)
spl_board_init();
#endif
gd->have_console = 1;
+#ifndef CONFIG_SPL_DISABLE_BANNER_PRINT
puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
- U_BOOT_TIME ")\n");
+ U_BOOT_TIME " " U_BOOT_TZ ")\n");
+#endif
#ifdef CONFIG_SPL_DISPLAY_PRINT
spl_display_print();
#endif
ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
/* Fill BL32 related information if it exists */
-#ifdef BL32_BASE
bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP,
ATF_VERSION_1, 0);
bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+#ifndef BL32_BASE
+ bl2_to_bl31_params->bl32_ep_info->pc = 0;
#endif /* BL32_BASE */
/* Fill BL33 related information */
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
+# CONFIG_ENV_IS_IN_FLASH is not set
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
+# CONFIG_ENV_IS_IN_FLASH is not set
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7794=y
CONFIG_TARGET_ALT=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_SYS_OMAP24_I2C_SPEED=1000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
+CONFIG_TARGET_PDU001=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
+CONFIG_LOCALVERSION="-EETS-1.0.0"
+CONFIG_BOOTDELAY=1
+CONFIG_SPL=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65910=y
+CONFIG_SYS_NS16550=y
+# CONFIG_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_HCD=y
+CONFIG_USB_AM35X=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_AM35X=y
# CONFIG_FAT_WRITE is not set
CONFIG_BCH=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_AM43XX=y
-CONFIG_ISW_ENTRY_ADDR=0x30000000
+CONFIG_SYS_TEXT_BASE=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
+CONFIG_R8A7740=y
CONFIG_TARGET_ARMADILLO_800EVA=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7792=y
CONFIG_TARGET_BLANCHE=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot"
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
+CONFIG_DA850_LOWLEVEL=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_AM35X=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6318=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="AR-5315un # "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_BCM6345=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_POWER_DOMAIN=y
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6368=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="WAP-5813n # "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_BCM6345=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
+CONFIG_DA850_LOWLEVEL=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_FS_EXT4=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader-nand),1024k(uboot-nand),256k(params-nand),5120k(kernel),-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK322X=y
CONFIG_RAM=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3328=y
CONFIG_DM_PMIC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7793=y
CONFIG_TARGET_GOSE=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_PANIC_HANG=y
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7791=y
CONFIG_TARGET_KOELSCH=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7790=y
CONFIG_TARGET_LAGER=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012A2G5RDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
# CONFIG_CMD_UBIFS is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
-CONFIG_ENV_IS_IN_FLASH=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_SPI=y
CONFIG_WDT_BCM6345=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_S2MPS11=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_S2MPS11=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_BLK is not set
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
+CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_BLK is not set
CONFIG_DM_I2C=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
CONFIG_BCH=y
+# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_SMC911X_32_BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
+CONFIG_TWL4030_USB=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_UDC=y
+CONFIG_USB_OMAP3=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_OMAPL138_LCDK=y
+CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_FAT_WRITE=y
CONFIG_LIB_RAND=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_R8A7791=y
CONFIG_TARGET_PORTER=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_UNIPHIER=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARCH_QEMU=y
+CONFIG_TARGET_QEMU_ARM_64BIT=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_OF_BOARD=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_BLK=y
+# CONFIG_MMC is not set
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_ARM=y
CONFIG_ARM_SMCCC=y
CONFIG_ARCH_QEMU=y
+CONFIG_TARGET_QEMU_ARM_32BIT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x"
+CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb"
+CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_RCAR_GEN3=y
CONFIG_R8A7796=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x"
+CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_RCAR_GEN3=y
CONFIG_R8A7796=y
CONFIG_TARGET_ULCB=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb"
+CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_RCAR_GEN3=y
CONFIG_R8A77970=y
CONFIG_TARGET_EAGLE=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle"
+CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_RCAR_GEN3=y
CONFIG_R8A77995=y
CONFIG_TARGET_DRAAK=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak"
+CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_BCM283X=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_BCM283X=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_BCM283X=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_BCM283X=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_BCM283X=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_SPI=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7794=y
CONFIG_TARGET_SILK=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_TWL4030_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_CLK=y
-CONFIG_DM_GPIO=y
-CONFIG_MISC=y
-CONFIG_STM32_RCC=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_STM32=y
-CONFIG_RAM=y
-CONFIG_STM32_SDRAM=y
-CONFIG_DM_RESET=y
-CONFIG_STM32_RESET=y
-CONFIG_STM32X7_SERIAL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_STM32F4=y
+CONFIG_TARGET_STM32F429_EVALUATION=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
# CONFIG_BLK is not set
-CONFIG_CLK=y
-CONFIG_DM_GPIO=y
-CONFIG_MISC=y
-CONFIG_STM32_RCC=y
CONFIG_DM_MMC=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD_NOR_FLASH=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_STM32=y
-CONFIG_RAM=y
-CONFIG_STM32_SDRAM=y
-CONFIG_DM_RESET=y
-CONFIG_STM32_RESET=y
-CONFIG_STM32X7_SERIAL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
# CONFIG_BLK is not set
-CONFIG_CLK=y
-CONFIG_DM_GPIO=y
-CONFIG_MISC=y
-CONFIG_STM32_RCC=y
CONFIG_DM_MMC=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_ARM_PL180_MMCI=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
-CONFIG_PINCTRL_STM32=y
-CONFIG_RAM=y
-CONFIG_STM32_SDRAM=y
-CONFIG_DM_RESET=y
-CONFIG_STM32_RESET=y
-CONFIG_STM32X7_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_R8A7790=y
CONFIG_TARGET_STOUT=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
mode or in read-write mode.
First, to enable support for both ext4 (and, automatically, ext2 as well),
-but without selecting the corresponding commands, use one of:
+but without selecting the corresponding commands, enable one of the following:
- #define CONFIG_FS_EXT4 (for read-only)
- #define CONFIG_EXT4_WRITE (for read-write)
+ CONFIG_FS_EXT4 (for read-only)
+ CONFIG_EXT4_WRITE (for read-write)
Next, to select the ext2-related commands:
use one or both of:
- #define CONFIG_CMD_EXT2
- #define CONFIG_CMD_EXT4
+ CONFIG_CMD_EXT2
+ CONFIG_CMD_EXT4
-Selecting either of the above automatically defines CONFIG_FS_EXT4 if it
-wasn't defined already.
+Selecting either of the above automatically selects CONFIG_FS_EXT4 if it
+wasn't enabled already.
-In addition, to get the write access command "ext4write", use:
+In addition, to get the write access command "ext4write", enable:
- #define CONFIG_CMD_EXT4_WRITE
+ CONFIG_CMD_EXT4_WRITE
-which automatically defines CONFIG_EXT4_WRITE if it wasn't defined
+which automatically selects CONFIG_EXT4_WRITE if it wasn't defined
already.
Also relevant are the generic filesystem commands, selected by:
- #define CONFIG_CMD_FS_GENERIC
+ CONFIG_CMD_FS_GENERIC
This does not automatically enable EXT4 support for you, you still need
to do that yourself.
--- /dev/null
+# iSCSI booting with U-Boot and iPXE
+
+## Motivation
+
+U-Boot has only a reduced set of supported network protocols. The focus for
+network booting has been on UDP based protocols. A TCP stack and HTTP support
+are expected to be integrated in 2018 together with a wget command.
+
+For booting a diskless computer this leaves us with BOOTP or DHCP to get the
+address of a boot script. TFTP or NFS can be used to load the boot script, the
+operating system kernel and the initial file system (initrd).
+
+These protocols are insecure. The client cannot validate the authenticity
+of the contacted servers. And the server cannot verify the identity of the
+client.
+
+Furthermore the services providing the operating system loader or kernel are
+not the ones that the operating system typically will use. Especially in a SAN
+environment this makes updating the operating system a hassle. After installing
+a new kernel version the boot files have to be copied to the TFTP server
+directory.
+
+The HTTPS protocol provides certificate based validation of servers. Sensitive
+data like passwords can be securely transmitted.
+
+The iSCSI protocol is used for connecting storage attached networks. It
+provides mutual authentication using the CHAP protocol. It typically runs on
+a TCP transport.
+
+Thus a better solution than DHCP/TFTP/NFS boot would be to load a boot script
+via HTTPS and to download any other files needed for booting via iSCSI from the
+same target where the operating system is installed.
+
+An alternative to implementing these protocols in U-Boot is to use an existing
+software that can run on top of U-Boot. iPXE is the "swiss army knife" of
+network booting. It supports both HTTPS and iSCSI. It has a scripting engine for
+fine grained control of the boot process and can provide a command shell.
+
+iPXE can be built as an EFI application (named snp.efi) which can be loaded and
+run by U-Boot.
+
+## Boot sequence
+
+U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This
+application has network access via the simple network protocol offered by
+U-Boot.
+
+iPXE executes its internal script. This script may optionally chain load a
+secondary boot script via HTTPS or open a shell.
+
+For the further boot process iPXE connects to the iSCSI server. This includes
+the mutual authentication using the CHAP protocol. After the authentication iPXE
+has access to the iSCSI targets.
+
+For a selected iSCSI target iPXE sets up a handle with the block IO protocol. It
+uses the ConnectController boot service of U-Boot to request U-Boot to connect a
+file system driver. U-Boot reads from the iSCSI drive via the block IO protocol
+offered by iPXE. It creates the partition handles and installs the simple file
+protocol. Now iPXE can call the simple file protocol to load Grub. U-Boot uses
+the block IO protocol offered by iPXE to fulfill the request.
+
+Once Grub is started it uses the same block IO protocol to load Linux. Via
+the EFI stub Linux is called as an EFI application.
+
+```
+ +--------+ +--------+
+ | | Runs | |
+ | U-Boot |=========>| iPXE |
+ | EFI | | snp.efi|
++--------+ | | DHCP | |
+| |<====|********|<=========| |
+| DHCP | | | Get IP | |
+| Server | | | Address | |
+| |====>|********|=========>| |
++--------+ | | Response | |
+ | | | |
+ | | | |
++--------+ | | HTTPS | |
+| |<====|********|<=========| |
+| HTTPS | | | Load | |
+| Server | | | Script | |
+| |====>|********|=========>| |
++--------+ | | | |
+ | | | |
+ | | | |
++--------+ | | iSCSI | |
+| |<====|********|<=========| |
+| iSCSI | | | Auth | |
+| Server |====>|********|=========>| |
+| | | | | |
+| | | | Loads | |
+| |<====|********|<=========| | +--------+
+| | | | Grub | | Runs | |
+| |====>|********|=========>| |=======>| Grub |
+| | | | | | | |
+| | | | | | | |
+| | | | | | Loads | |
+| |<====|********|<=========|********|<=======| | +--------+
+| | | | | | Linux | | Runs | |
+| |====>|********|=========>|********|=======>| |=====>| Linux |
+| | | | | | | | | |
++--------+ +--------+ +--------+ +--------+ | |
+ | |
+ | |
+ | ~ ~ ~ ~|
+```
+
+## Security
+
+The iSCSI protocol is not encrypted. The traffic could be secured using IPsec
+but neither U-Boot nor iPXE does support this. So we should at least separate
+the iSCSI traffic from all other network traffic. This can be achieved using a
+virtual local area network (VLAN).
+
+## Configuration
+
+### iPXE
+
+For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed.
+
+ git clone http://git.ipxe.org/ipxe.git
+ cd ipxe/src
+ make bin-arm64-efi/snp.efi -j6 EMBED=myscript.ipxe
+
+The available commands for the boot script are documented at:
+
+http://ipxe.org/cmd
+
+Credentials are managed as environment variables. These are described here:
+
+http://ipxe.org/cfg
+
+iPXE by default will put the CPU to rest when waiting for input. U-Boot does
+not wake it up due to missing interrupt support. To avoid this behavior create
+file src/config/local/nap.h.
+
+ /* nap.h */
+ #undef NAP_EFIX86
+ #undef NAP_EFIARM
+ #define NAP_NULL
+
+The supported commands in iPXE are controlled by an include, too. Putting the
+following into src/config/local/general.h is sufficient for most use cases.
+
+ /* general.h */
+ #define NSLOOKUP_CMD /* Name resolution command */
+ #define PING_CMD /* Ping command */
+ #define NTP_CMD /* NTP commands */
+ #define VLAN_CMD /* VLAN commands */
+ #define IMAGE_EFI /* EFI image support */
+ #define DOWNLOAD_PROTO_HTTPS /* Secure Hypertext Transfer Protocol */
+ #define DOWNLOAD_PROTO_FTP /* File Transfer Protocol */
+ #define DOWNLOAD_PROTO_NFS /* Network File System Protocol */
+ #define DOWNLOAD_PROTO_FILE /* Local file system access */
+
+## Links
+
+* https://ipxe.org - iPXE open source boot firmware
+* https://www.gnu.org/software/grub/ - GNU Grub (Grand Unified Bootloader)
1.2 Configuration settings for M54418TWR Development Board
CONFIG_MCF5441x -- define for all MCF5441x CPUs
CONFIG_M54418 -- define for all Freescale MCF54418 CPUs
-CONFIG_M54418TWR -- define for M54418TWR board
CONFIG_MCFUART -- define to use common CF Uart driver
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
# SPDX-License-Identifier: GPL-2.0+
#
-U-Boot on QEMU's 'virt' machine on ARM
-======================================
+U-Boot on QEMU's 'virt' machine on ARM & AArch64
+================================================
QEMU for ARM supports a special 'virt' machine designed for emulation and
virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit ARM and AArch64 are supported.
The 'virt' platform provides the following as the basic functionality:
- A generated device tree blob placed at the start of RAM
- A freely configurable amount of RAM, described by the DTB
- A PL011 serial port, discoverable via the DTB
- - An ARMv7 architected timer
+ - An ARMv7/ARMv8 architected timer
- PSCI for rebooting the system
- A generic ECAM-based PCI host controller, discoverable via the DTB
Building U-Boot
---------------
-Set the CROSS_COMPILE and ARCH=arm environment variables as usual, and run:
+Set the CROSS_COMPILE environment variable as usual, and run:
+- For ARM:
make qemu_arm_defconfig
make
+- For AArch64:
+ make qemu_arm64_defconfig
+ make
+
Running U-Boot
--------------
The minimal QEMU command line to get U-Boot up and running is:
+- For ARM:
qemu-system-arm -machine virt,highmem=off -bios u-boot.bin
+- For AArch64:
+ qemu-system-aarch64 -machine virt,highmem=off -cpu cortex-a57 -bios u-boot.bin
+
The 'highmem=off' parameter to the 'virt' machine is required for PCI to work
-in U-Boot.
+in U-Boot. Also, for some odd reason qemu-system-aarch64 needs to be explicitly
+told to use a 64-bit CPU or it will boot in 32-bit mode.
Additional peripherals that have been tested to work in both U-Boot and Linux
can be enabled with the following command line parameters:
The soft SPI node requires the following properties:
-compatible: "u-boot,soft-spi"
-soft_spi_cs: GPIO number to use for SPI chip select (output)
-soft_spi_sclk: GPIO number to use for SPI clock (output)
-soft_spi_mosi: GPIO number to use for SPI MOSI line (output)
-soft_spi_miso GPIO number to use for SPI MISO line (input)
+Mandatory properties:
+compatible: "spi-gpio"
+cs-gpios: GPIOs to use for SPI chip select (output)
+gpio-sck: GPIO to use for SPI clock (output)
+And at least one of:
+gpio-mosi: GPIO to use for SPI MOSI line (output)
+gpio-miso: GPIO to use for SPI MISO line (input)
+
+Optional propertie:
spi-delay-us: Number of microseconds of delay between each CS transition
The GPIOs should be specified as required by the GPIO controller referenced.
Example:
soft-spi {
- compatible = "u-boot,soft-spi";
- cs-gpio = <&gpio 235 0>; /* Y43 */
- sclk-gpio = <&gpio 225 0>; /* Y31 */
- mosi-gpio = <&gpio 227 0>; /* Y33 */
- miso-gpio = <&gpio 224 0>; /* Y30 */
+ compatible = "spi-gpio";
+ cs-gpios = <&gpio 235 0>; /* Y43 */
+ gpio-sck = <&gpio 225 0>; /* Y31 */
+ gpio-mosi = <&gpio 227 0>; /* Y33 */
+ gpio-miso = <&gpio 224 0>; /* Y30 */
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;
- reg : 1.Physical base address and size of SPI registers map.
2. Physical base address & size of NOR Flash.
- clocks : Clock phandles (see clock bindings for details).
-- sram-size : spi controller sram size.
+- cdns,fifo-depth : Size of the data FIFO in words.
+- cdns,fifo-width : Bus width of the data FIFO in bytes.
+- cdns,trigger-address : 32-bit indirect AHB trigger address.
+- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
- status : enable in requried dts.
connected flash properties
- spi-max-frequency : Max supported spi frequency.
- page-size : Flash page size.
- block-size : Flash memory block size.
-- tshsl-ns : Added delay in master reference clocks (ref_clk) for
+- cdns,tshsl-ns : Added delay in master reference clocks (ref_clk) for
the length that the master mode chip select outputs
are de-asserted between transactions.
-- tsd2d-ns : Delay in master reference clocks (ref_clk) between one
+- cdns,tsd2d-ns : Delay in master reference clocks (ref_clk) between one
chip select being de-activated and the activation of
another.
-- tchsh-ns : Delay in master reference clocks between last bit of
+- cdns,tchsh-ns : Delay in master reference clocks between last bit of
current transaction and de-asserting the device chip
select (n_ss_out).
-- tslch-ns : Delay in master reference clocks between setting
+- cdns,tslch-ns : Delay in master reference clocks between setting
n_ss_out low and first bit transfer
[IF_TYPE_HOST] = "host",
[IF_TYPE_SYSTEMACE] = "ace",
[IF_TYPE_NVME] = "nvme",
+ [IF_TYPE_EFI] = "efi",
};
static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
[IF_TYPE_SD] = UCLASS_INVALID,
[IF_TYPE_SATA] = UCLASS_AHCI,
[IF_TYPE_HOST] = UCLASS_ROOT,
- [IF_TYPE_NVME] = UCLASS_NVME,
[IF_TYPE_SYSTEMACE] = UCLASS_INVALID,
+ [IF_TYPE_NVME] = UCLASS_NVME,
+ [IF_TYPE_EFI] = UCLASS_EFI,
};
static enum if_type if_typename_to_iftype(const char *if_typename)
#
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
-obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
-obj-$(CONFIG_SANDBOX) += clk_sandbox.o
-obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
-obj-$(CONFIG_CLK_RENESAS) += renesas/
-obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
-obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
obj-y += tegra/
-obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
-obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
-obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
+obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
* |-->| TUNNEL PLL |
* | --------------
* | |
- * | |-->|CGU_TUN_IDIV|----------->
+ * | |-->|CGU_TUN_IDIV_TUN|----------->
+ * | |-->|CGU_TUN_IDIV_ROM|----------->
+ * | |-->|CGU_TUN_IDIV_PWM|----------->
* |
* | ------------
* |-->| HDMI PLL |
DECLARE_GLOBAL_DATA_PTR;
#define CGU_ARC_IDIV 0x080
-#define CGU_TUN_IDIV 0x380
+#define CGU_TUN_IDIV_TUN 0x380
+#define CGU_TUN_IDIV_ROM 0x390
+#define CGU_TUN_IDIV_PWM 0x3A0
#define CGU_HDMI_IDIV_APB 0x480
#define CGU_SYS_IDIV_APB 0x180
#define CGU_SYS_IDIV_AXI 0x190
#define CREG_CORE_IF_CLK_DIV_1 0x0
#define CREG_CORE_IF_CLK_DIV_2 0x1
+#define MIN_PLL_RATE 100000000 /* 100 MHz */
#define PARENT_RATE 33333333 /* fixed clock - xtal */
-#define CGU_MAX_CLOCKS 24
+#define CGU_MAX_CLOCKS 26
+
+#define CGU_SYS_CLOCKS 16
+#define MAX_AXI_CLOCKS 4
+
+#define CGU_TUN_CLOCKS 3
+#define MAX_TUN_CLOCKS 6
+
+struct hsdk_tun_idiv_cfg {
+ u32 oft;
+ u8 val[MAX_TUN_CLOCKS];
+};
+
+struct hsdk_tun_clk_cfg {
+ const u32 clk_rate[MAX_TUN_CLOCKS];
+ const u32 pll_rate[MAX_TUN_CLOCKS];
+ const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
+};
+
+static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
+ { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
+ { 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, {
+ { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
+ { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
+ { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } }
+ }
+};
+
+struct hsdk_sys_idiv_cfg {
+ u32 oft;
+ u8 val[MAX_AXI_CLOCKS];
+};
+
+struct hsdk_axi_clk_cfg {
+ const u32 clk_rate[MAX_AXI_CLOCKS];
+ const u32 pll_rate[MAX_AXI_CLOCKS];
+ const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
+};
+
+static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
+ { 200000000, 400000000, 600000000, 800000000 },
+ { 800000000, 800000000, 600000000, 800000000 }, {
+ { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
+ { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
+ { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
+ { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
+ { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
+ { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
+ { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
+ { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
+ { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
+ { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
+ { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
+ { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
+ { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
+ { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
+ { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
+ { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
+ }
+};
struct hsdk_pll_cfg {
u32 rate;
};
static ulong idiv_set(struct clk *, ulong);
+static ulong cpu_clk_set(struct clk *, ulong);
+static ulong axi_clk_set(struct clk *, ulong);
+static ulong tun_clk_set(struct clk *, ulong);
static ulong idiv_get(struct clk *);
static int idiv_off(struct clk *);
static ulong pll_set(struct clk *, ulong);
static const struct hsdk_cgu_clock_map clock_map[] = {
{ CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
- { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
{ CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
{ CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
};
}
}
- pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+ pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
return -EINVAL;
}
return parent_rate / div_factor;
}
+/* Special behavior: wen we set this clock we set both idiv and pll */
+static ulong cpu_clk_set(struct clk *sclk, ulong rate)
+{
+ ulong ret;
+
+ ret = pll_set(sclk, rate);
+ idiv_set(sclk, rate);
+
+ return ret;
+}
+
+/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
+static ulong axi_clk_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong pll_rate;
+ int i, freq_idx = -1;
+ ulong ret = 0;
+
+ pll_rate = pll_get(sclk);
+
+ for (i = 0; i < MAX_AXI_CLOCKS; i++) {
+ if (axi_clk_cfg.clk_rate[i] == rate) {
+ freq_idx = i;
+ break;
+ }
+ }
+
+ if (freq_idx < 0) {
+ pr_err("axi clk: invalid rate=%ld Hz\n", rate);
+ return -EINVAL;
+ }
+
+ /* configure PLL before dividers */
+ if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+
+ /* configure SYS dividers */
+ for (i = 0; i < CGU_SYS_CLOCKS; i++) {
+ clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
+ hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
+ }
+
+ /* configure PLL after dividers */
+ if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+
+ return ret;
+}
+
+static ulong tun_clk_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong pll_rate;
+ int i, freq_idx = -1;
+ ulong ret = 0;
+
+ pll_rate = pll_get(sclk);
+
+ for (i = 0; i < MAX_TUN_CLOCKS; i++) {
+ if (tun_clk_cfg.clk_rate[i] == rate) {
+ freq_idx = i;
+ break;
+ }
+ }
+
+ if (freq_idx < 0) {
+ pr_err("tun clk: invalid rate=%ld Hz\n", rate);
+ return -EINVAL;
+ }
+
+ /* configure PLL before dividers */
+ if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
+
+ /* configure SYS dividers */
+ for (i = 0; i < CGU_TUN_CLOCKS; i++) {
+ clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
+ hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
+ }
+
+ /* configure PLL after dividers */
+ if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
+
+ return ret;
+}
+
static ulong idiv_set(struct clk *sclk, ulong rate)
{
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
}
if (div_factor & ~CGU_IDIV_MASK) {
- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
rate, parent_rate, div_factor, CGU_IDIV_MASK);
div_factor = CGU_IDIV_MASK;
}
if (div_factor == 0) {
- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
rate, parent_rate, div_factor);
div_factor = 1;
.id = UCLASS_CLK,
.of_match = hsdk_cgu_clk_id,
.probe = hsdk_cgu_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
.ops = &hsdk_cgu_ops,
};
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
* Copyright (c) 2016, NVIDIA CORPORATION.
+ * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <dm/read.h>
#include <dt-structs.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
+static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
- return (struct clk_ops *)dev->driver->ops;
+ return (const struct clk_ops *)dev->driver->ops;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
return 0;
}
-int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
+static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
+ int index, struct clk *clk)
{
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_clk;
- struct clk_ops *ops;
+ const struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(clk);
clk->dev = NULL;
- ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
- index, &args);
+ ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
+ index, &args);
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
__func__, ret);
return clk_request(dev_clk, clk);
}
+
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
+{
+ return clk_get_by_indexed_prop(dev, "clocks", index, clk);
+}
+
+static int clk_set_default_parents(struct udevice *dev)
+{
+ struct clk clk, parent_clk;
+ int index;
+ int num_parents;
+ int ret;
+
+ num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
+ "#clock-cells");
+ if (num_parents < 0) {
+ debug("%s: could not read assigned-clock-parents for %p\n",
+ __func__, dev);
+ return 0;
+ }
+
+ for (index = 0; index < num_parents; index++) {
+ ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
+ index, &parent_clk);
+ if (ret) {
+ debug("%s: could not get parent clock %d for %s\n",
+ __func__, index, dev_read_name(dev));
+ return ret;
+ }
+
+ ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
+ index, &clk);
+ if (ret) {
+ debug("%s: could not get assigned clock %d for %s\n",
+ __func__, index, dev_read_name(dev));
+ return ret;
+ }
+
+ ret = clk_set_parent(&clk, &parent_clk);
+
+ /*
+ * Not all drivers may support clock-reparenting (as of now).
+ * Ignore errors due to this.
+ */
+ if (ret == -ENOSYS)
+ continue;
+
+ if (ret) {
+ debug("%s: failed to reparent clock %d for %s\n",
+ __func__, index, dev_read_name(dev));
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int clk_set_default_rates(struct udevice *dev)
+{
+ struct clk clk;
+ int index;
+ int num_rates;
+ int size;
+ int ret = 0;
+ u32 *rates = NULL;
+
+ size = dev_read_size(dev, "assigned-clock-rates");
+ if (size < 0)
+ return 0;
+
+ num_rates = size / sizeof(u32);
+ rates = calloc(num_rates, sizeof(u32));
+ if (!rates)
+ return -ENOMEM;
+
+ ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
+ if (ret)
+ goto fail;
+
+ for (index = 0; index < num_rates; index++) {
+ ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
+ index, &clk);
+ if (ret) {
+ debug("%s: could not get assigned clock %d for %s\n",
+ __func__, index, dev_read_name(dev));
+ continue;
+ }
+
+ ret = clk_set_rate(&clk, rates[index]);
+ if (ret < 0) {
+ debug("%s: failed to set rate on clock %d for %s\n",
+ __func__, index, dev_read_name(dev));
+ break;
+ }
+ }
+
+fail:
+ free(rates);
+ return ret;
+}
+
+int clk_set_defaults(struct udevice *dev)
+{
+ int ret;
+
+ /* If this is running pre-reloc state, don't take any action. */
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
+
+ debug("%s(%s)\n", __func__, dev_read_name(dev));
+
+ ret = clk_set_default_parents(dev);
+ if (ret)
+ return ret;
+
+ ret = clk_set_default_rates(dev);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
# endif /* OF_PLATDATA */
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
int clk_request(struct udevice *dev, struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(dev);
+ const struct clk_ops *ops = clk_dev_ops(dev);
debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
int clk_free(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
ulong clk_get_rate(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
ulong clk_set_rate(struct clk *clk, ulong rate)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
return ops->set_rate(clk, rate);
}
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+ debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
+
+ if (!ops->set_parent)
+ return -ENOSYS;
+
+ return ops->set_parent(clk, parent);
+}
+
int clk_enable(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
int clk_disable(struct clk *clk)
{
- struct clk_ops *ops = clk_dev_ops(clk->dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
#include <clk-uclass.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct clk_fixed_rate {
unsigned long fixed_rate;
};
static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- to_clk_fixed_rate(dev)->fixed_rate = dev_read_u32_default(dev,
- "clock-frequency", 0);
+ to_clk_fixed_rate(dev)->fixed_rate =
+ dev_read_u32_default(dev, "clock-frequency", 0);
#endif
return 0;
writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
/* wait till previous src change is active */
- wait_for_bit(__func__, reg, REFO_DIVSW_EN | REFO_ACTIVE,
- false, CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(reg, REFO_DIVSW_EN | REFO_ACTIVE,
+ false, CONFIG_SYS_HZ, false);
/* parent_id */
v = readl(reg);
writel(REFO_DIVSW_EN, reg + _SET_OFFSET);
/* wait for divider switching to complete */
- return wait_for_bit(__func__, reg, REFO_DIVSW_EN, false,
- CONFIG_SYS_HZ, false);
+ return wait_for_bit_le32(reg, REFO_DIVSW_EN, false,
+ CONFIG_SYS_HZ, false);
}
static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph)
/* Wait for ready */
mask = MPLL_RDY | MPLL_VREG_RDY;
- return wait_for_bit(__func__, priv->syscfg_base + CFGMPLL, mask,
- true, get_tbclk(), false);
+ return wait_for_bit_le32(priv->syscfg_base + CFGMPLL, mask,
+ true, get_tbclk(), false);
}
static void pic32_clk_init(struct udevice *dev)
#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
-#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17)
+#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
-#define RCC_APB2ENR_SAI1EN BIT(22)
-
/*
* RCC AHB1ENR specific definitions
*/
* RCC APB2ENR specific definitions
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
+#define RCC_APB2ENR_SAI1EN BIT(22)
enum periph_clock {
- SYSCFG_CLOCK_CFG,
TIMER2_CLOCK_CFG,
- STMMAC_CLOCK_CFG,
};
-struct stm32_clk_info stm32f4_clk_info = {
+static const struct stm32_clk_info stm32f4_clk_info = {
/* 180 MHz */
.sys_pll_psc = {
- .pll_m = 8,
.pll_n = 360,
.pll_p = 2,
.pll_q = 8,
.v2 = false,
};
-struct stm32_clk_info stm32f7_clk_info = {
+static const struct stm32_clk_info stm32f7_clk_info = {
/* 200 MHz */
.sys_pll_psc = {
- .pll_m = 25,
.pll_n = 400,
.pll_p = 2,
.pll_q = 8,
struct stm32_clk {
struct stm32_rcc_regs *base;
struct stm32_pwr_regs *pwr_regs;
- struct stm32_clk_info *info;
+ struct stm32_clk_info info;
+ unsigned long hse_rate;
};
static int configure_clocks(struct udevice *dev)
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
struct stm32_pwr_regs *pwr = priv->pwr_regs;
- struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
+ struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
u32 pllsaicfgr = 0;
/* Reset RCC configuration */
;
setbits_le32(®s->cfgr, ((
- sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
- | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
- | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
+ sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
+ | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
+ | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
/* Configure the main PLL */
setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
- sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
+ sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
- sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
+ sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
- ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
+ ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
- sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
+ sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
/* Configure the SAI PLL to get a 48 MHz source */
pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
while (!(readl(®s->cr) & RCC_CR_PLLRDY))
;
- if (priv->info->v2) { /*stm32f7 case */
+ if (priv->info.v2) { /*stm32f7 case */
/* select PLLSAI as 48MHz clock source */
setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
- if (priv->info->has_overdrive) {
+ if (priv->info.has_overdrive) {
/*
* Enable high performance mode
* System frequency up to 200 MHz
/* gate the SAI clock, needed for MMC 1&2 clocks */
setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
+#ifdef CONFIG_ETH_DESIGNWARE
+ /* gate the SYSCFG clock, needed to set RMII ethernet interface */
+ setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
+#endif
+
return 0;
}
pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
>> RCC_PLLCFGR_PLLQ_SHIFT;
- if (priv->info->v2) /*stm32f7 case */
+ if (priv->info.v2) /*stm32f7 case */
pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
else
pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
>> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
- return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip;
+ return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
}
/* PLL48CLK is selected from PLLQ */
return sysclk / pllq;
>> RCC_PLLCFGR_PLLN_SHIFT);
pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
- sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
+ sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
} else {
return -EINVAL;
}
}
}
+static ulong stm32_set_rate(struct clk *clk, ulong rate)
+{
+ return 0;
+}
+
static int stm32_clk_enable(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
void clock_setup(int peripheral)
{
switch (peripheral) {
- case SYSCFG_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
- break;
case TIMER2_CLOCK_CFG:
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
break;
- case STMMAC_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
- setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
- setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
- break;
default:
break;
}
static int stm32_clk_probe(struct udevice *dev)
{
struct ofnode_phandle_args args;
+ struct udevice *fixed_clock_dev = NULL;
+ struct clk clk;
int err;
debug("%s\n", __func__);
switch (dev_get_driver_data(dev)) {
case STM32F4:
- priv->info = &stm32f4_clk_info;
+ memcpy(&priv->info, &stm32f4_clk_info,
+ sizeof(struct stm32_clk_info));
break;
case STM32F7:
- priv->info = &stm32f7_clk_info;
+ memcpy(&priv->info, &stm32f7_clk_info,
+ sizeof(struct stm32_clk_info));
break;
default:
return -EINVAL;
}
- if (priv->info->has_overdrive) {
+ /* retrieve HSE frequency (external oscillator) */
+ err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
+ &fixed_clock_dev);
+
+ if (err) {
+ pr_err("Can't find fixed clock (%d)", err);
+ return err;
+ }
+
+ err = clk_request(fixed_clock_dev, &clk);
+ if (err) {
+ pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
+ err);
+ return err;
+ }
+
+ /*
+ * set pllm factor accordingly to the external oscillator
+ * frequency (HSE). For STM32F4 and STM32F7, we want VCO
+ * freq at 1MHz
+ * if input PLL frequency is 25Mhz, divide it by 25
+ */
+ clk.id = 0;
+ priv->hse_rate = clk_get_rate(&clk);
+
+ if (priv->hse_rate < 1000000) {
+ pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
+ priv->hse_rate);
+ return -EINVAL;
+ }
+
+ priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
+
+ if (priv->info.has_overdrive) {
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (err) {
.of_xlate = stm32_clk_of_xlate,
.enable = stm32_clk_enable,
.get_rate = stm32_clk_get_rate,
+ .set_rate = stm32_set_rate,
};
U_BOOT_DRIVER(stm32fx_clk) = {
help
Enable support for clock present on Renesas RCar SoCs.
+config CLK_RCAR_GEN2
+ bool "Renesas RCar Gen2 clock driver"
+ def_bool y if RCAR_32
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas RCar Gen2 SoC.
+
+config CLK_R8A7790
+ bool "Renesas R8A7790 clock driver"
+ def_bool y if R8A7790
+ depends on CLK_RCAR_GEN2
+ help
+ Enable this to support the clocks on Renesas R8A7790 SoC.
+
+config CLK_R8A7791
+ bool "Renesas R8A7791 clock driver"
+ def_bool y if R8A7791
+ depends on CLK_RCAR_GEN2
+ help
+ Enable this to support the clocks on Renesas R8A7791 SoC.
+
+config CLK_R8A7792
+ bool "Renesas R8A7792 clock driver"
+ def_bool y if R8A7792
+ depends on CLK_RCAR_GEN2
+ help
+ Enable this to support the clocks on Renesas R8A7792 SoC.
+
+config CLK_R8A7793
+ bool "Renesas R8A7793 clock driver"
+ def_bool y if R8A7793
+ depends on CLK_RCAR_GEN2
+ help
+ Enable this to support the clocks on Renesas R8A7793 SoC.
+
+config CLK_R8A7794
+ bool "Renesas R8A7794 clock driver"
+ def_bool y if R8A7794
+ depends on CLK_RCAR_GEN2
+ help
+ Enable this to support the clocks on Renesas R8A7794 SoC.
+
config CLK_RCAR_GEN3
bool "Renesas RCar Gen3 clock driver"
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
help
Enable this to support the clocks on Renesas RCar Gen3 SoC.
+
+config CLK_R8A7795
+ bool "Renesas R8A7795 clock driver"
+ def_bool y if R8A7795
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A7795 SoC.
+
+config CLK_R8A7796
+ bool "Renesas R8A7796 clock driver"
+ def_bool y if R8A7796
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A7796 SoC.
+
+config CLK_R8A77970
+ bool "Renesas R8A77970 clock driver"
+ def_bool y if R8A77970
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A77970 SoC.
+
+config CLK_R8A77995
+ bool "Renesas R8A77995 clock driver"
+ def_bool y if R8A77995
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A77995 SoC.
+obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
+obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
+obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
+obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
--- /dev/null
+/*
+ * Renesas RCar Gen2 CPG MSSR driver
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+#define CPG_RST_MODEMR 0x0060
+
+#define CPG_PLL0CR 0x00d8
+#define CPG_SDCKCR 0x0074
+
+struct clk_div_table {
+ u8 val;
+ u8 div;
+};
+
+/* SDHI divisors */
+static const struct clk_div_table cpg_sdh_div_table[] = {
+ { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_sd01_div_table[] = {
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
+ { 0, 0 },
+};
+
+static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div)
+{
+ while ((*table++).val) {
+ if ((*table).div == div)
+ return div;
+ }
+ return 0xff;
+}
+
+static int gen2_clk_enable(struct clk *clk)
+{
+ struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
+
+ return renesas_clk_endisable(clk, priv->base, true);
+}
+
+static int gen2_clk_disable(struct clk *clk)
+{
+ struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
+
+ return renesas_clk_endisable(clk, priv->base, false);
+}
+
+static ulong gen2_clk_get_rate(struct clk *clk)
+{
+ struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
+ struct cpg_mssr_info *info = priv->info;
+ struct clk parent;
+ const struct cpg_core_clk *core;
+ const struct rcar_gen2_cpg_pll_config *pll_config =
+ priv->cpg_pll_config;
+ u32 value, mult, div, rate = 0;
+ int ret;
+
+ debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
+
+ ret = renesas_clk_get_parent(clk, info, &parent);
+ if (ret) {
+ printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
+ return ret;
+ }
+
+ if (renesas_clk_is_mod(clk)) {
+ rate = gen2_clk_get_rate(&parent);
+ debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
+ __func__, __LINE__, parent.id, rate);
+ return rate;
+ }
+
+ ret = renesas_clk_get_core(clk, info, &core);
+ if (ret)
+ return ret;
+
+ switch (core->type) {
+ case CLK_TYPE_IN:
+ if (core->id == info->clk_extal_id) {
+ rate = clk_get_rate(&priv->clk_extal);
+ debug("%s[%i] EXTAL clk: rate=%u\n",
+ __func__, __LINE__, rate);
+ return rate;
+ }
+
+ if (core->id == info->clk_extal_usb_id) {
+ rate = clk_get_rate(&priv->clk_extal_usb);
+ debug("%s[%i] EXTALR clk: rate=%u\n",
+ __func__, __LINE__, rate);
+ return rate;
+ }
+
+ return -EINVAL;
+
+ case CLK_TYPE_FF:
+ rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
+ debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, core->mult, core->div, rate);
+ return rate;
+
+ case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */
+ value = (readl(priv->base + core->offset) & 0x3f) + 1;
+ rate = gen2_clk_get_rate(&parent) / value;
+ debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, value, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_MAIN:
+ rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
+ debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, pll_config->extal_div, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_PLL0:
+ /*
+ * PLL0 is a configurable multiplier clock except on R-Car
+ * V2H/E2. Register the PLL0 clock as a fixed factor clock for
+ * now as there's no generic multiplier clock implementation and
+ * we currently have no need to change the multiplier value.
+ */
+ mult = pll_config->pll0_mult;
+ if (!mult) {
+ value = readl(priv->base + CPG_PLL0CR);
+ mult = (((value >> 24) & 0x7f) + 1) * 2;
+ }
+
+ rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
+ debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
+ __func__, __LINE__, core->parent, mult, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_PLL1:
+ rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
+ debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, pll_config->pll1_mult, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_PLL3:
+ rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
+ debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, pll_config->pll3_mult, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_SDH:
+ value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
+ div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
+ rate = gen2_clk_get_rate(&parent) / div;
+ debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, div, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_SD0:
+ value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
+ div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
+ rate = gen2_clk_get_rate(&parent) / div;
+ debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, div, rate);
+ return rate;
+
+ case CLK_TYPE_GEN2_SD1:
+ value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
+ div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
+ rate = gen2_clk_get_rate(&parent) / div;
+ debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
+ __func__, __LINE__,
+ core->parent, div, rate);
+ return rate;
+ }
+
+ printf("%s[%i] unknown fail\n", __func__, __LINE__);
+
+ return -ENOENT;
+}
+
+static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
+{
+ return gen2_clk_get_rate(clk);
+}
+
+static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ debug("Invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ clk->id = (args->args[0] << 16) | args->args[1];
+
+ return 0;
+}
+
+const struct clk_ops gen2_clk_ops = {
+ .enable = gen2_clk_enable,
+ .disable = gen2_clk_disable,
+ .get_rate = gen2_clk_get_rate,
+ .set_rate = gen2_clk_set_rate,
+ .of_xlate = gen2_clk_of_xlate,
+};
+
+int gen2_clk_probe(struct udevice *dev)
+{
+ struct gen2_clk_priv *priv = dev_get_priv(dev);
+ struct cpg_mssr_info *info =
+ (struct cpg_mssr_info *)dev_get_driver_data(dev);
+ fdt_addr_t rst_base;
+ u32 cpg_mode;
+ int ret;
+
+ priv->base = (struct gen2_base *)devfdt_get_addr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ priv->info = info;
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
+ if (ret < 0)
+ return ret;
+
+ rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
+ if (rst_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ cpg_mode = readl(rst_base + CPG_RST_MODEMR);
+
+ priv->cpg_pll_config =
+ (struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
+ if (!priv->cpg_pll_config->extal_div)
+ return -EINVAL;
+
+ ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
+ if (ret < 0)
+ return ret;
+
+ if (info->extal_usb_node) {
+ ret = clk_get_by_name(dev, info->extal_usb_node,
+ &priv->clk_extal_usb);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+int gen2_clk_remove(struct udevice *dev)
+{
+ struct gen2_clk_priv *priv = dev_get_priv(dev);
+
+ return renesas_clk_remove(priv->base, priv->info);
+}
#include <wait_bit.h>
#include <asm/io.h>
-#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
-#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
-#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
-#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
#define CPG_RST_MODEMR 0x0060
#define CPG_RPC_POSTDIV_OFFSET 0
/*
- * Module Standby and Software Reset register offets.
- *
- * If the registers exist, these are valid for SH-Mobile, R-Mobile,
- * R-Car Gen2, R-Car Gen3, and RZ/G1.
- * These are NOT valid for R-Car Gen1 and RZ/A1!
- */
-
-/*
- * Module Stop Status Register offsets
- */
-
-static const u16 mstpsr[] = {
- 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
- 0x9A0, 0x9A4, 0x9A8, 0x9AC,
-};
-
-#define MSTPSR(i) mstpsr[i]
-
-
-/*
- * System Module Stop Control Register offsets
- */
-
-static const u16 smstpcr[] = {
- 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
- 0x990, 0x994, 0x998, 0x99C,
-};
-
-#define SMSTPCR(i) smstpcr[i]
-
-
-/* Realtime Module Stop Control Register offsets */
-#define RMSTPCR(i) (smstpcr[i] - 0x20)
-
-/* Modem Module Stop Control Register offsets (r8a73a4) */
-#define MMSTPCR(i) (smstpcr[i] + 0x20)
-
-/* Software Reset Clearing Register offsets */
-#define SRSTCLR(i) (0x940 + (i) * 4)
-
-struct gen3_clk_priv {
- void __iomem *base;
- struct clk clk_extal;
- struct clk clk_extalr;
- const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
- const struct cpg_core_clk *core_clk;
- u32 core_clk_size;
- const struct mssr_mod_clk *mod_clk;
- u32 mod_clk_size;
-};
-
-/*
- * Definitions of CPG Core Clocks
- *
- * These include:
- * - Clock outputs exported to DT
- * - External input clocks
- * - Internal CPG clocks
- */
-struct cpg_core_clk {
- /* Common */
- const char *name;
- unsigned int id;
- unsigned int type;
- /* Depending on type */
- unsigned int parent; /* Core Clocks only */
- unsigned int div;
- unsigned int mult;
- unsigned int offset;
-};
-
-enum clk_types {
- /* Generic */
- CLK_TYPE_IN, /* External Clock Input */
- CLK_TYPE_FF, /* Fixed Factor Clock */
-
- /* Custom definitions start here */
- CLK_TYPE_CUSTOM,
-};
-
-#define DEF_TYPE(_name, _id, _type...) \
- { .name = _name, .id = _id, .type = _type }
-#define DEF_BASE(_name, _id, _type, _parent...) \
- DEF_TYPE(_name, _id, _type, .parent = _parent)
-
-#define DEF_INPUT(_name, _id) \
- DEF_TYPE(_name, _id, CLK_TYPE_IN)
-#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
- DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
-#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
-#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
- _div_clean) \
- DEF_BASE(_name, _id, CLK_TYPE_FF, \
- (_parent_clean), .div = (_div_clean), 1)
-
-/*
- * Definitions of Module Clocks
- */
-struct mssr_mod_clk {
- const char *name;
- unsigned int id;
- unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
-};
-
-/* Convert from sparse base-100 to packed index space */
-#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
-
-#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
-
-#define DEF_MOD(_name, _mod, _parent...) \
- { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
-
-enum rcar_gen3_clk_types {
- CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
- CLK_TYPE_GEN3_PLL0,
- CLK_TYPE_GEN3_PLL1,
- CLK_TYPE_GEN3_PLL2,
- CLK_TYPE_GEN3_PLL3,
- CLK_TYPE_GEN3_PLL4,
- CLK_TYPE_GEN3_SD,
- CLK_TYPE_GEN3_RPC,
- CLK_TYPE_GEN3_R,
- CLK_TYPE_GEN3_PE,
- CLK_TYPE_GEN3_Z2,
-};
-
-struct rcar_gen3_cpg_pll_config {
- unsigned int extal_div;
- unsigned int pll1_mult;
- unsigned int pll3_mult;
-};
-
-enum clk_ids {
- /* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
-
- /* External Input Clocks */
- CLK_EXTAL,
- CLK_EXTALR,
-
- /* Internal Core Clocks */
- CLK_MAIN,
- CLK_PLL0,
- CLK_PLL1,
- CLK_PLL2,
- CLK_PLL3,
- CLK_PLL4,
- CLK_PLL1_DIV2,
- CLK_PLL1_DIV4,
- CLK_PLL0D2,
- CLK_PLL0D3,
- CLK_PLL0D5,
- CLK_PLL1D2,
- CLK_PE,
- CLK_S0,
- CLK_S1,
- CLK_S2,
- CLK_S3,
- CLK_SDSRC,
- CLK_RPCSRC,
- CLK_SSPSRC,
- CLK_RINT,
-
- /* Module Clocks */
- MOD_CLK_BASE
-};
-
-static const struct cpg_core_clk r8a7795_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
- DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
-
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
- DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
- DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
- DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
- DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
- DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
- DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
-
- DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
-
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
- DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
-};
-
-static const struct mssr_mod_clk r8a7795_mod_clks[] = {
- DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
- DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
- DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
- DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
- DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
- DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
- DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
- DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
- DEF_MOD("cmt3", 300, R8A7795_CLK_R),
- DEF_MOD("cmt2", 301, R8A7795_CLK_R),
- DEF_MOD("cmt1", 302, R8A7795_CLK_R),
- DEF_MOD("cmt0", 303, R8A7795_CLK_R),
- DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
- DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
- DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
- DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
- DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
- DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
- DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
- DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
- DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
- DEF_MOD("rwdt", 402, R8A7795_CLK_R),
- DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
- DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
- DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
- DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
- DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
- DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
- DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
- DEF_MOD("thermal", 522, R8A7795_CLK_CP),
- DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
- DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
- DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
- DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
- DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
- DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
- DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
- DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
- DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
- DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
- DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
- DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
- DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
- DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
- DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
- DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
- DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
- DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
- DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
- DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
- DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
- DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
- DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
- DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
- DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
- DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
- DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
- DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
- DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
- DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
- DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
- DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
- DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
- DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
- DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
- DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
- DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
- DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
- DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
- DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
- DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
- DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
- DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
- DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
- DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
- DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
- DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
- DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
- DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
- DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
- DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
- DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
- DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
- DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
- DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
- DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
- DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
- DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
- DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
- DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
- DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
- DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
- DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
- DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
- DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
- DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
- DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
- DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
- DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
- DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
- DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
- DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
- DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
- DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
- DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
-};
-
-static const struct cpg_core_clk r8a7796_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
- DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
-
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
- DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
- DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
- DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
- DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
- DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
- DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
-
- DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
-
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
- DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
-};
-
-static const struct mssr_mod_clk r8a7796_mod_clks[] = {
- DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
- DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
- DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
- DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
- DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
- DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
- DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
- DEF_MOD("cmt3", 300, R8A7796_CLK_R),
- DEF_MOD("cmt2", 301, R8A7796_CLK_R),
- DEF_MOD("cmt1", 302, R8A7796_CLK_R),
- DEF_MOD("cmt0", 303, R8A7796_CLK_R),
- DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
- DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
- DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
- DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
- DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
- DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
- DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
- DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
- DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
- DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
- DEF_MOD("rwdt", 402, R8A7796_CLK_R),
- DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
- DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
- DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
- DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
- DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
- DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
- DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
- DEF_MOD("thermal", 522, R8A7796_CLK_CP),
- DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
- DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
- DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
- DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
- DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
- DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
- DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
- DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
- DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
- DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
- DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
- DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
- DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
- DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
- DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
- DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
- DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
- DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
- DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
- DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
- DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
- DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
- DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
- DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
- DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
- DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
- DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
- DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
- DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
- DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
- DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
- DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
- DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
- DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
- DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
- DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
- DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
- DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
- DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
- DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
- DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
- DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
- DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
- DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
- DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
- DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
- DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
- DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
- DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
- DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
- DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
- DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
- DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
- DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
- DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
- DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
- DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
- DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
- DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
- DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
- DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
- DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
- DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
- DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
-};
-
-static const struct cpg_core_clk r8a77970_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
-
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
- DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
-
- DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
-
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
- DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
-};
-
-static const struct mssr_mod_clk r8a77970_mod_clks[] = {
- DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
- DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
- DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
- DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
- DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
- DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("thermal", 522, R8A77970_CLK_CP),
- DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
- DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
- DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
- DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
- DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
- DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
- DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
- DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
- DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
- DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
- DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
- DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
- DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
- DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
- DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
- DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
- DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
- DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
- DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
- DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
- DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
- DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
- DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
- DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
-};
-
-static const struct cpg_core_clk r8a77995_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
-
- DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
- DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
- DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
- DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
- DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
- DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
- DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
- DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
- DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
- DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
- DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
- DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
- DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
- DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
- DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
-
- DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
- DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
- DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
- DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
-
- DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
-};
-
-static const struct mssr_mod_clk r8a77995_mod_clks[] = {
- DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
- DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
- DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
- DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
- DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
- DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
- DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
- DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
- DEF_MOD("cmt3", 300, R8A77995_CLK_R),
- DEF_MOD("cmt2", 301, R8A77995_CLK_R),
- DEF_MOD("cmt1", 302, R8A77995_CLK_R),
- DEF_MOD("cmt0", 303, R8A77995_CLK_R),
- DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
- DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
- DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
- DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
- DEF_MOD("rwdt", 402, R8A77995_CLK_R),
- DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
- DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
- DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
- DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
- DEF_MOD("thermal", 522, R8A77995_CLK_CP),
- DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
- DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
- DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
- DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
- DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
- DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
- DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
- DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
- DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
- DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
- DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
- DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
- DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
- DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
- DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
- DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
- DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
- DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
- DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
- DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
- DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
- DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
- DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
- DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
- DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
- DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
- DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
- DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
- DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
- DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
- DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
- DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
- DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
- DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
- DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
- DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
-};
-
-/*
- * CPG Clock Data
- */
-
-/*
- * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
- * 14 13 19 17 (MHz)
- *-------------------------------------------------------------------
- * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
- * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
- * 0 0 1 0 Prohibited setting
- * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
- * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
- * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
- * 0 1 1 0 Prohibited setting
- * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
- * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
- * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
- * 1 0 1 0 Prohibited setting
- * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
- * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
- * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
- * 1 1 1 0 Prohibited setting
- * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
- */
-#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
- (((md) & BIT(13)) >> 11) | \
- (((md) & BIT(19)) >> 18) | \
- (((md) & BIT(17)) >> 17))
-
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
- /* EXTAL div PLL1 mult PLL3 mult */
- { 1, 192, 192, },
- { 1, 192, 128, },
- { 0, /* Prohibited setting */ },
- { 1, 192, 192, },
- { 1, 160, 160, },
- { 1, 160, 106, },
- { 0, /* Prohibited setting */ },
- { 1, 160, 160, },
- { 1, 128, 128, },
- { 1, 128, 84, },
- { 0, /* Prohibited setting */ },
- { 1, 128, 128, },
- { 2, 192, 192, },
- { 2, 192, 128, },
- { 0, /* Prohibited setting */ },
- { 2, 192, 192, },
-};
-
-/*
* SDn Clock
*/
#define CPG_SD_STP_HCK BIT(9)
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
};
-static bool gen3_clk_is_mod(struct clk *clk)
-{
- return (clk->id >> 16) == CPG_MOD;
-}
-
-static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
-{
- struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- const unsigned long clkid = clk->id & 0xffff;
- int i;
-
- if (!gen3_clk_is_mod(clk))
- return -EINVAL;
-
- for (i = 0; i < priv->mod_clk_size; i++) {
- if (priv->mod_clk[i].id != MOD_CLK_ID(clkid))
- continue;
-
- *mssr = &priv->mod_clk[i];
- return 0;
- }
-
- return -ENODEV;
-}
-
-static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
-{
- struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- const unsigned long clkid = clk->id & 0xffff;
- int i;
-
- if (gen3_clk_is_mod(clk))
- return -EINVAL;
-
- for (i = 0; i < priv->core_clk_size; i++) {
- if (priv->core_clk[i].id != clkid)
- continue;
-
- *core = &priv->core_clk[i];
- return 0;
- }
-
- return -ENODEV;
-}
-
-static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
-{
- const struct cpg_core_clk *core;
- const struct mssr_mod_clk *mssr;
- int ret;
-
- if (gen3_clk_is_mod(clk)) {
- ret = gen3_clk_get_mod(clk, &mssr);
- if (ret)
- return ret;
-
- parent->id = mssr->parent;
- } else {
- ret = gen3_clk_get_core(clk, &core);
- if (ret)
- return ret;
-
- if (core->type == CLK_TYPE_IN)
- parent->id = ~0; /* Top-level clock */
- else
- parent->id = core->parent;
- }
-
- parent->dev = clk->dev;
-
- return 0;
-}
-
static int gen3_clk_setup_sdif_div(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
+ struct cpg_mssr_info *info = priv->info;
const struct cpg_core_clk *core;
struct clk parent;
int ret;
- ret = gen3_clk_get_parent(clk, &parent);
+ ret = renesas_clk_get_parent(clk, info, &parent);
if (ret) {
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
return ret;
}
- if (gen3_clk_is_mod(&parent))
+ if (renesas_clk_is_mod(&parent))
return 0;
- ret = gen3_clk_get_core(&parent, &core);
+ ret = renesas_clk_get_core(&parent, info, &core);
if (ret)
return ret;
return 0;
}
-static int gen3_clk_endisable(struct clk *clk, bool enable)
+static int gen3_clk_enable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- const unsigned long clkid = clk->id & 0xffff;
- const unsigned int reg = clkid / 100;
- const unsigned int bit = clkid % 100;
- const u32 bitmask = BIT(bit);
- int ret;
-
- if (!gen3_clk_is_mod(clk))
- return -EINVAL;
+ int ret = gen3_clk_setup_sdif_div(clk);
- debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
- clkid, reg, bit, enable ? "ON" : "OFF");
+ if (ret)
+ return ret;
- if (enable) {
- ret = gen3_clk_setup_sdif_div(clk);
- if (ret)
- return ret;
- clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
- return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
- bitmask, 0, 100, 0);
- } else {
- setbits_le32(priv->base + SMSTPCR(reg), bitmask);
- return 0;
- }
-}
-
-static int gen3_clk_enable(struct clk *clk)
-{
- return gen3_clk_endisable(clk, true);
+ return renesas_clk_endisable(clk, priv->base, true);
}
static int gen3_clk_disable(struct clk *clk)
{
- return gen3_clk_endisable(clk, false);
+ struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
+
+ return renesas_clk_endisable(clk, priv->base, false);
}
static ulong gen3_clk_get_rate(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
+ struct cpg_mssr_info *info = priv->info;
struct clk parent;
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
- ret = gen3_clk_get_parent(clk, &parent);
+ ret = renesas_clk_get_parent(clk, info, &parent);
if (ret) {
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
return ret;
}
- if (gen3_clk_is_mod(clk)) {
+ if (renesas_clk_is_mod(clk)) {
rate = gen3_clk_get_rate(&parent);
debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
__func__, __LINE__, parent.id, rate);
return rate;
}
- ret = gen3_clk_get_core(clk, &core);
+ ret = renesas_clk_get_core(clk, info, &core);
if (ret)
return ret;
switch (core->type) {
case CLK_TYPE_IN:
- if (core->id == CLK_EXTAL) {
+ if (core->id == info->clk_extal_id) {
rate = clk_get_rate(&priv->clk_extal);
debug("%s[%i] EXTAL clk: rate=%u\n",
__func__, __LINE__, rate);
return rate;
}
- if (core->id == CLK_EXTALR) {
+ if (core->id == info->clk_extalr_id) {
rate = clk_get_rate(&priv->clk_extalr);
debug("%s[%i] EXTALR clk: rate=%u\n",
__func__, __LINE__, rate);
return 0;
}
-static const struct clk_ops gen3_clk_ops = {
+const struct clk_ops gen3_clk_ops = {
.enable = gen3_clk_enable,
.disable = gen3_clk_disable,
.get_rate = gen3_clk_get_rate,
.of_xlate = gen3_clk_of_xlate,
};
-enum gen3_clk_model {
- CLK_R8A7795,
- CLK_R8A7796,
- CLK_R8A77970,
- CLK_R8A77995,
-};
-
-static int gen3_clk_probe(struct udevice *dev)
+int gen3_clk_probe(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
- enum gen3_clk_model model = dev_get_driver_data(dev);
+ struct cpg_mssr_info *info =
+ (struct cpg_mssr_info *)dev_get_driver_data(dev);
fdt_addr_t rst_base;
u32 cpg_mode;
int ret;
if (!priv->base)
return -EINVAL;
- switch (model) {
- case CLK_R8A7795:
- priv->core_clk = r8a7795_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks);
- priv->mod_clk = r8a7795_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a7795-rst");
- if (ret < 0)
- return ret;
- break;
- case CLK_R8A7796:
- priv->core_clk = r8a7796_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks);
- priv->mod_clk = r8a7796_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a7796-rst");
- if (ret < 0)
- return ret;
- break;
- case CLK_R8A77970:
- priv->core_clk = r8a77970_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks);
- priv->mod_clk = r8a77970_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a77970-rst");
- if (ret < 0)
- return ret;
- break;
- case CLK_R8A77995:
- priv->core_clk = r8a77995_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks);
- priv->mod_clk = r8a77995_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a77995-rst");
- if (ret < 0)
- return ret;
- break;
- default:
- return -EINVAL;
- }
+ priv->info = info;
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
+ if (ret < 0)
+ return ret;
rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
if (rst_base == FDT_ADDR_T_NONE)
cpg_mode = readl(rst_base + CPG_RST_MODEMR);
- priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+ priv->cpg_pll_config =
+ (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;
if (ret < 0)
return ret;
- if (model != CLK_R8A77995) {
- ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
+ if (info->extalr_node) {
+ ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
if (ret < 0)
return ret;
}
return 0;
}
-struct mstp_stop_table {
- u32 dis;
- u32 en;
-};
-
-static struct mstp_stop_table r8a7795_mstp_table[] = {
- { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
- { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
- { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 },
- { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 },
- { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
-};
-
-static struct mstp_stop_table r8a7796_mstp_table[] = {
- { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
- { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
- { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
-};
-
-static struct mstp_stop_table r8a77970_mstp_table[] = {
- { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
- { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
- { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
-};
-
-static struct mstp_stop_table r8a77995_mstp_table[] = {
- { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
- { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
- { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
-};
-
-#define TSTR0 0x04
-#define TSTR0_STR0 BIT(0)
-
-static int gen3_clk_remove(struct udevice *dev)
+int gen3_clk_remove(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
- enum gen3_clk_model model = dev_get_driver_data(dev);
- struct mstp_stop_table *tbl;
- unsigned int i, tbl_size;
-
- switch (model) {
- case CLK_R8A7795:
- tbl = r8a7795_mstp_table;
- tbl_size = ARRAY_SIZE(r8a7795_mstp_table);
- break;
- case CLK_R8A7796:
- tbl = r8a7796_mstp_table;
- tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
- break;
- case CLK_R8A77970:
- tbl = r8a77970_mstp_table;
- tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
- break;
- case CLK_R8A77995:
- tbl = r8a77995_mstp_table;
- tbl_size = ARRAY_SIZE(r8a77995_mstp_table);
- break;
- default:
- return -EINVAL;
- }
-
- /* Stop TMU0 */
- clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
- /* Stop module clock */
- for (i = 0; i < tbl_size; i++) {
- clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en);
- clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0);
- }
-
- return 0;
+ return renesas_clk_remove(priv->base, priv->info);
}
-
-static const struct udevice_id gen3_clk_ids[] = {
- { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
- { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
- { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
- { .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 },
- { }
-};
-
-U_BOOT_DRIVER(clk_gen3) = {
- .name = "clk_gen3",
- .id = UCLASS_CLK,
- .of_match = gen3_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
- .ops = &gen3_clk_ops,
- .probe = gen3_clk_probe,
- .remove = gen3_clk_remove,
-};
--- /dev/null
+/*
+ * r8a7790 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
+ DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
+ DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
+ DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
+ DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
+ DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
+ DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+ DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
+ DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248),
+ DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
+};
+
+static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
+ DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
+ DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
+ DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
+ DEF_MOD("jpu", 106, R8A7790_CLK_M2),
+ DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
+ DEF_MOD("tmu1", 111, R8A7790_CLK_P),
+ DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
+ DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
+ DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7790_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7790_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7790_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
+ DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7790_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7790_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7790_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
+ DEF_MOD("msiof3", 215, R8A7790_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7790_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS),
+ DEF_MOD("iic2", 300, R8A7790_CLK_HP),
+ DEF_MOD("tpu0", 304, R8A7790_CLK_CP),
+ DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1),
+ DEF_MOD("scif2", 310, R8A7790_CLK_P),
+ DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2),
+ DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1),
+ DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7790_CLK_HP),
+ DEF_MOD("pciec", 319, R8A7790_CLK_MP),
+ DEF_MOD("iic1", 323, R8A7790_CLK_HP),
+ DEF_MOD("usb3.0", 328, R8A7790_CLK_MP),
+ DEF_MOD("cmt1", 329, R8A7790_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7790_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
+ DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
+ DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP),
+ DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7790_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7790_CLK_HP),
+ DEF_MOD("hscif1", 716, R8A7790_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7790_CLK_ZS),
+ DEF_MOD("scif1", 720, R8A7790_CLK_P),
+ DEF_MOD("scif0", 721, R8A7790_CLK_P),
+ DEF_MOD("du2", 722, R8A7790_CLK_ZX),
+ DEF_MOD("du1", 723, R8A7790_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7790_CLK_ZX),
+ DEF_MOD("lvds1", 725, R8A7790_CLK_ZX),
+ DEF_MOD("lvds0", 726, R8A7790_CLK_ZX),
+ DEF_MOD("mlb", 802, R8A7790_CLK_HP),
+ DEF_MOD("vin3", 808, R8A7790_CLK_ZG),
+ DEF_MOD("vin2", 809, R8A7790_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7790_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7790_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7790_CLK_HP),
+ DEF_MOD("ether", 813, R8A7790_CLK_P),
+ DEF_MOD("sata1", 814, R8A7790_CLK_ZS),
+ DEF_MOD("sata0", 815, R8A7790_CLK_ZS),
+ DEF_MOD("gyro-adc", 901, R8A7790_CLK_P),
+ DEF_MOD("gpio5", 907, R8A7790_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7790_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7790_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7790_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7790_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7790_CLK_CP),
+ DEF_MOD("can1", 915, R8A7790_CLK_P),
+ DEF_MOD("can0", 916, R8A7790_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI),
+ DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP),
+ DEF_MOD("i2c3", 928, R8A7790_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7790_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7790_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7790_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7790_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7790_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *1
+ *---------------------------------------------------
+ * 0 0 0 15 x172/2 x208/2 x106
+ * 0 0 1 15 x172/2 x208/2 x88
+ * 0 1 0 20 x130/2 x156/2 x80
+ * 0 1 1 20 x130/2 x156/2 x66
+ * 1 0 0 26 / 2 x200/2 x240/2 x122
+ * 1 0 1 26 / 2 x200/2 x240/2 x102
+ * 1 1 0 30 / 2 x172/2 x208/2 x106
+ * 1 1 1 30 / 2 x172/2 x208/2 x88
+ *
+ * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
+ { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
+};
+
+static const struct mstp_stop_table r8a7790_mstp_table[] = {
+ { 0x00640801, 0x400000, 0x00640801, 0x0 },
+ { 0xDB6E9BDF, 0x0, 0xDB6E9BDF, 0x0 },
+ { 0x300DA1FC, 0x2010, 0x300DA1FC, 0x0 },
+ { 0xF08CF831, 0x0, 0xF08CF831, 0x0 },
+ { 0x80000184, 0x180, 0x80000184, 0x0 },
+ { 0x44C00046, 0x0, 0x44C00046, 0x0 },
+ { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
+ { 0x07F30718, 0x200000, 0x07F30718, 0x0 },
+ { 0x01F0FF84, 0x0, 0x01F0FF84, 0x0 },
+ { 0xF5979FCF, 0x0, 0xF5979FCF, 0x0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
+ { 0x00000000, 0x0, 0x00000000, 0x0 },
+};
+
+static const void *r8a7790_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a7790_cpg_mssr_info = {
+ .core_clk = r8a7790_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7790_core_clks),
+ .mod_clk = r8a7790_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7790_mod_clks),
+ .mstp_table = r8a7790_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table),
+ .reset_node = "renesas,r8a7790-rst",
+ .extal_usb_node = "usb_extal",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extal_usb_id = CLK_USB_EXTAL,
+ .pll0_div = 2,
+ .get_pll_config = r8a7790_get_pll_config,
+};
+
+static const struct udevice_id r8a7790_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7790-cpg-mssr",
+ .data = (ulong)&r8a7790_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7790) = {
+ .name = "clk_r8a7790",
+ .id = UCLASS_CLK,
+ .of_match = r8a7790_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .ops = &gen2_clk_ops,
+ .probe = gen2_clk_probe,
+ .remove = gen2_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A7791 CPG MSSR driver
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7791 Clock Pulse Generator / Module Standby and Software Reset
+ * Copyright (C) 2015-2017 Glider bvba
+ * Based on clk-rcar-gen2.c
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7791_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
+ DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
+ DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
+ DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+ DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
+ DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
+};
+
+static const struct mssr_mod_clk r8a7791_mod_clks[] = {
+ DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
+ DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
+ DEF_MOD("jpu", 106, R8A7791_CLK_M2),
+ DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
+ DEF_MOD("tmu1", 111, R8A7791_CLK_P),
+ DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
+ DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7791_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7791_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7791_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
+ DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
+ DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7791_CLK_HP),
+ DEF_MOD("pciec", 319, R8A7791_CLK_MP),
+ DEF_MOD("iic1", 323, R8A7791_CLK_HP),
+ DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
+ DEF_MOD("cmt1", 329, R8A7791_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7791_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
+ DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
+ DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
+ DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7791_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
+ DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
+ DEF_MOD("scif5", 714, R8A7791_CLK_P),
+ DEF_MOD("scif4", 715, R8A7791_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7791_CLK_P),
+ DEF_MOD("scif2", 719, R8A7791_CLK_P),
+ DEF_MOD("scif1", 720, R8A7791_CLK_P),
+ DEF_MOD("scif0", 721, R8A7791_CLK_P),
+ DEF_MOD("du1", 723, R8A7791_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7791_CLK_ZX),
+ DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
+ DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
+ DEF_MOD("mlb", 802, R8A7791_CLK_HP),
+ DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
+ DEF_MOD("ether", 813, R8A7791_CLK_P),
+ DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
+ DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
+ DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
+ DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
+ DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
+ DEF_MOD("can1", 915, R8A7791_CLK_P),
+ DEF_MOD("can0", 916, R8A7791_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
+ DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
+ DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+ DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
+ DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
+ DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *1
+ *---------------------------------------------------
+ * 0 0 0 15 x172/2 x208/2 x106
+ * 0 0 1 15 x172/2 x208/2 x88
+ * 0 1 0 20 x130/2 x156/2 x80
+ * 0 1 1 20 x130/2 x156/2 x66
+ * 1 0 0 26 / 2 x200/2 x240/2 x122
+ * 1 0 1 26 / 2 x200/2 x240/2 x102
+ * 1 1 0 30 / 2 x172/2 x208/2 x106
+ * 1 1 1 30 / 2 x172/2 x208/2 x88
+ *
+ * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+ { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
+ { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
+};
+
+static const struct mstp_stop_table r8a7791_mstp_table[] = {
+ { 0x00640801, 0x400000, 0x00640801, 0x0 },
+ { 0x9B6C9B5A, 0x0, 0x9B6C9B5A, 0x0 },
+ { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
+ { 0xF08CD810, 0x0, 0xF08CD810, 0x0 },
+ { 0x800001C4, 0x180, 0x800001C4, 0x0 },
+ { 0x44C00046, 0x0, 0x44C00046, 0x0 },
+ { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
+ { 0x05BFE618, 0x200000, 0x05BFE618, 0x0 },
+ { 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 },
+ { 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
+ { 0x000001C0, 0x0, 0x000001C0, 0x0 },
+};
+
+static const void *r8a7791_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a7791_cpg_mssr_info = {
+ .core_clk = r8a7791_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7791_core_clks),
+ .mod_clk = r8a7791_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7791_mod_clks),
+ .mstp_table = r8a7791_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
+ .reset_node = "renesas,r8a7791-rst",
+ .extal_usb_node = "usb_extal",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extal_usb_id = CLK_USB_EXTAL,
+ .pll0_div = 2,
+ .get_pll_config = r8a7791_get_pll_config,
+};
+
+static const struct udevice_id r8a7791_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7791-cpg-mssr",
+ .data = (ulong)&r8a7791_cpg_mssr_info
+ },
+ {
+ .compatible = "renesas,r8a7793-cpg-mssr",
+ .data = (ulong)&r8a7791_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7791) = {
+ .name = "clk_r8a7791",
+ .id = UCLASS_CLK,
+ .of_match = r8a7791_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .ops = &gen2_clk_ops,
+ .probe = gen2_clk_probe,
+ .remove = gen2_clk_remove,
+};
--- /dev/null
+/*
+ * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+
+ DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
+ DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
+ DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
+ DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
+ DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
+ DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
+ DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
+ DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
+};
+
+static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
+ DEF_MOD("jpu", 106, R8A7792_CLK_M2),
+ DEF_MOD("tmu1", 111, R8A7792_CLK_P),
+ DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7792_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7792_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7792_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
+ DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
+ DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
+ DEF_MOD("cmt1", 329, R8A7792_CLK_R),
+ DEF_MOD("irqc", 407, R8A7792_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
+ DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7792_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7792_CLK_P),
+ DEF_MOD("scif2", 719, R8A7792_CLK_P),
+ DEF_MOD("scif1", 720, R8A7792_CLK_P),
+ DEF_MOD("scif0", 721, R8A7792_CLK_P),
+ DEF_MOD("du1", 723, R8A7792_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7792_CLK_ZX),
+ DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
+ DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
+ DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
+ DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
+ DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
+ DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
+ DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
+ DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
+ DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
+ DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
+ DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
+ DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
+ DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
+ DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
+ DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
+ DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
+ DEF_MOD("can1", 915, R8A7792_CLK_P),
+ DEF_MOD("can0", 916, R8A7792_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
+ DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
+ DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
+ DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
+ DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+};
+
+static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *2
+ *---------------------------------------------------
+ * 0 0 0 15 x200/3 x208/2 x106
+ * 0 0 1 15 x200/3 x208/2 x88
+ * 0 1 0 20 x150/3 x156/2 x80
+ * 0 1 1 20 x150/3 x156/2 x66
+ * 1 0 0 26 / 2 x230/3 x240/2 x122
+ * 1 0 1 26 / 2 x230/3 x240/2 x102
+ * 1 1 0 30 / 2 x200/3 x208/2 x106
+ * 1 1 1 30 / 2 x200/3 x208/2 x88
+ *
+ * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
+ * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ { 1, 208, 106, 200 },
+ { 1, 208, 88, 200 },
+ { 1, 156, 80, 150 },
+ { 1, 156, 66, 150 },
+ { 2, 240, 122, 230 },
+ { 2, 240, 102, 230 },
+ { 2, 208, 106, 200 },
+ { 2, 208, 88, 200 },
+};
+
+static const struct mstp_stop_table r8a7792_mstp_table[] = {
+ { 0x00400801, 0x400000, 0x00400801, 0x0 },
+ { 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
+ { 0x108CE100, 0x0, 0x108CE100, 0x80000 },
+ { 0x20004010, 0x4000, 0x20004010, 0x0 },
+ { 0x80000184, 0x180, 0x80000184, 0x0 },
+ { 0x44C00004, 0x0, 0x44C00004, 0x0 },
+ { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
+ { 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
+ { 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
+ { 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
+ { 0x00001820, 0x0, 0x00001820, 0x0 },
+ { 0x00000008, 0x0, 0x00000008, 0x0 },
+};
+
+static const void *r8a7792_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
+ .core_clk = r8a7792_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7792_core_clks),
+ .mod_clk = r8a7792_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7792_mod_clks),
+ .mstp_table = r8a7792_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
+ .reset_node = "renesas,r8a7792-rst",
+ .extal_usb_node = "usb_extal",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extal_usb_id = CLK_USB_EXTAL,
+ .pll0_div = 2,
+ .get_pll_config = r8a7792_get_pll_config,
+};
+
+static const struct udevice_id r8a7792_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7792-cpg-mssr",
+ .data = (ulong)&r8a7792_cpg_mssr_info
+ },
+ {
+ .compatible = "renesas,r8a7793-cpg-mssr",
+ .data = (ulong)&r8a7792_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7792) = {
+ .name = "clk_r8a7792",
+ .id = UCLASS_CLK,
+ .of_match = r8a7792_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .ops = &gen2_clk_ops,
+ .probe = gen2_clk_probe,
+ .remove = gen2_clk_remove,
+};
--- /dev/null
+/*
+ * r8a7794 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
+ DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
+ DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
+ DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+};
+
+static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
+ DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
+ DEF_MOD("jpu", 106, R8A7794_CLK_M2),
+ DEF_MOD("tmu1", 111, R8A7794_CLK_P),
+ DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7794_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7794_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7794_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
+ DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7794_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7794_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7794_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7794_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7794_CLK_CP),
+ DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2),
+ DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7794_CLK_HP),
+ DEF_MOD("iic1", 323, R8A7794_CLK_HP),
+ DEF_MOD("cmt1", 329, R8A7794_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7794_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
+ DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
+ DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP),
+ DEF_MOD("pwm", 523, R8A7794_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7794_CLK_HP),
+ DEF_MOD("hscif2", 713, R8A7794_CLK_ZS),
+ DEF_MOD("scif5", 714, R8A7794_CLK_P),
+ DEF_MOD("scif4", 715, R8A7794_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7794_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7794_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7794_CLK_P),
+ DEF_MOD("scif2", 719, R8A7794_CLK_P),
+ DEF_MOD("scif1", 720, R8A7794_CLK_P),
+ DEF_MOD("scif0", 721, R8A7794_CLK_P),
+ DEF_MOD("du1", 723, R8A7794_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7794_CLK_ZX),
+ DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX),
+ DEF_MOD("mlb", 802, R8A7794_CLK_HP),
+ DEF_MOD("vin1", 810, R8A7794_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7794_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7794_CLK_HP),
+ DEF_MOD("ether", 813, R8A7794_CLK_P),
+ DEF_MOD("gyro-adc", 901, R8A7794_CLK_P),
+ DEF_MOD("gpio6", 905, R8A7794_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7794_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7794_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7794_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7794_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7794_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7794_CLK_CP),
+ DEF_MOD("can1", 915, R8A7794_CLK_P),
+ DEF_MOD("can0", 916, R8A7794_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI),
+ DEF_MOD("i2c5", 925, R8A7794_CLK_HP),
+ DEF_MOD("i2c4", 927, R8A7794_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7794_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7794_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7794_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7794_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7794_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7794_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scifa3", 1106, R8A7794_CLK_MP),
+ DEF_MOD("scifa4", 1107, R8A7794_CLK_MP),
+ DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
+};
+
+static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *2
+ *---------------------------------------------------
+ * 0 0 1 15 x200/3 x208/2 x88
+ * 0 1 1 20 x150/3 x156/2 x66
+ * 1 0 1 26 / 2 x230/3 x240/2 x102
+ * 1 1 1 30 / 2 x200/3 x208/2 x88
+ *
+ * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
+ * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
+ { 1, 208, 88, 200 },
+ { 1, 156, 66, 150 },
+ { 2, 240, 102, 230 },
+ { 2, 208, 88, 200 },
+};
+
+static const struct mstp_stop_table r8a7794_mstp_table[] = {
+ { 0x00440801, 0x400000, 0x00440801, 0x0 },
+ { 0x936899DA, 0x0, 0x936899DA, 0x0 },
+ { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
+ { 0xE084D810, 0x0, 0xE084D810, 0x0 },
+ { 0x800001C4, 0x180, 0x800001C4, 0x0 },
+ { 0x40C00044, 0x0, 0x40C00044, 0x0 },
+ { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
+ { 0x013FE618, 0x80000, 0x013FE618, 0x0 },
+ { 0x40803C05, 0x0, 0x40803C05, 0x0 },
+ { 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
+ { 0x000001C0, 0x0, 0x000001C0, 0x0 },
+};
+
+static const void *r8a7794_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a7794_cpg_mssr_info = {
+ .core_clk = r8a7794_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7794_core_clks),
+ .mod_clk = r8a7794_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7794_mod_clks),
+ .mstp_table = r8a7794_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table),
+ .reset_node = "renesas,r8a7794-rst",
+ .extal_usb_node = "usb_extal",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extal_usb_id = CLK_USB_EXTAL,
+ .pll0_div = 2,
+ .get_pll_config = r8a7794_get_pll_config,
+};
+
+static const struct udevice_id r8a7794_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7794-cpg-mssr",
+ .data = (ulong)&r8a7794_cpg_mssr_info
+ },
+ {
+ .compatible = "renesas,r8a7793-cpg-mssr",
+ .data = (ulong)&r8a7794_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7794) = {
+ .name = "clk_r8a7794",
+ .id = UCLASS_CLK,
+ .of_match = r8a7794_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .ops = &gen2_clk_ops,
+ .probe = gen2_clk_probe,
+ .remove = gen2_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A7795 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_SSPSRC,
+ CLK_RINT,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7795_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
+ DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
+ DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
+ DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
+ DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
+
+ DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a7795_mod_clks[] = {
+ DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
+ DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
+ DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
+ DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
+ DEF_MOD("cmt3", 300, R8A7795_CLK_R),
+ DEF_MOD("cmt2", 301, R8A7795_CLK_R),
+ DEF_MOD("cmt1", 302, R8A7795_CLK_R),
+ DEF_MOD("cmt0", 303, R8A7795_CLK_R),
+ DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
+ DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
+ DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
+ DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
+ DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
+ DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
+ DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
+ DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
+ DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A7795_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
+ DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
+ DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
+ DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
+ DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
+ DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
+ DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
+ DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
+ DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
+ DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
+ DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
+ DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
+ DEF_MOD("thermal", 522, R8A7795_CLK_CP),
+ DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
+ DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
+ DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
+ DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
+ DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
+ DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
+ DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
+ DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
+ DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
+ DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
+ DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
+ DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
+ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
+ DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
+ DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
+ DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
+ DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
+ DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
+ DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
+ DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
+ DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
+ DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
+ DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
+ DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
+ DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
+ DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
+ DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
+ DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
+ DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
+ DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
+ DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
+ DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
+ DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
+ DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
+ DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
+ DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
+ * 14 13 19 17 (MHz)
+ *-------------------------------------------------------------------
+ * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
+ * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
+ * 0 0 1 0 Prohibited setting
+ * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
+ * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
+ * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
+ * 0 1 1 0 Prohibited setting
+ * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
+ * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
+ * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
+ * 1 0 1 0 Prohibited setting
+ * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
+ * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
+ * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
+ * 1 1 1 0 Prohibited setting
+ * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
+ (((md) & BIT(13)) >> 11) | \
+ (((md) & BIT(19)) >> 18) | \
+ (((md) & BIT(17)) >> 17))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 192, 1, 192, 1, },
+ { 1, 192, 1, 128, 1, },
+ { 0, /* Prohibited setting */ },
+ { 1, 192, 1, 192, 1, },
+ { 1, 160, 1, 160, 1, },
+ { 1, 160, 1, 106, 1, },
+ { 0, /* Prohibited setting */ },
+ { 1, 160, 1, 160, 1, },
+ { 1, 128, 1, 128, 1, },
+ { 1, 128, 1, 84, 1, },
+ { 0, /* Prohibited setting */ },
+ { 1, 128, 1, 128, 1, },
+ { 2, 192, 1, 192, 1, },
+ { 2, 192, 1, 128, 1, },
+ { 0, /* Prohibited setting */ },
+ { 2, 192, 1, 192, 1, },
+};
+
+static const struct mstp_stop_table r8a7795_mstp_table[] = {
+ { 0x00640800, 0x0, 0x00640800, 0 },
+ { 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
+ { 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
+ { 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
+ { 0x80000184, 0x180, 0x80000184, 0 },
+ { 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
+ { 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
+ { 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 },
+ { 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
+ { 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+ { 0x00000000, 0x0, 0x00000000, 0 },
+};
+
+static const void *r8a7795_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
+ .core_clk = r8a7795_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
+ .mod_clk = r8a7795_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks),
+ .mstp_table = r8a7795_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
+ .reset_node = "renesas,r8a7795-rst",
+ .extalr_node = "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a7795_get_pll_config,
+};
+
+static const struct udevice_id r8a7795_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7795-cpg-mssr",
+ .data = (ulong)&r8a7795_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7795) = {
+ .name = "clk_r8a7795",
+ .id = UCLASS_CLK,
+ .of_match = r8a7795_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A7796 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_SSPSRC,
+ CLK_RINT,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7796_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
+ DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
+ DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
+ DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
+ DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
+
+ DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a7796_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
+ DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
+ DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
+ DEF_MOD("cmt3", 300, R8A7796_CLK_R),
+ DEF_MOD("cmt2", 301, R8A7796_CLK_R),
+ DEF_MOD("cmt1", 302, R8A7796_CLK_R),
+ DEF_MOD("cmt0", 303, R8A7796_CLK_R),
+ DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
+ DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
+ DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
+ DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
+ DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
+ DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
+ DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
+ DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
+ DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A7796_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
+ DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
+ DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
+ DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
+ DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
+ DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
+ DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
+ DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
+ DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
+ DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
+ DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
+ DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
+ DEF_MOD("thermal", 522, R8A7796_CLK_CP),
+ DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
+ DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
+ DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
+ DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
+ DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
+ DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
+ DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
+ DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
+ DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
+ DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
+ DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
+ DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
+ DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
+ DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
+ DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
+ DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
+ DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
+ DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
+ DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
+ DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
+ DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
+ DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
+ DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
+ DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
+ DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
+ DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
+ DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
+ DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
+ * 14 13 19 17 (MHz)
+ *-------------------------------------------------------------------
+ * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
+ * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
+ * 0 0 1 0 Prohibited setting
+ * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
+ * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
+ * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
+ * 0 1 1 0 Prohibited setting
+ * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
+ * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
+ * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
+ * 1 0 1 0 Prohibited setting
+ * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
+ * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
+ * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
+ * 1 1 1 0 Prohibited setting
+ * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
+ (((md) & BIT(13)) >> 11) | \
+ (((md) & BIT(19)) >> 18) | \
+ (((md) & BIT(17)) >> 17))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 192, 1, 192, 1, },
+ { 1, 192, 1, 128, 1, },
+ { 0, /* Prohibited setting */ },
+ { 1, 192, 1, 192, 1, },
+ { 1, 160, 1, 160, 1, },
+ { 1, 160, 1, 106, 1, },
+ { 0, /* Prohibited setting */ },
+ { 1, 160, 1, 160, 1, },
+ { 1, 128, 1, 128, 1, },
+ { 1, 128, 1, 84, 1, },
+ { 0, /* Prohibited setting */ },
+ { 1, 128, 1, 128, 1, },
+ { 2, 192, 1, 192, 1, },
+ { 2, 192, 1, 128, 1, },
+ { 0, /* Prohibited setting */ },
+ { 2, 192, 1, 192, 1, },
+};
+
+static const struct mstp_stop_table r8a7796_mstp_table[] = {
+ { 0x00200000, 0x0, 0x00200000, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
+ { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
+ { 0x80000184, 0x180, 0x80000184, 0 },
+ { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
+ { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+ { 0x000000B7, 0x0, 0x000000B7, 0 },
+};
+
+static const void *r8a7796_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
+ .core_clk = r8a7796_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
+ .mod_clk = r8a7796_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
+ .mstp_table = r8a7796_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
+ .reset_node = "renesas,r8a7796-rst",
+ .extalr_node = "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a7796_get_pll_config,
+};
+
+static const struct udevice_id r8a7796_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7796-cpg-mssr",
+ .data = (ulong)&r8a7796_cpg_mssr_info,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7796) = {
+ .name = "clk_r8a7796",
+ .id = UCLASS_CLK,
+ .of_match = r8a7796_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A77970 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_PLL0D2,
+ CLK_PLL0D3,
+ CLK_PLL0D5,
+ CLK_PLL1D2,
+ CLK_PE,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_SSPSRC,
+ CLK_RINT,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77970_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
+ DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
+
+ DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+ DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
+ DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
+ DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
+ DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
+ DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("thermal", 522, R8A77970_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
+ DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
+ DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
+ DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
+ DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
+ DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
+ DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
+ DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
+ DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
+ DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
+ DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
+ DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz)
+ *-------------------------------------------------
+ * 0 0 0 16.66 x 1 x192 x192 x96
+ * 0 0 1 16.66 x 1 x192 x192 x80
+ * 0 1 0 20 x 1 x160 x160 x80
+ * 0 1 1 20 x 1 x160 x160 x66
+ * 1 0 0 27 / 2 x236 x236 x118
+ * 1 0 1 27 / 2 x236 x236 x98
+ * 1 1 0 33.33 / 2 x192 x192 x96
+ * 1 1 1 33.33 / 2 x192 x192 x80
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 192, 1, 96, 1, },
+ { 1, 192, 1, 80, 1, },
+ { 1, 160, 1, 80, 1, },
+ { 1, 160, 1, 66, 1, },
+ { 2, 236, 1, 118, 1, },
+ { 2, 236, 1, 98, 1, },
+ { 2, 192, 1, 96, 1, },
+ { 2, 192, 1, 80, 1, },
+};
+
+static const struct mstp_stop_table r8a77970_mstp_table[] = {
+ { 0x00230000, 0x0, 0x00230000, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x14062FD8, 0x2040, 0x14062FD8, 0 },
+ { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
+ { 0x80000184, 0x180, 0x80000184, 0 },
+ { 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
+ { 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+ { 0x000000B7, 0x0, 0x000000B7, 0 },
+};
+
+static const void *r8a77970_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
+ .core_clk = r8a77970_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
+ .mod_clk = r8a77970_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
+ .mstp_table = r8a77970_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
+ .reset_node = "renesas,r8a77970-rst",
+ .extalr_node = "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a77970_get_pll_config,
+};
+
+static const struct udevice_id r8a77970_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a77970-cpg-mssr",
+ .data = (ulong)&r8a77970_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a77970) = {
+ .name = "clk_r8a77970",
+ .id = UCLASS_CLK,
+ .of_match = r8a77970_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A77995 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77995_CLK_CP,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL0D2,
+ CLK_PLL0D3,
+ CLK_PLL0D5,
+ CLK_PLL1D2,
+ CLK_PE,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_SSPSRC,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77995_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
+ DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
+ DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
+ DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
+ DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
+ DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
+ DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
+
+ DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
+ DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+ DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+ DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
+};
+
+static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
+ DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
+ DEF_MOD("cmt3", 300, R8A77995_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77995_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77995_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77995_CLK_R),
+ DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
+ DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
+ DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A77995_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
+ DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
+ DEF_MOD("thermal", 522, R8A77995_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
+ DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
+ DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
+ DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
+ DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
+ DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
+ DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
+ DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
+ DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
+ DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
+ DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
+ DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
+ *--------------------------------------------------------------------
+ * 0 48 x 1 x250/4 x100/3 x100/3
+ * 1 48 x 1 x250/4 x100/3 x116/6
+ */
+#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 100, 3, 100, 3, },
+ { 1, 100, 3, 116, 6, },
+};
+
+static const struct mstp_stop_table r8a77995_mstp_table[] = {
+ { 0x00200000, 0x0, 0x00200000, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
+ { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
+ { 0x80000184, 0x180, 0x80000184, 0 },
+ { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
+ { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+ { 0x000000B7, 0x0, 0x000000B7, 0 },
+};
+
+static const void *r8a77995_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
+ .core_clk = r8a77995_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
+ .mod_clk = r8a77995_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
+ .mstp_table = r8a77995_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
+ .reset_node = "renesas,r8a77995-rst",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = ~0,
+ .get_pll_config = r8a77995_get_pll_config,
+};
+
+static const struct udevice_id r8a77995_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a77995-cpg-mssr",
+ .data = (ulong)&r8a77995_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a77995) = {
+ .name = "clk_r8a77995",
+ .id = UCLASS_CLK,
+ .of_match = r8a77995_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * R-Car Gen2 Clock Pulse Generator
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
+#define __CLK_RENESAS_RCAR_GEN2_CPG_H__
+
+enum rcar_gen2_clk_types {
+ CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
+ CLK_TYPE_GEN2_PLL0,
+ CLK_TYPE_GEN2_PLL1,
+ CLK_TYPE_GEN2_PLL3,
+ CLK_TYPE_GEN2_Z,
+ CLK_TYPE_GEN2_LB,
+ CLK_TYPE_GEN2_ADSP,
+ CLK_TYPE_GEN2_SDH,
+ CLK_TYPE_GEN2_SD0,
+ CLK_TYPE_GEN2_SD1,
+ CLK_TYPE_GEN2_QSPI,
+ CLK_TYPE_GEN2_RCAN,
+};
+
+struct rcar_gen2_cpg_pll_config {
+ unsigned int extal_div;
+ unsigned int pll1_mult;
+ unsigned int pll3_mult;
+ unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
+};
+
+struct gen2_clk_priv {
+ void __iomem *base;
+ struct cpg_mssr_info *info;
+ struct clk clk_extal;
+ struct clk clk_extal_usb;
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+};
+
+int gen2_clk_probe(struct udevice *dev);
+int gen2_clk_remove(struct udevice *dev);
+
+extern const struct clk_ops gen2_clk_ops;
+
+#endif
--- /dev/null
+/*
+ * R-Car Gen3 Clock Pulse Generator
+ *
+ * Copyright (C) 2015-2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
+#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
+
+enum rcar_gen3_clk_types {
+ CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
+ CLK_TYPE_GEN3_PLL0,
+ CLK_TYPE_GEN3_PLL1,
+ CLK_TYPE_GEN3_PLL2,
+ CLK_TYPE_GEN3_PLL3,
+ CLK_TYPE_GEN3_PLL4,
+ CLK_TYPE_GEN3_SD,
+ CLK_TYPE_GEN3_RPC,
+ CLK_TYPE_GEN3_R,
+ CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_Z2,
+};
+
+#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+ _div_clean) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, \
+ (_parent_clean), .div = (_div_clean), 1)
+
+struct rcar_gen3_cpg_pll_config {
+ u8 extal_div;
+ u8 pll1_mult;
+ u8 pll1_div;
+ u8 pll3_mult;
+ u8 pll3_div;
+};
+
+#define CPG_RCKCR 0x240
+
+struct gen3_clk_priv {
+ void __iomem *base;
+ struct cpg_mssr_info *info;
+ struct clk clk_extal;
+ struct clk clk_extalr;
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+};
+
+int gen3_clk_probe(struct udevice *dev);
+int gen3_clk_remove(struct udevice *dev);
+
+extern const struct clk_ops gen3_clk_ops;
+
+#endif
--- /dev/null
+/*
+ * Renesas RCar Gen3 CPG MSSR driver
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+
+/*
+ * Module Standby and Software Reset register offets.
+ *
+ * If the registers exist, these are valid for SH-Mobile, R-Mobile,
+ * R-Car Gen2, R-Car Gen3, and RZ/G1.
+ * These are NOT valid for R-Car Gen1 and RZ/A1!
+ */
+
+/*
+ * Module Stop Status Register offsets
+ */
+
+static const u16 mstpsr[] = {
+ 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
+ 0x9A0, 0x9A4, 0x9A8, 0x9AC,
+};
+
+#define MSTPSR(i) mstpsr[i]
+
+
+/*
+ * System Module Stop Control Register offsets
+ */
+
+static const u16 smstpcr[] = {
+ 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
+ 0x990, 0x994, 0x998, 0x99C,
+};
+
+#define SMSTPCR(i) smstpcr[i]
+
+
+/* Realtime Module Stop Control Register offsets */
+#define RMSTPCR(i) (smstpcr[i] - 0x20)
+
+/* Modem Module Stop Control Register offsets (r8a73a4) */
+#define MMSTPCR(i) (smstpcr[i] + 0x20)
+
+/* Software Reset Clearing Register offsets */
+#define SRSTCLR(i) (0x940 + (i) * 4)
+
+bool renesas_clk_is_mod(struct clk *clk)
+{
+ return (clk->id >> 16) == CPG_MOD;
+}
+
+int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
+ const struct mssr_mod_clk **mssr)
+{
+ const unsigned long clkid = clk->id & 0xffff;
+ int i;
+
+ for (i = 0; i < info->mod_clk_size; i++) {
+ if (info->mod_clk[i].id !=
+ (info->mod_clk_base + MOD_CLK_PACK(clkid)))
+ continue;
+
+ *mssr = &info->mod_clk[i];
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
+ const struct cpg_core_clk **core)
+{
+ const unsigned long clkid = clk->id & 0xffff;
+ int i;
+
+ for (i = 0; i < info->core_clk_size; i++) {
+ if (info->core_clk[i].id != clkid)
+ continue;
+
+ *core = &info->core_clk[i];
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
+ struct clk *parent)
+{
+ const struct cpg_core_clk *core;
+ const struct mssr_mod_clk *mssr;
+ int ret;
+
+ if (renesas_clk_is_mod(clk)) {
+ ret = renesas_clk_get_mod(clk, info, &mssr);
+ if (ret)
+ return ret;
+
+ parent->id = mssr->parent;
+ } else {
+ ret = renesas_clk_get_core(clk, info, &core);
+ if (ret)
+ return ret;
+
+ if (core->type == CLK_TYPE_IN)
+ parent->id = ~0; /* Top-level clock */
+ else
+ parent->id = core->parent;
+ }
+
+ parent->dev = clk->dev;
+
+ return 0;
+}
+
+int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
+{
+ const unsigned long clkid = clk->id & 0xffff;
+ const unsigned int reg = clkid / 100;
+ const unsigned int bit = clkid % 100;
+ const u32 bitmask = BIT(bit);
+
+ if (!renesas_clk_is_mod(clk))
+ return -EINVAL;
+
+ debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
+ clkid, reg, bit, enable ? "ON" : "OFF");
+
+ if (enable) {
+ clrbits_le32(base + SMSTPCR(reg), bitmask);
+ return wait_for_bit_le32(base + MSTPSR(reg),
+ bitmask, 0, 100, 0);
+ } else {
+ setbits_le32(base + SMSTPCR(reg), bitmask);
+ return 0;
+ }
+}
+
+int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
+{
+ unsigned int i;
+
+ /* Stop TMU0 */
+ clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
+
+ /* Stop module clock */
+ for (i = 0; i < info->mstp_table_size; i++) {
+ clrsetbits_le32(base + SMSTPCR(i),
+ info->mstp_table[i].sdis,
+ info->mstp_table[i].sen);
+ clrsetbits_le32(base + RMSTPCR(i),
+ info->mstp_table[i].rdis,
+ info->mstp_table[i].ren);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Renesas RCar Gen3 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
+#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
+
+struct cpg_mssr_info {
+ const struct cpg_core_clk *core_clk;
+ unsigned int core_clk_size;
+ const struct mssr_mod_clk *mod_clk;
+ unsigned int mod_clk_size;
+ const struct mstp_stop_table *mstp_table;
+ unsigned int mstp_table_size;
+ const char *reset_node;
+ const char *extalr_node;
+ const char *extal_usb_node;
+ unsigned int mod_clk_base;
+ unsigned int clk_extal_id;
+ unsigned int clk_extalr_id;
+ unsigned int clk_extal_usb_id;
+ unsigned int pll0_div;
+ const void *(*get_pll_config)(const u32 cpg_mode);
+};
+
+/*
+ * Definitions of CPG Core Clocks
+ *
+ * These include:
+ * - Clock outputs exported to DT
+ * - External input clocks
+ * - Internal CPG clocks
+ */
+struct cpg_core_clk {
+ /* Common */
+ const char *name;
+ unsigned int id;
+ unsigned int type;
+ /* Depending on type */
+ unsigned int parent; /* Core Clocks only */
+ unsigned int div;
+ unsigned int mult;
+ unsigned int offset;
+};
+
+enum clk_types {
+ /* Generic */
+ CLK_TYPE_IN, /* External Clock Input */
+ CLK_TYPE_FF, /* Fixed Factor Clock */
+ CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
+ CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
+
+ /* Custom definitions start here */
+ CLK_TYPE_CUSTOM,
+};
+
+#define DEF_TYPE(_name, _id, _type...) \
+ { .name = _name, .id = _id, .type = _type }
+#define DEF_BASE(_name, _id, _type, _parent...) \
+ DEF_TYPE(_name, _id, _type, .parent = _parent)
+
+#define DEF_INPUT(_name, _id) \
+ DEF_TYPE(_name, _id, CLK_TYPE_IN)
+#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+#define DEF_DIV6P1(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
+#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
+ DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
+
+/*
+ * Definitions of Module Clocks
+ */
+struct mssr_mod_clk {
+ const char *name;
+ unsigned int id;
+ unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
+};
+
+/* Convert from sparse base-100 to packed index space */
+#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
+
+#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
+
+#define DEF_MOD(_name, _mod, _parent...) \
+ { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
+
+struct mstp_stop_table {
+ u32 sdis;
+ u32 sen;
+ u32 rdis;
+ u32 ren;
+};
+
+#define TSTR0 0x04
+#define TSTR0_STR0 BIT(0)
+
+bool renesas_clk_is_mod(struct clk *clk);
+int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
+ const struct mssr_mod_clk **mssr);
+int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
+ const struct cpg_core_clk **core);
+int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
+ struct clk *parent);
+int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
+int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
+
+#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
return DIV_TO_RATE(src_rate, div) / 2;
}
+static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
+{
+ ulong ret;
+
+ /*
+ * The gmac clock can be derived either from an external clock
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
+ /* An external clock will always generate the right rate... */
+ ret = freq;
+ } else {
+ u32 con = readl(&cru->cru_clksel_con[5]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
+ pll_rate = GPLL_HZ;
+ else
+ /* CPLL is not set */
+ return -EPERM;
+
+ div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
+ div << CLK_MAC_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
+}
+
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
int periph, uint freq)
{
case CLK_DDR:
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
break;
+ case SCLK_MAC:
+ new_rate = rk322x_mac_set_clk(priv->cru, rate);
+ break;
+ case PLL_GPLL:
+ return 0;
default:
return -ENOENT;
}
return new_rate;
}
+static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk322x_cru *cru = priv->cru;
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
+ debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
+ return 0;
+ }
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
+ debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ struct rk322x_cru *cru = priv->cru;
+ int ret;
+
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ if (!strcmp(clock_output_name, "ext_gmac")) {
+ debug("%s: switching gmac extclk to ext_gmac\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
+ return 0;
+ } else if (!strcmp(clock_output_name, "phy_50m_out")) {
+ debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC:
+ return rk322x_gmac_set_parent(clk, parent);
+ case SCLK_MAC_EXTCLK:
+ return rk322x_gmac_extclk_set_parent(clk, parent);
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk322x_clk_ops = {
.get_rate = rk322x_clk_get_rate,
.set_rate = rk322x_clk_set_rate,
+ .set_parent = rk322x_clk_set_parent,
};
static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
return 0;
}
-static int rockchip_mac_set_clk(struct rk3288_cru *cru,
- int periph, uint freq)
+static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
{
- /* Assuming mac_clk is fed by an external clock */
- rk_clrsetreg(&cru->cru_clksel_con[21],
- RMII_EXTCLK_MASK,
- RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+ ulong ret;
+
+ /*
+ * The gmac clock can be derived either from an external clock
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
+ /* An external clock will always generate the right rate... */
+ ret = freq;
+ } else {
+ u32 con = readl(&cru->cru_clksel_con[21]);
+ ulong pll_rate;
+ u8 div;
+
+ if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+ EMAC_PLL_SELECT_GENERAL)
+ pll_rate = GPLL_HZ;
+ else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+ EMAC_PLL_SELECT_CODEC)
+ pll_rate = CPLL_HZ;
+ else
+ pll_rate = NPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
+ div << MAC_DIV_CON_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
- return 0;
+ return ret;
}
static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
break;
#ifndef CONFIG_SPL_BUILD
case SCLK_MAC:
- new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
+ new_rate = rockchip_mac_set_clk(priv->cru, rate);
break;
case DCLK_VOP0:
case DCLK_VOP1:
case SCLK_SARADC:
new_rate = rockchip_saradc_set_clk(priv->cru, rate);
break;
+ case PLL_GPLL:
+ case PLL_CPLL:
+ case PLL_NPLL:
+ case ACLK_CPU:
+ case HCLK_CPU:
+ case PCLK_CPU:
+ case ACLK_PERI:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ case SCLK_UART0:
+ return 0;
default:
return -ENOENT;
}
return new_rate;
}
+static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3288_cru *cru = priv->cru;
+ const char *clock_output_name;
+ int ret;
+
+ /*
+ * If the requested parent is in the same clock-controller and
+ * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
+ * clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
+ debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "ext_gmac".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "ext_gmac", switch to the external clock input */
+ if (!strcmp(clock_output_name, "ext_gmac")) {
+ debug("%s: switching GMAC to external clock\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
+ RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC:
+ return rk3288_gmac_set_parent(clk, parent);
+ case SCLK_USBPHY480M_SRC:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk3288_clk_ops = {
.get_rate = rk3288_clk_get_rate,
.set_rate = rk3288_clk_set_rate,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .set_parent = rk3288_clk_set_parent,
+#endif
};
static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3328.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3328.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
PCLK_DBG_DIV_SHIFT = 0,
PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
+ /* CLKSEL_CON27 */
+ GMAC2IO_PLL_SEL_SHIFT = 7,
+ GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
+ GMAC2IO_PLL_SEL_CPLL = 0,
+ GMAC2IO_PLL_SEL_GPLL = 1,
+ GMAC2IO_CLK_DIV_MASK = 0x1f,
+ GMAC2IO_CLK_DIV_SHIFT = 0,
+
/* CLKSEL_CON28 */
ACLK_PERIHP_PLL_SEL_CPLL = 0,
ACLK_PERIHP_PLL_SEL_GPLL,
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
}
+static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
+{
+ struct rk3328_grf_regs *grf;
+ ulong ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * The RGMII CLK can be derived either from an external "clkin"
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&grf->mac_con[1]) & BIT(10) &&
+ readl(&grf->soc_con[4]) & BIT(14)) {
+ /* An external clock will always generate the right rate... */
+ ret = rate;
+ } else {
+ u32 con = readl(&cru->clksel_con[27]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
+ pll_rate = GPLL_HZ;
+ else
+ pll_rate = CPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, rate) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
+ div << GMAC2IO_CLK_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
+}
+
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
{
u32 div, con, con_id;
case SCLK_I2C3:
ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
break;
+ case SCLK_MAC2IO:
+ ret = rk3328_gmac2io_set_clk(priv->cru, rate);
+ break;
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
case SCLK_SARADC:
ret = rk3328_saradc_set_clk(priv->cru, rate);
break;
+ case DCLK_LCDC:
+ case SCLK_PDM:
+ case SCLK_RTC32K:
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_SDIO:
+ case SCLK_TSP:
+ case SCLK_WIFI:
+ case ACLK_BUS_PRE:
+ case HCLK_BUS_PRE:
+ case PCLK_BUS_PRE:
+ case ACLK_PERI_PRE:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ case ACLK_VIO_PRE:
+ case HCLK_VIO_PRE:
+ case ACLK_RGA_PRE:
+ case SCLK_RGA:
+ case ACLK_VOP_PRE:
+ case ACLK_RKVDEC_PRE:
+ case ACLK_RKVENC:
+ case ACLK_VPU_PRE:
+ case SCLK_VDEC_CABAC:
+ case SCLK_VDEC_CORE:
+ case SCLK_VENC_CORE:
+ case SCLK_VENC_DSP:
+ case SCLK_EFUSE:
+ case PCLK_DDR:
+ case ACLK_GMAC:
+ case PCLK_GMAC:
+ case SCLK_USB3OTG_SUSPEND:
+ return 0;
default:
return -ENOENT;
}
return ret;
}
+static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3328_grf_regs *grf;
+ const char *clock_output_name;
+ int ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
+ debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
+ rk_clrreg(&grf->mac_con[1], BIT(10));
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "gmac_clkin".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "gmac_clkin", switch to the external clock input */
+ if (!strcmp(clock_output_name, "gmac_clkin")) {
+ debug("%s: switching RGMII to CLKIN\n", __func__);
+ rk_setreg(&grf->mac_con[1], BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3328_grf_regs *grf;
+ const char *clock_output_name;
+ int ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
+ debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
+ rk_clrreg(&grf->soc_con[4], BIT(14));
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "gmac_clkin".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "gmac_clkin", switch to the external clock input */
+ if (!strcmp(clock_output_name, "gmac_clkin")) {
+ debug("%s: switching RGMII to CLKIN\n", __func__);
+ rk_setreg(&grf->soc_con[4], BIT(14));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC2IO:
+ return rk3328_gmac2io_set_parent(clk, parent);
+ case SCLK_MAC2IO_EXT:
+ return rk3328_gmac2io_ext_set_parent(clk, parent);
+ case DCLK_LCDC:
+ case SCLK_PDM:
+ case SCLK_RTC32K:
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk3328_clk_ops = {
.get_rate = rk3328_clk_get_rate,
.set_rate = rk3328_clk_set_rate,
+ .set_parent = rk3328_clk_set_parent,
};
static int rk3328_clk_probe(struct udevice *dev)
#endif
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
- ulong clk_id, ulong set_rate)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
{
+ ulong ret;
+
/*
- * This models the 'assigned-clock-parents = <&ext_gmac>' from
- * the DTS and switches to the 'ext_gmac' clock parent.
+ * The gmac clock can be derived either from an external clock
+ * or can be generated from internally by a divider from SCLK_MAC.
*/
- rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
- return set_rate;
+ if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
+ /* An external clock will always generate the right rate... */
+ ret = set_rate;
+ } else {
+ u32 con = readl(&cru->clksel_con[43]);
+ ulong pll_rate;
+ u8 div;
+
+ if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+ GMAC_PLL_SELECT_GENERAL)
+ pll_rate = GPLL_HZ;
+ else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+ GMAC_PLL_SELECT_CODEC)
+ pll_rate = CPLL_HZ;
+ else
+ /* CPLL is not set */
+ return -EPERM;
+
+ div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
+ div << GMAC_DIV_CON_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
}
#endif
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case SCLK_MAC:
/* select the external clock */
- ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
+ ret = rk3368_gmac_set_clk(priv->cru, rate);
break;
#endif
case SCLK_SARADC:
return ret;
}
+static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3368_cru *cru = priv->cru;
+ const char *clock_output_name;
+ int ret;
+
+ /*
+ * If the requested parent is in the same clock-controller and
+ * the id is SCLK_MAC ("sclk_mac"), switch to the internal
+ * clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+ debug("%s: switching GAMC to SCLK_MAC\n", __func__);
+ rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "ext_gmac".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "ext_gmac", switch to the external clock input */
+ if (!strcmp(clock_output_name, "ext_gmac")) {
+ debug("%s: switching GMAC to external clock\n", __func__);
+ rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC:
+ return rk3368_gmac_set_parent(clk, parent);
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk3368_clk_ops = {
.get_rate = rk3368_clk_get_rate,
.set_rate = rk3368_clk_set_rate,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .set_parent = rk3368_clk_set_parent,
+#endif
};
static int rk3368_clk_probe(struct udevice *dev)
return rk3399_mmc_get_clk(cru, clk_id);
}
+static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
+{
+ ulong ret;
+
+ /*
+ * The RGMII CLK can be derived either from an external "clkin"
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&cru->clksel_con[19]) & BIT(4)) {
+ /* An external clock will always generate the right rate... */
+ ret = rate;
+ } else {
+ /*
+ * No platform uses an internal clock to date.
+ * Implement this once it becomes necessary and print an error
+ * if someone tries to use it (while it remains unimplemented).
+ */
+ pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
+ ret = 0;
+ }
+
+ return ret;
+}
+
#define PMUSGRF_DDR_RGN_CON16 0xff330040
static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
ulong set_rate)
switch (clk->id) {
case 0 ... 63:
return 0;
+
+ case ACLK_PERIHP:
+ case HCLK_PERIHP:
+ case PCLK_PERIHP:
+ return 0;
+
+ case ACLK_PERILP0:
+ case HCLK_PERILP0:
+ case PCLK_PERILP0:
+ return 0;
+
+ case ACLK_CCI:
+ return 0;
+
+ case HCLK_PERILP1:
+ case PCLK_PERILP1:
+ return 0;
+
case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_MAC:
- /* nothing to do, as this is an external clock */
- ret = rate;
+ ret = rk3399_gmac_set_clk(priv->cru, rate);
break;
case SCLK_I2C1:
case SCLK_I2C2:
return ret;
}
+static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ int ret;
+
+ /*
+ * If the requested parent is in the same clock-controller and
+ * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+ debug("%s: switching RGMII to SCLK_MAC\n", __func__);
+ rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "clkin_gmac".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "clkin_gmac", switch to the external clock input */
+ if (!strcmp(clock_output_name, "clkin_gmac")) {
+ debug("%s: switching RGMII to CLKIN\n", __func__);
+ rk_setreg(&priv->cru->clksel_con[19], BIT(4));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_RMII_SRC:
+ return rk3399_gmac_set_parent(clk, parent);
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static int rk3399_clk_enable(struct clk *clk)
{
switch (clk->id) {
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .set_parent = rk3399_clk_set_parent,
+#endif
.enable = rk3399_clk_enable,
};
#include <common.h>
#include <asm/io.h>
+#include <clk.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <malloc.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/of_access.h>
#include <dm/pinctrl.h>
#include <dm/platdata.h>
#include <dm/read.h>
goto fail;
}
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev);
+ if (ret)
+ goto fail;
+
if (drv->probe) {
ret = drv->probe(dev);
if (ret) {
bool device_is_compatible(struct udevice *dev, const char *compat)
{
const void *fdt = gd->fdt_blob;
+ ofnode node = dev_ofnode(dev);
- return !fdt_node_check_compatible(fdt, dev_of_offset(dev), compat);
+ if (ofnode_is_np(node))
+ return of_device_is_compatible(ofnode_to_np(node), compat, NULL, NULL);
+ else
+ return !fdt_node_check_compatible(fdt, ofnode_to_offset(node), compat);
}
bool of_machine_is_compatible(const char *compat)
&flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
- na = of_n_addr_cells(ofnode_to_np(node));
- return of_read_number(prop_val, na);
+
+ if (IS_ENABLED(CONFIG_OF_TRANSLATE)) {
+ return of_translate_address(ofnode_to_np(node), prop_val);
+ } else {
+ na = of_n_addr_cells(ofnode_to_np(node));
+ return of_read_number(prop_val, na);
+ }
} else {
return fdt_get_base_address(gd->fdt_blob,
ofnode_to_offset(node));
int ret;
ret = of_parse_phandle_with_args(ofnode_to_np(node),
- list_name, cells_name, index, &args);
+ list_name, cells_name, index,
+ &args);
if (ret)
return ret;
ofnode_from_of_phandle_args(&args, out_args);
int ret;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
- ofnode_to_offset(node), list_name, cells_name,
- cell_count, index, &args);
+ ofnode_to_offset(node),
+ list_name, cells_name,
+ cell_count, index, &args);
if (ret)
return ret;
ofnode_from_fdtdec_phandle_args(&args, out_args);
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[1]);
break;
- } else {
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
}
+
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
}
if (i == num) {
}
return 0;
- } else {
- ret = -EINVAL;
}
+ ret = -EINVAL;
+
fail:
debug("(not found)\n");
return ret;
return ofnode_read_resource(node, index, res);
}
+
+u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr)
+{
+ if (ofnode_is_np(node))
+ return of_translate_address(ofnode_to_np(node), in_addr);
+ else
+ return fdt_translate_address(gd->fdt_blob, ofnode_to_offset(node), in_addr);
+}
#include <mapmem.h>
#include <dm/of_access.h>
+int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp)
+{
+ return ofnode_read_u32(dev_ofnode(dev), propname, outp);
+}
+
int dev_read_u32_default(struct udevice *dev, const char *propname, int def)
{
return ofnode_read_u32_default(dev_ofnode(dev), propname, def);
}
fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *property,
- fdt_size_t *sizep)
+ fdt_size_t *sizep)
{
return ofnode_get_addr_size(dev_ofnode(dev), property, sizep);
}
}
int dev_read_stringlist_search(struct udevice *dev, const char *property,
- const char *string)
+ const char *string)
{
return ofnode_stringlist_search(dev_ofnode(dev), property, string);
}
}
int dev_read_phandle_with_args(struct udevice *dev, const char *list_name,
- const char *cells_name, int cell_count,
- int index,
- struct ofnode_phandle_args *out_args)
+ const char *cells_name, int cell_count,
+ int index, struct ofnode_phandle_args *out_args)
{
return ofnode_parse_phandle_with_args(dev_ofnode(dev), list_name,
cells_name, cell_count, index,
{
return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
}
+
+u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_address(dev_ofnode(dev), in_addr);
+}
#define REG_BCM6328_OTP 0x62c
#define BCM6328_TP1_DISABLED BIT(9)
+#define REG_BCM6318_STRAP_OVRDBUS 0x900
+#define OVRDBUS_6318_FREQ_SHIFT 23
+#define OVRDBUS_6318_FREQ_MASK (0x3 << OVRDBUS_6318_FREQ_SHIFT)
+
#define REG_BCM6328_MISC_STRAPBUS 0x1a40
#define STRAPBUS_6328_FCVO_SHIFT 7
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
#define DMIPSPLLCFG_6358_N2_SHIFT 29
#define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
+#define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0
+#define DMIPSPLLCFG_6368_P1_SHIFT 0
+#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT 4
+#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
+#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+#define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4
+#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
+#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
#define REG_BCM63268_MISC_STRAPBUS 0x1814
#define STRAPBUS_63268_FCVO_SHIFT 21
#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
return 333000000;
}
+static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int mips_pll_fcvo;
+
+ mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
+ mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
+ >> OVRDBUS_6318_FREQ_SHIFT;
+
+ switch (mips_pll_fcvo) {
+ case 0:
+ return 166000000;
+ case 1:
+ return 400000000;
+ case 2:
+ return 250000000;
+ case 3:
+ return 333000000;
+ default:
+ return 0;
+ }
+}
+
static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
{
unsigned int mips_pll_fcvo;
return (16 * 1000000 * n1 * n2) / m1;
}
+static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int tmp, p1, p2, ndiv, m1;
+
+ tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
+ p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
+ p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
+ ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
+ DMIPSPLLCFG_6368_NDIV_SHIFT;
+
+ tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
+ m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
+
+ return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+}
+
static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
{
unsigned int mips_pll_fcvo;
.get_cpu_count = bcm6358_get_cpu_count,
};
+static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
+ .get_cpu_desc = bmips_short_cpu_desc,
+ .get_cpu_freq = bcm6318_get_cpu_freq,
+ .get_cpu_count = bcm6345_get_cpu_count,
+};
+
static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
.get_cpu_desc = bmips_long_cpu_desc,
.get_cpu_freq = bcm6328_get_cpu_freq,
.get_cpu_count = bcm6358_get_cpu_count,
};
+static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
+ .get_cpu_desc = bmips_short_cpu_desc,
+ .get_cpu_freq = bcm6368_get_cpu_freq,
+ .get_cpu_count = bcm6358_get_cpu_count,
+};
+
static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
.get_cpu_desc = bmips_long_cpu_desc,
.get_cpu_freq = bcm63268_get_cpu_freq,
.compatible = "brcm,bcm3380-cpu",
.data = (ulong)&bmips_cpu_bcm3380,
}, {
+ .compatible = "brcm,bcm6318-cpu",
+ .data = (ulong)&bmips_cpu_bcm6318,
+ }, {
.compatible = "brcm,bcm6328-cpu",
.data = (ulong)&bmips_cpu_bcm6328,
}, {
.compatible = "brcm,bcm6358-cpu",
.data = (ulong)&bmips_cpu_bcm6358,
}, {
+ .compatible = "brcm,bcm6368-cpu",
+ .data = (ulong)&bmips_cpu_bcm6368,
+ }, {
.compatible = "brcm,bcm63268-cpu",
.data = (ulong)&bmips_cpu_bcm63268,
},
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
{
int ret = 0;
uint32_t *desc;
+ unsigned int size;
- desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+ desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
if (!desc) {
debug("Not enough memory for descriptor allocation\n");
return -ENOMEM;
}
+ if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
+ !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
+ puts("Error: Address arguments are not aligned\n");
+ return -EINVAL;
+ }
+
+ size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
+
inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
driver_hash[algo].alg_type,
driver_hash[algo].digestsize,
0);
+ size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+
ret = run_descriptor_jr(desc);
+ size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range((unsigned long)pout,
+ (unsigned long)pout + size);
+
free(desc);
return ret;
}
u32 debug_info;
if (pass) {
- printf("%s: CALIBRATION PASSED\n", __FILE__);
+ debug("%s: CALIBRATION PASSED\n", __FILE__);
gbl->fom_in /= 2;
gbl->fom_out /= 2;
writel(debug_info, &phy_mgr_cfg->cal_debug_info);
writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else {
- printf("%s: CALIBRATION FAILED\n", __FILE__);
+ debug("%s: CALIBRATION FAILED\n", __FILE__);
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
writel(debug_info, &sdr_reg_file->failing_stage);
}
- printf("%s: Calibration complete\n", __FILE__);
+ debug("%s: Calibration complete\n", __FILE__);
}
/**
initialize_tracking();
- printf("%s: Preparing to start memory calibration\n", __FILE__);
+ debug("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
debug_cond(DLEVEL >= 1,
if (step == 2)
goto step2;
+ /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
+ ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+
if (regs->ddr_eor)
ddr_out32(&ddr->eor, regs->ddr_eor);
ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
- ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
extern u32 g_zpodt_ctrl;
extern u32 g_znodt_ctrl;
extern u32 g_dic;
-extern u32 g_odt_config;
+extern u32 g_odt_config_2cs;
+extern u32 g_odt_config_1cs;
extern u32 g_rtt_nom;
extern u8 debug_training_access;
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
- SPEED_BIN_TMOD
+ SPEED_BIN_TMOD,
+ SPEED_BIN_TXPDLL
};
#endif /* _DDR3_TOPOLOGY_DEF_H */
#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
+#define TIMES_9_TREFI_CYCLES 0x8
+
u32 window_mem_addr = 0;
u32 phy_reg0_val = 0;
u32 phy_reg1_val = 8;
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 data_read[MAX_INTERFACE_NUM];
struct hws_topology_map *tm = ddr3_get_topology_map();
+ u32 odt_config = g_odt_config_2cs;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("cl_value 0x%x cwl_val 0x%x\n",
cl_value, cwl_val));
-
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
data_value =
((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
(0x7 << 4) | (1 << 2)));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
- MR0_REG, twr_mask_table[t_wr + 1],
- 0xe00));
+ MR0_REG, twr_mask_table[t_wr + 1] << 9,
+ (0x7 << 9)));
+
/*
* MR1: Set RTT and DIC Design GL values
DUNIT_CONTROL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
+ /* calculate number of CS (per interface) */
+ CHECK_STATUS(calc_cs_num
+ (dev_num, if_id, &cs_num));
timing = tm->interface_params[if_id].timing;
if (mode2_t != 0xff) {
/* Board topology map is forcing timing */
t2t = (timing == HWS_TIM_2T) ? 1 : 0;
} else {
- /* calculate number of CS (per interface) */
- CHECK_STATUS(calc_cs_num
- (dev_num, if_id, &cs_num));
t2t = (cs_num == 1) ? 0 : 1;
}
DDR_CONTROL_LOW_REG, t2t << 3,
0x3 << 3));
/* move the block to ddr3_tip_set_timing - start */
- t_pd = GET_MAX_VALUE(t_ckclk * 3,
- speed_bin_table(speed_bin_index,
- SPEED_BIN_TPD));
- t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk);
- txpdll = GET_MAX_VALUE(t_ckclk * 10, 24);
+ t_pd = TIMES_9_TREFI_CYCLES;
+ txpdll = GET_MAX_VALUE(t_ckclk * 10,
+ speed_bin_table(speed_bin_index,
+ SPEED_BIN_TXPDLL));
txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk);
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
- DDR_TIMING_REG, txpdll << 4,
- 0x1f << 4));
+ DDR_TIMING_REG, txpdll << 4 | t_pd,
+ 0x1f << 4 | 0xf));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
(1 << 11)));
/* Set Active control for ODT write transactions */
+ if (cs_num == 1)
+ odt_config = g_odt_config_1cs;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
- PARAM_NOT_CARE, 0x1494, g_odt_config,
+ PARAM_NOT_CARE, 0x1494, odt_config,
MASK_ALL_BITS));
}
} else {
u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
bus_cnt = 0, t_hclk = 0, t_wr = 0,
refresh_interval_cnt = 0, cnt_id;
+ u32 t_ckclk;
u32 t_refi = 0, end_if, start_if;
u32 bus_index = 0;
int is_dll_off = 0;
/* adjust t_refi to new frequency */
t_refi = (tm->interface_params[if_id].interface_temp ==
- HWS_TEMP_HIGH) ? TREFI_LOW : TREFI_HIGH;
+ HWS_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
t_refi *= 1000; /*psec */
/* HCLK in[ps] */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id, DFS_REG,
(cwl_mask_table[cwl_value] << 12), 0x7000));
- t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR);
- t_wr = (t_wr / 1000);
+
+ t_ckclk = MEGA / freq_val[frequency];
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
+
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id, DFS_REG,
(twr_mask_table[t_wr + 1] << 16), 0x70000));
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_LOW,
val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_HI_REG,
val, 0xffff));
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_LOW, val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_HI_REG, val, 0xffff));
if (odt_additional == 1) {
10,
10,
10,
- 1, /*5 */
- 2, /*6 */
- 3, /*7 */
+ 1, /*5*/
+ 2, /*6*/
+ 3, /*7*/
+ 4, /*8*/
10,
+ 5, /*10*/
10,
- 5, /*10 */
+ 6, /*12*/
10,
- 6, /*12 */
+ 7, /*14*/
10,
- 7, /*14 */
- 10,
- 0 /*16 */
+ 0 /*16*/
};
u8 cl_mask_table[] = {
case SPEED_BIN_TMOD:
result = 15000;
break;
+ case SPEED_BIN_TXPDLL:
+ result = 24000;
+ break;
default:
break;
}
#define VREF_MAX_INDEX 7
#define MAX_VALUE (1024 - 1)
#define MIN_VALUE (-MAX_VALUE)
-#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
+#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ck_delay = (u32)-1, ck_delay_16 = (u32)-1;
u32 ca_delay;
*/
int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
{
- u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0;
+ u32 cs_num = 0, max_cs = 0, max_read_sample = 0, min_read_sample = 0x1f;
u32 data_read[MAX_INTERFACE_NUM] = { 0 };
u32 read_sample[MAX_CS_NUM];
u32 val;
data_read, MASK_ALL_BITS));
val = data_read[if_id];
- for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
+ max_cs = hws_ddr3_tip_max_cs_get();
+
+ for (cs_num = 0; cs_num < max_cs; cs_num++) {
read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
/* find maximum of read_samples */
if (read_sample[cs_num] >= max_read_sample) {
- if (read_sample[cs_num] == max_read_sample)
- max_phase = MIN_VALUE;
- else
+ if (read_sample[cs_num] == max_read_sample) {
+ /* search for max phase */;
+ } else {
max_read_sample = read_sample[cs_num];
+ max_phase = MIN_VALUE;
+ }
for (pup_index = 0;
pup_index < tm->num_of_bus_per_interface;
min_read_sample = read_sample[cs_num];
}
+ if (min_read_sample <= tm->interface_params[if_id].cas_l) {
+ min_read_sample = (int)tm->interface_params[if_id].cas_l;
+ }
+
min_read_sample = min_read_sample - 1;
max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
- if (min_read_sample >= 0xf)
- min_read_sample = 0xf;
if (max_read_sample >= 0x1f)
max_read_sample = 0x1f;
u32 g_znodt_data = 45; /* controller data - N ODT */
u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
u32 g_znodt_ctrl = 45; /* controller data - N ODT */
-u32 g_odt_config = 0x120012;
+u32 g_odt_config_2cs = 0x120012;
+u32 g_odt_config_1cs = 0x10000;
u32 g_rtt_nom = 0x44;
u32 g_dic = 0x2;
writel(SCL_START | SCL_EN, &ddr2_phy->scl_start);
/* Wait for SCL for data byte to pass */
- return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS,
- true, CONFIG_SYS_HZ, false);
+ return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS,
+ true, CONFIG_SYS_HZ, false);
}
/* DDR2 Controller initialization */
writel(INIT_START, &ctrl->memcon);
/* wait for all host cmds to be transmitted */
- wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false,
+ CONFIG_SYS_HZ, false);
/* inform all cmds issued, ready for normal operation */
writel(INIT_START | INIT_DONE, &ctrl->memcon);
config USB_FUNCTION_DFU
bool
+ select HASH
if CMD_DFU
config DFU_TFTP
#define EDMA3_QEESR 0x108c
#define EDMA3_QSECR 0x1094
+#define EDMA_FILL_BUFFER_SIZE 512
+
struct ti_edma3_priv {
u32 base;
};
+static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN);
+
/**
* qedma3_start - start qdma on a channel
* @base: base address of edma
}
void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, void *src, size_t len)
+ void *dst, void *src, size_t len, size_t s_len)
{
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
unsigned int addr = (unsigned int) (dst);
unsigned int max_acnt = 0x7FFFU;
- if (len > max_acnt) {
+ if (len > s_len) {
+ b_cnt_value = (len / s_len);
+ rem_bytes = (len % s_len);
+ a_cnt_value = s_len;
+ } else if (len > max_acnt) {
b_cnt_value = (len / max_acnt);
rem_bytes = (len % max_acnt);
a_cnt_value = max_acnt;
slot.acnt = a_cnt_value;
slot.bcnt = b_cnt_value;
slot.ccnt = 1;
- slot.src_bidx = a_cnt_value;
+ if (len == s_len)
+ slot.src_bidx = a_cnt_value;
+ else
+ slot.src_bidx = 0;
slot.dst_bidx = a_cnt_value;
slot.src_cidx = 0;
slot.dst_cidx = 0;
if (rem_bytes != 0) {
slot.opt = 0;
- slot.src =
- (b_cnt_value * max_acnt) + ((unsigned int) src);
+ if (len == s_len)
+ slot.src =
+ (b_cnt_value * max_acnt) + ((unsigned int) src);
+ else
+ slot.src = (unsigned int) src;
slot.acnt = rem_bytes;
slot.bcnt = 1;
slot.ccnt = 1;
}
}
+void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len)
+{
+ int xfer_len;
+ int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535;
+
+ memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer));
+
+ while (len) {
+ xfer_len = len;
+ if (xfer_len > max_xfer)
+ xfer_len = max_xfer;
+
+ __edma3_transfer(edma3_base_addr, edma_slot_num, dst,
+ edma_fill_buffer, xfer_len,
+ EDMA_FILL_BUFFER_SIZE);
+ len -= xfer_len;
+ dst += xfer_len;
+ }
+}
+
#ifndef CONFIG_DMA
void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, void *src, size_t len)
{
- __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len);
+ __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len);
+}
+
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len)
+{
+ __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len);
}
#else
switch (direction) {
case DMA_MEM_TO_MEM:
- __edma3_transfer(priv->base, 1, dst, src, len);
+ __edma3_transfer(priv->base, 1, dst, src, len, len);
break;
default:
pr_err("Transfer type not implemented in DMA driver\n");
static int wait_for_user_mode(void)
{
- return wait_for_bit(__func__,
- &fpga_manager_base->imgcfg_stat,
+ return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
1, FPGA_TIMEOUT_MSEC, false);
}
/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
* timeout at 1000ms
*/
- return wait_for_bit(__func__,
- &fpga_manager_base->imgcfg_stat,
- mask,
- false, FPGA_TIMEOUT_MSEC, false);
+ return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+ mask,
+ false, FPGA_TIMEOUT_MSEC, false);
}
static int wait_for_f2s_nstatus_pin(unsigned long value)
{
/* Poll until f2s to specific value, timeout at 1000ms */
- return wait_for_bit(__func__,
- &fpga_manager_base->imgcfg_stat,
- ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
- value, FPGA_TIMEOUT_MSEC, false);
+ return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+ value, FPGA_TIMEOUT_MSEC, false);
}
/* set CD ratio */
Now, max 24 bits chips and PCA953X compatible chips are
supported
-config MPC85XX_GPIO
- bool "Freescale MPC85XX GPIO driver"
+config MPC8XXX_GPIO
+ bool "Freescale MPC8XXX GPIO driver"
depends on DM_GPIO
help
- This driver supports the built-in GPIO controller of MPC85XX CPUs.
+ This driver supports the built-in GPIO controller of MPC8XXX CPUs.
Each GPIO bank is identified by its own entry in the device tree,
i.e.
Aside from the standard functions of input/output mode, and output
value setting, the open-drain feature, which can configure individual
GPIOs to work as open-drain outputs, is supported.
-
- The driver has been tested on MPC85XX, but it is likely that other
- PowerQUICC III devices will work as well.
endmenu
obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
-obj-$(CONFIG_MPC85XX_GPIO) += mpc85xx_gpio.o
+obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
#include <common.h>
#include <dm.h>
+#include <dm/pinctrl.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
struct bcm2835_gpios {
struct bcm2835_gpio_regs *reg;
+ struct udevice *pinctrl;
};
static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
return 0;
}
-static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned gpio,
+static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned int gpio,
int value)
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
return 0;
}
-int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned gpio)
-{
- struct bcm2835_gpios *gpios = dev_get_priv(dev);
- u32 val;
-
- val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
-
- return (val >> BCM2835_GPIO_FSEL_SHIFT(gpio) & BCM2835_GPIO_FSEL_MASK);
-}
-
static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
{
- int funcid = bcm2835_gpio_get_func_id(dev, offset);
+ struct bcm2835_gpios *priv = dev_get_priv(dev);
+ int funcid;
+
+ funcid = pinctrl_get_gpio_mux(priv->pinctrl, 0, offset);
switch (funcid) {
case BCM2835_GPIO_OUTPUT:
}
}
-
static const struct dm_gpio_ops gpio_bcm2835_ops = {
.direction_input = bcm2835_gpio_direction_input,
.direction_output = bcm2835_gpio_direction_output,
uc_priv->gpio_count = BCM2835_GPIO_COUNT;
gpios->reg = (struct bcm2835_gpio_regs *)plat->base;
+ /* We know we're spawned by the pinctrl driver */
+ gpios->pinctrl = dev->parent;
+
return 0;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id bcm2835_gpio_id[] = {
- {.compatible = "brcm,bcm2835-gpio"},
- {}
-};
-
static int bcm2835_gpio_ofdata_to_platdata(struct udevice *dev)
{
struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
U_BOOT_DRIVER(gpio_bcm2835) = {
.name = "gpio_bcm2835",
.id = UCLASS_GPIO,
- .of_match = of_match_ptr(bcm2835_gpio_id),
.ofdata_to_platdata = of_match_ptr(bcm2835_gpio_ofdata_to_platdata),
.platdata_auto_alloc_size = sizeof(struct bcm2835_gpio_platdata),
.ops = &gpio_bcm2835_ops,
{ .compatible = "renesas,gpio-r8a7796" },
{ .compatible = "renesas,gpio-r8a77970" },
{ .compatible = "renesas,gpio-r8a77995" },
+ { .compatible = "renesas,rcar-gen2-gpio" },
{ .compatible = "renesas,rcar-gen3-gpio" },
{ /* sentinel */ }
};
+++ /dev/null
-/*
- * (C) Copyright 2016
- * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
- *
- * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
- *
- * Copyright 2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <mapmem.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct ccsr_gpio {
- u32 gpdir;
- u32 gpodr;
- u32 gpdat;
- u32 gpier;
- u32 gpimr;
- u32 gpicr;
-};
-
-struct mpc85xx_gpio_data {
- /* The bank's register base in memory */
- struct ccsr_gpio __iomem *base;
- /* The address of the registers; used to identify the bank */
- ulong addr;
- /* The GPIO count of the bank */
- uint gpio_count;
- /* The GPDAT register cannot be used to determine the value of output
- * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
- * for output pins */
- u32 dat_shadow;
-};
-
-inline u32 gpio_mask(unsigned gpio) {
- return (1U << (31 - (gpio)));
-}
-
-static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
-{
- return in_be32(&base->gpdat) & mask;
-}
-
-static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
-{
- return in_be32(&base->gpdir) & mask;
-}
-
-static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
-{
- clrbits_be32(&base->gpdat, gpios);
- /* GPDIR register 0 -> input */
- clrbits_be32(&base->gpdir, gpios);
-}
-
-static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
-{
- clrbits_be32(&base->gpdat, gpios);
- /* GPDIR register 1 -> output */
- setbits_be32(&base->gpdir, gpios);
-}
-
-static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
-{
- setbits_be32(&base->gpdat, gpios);
- /* GPDIR register 1 -> output */
- setbits_be32(&base->gpdir, gpios);
-}
-
-static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
-{
- return in_be32(&base->gpodr) & mask;
-}
-
-static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
- gpios)
-{
- /* GPODR register 1 -> open drain on */
- setbits_be32(&base->gpodr, gpios);
-}
-
-static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
- u32 gpios)
-{
- /* GPODR register 0 -> open drain off (actively driven) */
- clrbits_be32(&base->gpodr, gpios);
-}
-
-static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
- return 0;
-}
-
-static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio,
- int value)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- if (value) {
- data->dat_shadow |= gpio_mask(gpio);
- mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
- } else {
- data->dat_shadow &= ~gpio_mask(gpio);
- mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
- }
- return 0;
-}
-
-static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio,
- int value)
-{
- return mpc85xx_gpio_set_value(dev, gpio, value);
-}
-
-static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
- /* Output -> use shadowed value */
- return !!(data->dat_shadow & gpio_mask(gpio));
- } else {
- /* Input -> read value from GPDAT register */
- return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
- }
-}
-
-static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
-}
-
-static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
- int value)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- if (value) {
- mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
- } else {
- mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
- }
- return 0;
-}
-
-static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
- int dir;
-
- dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
- return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
- struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
- fdt_addr_t addr;
- fdt_size_t size;
-
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
- dev_of_offset(dev), "reg", 0, &size, false);
-
- plat->addr = addr;
- plat->size = size;
- plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "ngpios", 32);
-
- return 0;
-}
-#endif
-
-static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
-{
- struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
- struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
- unsigned long size = plat->size;
-
- if (size == 0)
- size = 0x100;
-
- priv->addr = plat->addr;
- priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
-
- if (!priv->base)
- return -ENOMEM;
-
- priv->gpio_count = plat->ngpios;
- priv->dat_shadow = 0;
-
- return 0;
-}
-
-static int mpc85xx_gpio_probe(struct udevice *dev)
-{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
- char name[32], *str;
-
- mpc85xx_gpio_platdata_to_priv(dev);
-
- snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
- str = strdup(name);
-
- if (!str)
- return -ENOMEM;
-
- uc_priv->bank_name = str;
- uc_priv->gpio_count = data->gpio_count;
-
- return 0;
-}
-
-static const struct dm_gpio_ops gpio_mpc85xx_ops = {
- .direction_input = mpc85xx_gpio_direction_input,
- .direction_output = mpc85xx_gpio_direction_output,
- .get_value = mpc85xx_gpio_get_value,
- .set_value = mpc85xx_gpio_set_value,
- .get_open_drain = mpc85xx_gpio_get_open_drain,
- .set_open_drain = mpc85xx_gpio_set_open_drain,
- .get_function = mpc85xx_gpio_get_function,
-};
-
-static const struct udevice_id mpc85xx_gpio_ids[] = {
- { .compatible = "fsl,pq3-gpio" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(gpio_mpc85xx) = {
- .name = "gpio_mpc85xx",
- .id = UCLASS_GPIO,
- .ops = &gpio_mpc85xx_ops,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
- .of_match = mpc85xx_gpio_ids,
-#endif
- .probe = mpc85xx_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
-};
--- /dev/null
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ *
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+};
+
+struct mpc8xxx_gpio_data {
+ /* The bank's register base in memory */
+ struct ccsr_gpio __iomem *base;
+ /* The address of the registers; used to identify the bank */
+ ulong addr;
+ /* The GPIO count of the bank */
+ uint gpio_count;
+ /* The GPDAT register cannot be used to determine the value of output
+ * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
+ * for output pins
+ */
+ u32 dat_shadow;
+ ulong type;
+};
+
+enum {
+ MPC8XXX_GPIO_TYPE,
+ MPC5121_GPIO_TYPE,
+};
+
+inline u32 gpio_mask(uint gpio)
+{
+ return (1U << (31 - (gpio)));
+}
+
+static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpdat) & mask;
+}
+
+static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpdir) & mask;
+}
+
+static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
+{
+ clrbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 0 -> input */
+ clrbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
+{
+ clrbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 1 -> output */
+ setbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
+{
+ setbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 1 -> output */
+ setbits_be32(&base->gpdir, gpios);
+}
+
+static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpodr) & mask;
+}
+
+static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+ gpios)
+{
+ /* GPODR register 1 -> open drain on */
+ setbits_be32(&base->gpodr, gpios);
+}
+
+static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
+ u32 gpios)
+{
+ /* GPODR register 0 -> open drain off (actively driven) */
+ clrbits_be32(&base->gpodr, gpios);
+}
+
+static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio));
+ return 0;
+}
+
+static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (value) {
+ data->dat_shadow |= gpio_mask(gpio);
+ mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
+ } else {
+ data->dat_shadow &= ~gpio_mask(gpio);
+ mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
+ }
+ return 0;
+}
+
+static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
+ int value)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ /* GPIO 28..31 are input only on MPC5121 */
+ if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
+ return -EINVAL;
+
+ return mpc8xxx_gpio_set_value(dev, gpio, value);
+}
+
+static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+ /* Output -> use shadowed value */
+ return !!(data->dat_shadow & gpio_mask(gpio));
+ }
+
+ /* Input -> read value from GPDAT register */
+ return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
+ int value)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (value)
+ mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+ else
+ mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+
+ return 0;
+}
+
+static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+ int dir;
+
+ dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
+ return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ fdt_addr_t addr;
+ u32 reg[2];
+
+ dev_read_u32_array(dev, "reg", reg, 2);
+ addr = dev_translate_address(dev, reg);
+
+ plat->addr = addr;
+ plat->size = reg[1];
+ plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
+
+ return 0;
+}
+#endif
+
+static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
+{
+ struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ unsigned long size = plat->size;
+ ulong driver_data = dev_get_driver_data(dev);
+
+ if (size == 0)
+ size = 0x100;
+
+ priv->addr = plat->addr;
+ priv->base = map_sysmem(plat->addr, size);
+
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->gpio_count = plat->ngpios;
+ priv->dat_shadow = 0;
+
+ priv->type = driver_data;
+
+ return 0;
+}
+
+static int mpc8xxx_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+ char name[32], *str;
+
+ mpc8xxx_gpio_platdata_to_priv(dev);
+
+ snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+ str = strdup(name);
+
+ if (!str)
+ return -ENOMEM;
+
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = data->gpio_count;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
+ .direction_input = mpc8xxx_gpio_direction_input,
+ .direction_output = mpc8xxx_gpio_direction_output,
+ .get_value = mpc8xxx_gpio_get_value,
+ .set_value = mpc8xxx_gpio_set_value,
+ .get_open_drain = mpc8xxx_gpio_get_open_drain,
+ .set_open_drain = mpc8xxx_gpio_set_open_drain,
+ .get_function = mpc8xxx_gpio_get_function,
+};
+
+static const struct udevice_id mpc8xxx_gpio_ids[] = {
+ { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
+ { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
+ { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
+ { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_mpc8xxx) = {
+ .name = "gpio_mpc8xxx",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_mpc8xxx_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+ .of_match = mpc8xxx_gpio_ids,
+#endif
+ .probe = mpc8xxx_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
+};
return (int)val;
}
-#ifdef CONFIG_CMD_PCA953X
+#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD)
/*
* Display pca953x information
*/
return 0;
}
-cmd_tbl_t cmd_pca953x[] = {
+static cmd_tbl_t cmd_pca953x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""),
};
-int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
int ret = CMD_RET_USAGE, val;
#define MAX_BANK 5
#define BANK_SZ 8
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* struct pca953x_info - Data for pca953x
*
ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
} else if (info->gpio_count == 40) {
/* Auto increment */
- ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
+ ret = dm_i2c_read(dev, (reg << 3) | 0x80, val,
+ info->bank_count);
} else {
dev_err(dev, "Unsupported now\n");
return -EINVAL;
return !(info->reg_direction[bank] & (1 << off));
}
-static int pca953x_get_value(struct udevice *dev, unsigned offset)
+static int pca953x_get_value(struct udevice *dev, uint offset)
{
int ret;
u8 val = 0;
return (val >> off) & 0x1;
}
-static int pca953x_set_value(struct udevice *dev, unsigned offset,
- int value)
+static int pca953x_set_value(struct udevice *dev, uint offset, int value)
{
struct pca953x_info *info = dev_get_platdata(dev);
int bank = offset / BANK_SZ;
return 0;
}
-static int pca953x_set_direction(struct udevice *dev, unsigned offset, int dir)
+static int pca953x_set_direction(struct udevice *dev, uint offset, int dir)
{
struct pca953x_info *info = dev_get_platdata(dev);
int bank = offset / BANK_SZ;
return 0;
}
-static int pca953x_direction_input(struct udevice *dev, unsigned offset)
+static int pca953x_direction_input(struct udevice *dev, uint offset)
{
return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
}
-static int pca953x_direction_output(struct udevice *dev, unsigned offset,
- int value)
+static int pca953x_direction_output(struct udevice *dev, uint offset, int value)
{
/* Configure output value. */
pca953x_set_value(dev, offset, value);
return 0;
}
-static int pca953x_get_function(struct udevice *dev, unsigned offset)
+static int pca953x_get_function(struct udevice *dev, uint offset)
{
if (pca953x_is_output(dev, offset))
return GPIOF_OUTPUT;
struct ofnode_phandle_args *args)
{
desc->offset = args->args[0];
- desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+ desc->flags = args->args[1] & (GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
return 0;
}
ulong driver_data;
int ret;
- addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
+ addr = dev_read_addr(dev);
if (addr == 0)
return -ENODEV;
ID("allwinner,sun4i-a10-pinctrl", a_all),
ID("allwinner,sun5i-a10s-pinctrl", a_all),
ID("allwinner,sun5i-a13-pinctrl", a_all),
+ ID("allwinner,sun50i-h5-pinctrl", a_all),
ID("allwinner,sun6i-a31-pinctrl", a_all),
ID("allwinner,sun6i-a31s-pinctrl", a_all),
ID("allwinner,sun7i-a20-pinctrl", a_all),
return ret;
}
-#ifdef CONFIG_CMD_TCA642X
+#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD)
/*
* Display tca642x information
*/
return 0;
}
-cmd_tbl_t cmd_tca642x[] = {
+static cmd_tbl_t cmd_tca642x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""),
};
-int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
int ret = CMD_RET_USAGE, val;
help
Add support for the OMAP2+ I2C driver.
+if SYS_I2C_OMAP24XX
+config SYS_OMAP24_I2C_SLAVE
+ int "I2C Slave addr channel 0"
+ default 1
+ help
+ OMAP24xx I2C Slave address channel 0
+
+config SYS_OMAP24_I2C_SPEED
+ int "I2C Slave channel 0 speed"
+ default 100000
+ help
+ OMAP24xx Slave speed channel 0
+endif
+
config SYS_I2C_RCAR_IIC
bool "Renesas RCar Gen3 IIC driver"
depends on RCAR_GEN3 && DM_I2C
free(table_loader);
return addr;
}
+
+ulong acpi_get_rsdp_addr(void)
+{
+ struct fw_file *file;
+
+ file = qemu_fwcfg_find_file("etc/acpi/rsdp");
+ return file->addr;
+}
#endif
/* Read configuration item using fw_cfg PIO interface */
help
Enable write access to MMC and SD Cards
+config MMC_BROKEN_CD
+ bool "Poll for broken card detection case"
+ help
+ If card detection feature is broken, just poll to detect.
+
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
This selects support for the Matsushita SD/MMC Host Controller on
SocioNext UniPhier and Renesas RCar SoCs.
+config MMC_BCM2835
+ bool "BCM2835 family custom SD/MMC Host Controller support"
+ depends on ARCH_BCM283X
+ depends on BLK && DM_MMC
+ depends on OF_CONTROL
+ default y
+ help
+ This selects support for the custom SD host controller in the BCM2835
+ family of devices.
+
+ If you have a BCM2835 platform with SD or MMC devices, say Y here.
+
+ If unsure, say N.
+
config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
+obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
--- /dev/null
+/*
+ * bcm2835 sdhost driver.
+ *
+ * The 2835 has two SD controllers: The Arasan sdhci controller
+ * (supported by the iproc driver) and a custom sdhost controller
+ * (supported by this driver).
+ *
+ * The sdhci controller supports both sdcard and sdio. The sdhost
+ * controller supports the sdcard only, but has better performance.
+ * Also note that the rpi3 has sdio wifi, so driving the sdcard with
+ * the sdhost controller allows to use the sdhci controller for wifi
+ * support.
+ *
+ * The configuration is done by devicetree via pin muxing. Both
+ * SD controller are available on the same pins (2 pin groups = pin 22
+ * to 27 + pin 48 to 53). So it's possible to use both SD controllers
+ * at the same time with different pin groups.
+ *
+ * This code was ported to U-Boot by
+ * Alexander Graf <agraf@suse.de>
+ * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
+ * Phil Elwell <phil@raspberrypi.org>
+ * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
+ * which is based on
+ * mmc-bcm2835.c by Gellert Weisz
+ * which is, in turn, based on
+ * sdhci-bcm2708.c by Broadcom
+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
+ * sdhci.c and sdhci-pci.c by Pierre Ossman
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <mmc.h>
+#include <asm/arch/msg.h>
+#include <asm/unaligned.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/sizes.h>
+#include <mach/gpio.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define msleep(a) udelay(a * 1000)
+
+#define SDCMD 0x00 /* Command to SD card - 16 R/W */
+#define SDARG 0x04 /* Argument to SD card - 32 R/W */
+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
+#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
+#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
+#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
+#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
+#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
+#define SDHSTS 0x20 /* SD host status - 11 R/W */
+#define SDVDD 0x30 /* SD card power control - 1 R/W */
+#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
+#define SDHCFG 0x38 /* Host configuration - 2 R/W */
+#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
+#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
+
+#define SDCMD_NEW_FLAG 0x8000
+#define SDCMD_FAIL_FLAG 0x4000
+#define SDCMD_BUSYWAIT 0x800
+#define SDCMD_NO_RESPONSE 0x400
+#define SDCMD_LONG_RESPONSE 0x200
+#define SDCMD_WRITE_CMD 0x80
+#define SDCMD_READ_CMD 0x40
+#define SDCMD_CMD_MASK 0x3f
+
+#define SDCDIV_MAX_CDIV 0x7ff
+
+#define SDHSTS_BUSY_IRPT 0x400
+#define SDHSTS_BLOCK_IRPT 0x200
+#define SDHSTS_SDIO_IRPT 0x100
+#define SDHSTS_REW_TIME_OUT 0x80
+#define SDHSTS_CMD_TIME_OUT 0x40
+#define SDHSTS_CRC16_ERROR 0x20
+#define SDHSTS_CRC7_ERROR 0x10
+#define SDHSTS_FIFO_ERROR 0x08
+#define SDHSTS_DATA_FLAG 0x01
+
+#define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
+ SDHSTS_BLOCK_IRPT | \
+ SDHSTS_SDIO_IRPT | \
+ SDHSTS_REW_TIME_OUT | \
+ SDHSTS_CMD_TIME_OUT | \
+ SDHSTS_CRC16_ERROR | \
+ SDHSTS_CRC7_ERROR | \
+ SDHSTS_FIFO_ERROR)
+
+#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
+ SDHSTS_CRC16_ERROR | \
+ SDHSTS_REW_TIME_OUT | \
+ SDHSTS_FIFO_ERROR)
+
+#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
+ SDHSTS_TRANSFER_ERROR_MASK)
+
+#define SDHCFG_BUSY_IRPT_EN BIT(10)
+#define SDHCFG_BLOCK_IRPT_EN BIT(8)
+#define SDHCFG_SDIO_IRPT_EN BIT(5)
+#define SDHCFG_DATA_IRPT_EN BIT(4)
+#define SDHCFG_SLOW_CARD BIT(3)
+#define SDHCFG_WIDE_EXT_BUS BIT(2)
+#define SDHCFG_WIDE_INT_BUS BIT(1)
+#define SDHCFG_REL_CMD_LINE BIT(0)
+
+#define SDVDD_POWER_OFF 0
+#define SDVDD_POWER_ON 1
+
+#define SDEDM_FORCE_DATA_MODE BIT(19)
+#define SDEDM_CLOCK_PULSE BIT(20)
+#define SDEDM_BYPASS BIT(21)
+
+#define SDEDM_FIFO_FILL_SHIFT 4
+#define SDEDM_FIFO_FILL_MASK 0x1f
+static u32 edm_fifo_fill(u32 edm)
+{
+ return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
+}
+
+#define SDEDM_WRITE_THRESHOLD_SHIFT 9
+#define SDEDM_READ_THRESHOLD_SHIFT 14
+#define SDEDM_THRESHOLD_MASK 0x1f
+
+#define SDEDM_FSM_MASK 0xf
+#define SDEDM_FSM_IDENTMODE 0x0
+#define SDEDM_FSM_DATAMODE 0x1
+#define SDEDM_FSM_READDATA 0x2
+#define SDEDM_FSM_WRITEDATA 0x3
+#define SDEDM_FSM_READWAIT 0x4
+#define SDEDM_FSM_READCRC 0x5
+#define SDEDM_FSM_WRITECRC 0x6
+#define SDEDM_FSM_WRITEWAIT1 0x7
+#define SDEDM_FSM_POWERDOWN 0x8
+#define SDEDM_FSM_POWERUP 0x9
+#define SDEDM_FSM_WRITESTART1 0xa
+#define SDEDM_FSM_WRITESTART2 0xb
+#define SDEDM_FSM_GENPULSES 0xc
+#define SDEDM_FSM_WRITEWAIT2 0xd
+#define SDEDM_FSM_STARTPOWDOWN 0xf
+
+#define SDDATA_FIFO_WORDS 16
+
+#define FIFO_READ_THRESHOLD 4
+#define FIFO_WRITE_THRESHOLD 4
+#define SDDATA_FIFO_PIO_BURST 8
+
+#define SDHST_TIMEOUT_MAX_USEC 100000
+
+struct bcm2835_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct bcm2835_host {
+ void __iomem *ioaddr;
+ u32 phys_addr;
+
+ int clock; /* Current clock speed */
+ unsigned int max_clk; /* Max possible freq */
+ unsigned int blocks; /* remaining PIO blocks */
+ int irq; /* Device IRQ */
+
+ u32 ns_per_fifo_word;
+
+ /* cached registers */
+ u32 hcfg;
+ u32 cdiv;
+
+ struct mmc_cmd *cmd; /* Current command */
+ struct mmc_data *data; /* Current data request */
+ bool data_complete:1;/* Data finished before cmd */
+ bool use_busy:1; /* Wait for busy interrupt */
+ bool wait_data_complete:1; /* Wait for data */
+
+ /* for threaded irq handler */
+ bool irq_block;
+ bool irq_busy;
+ bool irq_data;
+
+ struct udevice *dev;
+ struct mmc *mmc;
+ struct bcm2835_plat *plat;
+};
+
+static void bcm2835_dumpregs(struct bcm2835_host *host)
+{
+ dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
+ dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
+ dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
+ dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
+ dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
+ dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
+ dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
+ dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
+ dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
+ dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
+ dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
+ dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
+ dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
+ dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
+ dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
+ dev_dbg(dev, "===========================================\n");
+}
+
+static void bcm2835_reset_internal(struct bcm2835_host *host)
+{
+ u32 temp;
+
+ writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
+ writel(0, host->ioaddr + SDCMD);
+ writel(0, host->ioaddr + SDARG);
+ /* Set timeout to a big enough value so we don't hit it */
+ writel(0xf00000, host->ioaddr + SDTOUT);
+ writel(0, host->ioaddr + SDCDIV);
+ /* Clear status register */
+ writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
+ writel(0, host->ioaddr + SDHCFG);
+ writel(0, host->ioaddr + SDHBCT);
+ writel(0, host->ioaddr + SDHBLC);
+
+ /* Limit fifo usage due to silicon bug */
+ temp = readl(host->ioaddr + SDEDM);
+ temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
+ (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
+ temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
+ (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
+ writel(temp, host->ioaddr + SDEDM);
+ /* Wait for FIFO threshold to populate */
+ msleep(20);
+ writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
+ /* Wait for all components to go through power on cycle */
+ msleep(20);
+ host->clock = 0;
+ writel(host->hcfg, host->ioaddr + SDHCFG);
+ writel(host->cdiv, host->ioaddr + SDCDIV);
+}
+
+static int bcm2835_finish_command(struct bcm2835_host *host);
+
+static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
+{
+ int timediff;
+ u32 alternate_idle;
+
+ alternate_idle = (host->data->flags & MMC_DATA_READ) ?
+ SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
+
+ timediff = 0;
+
+ while (1) {
+ u32 edm, fsm;
+
+ edm = readl(host->ioaddr + SDEDM);
+ fsm = edm & SDEDM_FSM_MASK;
+
+ if ((fsm == SDEDM_FSM_IDENTMODE) ||
+ (fsm == SDEDM_FSM_DATAMODE))
+ break;
+ if (fsm == alternate_idle) {
+ writel(edm | SDEDM_FORCE_DATA_MODE,
+ host->ioaddr + SDEDM);
+ break;
+ }
+
+ /* Error out after 100000 register reads (~1s) */
+ if (timediff++ == 100000) {
+ dev_err(host->dev,
+ "wait_transfer_complete - still waiting after %d retries\n",
+ timediff);
+ bcm2835_dumpregs(host);
+ return;
+ }
+ }
+}
+
+static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
+{
+ struct mmc_data *data = host->data;
+ size_t blksize = data->blocksize;
+ int copy_words;
+ u32 hsts = 0;
+ u32 *buf;
+
+ if (blksize % sizeof(u32))
+ return -EINVAL;
+
+ buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
+
+ if (is_read)
+ data->dest += blksize;
+ else
+ data->src += blksize;
+
+ copy_words = blksize / sizeof(u32);
+
+ /*
+ * Copy all contents from/to the FIFO as far as it reaches,
+ * then wait for it to fill/empty again and rewind.
+ */
+ while (copy_words) {
+ int burst_words, words;
+ u32 edm;
+
+ burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
+ edm = readl(host->ioaddr + SDEDM);
+ if (is_read)
+ words = edm_fifo_fill(edm);
+ else
+ words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
+
+ if (words < burst_words) {
+ int fsm_state = (edm & SDEDM_FSM_MASK);
+
+ if ((is_read &&
+ (fsm_state != SDEDM_FSM_READDATA &&
+ fsm_state != SDEDM_FSM_READWAIT &&
+ fsm_state != SDEDM_FSM_READCRC)) ||
+ (!is_read &&
+ (fsm_state != SDEDM_FSM_WRITEDATA &&
+ fsm_state != SDEDM_FSM_WRITESTART1 &&
+ fsm_state != SDEDM_FSM_WRITESTART2))) {
+ hsts = readl(host->ioaddr + SDHSTS);
+ printf("fsm %x, hsts %08x\n", fsm_state, hsts);
+ if (hsts & SDHSTS_ERROR_MASK)
+ break;
+ }
+
+ continue;
+ } else if (words > copy_words) {
+ words = copy_words;
+ }
+
+ copy_words -= words;
+
+ /* Copy current chunk to/from the FIFO */
+ while (words) {
+ if (is_read)
+ *(buf++) = readl(host->ioaddr + SDDATA);
+ else
+ writel(*(buf++), host->ioaddr + SDDATA);
+ words--;
+ }
+ }
+
+ return 0;
+}
+
+static int bcm2835_transfer_pio(struct bcm2835_host *host)
+{
+ u32 sdhsts;
+ bool is_read;
+ int ret = 0;
+
+ is_read = (host->data->flags & MMC_DATA_READ) != 0;
+ ret = bcm2835_transfer_block_pio(host, is_read);
+
+ if (host->wait_data_complete)
+ bcm2835_wait_transfer_complete(host);
+
+ sdhsts = readl(host->ioaddr + SDHSTS);
+ if (sdhsts & (SDHSTS_CRC16_ERROR |
+ SDHSTS_CRC7_ERROR |
+ SDHSTS_FIFO_ERROR)) {
+ printf("%s transfer error - HSTS %08x\n",
+ is_read ? "read" : "write", sdhsts);
+ ret = -EILSEQ;
+ } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
+ SDHSTS_REW_TIME_OUT))) {
+ printf("%s timeout error - HSTS %08x\n",
+ is_read ? "read" : "write", sdhsts);
+ ret = -ETIMEDOUT;
+ }
+
+ return ret;
+}
+
+static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
+{
+ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
+ SDHCFG_BUSY_IRPT_EN;
+
+ host->hcfg = (host->hcfg & ~all_irqs) |
+ SDHCFG_DATA_IRPT_EN |
+ SDHCFG_BUSY_IRPT_EN;
+
+ writel(host->hcfg, host->ioaddr + SDHCFG);
+}
+
+static
+void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ WARN_ON(host->data);
+
+ host->data = data;
+ if (!data)
+ return;
+
+ host->wait_data_complete = cmd->cmdidx != MMC_CMD_READ_MULTIPLE_BLOCK;
+ host->data_complete = false;
+
+ /* Use PIO */
+ host->blocks = data->blocks;
+
+ bcm2835_set_transfer_irqs(host);
+
+ writel(data->blocksize, host->ioaddr + SDHBCT);
+ writel(data->blocks, host->ioaddr + SDHBLC);
+}
+
+static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
+{
+ u32 value;
+ int ret;
+ int timeout_us = SDHST_TIMEOUT_MAX_USEC;
+
+ ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
+ !(value & SDCMD_NEW_FLAG), timeout_us);
+ if (ret == -ETIMEDOUT)
+ printf("%s: timeout (%d us)\n", __func__, timeout_us);
+
+ return value;
+}
+
+static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ u32 sdcmd, sdhsts;
+
+ WARN_ON(host->cmd);
+
+ if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
+ printf("unsupported response type!\n");
+ return -EINVAL;
+ }
+
+ sdcmd = bcm2835_read_wait_sdcmd(host);
+ if (sdcmd & SDCMD_NEW_FLAG) {
+ printf("previous command never completed.\n");
+ bcm2835_dumpregs(host);
+ return -EBUSY;
+ }
+
+ host->cmd = cmd;
+
+ /* Clear any error flags */
+ sdhsts = readl(host->ioaddr + SDHSTS);
+ if (sdhsts & SDHSTS_ERROR_MASK)
+ writel(sdhsts, host->ioaddr + SDHSTS);
+
+ bcm2835_prepare_data(host, cmd, data);
+
+ writel(cmd->cmdarg, host->ioaddr + SDARG);
+
+ sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
+
+ host->use_busy = false;
+ if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
+ sdcmd |= SDCMD_NO_RESPONSE;
+ } else {
+ if (cmd->resp_type & MMC_RSP_136)
+ sdcmd |= SDCMD_LONG_RESPONSE;
+ if (cmd->resp_type & MMC_RSP_BUSY) {
+ sdcmd |= SDCMD_BUSYWAIT;
+ host->use_busy = true;
+ }
+ }
+
+ if (data) {
+ if (data->flags & MMC_DATA_WRITE)
+ sdcmd |= SDCMD_WRITE_CMD;
+ if (data->flags & MMC_DATA_READ)
+ sdcmd |= SDCMD_READ_CMD;
+ }
+
+ writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
+
+ return 0;
+}
+
+static int bcm2835_transfer_complete(struct bcm2835_host *host)
+{
+ int ret = 0;
+
+ WARN_ON(!host->data_complete);
+
+ host->data = NULL;
+
+ return ret;
+}
+
+static void bcm2835_finish_data(struct bcm2835_host *host)
+{
+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
+ writel(host->hcfg, host->ioaddr + SDHCFG);
+
+ host->data_complete = true;
+
+ if (host->cmd) {
+ /* Data managed to finish before the
+ * command completed. Make sure we do
+ * things in the proper order.
+ */
+ dev_dbg(dev, "Finished early - HSTS %08x\n",
+ readl(host->ioaddr + SDHSTS));
+ } else {
+ bcm2835_transfer_complete(host);
+ }
+}
+
+static int bcm2835_finish_command(struct bcm2835_host *host)
+{
+ struct mmc_cmd *cmd = host->cmd;
+ u32 sdcmd;
+ int ret = 0;
+
+ sdcmd = bcm2835_read_wait_sdcmd(host);
+
+ /* Check for errors */
+ if (sdcmd & SDCMD_NEW_FLAG) {
+ printf("command never completed.\n");
+ bcm2835_dumpregs(host);
+ return -EIO;
+ } else if (sdcmd & SDCMD_FAIL_FLAG) {
+ u32 sdhsts = readl(host->ioaddr + SDHSTS);
+
+ /* Clear the errors */
+ writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
+
+ if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
+ (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
+ if (sdhsts & SDHSTS_CMD_TIME_OUT) {
+ ret = -ETIMEDOUT;
+ } else {
+ printf("unexpected command %d error\n",
+ host->cmd->cmdidx);
+ bcm2835_dumpregs(host);
+ ret = -EILSEQ;
+ }
+
+ return ret;
+ }
+ }
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ cmd->response[3 - i] =
+ readl(host->ioaddr + SDRSP0 + i * 4);
+ }
+ } else {
+ cmd->response[0] = readl(host->ioaddr + SDRSP0);
+ }
+ }
+
+ /* Processed actual command. */
+ host->cmd = NULL;
+ if (host->data && host->data_complete)
+ ret = bcm2835_transfer_complete(host);
+
+ return ret;
+}
+
+static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
+{
+ int ret = -EINVAL;
+
+ if (!(intmask & SDHSTS_ERROR_MASK))
+ return 0;
+
+ if (!host->cmd)
+ return -EINVAL;
+
+ printf("sdhost_busy_irq: intmask %08x\n", intmask);
+ if (intmask & SDHSTS_CRC7_ERROR) {
+ ret = -EILSEQ;
+ } else if (intmask & (SDHSTS_CRC16_ERROR |
+ SDHSTS_FIFO_ERROR)) {
+ ret = -EILSEQ;
+ } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
+ ret = -ETIMEDOUT;
+ }
+ bcm2835_dumpregs(host);
+ return ret;
+}
+
+static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
+{
+ int ret = 0;
+
+ if (!host->data)
+ return 0;
+ if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
+ ret = -EILSEQ;
+ if (intmask & SDHSTS_REW_TIME_OUT)
+ ret = -ETIMEDOUT;
+
+ if (ret)
+ printf("%s:%d %d\n", __func__, __LINE__, ret);
+
+ return ret;
+}
+
+static void bcm2835_busy_irq(struct bcm2835_host *host)
+{
+ if (WARN_ON(!host->cmd)) {
+ bcm2835_dumpregs(host);
+ return;
+ }
+
+ if (WARN_ON(!host->use_busy)) {
+ bcm2835_dumpregs(host);
+ return;
+ }
+ host->use_busy = false;
+
+ bcm2835_finish_command(host);
+}
+
+static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
+{
+ int ret;
+
+ /*
+ * There are no dedicated data/space available interrupt
+ * status bits, so it is necessary to use the single shared
+ * data/space available FIFO status bits. It is therefore not
+ * an error to get here when there is no data transfer in
+ * progress.
+ */
+ if (!host->data)
+ return;
+
+ ret = bcm2835_check_data_error(host, intmask);
+ if (ret)
+ goto finished;
+
+ if (host->data->flags & MMC_DATA_WRITE) {
+ /* Use the block interrupt for writes after the first block */
+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
+ host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
+ writel(host->hcfg, host->ioaddr + SDHCFG);
+ bcm2835_transfer_pio(host);
+ } else {
+ bcm2835_transfer_pio(host);
+ host->blocks--;
+ if ((host->blocks == 0))
+ goto finished;
+ }
+ return;
+
+finished:
+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
+ writel(host->hcfg, host->ioaddr + SDHCFG);
+}
+
+static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
+{
+ if (!host->data)
+ return;
+ if ((host->blocks == 0))
+ bcm2835_finish_data(host);
+}
+
+static void bcm2835_block_irq(struct bcm2835_host *host)
+{
+ if (WARN_ON(!host->data)) {
+ bcm2835_dumpregs(host);
+ return;
+ }
+
+ WARN_ON(!host->blocks);
+ if ((--host->blocks == 0))
+ bcm2835_finish_data(host);
+ else
+ bcm2835_transfer_pio(host);
+}
+
+static irqreturn_t bcm2835_irq(int irq, void *dev_id)
+{
+ irqreturn_t result = IRQ_NONE;
+ struct bcm2835_host *host = dev_id;
+ u32 intmask;
+
+ intmask = readl(host->ioaddr + SDHSTS);
+
+ writel(SDHSTS_BUSY_IRPT |
+ SDHSTS_BLOCK_IRPT |
+ SDHSTS_SDIO_IRPT |
+ SDHSTS_DATA_FLAG,
+ host->ioaddr + SDHSTS);
+
+ if (intmask & SDHSTS_BLOCK_IRPT) {
+ bcm2835_check_data_error(host, intmask);
+ host->irq_block = true;
+ result = IRQ_WAKE_THREAD;
+ }
+
+ if (intmask & SDHSTS_BUSY_IRPT) {
+ if (!bcm2835_check_cmd_error(host, intmask)) {
+ host->irq_busy = true;
+ result = IRQ_WAKE_THREAD;
+ } else {
+ result = IRQ_HANDLED;
+ }
+ }
+
+ /* There is no true data interrupt status bit, so it is
+ * necessary to qualify the data flag with the interrupt
+ * enable bit.
+ */
+ if ((intmask & SDHSTS_DATA_FLAG) &&
+ (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
+ bcm2835_data_irq(host, intmask);
+ host->irq_data = true;
+ result = IRQ_WAKE_THREAD;
+ }
+
+ return result;
+}
+
+static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
+{
+ struct bcm2835_host *host = dev_id;
+
+ if (host->irq_block) {
+ host->irq_block = false;
+ bcm2835_block_irq(host);
+ }
+
+ if (host->irq_busy) {
+ host->irq_busy = false;
+ bcm2835_busy_irq(host);
+ }
+
+ if (host->irq_data) {
+ host->irq_data = false;
+ bcm2835_data_threaded_irq(host);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void bcm2835_irq_poll(struct bcm2835_host *host)
+{
+ u32 intmask;
+
+ while (1) {
+ intmask = readl(host->ioaddr + SDHSTS);
+ if (intmask & (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT |
+ SDHSTS_SDIO_IRPT | SDHSTS_DATA_FLAG)) {
+ bcm2835_irq(0, host);
+ bcm2835_threaded_irq(0, host);
+ return;
+ }
+ }
+}
+
+static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
+{
+ int div;
+
+ /* The SDCDIV register has 11 bits, and holds (div - 2). But
+ * in data mode the max is 50MHz wihout a minimum, and only
+ * the bottom 3 bits are used. Since the switch over is
+ * automatic (unless we have marked the card as slow...),
+ * chosen values have to make sense in both modes. Ident mode
+ * must be 100-400KHz, so can range check the requested
+ * clock. CMD15 must be used to return to data mode, so this
+ * can be monitored.
+ *
+ * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
+ * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
+ *
+ * 623->400KHz/27.8MHz
+ * reset value (507)->491159/50MHz
+ *
+ * BUT, the 3-bit clock divisor in data mode is too small if
+ * the core clock is higher than 250MHz, so instead use the
+ * SLOW_CARD configuration bit to force the use of the ident
+ * clock divisor at all times.
+ */
+
+ if (clock < 100000) {
+ /* Can't stop the clock, but make it as slow as possible
+ * to show willing
+ */
+ host->cdiv = SDCDIV_MAX_CDIV;
+ writel(host->cdiv, host->ioaddr + SDCDIV);
+ return;
+ }
+
+ div = host->max_clk / clock;
+ if (div < 2)
+ div = 2;
+ if ((host->max_clk / div) > clock)
+ div++;
+ div -= 2;
+
+ if (div > SDCDIV_MAX_CDIV)
+ div = SDCDIV_MAX_CDIV;
+
+ clock = host->max_clk / (div + 2);
+ host->mmc->clock = clock;
+
+ /* Calibrate some delays */
+
+ host->ns_per_fifo_word = (1000000000 / clock) *
+ ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
+
+ host->cdiv = div;
+ writel(host->cdiv, host->ioaddr + SDCDIV);
+
+ /* Set the timeout to 500ms */
+ writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
+}
+
+static inline int is_power_of_2(u64 x)
+{
+ return !(x & (x - 1));
+}
+
+static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct bcm2835_host *host = dev_get_priv(dev);
+ u32 edm, fsm;
+ int ret = 0;
+
+ if (data && !is_power_of_2(data->blocksize)) {
+ printf("unsupported block size (%d bytes)\n", data->blocksize);
+
+ if (cmd)
+ return -EINVAL;
+ }
+
+ edm = readl(host->ioaddr + SDEDM);
+ fsm = edm & SDEDM_FSM_MASK;
+
+ if ((fsm != SDEDM_FSM_IDENTMODE) &&
+ (fsm != SDEDM_FSM_DATAMODE) &&
+ (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
+ printf("previous command (%d) not complete (EDM %08x)\n",
+ readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
+ bcm2835_dumpregs(host);
+
+ if (cmd)
+ return -EILSEQ;
+
+ return 0;
+ }
+
+ if (cmd) {
+ ret = bcm2835_send_command(host, cmd, data);
+ if (!ret && !host->use_busy)
+ ret = bcm2835_finish_command(host);
+ }
+
+ /* Wait for completion of busy signal or data transfer */
+ while (host->use_busy || host->data)
+ bcm2835_irq_poll(host);
+
+ return ret;
+}
+
+static int bcm2835_set_ios(struct udevice *dev)
+{
+ struct bcm2835_host *host = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+ if (!mmc->clock || mmc->clock != host->clock) {
+ bcm2835_set_clock(host, mmc->clock);
+ host->clock = mmc->clock;
+ }
+
+ /* set bus width */
+ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
+ if (mmc->bus_width == 4)
+ host->hcfg |= SDHCFG_WIDE_EXT_BUS;
+
+ host->hcfg |= SDHCFG_WIDE_INT_BUS;
+
+ /* Disable clever clock switching, to cope with fast core clocks */
+ host->hcfg |= SDHCFG_SLOW_CARD;
+
+ writel(host->hcfg, host->ioaddr + SDHCFG);
+
+ return 0;
+}
+
+static void bcm2835_add_host(struct bcm2835_host *host)
+{
+ struct mmc_config *cfg = &host->plat->cfg;
+
+ cfg->f_max = host->max_clk;
+ cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
+ cfg->b_max = 65535;
+
+ dev_dbg(dev, "f_max %d, f_min %d\n",
+ cfg->f_max, cfg->f_min);
+
+ /* host controller capabilities */
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+ /* report supported voltage ranges */
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ /* Set interrupt enables */
+ host->hcfg = SDHCFG_BUSY_IRPT_EN;
+
+ bcm2835_reset_internal(host);
+}
+
+static int bcm2835_probe(struct udevice *dev)
+{
+ struct bcm2835_plat *plat = dev_get_platdata(dev);
+ struct bcm2835_host *host = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+
+ host->dev = dev;
+ host->mmc = mmc;
+ host->plat = plat;
+ upriv->mmc = &plat->mmc;
+ plat->cfg.name = dev->name;
+
+ host->phys_addr = devfdt_get_addr(dev);
+ if (host->phys_addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
+ if (!host->ioaddr)
+ return -ENOMEM;
+
+ host->max_clk = bcm2835_get_mmc_clock();
+
+ bcm2835_add_host(host);
+
+ dev_dbg(dev, "%s -> OK\n", __func__);
+
+ return 0;
+}
+
+static const struct udevice_id bcm2835_match[] = {
+ { .compatible = "brcm,bcm2835-sdhost" },
+ { }
+};
+
+static const struct dm_mmc_ops bcm2835_ops = {
+ .send_cmd = bcm2835_send_cmd,
+ .set_ios = bcm2835_set_ios,
+};
+
+static int bcm2835_bind(struct udevice *dev)
+{
+ struct bcm2835_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+U_BOOT_DRIVER(bcm2835_sdhost) = {
+ .name = "bcm2835-sdhost",
+ .id = UCLASS_MMC,
+ .of_match = bcm2835_match,
+ .bind = bcm2835_bind,
+ .probe = bcm2835_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm2835_host),
+ .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),
+ .ops = &bcm2835_ops,
+};
static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
int pre_div = 1;
+#endif
#else
int pre_div = 2;
#endif
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- struct fsl_esdhc *regs = priv->esdhc_regs;
int sdhc_clk = priv->sdhc_clk;
uint clk;
cfg->host_caps |= MMC_MODE_1BIT;
break;
default:
- debug("warning: %s invalid bus-width property. using 1-bit\n",
- dev_read_name(dev));
- cfg->host_caps |= MMC_MODE_1BIT;
- break;
+ dev_err(dev, "Invalid \"bus-width\" value %u!\n", val);
+ return -EINVAL;
}
- cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
+ /* f_max is obtained from the optional "max-frequency" property */
+ dev_read_u32(dev, "max-frequency", &cfg->f_max);
if (dev_read_bool(dev, "cap-sd-highspeed"))
cfg->host_caps |= MMC_CAP(SD_HS);
int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
{
- if (clock > mmc->cfg->f_max)
- clock = mmc->cfg->f_max;
+ if (!disable) {
+ if (clock > mmc->cfg->f_max)
+ clock = mmc->cfg->f_max;
- if (clock < mmc->cfg->f_min)
- clock = mmc->cfg->f_min;
+ if (clock < mmc->cfg->f_min)
+ clock = mmc->cfg->f_min;
+ }
mmc->clock = clock;
mmc->clk_disable = disable;
static int mmc_power_off(struct mmc *mmc)
{
- mmc_set_clock(mmc, 1, true);
+ mmc_set_clock(mmc, 0, true);
#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
if (mmc->vmmc_supply) {
int ret = regulator_set_enable(mmc->vmmc_supply, false);
mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
+#if !defined(CONFIG_MMC_BROKEN_CD)
/* we pretend there's no card when init is NULL */
no_card = mmc_getcd(mmc) == 0;
+#else
+ no_card = 0;
+#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
no_card = no_card || (mmc->cfg->ops->init == NULL);
#endif
/* Wait for reset to be written to register */
- if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2,
- SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
+ if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
+ SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
printf("msm_sdhci: reset request failed\n");
return -EIO;
}
/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
- if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER,
- SDCC_MCI_POWER_SW_RST, false, 2, false)) {
+ if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
+ SDCC_MCI_POWER_SW_RST, false, 2, false)) {
printf("msm_sdhci: stuck in reset\n");
return -ETIMEDOUT;
}
#include <config.h>
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#define SYSCTL_SRC (1 << 25)
#define SYSCTL_SRD (1 << 26)
-struct omap2_mmc_platform_config {
- u32 reg_offset;
-};
-
struct omap_hsmmc_data {
struct hsmmc *base_addr;
#if !CONFIG_IS_ENABLED(DM_MMC)
int wp_gpio;
#endif
#endif
+ u8 controller_flags;
+#ifndef CONFIG_OMAP34XX
+ struct omap_hsmmc_adma_desc *adma_desc_table;
+ uint desc_slot;
+#endif
};
+#ifndef CONFIG_OMAP34XX
+struct omap_hsmmc_adma_desc {
+ u8 attr;
+ u8 reserved;
+ u16 len;
+ u32 addr;
+};
+
+#define ADMA_MAX_LEN 63488
+
+/* Decriptor table defines */
+#define ADMA_DESC_ATTR_VALID BIT(0)
+#define ADMA_DESC_ATTR_END BIT(1)
+#define ADMA_DESC_ATTR_INT BIT(2)
+#define ADMA_DESC_ATTR_ACT1 BIT(4)
+#define ADMA_DESC_ATTR_ACT2 BIT(5)
+
+#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
+#endif
+
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
+/* DMA transfers can take a long time if a lot a data is transferred.
+ * The timeout must take in account the amount of data. Let's assume
+ * that the time will never exceed 333 ms per MB (in other word we assume
+ * that the bandwidth is always above 3MB/s).
+ */
+#define DMA_TIMEOUT_PER_MB 333
+#define OMAP_HSMMC_USE_ADMA BIT(2)
+
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
return -ETIMEDOUT;
}
}
+#ifndef CONFIG_OMAP34XX
+ reg_val = readl(&mmc_base->hl_hwinfo);
+ if (reg_val & MADMA_EN)
+ priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
+#endif
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
&mmc_base->capa);
dsor = 240;
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
- (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ (ICE_STOP | DTO_15THDTO));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
- IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
- &mmc_base->ie);
+ IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
+ IE_CC, &mmc_base->ie);
mmc_init_stream(mmc_base);
}
}
}
+
+#ifndef CONFIG_OMAP34XX
+static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
+{
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ struct omap_hsmmc_adma_desc *desc;
+ u8 attr;
+
+ desc = &priv->adma_desc_table[priv->desc_slot];
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (!end)
+ priv->desc_slot++;
+ else
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->len = len;
+ desc->addr = (u32)buf;
+ desc->reserved = 0;
+ desc->attr = attr;
+}
+
+static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
+ struct mmc_data *data)
+{
+ uint total_len = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ int i = desc_count;
+ char *buf;
+
+ priv->desc_slot = 0;
+ priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
+ memalign(ARCH_DMA_MINALIGN, desc_count *
+ sizeof(struct omap_hsmmc_adma_desc));
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ while (--i) {
+ omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
+ buf += ADMA_MAX_LEN;
+ total_len -= ADMA_MAX_LEN;
+ }
+
+ omap_hsmmc_adma_desc(mmc, buf, total_len, true);
+
+ flush_dcache_range((long)priv->adma_desc_table,
+ (long)priv->adma_desc_table +
+ ROUND(desc_count *
+ sizeof(struct omap_hsmmc_adma_desc),
+ ARCH_DMA_MINALIGN));
+}
+
+static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
+{
+ struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ u32 val;
+ char *buf;
+
+ mmc_base = priv->base_addr;
+ omap_hsmmc_prepare_adma_table(mmc, data);
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ val = readl(&mmc_base->hctl);
+ val |= DMA_SELECT;
+ writel(val, &mmc_base->hctl);
+
+ val = readl(&mmc_base->con);
+ val |= DMA_MASTER;
+ writel(val, &mmc_base->con);
+
+ writel((u32)priv->adma_desc_table, &mmc_base->admasal);
+
+ flush_dcache_range((u32)buf,
+ (u32)buf +
+ ROUND(data->blocksize * data->blocks,
+ ARCH_DMA_MINALIGN));
+}
+
+static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
+{
+ struct hsmmc *mmc_base;
+ struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+ u32 val;
+
+ mmc_base = priv->base_addr;
+
+ val = readl(&mmc_base->con);
+ val &= ~DMA_MASTER;
+ writel(val, &mmc_base->con);
+
+ val = readl(&mmc_base->hctl);
+ val &= ~DMA_SELECT;
+ writel(val, &mmc_base->hctl);
+
+ kfree(priv->adma_desc_table);
+}
+#else
+#define omap_hsmmc_adma_desc
+#define omap_hsmmc_prepare_adma_table
+#define omap_hsmmc_prepare_data
+#define omap_hsmmc_dma_cleanup
+#endif
+
#if !CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
struct mmc_data *data)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
+#ifndef CONFIG_OMAP34XX
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = upriv->mmc;
+#endif
#endif
struct hsmmc *mmc_base;
unsigned int flags, mmc_stat;
ulong start;
mmc_base = priv->base_addr;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0;
+
start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
/* enable default flags */
flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
- MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
+ MSBS_SGLEBLK);
+ flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
if (cmd->resp_type & MMC_RSP_CRC)
flags |= CCCE_CHECK;
if (data) {
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
- flags |= (MSBS_MULTIBLK | BCE_ENABLE);
+ flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
data->blocksize = 512;
writel(data->blocksize | (data->blocks << 16),
&mmc_base->blk);
flags |= (DP_DATA | DDIR_READ);
else
flags |= (DP_DATA | DDIR_WRITE);
+
+#ifndef CONFIG_OMAP34XX
+ if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
+ !mmc_is_tuning_cmd(cmd->cmdidx)) {
+ omap_hsmmc_prepare_data(mmc, data);
+ flags |= DE_ENABLE;
+ }
+#endif
}
writel(cmd->cmdarg, &mmc_base->arg);
start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
+ if (get_timer(start) > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return -ETIMEDOUT;
}
}
}
+#ifndef CONFIG_OMAP34XX
+ if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
+ !mmc_is_tuning_cmd(cmd->cmdidx)) {
+ u32 sz_mb, timeout;
+
+ if (mmc_stat & IE_ADMAE) {
+ omap_hsmmc_dma_cleanup(mmc);
+ return -EIO;
+ }
+
+ sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
+ timeout = sz_mb * DMA_TIMEOUT_PER_MB;
+ if (timeout < MAX_RETRY_MS)
+ timeout = MAX_RETRY_MS;
+
+ start = get_timer(0);
+ do {
+ mmc_stat = readl(&mmc_base->stat);
+ if (mmc_stat & TC_MASK) {
+ writel(readl(&mmc_base->stat) | TC_MASK,
+ &mmc_base->stat);
+ break;
+ }
+ if (get_timer(start) > timeout) {
+ printf("%s : DMA timeout: No status update\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ } while (1);
+
+ omap_hsmmc_dma_cleanup(mmc);
+ return 0;
+ }
+#endif
+
if (data && (data->flags & MMC_DATA_READ)) {
mmc_read_data(mmc_base, data->dest,
data->blocksize * data->blocks);
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
- (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ (ICE_STOP | DTO_15THDTO));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
- struct omap2_mmc_platform_config *data =
- (struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
plat->base_addr = map_physmem(devfdt_get_addr(dev),
sizeof(struct hsmmc *),
- MAP_NOCACHE) + data->reg_offset;
+ MAP_NOCACHE);
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
- .reg_offset = 0,
-};
-
-static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
- .reg_offset = 0x100,
-};
-
-static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
- .reg_offset = 0x100,
-};
-
static const struct udevice_id omap_hsmmc_ids[] = {
- {
- .compatible = "ti,omap3-hsmmc",
- .data = (ulong)&omap3_mmc_pdata
- },
- {
- .compatible = "ti,omap4-hsmmc",
- .data = (ulong)&omap4_mmc_pdata
- },
- {
- .compatible = "ti,am33xx-hsmmc",
- .data = (ulong)&am33xx_mmc_pdata
- },
+ { .compatible = "ti,omap3-hsmmc" },
+ { .compatible = "ti,omap4-hsmmc" },
+ { .compatible = "ti,am33xx-hsmmc" },
{ }
};
#endif
#include <common.h>
#include <dm.h>
+#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
#define SDHCI_CDNS_HRS04_ACK BIT(26)
#define SDHCI_CDNS_HRS04_RD BIT(25)
#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
-#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
-#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
+#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
+#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
+#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
-#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
-#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
-#define SDHCI_CDNS_HRS06_MODE_MASK 0x7
+#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
+#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
#define SDHCI_CDNS_HRS06_MODE_SD 0x0
#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
+/*
+ * The tuned val register is 6 bit-wide, but not the whole of the range is
+ * available. The range 0-42 seems to be available (then 43 wraps around to 0)
+ * but I am not quite sure if it is official. Use only 0 to 39 for safety.
+ */
+#define SDHCI_CDNS_MAX_TUNING_LOOP 40
+
struct sdhci_cdns_plat {
struct mmc_config cfg;
struct mmc mmc;
u32 tmp;
int ret;
- tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
- (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
+ tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
+ FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
writel(tmp, reg);
tmp |= SDHCI_CDNS_HRS04_WR;
* The mode should be decided by MMC_TIMING_* like Linux, but
* U-Boot does not support timing. Use the clock frequency instead.
*/
- if (clock <= 26000000)
+ if (clock <= 26000000) {
mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
- else if (clock <= 52000000) {
+ } else if (clock <= 52000000) {
if (mmc->ddr_mode)
mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
else
mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
} else {
- /*
- * REVISIT:
- * The IP supports HS200/HS400, revisit once U-Boot support it
- */
- printf("unsupported frequency %d\n", clock);
- return;
+ if (mmc->ddr_mode)
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
+ else
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
}
tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
- tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
- tmp |= mode;
+ tmp &= ~SDHCI_CDNS_HRS06_MODE;
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
}
.set_control_reg = sdhci_cdns_set_control_reg,
};
+static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
+ unsigned int val)
+{
+ void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
+ u32 tmp;
+
+ if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
+ return -EINVAL;
+
+ tmp = readl(reg);
+ tmp &= ~SDHCI_CDNS_HRS06_TUNE;
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
+ tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
+ writel(tmp, reg);
+
+ return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
+ 1);
+}
+
+static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
+ unsigned int opcode)
+{
+ struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct mmc *mmc = &plat->mmc;
+ int cur_streak = 0;
+ int max_streak = 0;
+ int end_of_streak = 0;
+ int i;
+
+ /*
+ * This handler only implements the eMMC tuning that is specific to
+ * this controller. The tuning for SD timing should be handled by the
+ * SDHCI core.
+ */
+ if (!IS_MMC(mmc))
+ return -ENOTSUPP;
+
+ if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ return -EINVAL;
+
+ for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
+ if (sdhci_cdns_set_tune_val(plat, i) ||
+ mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
+ cur_streak = 0;
+ } else { /* good */
+ cur_streak++;
+ if (cur_streak > max_streak) {
+ max_streak = cur_streak;
+ end_of_streak = i;
+ }
+ }
+ }
+
+ if (!max_streak) {
+ dev_err(dev, "no tuning point found\n");
+ return -EIO;
+ }
+
+ return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
+}
+
+static struct dm_mmc_ops sdhci_cdns_mmc_ops;
+
static int sdhci_cdns_bind(struct udevice *dev)
{
struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
+ sdhci_cdns_mmc_ops = sdhci_ops;
+#ifdef MMC_SUPPORTS_TUNING
+ sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
+#endif
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
if (ret)
.probe = sdhci_cdns_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
- .ops = &sdhci_ops,
+ .ops = &sdhci_cdns_mmc_ops,
};
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- printf("%s: Error detected in status(0x%X)!\n",
- __func__, stat);
+ pr_debug("%s: Error detected in status(0x%X)!\n",
+ __func__, stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
cfg->voltages |= host->voltages;
- cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
/* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
+#else
+int cfi_flash_num_flash_banks;
#endif
#ifdef CONFIG_CFI_FLASH /* for driver model */
/*-----------------------------------------------------------------------
*/
-#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
+ (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base)
{
int i;
* create an address based on the offset and the port width
*/
static inline void *
-flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
+flash_map(flash_info_t *info, flash_sect_t sect, uint offset)
{
unsigned int byte_offset = offset * info->portwidth;
}
static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
- unsigned int offset, void *addr)
+ unsigned int offset, void *addr)
{
}
uchar val;
uchar *cp = (uchar *) cmdbuf;
- for (i = info->portwidth; i > 0; i--){
- cword_offset = (info->portwidth-i)%info->chipwidth;
+ for (i = info->portwidth; i > 0; i--) {
+ cword_offset = (info->portwidth - i) % info->chipwidth;
#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
cp_offset = info->portwidth - i;
- val = *((uchar*)&cmd_le + cword_offset);
+ val = *((uchar *)&cmd_le + cword_offset);
#else
cp_offset = i - 1;
- val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
+ val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1);
#endif
cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
}
/*-----------------------------------------------------------------------
* Debug support
*/
-static void print_longlong (char *str, unsigned long long data)
+static void print_longlong(char *str, unsigned long long data)
{
int i;
char *cp;
- cp = (char *) &data;
+ cp = (char *)&data;
for (i = 0; i < 8; i++)
- sprintf (&str[i * 2], "%2.2x", *cp++);
+ sprintf(&str[i * 2], "%2.2x", *cp++);
}
-static void flash_printqry (struct cfi_qry *qry)
+static void flash_printqry(struct cfi_qry *qry)
{
u8 *p = (u8 *)qry;
int x, y;
debug(" ");
for (y = 0; y < 16; y++) {
unsigned char c = p[x + y];
+
if (c >= 0x20 && c <= 0x7e)
debug("%c", c);
else
}
#endif
-
/*-----------------------------------------------------------------------
* read a character at a port width address
*/
-static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
+static inline uchar flash_read_uchar(flash_info_t *info, uint offset)
{
uchar *cp;
uchar retval;
- cp = flash_map (info, 0, offset);
+ cp = flash_map(info, 0, offset);
#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
retval = flash_read8(cp);
#else
retval = flash_read8(cp + info->portwidth - 1);
#endif
- flash_unmap (info, 0, offset, cp);
+ flash_unmap(info, 0, offset, cp);
return retval;
}
/*-----------------------------------------------------------------------
* read a word at a port width address, assume 16bit bus
*/
-static inline ushort flash_read_word (flash_info_t * info, uint offset)
+static inline ushort flash_read_word(flash_info_t *info, uint offset)
{
ushort *addr, retval;
- addr = flash_map (info, 0, offset);
- retval = flash_read16 (addr);
- flash_unmap (info, 0, offset, addr);
+ addr = flash_map(info, 0, offset);
+ retval = flash_read16(addr);
+ flash_unmap(info, 0, offset, addr);
return retval;
}
-
/*-----------------------------------------------------------------------
* read a long word by picking the least significant byte of each maximum
* port size word. Swap for ppc format.
*/
-static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
+static ulong flash_read_long (flash_info_t *info, flash_sect_t sect,
uint offset)
{
uchar *addr;
#ifdef DEBUG
int x;
#endif
- addr = flash_map (info, sect, offset);
+ addr = flash_map(info, sect, offset);
#ifdef DEBUG
- debug ("long addr is at %p info->portwidth = %d\n", addr,
- info->portwidth);
- for (x = 0; x < 4 * info->portwidth; x++) {
- debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
- }
+ debug("long addr is at %p info->portwidth = %d\n", addr,
+ info->portwidth);
+ for (x = 0; x < 4 * info->portwidth; x++)
+ debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
#endif
#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
retval = ((flash_read8(addr) << 16) |
static void flash_write_cmd(flash_info_t *info, flash_sect_t sect,
uint offset, u32 cmd)
{
-
void *addr;
cfiword_t cword;
- addr = flash_map (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
+ addr = flash_map(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
- debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
- cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
+ cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
flash_write8(cword.w8, addr);
break;
case FLASH_CFI_16BIT:
- debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
- cmd, cword.w16,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
+ cmd, cword.w16,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
flash_write16(cword.w16, addr);
break;
case FLASH_CFI_32BIT:
- debug ("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr,
- cmd, cword.w32,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr,
+ cmd, cword.w32,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
flash_write32(cword.w32, addr);
break;
case FLASH_CFI_64BIT:
{
char str[20];
- print_longlong (str, cword.w64);
+ print_longlong(str, cword.w64);
- debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
- addr, cmd, str,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
+ addr, cmd, str,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
}
#endif
flash_write64(cword.w64, addr);
flash_unmap(info, sect, offset, addr);
}
-static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
+static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect)
{
- flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
- flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
+ flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
+ flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
}
/*-----------------------------------------------------------------------
*/
-static int flash_isequal (flash_info_t * info, flash_sect_t sect,
- uint offset, uchar cmd)
+static int flash_isequal(flash_info_t *info, flash_sect_t sect, uint offset,
+ uchar cmd)
{
void *addr;
cfiword_t cword;
int retval;
- addr = flash_map (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
+ addr = flash_map(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
- debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
+ debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
- debug ("is= %x %x\n", flash_read8(addr), cword.w8);
+ debug("is= %x %x\n", flash_read8(addr), cword.w8);
retval = (flash_read8(addr) == cword.w8);
break;
case FLASH_CFI_16BIT:
- debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16);
+ debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16);
retval = (flash_read16(addr) == cword.w16);
break;
case FLASH_CFI_32BIT:
- debug ("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32);
+ debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32);
retval = (flash_read32(addr) == cword.w32);
break;
case FLASH_CFI_64BIT:
char str1[20];
char str2[20];
- print_longlong (str1, flash_read64(addr));
- print_longlong (str2, cword.w64);
- debug ("is= %s %s\n", str1, str2);
+ print_longlong(str1, flash_read64(addr));
+ print_longlong(str2, cword.w64);
+ debug("is= %s %s\n", str1, str2);
}
#endif
retval = (flash_read64(addr) == cword.w64);
/*-----------------------------------------------------------------------
*/
-static int flash_isset (flash_info_t * info, flash_sect_t sect,
- uint offset, uchar cmd)
+static int flash_isset(flash_info_t *info, flash_sect_t sect, uint offset,
+ uchar cmd)
{
void *addr;
cfiword_t cword;
int retval;
- addr = flash_map (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
+ addr = flash_map(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
retval = ((flash_read8(addr) & cword.w8) == cword.w8);
/*-----------------------------------------------------------------------
*/
-static int flash_toggle (flash_info_t * info, flash_sect_t sect,
- uint offset, uchar cmd)
+static int flash_toggle(flash_info_t *info, flash_sect_t sect, uint offset,
+ uchar cmd)
{
- void *addr;
+ u8 *addr;
cfiword_t cword;
int retval;
- addr = flash_map (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
+ addr = flash_map(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
retval = flash_read8(addr) != flash_read8(addr);
retval = flash_read32(addr) != flash_read32(addr);
break;
case FLASH_CFI_64BIT:
- retval = ( (flash_read32( addr ) != flash_read32( addr )) ||
- (flash_read32(addr+4) != flash_read32(addr+4)) );
+ retval = ((flash_read32(addr) != flash_read32(addr)) ||
+ (flash_read32(addr + 4) != flash_read32(addr + 4)));
break;
default:
retval = 0;
* This routine checks the status of the chip and returns true if the
* chip is busy.
*/
-static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
+static int flash_is_busy(flash_info_t *info, flash_sect_t sect)
{
int retval;
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
- retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
+ retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE);
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_LEGACY:
#endif
if (info->sr_supported) {
- flash_write_cmd (info, sect, info->addr_unlock1,
- FLASH_CMD_READ_STATUS);
- retval = !flash_isset (info, sect, 0,
- FLASH_STATUS_DONE);
+ flash_write_cmd(info, sect, info->addr_unlock1,
+ FLASH_CMD_READ_STATUS);
+ retval = !flash_isset(info, sect, 0,
+ FLASH_STATUS_DONE);
} else {
- retval = flash_toggle (info, sect, 0,
- AMD_STATUS_TOGGLE);
+ retval = flash_toggle(info, sect, 0,
+ AMD_STATUS_TOGGLE);
}
break;
default:
retval = 0;
}
- debug ("flash_is_busy: %d\n", retval);
+ debug("%s: %d\n", __func__, retval);
return retval;
}
* wait for XSR.7 to be set. Time out with an error if it does not.
* This routine does not set the flash to read-array mode.
*/
-static int flash_status_check (flash_info_t * info, flash_sect_t sector,
- ulong tout, char *prompt)
+static int flash_status_check(flash_info_t *info, flash_sect_t sector,
+ ulong tout, char *prompt)
{
ulong start;
#if CONFIG_SYS_HZ != 1000
+ /* Avoid overflow for large HZ */
if ((ulong)CONFIG_SYS_HZ > 100000)
- tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
+ tout *= (ulong)CONFIG_SYS_HZ / 1000;
else
tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
#endif
#ifdef CONFIG_SYS_LOW_RES_TIMER
reset_timer();
#endif
- start = get_timer (0);
+ start = get_timer(0);
WATCHDOG_RESET();
- while (flash_is_busy (info, sector)) {
- if (get_timer (start) > tout) {
- printf ("Flash %s timeout at address %lx data %lx\n",
- prompt, info->start[sector],
- flash_read_long (info, sector, 0));
- flash_write_cmd (info, sector, 0, info->cmd_reset);
+ while (flash_is_busy(info, sector)) {
+ if (get_timer(start) > tout) {
+ printf("Flash %s timeout at address %lx data %lx\n",
+ prompt, info->start[sector],
+ flash_read_long(info, sector, 0));
+ flash_write_cmd(info, sector, 0, info->cmd_reset);
udelay(1);
- return ERR_TIMOUT;
+ return ERR_TIMEOUT;
}
- udelay (1); /* also triggers watchdog */
+ udelay(1); /* also triggers watchdog */
}
return ERR_OK;
}
*
* This routine sets the flash to read-array mode.
*/
-static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
- ulong tout, char *prompt)
+static int flash_full_status_check(flash_info_t *info, flash_sect_t sector,
+ ulong tout, char *prompt)
{
int retcode;
- retcode = flash_status_check (info, sector, tout, prompt);
+ retcode = flash_status_check(info, sector, tout, prompt);
switch (info->vendor) {
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
- if ((retcode == ERR_OK)
- && !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+ if (retcode == ERR_OK &&
+ !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
- printf ("Flash %s error at address %lx\n", prompt,
- info->start[sector]);
- if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
+ printf("Flash %s error at address %lx\n", prompt,
+ info->start[sector]);
+ if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS |
FLASH_STATUS_PSLBS)) {
- puts ("Command Sequence Error.\n");
- } else if (flash_isset (info, sector, 0,
+ puts("Command Sequence Error.\n");
+ } else if (flash_isset(info, sector, 0,
FLASH_STATUS_ECLBS)) {
- puts ("Block Erase Error.\n");
+ puts("Block Erase Error.\n");
retcode = ERR_NOT_ERASED;
- } else if (flash_isset (info, sector, 0,
+ } else if (flash_isset(info, sector, 0,
FLASH_STATUS_PSLBS)) {
- puts ("Locking Error\n");
+ puts("Locking Error\n");
}
- if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
- puts ("Block locked.\n");
+ if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
+ puts("Block locked.\n");
retcode = ERR_PROTECTED;
}
- if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
- puts ("Vpp Low Error.\n");
+ if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+ puts("Vpp Low Error.\n");
}
- flash_write_cmd (info, sector, 0, info->cmd_reset);
+ flash_write_cmd(info, sector, 0, info->cmd_reset);
udelay(1);
break;
default:
int ready;
#if CONFIG_SYS_HZ != 1000
+ /* Avoid overflow for large HZ */
if ((ulong)CONFIG_SYS_HZ > 100000)
- tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
+ tout *= (ulong)CONFIG_SYS_HZ / 1000;
else
tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
#endif
if (get_timer(start) > tout) {
printf("Flash %s timeout at address %lx data %lx\n",
prompt, (ulong)dst, (ulong)flash_read8(dst));
- return ERR_TIMOUT;
+ return ERR_TIMEOUT;
}
udelay(1); /* also triggers watchdog */
}
/*-----------------------------------------------------------------------
*/
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
{
#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
unsigned short w;
* Loop through the sector table starting from the previously found sector.
* Searches forwards or backwards, dependent on the passed address.
*/
-static flash_sect_t find_sector (flash_info_t * info, ulong addr)
+static flash_sect_t find_sector(flash_info_t *info, ulong addr)
{
static flash_sect_t saved_sector; /* previously found sector */
static flash_info_t *saved_info; /* previously used flash bank */
flash_sect_t sector = saved_sector;
- if ((info != saved_info) || (sector >= info->sector_count))
+ if (info != saved_info || sector >= info->sector_count)
sector = 0;
- while ((info->start[sector] < addr)
- && (sector < info->sector_count - 1))
+ while ((sector < info->sector_count - 1) &&
+ (info->start[sector] < addr))
sector++;
while ((info->start[sector] > addr) && (sector > 0))
/*
/*-----------------------------------------------------------------------
*/
-static int flash_write_cfiword (flash_info_t * info, ulong dest,
- cfiword_t cword)
+static int flash_write_cfiword(flash_info_t *info, ulong dest, cfiword_t cword)
{
void *dstaddr = (void *)dest;
int flag;
return ERR_NOT_ERASED;
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ flag = disable_interrupts();
switch (info->vendor) {
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
- flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
break;
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
sect = find_sector(info, dest);
- flash_unlock_seq (info, sect);
- flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
+ flash_unlock_seq(info, sect);
+ flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE);
sect_found = 1;
break;
#ifdef CONFIG_FLASH_CFI_LEGACY
case CFI_CMDSET_AMD_LEGACY:
sect = find_sector(info, dest);
- flash_unlock_seq (info, 0);
- flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE);
sect_found = 1;
break;
#endif
/* re-enable interrupts if necessary */
if (flag)
- enable_interrupts ();
+ enable_interrupts();
if (!sect_found)
- sect = find_sector (info, dest);
+ sect = find_sector(info, dest);
if (use_flash_status_poll(info))
return flash_status_poll(info, &cword, dstaddr,
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
- int len)
+static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp,
+ int len)
{
flash_sect_t sector;
int cnt;
int retcode;
- void *src = cp;
- void *dst = (void *)dest;
- void *dst2 = dst;
+ u8 *src = cp;
+ u8 *dst = (u8 *)dest;
+ u8 *dst2 = dst;
int flag = 1;
uint offset = 0;
unsigned int shift;
}
src = cp;
- sector = find_sector (info, dest);
+ sector = find_sector(info, dest);
switch (info->vendor) {
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
- FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS);
- flash_write_cmd (info, sector, 0, write_cmd);
- retcode = flash_status_check (info, sector,
- info->buffer_write_tout,
- "write to buffer");
+ FLASH_CMD_WRITE_BUFFER_PROG :
+ FLASH_CMD_WRITE_TO_BUFFER;
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
+ flash_write_cmd(info, sector, 0, write_cmd);
+ retcode = flash_status_check(info, sector,
+ info->buffer_write_tout,
+ "write to buffer");
if (retcode == ERR_OK) {
/* reduce the number of loops by the width of
- * the port */
+ * the port
+ */
cnt = len >> shift;
- flash_write_cmd (info, sector, 0, cnt - 1);
+ flash_write_cmd(info, sector, 0, cnt - 1);
while (cnt-- > 0) {
switch (info->portwidth) {
case FLASH_CFI_8BIT:
goto out_unmap;
}
}
- flash_write_cmd (info, sector, 0,
- FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check (
+ flash_write_cmd(info, sector, 0,
+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode = flash_full_status_check(
info, sector, info->buffer_write_tout,
"buffer write");
}
goto out_unmap;
}
- flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
+ flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
if (use_flash_status_poll(info))
retcode = flash_status_poll(info, src - (1 << shift),
dst - (1 << shift),
break;
default:
- debug ("Unknown Command Set\n");
+ debug("Unknown Command Set\n");
retcode = ERR_INVAL;
break;
}
}
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-
/*-----------------------------------------------------------------------
*/
-int flash_erase (flash_info_t * info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
{
int rcode = 0;
int prot;
int st;
if (info->flash_id != FLASH_MAN_CFI) {
- puts ("Can't erase unknown flash type - aborted\n");
+ puts("Can't erase unknown flash type - aborted\n");
return 1;
}
- if ((s_first < 0) || (s_first > s_last)) {
- puts ("- no sectors to erase\n");
+ if (s_first < 0 || s_first > s_last) {
+ puts("- no sectors to erase\n");
return 1;
}
prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
+ for (sect = s_first; sect <= s_last; ++sect)
+ if (info->protect[sect])
prot++;
- }
- }
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
} else if (flash_verbose) {
- putc ('\n');
+ putc('\n');
}
-
for (sect = s_first; sect <= s_last; sect++) {
if (ctrlc()) {
printf("\n");
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_ERASE_CONFIRM);
+ flash_write_cmd(info, sect, 0,
+ FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sect, 0,
+ FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd(info, sect, 0,
+ FLASH_CMD_ERASE_CONFIRM);
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
- flash_unlock_seq (info, sect);
- flash_write_cmd (info, sect,
+ flash_unlock_seq(info, sect);
+ flash_write_cmd(info, sect,
info->addr_unlock1,
AMD_CMD_ERASE_START);
- flash_unlock_seq (info, sect);
- flash_write_cmd (info, sect, 0,
- info->cmd_erase_sector);
+ flash_unlock_seq(info, sect);
+ flash_write_cmd(info, sect, 0,
+ info->cmd_erase_sector);
break;
#ifdef CONFIG_FLASH_CFI_LEGACY
case CFI_CMDSET_AMD_LEGACY:
- flash_unlock_seq (info, 0);
- flash_write_cmd (info, 0, info->addr_unlock1,
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0, info->addr_unlock1,
AMD_CMD_ERASE_START);
- flash_unlock_seq (info, 0);
- flash_write_cmd (info, sect, 0,
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, sect, 0,
AMD_CMD_ERASE_SECTOR);
break;
#endif
default:
- debug ("Unkown flash vendor %d\n",
- info->vendor);
+ debug("Unknown flash vendor %d\n",
+ info->vendor);
break;
}
if (use_flash_status_poll(info)) {
cfiword_t cword;
void *dest;
+
cword.w64 = 0xffffffffffffffffULL;
dest = flash_map(info, sect, 0);
st = flash_status_poll(info, &cword, dest,
- info->erase_blk_tout, "erase");
+ info->erase_blk_tout,
+ "erase");
flash_unmap(info, sect, 0, dest);
- } else
+ } else {
st = flash_full_status_check(info, sect,
info->erase_blk_tout,
"erase");
+ }
+
if (st)
rcode = 1;
else if (flash_verbose)
- putc ('.');
+ putc('.');
}
}
if (flash_verbose)
- puts (" done\n");
+ puts(" done\n");
return rcode;
}
}
#endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
-void flash_print_info (flash_info_t * info)
+void flash_print_info(flash_info_t *info)
{
int i;
if (info->flash_id != FLASH_MAN_CFI) {
- puts ("missing or unknown FLASH type\n");
+ puts("missing or unknown FLASH type\n");
return;
}
- printf ("%s flash (%d x %d)",
- info->name,
- (info->portwidth << 3), (info->chipwidth << 3));
- if (info->size < 1024*1024)
- printf (" Size: %ld kB in %d Sectors\n",
- info->size >> 10, info->sector_count);
+ printf("%s flash (%d x %d)",
+ info->name,
+ (info->portwidth << 3), (info->chipwidth << 3));
+ if (info->size < 1024 * 1024)
+ printf(" Size: %ld kB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
else
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf (" ");
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf(" ");
switch (info->vendor) {
- case CFI_CMDSET_INTEL_PROG_REGIONS:
- printf ("Intel Prog Regions");
- break;
- case CFI_CMDSET_INTEL_STANDARD:
- printf ("Intel Standard");
- break;
- case CFI_CMDSET_INTEL_EXTENDED:
- printf ("Intel Extended");
- break;
- case CFI_CMDSET_AMD_STANDARD:
- printf ("AMD Standard");
- break;
- case CFI_CMDSET_AMD_EXTENDED:
- printf ("AMD Extended");
- break;
+ case CFI_CMDSET_INTEL_PROG_REGIONS:
+ printf("Intel Prog Regions");
+ break;
+ case CFI_CMDSET_INTEL_STANDARD:
+ printf("Intel Standard");
+ break;
+ case CFI_CMDSET_INTEL_EXTENDED:
+ printf("Intel Extended");
+ break;
+ case CFI_CMDSET_AMD_STANDARD:
+ printf("AMD Standard");
+ break;
+ case CFI_CMDSET_AMD_EXTENDED:
+ printf("AMD Extended");
+ break;
#ifdef CONFIG_FLASH_CFI_LEGACY
- case CFI_CMDSET_AMD_LEGACY:
- printf ("AMD Legacy");
- break;
+ case CFI_CMDSET_AMD_LEGACY:
+ printf("AMD Legacy");
+ break;
#endif
- default:
- printf ("Unknown (%d)", info->vendor);
- break;
+ default:
+ printf("Unknown (%d)", info->vendor);
+ break;
}
- printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
- info->manufacturer_id);
- printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
- info->device_id);
+ printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
+ info->manufacturer_id);
+ printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
+ info->device_id);
if ((info->device_id & 0xff) == 0x7E) {
printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
- info->device_id2);
+ info->device_id2);
}
- if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock))
+ if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock)
printf("\n Advanced Sector Protection (PPB) enabled");
- printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
- info->erase_blk_tout,
- info->write_tout);
+ printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
+ info->erase_blk_tout, info->write_tout);
if (info->buffer_size > 1) {
- printf (" Buffer write timeout: %ld ms, "
- "buffer size: %d bytes\n",
- info->buffer_write_tout,
- info->buffer_size);
+ printf(" Buffer write timeout: %ld ms, ",
+ info->buffer_write_tout);
+ printf("buffer size: %d bytes\n", info->buffer_size);
}
- puts ("\n Sector Start Addresses:");
+ puts("\n Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if (ctrlc())
break;
putc('\n');
#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
/* print empty and read-only info */
- printf (" %08lX %c %s ",
- info->start[i],
- sector_erased(info, i) ? 'E' : ' ',
- info->protect[i] ? "RO" : " ");
+ printf(" %08lX %c %s ",
+ info->start[i],
+ sector_erased(info, i) ? 'E' : ' ',
+ info->protect[i] ? "RO" : " ");
#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
- printf (" %08lX %s ",
- info->start[i],
- info->protect[i] ? "RO" : " ");
+ printf(" %08lX %s ",
+ info->start[i],
+ info->protect[i] ? "RO" : " ");
#endif
}
- putc ('\n');
- return;
+ putc('\n');
}
/*-----------------------------------------------------------------------
#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
if (flash_verbose) { \
dots -= dots_sub; \
- if ((scale > 0) && (dots <= 0)) { \
+ if (scale > 0 && dots <= 0) { \
if ((digit % 5) == 0) \
- printf ("%d", digit / 5); \
+ printf("%d", digit / 5); \
else \
- putc ('.'); \
+ putc('.'); \
digit--; \
dots += scale; \
} \
* 1 - write timeout
* 2 - Flash not erased
*/
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong wp;
uchar *p;
wp = (addr & ~(info->portwidth - 1));
/* handle unaligned start */
- if ((aln = addr - wp) != 0) {
+ aln = addr - wp;
+ if (aln != 0) {
cword.w32 = 0;
p = (uchar *)wp;
for (i = 0; i < aln; ++i)
- flash_add_byte (info, &cword, flash_read8(p + i));
+ flash_add_byte(info, &cword, flash_read8(p + i));
for (; (i < info->portwidth) && (cnt > 0); i++) {
- flash_add_byte (info, &cword, *src++);
+ flash_add_byte(info, &cword, *src++);
cnt--;
}
for (; (cnt == 0) && (i < info->portwidth); ++i)
- flash_add_byte (info, &cword, flash_read8(p + i));
+ flash_add_byte(info, &cword, flash_read8(p + i));
- rc = flash_write_cfiword (info, wp, cword);
+ rc = flash_write_cfiword(info, wp, cword);
if (rc != 0)
return rc;
if (info->buffer_size == 1) {
cword.w32 = 0;
for (i = 0; i < info->portwidth; i++)
- flash_add_byte (info, &cword, *src++);
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+ flash_add_byte(info, &cword, *src++);
+ rc = flash_write_cfiword(info, wp, cword);
+ if (rc != 0)
return rc;
wp += info->portwidth;
cnt -= info->portwidth;
i = buffered_size - (wp % buffered_size);
if (i > cnt)
i = cnt;
- if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
+ rc = flash_write_cfibuffer(info, wp, src, i);
+ if (rc != ERR_OK)
return rc;
i -= i & (info->portwidth - 1);
wp += i;
#else
while (cnt >= info->portwidth) {
cword.w32 = 0;
- for (i = 0; i < info->portwidth; i++) {
- flash_add_byte (info, &cword, *src++);
- }
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+ for (i = 0; i < info->portwidth; i++)
+ flash_add_byte(info, &cword, *src++);
+ rc = flash_write_cfiword(info, wp, cword);
+ if (rc != 0)
return rc;
wp += info->portwidth;
cnt -= info->portwidth;
}
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
+ if (cnt == 0)
return (0);
- }
/*
* handle unaligned tail bytes
cword.w32 = 0;
p = (uchar *)wp;
for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
- flash_add_byte (info, &cword, *src++);
+ flash_add_byte(info, &cword, *src++);
--cnt;
}
for (; i < info->portwidth; ++i)
- flash_add_byte (info, &cword, flash_read8(p + i));
+ flash_add_byte(info, &cword, flash_read8(p + i));
- return flash_write_cfiword (info, wp, cword);
+ return flash_write_cfiword(info, wp, cword);
}
static inline int manufact_match(flash_info_t *info, u32 manu)
static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
{
- if (manufact_match(info, INTEL_MANUFACT)
- && info->device_id == NUMONYX_256MBIT) {
+ if (manufact_match(info, INTEL_MANUFACT) &&
+ info->device_id == NUMONYX_256MBIT) {
/*
* see errata called
* "Numonyx Axcell P33/P30 Specification Update" :)
return 0;
}
-int flash_real_protect (flash_info_t * info, long sector, int prot)
+int flash_real_protect(flash_info_t *info, long sector, int prot)
{
int retcode = 0;
switch (info->vendor) {
- case CFI_CMDSET_INTEL_PROG_REGIONS:
- case CFI_CMDSET_INTEL_STANDARD:
- case CFI_CMDSET_INTEL_EXTENDED:
- if (!cfi_protect_bugfix(info, sector, prot)) {
- flash_write_cmd(info, sector, 0,
- FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0,
+ case CFI_CMDSET_INTEL_PROG_REGIONS:
+ case CFI_CMDSET_INTEL_STANDARD:
+ case CFI_CMDSET_INTEL_EXTENDED:
+ if (!cfi_protect_bugfix(info, sector, prot)) {
+ flash_write_cmd(info, sector, 0,
+ FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0,
FLASH_CMD_PROTECT);
- if (prot)
- flash_write_cmd(info, sector, 0,
+ if (prot)
+ flash_write_cmd(info, sector, 0,
FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0,
+ else
+ flash_write_cmd(info, sector, 0,
FLASH_CMD_PROTECT_CLEAR);
-
- }
- break;
- case CFI_CMDSET_AMD_EXTENDED:
- case CFI_CMDSET_AMD_STANDARD:
- /* U-Boot only checks the first byte */
- if (manufact_match(info, ATM_MANUFACT)) {
- if (prot) {
- flash_unlock_seq (info, 0);
- flash_write_cmd (info, 0,
- info->addr_unlock1,
- ATM_CMD_SOFTLOCK_START);
- flash_unlock_seq (info, 0);
- flash_write_cmd (info, sector, 0,
- ATM_CMD_LOCK_SECT);
- } else {
- flash_write_cmd (info, 0,
- info->addr_unlock1,
- AMD_CMD_UNLOCK_START);
- if (info->device_id == ATM_ID_BV6416)
- flash_write_cmd (info, sector,
+ }
+ break;
+ case CFI_CMDSET_AMD_EXTENDED:
+ case CFI_CMDSET_AMD_STANDARD:
+ /* U-Boot only checks the first byte */
+ if (manufact_match(info, ATM_MANUFACT)) {
+ if (prot) {
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0,
+ info->addr_unlock1,
+ ATM_CMD_SOFTLOCK_START);
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, sector, 0,
+ ATM_CMD_LOCK_SECT);
+ } else {
+ flash_write_cmd(info, 0,
+ info->addr_unlock1,
+ AMD_CMD_UNLOCK_START);
+ if (info->device_id == ATM_ID_BV6416)
+ flash_write_cmd(info, sector,
0, ATM_CMD_UNLOCK_SECT);
- }
}
- if (info->legacy_unlock) {
- int flag = disable_interrupts();
- int lock_flag;
-
- flash_unlock_seq(info, 0);
- flash_write_cmd(info, 0, info->addr_unlock1,
- AMD_CMD_SET_PPB_ENTRY);
- lock_flag = flash_isset(info, sector, 0, 0x01);
- if (prot) {
- if (lock_flag) {
- flash_write_cmd(info, sector, 0,
+ }
+ if (info->legacy_unlock) {
+ int flag = disable_interrupts();
+ int lock_flag;
+
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0, info->addr_unlock1,
+ AMD_CMD_SET_PPB_ENTRY);
+ lock_flag = flash_isset(info, sector, 0, 0x01);
+ if (prot) {
+ if (lock_flag) {
+ flash_write_cmd(info, sector, 0,
AMD_CMD_PPB_LOCK_BC1);
- flash_write_cmd(info, sector, 0,
+ flash_write_cmd(info, sector, 0,
AMD_CMD_PPB_LOCK_BC2);
- }
- debug("sector %ld %slocked\n", sector,
- lock_flag ? "" : "already ");
- } else {
- if (!lock_flag) {
- debug("unlock %ld\n", sector);
- flash_write_cmd(info, 0, 0,
+ }
+ debug("sector %ld %slocked\n", sector,
+ lock_flag ? "" : "already ");
+ } else {
+ if (!lock_flag) {
+ debug("unlock %ld\n", sector);
+ flash_write_cmd(info, 0, 0,
AMD_CMD_PPB_UNLOCK_BC1);
- flash_write_cmd(info, 0, 0,
+ flash_write_cmd(info, 0, 0,
AMD_CMD_PPB_UNLOCK_BC2);
- }
- debug("sector %ld %sunlocked\n", sector,
- !lock_flag ? "" : "already ");
}
- if (flag)
- enable_interrupts();
-
- if (flash_status_check(info, sector,
- info->erase_blk_tout,
- prot ? "protect" : "unprotect"))
- printf("status check error\n");
-
- flash_write_cmd(info, 0, 0,
- AMD_CMD_SET_PPB_EXIT_BC1);
- flash_write_cmd(info, 0, 0,
- AMD_CMD_SET_PPB_EXIT_BC2);
+ debug("sector %ld %sunlocked\n", sector,
+ !lock_flag ? "" : "already ");
}
- break;
+ if (flag)
+ enable_interrupts();
+
+ if (flash_status_check(info, sector,
+ info->erase_blk_tout,
+ prot ? "protect" : "unprotect"))
+ printf("status check error\n");
+
+ flash_write_cmd(info, 0, 0,
+ AMD_CMD_SET_PPB_EXIT_BC1);
+ flash_write_cmd(info, 0, 0,
+ AMD_CMD_SET_PPB_EXIT_BC2);
+ }
+ break;
#ifdef CONFIG_FLASH_CFI_LEGACY
- case CFI_CMDSET_AMD_LEGACY:
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
- if (prot)
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+ case CFI_CMDSET_AMD_LEGACY:
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+ if (prot)
+ flash_write_cmd(info, sector, 0,
+ FLASH_CMD_PROTECT_SET);
+ else
+ flash_write_cmd(info, sector, 0,
+ FLASH_CMD_PROTECT_CLEAR);
#endif
};
* flash_full_status_check() to work correctly
*/
flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
- if ((retcode =
- flash_full_status_check (info, sector, info->erase_blk_tout,
- prot ? "protect" : "unprotect")) == 0) {
-
+ retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+ prot ? "protect" : "unprotect");
+ if (retcode == 0) {
info->protect[sector] = prot;
/*
* On some of Intel's flash chips (marked via legacy_unlock)
* unprotect unprotects all locking.
*/
- if ((prot == 0) && (info->legacy_unlock)) {
+ if (prot == 0 && info->legacy_unlock) {
flash_sect_t i;
for (i = 0; i < info->sector_count; i++) {
if (info->protect[i])
- flash_real_protect (info, i, 1);
+ flash_real_protect(info, i, 1);
}
}
}
/*-----------------------------------------------------------------------
* flash_read_user_serial - read the OneTimeProgramming cells
*/
-void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
- int len)
+void flash_read_user_serial(flash_info_t *info, void *buffer, int offset,
+ int len)
{
uchar *src;
uchar *dst;
dst = buffer;
- src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
- flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
- memcpy (dst, src + offset, len);
- flash_write_cmd (info, 0, 0, info->cmd_reset);
+ src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
+ memcpy(dst, src + offset, len);
+ flash_write_cmd(info, 0, 0, info->cmd_reset);
udelay(1);
flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
}
/*
* flash_read_factory_serial - read the device Id from the protection area
*/
-void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
- int len)
+void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset,
+ int len)
{
uchar *src;
- src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
- flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
- memcpy (buffer, src + offset, len);
- flash_write_cmd (info, 0, 0, info->cmd_reset);
+ src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
+ memcpy(buffer, src + offset, len);
+ flash_write_cmd(info, 0, 0, info->cmd_reset);
udelay(1);
flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
}
u32 tmp;
for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
- tmp = get_unaligned(&(qry->erase_region_info[i]));
- put_unaligned(get_unaligned(&(qry->erase_region_info[j])),
- &(qry->erase_region_info[i]));
- put_unaligned(tmp, &(qry->erase_region_info[j]));
+ tmp = get_unaligned(&qry->erase_region_info[i]);
+ put_unaligned(get_unaligned(&qry->erase_region_info[j]),
+ &qry->erase_region_info[i]);
+ put_unaligned(tmp, &qry->erase_region_info[j]);
}
}
udelay(1);
flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
udelay(1000); /* some flash are slow to respond */
- info->manufacturer_id = flash_read_uchar (info,
- FLASH_OFFSET_MANUFACTURER_ID);
+ info->manufacturer_id = flash_read_uchar(info,
+ FLASH_OFFSET_MANUFACTURER_ID);
info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
- flash_read_word (info, FLASH_OFFSET_DEVICE_ID) :
- flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID);
+ flash_read_word(info, FLASH_OFFSET_DEVICE_ID) :
+ flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID);
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
/* read legacy lock/unlock bit from intel flash */
if (info->ext_addr) {
- info->legacy_unlock = flash_read_uchar (info,
- info->ext_addr + 5) & 0x08;
+ info->legacy_unlock =
+ flash_read_uchar(info, info->ext_addr + 5) & 0x08;
}
#endif
static void cmdset_amd_read_jedec_ids(flash_info_t *info)
{
- ushort bankId = 0;
- uchar manuId;
+ ushort bank_id = 0;
+ uchar manu_id;
uchar feature;
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
udelay(1000); /* some flash are slow to respond */
- manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID);
+ manu_id = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID);
/* JEDEC JEP106Z specifies ID codes up to bank 7 */
- while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) {
- bankId += 0x100;
- manuId = flash_read_uchar (info,
- bankId | FLASH_OFFSET_MANUFACTURER_ID);
+ while (manu_id == FLASH_CONTINUATION_CODE && bank_id < 0x800) {
+ bank_id += 0x100;
+ manu_id = flash_read_uchar(info,
+ bank_id | FLASH_OFFSET_MANUFACTURER_ID);
}
- info->manufacturer_id = manuId;
+ info->manufacturer_id = manu_id;
debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n",
info->ext_addr, info->cfi_version);
info->sr_supported = feature & 0x1;
}
- switch (info->chipwidth){
+ switch (info->chipwidth) {
case FLASH_CFI_8BIT:
- info->device_id = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID);
+ info->device_id = flash_read_uchar(info,
+ FLASH_OFFSET_DEVICE_ID);
if (info->device_id == 0x7E) {
/* AMD 3-byte (expanded) device ids */
- info->device_id2 = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID2);
+ info->device_id2 = flash_read_uchar(info,
+ FLASH_OFFSET_DEVICE_ID2);
info->device_id2 <<= 8;
- info->device_id2 |= flash_read_uchar (info,
+ info->device_id2 |= flash_read_uchar(info,
FLASH_OFFSET_DEVICE_ID3);
}
break;
case FLASH_CFI_16BIT:
- info->device_id = flash_read_word (info,
- FLASH_OFFSET_DEVICE_ID);
+ info->device_id = flash_read_word(info,
+ FLASH_OFFSET_DEVICE_ID);
if ((info->device_id & 0xff) == 0x7E) {
/* AMD 3-byte (expanded) device ids */
- info->device_id2 = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID2);
+ info->device_id2 = flash_read_uchar(info,
+ FLASH_OFFSET_DEVICE_ID2);
info->device_id2 <<= 8;
- info->device_id2 |= flash_read_uchar (info,
+ info->device_id2 |= flash_read_uchar(info,
FLASH_OFFSET_DEVICE_ID3);
}
break;
}
#ifdef CONFIG_FLASH_CFI_LEGACY
-static void flash_read_jedec_ids (flash_info_t * info)
+static void flash_read_jedec_ids(flash_info_t *info)
{
info->manufacturer_id = 0;
info->device_id = 0;
if (board_flash_get_legacy(base, banknum, info)) {
/* board code may have filled info completely. If not, we
- use JEDEC ID probing. */
+ * use JEDEC ID probing.
+ */
if (!info->vendor) {
int modes[] = {
CFI_CMDSET_AMD_STANDARD,
(ulong)map_physmem(base,
info->portwidth,
MAP_NOCACHE);
- if (info->portwidth == FLASH_CFI_8BIT
- && info->interface == FLASH_CFI_X8X16) {
+ if (info->portwidth == FLASH_CFI_8BIT &&
+ info->interface == FLASH_CFI_X8X16) {
info->addr_unlock1 = 0x2AAA;
info->addr_unlock2 = 0x5555;
} else {
}
flash_read_jedec_ids(info);
debug("JEDEC PROBE: ID %x %x %x\n",
- info->manufacturer_id,
- info->device_id,
- info->device_id2);
+ info->manufacturer_id,
+ info->device_id,
+ info->device_id2);
if (jedec_flash_match(info, info->start[0]))
break;
- else
- unmap_physmem((void *)info->start[0],
- info->portwidth);
+
+ unmap_physmem((void *)info->start[0],
+ info->portwidth);
}
}
- switch(info->vendor) {
+ switch (info->vendor) {
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
* detect if flash is compatible with the Common Flash Interface (CFI)
* http://www.jedec.org/download/search/jesd68.pdf
*/
-static void flash_read_cfi (flash_info_t *info, void *buf,
- unsigned int start, size_t len)
+static void flash_read_cfi(flash_info_t *info, void *buf, unsigned int start,
+ size_t len)
{
u8 *p = buf;
unsigned int i;
udelay(1);
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}
+
void flash_cmd_reset(flash_info_t *info)
- __attribute__((weak,alias("__flash_cmd_reset")));
+ __attribute__((weak, alias("__flash_cmd_reset")));
-static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
+static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
{
int cfi_offset;
for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi);
cfi_offset++) {
- flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
- FLASH_CMD_CFI);
- if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
- && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
- && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
+ flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset],
+ FLASH_CMD_CFI);
+ if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
- sizeof(struct cfi_qry));
+ sizeof(struct cfi_qry));
info->interface = le16_to_cpu(qry->interface_desc);
info->cfi_offset = flash_offset_cfi[cfi_offset];
- debug ("device interface is %d\n",
- info->interface);
- debug ("found port %d chip %d ",
- info->portwidth, info->chipwidth);
- debug ("port %d bits chip %d bits\n",
- info->portwidth << CFI_FLASH_SHIFT_WIDTH,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ debug("device interface is %d\n",
+ info->interface);
+ debug("found port %d chip %d ",
+ info->portwidth, info->chipwidth);
+ debug("port %d bits chip %d bits\n",
+ info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
/* calculate command offsets as in the Linux driver */
info->addr_unlock1 = 0x555;
* modify the unlock address if we are
* in compatibility mode
*/
- if ( /* x8/x16 in x8 mode */
- ((info->chipwidth == FLASH_CFI_BY8) &&
- (info->interface == FLASH_CFI_X8X16)) ||
- /* x16/x32 in x16 mode */
- ((info->chipwidth == FLASH_CFI_BY16) &&
- (info->interface == FLASH_CFI_X16X32)))
- {
+ if (/* x8/x16 in x8 mode */
+ (info->chipwidth == FLASH_CFI_BY8 &&
+ info->interface == FLASH_CFI_X8X16) ||
+ /* x16/x32 in x16 mode */
+ (info->chipwidth == FLASH_CFI_BY16 &&
+ info->interface == FLASH_CFI_X16X32)) {
info->addr_unlock1 = 0xaaa;
info->addr_unlock2 = 0x555;
}
return 0;
}
-static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
+static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
{
- debug ("flash detect cfi\n");
+ debug("flash detect cfi\n");
for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
if (__flash_detect_cfi(info, qry))
return 1;
}
- debug ("not found\n");
+ debug("not found\n");
return 0;
}
if (info->device_id == 0x5D23 || /* SST39VF3201B */
info->device_id == 0x5C23) { /* SST39VF3202B */
/* set sector granularity to 4KB */
- info->cmd_erase_sector=0x50;
+ info->cmd_erase_sector = 0x50;
}
}
* There's an app note from Numonyx on this issue.
* So adjust the buffer size for M29EW while operating in 8-bit mode
*/
- if (((qry->max_buf_write_size) > 0x8) &&
- (info->device_id == 0x7E) &&
- (info->device_id2 == 0x2201 ||
- info->device_id2 == 0x2301 ||
- info->device_id2 == 0x2801 ||
- info->device_id2 == 0x4801)) {
- debug("Adjusted buffer size on Numonyx flash"
- " M29EW family in 8 bit mode\n");
+ if (qry->max_buf_write_size > 0x8 &&
+ info->device_id == 0x7E &&
+ (info->device_id2 == 0x2201 ||
+ info->device_id2 == 0x2301 ||
+ info->device_id2 == 0x2801 ||
+ info->device_id2 == 0x4801)) {
+ debug("Adjusted buffer size on Numonyx flash");
+ debug(" M29EW family in 8 bit mode\n");
qry->max_buf_write_size = 0x8;
}
}
* The following code cannot be run from FLASH!
*
*/
-ulong flash_get_size (phys_addr_t base, int banknum)
+ulong flash_get_size(phys_addr_t base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
int i, j;
info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
- if (flash_detect_cfi (info, &qry)) {
- info->vendor = le16_to_cpu(get_unaligned(&(qry.p_id)));
- info->ext_addr = le16_to_cpu(get_unaligned(&(qry.p_adr)));
+ if (flash_detect_cfi(info, &qry)) {
+ info->vendor = le16_to_cpu(get_unaligned(&qry.p_id));
+ info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr));
num_erase_regions = qry.num_erase_regions;
if (info->ext_addr) {
- info->cfi_version = (ushort) flash_read_uchar (info,
+ info->cfi_version = (ushort)flash_read_uchar(info,
info->ext_addr + 3) << 8;
- info->cfi_version |= (ushort) flash_read_uchar (info,
+ info->cfi_version |= (ushort)flash_read_uchar(info,
info->ext_addr + 4);
}
#ifdef DEBUG
- flash_printqry (&qry);
+ flash_printqry(&qry);
#endif
switch (info->vendor) {
break;
default:
printf("CFI: Unknown command set 0x%x\n",
- info->vendor);
+ info->vendor);
/*
* Unfortunately, this means we don't know how
* to get the chip back to Read mode. Might
break;
}
- debug ("manufacturer is %d\n", info->vendor);
- debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
- debug ("device id is 0x%x\n", info->device_id);
- debug ("device id2 is 0x%x\n", info->device_id2);
- debug ("cfi version is 0x%04x\n", info->cfi_version);
+ debug("manufacturer is %d\n", info->vendor);
+ debug("manufacturer id is 0x%x\n", info->manufacturer_id);
+ debug("device id is 0x%x\n", info->device_id);
+ debug("device id2 is 0x%x\n", info->device_id2);
+ debug("cfi version is 0x%04x\n", info->cfi_version);
size_ratio = info->portwidth / info->chipwidth;
/* if the chip is x8/x16 reduce the ratio by half */
- if ((info->interface == FLASH_CFI_X8X16)
- && (info->chipwidth == FLASH_CFI_BY8)) {
+ if (info->interface == FLASH_CFI_X8X16 &&
+ info->chipwidth == FLASH_CFI_BY8) {
size_ratio >>= 1;
}
- debug ("size_ratio %d port %d bits chip %d bits\n",
- size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ debug("size_ratio %d port %d bits chip %d bits\n",
+ size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
info->size = 1 << qry.dev_size;
/* multiply the size by the number of chips */
info->size *= size_ratio;
max_size = cfi_flash_bank_size(banknum);
- if (max_size && (info->size > max_size)) {
+ if (max_size && info->size > max_size) {
debug("[truncated from %ldMiB]", info->size >> 20);
info->size = max_size;
}
- debug ("found %d erase regions\n", num_erase_regions);
+ debug("found %d erase regions\n", num_erase_regions);
sect_cnt = 0;
sector = base;
for (i = 0; i < num_erase_regions; i++) {
if (i > NUM_ERASE_REGIONS) {
- printf ("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
+ printf("%d erase regions found, only %d used\n",
+ num_erase_regions, NUM_ERASE_REGIONS);
break;
}
tmp = le32_to_cpu(get_unaligned(
- &(qry.erase_region_info[i])));
+ &qry.erase_region_info[i]));
debug("erase region %u: 0x%08lx\n", i, tmp);
erase_region_count = (tmp & 0xffff) + 1;
tmp >>= 16;
erase_region_size =
(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
- debug ("erase_region_count = %d erase_region_size = %d\n",
- erase_region_count, erase_region_size);
+ debug("erase_region_count = %d ", erase_region_count);
+ debug("erase_region_size = %d\n", erase_region_size);
for (j = 0; j < erase_region_count; j++) {
if (sector - base >= info->size)
break;
flash_write_cmd(info, sect_cnt, 0,
FLASH_CMD_READ_ID);
info->protect[sect_cnt] =
- flash_isset (info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
+ flash_isset(info, sect_cnt,
+ FLASH_OFFSET_PROTECT,
+ FLASH_STATUS_PROTECT);
flash_write_cmd(info, sect_cnt, 0,
FLASH_CMD_RESET);
break;
/* round up when converting to ms */
info->write_tout = (tmp + 999) / 1000;
info->flash_id = FLASH_MAN_CFI;
- if ((info->interface == FLASH_CFI_X8X16) &&
- (info->chipwidth == FLASH_CFI_BY8)) {
+ if (info->interface == FLASH_CFI_X8X16 &&
+ info->chipwidth == FLASH_CFI_BY8) {
/* XXX - Need to test on x8/x16 in parallel. */
info->portwidth >>= 1;
}
- flash_write_cmd (info, 0, 0, info->cmd_reset);
+ flash_write_cmd(info, 0, 0, info->cmd_reset);
}
return (info->size);
#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
(!defined(CONFIG_MONITOR_IS_IN_RAM))
flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
/* Environment protection ON by default */
#ifdef CONFIG_ENV_IS_IN_FLASH
flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- flash_get_info(CONFIG_ENV_ADDR));
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ flash_get_info(CONFIG_ENV_ADDR));
#endif
/* Redundant environment protection ON by default */
#ifdef CONFIG_ENV_ADDR_REDUND
flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- flash_get_info(CONFIG_ENV_ADDR_REDUND));
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ flash_get_info(CONFIG_ENV_ADDR_REDUND));
#endif
#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
debug("autoprotecting from %08lx to %08lx\n",
apl[i].start, apl[i].start + apl[i].size - 1);
flash_protect(FLAG_PROTECT_SET,
- apl[i].start,
- apl[i].start + apl[i].size - 1,
- flash_get_info(apl[i].start));
+ apl[i].start,
+ apl[i].start + apl[i].size - 1,
+ flash_get_info(apl[i].start));
}
#endif
}
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
unsigned long size = 0;
int i;
#ifdef CONFIG_SYS_FLASH_PROTECTION
/* read environment from EEPROM */
char s[64];
+
env_get_f("unlock", s, sizeof(s));
#endif
size += flash_info[i].size;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
#ifndef CONFIG_SYS_FLASH_QUIET_TEST
- printf ("## Unknown flash on Bank %d "
- "- Size = 0x%08lx = %ld MB\n",
- i+1, flash_info[i].size,
- flash_info[i].size >> 20);
+ printf("## Unknown flash on Bank %d ", i + 1);
+ printf("- Size = 0x%08lx = %ld MB\n",
+ flash_info[i].size,
+ flash_info[i].size >> 20);
#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
* unlock only one sector. This will
* unlock all sectors.
*/
- flash_real_protect (&flash_info[i], 0, 0);
+ flash_real_protect(&flash_info[i], 0, 0);
flash_info[i].legacy_unlock = 1;
/*
* No legancy unlocking -> unlock all sectors
*/
- flash_protect (FLAG_PROTECT_CLEAR,
- flash_info[i].start[0],
- flash_info[i].start[0]
- + flash_info[i].size - 1,
- &flash_info[i]);
+ flash_protect(FLAG_PROTECT_CLEAR,
+ flash_info[i].start[0],
+ flash_info[i].start[0]
+ + flash_info[i].size - 1,
+ &flash_info[i]);
}
}
#endif /* CONFIG_SYS_FLASH_PROTECTION */
static int flash_wait_till_busy(const char *func, ulong timeout)
{
- int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
- NVM_WR, false, timeout, false);
+ int ret = wait_for_bit_le32(&nvm_regs_p->ctrl.raw,
+ NVM_WR, false, timeout, false);
- return ret ? ERR_TIMOUT : ERR_OK;
+ return ret ? ERR_TIMEOUT : ERR_OK;
}
static inline int flash_complete_operation(void)
* Erase flash sectors, returns:
* ERR_OK - OK
* ERR_INVAL - invalid sector arguments
- * ERR_TIMOUT - write timeout
+ * ERR_TIMEOUT - write timeout
* ERR_NOT_ERASED - Flash not erased
* ERR_UNKNOWN_FLASH_VENDOR - incorrect flash
*/
/*
* Copy memory to flash, returns:
* ERR_OK - OK
- * ERR_TIMOUT - write timeout
+ * ERR_TIMEOUT - write timeout
* ERR_NOT_ERASED - Flash not erased
*/
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
}
#ifndef CONFIG_DM_SPI_FLASH
-static struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus)
+struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
{
+ struct spi_slave *bus;
struct spi_flash *flash;
+ bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
+ if (!bus)
+ return NULL;
+
/* Allocate space if needed (not used by sf-uclass */
flash = calloc(1, sizeof(*flash));
if (!flash) {
return flash;
}
-struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode)
-{
- struct spi_slave *bus;
-
- bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
- if (!bus)
- return NULL;
- return spi_flash_probe_tail(bus);
-}
-
-#ifdef CONFIG_OF_SPI_FLASH
-struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
- int spi_node)
-{
- struct spi_slave *bus;
-
- bus = spi_setup_slave_fdt(blob, slave_node, spi_node);
- if (!bus)
- return NULL;
- return spi_flash_probe_tail(bus);
-}
-#endif
-
void spi_flash_free(struct spi_flash *flash)
{
#ifdef CONFIG_SPI_FLASH_MTD
}
static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
- const void *buf)
+ const void *buf)
{
struct spi_flash *flash = dev_get_uclass_priv(dev);
if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)spi->max_write_size);
+ spi->max_write_size - sizeof(cmd));
spi_flash_addr(write_addr, cmd);
else
read_len = remain_len;
+ if (spi->max_read_size)
+ read_len = min(read_len, spi->max_read_size);
+
spi_flash_addr(read_addr, cmd);
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
regs + AG7XXX_ETH_MII_MGMT_CMD);
- ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
- AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+ ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+ AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
if (ret)
return ret;
regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
- ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
- AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+ ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+ AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
return ret;
}
/* Stop the TX DMA. */
writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
- wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
- 1000, 0);
+ wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+ 1000, 0);
/* Stop the RX DMA. */
writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
- wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
- 1000, 0);
+ wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+ 1000, 0);
}
/*
static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
{
- return wait_for_bit(__func__, &eqos->mac_regs->mdio_address,
- EQOS_MAC_MDIO_ADDRESS_GB, false, 1000000, true);
+ return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
+ EQOS_MAC_MDIO_ADDRESS_GB, false,
+ 1000000, true);
}
static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
setbits_le32(&eqos->tegra186_regs->auto_cal_config,
EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
- ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
- EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
+ ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
+ EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
if (ret) {
pr_err("calibrate didn't start");
goto failed;
}
- ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
- EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
+ ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
+ EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
if (ret) {
pr_err("calibrate didn't finish");
goto failed;
eqos->reg_access_ok = true;
- ret = wait_for_bit(__func__, &eqos->dma_regs->mode,
- EQOS_DMA_MODE_SWR, false, 10, false);
+ ret = wait_for_bit_le32(&eqos->dma_regs->mode,
+ EQOS_DMA_MODE_SWR, false, 10, false);
if (ret) {
pr_err("EQOS_DMA_MODE_SWR stuck");
goto err_stop_resets;
ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
- rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS),
- MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+ rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+ MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
if (rc == 0) {
u32 data = ethoc_read(priv, MIIRX_DATA);
ethoc_write(priv, MIITX_DATA, val);
ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
- rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS),
- MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+ rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+ MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
if (rc == 0) {
/* reset MII command register */
#include <asm/arch/periph.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk322x.h>
#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3328.h>
#include <asm/arch/grf_rk3368.h>
#include <asm/arch/grf_rk3399.h>
+#include <asm/arch/grf_rv1108.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"
*/
struct gmac_rockchip_platdata {
struct dw_eth_pdata dw_eth_pdata;
+ bool clock_input;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ const char *string;
+
+ string = dev_read_string(dev, "clock_in_out");
+ if (!strcmp(string, "input"))
+ pdata->clock_input = true;
+ else
+ pdata->clock_input = false;
/* Check the new naming-style first... */
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
return designware_eth_ofdata_to_platdata(dev);
}
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
+ int clk;
+ enum {
+ RK3228_GMAC_CLK_SEL_SHIFT = 8,
+ RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
+ RK3228_GMAC_CLK_SEL_125M = 0 << 8,
+ RK3228_GMAC_CLK_SEL_25M = 3 << 8,
+ RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3228_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3228_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3228_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
return 0;
}
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
+ int clk;
+ enum {
+ RK3328_GMAC_CLK_SEL_SHIFT = 11,
+ RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
+ RK3328_GMAC_CLK_SEL_125M = 0 << 11,
+ RK3328_GMAC_CLK_SEL_25M = 3 << 11,
+ RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3328_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3328_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3328_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
return 0;
}
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+{
+ struct rv1108_grf *grf;
+ int clk, speed;
+ enum {
+ RV1108_GMAC_SPEED_MASK = BIT(2),
+ RV1108_GMAC_SPEED_10M = 0 << 2,
+ RV1108_GMAC_SPEED_100M = 1 << 2,
+ RV1108_GMAC_CLK_SEL_MASK = BIT(7),
+ RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
+ RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RV1108_GMAC_CLK_SEL_2_5M;
+ speed = RV1108_GMAC_SPEED_10M;
+ break;
+ case 100:
+ clk = RV1108_GMAC_CLK_SEL_25M;
+ speed = RV1108_GMAC_SPEED_100M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+ RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+ clk | speed);
+
+ return 0;
+}
+
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_RMII_MODE_SHIFT = 10,
+ RK3228_RMII_MODE_MASK = BIT(10),
+
+ RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_RMII_MODE_MASK |
+ RK3228_GMAC_PHY_INTF_SEL_MASK |
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+ RK3228_GMAC_PHY_INTF_SEL_RGMII |
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(&grf->mac_con[0],
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+ pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_grf *grf;
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_SHIFT = 9,
+ RK3328_RMII_MODE_MASK = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3328_RMII_MODE_MASK |
+ RK3328_GMAC_PHY_INTF_SEL_MASK |
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+ RK3328_GMAC_PHY_INTF_SEL_RGMII |
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(&grf->mac_con[0],
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+ pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3368_grf *grf;
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rv1108_grf *grf;
+
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+ RV1108_GMAC_PHY_INTF_SEL_MASK,
+ RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
struct clk clk;
+ ulong rate;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(&clk, 0);
- if (ret)
- return ret;
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * If the gmac clock is from internal pll, need to set and
+ * check the return value for gmac clock at RGMII mode. If
+ * the gmac clock is from external source, the clock rate
+ * is not set, because of it is bypassed.
+ */
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
+
+ /* Set to RGMII mode */
+ if (ops->set_to_rgmii)
+ ops->set_to_rgmii(pdata);
+ else
+ return -EPERM;
+
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* The commet is the same as RGMII mode */
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 50000000);
+ if (rate != 50000000)
+ return -EINVAL;
+ }
+
+ /* Set to RMII mode */
+ if (ops->set_to_rmii)
+ ops->set_to_rmii(pdata);
+ else
+ return -EPERM;
- /* Set to RGMII mode */
- ops->set_to_rgmii(pdata);
+ break;
+ default:
+ debug("NO interface defined!\n");
+ return -ENXIO;
+ }
return designware_eth_probe(dev);
}
.write_hwaddr = designware_eth_write_hwaddr,
};
+const struct rk_gmac_ops rk3228_gmac_ops = {
+ .fix_mac_speed = rk3228_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3288_gmac_ops = {
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops rk3328_gmac_ops = {
+ .fix_mac_speed = rk3328_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3368_gmac_ops = {
.fix_mac_speed = rk3368_gmac_fix_mac_speed,
.set_to_rgmii = rk3368_gmac_set_to_rgmii,
.set_to_rgmii = rk3399_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops rv1108_gmac_ops = {
+ .fix_mac_speed = rv1108_set_rmii_speed,
+ .set_to_rmii = rv1108_gmac_set_to_rmii,
+};
+
static const struct udevice_id rockchip_gmac_ids[] = {
+ { .compatible = "rockchip,rk3228-gmac",
+ .data = (ulong)&rk3228_gmac_ops },
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)&rk3288_gmac_ops },
+ { .compatible = "rockchip,rk3328-gmac",
+ .data = (ulong)&rk3328_gmac_ops },
{ .compatible = "rockchip,rk3368-gmac",
.data = (ulong)&rk3368_gmac_ops },
{ .compatible = "rockchip,rk3399-gmac",
.data = (ulong)&rk3399_gmac_ops },
+ { .compatible = "rockchip,rv1108-gmac",
+ .data = (ulong)&rv1108_gmac_ops },
{ }
};
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
- u64 mdio_addr;
+ phys_addr_t mdio_addr;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
/* wait till busy */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ CONFIG_SYS_HZ, false);
/* turn controller ON to access PHY over MII */
writel(ETHCON_ON, &ectl_p->con1.set);
writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
/* wait till busy */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ CONFIG_SYS_HZ, false);
/* decrement received buffcnt to zero. */
while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
mdelay(10);
/* wait until everything is down */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- 2 * CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ 2 * CONFIG_SYS_HZ, false);
/* clear any existing interrupt event */
writel(0xffffffff, &ectl_p->irq.clr);
struct pic32_mii_regs *mii_regs = bus->priv;
/* Wait for the previous operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
/* Put phyaddr and regaddr into MIIMADD */
v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
udelay(12);
/* Wait for write to complete */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
return 0;
}
struct pic32_mii_regs *mii_regs = bus->priv;
/* Wait for the previous operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
/* Put phyaddr and regaddr into MIIMADD */
v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
udelay(12);
/* Wait for read to complete */
- wait_for_bit(__func__, &mii_regs->mind.raw,
- MIIMIND_NOTVALID | MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&mii_regs->mind.raw,
+ MIIMIND_NOTVALID | MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, false);
/* Clear the command register */
writel(0, &mii_regs->mcmd.raw);
writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw);
/* Wait for the operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
false, CONFIG_SYS_HZ, true);
/* Clear reset bit */
writel(0, &mii_regs->mcfg);
/* Wait for the operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
/* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */
writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw);
/* Wait for the operation to finish */
- wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
- false, CONFIG_SYS_HZ, true);
+ wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+ false, CONFIG_SYS_HZ, true);
return 0;
}
writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
/* Check the operating mode is changed to the config mode. */
- return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
- CSR_OPS_CONFIG, true, 100, true);
+ return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
+ CSR_OPS_CONFIG, true, 100, true);
}
static void ravb_base_desc_init(struct ravb_priv *eth)
return 0;
}
-int ravb_start(struct udevice *dev)
+static int ravb_start(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
int ret;
#include <linux/errno.h>
#include <asm/io.h>
+#ifdef CONFIG_DM_ETH
+#include <clk.h>
+#include <dm.h>
+#include <linux/mii.h>
+#include <asm/gpio.h>
+#endif
+
#include "sh_eth.h"
#ifndef CONFIG_SH_ETHER_USE_PORT
#define TIMEOUT_CNT 1000
-int sh_eth_send(struct eth_device *dev, void *packet, int len)
+static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
{
- struct sh_eth_dev *eth = dev->priv;
int port = eth->port, ret = 0, timeout;
struct sh_eth_info *port_info = ð->port_info[port];
return ret;
}
-int sh_eth_recv(struct eth_device *dev)
+static int sh_eth_recv_start(struct sh_eth_dev *eth)
{
- struct sh_eth_dev *eth = dev->priv;
int port = eth->port, len = 0;
struct sh_eth_info *port_info = ð->port_info[port];
- uchar *packet;
/* Check if the rx descriptor is ready */
invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
- if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
- /* Check for errors */
- if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
- len = port_info->rx_desc_cur->rd1 & 0xffff;
- packet = (uchar *)
- ADDR_TO_P2(port_info->rx_desc_cur->rd2);
- invalidate_cache(packet, len);
- net_process_received_packet(packet, len);
- }
-
- /* Make current descriptor available again */
- if (port_info->rx_desc_cur->rd0 & RD_RDLE)
- port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
- else
- port_info->rx_desc_cur->rd0 = RD_RACT;
-
- flush_cache_wback(port_info->rx_desc_cur,
- sizeof(struct rx_desc_s));
-
- /* Point to the next descriptor */
- port_info->rx_desc_cur++;
- if (port_info->rx_desc_cur >=
- port_info->rx_desc_base + NUM_RX_DESC)
- port_info->rx_desc_cur = port_info->rx_desc_base;
- }
+ if (port_info->rx_desc_cur->rd0 & RD_RACT)
+ return -EINVAL;
- /* Restart the receiver if disabled */
- if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
- sh_eth_write(port_info, EDRRR_R, EDRRR);
+ /* Check for errors */
+ if (port_info->rx_desc_cur->rd0 & RD_RFE)
+ return -EINVAL;
+
+ len = port_info->rx_desc_cur->rd1 & 0xffff;
return len;
}
+static void sh_eth_recv_finish(struct sh_eth_dev *eth)
+{
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ /* Make current descriptor available again */
+ if (port_info->rx_desc_cur->rd0 & RD_RDLE)
+ port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
+ else
+ port_info->rx_desc_cur->rd0 = RD_RACT;
+
+ flush_cache_wback(port_info->rx_desc_cur,
+ sizeof(struct rx_desc_s));
+
+ /* Point to the next descriptor */
+ port_info->rx_desc_cur++;
+ if (port_info->rx_desc_cur >=
+ port_info->rx_desc_base + NUM_RX_DESC)
+ port_info->rx_desc_cur = port_info->rx_desc_base;
+}
+
static int sh_eth_reset(struct sh_eth_dev *eth)
{
struct sh_eth_info *port_info = ð->port_info[eth->port];
return ret;
}
-static int sh_eth_phy_config(struct sh_eth_dev *eth)
+static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
+ unsigned char *mac)
{
- int port = eth->port, ret = 0;
- struct sh_eth_info *port_info = ð->port_info[port];
- struct eth_device *dev = port_info->dev;
- struct phy_device *phydev;
+ u32 val;
- phydev = phy_connect(
- miiphy_get_dev_by_name(dev->name),
- port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
- port_info->phydev = phydev;
- phy_config(phydev);
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ sh_eth_write(port_info, val, MAHR);
- return ret;
+ val = (mac[4] << 8) | mac[5];
+ sh_eth_write(port_info, val, MALR);
}
-static int sh_eth_config(struct sh_eth_dev *eth)
+static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
{
- int port = eth->port, ret = 0;
- u32 val;
- struct sh_eth_info *port_info = ð->port_info[port];
- struct eth_device *dev = port_info->dev;
- struct phy_device *phy;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
/* Configure e-dmac registers */
sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
sh_eth_write(port_info, 0, ECSIPR);
/* Set Mac address */
- val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
- dev->enetaddr[2] << 8 | dev->enetaddr[3];
- sh_eth_write(port_info, val, MAHR);
-
- val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
- sh_eth_write(port_info, val, MALR);
+ sh_eth_write_hwaddr(port_info, mac);
sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif
- /* Configure phy */
- ret = sh_eth_phy_config(eth);
- if (ret) {
- printf(SHETHER_NAME ": phy config timeout\n");
- goto err_phy_cfg;
- }
- phy = port_info->phydev;
- ret = phy_startup(phy);
- if (ret) {
- printf(SHETHER_NAME ": phy startup failure\n");
- return ret;
- }
+}
- val = 0;
+static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
+{
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+ struct phy_device *phy = port_info->phydev;
+ int ret = 0;
+ u32 val = 0;
/* Set the transfer speed */
if (phy->speed == 100) {
sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
- defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
- defined(CONFIG_R8A7794)
+#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
}
return ret;
-
-err_phy_cfg:
- return ret;
}
static void sh_eth_start(struct sh_eth_dev *eth)
sh_eth_write(port_info, ~EDRRR_R, EDRRR);
}
-int sh_eth_init(struct eth_device *dev, bd_t *bd)
+static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
{
int ret = 0;
- struct sh_eth_dev *eth = dev->priv;
ret = sh_eth_reset(eth);
if (ret)
- goto err;
+ return ret;
ret = sh_eth_desc_init(eth);
if (ret)
- goto err;
+ return ret;
+
+ sh_eth_mac_regs_config(eth, mac);
+
+ return 0;
+}
+
+static int sh_eth_start_common(struct sh_eth_dev *eth)
+{
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+ int ret;
- ret = sh_eth_config(eth);
+ ret = phy_startup(port_info->phydev);
+ if (ret) {
+ printf(SHETHER_NAME ": phy startup failure\n");
+ return ret;
+ }
+
+ ret = sh_eth_phy_regs_config(eth);
if (ret)
- goto err_config;
+ return ret;
sh_eth_start(eth);
+ return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
+{
+ int port = eth->port, ret = 0;
+ struct sh_eth_info *port_info = ð->port_info[port];
+ struct eth_device *dev = port_info->dev;
+ struct phy_device *phydev;
+
+ phydev = phy_connect(
+ miiphy_get_dev_by_name(dev->name),
+ port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
+ port_info->phydev = phydev;
+ phy_config(phydev);
+
return ret;
+}
+
+static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
+{
+ struct sh_eth_dev *eth = dev->priv;
+
+ return sh_eth_send_common(eth, packet, len);
+}
+
+static int sh_eth_recv_common(struct sh_eth_dev *eth)
+{
+ int port = eth->port, len = 0;
+ struct sh_eth_info *port_info = ð->port_info[port];
+ uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+
+ len = sh_eth_recv_start(eth);
+ if (len > 0) {
+ invalidate_cache(packet, len);
+ net_process_received_packet(packet, len);
+ sh_eth_recv_finish(eth);
+ } else
+ len = 0;
-err_config:
+ /* Restart the receiver if disabled */
+ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
+
+ return len;
+}
+
+static int sh_eth_recv_legacy(struct eth_device *dev)
+{
+ struct sh_eth_dev *eth = dev->priv;
+
+ return sh_eth_recv_common(eth);
+}
+
+static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
+{
+ struct sh_eth_dev *eth = dev->priv;
+ int ret;
+
+ ret = sh_eth_init_common(eth, dev->enetaddr);
+ if (ret)
+ return ret;
+
+ ret = sh_eth_phy_config_legacy(eth);
+ if (ret) {
+ printf(SHETHER_NAME ": phy config timeout\n");
+ goto err_start;
+ }
+
+ ret = sh_eth_start_common(eth);
+ if (ret)
+ goto err_start;
+
+ return 0;
+
+err_start:
sh_eth_tx_desc_free(eth);
sh_eth_rx_desc_free(eth);
-
-err:
return ret;
}
-void sh_eth_halt(struct eth_device *dev)
+void sh_eth_halt_legacy(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
dev->priv = (void *)eth;
dev->iobase = 0;
- dev->init = sh_eth_init;
- dev->halt = sh_eth_halt;
- dev->send = sh_eth_send;
- dev->recv = sh_eth_recv;
+ dev->init = sh_eth_init_legacy;
+ dev->halt = sh_eth_halt_legacy;
+ dev->send = sh_eth_send_legacy;
+ dev->recv = sh_eth_recv_legacy;
eth->port_info[eth->port].dev = dev;
strcpy(dev->name, SHETHER_NAME);
return ret;
}
+#else /* CONFIG_DM_ETH */
+
+struct sh_ether_priv {
+ struct sh_eth_dev shdev;
+
+ struct mii_dev *bus;
+ void __iomem *iobase;
+ struct clk clk;
+ struct gpio_desc reset_gpio;
+};
+
+static int sh_ether_send(struct udevice *dev, void *packet, int len)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+ struct sh_eth_dev *eth = &priv->shdev;
+
+ return sh_eth_send_common(eth, packet, len);
+}
+
+static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+ uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+ int len;
+
+ len = sh_eth_recv_start(eth);
+ if (len > 0) {
+ invalidate_cache(packet, len);
+ *packetp = packet;
+
+ return len;
+ } else {
+ len = 0;
+
+ /* Restart the receiver if disabled */
+ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
+
+ return -EAGAIN;
+ }
+}
+
+static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ sh_eth_recv_finish(eth);
+
+ /* Restart the receiver if disabled */
+ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
+ sh_eth_write(port_info, EDRRR_R, EDRRR);
+
+ return 0;
+}
+
+static int sh_ether_write_hwaddr(struct udevice *dev)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ sh_eth_write_hwaddr(port_info, pdata->enetaddr);
+
+ return 0;
+}
+
+static int sh_eth_phy_config(struct udevice *dev)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ int port = eth->port, ret = 0;
+ struct sh_eth_info *port_info = ð->port_info[port];
+ struct phy_device *phydev;
+ int mask = 0xffffffff;
+
+ phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
+ if (!phydev)
+ return -ENODEV;
+
+ phy_connect_dev(phydev, dev);
+
+ port_info->phydev = phydev;
+ phy_config(phydev);
+
+ return ret;
+}
+
+static int sh_ether_start(struct udevice *dev)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ int ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
+
+ ret = sh_eth_init_common(eth, pdata->enetaddr);
+ if (ret)
+ goto err_clk;
+
+ ret = sh_eth_phy_config(dev);
+ if (ret) {
+ printf(SHETHER_NAME ": phy config timeout\n");
+ goto err_start;
+ }
+
+ ret = sh_eth_start_common(eth);
+ if (ret)
+ goto err_start;
+
+ return 0;
+
+err_start:
+ sh_eth_tx_desc_free(eth);
+ sh_eth_rx_desc_free(eth);
+err_clk:
+ clk_disable(&priv->clk);
+ return ret;
+}
+
+static void sh_ether_stop(struct udevice *dev)
+{
+ struct sh_ether_priv *priv = dev_get_priv(dev);
+
+ sh_eth_stop(&priv->shdev);
+ clk_disable(&priv->clk);
+}
+
+static int sh_ether_probe(struct udevice *udev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(udev);
+ struct sh_ether_priv *priv = dev_get_priv(udev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ struct mii_dev *mdiodev;
+ void __iomem *iobase;
+ int ret;
+
+ iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
+ priv->iobase = iobase;
+
+ ret = clk_get_by_index(udev, 0, &priv->clk);
+ if (ret < 0)
+ goto err_mdio_alloc;
+
+ gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
+ GPIOD_IS_OUT);
+
+ mdiodev = mdio_alloc();
+ if (!mdiodev) {
+ ret = -ENOMEM;
+ goto err_mdio_alloc;
+ }
+
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+ bb_miiphy_buses[0].priv = eth;
+ snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
+
+ ret = mdio_register(mdiodev);
+ if (ret < 0)
+ goto err_mdio_register;
+
+ priv->bus = miiphy_get_dev_by_name(udev->name);
+
+ eth->port = CONFIG_SH_ETHER_USE_PORT;
+ eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
+ eth->port_info[eth->port].iobase =
+ (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
+
+ return 0;
+
+err_mdio_register:
+ mdio_free(mdiodev);
+err_mdio_alloc:
+ unmap_physmem(priv->iobase, MAP_NOCACHE);
+ return ret;
+}
+
+static int sh_ether_remove(struct udevice *udev)
+{
+ struct sh_ether_priv *priv = dev_get_priv(udev);
+ struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ free(port_info->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ if (dm_gpio_is_valid(&priv->reset_gpio))
+ dm_gpio_free(udev, &priv->reset_gpio);
+
+ unmap_physmem(priv->iobase, MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct eth_ops sh_ether_ops = {
+ .start = sh_ether_start,
+ .send = sh_ether_send,
+ .recv = sh_ether_recv,
+ .free_pkt = sh_ether_free_pkt,
+ .stop = sh_ether_stop,
+ .write_hwaddr = sh_ether_write_hwaddr,
+};
+
+int sh_ether_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const char *phy_mode;
+ const fdt32_t *cell;
+ int ret = 0;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ pdata->max_speed = 1000;
+ cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
+ if (cell)
+ pdata->max_speed = fdt32_to_cpu(*cell);
+
+ sprintf(bb_miiphy_buses[0].name, dev->name);
+
+ return ret;
+}
+
+static const struct udevice_id sh_ether_ids[] = {
+ { .compatible = "renesas,ether-r8a7791" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_sh_ether) = {
+ .name = "sh_ether",
+ .id = UCLASS_ETH,
+ .of_match = sh_ether_ids,
+ .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
+ .probe = sh_ether_probe,
+ .remove = sh_ether_remove,
+ .ops = &sh_ether_ops,
+ .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
+
/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
{
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
#elif defined(CONFIG_R7S72100)
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
ECMR_RTM = 0x00000004,
#endif
* processor mode and hence bypass in this mode
*/
if (!priv->eth_hasnobuf) {
- err = wait_for_bit(__func__, (const u32 *)®s->is,
- XAE_INT_MGTRDY_MASK, true, 200, false);
+ err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
+ true, 200, false);
if (err) {
printf("%s: Timeout\n", __func__);
return 1;
struct zynq_gem_regs *regs = priv->iobase;
int err;
- err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, false);
+ err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, false);
if (err)
return err;
/* Write mgtcr and wait for completion */
writel(mgtcr, ®s->phymntnc);
- err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, false);
+ err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, false);
if (err)
return err;
if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
printf("TX buffers exhausted in mid frame\n");
- return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
- true, 20000, true);
+ return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
+ true, 20000, true);
}
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
DesignWare hardware.
+config PCI_RCAR_GEN2
+ bool "Renesas RCar Gen2 PCIe driver"
+ depends on DM_PCI
+ depends on RCAR_32
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
+ also used to access EHCI USB controller on the SoC.
+
config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
+obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_SH4_PCI) += pci_sh4.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
--- /dev/null
+/*
+ * Renesas RCar Gen2 PCIEC driver
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+
+/* AHB-PCI Bridge PCI communication registers */
+#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
+
+#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
+#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
+#define RCAR_PCIAHB_PREFETCH0 0x0
+#define RCAR_PCIAHB_PREFETCH4 0x1
+#define RCAR_PCIAHB_PREFETCH8 0x2
+#define RCAR_PCIAHB_PREFETCH16 0x3
+
+#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
+#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
+#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
+#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
+#define RCAR_AHBPCI_WIN1_HOST BIT(30)
+#define RCAR_AHBPCI_WIN1_DEVICE BIT(31)
+
+#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
+#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
+#define RCAR_PCI_INT_SIGTABORT BIT(0)
+#define RCAR_PCI_INT_SIGRETABORT BIT(1)
+#define RCAR_PCI_INT_REMABORT BIT(2)
+#define RCAR_PCI_INT_PERR BIT(3)
+#define RCAR_PCI_INT_SIGSERR BIT(4)
+#define RCAR_PCI_INT_RESERR BIT(5)
+#define RCAR_PCI_INT_WIN1ERR BIT(12)
+#define RCAR_PCI_INT_WIN2ERR BIT(13)
+#define RCAR_PCI_INT_A BIT(16)
+#define RCAR_PCI_INT_B BIT(17)
+#define RCAR_PCI_INT_PME BIT(19)
+#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
+ RCAR_PCI_INT_SIGRETABORT | \
+ RCAR_PCI_INT_SIGRETABORT | \
+ RCAR_PCI_INT_REMABORT | \
+ RCAR_PCI_INT_PERR | \
+ RCAR_PCI_INT_SIGSERR | \
+ RCAR_PCI_INT_RESERR | \
+ RCAR_PCI_INT_WIN1ERR | \
+ RCAR_PCI_INT_WIN2ERR)
+
+#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
+#define RCAR_AHB_BUS_MMODE_HTRANS BIT(0)
+#define RCAR_AHB_BUS_MMODE_BYTE_BURST BIT(1)
+#define RCAR_AHB_BUS_MMODE_WR_INCR BIT(2)
+#define RCAR_AHB_BUS_MMODE_HBUS_REQ BIT(7)
+#define RCAR_AHB_BUS_SMODE_READYCTR BIT(17)
+#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
+ RCAR_AHB_BUS_MMODE_BYTE_BURST | \
+ RCAR_AHB_BUS_MMODE_WR_INCR | \
+ RCAR_AHB_BUS_MMODE_HBUS_REQ | \
+ RCAR_AHB_BUS_SMODE_READYCTR)
+
+#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
+#define RCAR_USBCTR_USBH_RST BIT(0)
+#define RCAR_USBCTR_PCICLK_MASK BIT(1)
+#define RCAR_USBCTR_PLL_RST BIT(2)
+#define RCAR_USBCTR_DIRPD BIT(8)
+#define RCAR_USBCTR_PCIAHB_WIN2_EN BIT(9)
+#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
+#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
+#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
+#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
+#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
+
+#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
+#define RCAR_PCI_ARBITER_PCIREQ0 BIT(0)
+#define RCAR_PCI_ARBITER_PCIREQ1 BIT(1)
+#define RCAR_PCI_ARBITER_PCIBP_MODE BIT(12)
+
+#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
+
+struct rcar_gen2_pci_priv {
+ fdt_addr_t cfg_base;
+ fdt_addr_t mem_base;
+};
+
+static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset)
+{
+ u32 slot;
+
+ if (PCI_FUNC(d))
+ return -EINVAL;
+
+ /* Only one EHCI/OHCI device built-in */
+ slot = PCI_DEV(d);
+ if (slot > 2)
+ return -EINVAL;
+
+ /* bridge logic only has registers to 0x40 */
+ if (slot == 0x0 && offset >= 0x40)
+ return -EINVAL;
+
+ return 0;
+}
+
+static u32 get_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
+{
+ struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
+
+ return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3);
+}
+
+static u32 setup_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
+{
+ struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ reg = PCI_DEV(bdf) ? RCAR_AHBPCI_WIN1_DEVICE : RCAR_AHBPCI_WIN1_HOST;
+ reg |= RCAR_AHBPCI_WIN_CTR_CFG;
+ writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG);
+
+ return get_bus_address(dev, bdf, offset);
+}
+
+static int rcar_gen2_pci_read_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong *value,
+ enum pci_size_t size)
+{
+ u32 addr, reg;
+ int ret;
+
+ ret = rcar_gen2_pci_addr_valid(bdf, offset);
+ if (ret) {
+ *value = pci_get_ff(size);
+ return 0;
+ }
+
+ addr = get_bus_address(dev, bdf, offset);
+ reg = readl(addr);
+ *value = pci_conv_32_to_size(reg, offset, size);
+
+ return 0;
+}
+
+static int rcar_gen2_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ u32 addr, reg, old;
+ int ret;
+
+ ret = rcar_gen2_pci_addr_valid(bdf, offset);
+ if (ret)
+ return ret;
+
+ addr = get_bus_address(dev, bdf, offset);
+
+ old = readl(addr);
+ reg = pci_conv_size_to_32(old, value, offset, size);
+ writel(reg, addr);
+
+ return 0;
+}
+
+static int rcar_gen2_pci_probe(struct udevice *dev)
+{
+ struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
+ struct clk pci_clk;
+ u32 devad;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &pci_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&pci_clk);
+ if (ret)
+ return ret;
+
+ /* Clock & Reset & Direct Power Down */
+ clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG,
+ RCAR_USBCTR_DIRPD | RCAR_USBCTR_PCICLK_MASK |
+ RCAR_USBCTR_USBH_RST,
+ RCAR_USBCTR_PCIAHB_WIN1_1G);
+ clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST);
+
+ /* AHB-PCI Bridge Communication Registers */
+ writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
+ writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
+ priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
+ writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
+ priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
+ writel(priv->mem_base | RCAR_AHBPCI_WIN_CTR_MEM,
+ priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG);
+ setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG,
+ RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
+ RCAR_PCI_ARBITER_PCIBP_MODE);
+
+ /* PCI Configuration Registers for AHBPCI */
+ devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
+ writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
+ writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
+ writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
+ writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
+ devad + PCI_COMMAND);
+
+ /* PCI Configuration Registers for OHCI */
+ devad = setup_bus_address(dev, PCI_BDF(0, 1, 0), 0);
+ writel(priv->mem_base + 0x0, devad + PCI_BASE_ADDRESS_0);
+ writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
+ devad + PCI_COMMAND);
+
+ /* PCI Configuration Registers for EHCI */
+ devad = setup_bus_address(dev, PCI_BDF(0, 2, 0), 0);
+ writel(priv->mem_base + 0x1000, devad + PCI_BASE_ADDRESS_0);
+ writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
+ devad + PCI_COMMAND);
+
+ /* Enable PCI interrupt */
+ setbits_le32(priv->cfg_base + RCAR_PCI_INT_ENABLE_REG,
+ RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME);
+
+ return 0;
+}
+
+static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
+
+ priv->cfg_base = devfdt_get_addr_index(dev, 0);
+ priv->mem_base = devfdt_get_addr_index(dev, 1);
+ if (!priv->cfg_base || !priv->mem_base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops rcar_gen2_pci_ops = {
+ .read_config = rcar_gen2_pci_read_config,
+ .write_config = rcar_gen2_pci_write_config,
+};
+
+static const struct udevice_id rcar_gen2_pci_ids[] = {
+ { .compatible = "renesas,pci-rcar-gen2" },
+ { }
+};
+
+U_BOOT_DRIVER(rcar_gen2_pci) = {
+ .name = "rcar_gen2_pci",
+ .id = UCLASS_PCI,
+ .of_match = rcar_gen2_pci_ids,
+ .ops = &rcar_gen2_pci_ops,
+ .probe = rcar_gen2_pci_probe,
+ .ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv),
+};
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
+source "drivers/pinctrl/broadcom/Kconfig"
endmenu
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
+obj-y += broadcom/
--- /dev/null
+config PINCTRL_BCM283X
+ depends on ARCH_BCM283X && PINCTRL_FULL && OF_CONTROL
+ default y
+ bool "Broadcom 283x family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Broadcom's 283x family of SoCs.
--- /dev/null
+#
+# Copyright (C) 2018 Alexander Graf <agraf@suse.de>
+#
+# SPDX-License-Identifier: GPL-2.0
+# https://spdx.org/licenses
+
+obj-$(CONFIG_PINCTRL_BCM283X) += pinctrl-bcm283x.o
--- /dev/null
+/*
+ * Copyright (C) 2018 Alexander Graf <agraf@suse.de>
+ *
+ * Based on drivers/pinctrl/mvebu/pinctrl-mvebu.c and
+ * drivers/gpio/bcm2835_gpio.c
+ *
+ * This driver gets instantiated by the GPIO driver, because both devices
+ * share the same device node.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <config.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+struct bcm283x_pinctrl_priv {
+ u32 *base_reg;
+};
+
+#define MAX_PINS_PER_BANK 16
+
+static void bcm2835_gpio_set_func_id(struct udevice *dev, unsigned int gpio,
+ int func)
+{
+ struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev);
+ int reg_offset;
+ int field_offset;
+
+ reg_offset = BCM2835_GPIO_FSEL_BANK(gpio);
+ field_offset = BCM2835_GPIO_FSEL_SHIFT(gpio);
+
+ clrsetbits_le32(&priv->base_reg[reg_offset],
+ BCM2835_GPIO_FSEL_MASK << field_offset,
+ (func & BCM2835_GPIO_FSEL_MASK) << field_offset);
+}
+
+static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio)
+{
+ struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]);
+
+ return (val >> BCM2835_GPIO_FSEL_SHIFT(gpio) & BCM2835_GPIO_FSEL_MASK);
+}
+
+/*
+ * bcm283x_pinctrl_set_state: configure pin functions.
+ * @dev: the pinctrl device to be configured.
+ * @config: the state to be configured.
+ * @return: 0 in success
+ */
+int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ u32 pin_arr[MAX_PINS_PER_BANK];
+ u32 function;
+ int i, len, pin_count = 0;
+
+ if (!dev_read_prop(config, "brcm,pins", &len) || !len ||
+ len & 0x3 || dev_read_u32_array(config, "brcm,pins", pin_arr,
+ len / sizeof(u32))) {
+ debug("Failed reading pins array for pinconfig %s (%d)\n",
+ config->name, len);
+ return -EINVAL;
+ }
+
+ pin_count = len / sizeof(u32);
+
+ function = dev_read_u32_default(config, "brcm,function", -1);
+ if (function < 0) {
+ debug("Failed reading function for pinconfig %s (%d)\n",
+ config->name, function);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < pin_count; i++)
+ bcm2835_gpio_set_func_id(dev, pin_arr[i], function);
+
+ return 0;
+}
+
+static int bcm283x_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+ int index)
+{
+ if (banknum != 0)
+ return -EINVAL;
+
+ return bcm2835_gpio_get_func_id(dev, index);
+}
+
+static const struct udevice_id bcm2835_pinctrl_id[] = {
+ {.compatible = "brcm,bcm2835-gpio"},
+ {}
+};
+
+int bcm283x_pinctl_probe(struct udevice *dev)
+{
+ struct bcm283x_pinctrl_priv *priv;
+ int ret;
+ struct udevice *pdev;
+
+ priv = dev_get_priv(dev);
+ if (!priv) {
+ debug("%s: Failed to get private\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->base_reg = dev_read_addr_ptr(dev);
+ if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+ debug("%s: Failed to get base address\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Create GPIO device as well */
+ ret = device_bind(dev, lists_driver_lookup_name("gpio_bcm2835"),
+ "gpio_bcm2835", NULL, dev_of_offset(dev), &pdev);
+ if (ret) {
+ /*
+ * While we really want the pinctrl driver to work to make
+ * devices go where they should go, the GPIO controller is
+ * not quite as crucial as it's only rarely used, so don't
+ * fail here.
+ */
+ printf("Failed to bind GPIO driver\n");
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops bcm283x_pinctrl_ops = {
+ .set_state = bcm283x_pinctrl_set_state,
+ .get_gpio_mux = bcm283x_pinctrl_get_gpio_mux,
+};
+
+U_BOOT_DRIVER(pinctrl_bcm283x) = {
+ .name = "bcm283x_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(bcm2835_pinctrl_id),
+ .priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
+ .ops = &bcm283x_pinctrl_ops,
+ .probe = bcm283x_pinctl_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
help
Enable support for clock present on Renesas RCar SoCs.
+config PINCTRL_PFC_R8A7790
+ bool "Renesas RCar Gen2 R8A7790 pin control driver"
+ def_bool y if R8A7790
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
+config PINCTRL_PFC_R8A7791
+ bool "Renesas RCar Gen2 R8A7791 pin control driver"
+ def_bool y if R8A7791
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
+config PINCTRL_PFC_R8A7792
+ bool "Renesas RCar Gen2 R8A7792 pin control driver"
+ def_bool y if R8A7792
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
+config PINCTRL_PFC_R8A7793
+ bool "Renesas RCar Gen2 R8A7793 pin control driver"
+ def_bool y if R8A7793
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
+config PINCTRL_PFC_R8A7794
+ bool "Renesas RCar Gen2 R8A7794 pin control driver"
+ def_bool y if R8A7794
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
def_bool y if R8A7795
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
--- /dev/null
+/*
+ * R8A7790 processor support
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+/*
+ * All pins assigned to GPIO bank 3 can be used for SD interfaces in
+ * which case they support both 3.3V and 1.8V signalling.
+ */
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_32(0, fn, sfx), \
+ PORT_GP_30(1, fn, sfx), \
+ PORT_GP_30(2, fn, sfx), \
+ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_32(5, fn, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+ FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+ FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+ FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+ FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+ FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+ FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+ FN_IP3_14_12, FN_IP3_17_15,
+
+ /* GPSR1 */
+ FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+ FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+ FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+ FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+ FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+ FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+ FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+ /* GPSR2 */
+ FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+ FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+ FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+ FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+ FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+ FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+ FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+ /* GPSR3 */
+ FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+ FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+ FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+ FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+ FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+ FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+ FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+ /* GPSR4 */
+ FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+ FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+ FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+ FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+ FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+ FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+ FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+ FN_IP14_15_12, FN_IP14_18_16,
+
+ /* GPSR5 */
+ FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+ FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+ FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+ FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+ FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+ FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+ FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+ /* IPSR0 */
+ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+ FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
+ FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
+ FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
+ FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
+ FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+ FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
+ FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+ FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
+ FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+ FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
+ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
+ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
+ FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+
+ /* IPSR1 */
+ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
+ FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
+ FN_SCIFA1_TXD_C, FN_AVB_TXD2,
+ FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
+ FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
+ FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+ FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+ FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+ FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+ FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
+ FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+ FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+ FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+ FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+ FN_A0, FN_PWM3, FN_A1, FN_PWM4,
+
+ /* IPSR2 */
+ FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
+ FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
+ FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
+ FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
+ FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+ FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+ FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
+ FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+ FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
+ FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+ FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
+
+ /* IPSR3 */
+ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+ FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
+ FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+ FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+ FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+ FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+ FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
+ FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
+ FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
+ FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
+ FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
+ FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
+ FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+
+ /* IPSR4 */
+ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
+ FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
+ FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
+ FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
+ FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+ FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
+ FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
+ FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+ FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+ FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
+ FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
+ FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
+ FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
+ FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+ FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
+
+ /* IPSR5 */
+ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+ FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+ FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
+ FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
+ FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
+ FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
+ FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
+ FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
+ FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
+ FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+ FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+ FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
+ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+ FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+ FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+ FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+ FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
+ FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
+ FN_SSI_WS78_B,
+
+ /* IPSR6 */
+ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+ FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+ FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+ FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+ FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+ FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+ FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
+ FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
+ FN_I2C2_SCL_E, FN_ETH_RX_ER,
+ FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+ FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
+ FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+ FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+ FN_HRX0_E, FN_STP_ISSYNC_0_B,
+ FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+ FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
+ FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+ FN_ETH_REF_CLK, FN_HCTS0_N_E,
+ FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+ /* IPSR7 */
+ FN_ETH_MDIO, FN_HRTS0_N_E,
+ FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+ FN_HTX0_F, FN_BPFCLK_G,
+ FN_ETH_TX_EN, FN_SIM0_CLK_C,
+ FN_HRTS0_N_F, FN_ETH_MAGIC,
+ FN_SIM0_RST_C, FN_ETH_TXD0,
+ FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+ FN_ETH_MDC, FN_STP_ISD_1_B,
+ FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+ FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+ FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+ FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+ FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+ FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
+ FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+ FN_ATACS00_N, FN_AVB_RXD1,
+ FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+
+ /* IPSR8 */
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+ FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+ FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+ FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+ FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+ FN_VI1_CLK, FN_AVB_RX_DV,
+ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+ FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
+ FN_SCIFA1_RXD_D, FN_AVB_MDC,
+ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+ FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+ FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+ FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
+ FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+ FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+ /* IPSR9 */
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
+ FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+ FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
+ FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+ FN_AVB_TX_EN, FN_SD1_CMD,
+ FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
+ FN_SD1_DAT0, FN_AVB_TX_CLK,
+ FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+ FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+ FN_AVB_COL, FN_SCIFB0_CTS_N_B,
+ FN_SD1_DAT3, FN_AVB_RXD0,
+ FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+ FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+ FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
+ FN_VI3_CLK_B,
+
+ /* IPSR10 */
+ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+ FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
+ FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+ FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
+ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
+ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+ FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+ FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+ FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+ FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+ FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+ /* IPSR11 */
+ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+ FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+ FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+ FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+ FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+ FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+ FN_FMIN_E, FN_FMIN_F,
+ FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
+ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
+ FN_I2C2_SDA_B, FN_MLB_DAT,
+ FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+ FN_SSI_SCK0129, FN_CAN_CLK_B,
+ FN_MOUT0,
+
+ /* IPSR12 */
+ FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
+ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
+ FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
+ FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+ FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+ FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
+ FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+ FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
+ FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
+ FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+ FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
+ FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+ FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
+ FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+ FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
+ FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+ FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
+ FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+ FN_CAN_DEBUGOUT4,
+
+ /* IPSR13 */
+ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+ FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
+ FN_SCIFB1_CTS_N, FN_BPFCLK_D,
+ FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+ FN_BPFCLK_F, FN_SSI_WS6,
+ FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+ FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
+ FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
+ FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
+ FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
+ FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
+ FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
+ FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
+ FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+ FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
+ FN_BPFCLK_E, FN_SSI_SDATA7_B,
+ FN_FMIN_G, FN_SSI_SDATA8,
+ FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+ FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
+ FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+ FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
+ FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
+
+ /* IPSR14 */
+ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+ FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+ FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
+ FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
+ FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
+ FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
+ FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
+ FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
+ FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
+ FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
+ FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
+ FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+ FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+ FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
+ FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
+ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
+ FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+ FN_HRTS0_N_C,
+
+ /* IPSR15 */
+ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
+ FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
+ FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
+ FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
+ FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
+ FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
+ FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
+ FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
+ FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
+ FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+ FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
+ FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
+ FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
+ FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
+ FN_DU2_DG6, FN_LCDOUT14,
+
+ /* IPSR16 */
+ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+ FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
+ FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+ FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
+ FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
+ FN_TCLK1_B,
+
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ FN_SEL_SCIF1_4,
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+ FN_SEL_SCIFB1_4,
+ FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+ FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+ FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+ FN_SEL_VI3_0, FN_SEL_VI3_1,
+ FN_SEL_VI2_0, FN_SEL_VI2_1,
+ FN_SEL_VI1_0, FN_SEL_VI1_1,
+ FN_SEL_VI0_0, FN_SEL_VI0_1,
+ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+ FN_SEL_LBS_0, FN_SEL_LBS_1,
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
+ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ FN_SEL_SSP_0, FN_SEL_SSP_1,
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+ FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+ FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+ FN_SEL_IIC2_4,
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ FN_SEL_I2C2_4,
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+ VI1_DATA7_VI1_B7_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+ USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+ DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+ D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+ D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+ VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+ VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+ VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+ SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+ VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+ SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+ VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+ IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+ I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
+ VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
+ D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
+ VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+ D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
+ VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+ SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
+ VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+ SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
+ VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+ D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+ VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+ D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+ VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+ SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+ VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+ D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+ VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+ A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+ A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+ PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+ TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+ A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+ SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+ A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+ VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
+ A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+ VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
+ A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+ VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+ A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+ VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+ A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+ VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+ A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+ MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+ VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+ ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+ ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+ A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+ AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+ ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+ VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+ A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+ A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+ VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+ VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+ VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+ VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+ VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+ VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+ CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+ VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+ VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+ MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+ HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+ VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+ VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+ EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+ VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+ EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+ VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
+ INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+ MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+ VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
+ I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+ CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+ CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+ VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+ INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+ VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+ WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+ VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+ VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+ MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+ VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+ SSI_WS78_B_MARK,
+
+ DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+ VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+ DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+ SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+ INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+ DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+ MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+ SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+ ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+ TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
+ I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
+ STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+ IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
+ STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+ SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+ HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+ TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+ RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
+ STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+ ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
+ STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+ ETH_MDIO_MARK, HRTS0_N_E_MARK,
+ SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+ HTX0_F_MARK, BPFCLK_G_MARK,
+ ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
+ HRTS0_N_F_MARK, ETH_MAGIC_MARK,
+ SIM0_RST_C_MARK, ETH_TXD0_MARK,
+ STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+ ETH_MDC_MARK, STP_ISD_1_B_MARK,
+ TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+ SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+ GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+ STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+ PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+ PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
+ AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+ ATACS00_N_MARK, AVB_RXD1_MARK,
+ VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+
+ VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+ VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+ AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+ AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+ AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+ AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+ VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+ VI1_CLK_MARK, AVB_RX_DV_MARK,
+ VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+ AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+ SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
+ VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+ VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+ AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+ AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+ AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+ SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+ SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+ SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+ SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+ SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+ SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+ SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+ GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
+ I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+ MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+ GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
+ I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+ AVB_TX_EN_MARK, SD1_CMD_MARK,
+ AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+ SD1_DAT0_MARK, AVB_TX_CLK_MARK,
+ SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+ SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+ AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
+ SD1_DAT3_MARK, AVB_RXD0_MARK,
+ SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+ TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+ IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
+ VI3_CLK_B_MARK,
+
+ SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+ GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
+ SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+ VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+ VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+ VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+ TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+ SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+ VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+ TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+ SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
+ VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+ TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+ SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
+ VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+ GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+ MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+ HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+ VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+ TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+ VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+ GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+ SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+ GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+ TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+ SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+ MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+ SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+ MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+ SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+ VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+ MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+ FMIN_E_MARK, FMIN_F_MARK,
+ MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
+ MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
+ I2C2_SDA_B_MARK, MLB_DAT_MARK,
+ SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+ SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+ MOUT0_MARK,
+
+ SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+ SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+ SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+ SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+ SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+ MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+ STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+ CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+ SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+ SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+ MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+ SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+ MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+ SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+ CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+ IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+ CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+ IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+ CAN_DEBUGOUT4_MARK,
+
+ SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+ LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+ SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
+ DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+ BPFCLK_F_MARK, SSI_WS6_MARK,
+ SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+ LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+ FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+ CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+ SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+ CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+ SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+ LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+ STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+ TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+ BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
+ FMIN_G_MARK, SSI_SDATA8_MARK,
+ STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+ CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+ STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+ SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+ SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+ AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+ DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+ REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+ MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
+ I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+ DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+ TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+ HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+ LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
+ SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
+ MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+ SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+ DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+ LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+ CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+ SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
+ MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+ HRTS0_N_C_MARK,
+
+ SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+ LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+ TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
+ SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+ IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+ DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+ DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+ LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+ LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+ LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+ DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+ SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+ HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+ DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+ DU2_DG6_MARK, LCDOUT14_MARK,
+
+ MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+ DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+ MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+ ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
+ USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+ TCLK1_B_MARK,
+
+ IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
+ IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
+ PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_SINGLE(VI1_DATA7_VI1_B7),
+ PINMUX_SINGLE(USB0_PWEN),
+ PINMUX_SINGLE(USB0_OVC_VBUS),
+ PINMUX_SINGLE(USB2_PWEN),
+ PINMUX_SINGLE(USB2_OVC),
+ PINMUX_SINGLE(AVS1),
+ PINMUX_SINGLE(AVS2),
+ PINMUX_SINGLE(DU_DOTCLKIN0),
+ PINMUX_SINGLE(DU_DOTCLKIN2),
+
+ PINMUX_IPSR_GPSR(IP0_2_0, D0),
+ PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
+ PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
+ PINMUX_IPSR_GPSR(IP0_5_3, D1),
+ PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
+ PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
+ PINMUX_IPSR_GPSR(IP0_8_6, D2),
+ PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
+ PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
+ PINMUX_IPSR_GPSR(IP0_11_9, D3),
+ PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
+ PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
+ PINMUX_IPSR_GPSR(IP0_15_12, D4),
+ PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
+ PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_GPSR(IP0_19_16, D5),
+ PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
+ PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_GPSR(IP0_22_20, D6),
+ PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
+ PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
+ PINMUX_IPSR_GPSR(IP0_26_23, D7),
+ PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
+ PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
+ PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
+ PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
+ PINMUX_IPSR_GPSR(IP0_30_27, D8),
+ PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
+ PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
+
+ PINMUX_IPSR_GPSR(IP1_3_0, D9),
+ PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
+ PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_7_4, D10),
+ PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
+ PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_11_8, D11),
+ PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
+ PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_14_12, D12),
+ PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
+ PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_17_15, D13),
+ PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
+ PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_21_18, D14),
+ PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
+ PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
+ PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_25_22, D15),
+ PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
+ PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
+ PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
+ PINMUX_IPSR_GPSR(IP1_27_26, A0),
+ PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
+ PINMUX_IPSR_GPSR(IP1_29_28, A1),
+ PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
+
+ PINMUX_IPSR_GPSR(IP2_2_0, A2),
+ PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
+ PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
+ PINMUX_IPSR_GPSR(IP2_5_3, A3),
+ PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
+ PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
+ PINMUX_IPSR_GPSR(IP2_8_6, A4),
+ PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
+ PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP2_11_9, A5),
+ PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP2_14_12, A6),
+ PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP2_17_15, A7),
+ PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
+ PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP2_21_18, A8),
+ PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
+ PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP2_25_22, A9),
+ PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
+ PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP2_28_26, A10),
+ PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
+ PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
+ PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
+
+ PINMUX_IPSR_GPSR(IP3_3_0, A11),
+ PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
+ PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
+ PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP3_7_4, A12),
+ PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
+ PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
+ PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP3_11_8, A13),
+ PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
+ PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
+ PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP3_14_12, A14),
+ PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
+ PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP3_17_15, A15),
+ PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
+ PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP3_19_18, A16),
+ PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
+ PINMUX_IPSR_GPSR(IP3_22_20, A17),
+ PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
+ PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
+ PINMUX_IPSR_GPSR(IP3_25_23, A18),
+ PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
+ PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
+ PINMUX_IPSR_GPSR(IP3_28_26, A19),
+ PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
+ PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
+ PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
+ PINMUX_IPSR_GPSR(IP3_31_29, A20),
+ PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
+ PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
+
+ PINMUX_IPSR_GPSR(IP4_2_0, A21),
+ PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
+ PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
+ PINMUX_IPSR_GPSR(IP4_5_3, A22),
+ PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
+ PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
+ PINMUX_IPSR_GPSR(IP4_8_6, A23),
+ PINMUX_IPSR_GPSR(IP4_8_6, IO2),
+ PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
+ PINMUX_IPSR_GPSR(IP4_11_9, A24),
+ PINMUX_IPSR_GPSR(IP4_11_9, IO3),
+ PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
+ PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP4_14_12, A25),
+ PINMUX_IPSR_GPSR(IP4_14_12, SSL),
+ PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
+ PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
+ PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
+ PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
+ PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
+ PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
+ PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
+ PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
+ PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
+ PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
+ PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
+ PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
+ PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
+ PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
+ PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
+
+ PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
+ PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
+ PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
+ PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
+ PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
+ PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
+ PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
+ PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
+ PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
+ PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
+ PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
+ PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
+ PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
+ PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
+ PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
+ PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
+ PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
+ PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
+ PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
+ PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
+ PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
+ PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
+ PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
+ PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
+ PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
+ PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
+ PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
+ PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
+ PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
+ PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
+ PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
+ PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
+ PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
+ PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
+ PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
+ PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
+ PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
+ PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
+ PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
+ PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
+
+ PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
+ PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
+ PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
+ PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+ PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
+ PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+ PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+ PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
+ PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
+ PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
+ PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+ PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
+ PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
+ PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
+ PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
+ PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
+ PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
+ PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
+ PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
+ PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
+ PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
+ PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
+ PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+ PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+ PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
+ PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+ PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+ PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
+ PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
+ PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+ PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+ PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
+ PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
+ PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+ PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+ PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
+ PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+ PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+ PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+ PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
+ PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
+ PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
+ PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
+ PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+ PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+ PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
+ PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+ PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
+ PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+ PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
+ PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+ PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
+ PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+ PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+ PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
+ PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+ PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+ PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+ PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
+ PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
+ PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
+ PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+ PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
+ PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
+ PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
+ PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
+ PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
+ PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
+ PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
+ PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
+
+ PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
+ PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
+ PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
+ PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
+ PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
+ PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
+ PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
+ PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
+ PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
+ PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
+ PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
+ PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+ PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
+ PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
+ PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
+ PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
+ PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
+ PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
+ PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+ PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+ PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
+ PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
+ PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
+ PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
+ PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
+ PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+ PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
+ PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
+ PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
+ PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
+ PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
+ PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
+ PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
+ PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
+ PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
+ PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
+ PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
+ PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
+ PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
+ PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
+ PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+ PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
+ PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
+ PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
+ PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
+ PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
+ PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
+ PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
+ PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
+ PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
+ PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
+ PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
+ PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
+ PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
+ PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
+ PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+ PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
+ PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
+ PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
+ PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+ PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+ PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
+ PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
+ PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+ PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
+ PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
+ PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
+ PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+ PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
+ PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+ PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
+ PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
+ PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
+ PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
+ PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
+ PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
+ PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+ PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
+ PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
+ PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
+ PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
+ PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
+ PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
+ PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
+ PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
+ PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+ PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
+ PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
+ PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
+ PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+ PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+ PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+ PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
+ PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
+ PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
+ PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
+ PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
+ PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
+ PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
+ PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
+ PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
+ PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
+ PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
+ PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
+ PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
+ PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
+ PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
+ PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
+ PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
+ PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
+ PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
+ PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+ PINMUX_IPSR_GPSR(IP11_17_15, VSP),
+ PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+ PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
+ PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
+ PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+ PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
+ PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
+ PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
+ PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
+ PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
+ PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
+ PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
+ PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
+ PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
+ PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+ PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
+
+ PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
+ PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
+ PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
+ PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
+ PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
+ PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
+ PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
+ PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
+ PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
+ PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
+ PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
+ PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
+ PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
+ PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+ PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
+ PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
+ PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
+ PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
+ PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
+ PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
+ PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
+ PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
+ PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
+ PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
+ PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
+ PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
+ PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
+ PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
+ PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
+ PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
+ PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
+ PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
+ PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
+ PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+ PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
+ PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
+ PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
+ PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+ PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
+
+ PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
+ PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
+ PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
+ PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
+ PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
+ PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
+ PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
+ PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
+ PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
+ PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
+ PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
+ PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
+ PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
+ PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
+ PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
+ PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
+ PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
+ PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
+ PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
+ PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
+ PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
+ PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
+ PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
+ PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
+ PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
+ PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
+ PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
+ PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
+ PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
+ PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+ PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
+ PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
+ PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
+ PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
+ PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
+ PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
+ PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
+ PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
+ PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
+ PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
+ PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
+ PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
+ PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
+
+ PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
+ PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
+ PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
+ PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
+ PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
+ PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
+ PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
+ PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
+ PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
+ PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
+ PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
+ PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
+ PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
+ PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
+ PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
+ PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
+ PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
+ PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
+ PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
+ PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
+ PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
+ PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
+ PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
+ PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
+ PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
+ PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
+ PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
+ PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
+ PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
+ PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
+ PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
+ PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
+ PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
+ PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
+ PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
+ PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
+ PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
+ PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
+ PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
+ PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
+ PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
+ PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
+ PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
+ PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
+ PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
+ PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
+ PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
+
+ PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
+ PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
+ PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
+ PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
+ PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
+ PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
+ PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
+ PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
+ PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
+ PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
+ PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
+ PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
+ PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
+ PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
+ PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
+ PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
+ PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
+ PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
+ PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
+ PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
+ PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
+ PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
+ PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
+ PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
+ PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
+ PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
+ PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
+ PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
+ PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
+ PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
+ PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
+ PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
+ PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
+ PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
+ PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
+ PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
+ PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
+ PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
+ PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
+ PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
+ PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
+ PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
+ PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
+
+ PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
+ PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
+ PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
+ PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
+ PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
+ PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
+ PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
+ PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
+ PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
+ PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
+ PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
+ PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
+ PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
+
+ PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
+ PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
+ PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
+ PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
+
+ PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
+ PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
+ PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
+ PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
+};
+
+/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+
+ /* Pins not associated with a GPIO port */
+ SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
+ SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
+ SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
+ SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
+};
+
+/* - AUDIO CLOCK ------------------------------------------------------------ */
+static const unsigned int audio_clk_a_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(4, 25),
+};
+static const unsigned int audio_clk_a_mux[] = {
+ AUDIO_CLKA_MARK,
+};
+static const unsigned int audio_clk_b_pins[] = {
+ /* CLK B */
+ RCAR_GP_PIN(4, 26),
+};
+static const unsigned int audio_clk_b_mux[] = {
+ AUDIO_CLKB_MARK,
+};
+static const unsigned int audio_clk_c_pins[] = {
+ /* CLK C */
+ RCAR_GP_PIN(5, 27),
+};
+static const unsigned int audio_clk_c_mux[] = {
+ AUDIO_CLKC_MARK,
+};
+static const unsigned int audio_clkout_pins[] = {
+ /* CLK OUT */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int audio_clkout_mux[] = {
+ AUDIO_CLKOUT_MARK,
+};
+static const unsigned int audio_clkout_b_pins[] = {
+ /* CLK OUT B */
+ RCAR_GP_PIN(0, 23),
+};
+static const unsigned int audio_clkout_b_mux[] = {
+ AUDIO_CLKOUT_B_MARK,
+};
+static const unsigned int audio_clkout_c_pins[] = {
+ /* CLK OUT C */
+ RCAR_GP_PIN(5, 27),
+};
+static const unsigned int audio_clkout_c_mux[] = {
+ AUDIO_CLKOUT_C_MARK,
+};
+static const unsigned int audio_clkout_d_pins[] = {
+ /* CLK OUT D */
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int audio_clkout_d_mux[] = {
+ AUDIO_CLKOUT_D_MARK,
+};
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 11),
+
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ RCAR_GP_PIN(2, 2),
+
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
+ RCAR_GP_PIN(3, 12),
+};
+static const unsigned int avb_mii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
+ AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
+ RCAR_GP_PIN(3, 12),
+};
+static const unsigned int avb_gmii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+ AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+ AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+ AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+ AVB_COL_MARK,
+};
+/* - DU RGB ----------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
+ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
+ DU2_DR3_MARK, DU2_DR2_MARK,
+ DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
+ DU2_DG3_MARK, DU2_DG2_MARK,
+ DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
+ DU2_DB3_MARK, DU2_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
+ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
+ RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
+ DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
+ DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
+ DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
+ DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
+ DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU0_DOTCLKOUT_MARK
+};
+static const unsigned int du_clk_out_1_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int du_clk_out_1_mux[] = {
+ DU1_DOTCLKOUT_MARK
+};
+static const unsigned int du_sync_0_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
+};
+static const unsigned int du_sync_0_mux[] = {
+ DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
+ DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du_sync_1_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int du_sync_1_mux[] = {
+ DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
+ DU2_DISP_MARK
+};
+static const unsigned int du_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(5, 17),
+};
+static const unsigned int du_cde_mux[] = {
+ DU2_CDE_MARK,
+};
+/* - DU0 -------------------------------------------------------------------- */
+static const unsigned int du0_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(5, 26),
+};
+static const unsigned int du0_clk_in_mux[] = {
+ DU_DOTCLKIN0_MARK
+};
+/* - DU1 -------------------------------------------------------------------- */
+static const unsigned int du1_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(5, 27),
+};
+static const unsigned int du1_clk_in_mux[] = {
+ DU_DOTCLKIN1_MARK,
+};
+/* - DU2 -------------------------------------------------------------------- */
+static const unsigned int du2_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(5, 28),
+};
+static const unsigned int du2_clk_in_mux[] = {
+ DU_DOTCLKIN2_MARK,
+};
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+ /* LINK */
+ RCAR_GP_PIN(2, 22),
+};
+static const unsigned int eth_link_mux[] = {
+ ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+ /* MAGIC */
+ RCAR_GP_PIN(2, 27),
+};
+static const unsigned int eth_magic_mux[] = {
+ ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+ /* MDC, MDIO */
+ RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int eth_mdio_mux[] = {
+ ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
+ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int eth_rmii_mux[] = {
+ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
+};
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 7),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+static const unsigned int hscif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int hscif0_data_b_mux[] = {
+ HRX0_B_MARK, HTX0_B_MARK,
+};
+static const unsigned int hscif0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
+};
+static const unsigned int hscif0_ctrl_b_mux[] = {
+ HRTS0_N_B_MARK, HCTS0_N_B_MARK,
+};
+static const unsigned int hscif0_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int hscif0_data_c_mux[] = {
+ HRX0_C_MARK, HTX0_C_MARK,
+};
+static const unsigned int hscif0_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
+};
+static const unsigned int hscif0_ctrl_c_mux[] = {
+ HRTS0_N_C_MARK, HCTS0_N_C_MARK,
+};
+static const unsigned int hscif0_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int hscif0_data_d_mux[] = {
+ HRX0_D_MARK, HTX0_D_MARK,
+};
+static const unsigned int hscif0_ctrl_d_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
+};
+static const unsigned int hscif0_ctrl_d_mux[] = {
+ HRTS0_N_D_MARK, HCTS0_N_D_MARK,
+};
+static const unsigned int hscif0_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int hscif0_data_e_mux[] = {
+ HRX0_E_MARK, HTX0_E_MARK,
+};
+static const unsigned int hscif0_ctrl_e_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int hscif0_ctrl_e_mux[] = {
+ HRTS0_N_E_MARK, HCTS0_N_E_MARK,
+};
+static const unsigned int hscif0_data_f_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
+};
+static const unsigned int hscif0_data_f_mux[] = {
+ HRX0_F_MARK, HTX0_F_MARK,
+};
+static const unsigned int hscif0_ctrl_f_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int hscif0_ctrl_f_mux[] = {
+ HRTS0_N_F_MARK, HCTS0_N_F_MARK,
+};
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 27),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+static const unsigned int hscif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int hscif1_data_b_mux[] = {
+ HRX1_B_MARK, HTX1_B_MARK,
+};
+static const unsigned int hscif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 28),
+};
+static const unsigned int hscif1_clk_b_mux[] = {
+ HSCK1_B_MARK,
+};
+static const unsigned int hscif1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int hscif1_ctrl_b_mux[] = {
+ HRTS1_N_B_MARK, HCTS1_N_B_MARK,
+};
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
+};
+static const unsigned int i2c0_mux[] = {
+ I2C0_SCL_MARK, I2C0_SDA_MARK,
+};
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int i2c1_mux[] = {
+ I2C1_SCL_MARK, I2C1_SDA_MARK,
+};
+static const unsigned int i2c1_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int i2c1_b_mux[] = {
+ I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
+};
+static const unsigned int i2c1_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int i2c1_c_mux[] = {
+ I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
+};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int i2c2_mux[] = {
+ I2C2_SCL_MARK, I2C2_SDA_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int i2c2_b_mux[] = {
+ I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
+};
+static const unsigned int i2c2_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int i2c2_c_mux[] = {
+ I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
+};
+static const unsigned int i2c2_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c2_d_mux[] = {
+ I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
+};
+static const unsigned int i2c2_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+static const unsigned int i2c2_e_mux[] = {
+ I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
+};
+static const unsigned int i2c3_mux[] = {
+ I2C3_SCL_MARK, I2C3_SDA_MARK,
+};
+/* - IIC0 (I2C4) ------------------------------------------------------------ */
+static const unsigned int iic0_pins[] = {
+ /* SCL, SDA */
+ PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
+};
+static const unsigned int iic0_mux[] = {
+ IIC0_SCL_MARK, IIC0_SDA_MARK,
+};
+/* - IIC1 (I2C5) ------------------------------------------------------------ */
+static const unsigned int iic1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int iic1_mux[] = {
+ IIC1_SCL_MARK, IIC1_SDA_MARK,
+};
+static const unsigned int iic1_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int iic1_b_mux[] = {
+ IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
+};
+static const unsigned int iic1_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int iic1_c_mux[] = {
+ IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
+};
+/* - IIC2 (I2C6) ------------------------------------------------------------ */
+static const unsigned int iic2_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int iic2_mux[] = {
+ IIC2_SCL_MARK, IIC2_SDA_MARK,
+};
+static const unsigned int iic2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int iic2_b_mux[] = {
+ IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
+};
+static const unsigned int iic2_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int iic2_c_mux[] = {
+ IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
+};
+static const unsigned int iic2_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int iic2_d_mux[] = {
+ IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
+};
+static const unsigned int iic2_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+static const unsigned int iic2_e_mux[] = {
+ IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
+};
+/* - IIC3 (I2C7) ------------------------------------------------------------ */
+static const unsigned int iic3_pins[] = {
+/* SCL, SDA */
+ PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
+};
+static const unsigned int iic3_mux[] = {
+ IIC3_SCL_MARK, IIC3_SDA_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(1, 29),
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+/* - MLB+ ------------------------------------------------------------------- */
+static const unsigned int mlb_3pin_pins[] = {
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int mlb_3pin_mux[] = {
+ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
+};
+/* - MMCIF0 ----------------------------------------------------------------- */
+static const unsigned int mmc0_data1_pins[] = {
+ /* D[0] */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int mmc0_data1_mux[] = {
+ MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int mmc0_data4_mux[] = {
+ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc0_data8_mux[] = {
+ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+ MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+ MMC0_CLK_MARK, MMC0_CMD_MARK,
+};
+/* - MMCIF1 ----------------------------------------------------------------- */
+static const unsigned int mmc1_data1_pins[] = {
+ /* D[0] */
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int mmc1_data1_mux[] = {
+ MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int mmc1_data4_mux[] = {
+ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int mmc1_data8_mux[] = {
+ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+ MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+ MMC1_CLK_MARK, MMC1_CMD_MARK,
+};
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(5, 14),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(5, 17),
+};
+static const unsigned int msiof0_rx_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+static const unsigned int msiof0_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(5, 15),
+};
+static const unsigned int msiof0_tx_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+
+static const unsigned int msiof0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof0_clk_b_mux[] = {
+ MSIOF0_SCK_B_MARK,
+};
+static const unsigned int msiof0_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(1, 12),
+};
+static const unsigned int msiof0_ss1_b_mux[] = {
+ MSIOF0_SS1_B_MARK,
+};
+static const unsigned int msiof0_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof0_ss2_b_mux[] = {
+ MSIOF0_SS2_B_MARK,
+};
+static const unsigned int msiof0_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(1, 29),
+};
+static const unsigned int msiof0_rx_b_mux[] = {
+ MSIOF0_RXD_B_MARK,
+};
+static const unsigned int msiof0_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(1, 28),
+};
+static const unsigned int msiof0_tx_b_mux[] = {
+ MSIOF0_TXD_B_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 8),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(4, 9),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(4, 10),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(4, 11),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(4, 13),
+};
+static const unsigned int msiof1_rx_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+static const unsigned int msiof1_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(4, 12),
+};
+static const unsigned int msiof1_tx_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+
+static const unsigned int msiof1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int msiof1_clk_b_mux[] = {
+ MSIOF1_SCK_B_MARK,
+};
+static const unsigned int msiof1_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof1_ss1_b_mux[] = {
+ MSIOF1_SS1_B_MARK,
+};
+static const unsigned int msiof1_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int msiof1_ss2_b_mux[] = {
+ MSIOF1_SS2_B_MARK,
+};
+static const unsigned int msiof1_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int msiof1_rx_b_mux[] = {
+ MSIOF1_RXD_B_MARK,
+};
+static const unsigned int msiof1_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int msiof1_tx_b_mux[] = {
+ MSIOF1_TXD_B_MARK,
+};
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 27),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 26),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 30),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 31),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 29),
+};
+static const unsigned int msiof2_rx_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+static const unsigned int msiof2_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 28),
+};
+static const unsigned int msiof2_tx_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(4, 30),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(4, 31),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(4, 27),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int msiof3_rx_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+static const unsigned int msiof3_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int msiof3_tx_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+
+static const unsigned int msiof3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int msiof3_clk_b_mux[] = {
+ MSIOF3_SCK_B_MARK,
+};
+static const unsigned int msiof3_sync_b_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_sync_b_mux[] = {
+ MSIOF3_SYNC_B_MARK,
+};
+static const unsigned int msiof3_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_rx_b_mux[] = {
+ MSIOF3_RXD_B_MARK,
+};
+static const unsigned int msiof3_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_tx_b_mux[] = {
+ MSIOF3_TXD_B_MARK,
+};
+/* - PWM -------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+ RCAR_GP_PIN(5, 29),
+};
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
+};
+static const unsigned int pwm0_b_pins[] = {
+ RCAR_GP_PIN(4, 30),
+};
+static const unsigned int pwm0_b_mux[] = {
+ PWM0_B_MARK,
+};
+static const unsigned int pwm1_pins[] = {
+ RCAR_GP_PIN(5, 30),
+};
+static const unsigned int pwm1_mux[] = {
+ PWM1_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ RCAR_GP_PIN(4, 31),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+static const unsigned int pwm2_pins[] = {
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int pwm2_mux[] = {
+ PWM2_MARK,
+};
+static const unsigned int pwm3_pins[] = {
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int pwm3_mux[] = {
+ PWM3_MARK,
+};
+static const unsigned int pwm4_pins[] = {
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int pwm4_mux[] = {
+ PWM4_MARK,
+};
+static const unsigned int pwm5_pins[] = {
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int pwm5_mux[] = {
+ PWM5_MARK,
+};
+static const unsigned int pwm6_pins[] = {
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int pwm6_mux[] = {
+ PWM6_MARK,
+};
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+ SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_MARK, CTS0_N_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif1_data_c_mux[] = {
+ RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif1_data_d_mux[] = {
+ RX1_D_MARK, TX1_D_MARK,
+};
+static const unsigned int scif1_clk_d_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scif1_clk_d_mux[] = {
+ SCK1_D_MARK,
+};
+static const unsigned int scif1_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif1_data_e_mux[] = {
+ RX1_E_MARK, TX1_E_MARK,
+};
+static const unsigned int scif1_clk_e_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scif1_clk_e_mux[] = {
+ SCK1_E_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scif2_data_b_mux[] = {
+ RX2_B_MARK, TX2_B_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa0_data_mux[] = {
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa0_clk_mux[] = {
+ SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+ SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+ SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scifa0_clk_b_mux[] = {
+ SCIFA0_SCK_B_MARK,
+};
+static const unsigned int scifa0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scifa0_ctrl_b_mux[] = {
+ SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scifa1_data_mux[] = {
+ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scifa1_clk_mux[] = {
+ SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+ SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+ SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+ SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa1_ctrl_b_mux[] = {
+ SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+ SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+ SCIFA1_SCK_C_MARK,
+};
+static const unsigned int scifa1_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scifa1_ctrl_c_mux[] = {
+ SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
+};
+static const unsigned int scifa1_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scifa1_data_d_mux[] = {
+ SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
+};
+static const unsigned int scifa1_clk_d_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scifa1_clk_d_mux[] = {
+ SCIFA1_SCK_D_MARK,
+};
+static const unsigned int scifa1_ctrl_d_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scifa1_ctrl_d_mux[] = {
+ SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa2_data_mux[] = {
+ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa2_clk_mux[] = {
+ SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+ SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+ SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
+};
+static const unsigned int scifa2_data_c_mux[] = {
+ SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
+};
+static const unsigned int scifa2_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 29),
+};
+static const unsigned int scifa2_clk_c_mux[] = {
+ SCIFA2_SCK_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scifb0_data_mux[] = {
+ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifb0_clk_mux[] = {
+ SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+ SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+ SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+ SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+ SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+ SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int scifb1_data_mux[] = {
+ SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 14),
+};
+static const unsigned int scifb1_clk_mux[] = {
+ SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+ SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+ SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+ SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+ SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+ SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+ SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+static const unsigned int scifb1_data_e_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scifb1_data_e_mux[] = {
+ SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
+};
+static const unsigned int scifb1_clk_e_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scifb1_clk_e_mux[] = {
+ SCIFB1_SCK_E_MARK,
+};
+static const unsigned int scifb1_data_f_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb1_data_f_mux[] = {
+ SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
+};
+static const unsigned int scifb1_data_g_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scifb1_data_g_mux[] = {
+ SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
+};
+static const unsigned int scifb1_clk_g_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scifb1_clk_g_mux[] = {
+ SCIFB1_SCK_G_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifb2_data_mux[] = {
+ SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifb2_clk_mux[] = {
+ SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+ SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+ SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+ SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+ SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+ SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(4, 26),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+ SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+ SD2_WP_MARK,
+};
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+ SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+ SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+ SD3_CLK_MARK, SD3_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 30),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+ SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 31),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+ SD3_WP_MARK,
+};
+/* - SSI -------------------------------------------------------------------- */
+static const unsigned int ssi0_data_pins[] = {
+ /* SDATA0 */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int ssi0_data_mux[] = {
+ SSI_SDATA0_MARK,
+};
+static const unsigned int ssi0129_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
+};
+static const unsigned int ssi0129_ctrl_mux[] = {
+ SSI_SCK0129_MARK, SSI_WS0129_MARK,
+};
+static const unsigned int ssi1_data_pins[] = {
+ /* SDATA1 */
+ RCAR_GP_PIN(4, 6),
+};
+static const unsigned int ssi1_data_mux[] = {
+ SSI_SDATA1_MARK,
+};
+static const unsigned int ssi1_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int ssi1_ctrl_mux[] = {
+ SSI_SCK1_MARK, SSI_WS1_MARK,
+};
+static const unsigned int ssi2_data_pins[] = {
+ /* SDATA2 */
+ RCAR_GP_PIN(4, 7),
+};
+static const unsigned int ssi2_data_mux[] = {
+ SSI_SDATA2_MARK,
+};
+static const unsigned int ssi2_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
+};
+static const unsigned int ssi2_ctrl_mux[] = {
+ SSI_SCK2_MARK, SSI_WS2_MARK,
+};
+static const unsigned int ssi3_data_pins[] = {
+ /* SDATA3 */
+ RCAR_GP_PIN(4, 10),
+};
+static const unsigned int ssi3_data_mux[] = {
+ SSI_SDATA3_MARK
+};
+static const unsigned int ssi34_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+};
+static const unsigned int ssi34_ctrl_mux[] = {
+ SSI_SCK34_MARK, SSI_WS34_MARK,
+};
+static const unsigned int ssi4_data_pins[] = {
+ /* SDATA4 */
+ RCAR_GP_PIN(4, 13),
+};
+static const unsigned int ssi4_data_mux[] = {
+ SSI_SDATA4_MARK,
+};
+static const unsigned int ssi4_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int ssi4_ctrl_mux[] = {
+ SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+static const unsigned int ssi5_pins[] = {
+ /* SDATA5, SCK, WS */
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int ssi5_mux[] = {
+ SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+static const unsigned int ssi5_b_pins[] = {
+ /* SDATA5, SCK, WS */
+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int ssi5_b_mux[] = {
+ SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
+};
+static const unsigned int ssi5_c_pins[] = {
+ /* SDATA5, SCK, WS */
+ RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int ssi5_c_mux[] = {
+ SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
+};
+static const unsigned int ssi6_pins[] = {
+ /* SDATA6, SCK, WS */
+ RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int ssi6_mux[] = {
+ SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+static const unsigned int ssi6_b_pins[] = {
+ /* SDATA6, SCK, WS */
+ RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
+};
+static const unsigned int ssi6_b_mux[] = {
+ SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
+};
+static const unsigned int ssi7_data_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int ssi7_data_mux[] = {
+ SSI_SDATA7_MARK,
+};
+static const unsigned int ssi7_b_data_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int ssi7_b_data_mux[] = {
+ SSI_SDATA7_B_MARK,
+};
+static const unsigned int ssi7_c_data_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int ssi7_c_data_mux[] = {
+ SSI_SDATA7_C_MARK,
+};
+static const unsigned int ssi78_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int ssi78_ctrl_mux[] = {
+ SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+static const unsigned int ssi78_b_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int ssi78_b_ctrl_mux[] = {
+ SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
+};
+static const unsigned int ssi78_c_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int ssi78_c_ctrl_mux[] = {
+ SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
+};
+static const unsigned int ssi8_data_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int ssi8_data_mux[] = {
+ SSI_SDATA8_MARK,
+};
+static const unsigned int ssi8_b_data_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int ssi8_b_data_mux[] = {
+ SSI_SDATA8_B_MARK,
+};
+static const unsigned int ssi8_c_data_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int ssi8_c_data_mux[] = {
+ SSI_SDATA8_C_MARK,
+};
+static const unsigned int ssi9_data_pins[] = {
+ /* SDATA9 */
+ RCAR_GP_PIN(4, 24),
+};
+static const unsigned int ssi9_data_mux[] = {
+ SSI_SDATA9_MARK,
+};
+static const unsigned int ssi9_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int ssi9_ctrl_mux[] = {
+ SSI_SCK9_MARK, SSI_WS9_MARK,
+};
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+ /* TO */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tpu0_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+ /* TO */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int tpu0_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+ /* TO */
+ RCAR_GP_PIN(0, 22),
+};
+static const unsigned int tpu0_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+ /* TO */
+ RCAR_GP_PIN(0, 23),
+};
+static const unsigned int tpu0_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ /* PWEN, OVC/VBUS */
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+};
+static const unsigned int usb0_mux[] = {
+ USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+};
+static const unsigned int usb0_ovc_vbus_pins[] = {
+ /* OVC/VBUS */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int usb0_ovc_vbus_mux[] = {
+ USB0_OVC_VBUS_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
+};
+static const unsigned int usb1_mux[] = {
+ USB1_PWEN_MARK, USB1_OVC_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
+};
+static const unsigned int usb2_mux[] = {
+ USB2_PWEN_MARK, USB2_OVC_MARK,
+};
+/* - VIN0 ------------------------------------------------------------------- */
+static const union vin_data vin0_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ /* G */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ /* R */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
+ },
+};
+static const union vin_data vin0_data_mux = {
+ .data24 = {
+ /* B */
+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G0_MARK, VI0_G1_MARK,
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R0_MARK, VI0_R1_MARK,
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
+ },
+};
+static const unsigned int vin0_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ /* G */
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ /* R */
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
+};
+static const unsigned int vin0_data18_mux[] = {
+ /* B */
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ RCAR_GP_PIN(0, 12), /* HSYNC */
+ RCAR_GP_PIN(0, 13), /* VSYNC */
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_HSYNC_N_MARK,
+ VI0_VSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ RCAR_GP_PIN(0, 15),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ RCAR_GP_PIN(0, 14),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const union vin_data vin1_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+ /* G */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
+ },
+};
+static const union vin_data vin1_data_mux = {
+ .data24 = {
+ /* B */
+ VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
+ VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
+ VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+ VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+ /* G */
+ VI1_G0_MARK, VI1_G1_MARK,
+ VI1_G2_MARK, VI1_G3_MARK,
+ VI1_G4_MARK, VI1_G5_MARK,
+ VI1_G6_MARK, VI1_G7_MARK,
+ /* R */
+ VI1_R0_MARK, VI1_R1_MARK,
+ VI1_R2_MARK, VI1_R3_MARK,
+ VI1_R4_MARK, VI1_R5_MARK,
+ VI1_R6_MARK, VI1_R7_MARK,
+ },
+};
+static const unsigned int vin1_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+ /* G */
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int vin1_data18_mux[] = {
+ /* B */
+ VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
+ VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+ VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+ /* G */
+ VI1_G2_MARK, VI1_G3_MARK,
+ VI1_G4_MARK, VI1_G5_MARK,
+ VI1_G6_MARK, VI1_G7_MARK,
+ /* R */
+ VI1_R2_MARK, VI1_R3_MARK,
+ VI1_R4_MARK, VI1_R5_MARK,
+ VI1_R6_MARK, VI1_R7_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+ RCAR_GP_PIN(1, 24), /* HSYNC */
+ RCAR_GP_PIN(1, 25), /* VSYNC */
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_HSYNC_N_MARK,
+ VI1_VSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ RCAR_GP_PIN(2, 9),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+/* - VIN2 ----------------------------------------------------------------- */
+static const union vin_data vin2_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ /* G */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
+ },
+};
+static const union vin_data vin2_data_mux = {
+ .data24 = {
+ /* B */
+ VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
+ VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
+ VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+ VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+ /* G */
+ VI2_G0_MARK, VI2_G1_MARK,
+ VI2_G2_MARK, VI2_G3_MARK,
+ VI2_G4_MARK, VI2_G5_MARK,
+ VI2_G6_MARK, VI2_G7_MARK,
+ /* R */
+ VI2_R0_MARK, VI2_R1_MARK,
+ VI2_R2_MARK, VI2_R3_MARK,
+ VI2_R4_MARK, VI2_R5_MARK,
+ VI2_R6_MARK, VI2_R7_MARK,
+ },
+};
+static const unsigned int vin2_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ /* G */
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int vin2_data18_mux[] = {
+ /* B */
+ VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
+ VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+ VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+ /* G */
+ VI2_G2_MARK, VI2_G3_MARK,
+ VI2_G4_MARK, VI2_G5_MARK,
+ VI2_G6_MARK, VI2_G7_MARK,
+ /* R */
+ VI2_R2_MARK, VI2_R3_MARK,
+ VI2_R4_MARK, VI2_R5_MARK,
+ VI2_R6_MARK, VI2_R7_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+ RCAR_GP_PIN(1, 16), /* HSYNC */
+ RCAR_GP_PIN(1, 21), /* VSYNC */
+};
+static const unsigned int vin2_sync_mux[] = {
+ VI2_HSYNC_N_MARK,
+ VI2_VSYNC_N_MARK,
+};
+static const unsigned int vin2_field_pins[] = {
+ RCAR_GP_PIN(1, 9),
+};
+static const unsigned int vin2_field_mux[] = {
+ VI2_FIELD_MARK,
+};
+static const unsigned int vin2_clkenb_pins[] = {
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int vin2_clkenb_mux[] = {
+ VI2_CLKENB_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int vin2_clk_mux[] = {
+ VI2_CLK_MARK,
+};
+/* - VIN3 ----------------------------------------------------------------- */
+static const unsigned int vin3_data8_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int vin3_data8_mux[] = {
+ VI3_DATA0_MARK, VI3_DATA1_MARK,
+ VI3_DATA2_MARK, VI3_DATA3_MARK,
+ VI3_DATA4_MARK, VI3_DATA5_MARK,
+ VI3_DATA6_MARK, VI3_DATA7_MARK,
+};
+static const unsigned int vin3_sync_pins[] = {
+ RCAR_GP_PIN(1, 16), /* HSYNC */
+ RCAR_GP_PIN(1, 17), /* VSYNC */
+};
+static const unsigned int vin3_sync_mux[] = {
+ VI3_HSYNC_N_MARK,
+ VI3_VSYNC_N_MARK,
+};
+static const unsigned int vin3_field_pins[] = {
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int vin3_field_mux[] = {
+ VI3_FIELD_MARK,
+};
+static const unsigned int vin3_clkenb_pins[] = {
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int vin3_clkenb_mux[] = {
+ VI3_CLKENB_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int vin3_clk_mux[] = {
+ VI3_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clk_a),
+ SH_PFC_PIN_GROUP(audio_clk_b),
+ SH_PFC_PIN_GROUP(audio_clk_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(audio_clkout_d),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync_0),
+ SH_PFC_PIN_GROUP(du_sync_1),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du2_clk_in),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif0_data_c),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_c),
+ SH_PFC_PIN_GROUP(hscif0_data_d),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_d),
+ SH_PFC_PIN_GROUP(hscif0_data_e),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_e),
+ SH_PFC_PIN_GROUP(hscif0_data_f),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_f),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_clk_b),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c2_e),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(iic0),
+ SH_PFC_PIN_GROUP(iic1),
+ SH_PFC_PIN_GROUP(iic1_b),
+ SH_PFC_PIN_GROUP(iic1_c),
+ SH_PFC_PIN_GROUP(iic2),
+ SH_PFC_PIN_GROUP(iic2_b),
+ SH_PFC_PIN_GROUP(iic2_c),
+ SH_PFC_PIN_GROUP(iic2_d),
+ SH_PFC_PIN_GROUP(iic2_e),
+ SH_PFC_PIN_GROUP(iic3),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(mlb_3pin),
+ SH_PFC_PIN_GROUP(mmc0_data1),
+ SH_PFC_PIN_GROUP(mmc0_data4),
+ SH_PFC_PIN_GROUP(mmc0_data8),
+ SH_PFC_PIN_GROUP(mmc0_ctrl),
+ SH_PFC_PIN_GROUP(mmc1_data1),
+ SH_PFC_PIN_GROUP(mmc1_data4),
+ SH_PFC_PIN_GROUP(mmc1_data8),
+ SH_PFC_PIN_GROUP(mmc1_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof0_clk_b),
+ SH_PFC_PIN_GROUP(msiof0_ss1_b),
+ SH_PFC_PIN_GROUP(msiof0_ss2_b),
+ SH_PFC_PIN_GROUP(msiof0_rx_b),
+ SH_PFC_PIN_GROUP(msiof0_tx_b),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_rx_b),
+ SH_PFC_PIN_GROUP(msiof1_tx_b),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_rx),
+ SH_PFC_PIN_GROUP(msiof3_tx),
+ SH_PFC_PIN_GROUP(msiof3_clk_b),
+ SH_PFC_PIN_GROUP(msiof3_sync_b),
+ SH_PFC_PIN_GROUP(msiof3_rx_b),
+ SH_PFC_PIN_GROUP(msiof3_tx_b),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+ SH_PFC_PIN_GROUP(pwm5),
+ SH_PFC_PIN_GROUP(pwm6),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_data_d),
+ SH_PFC_PIN_GROUP(scif1_clk_d),
+ SH_PFC_PIN_GROUP(scif1_data_e),
+ SH_PFC_PIN_GROUP(scif1_clk_e),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_clk),
+ SH_PFC_PIN_GROUP(scifa0_ctrl),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa0_clk_b),
+ SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_ctrl),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa1_clk_c),
+ SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+ SH_PFC_PIN_GROUP(scifa1_data_d),
+ SH_PFC_PIN_GROUP(scifa1_clk_d),
+ SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_ctrl),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa2_data_c),
+ SH_PFC_PIN_GROUP(scifa2_clk_c),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb0_data_b),
+ SH_PFC_PIN_GROUP(scifb0_clk_b),
+ SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb0_data_c),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb1_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data_b),
+ SH_PFC_PIN_GROUP(scifb1_clk_b),
+ SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb1_data_c),
+ SH_PFC_PIN_GROUP(scifb1_data_d),
+ SH_PFC_PIN_GROUP(scifb1_data_e),
+ SH_PFC_PIN_GROUP(scifb1_clk_e),
+ SH_PFC_PIN_GROUP(scifb1_data_f),
+ SH_PFC_PIN_GROUP(scifb1_data_g),
+ SH_PFC_PIN_GROUP(scifb1_clk_g),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scifb2_data_b),
+ SH_PFC_PIN_GROUP(scifb2_clk_b),
+ SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb2_data_c),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(sdhi3_data1),
+ SH_PFC_PIN_GROUP(sdhi3_data4),
+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
+ SH_PFC_PIN_GROUP(sdhi3_cd),
+ SH_PFC_PIN_GROUP(sdhi3_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi5),
+ SH_PFC_PIN_GROUP(ssi5_b),
+ SH_PFC_PIN_GROUP(ssi5_c),
+ SH_PFC_PIN_GROUP(ssi6),
+ SH_PFC_PIN_GROUP(ssi6_b),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi7_b_data),
+ SH_PFC_PIN_GROUP(ssi7_c_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi78_b_ctrl),
+ SH_PFC_PIN_GROUP(ssi78_c_ctrl),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_b_data),
+ SH_PFC_PIN_GROUP(ssi8_c_data),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(tpu0_to0),
+ SH_PFC_PIN_GROUP(tpu0_to1),
+ SH_PFC_PIN_GROUP(tpu0_to2),
+ SH_PFC_PIN_GROUP(tpu0_to3),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb0_ovc_vbus),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb2),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ VIN_DATA_PIN_GROUP(vin0_data, 4),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 24),
+ VIN_DATA_PIN_GROUP(vin1_data, 20),
+ SH_PFC_PIN_GROUP(vin1_data18),
+ VIN_DATA_PIN_GROUP(vin1_data, 16),
+ VIN_DATA_PIN_GROUP(vin1_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_data, 8),
+ VIN_DATA_PIN_GROUP(vin1_data, 4),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+ VIN_DATA_PIN_GROUP(vin2_data, 24),
+ SH_PFC_PIN_GROUP(vin2_data18),
+ VIN_DATA_PIN_GROUP(vin2_data, 16),
+ VIN_DATA_PIN_GROUP(vin2_data, 8),
+ VIN_DATA_PIN_GROUP(vin2_data, 4),
+ SH_PFC_PIN_GROUP(vin2_sync),
+ SH_PFC_PIN_GROUP(vin2_field),
+ SH_PFC_PIN_GROUP(vin2_clkenb),
+ SH_PFC_PIN_GROUP(vin2_clk),
+ SH_PFC_PIN_GROUP(vin3_data8),
+ SH_PFC_PIN_GROUP(vin3_sync),
+ SH_PFC_PIN_GROUP(vin3_field),
+ SH_PFC_PIN_GROUP(vin3_clkenb),
+ SH_PFC_PIN_GROUP(vin3_clk),
+};
+
+static const char * const audio_clk_groups[] = {
+ "audio_clk_a",
+ "audio_clk_b",
+ "audio_clk_c",
+ "audio_clkout",
+ "audio_clkout_b",
+ "audio_clkout_c",
+ "audio_clkout_d",
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_mii",
+ "avb_gmii",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_out_0",
+ "du_clk_out_1",
+ "du_sync_0",
+ "du_sync_1",
+ "du_cde",
+};
+
+static const char * const du0_groups[] = {
+ "du0_clk_in",
+};
+
+static const char * const du1_groups[] = {
+ "du1_clk_in",
+};
+
+static const char * const du2_groups[] = {
+ "du2_clk_in",
+};
+
+static const char * const eth_groups[] = {
+ "eth_link",
+ "eth_magic",
+ "eth_mdio",
+ "eth_rmii",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+ "hscif0_data_b",
+ "hscif0_ctrl_b",
+ "hscif0_data_c",
+ "hscif0_ctrl_c",
+ "hscif0_data_d",
+ "hscif0_ctrl_d",
+ "hscif0_data_e",
+ "hscif0_ctrl_e",
+ "hscif0_data_f",
+ "hscif0_ctrl_f",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+ "hscif1_data_b",
+ "hscif1_clk_b",
+ "hscif1_ctrl_b",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+ "i2c1_b",
+ "i2c1_c",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+ "i2c2_b",
+ "i2c2_c",
+ "i2c2_d",
+ "i2c2_e",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const iic0_groups[] = {
+ "iic0",
+};
+
+static const char * const iic1_groups[] = {
+ "iic1",
+ "iic1_b",
+ "iic1_c",
+};
+
+static const char * const iic2_groups[] = {
+ "iic2",
+ "iic2_b",
+ "iic2_c",
+ "iic2_d",
+ "iic2_e",
+};
+
+static const char * const iic3_groups[] = {
+ "iic3",
+};
+
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq1",
+ "intc_irq2",
+ "intc_irq3",
+};
+
+static const char * const mlb_groups[] = {
+ "mlb_3pin",
+};
+
+static const char * const mmc0_groups[] = {
+ "mmc0_data1",
+ "mmc0_data4",
+ "mmc0_data8",
+ "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+ "mmc1_data1",
+ "mmc1_data4",
+ "mmc1_data8",
+ "mmc1_ctrl",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_rx",
+ "msiof0_tx",
+ "msiof0_clk_b",
+ "msiof0_ss1_b",
+ "msiof0_ss2_b",
+ "msiof0_rx_b",
+ "msiof0_tx_b",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_rx",
+ "msiof1_tx",
+ "msiof1_clk_b",
+ "msiof1_ss1_b",
+ "msiof1_ss2_b",
+ "msiof1_rx_b",
+ "msiof1_tx_b",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_rx",
+ "msiof2_tx",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_rx",
+ "msiof3_tx",
+ "msiof3_clk_b",
+ "msiof3_sync_b",
+ "msiof3_rx_b",
+ "msiof3_tx_b",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0",
+ "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4",
+};
+
+static const char * const pwm5_groups[] = {
+ "pwm5",
+};
+
+static const char * const pwm6_groups[] = {
+ "pwm6",
+};
+
+static const char * const qspi_groups[] = {
+ "qspi_ctrl",
+ "qspi_data2",
+ "qspi_data4",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+ "scif0_data_b",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+ "scif1_data_c",
+ "scif1_data_d",
+ "scif1_clk_d",
+ "scif1_data_e",
+ "scif1_clk_e",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+ "scif2_data_b",
+};
+
+static const char * const scifa0_groups[] = {
+ "scifa0_data",
+ "scifa0_clk",
+ "scifa0_ctrl",
+ "scifa0_data_b",
+ "scifa0_clk_b",
+ "scifa0_ctrl_b",
+};
+
+static const char * const scifa1_groups[] = {
+ "scifa1_data",
+ "scifa1_clk",
+ "scifa1_ctrl",
+ "scifa1_data_b",
+ "scifa1_clk_b",
+ "scifa1_ctrl_b",
+ "scifa1_data_c",
+ "scifa1_clk_c",
+ "scifa1_ctrl_c",
+ "scifa1_data_d",
+ "scifa1_clk_d",
+ "scifa1_ctrl_d",
+};
+
+static const char * const scifa2_groups[] = {
+ "scifa2_data",
+ "scifa2_clk",
+ "scifa2_ctrl",
+ "scifa2_data_b",
+ "scifa2_data_c",
+ "scifa2_clk_c",
+};
+
+static const char * const scifb0_groups[] = {
+ "scifb0_data",
+ "scifb0_clk",
+ "scifb0_ctrl",
+ "scifb0_data_b",
+ "scifb0_clk_b",
+ "scifb0_ctrl_b",
+ "scifb0_data_c",
+};
+
+static const char * const scifb1_groups[] = {
+ "scifb1_data",
+ "scifb1_clk",
+ "scifb1_ctrl",
+ "scifb1_data_b",
+ "scifb1_clk_b",
+ "scifb1_ctrl_b",
+ "scifb1_data_c",
+ "scifb1_data_d",
+ "scifb1_data_e",
+ "scifb1_clk_e",
+ "scifb1_data_f",
+ "scifb1_data_g",
+ "scifb1_clk_g",
+};
+
+static const char * const scifb2_groups[] = {
+ "scifb2_data",
+ "scifb2_clk",
+ "scifb2_ctrl",
+ "scifb2_data_b",
+ "scifb2_clk_b",
+ "scifb2_ctrl_b",
+ "scifb2_data_c",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+ "scif_clk_b",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd",
+ "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+ "sdhi3_data1",
+ "sdhi3_data4",
+ "sdhi3_ctrl",
+ "sdhi3_cd",
+ "sdhi3_wp",
+};
+
+static const char * const ssi_groups[] = {
+ "ssi0_data",
+ "ssi0129_ctrl",
+ "ssi1_data",
+ "ssi1_ctrl",
+ "ssi2_data",
+ "ssi2_ctrl",
+ "ssi3_data",
+ "ssi34_ctrl",
+ "ssi4_data",
+ "ssi4_ctrl",
+ "ssi5",
+ "ssi5_b",
+ "ssi5_c",
+ "ssi6",
+ "ssi6_b",
+ "ssi7_data",
+ "ssi7_b_data",
+ "ssi7_c_data",
+ "ssi78_ctrl",
+ "ssi78_b_ctrl",
+ "ssi78_c_ctrl",
+ "ssi8_data",
+ "ssi8_b_data",
+ "ssi8_c_data",
+ "ssi9_data",
+ "ssi9_ctrl",
+};
+
+static const char * const tpu0_groups[] = {
+ "tpu0_to0",
+ "tpu0_to1",
+ "tpu0_to2",
+ "tpu0_to3",
+};
+
+static const char * const usb0_groups[] = {
+ "usb0",
+ "usb0_ovc_vbus",
+};
+
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const usb2_groups[] = {
+ "usb2",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data24",
+ "vin0_data20",
+ "vin0_data18",
+ "vin0_data16",
+ "vin0_data12",
+ "vin0_data10",
+ "vin0_data8",
+ "vin0_data4",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data24",
+ "vin1_data20",
+ "vin1_data18",
+ "vin1_data16",
+ "vin1_data12",
+ "vin1_data10",
+ "vin1_data8",
+ "vin1_data4",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+static const char * const vin2_groups[] = {
+ "vin2_data24",
+ "vin2_data18",
+ "vin2_data16",
+ "vin2_data8",
+ "vin2_data4",
+ "vin2_sync",
+ "vin2_field",
+ "vin2_clkenb",
+ "vin2_clk",
+};
+
+static const char * const vin3_groups[] = {
+ "vin3_data8",
+ "vin3_sync",
+ "vin3_field",
+ "vin3_clkenb",
+ "vin3_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(du2),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(iic0),
+ SH_PFC_FUNCTION(iic1),
+ SH_PFC_FUNCTION(iic2),
+ SH_PFC_FUNCTION(iic3),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mlb),
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(mmc1),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(sdhi3),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(tpu0),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb2),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+ SH_PFC_FUNCTION(vin2),
+ SH_PFC_FUNCTION(vin3),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ GP_0_31_FN, FN_IP3_17_15,
+ GP_0_30_FN, FN_IP3_14_12,
+ GP_0_29_FN, FN_IP3_11_8,
+ GP_0_28_FN, FN_IP3_7_4,
+ GP_0_27_FN, FN_IP3_3_0,
+ GP_0_26_FN, FN_IP2_28_26,
+ GP_0_25_FN, FN_IP2_25_22,
+ GP_0_24_FN, FN_IP2_21_18,
+ GP_0_23_FN, FN_IP2_17_15,
+ GP_0_22_FN, FN_IP2_14_12,
+ GP_0_21_FN, FN_IP2_11_9,
+ GP_0_20_FN, FN_IP2_8_6,
+ GP_0_19_FN, FN_IP2_5_3,
+ GP_0_18_FN, FN_IP2_2_0,
+ GP_0_17_FN, FN_IP1_29_28,
+ GP_0_16_FN, FN_IP1_27_26,
+ GP_0_15_FN, FN_IP1_25_22,
+ GP_0_14_FN, FN_IP1_21_18,
+ GP_0_13_FN, FN_IP1_17_15,
+ GP_0_12_FN, FN_IP1_14_12,
+ GP_0_11_FN, FN_IP1_11_8,
+ GP_0_10_FN, FN_IP1_7_4,
+ GP_0_9_FN, FN_IP1_3_0,
+ GP_0_8_FN, FN_IP0_30_27,
+ GP_0_7_FN, FN_IP0_26_23,
+ GP_0_6_FN, FN_IP0_22_20,
+ GP_0_5_FN, FN_IP0_19_16,
+ GP_0_4_FN, FN_IP0_15_12,
+ GP_0_3_FN, FN_IP0_11_9,
+ GP_0_2_FN, FN_IP0_8_6,
+ GP_0_1_FN, FN_IP0_5_3,
+ GP_0_0_FN, FN_IP0_2_0 }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ 0, 0,
+ 0, 0,
+ GP_1_29_FN, FN_IP6_13_11,
+ GP_1_28_FN, FN_IP6_10_9,
+ GP_1_27_FN, FN_IP6_8_6,
+ GP_1_26_FN, FN_IP6_5_3,
+ GP_1_25_FN, FN_IP6_2_0,
+ GP_1_24_FN, FN_IP5_29_27,
+ GP_1_23_FN, FN_IP5_26_24,
+ GP_1_22_FN, FN_IP5_23_21,
+ GP_1_21_FN, FN_IP5_20_18,
+ GP_1_20_FN, FN_IP5_17_15,
+ GP_1_19_FN, FN_IP5_14_13,
+ GP_1_18_FN, FN_IP5_12_10,
+ GP_1_17_FN, FN_IP5_9_6,
+ GP_1_16_FN, FN_IP5_5_3,
+ GP_1_15_FN, FN_IP5_2_0,
+ GP_1_14_FN, FN_IP4_29_27,
+ GP_1_13_FN, FN_IP4_26_24,
+ GP_1_12_FN, FN_IP4_23_21,
+ GP_1_11_FN, FN_IP4_20_18,
+ GP_1_10_FN, FN_IP4_17_15,
+ GP_1_9_FN, FN_IP4_14_12,
+ GP_1_8_FN, FN_IP4_11_9,
+ GP_1_7_FN, FN_IP4_8_6,
+ GP_1_6_FN, FN_IP4_5_3,
+ GP_1_5_FN, FN_IP4_2_0,
+ GP_1_4_FN, FN_IP3_31_29,
+ GP_1_3_FN, FN_IP3_28_26,
+ GP_1_2_FN, FN_IP3_25_23,
+ GP_1_1_FN, FN_IP3_22_20,
+ GP_1_0_FN, FN_IP3_19_18, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ 0, 0,
+ 0, 0,
+ GP_2_29_FN, FN_IP7_15_13,
+ GP_2_28_FN, FN_IP7_12_10,
+ GP_2_27_FN, FN_IP7_9_8,
+ GP_2_26_FN, FN_IP7_7_6,
+ GP_2_25_FN, FN_IP7_5_3,
+ GP_2_24_FN, FN_IP7_2_0,
+ GP_2_23_FN, FN_IP6_31_29,
+ GP_2_22_FN, FN_IP6_28_26,
+ GP_2_21_FN, FN_IP6_25_23,
+ GP_2_20_FN, FN_IP6_22_20,
+ GP_2_19_FN, FN_IP6_19_17,
+ GP_2_18_FN, FN_IP6_16_14,
+ GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+ GP_2_16_FN, FN_IP8_27,
+ GP_2_15_FN, FN_IP8_26,
+ GP_2_14_FN, FN_IP8_25_24,
+ GP_2_13_FN, FN_IP8_23_22,
+ GP_2_12_FN, FN_IP8_21_20,
+ GP_2_11_FN, FN_IP8_19_18,
+ GP_2_10_FN, FN_IP8_17_16,
+ GP_2_9_FN, FN_IP8_15_14,
+ GP_2_8_FN, FN_IP8_13_12,
+ GP_2_7_FN, FN_IP8_11_10,
+ GP_2_6_FN, FN_IP8_9_8,
+ GP_2_5_FN, FN_IP8_7_6,
+ GP_2_4_FN, FN_IP8_5_4,
+ GP_2_3_FN, FN_IP8_3_2,
+ GP_2_2_FN, FN_IP8_1_0,
+ GP_2_1_FN, FN_IP7_30_29,
+ GP_2_0_FN, FN_IP7_28_27 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ GP_3_31_FN, FN_IP11_21_18,
+ GP_3_30_FN, FN_IP11_17_15,
+ GP_3_29_FN, FN_IP11_14_13,
+ GP_3_28_FN, FN_IP11_12_11,
+ GP_3_27_FN, FN_IP11_10_9,
+ GP_3_26_FN, FN_IP11_8_7,
+ GP_3_25_FN, FN_IP11_6_5,
+ GP_3_24_FN, FN_IP11_4,
+ GP_3_23_FN, FN_IP11_3_0,
+ GP_3_22_FN, FN_IP10_29_26,
+ GP_3_21_FN, FN_IP10_25_23,
+ GP_3_20_FN, FN_IP10_22_19,
+ GP_3_19_FN, FN_IP10_18_15,
+ GP_3_18_FN, FN_IP10_14_11,
+ GP_3_17_FN, FN_IP10_10_7,
+ GP_3_16_FN, FN_IP10_6_4,
+ GP_3_15_FN, FN_IP10_3_0,
+ GP_3_14_FN, FN_IP9_31_28,
+ GP_3_13_FN, FN_IP9_27_26,
+ GP_3_12_FN, FN_IP9_25_24,
+ GP_3_11_FN, FN_IP9_23_22,
+ GP_3_10_FN, FN_IP9_21_20,
+ GP_3_9_FN, FN_IP9_19_18,
+ GP_3_8_FN, FN_IP9_17_16,
+ GP_3_7_FN, FN_IP9_15_12,
+ GP_3_6_FN, FN_IP9_11_8,
+ GP_3_5_FN, FN_IP9_7_6,
+ GP_3_4_FN, FN_IP9_5_4,
+ GP_3_3_FN, FN_IP9_3_2,
+ GP_3_2_FN, FN_IP9_1_0,
+ GP_3_1_FN, FN_IP8_30_29,
+ GP_3_0_FN, FN_IP8_28 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ GP_4_31_FN, FN_IP14_18_16,
+ GP_4_30_FN, FN_IP14_15_12,
+ GP_4_29_FN, FN_IP14_11_9,
+ GP_4_28_FN, FN_IP14_8_6,
+ GP_4_27_FN, FN_IP14_5_3,
+ GP_4_26_FN, FN_IP14_2_0,
+ GP_4_25_FN, FN_IP13_30_29,
+ GP_4_24_FN, FN_IP13_28_26,
+ GP_4_23_FN, FN_IP13_25_23,
+ GP_4_22_FN, FN_IP13_22_19,
+ GP_4_21_FN, FN_IP13_18_16,
+ GP_4_20_FN, FN_IP13_15_13,
+ GP_4_19_FN, FN_IP13_12_10,
+ GP_4_18_FN, FN_IP13_9_7,
+ GP_4_17_FN, FN_IP13_6_3,
+ GP_4_16_FN, FN_IP13_2_0,
+ GP_4_15_FN, FN_IP12_30_28,
+ GP_4_14_FN, FN_IP12_27_25,
+ GP_4_13_FN, FN_IP12_24_23,
+ GP_4_12_FN, FN_IP12_22_20,
+ GP_4_11_FN, FN_IP12_19_17,
+ GP_4_10_FN, FN_IP12_16_14,
+ GP_4_9_FN, FN_IP12_13_11,
+ GP_4_8_FN, FN_IP12_10_8,
+ GP_4_7_FN, FN_IP12_7_6,
+ GP_4_6_FN, FN_IP12_5_4,
+ GP_4_5_FN, FN_IP12_3_2,
+ GP_4_4_FN, FN_IP12_1_0,
+ GP_4_3_FN, FN_IP11_31_30,
+ GP_4_2_FN, FN_IP11_29_27,
+ GP_4_1_FN, FN_IP11_26_24,
+ GP_4_0_FN, FN_IP11_23_22 }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ GP_5_31_FN, FN_IP7_24_22,
+ GP_5_30_FN, FN_IP7_21_19,
+ GP_5_29_FN, FN_IP7_18_16,
+ GP_5_28_FN, FN_DU_DOTCLKIN2,
+ GP_5_27_FN, FN_IP7_26_25,
+ GP_5_26_FN, FN_DU_DOTCLKIN0,
+ GP_5_25_FN, FN_AVS2,
+ GP_5_24_FN, FN_AVS1,
+ GP_5_23_FN, FN_USB2_OVC,
+ GP_5_22_FN, FN_USB2_PWEN,
+ GP_5_21_FN, FN_IP16_7,
+ GP_5_20_FN, FN_IP16_6,
+ GP_5_19_FN, FN_USB0_OVC_VBUS,
+ GP_5_18_FN, FN_USB0_PWEN,
+ GP_5_17_FN, FN_IP16_5_3,
+ GP_5_16_FN, FN_IP16_2_0,
+ GP_5_15_FN, FN_IP15_29_28,
+ GP_5_14_FN, FN_IP15_27_26,
+ GP_5_13_FN, FN_IP15_25_23,
+ GP_5_12_FN, FN_IP15_22_20,
+ GP_5_11_FN, FN_IP15_19_18,
+ GP_5_10_FN, FN_IP15_17_16,
+ GP_5_9_FN, FN_IP15_15_14,
+ GP_5_8_FN, FN_IP15_13_12,
+ GP_5_7_FN, FN_IP15_11_9,
+ GP_5_6_FN, FN_IP15_8_6,
+ GP_5_5_FN, FN_IP15_5_3,
+ GP_5_4_FN, FN_IP15_2_0,
+ GP_5_3_FN, FN_IP14_30_28,
+ GP_5_2_FN, FN_IP14_27_25,
+ GP_5_1_FN, FN_IP14_24_22,
+ GP_5_0_FN, FN_IP14_21_19 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+ 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+ /* IP0_31 [1] */
+ 0, 0,
+ /* IP0_30_27 [4] */
+ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
+ FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_26_23 [4] */
+ FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
+ FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
+ FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_22_20 [3] */
+ FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+ FN_I2C2_SCL_C, 0, 0,
+ /* IP0_19_16 [4] */
+ FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+ FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_15_12 [4] */
+ FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+ FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_11_9 [3] */
+ FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
+ 0, 0, 0,
+ /* IP0_8_6 [3] */
+ FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
+ 0, 0, 0,
+ /* IP0_5_3 [3] */
+ FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
+ 0, 0, 0,
+ /* IP0_2_0 [3] */
+ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+ 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+ /* IP1_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP1_29_28 [2] */
+ FN_A1, FN_PWM4, 0, 0,
+ /* IP1_27_26 [2] */
+ FN_A0, FN_PWM3, 0, 0,
+ /* IP1_25_22 [4] */
+ FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+ FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_21_18 [4] */
+ FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+ FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_17_15 [3] */
+ FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+ FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
+ 0, 0, 0,
+ /* IP1_14_12 [3] */
+ FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+ FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+ 0, 0,
+ /* IP1_11_8 [4] */
+ FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
+ FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_7_4 [4] */
+ FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
+ FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_3_0 [4] */
+ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
+ FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+ 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+ /* IP2_31_29 [3] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_28_26 [3] */
+ FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+ FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
+ /* IP2_25_22 [4] */
+ FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+ FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_21_18 [4] */
+ FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+ FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_17_15 [3] */
+ FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+ 0, 0, 0, 0,
+ /* IP2_14_12 [3] */
+ FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
+ /* IP2_11_9 [3] */
+ FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
+ /* IP2_8_6 [3] */
+ FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
+ /* IP2_5_3 [3] */
+ FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
+ /* IP2_2_0 [3] */
+ FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+ 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+ /* IP3_31_29 [3] */
+ FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+ 0, 0, 0,
+ /* IP3_28_26 [3] */
+ FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
+ 0, 0, 0, 0,
+ /* IP3_25_23 [3] */
+ FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
+ /* IP3_22_20 [3] */
+ FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
+ /* IP3_19_18 [2] */
+ FN_A16, FN_ATAWR1_N, 0, 0,
+ /* IP3_17_15 [3] */
+ FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
+ 0, 0, 0, 0,
+ /* IP3_14_12 [3] */
+ FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
+ 0, 0, 0, 0,
+ /* IP3_11_8 [4] */
+ FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+ FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+ FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP3_7_4 [4] */
+ FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+ FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP3_3_0 [4] */
+ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+ FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+ 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP4_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP4_29_27 [3] */
+ FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+ FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
+ /* IP4_26_24 [3] */
+ FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
+ FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
+ /* IP4_23_21 [3] */
+ FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
+ FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
+ /* IP4_20_18 [3] */
+ FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+ FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
+ /* IP4_17_15 [3] */
+ FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+ 0, 0, 0,
+ /* IP4_14_12 [3] */
+ FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
+ FN_VI2_FIELD_B, 0, 0,
+ /* IP4_11_9 [3] */
+ FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+ FN_VI2_CLKENB_B, 0, 0,
+ /* IP4_8_6 [3] */
+ FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
+ /* IP4_5_3 [3] */
+ FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
+ /* IP4_2_0 [3] */
+ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+ 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+ /* IP5_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP5_29_27 [3] */
+ FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
+ FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
+ /* IP5_26_24 [3] */
+ FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+ FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+ FN_MSIOF0_SCK_B, 0,
+ /* IP5_23_21 [3] */
+ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+ FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
+ /* IP5_20_18 [3] */
+ FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+ FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
+ /* IP5_17_15 [3] */
+ FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+ FN_INTC_IRQ4_N, 0, 0,
+ /* IP5_14_13 [2] */
+ FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
+ /* IP5_12_10 [3] */
+ FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
+ 0, 0,
+ /* IP5_9_6 [4] */
+ FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
+ FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
+ FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
+ /* IP5_5_3 [3] */
+ FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+ FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
+ FN_INTC_EN0_N, FN_I2C1_SCL,
+ /* IP5_2_0 [3] */
+ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+ FN_VI2_R3, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+ 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+ /* IP6_31_29 [3] */
+ FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
+ FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+ /* IP6_28_26 [3] */
+ FN_ETH_LINK, 0, FN_HTX0_E,
+ FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+ /* IP6_25_23 [3] */
+ FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+ FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+ /* IP6_22_20 [3] */
+ FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+ FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+ /* IP6_19_17 [3] */
+ FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
+ FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
+ /* IP6_16_14 [3] */
+ FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
+ FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
+ FN_I2C2_SCL_E, 0,
+ /* IP6_13_11 [3] */
+ FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+ FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+ /* IP6_10_9 [2] */
+ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+ /* IP6_8_6 [3] */
+ FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+ FN_SSI_SDATA8_C, 0, 0, 0,
+ /* IP6_5_3 [3] */
+ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+ FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+ /* IP6_2_0 [3] */
+ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+ FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+ 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+ /* IP7_31 [1] */
+ 0, 0,
+ /* IP7_30_29 [2] */
+ FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
+ /* IP7_28_27 [2] */
+ FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
+ /* IP7_26_25 [2] */
+ FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+ /* IP7_24_22 [3] */
+ FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+ 0, 0, 0,
+ /* IP7_21_19 [3] */
+ FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+ FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+ /* IP7_18_16 [3] */
+ FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+ FN_GLO_SS_C, 0, 0, 0,
+ /* IP7_15_13 [3] */
+ FN_ETH_MDC, 0, FN_STP_ISD_1_B,
+ FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+ /* IP7_12_10 [3] */
+ FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+ FN_GLO_SCLK_C, 0, 0, 0,
+ /* IP7_9_8 [2] */
+ FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
+ /* IP7_7_6 [2] */
+ FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+ /* IP7_5_3 [3] */
+ FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
+ /* IP7_2_0 [3] */
+ FN_ETH_MDIO, 0, FN_HRTS0_N_E,
+ FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2) {
+ /* IP8_31 [1] */
+ 0, 0,
+ /* IP8_30_29 [2] */
+ FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+ /* IP8_28 [1] */
+ FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+ /* IP8_27 [1] */
+ FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+ /* IP8_26 [1] */
+ FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+ /* IP8_25_24 [2] */
+ FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+ FN_AVB_MAGIC, 0,
+ /* IP8_23_22 [2] */
+ FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+ /* IP8_21_20 [2] */
+ FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
+ /* IP8_19_18 [2] */
+ FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
+ /* IP8_17_16 [2] */
+ FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
+ /* IP8_15_14 [2] */
+ FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
+ /* IP8_13_12 [2] */
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
+ /* IP8_11_10 [2] */
+ FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
+ /* IP8_9_8 [2] */
+ FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+ /* IP8_7_6 [2] */
+ FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+ /* IP8_5_4 [2] */
+ FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+ /* IP8_3_2 [2] */
+ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+ /* IP8_1_0 [2] */
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+ 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+ /* IP9_31_28 [4] */
+ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+ FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
+ FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+ /* IP9_27_26 [2] */
+ FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
+ /* IP9_25_24 [2] */
+ FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
+ /* IP9_23_22 [2] */
+ FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
+ /* IP9_21_20 [2] */
+ FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
+ /* IP9_19_18 [2] */
+ FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
+ /* IP9_17_16 [2] */
+ FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
+ /* IP9_15_12 [4] */
+ FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+ FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
+ FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP9_11_8 [4] */
+ FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+ FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
+ FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP9_7_6 [2] */
+ FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+ /* IP9_5_4 [2] */
+ FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+ /* IP9_3_2 [2] */
+ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+ /* IP9_1_0 [2] */
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+ 2, 4, 3, 4, 4, 4, 4, 3, 4) {
+ /* IP10_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP10_29_26 [4] */
+ FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+ FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+ FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+ /* IP10_25_23 [3] */
+ FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+ FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+ /* IP10_22_19 [4] */
+ FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
+ FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+ FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_18_15 [4] */
+ FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
+ FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+ FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+ 0, 0, 0, 0, 0, 0,
+ /* IP10_14_11 [4] */
+ FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+ FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+ FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_10_7 [4] */
+ FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+ FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+ FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP10_6_4 [3] */
+ FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+ FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+ FN_VI3_DATA0_B, 0,
+ /* IP10_3_0 [4] */
+ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+ FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
+ FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+ /* IP11_31_30 [2] */
+ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+ /* IP11_29_27 [3] */
+ FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+ 0, 0, 0,
+ /* IP11_26_24 [3] */
+ FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
+ 0, 0, 0,
+ /* IP11_23_22 [2] */
+ FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
+ /* IP11_21_18 [4] */
+ FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+ 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
+ /* IP11_17_15 [3] */
+ FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+ FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+ /* IP11_14_13 [2] */
+ FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+ /* IP11_12_11 [2] */
+ FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+ /* IP11_10_9 [2] */
+ FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+ /* IP11_8_7 [2] */
+ FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+ /* IP11_6_5 [2] */
+ FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+ /* IP11_4 [1] */
+ FN_SD3_CLK, FN_MMC1_CLK,
+ /* IP11_3_0 [4] */
+ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+ FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+ 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ /* IP12_31 [1] */
+ 0, 0,
+ /* IP12_30_28 [3] */
+ FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
+ FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+ FN_CAN_DEBUGOUT4, 0, 0,
+ /* IP12_27_25 [3] */
+ FN_SSI_SCK5, FN_SCIFB1_SCK,
+ FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+ FN_CAN_DEBUGOUT3, 0, 0,
+ /* IP12_24_23 [2] */
+ FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+ FN_CAN_DEBUGOUT2,
+ /* IP12_22_20 [3] */
+ FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+ FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
+ /* IP12_19_17 [3] */
+ FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+ FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
+ /* IP12_16_14 [3] */
+ FN_SSI_SDATA3, FN_STP_ISCLK_0,
+ FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
+ /* IP12_13_11 [3] */
+ FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+ FN_CAN_STEP0, 0, 0, 0,
+ /* IP12_10_8 [3] */
+ FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+ FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
+ /* IP12_7_6 [2] */
+ FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+ /* IP12_5_4 [2] */
+ FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
+ /* IP12_3_2 [2] */
+ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
+ /* IP12_1_0 [2] */
+ FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+ 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+ /* IP13_31 [1] */
+ 0, 0,
+ /* IP13_30_29 [2] */
+ FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
+ /* IP13_28_26 [3] */
+ FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+ FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
+ /* IP13_25_23 [3] */
+ FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+ FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
+ /* IP13_22_19 [4] */
+ FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+ FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
+ 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
+ /* IP13_18_16 [3] */
+ FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
+ FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
+ /* IP13_15_13 [3] */
+ FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
+ FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
+ /* IP13_12_10 [3] */
+ FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
+ FN_CAN_DEBUGOUT8, 0, 0,
+ /* IP13_9_7 [3] */
+ FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+ FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
+ /* IP13_6_3 [4] */
+ FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
+ FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+ FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_2_0 [3] */
+ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+ FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+ 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+ /* IP14_30 [1] */
+ 0, 0,
+ /* IP14_30_28 [3] */
+ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
+ FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+ FN_HRTS0_N_C, 0,
+ /* IP14_27_25 [3] */
+ FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
+ FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
+ /* IP14_24_22 [3] */
+ FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+ FN_LCDOUT9, 0, 0, 0,
+ /* IP14_21_19 [3] */
+ FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+ FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
+ /* IP14_18_16 [3] */
+ FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
+ FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
+ /* IP14_15_12 [4] */
+ FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
+ FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
+ 0, 0, 0, 0, 0, 0, 0,
+ /* IP14_11_9 [3] */
+ FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
+ 0, 0, 0,
+ /* IP14_8_6 [3] */
+ FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
+ 0, 0, 0,
+ /* IP14_5_3 [3] */
+ FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
+ FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
+ /* IP14_2_0 [3] */
+ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+ FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+ FN_REMOCON, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+ 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+ /* IP15_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP15_29_28 [2] */
+ FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
+ /* IP15_27_26 [2] */
+ FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
+ /* IP15_25_23 [3] */
+ FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
+ FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
+ /* IP15_22_20 [3] */
+ FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+ FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
+ /* IP15_19_18 [2] */
+ FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
+ /* IP15_17_16 [2] */
+ FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
+ /* IP15_15_14 [2] */
+ FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
+ /* IP15_13_12 [2] */
+ FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
+ /* IP15_11_9 [3] */
+ FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
+ 0, 0, 0,
+ /* IP15_8_6 [3] */
+ FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
+ FN_IIC2_SDA, FN_I2C2_SDA, 0,
+ /* IP15_5_3 [3] */
+ FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
+ FN_IIC2_SCL, FN_I2C2_SCL, 0,
+ /* IP15_2_0 [3] */
+ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
+ FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+ 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+ /* IP16_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_19_16 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_15_12 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_11_8 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_7 [1] */
+ FN_USB1_OVC, FN_TCLK1_B,
+ /* IP16_6 [1] */
+ FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
+ /* IP16_5_3 [3] */
+ FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+ FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
+ /* IP16_2_0 [3] */
+ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+ FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+ 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+ /* SEL_SCIF1 [3] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ FN_SEL_SCIF1_4, 0, 0, 0,
+ /* SEL_SCIFB [2] */
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+ /* SEL_SCIFB2 [2] */
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+ /* SEL_SCIFB1 [3] */
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+ FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+ FN_SEL_SCIFB1_6, 0,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SCIFA1_3,
+ /* SEL_SCIF0 [1] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+ /* SEL_SCIFA [1] */
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ /* SEL_SOF1 [1] */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+ /* SEL_SSI7 [2] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+ /* SEL_SSI6 [1] */
+ FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+ /* SEL_SSI5 [2] */
+ FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+ /* SEL_VI3 [1] */
+ FN_SEL_VI3_0, FN_SEL_VI3_1,
+ /* SEL_VI2 [1] */
+ FN_SEL_VI2_0, FN_SEL_VI2_1,
+ /* SEL_VI1 [1] */
+ FN_SEL_VI1_0, FN_SEL_VI1_1,
+ /* SEL_VI0 [1] */
+ FN_SEL_VI0_0, FN_SEL_VI0_1,
+ /* SEL_TSIF1 [2] */
+ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_LBS [1] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_SOF3 [1] */
+ FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+ /* SEL_SOF0 [1] */
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 3, 1, 1, 1, 2, 1, 2, 1, 2,
+ 1, 1, 1, 3, 3, 2, 3, 2, 2) {
+ /* RESERVED [3] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* SEL_TMU1 [1] */
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ /* SEL_HSCIF1 [1] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ /* SEL_SCIFCLK [1] */
+ FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+ /* SEL_CAN0 [2] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ /* SEL_CANCLK [1] */
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+ /* SEL_SCIFA2 [2] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+ /* SEL_CAN1 [1] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_SCIF2 [1] */
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
+ /* SEL_ADI [1] */
+ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ /* SEL_SSP [1] */
+ FN_SEL_SSP_0, FN_SEL_SSP_1,
+ /* SEL_FM [3] */
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+ FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+ /* SEL_HSCIF0 [3] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+ FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+ /* SEL_GPS [2] */
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+ /* RESERVED [3] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* SEL_SIM [2] */
+ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+ /* SEL_SSI8 [2] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 1, 1, 2, 4, 4, 2, 2,
+ 4, 2, 3, 2, 3, 2) {
+ /* SEL_IICDVFS [1] */
+ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+ /* SEL_IIC0 [1] */
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* RESERVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+ /* RESERVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IIC2 [3] */
+ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+ FN_SEL_IIC2_4, 0, 0, 0,
+ /* SEL_IIC1 [2] */
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+ /* SEL_I2C2 [3] */
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ FN_SEL_I2C2_4, 0, 0, 0,
+ /* SEL_I2C1 [2] */
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+ },
+ { },
+};
+
+static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
+ return -EINVAL;
+
+ *pocctrl = 0xe606008c;
+
+ return 31 - (pin & 0x1f);
+}
+
+static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
+ .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
+};
+
+const struct sh_pfc_soc_info r8a7790_pinmux_info = {
+ .name = "r8a77900_pfc",
+ .ops = &r8a7790_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
--- /dev/null
+/*
+ * r8a7791/r8a7743 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2014-2017 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+/*
+ * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
+ * which case they support both 3.3V and 1.8V signalling.
+ */
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_32(0, fn, sfx), \
+ PORT_GP_26(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_32(3, fn, sfx), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_32(5, fn, sfx), \
+ PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_1(6, 24, fn, sfx), \
+ PORT_GP_1(6, 25, fn, sfx), \
+ PORT_GP_1(6, 26, fn, sfx), \
+ PORT_GP_1(6, 27, fn, sfx), \
+ PORT_GP_1(6, 28, fn, sfx), \
+ PORT_GP_1(6, 29, fn, sfx), \
+ PORT_GP_1(6, 30, fn, sfx), \
+ PORT_GP_1(6, 31, fn, sfx), \
+ PORT_GP_26(7, fn, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
+ FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+ FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
+ FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
+ FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
+ FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
+
+ /* GPSR1 */
+ FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
+ FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
+ FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
+ FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
+ FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
+ FN_IP3_21_20,
+
+ /* GPSR2 */
+ FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
+ FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
+ FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
+ FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
+ FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
+ FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
+ FN_IP6_5_3, FN_IP6_7_6,
+
+ /* GPSR3 */
+ FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
+ FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
+ FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
+ FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
+ FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
+ FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
+ FN_IP9_18_17,
+
+ /* GPSR4 */
+ FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
+ FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
+ FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
+ FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
+ FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
+ FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
+ FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+ FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
+
+ /* GPSR5 */
+ FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
+ FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
+ FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
+ FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
+ FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
+ FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
+ FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
+
+ /* GPSR6 */
+ FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
+ FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
+ FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
+ FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
+ FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
+ FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
+ FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
+ FN_USB1_OVC, FN_DU0_DOTCLKIN,
+
+ /* GPSR7 */
+ FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
+ FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
+ FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+ FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
+ FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
+ FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
+
+ /* IPSR0 */
+ FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
+ FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
+ FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
+ FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
+ FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
+ FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
+
+ /* IPSR1 */
+ FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
+ FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
+ FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
+ FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
+ FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
+ FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
+ FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
+ FN_A15, FN_BPFCLK_C,
+ FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
+ FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
+ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
+
+ /* IPSR2 */
+ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
+ FN_A20, FN_SPCLK,
+ FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
+ FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
+ FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
+ FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
+ FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
+ FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
+ FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
+ FN_EX_CS1_N, FN_MSIOF2_SCK,
+ FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
+ FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
+
+ /* IPSR3 */
+ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
+ FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
+ FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
+ FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
+ FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
+ FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
+ FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
+ FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
+ FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
+ FN_DREQ0, FN_PWM3, FN_TPU_TO3,
+ FN_DACK0, FN_DRACK0, FN_REMOCON,
+ FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
+ FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
+ FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
+ FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
+
+ /* IPSR4 */
+ FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
+ FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
+ FN_GLO_I0_D,
+ FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
+ FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
+ FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
+ FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
+ FN_GLO_Q1_D, FN_HCTS1_N_E,
+ FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
+ FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
+ FN_SSI_SCK4, FN_GLO_SS_D,
+ FN_SSI_WS4, FN_GLO_RFON_D,
+ FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
+ FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
+ FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
+
+ /* IPSR5 */
+ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
+ FN_MSIOF2_TXD_D, FN_VI1_R3_B,
+ FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
+ FN_MSIOF2_SS1_D, FN_VI1_R4_B,
+ FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
+ FN_MSIOF2_RXD_D, FN_VI1_R5_B,
+ FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
+ FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
+ FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
+ FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
+ FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
+ FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
+ FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
+ FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
+ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
+
+ /* IPSR6 */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
+ FN_SCIFA2_RXD, FN_FMIN_E,
+ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
+ FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
+ FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
+ FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
+ FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
+ FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
+ FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
+ FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
+ FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
+
+ /* IPSR7 */
+ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
+ FN_SCIF_CLK_B, FN_GPS_MAG_D,
+ FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
+ FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
+ FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
+ FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
+ FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
+ FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
+ FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
+ FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
+ FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
+ FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
+ FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
+ FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
+ FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
+ FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
+ FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
+ FN_SCIFA1_SCK, FN_SSI_SCK78_B,
+
+ /* IPSR8 */
+ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
+ FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
+ FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
+ FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
+ FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
+ FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
+ FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
+ FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
+ FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
+ FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
+ FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
+ FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
+ FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
+ FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
+ FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
+ FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
+ FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
+
+ /* IPSR9 */
+ FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
+ FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
+ FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
+ FN_DU1_DOTCLKOUT0, FN_QCLK,
+ FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
+ FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
+ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
+ FN_DU1_DISP, FN_QPOLA,
+ FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
+ FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
+ FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
+ FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
+ FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
+ FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
+ FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
+ FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
+
+ /* IPSR10 */
+ FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
+ FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
+ FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
+ FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
+ FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
+ FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
+ FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
+ FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
+ FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
+ FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
+ FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
+ FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
+ FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
+ FN_TS_SDATA0_C, FN_ATACS11_N,
+ FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
+ FN_TS_SCK0_C, FN_ATAG1_N,
+ FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
+ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
+ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
+
+ /* IPSR11 */
+ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
+ FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
+ FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+ FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
+ FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
+ FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
+ FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
+ FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
+ FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
+ FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
+ FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
+ FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
+ FN_VI1_DATA7, FN_AVB_MDC,
+ FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
+ FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
+
+ /* IPSR12 */
+ FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
+ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
+ FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+ FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
+ FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
+ FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+ FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+ FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+ FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+ FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+ FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
+ FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
+ FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
+ FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+ FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+ FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+ FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+
+ /* IPSR13 */
+ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
+ FN_ADICLK_B, FN_MSIOF0_SS1_C,
+ FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
+ FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
+ FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
+ FN_ADICHS2_B, FN_MSIOF0_TXD_C,
+ FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
+ FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
+ FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
+ FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
+ FN_SCIFA5_TXD_B, FN_TX3_C,
+ FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
+ FN_SCIFA5_RXD_B, FN_RX3_C,
+ FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
+ FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
+ FN_SD1_DATA3, FN_IERX_B,
+ FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
+
+ /* IPSR14 */
+ FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
+ FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
+ FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
+ FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
+ FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
+ FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
+ FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
+ FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
+ FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
+ FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
+ FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
+ FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
+ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
+ FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
+
+ /* IPSR15 */
+ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
+ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
+ FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
+ FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
+ FN_PWM5_B, FN_SCIFA3_TXD_C,
+ FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
+ FN_VI1_G6_B, FN_SCIFA3_RXD_C,
+ FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
+ FN_VI1_G7_B, FN_SCIFA3_SCK_C,
+ FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
+ FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
+ FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
+ FN_TCLK2, FN_VI1_DATA3_C,
+ FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
+ FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
+
+ /* IPSR16 */
+ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
+ FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
+ FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
+ FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
+ FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
+
+ /* MOD_SEL */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ FN_SEL_QSP_0, FN_SEL_QSP_1,
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
+ FN_SEL_HSCIF1_4,
+ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
+
+ /* MOD_SEL2 */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ FN_SEL_SCIF0_4,
+ FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
+ FN_SEL_ADG_0, FN_SEL_ADG_1,
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
+ FN_SEL_SIM_0, FN_SEL_SIM_1,
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+
+ /* MOD_SEL3 */
+ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
+ FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
+ FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ FN_SEL_MMC_0, FN_SEL_MMC_1,
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
+ FN_SEL_I2C1_4,
+ FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
+
+ /* MOD_SEL4 */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+ FN_SEL_SOF1_4,
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
+ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
+ FN_SEL_SCIF2_4,
+ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
+ FN_SEL_SOF2_4,
+ FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+ FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+ EX_CS0_N_MARK, RD_N_MARK,
+
+ AUDIO_CLKA_MARK,
+
+ VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+
+ SD1_CLK_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+ DU0_DOTCLKIN_MARK,
+
+ /* IPSR0 */
+ D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
+ D6_MARK, D7_MARK, D8_MARK,
+ D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
+ A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
+ PWM2_B_MARK,
+ A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
+ A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
+ A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
+
+ /* IPSR1 */
+ A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
+ A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
+ A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
+ A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
+ A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
+ A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
+ A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
+ A15_MARK, BPFCLK_C_MARK,
+ A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
+ A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
+ A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
+
+ /* IPSR2 */
+ A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
+ SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
+ A20_MARK, SPCLK_MARK,
+ A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
+ A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
+ A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
+ A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
+ A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
+ RX1_MARK, SCIFA1_RXD_MARK,
+ CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
+ CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
+ EX_CS1_N_MARK, MSIOF2_SCK_MARK,
+ EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
+ EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
+ ATAG0_N_MARK, EX_WAIT1_MARK,
+
+ /* IPSR3 */
+ EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
+ EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
+ SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
+ BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
+ SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
+ RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
+ SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
+ WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
+ WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
+ EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+ DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
+ DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
+ SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
+ SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
+ SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
+ SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
+ SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
+ SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
+
+ /* IPSR4 */
+ SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
+ SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
+ MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
+ SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
+ MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
+ SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
+ SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
+ HSCK1_E_MARK,
+ SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
+ GLO_Q1_D_MARK, HCTS1_N_E_MARK,
+ SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
+ SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
+ SSI_SCK4_MARK, GLO_SS_D_MARK,
+ SSI_WS4_MARK, GLO_RFON_D_MARK,
+ SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
+ SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
+ MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
+
+ /* IPSR5 */
+ SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
+ MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
+ SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
+ MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
+ SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
+ MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
+ SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
+ SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
+ SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
+ SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
+ SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
+ SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
+ SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
+ SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
+ SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
+
+ /* IPSR6 */
+ AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
+ SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
+ AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
+ SCIFA2_RXD_MARK, FMIN_E_MARK,
+ AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
+ IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
+ IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
+ IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
+ IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
+ IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
+ MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
+ IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
+ IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
+ I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
+ IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
+ GPS_CLK_C_MARK, GPS_CLK_D_MARK,
+ IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
+ GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
+
+ /* IPSR7 */
+ IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
+ SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
+ DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
+ SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
+ DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
+ SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
+ DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
+ DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
+ DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
+ DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
+ DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
+ DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
+ DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
+ SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
+ DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
+ SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
+ DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
+ SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
+
+ /* IPSR8 */
+ DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
+ DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
+ SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
+ DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
+ SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
+ DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
+ SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
+ DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
+ SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
+ DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
+ SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
+ DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
+ SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
+ DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
+ SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
+ DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
+ DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
+ DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
+
+ /* IPSR9 */
+ DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
+ DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
+ SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
+ DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
+ DU1_DOTCLKOUT0_MARK, QCLK_MARK,
+ DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
+ TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
+ DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
+ DU1_DISP_MARK, QPOLA_MARK,
+ DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
+ VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
+ VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
+ VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
+ VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
+ VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
+ VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
+ HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
+
+ /* IPSR10 */
+ VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
+ HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
+ VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
+ HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
+ VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
+ HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
+ VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
+ HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
+ VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
+ CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
+ VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
+ VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
+ VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
+ TS_SDATA0_C_MARK, ATACS11_N_MARK,
+ VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
+ TS_SCK0_C_MARK, ATAG1_N_MARK,
+ VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
+ VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
+ VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
+ I2C1_SCL_D_MARK,
+
+ /* IPSR11 */
+ VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
+ I2C1_SDA_D_MARK,
+ VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
+ VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
+ I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
+ VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
+ TX4_B_MARK, SCIFA4_TXD_B_MARK,
+ VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
+ RX4_B_MARK, SCIFA4_RXD_B_MARK,
+ VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
+ VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
+ VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
+ VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
+ VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
+ VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
+ VI1_DATA7_MARK, AVB_MDC_MARK,
+ ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
+ ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
+
+ /* IPSR12 */
+ ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
+ ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
+ ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
+ I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
+ ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
+ I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
+ ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
+ CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
+ ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
+ CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
+ ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
+ ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
+ ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
+ ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
+ STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
+ ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
+ STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
+ ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
+
+ /* IPSR13 */
+ STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
+ ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
+ STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
+ STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
+ STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
+ ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
+ SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
+ SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
+ SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
+ SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
+ SCIFA5_TXD_B_MARK, TX3_C_MARK,
+ SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
+ SCIFA5_RXD_B_MARK, RX3_C_MARK,
+ SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
+ SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
+ SD1_DATA3_MARK, IERX_B_MARK,
+ SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
+
+ /* IPSR14 */
+ SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
+ SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
+ SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
+ SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
+ SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
+ SCIFA5_TXD_C_MARK,
+ SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
+ SCIFA5_RXD_C_MARK,
+ MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
+ VI1_CLK_C_MARK, VI1_G0_B_MARK,
+ MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
+ VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
+ MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
+ MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
+ MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
+ VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
+ MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
+ VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
+
+ /* IPSR15 */
+ SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
+ SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
+ SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
+ GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
+ PWM5_B_MARK, SCIFA3_TXD_C_MARK,
+ GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
+ VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
+ GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
+ VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
+ HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
+ TCLK1_MARK, VI1_DATA1_C_MARK,
+ HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
+ HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
+ TCLK2_MARK, VI1_DATA3_C_MARK,
+ HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
+ CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
+ HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
+ CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
+
+ /* IPSR16 */
+ HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
+ GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
+ HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
+ GLO_SS_C_MARK, VI1_DATA7_C_MARK,
+ HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
+ HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
+ HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
+ PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_SINGLE(EX_CS0_N),
+ PINMUX_SINGLE(RD_N),
+ PINMUX_SINGLE(AUDIO_CLKA),
+ PINMUX_SINGLE(VI0_CLK),
+ PINMUX_SINGLE(VI0_DATA0_VI0_B0),
+ PINMUX_SINGLE(VI0_DATA1_VI0_B1),
+ PINMUX_SINGLE(VI0_DATA2_VI0_B2),
+ PINMUX_SINGLE(VI0_DATA4_VI0_B4),
+ PINMUX_SINGLE(VI0_DATA5_VI0_B5),
+ PINMUX_SINGLE(VI0_DATA6_VI0_B6),
+ PINMUX_SINGLE(VI0_DATA7_VI0_B7),
+ PINMUX_SINGLE(USB0_PWEN),
+ PINMUX_SINGLE(USB0_OVC),
+ PINMUX_SINGLE(USB1_PWEN),
+ PINMUX_SINGLE(USB1_OVC),
+ PINMUX_SINGLE(DU0_DOTCLKIN),
+ PINMUX_SINGLE(SD1_CLK),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_0, D0),
+ PINMUX_IPSR_GPSR(IP0_1, D1),
+ PINMUX_IPSR_GPSR(IP0_2, D2),
+ PINMUX_IPSR_GPSR(IP0_3, D3),
+ PINMUX_IPSR_GPSR(IP0_4, D4),
+ PINMUX_IPSR_GPSR(IP0_5, D5),
+ PINMUX_IPSR_GPSR(IP0_6, D6),
+ PINMUX_IPSR_GPSR(IP0_7, D7),
+ PINMUX_IPSR_GPSR(IP0_8, D8),
+ PINMUX_IPSR_GPSR(IP0_9, D9),
+ PINMUX_IPSR_GPSR(IP0_10, D10),
+ PINMUX_IPSR_GPSR(IP0_11, D11),
+ PINMUX_IPSR_GPSR(IP0_12, D12),
+ PINMUX_IPSR_GPSR(IP0_13, D13),
+ PINMUX_IPSR_GPSR(IP0_14, D14),
+ PINMUX_IPSR_GPSR(IP0_15, D15),
+ PINMUX_IPSR_GPSR(IP0_18_16, A0),
+ PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
+ PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
+ PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
+ PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
+ PINMUX_IPSR_GPSR(IP0_20_19, A1),
+ PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP0_22_21, A2),
+ PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP0_24_23, A3),
+ PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP0_26_25, A4),
+ PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP0_28_27, A5),
+ PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
+ PINMUX_IPSR_GPSR(IP0_30_29, A6),
+ PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_1_0, A7),
+ PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
+ PINMUX_IPSR_GPSR(IP1_3_2, A8),
+ PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
+ PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
+ PINMUX_IPSR_GPSR(IP1_5_4, A9),
+ PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
+ PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
+ PINMUX_IPSR_GPSR(IP1_7_6, A10),
+ PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
+ PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
+ PINMUX_IPSR_GPSR(IP1_10_8, A11),
+ PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
+ PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
+ PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
+ PINMUX_IPSR_GPSR(IP1_13_11, A12),
+ PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
+ PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
+ PINMUX_IPSR_GPSR(IP1_16_14, A13),
+ PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
+ PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
+ PINMUX_IPSR_GPSR(IP1_19_17, A14),
+ PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
+ PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
+ PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
+ PINMUX_IPSR_GPSR(IP1_22_20, A15),
+ PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_GPSR(IP1_25_23, A16),
+ PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
+ PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_GPSR(IP1_28_26, A17),
+ PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
+ PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
+ PINMUX_IPSR_GPSR(IP1_31_29, A18),
+ PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
+ PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_2_0, A19),
+ PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
+ PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
+ PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_GPSR(IP2_2_0, A20),
+ PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
+ PINMUX_IPSR_GPSR(IP2_6_5, A21),
+ PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
+ PINMUX_IPSR_GPSR(IP2_9_7, A22),
+ PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
+ PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
+ PINMUX_IPSR_GPSR(IP2_12_10, A23),
+ PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
+ PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
+ PINMUX_IPSR_GPSR(IP2_15_13, A24),
+ PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
+ PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
+ PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_GPSR(IP2_18_16, A25),
+ PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
+ PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
+ PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
+ PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
+ PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
+ PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
+ PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
+ PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
+ PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
+ PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
+ PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
+ PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
+ PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
+ PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
+ PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
+ PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
+ PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
+ PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
+ PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
+ PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
+ PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
+ PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
+ PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
+ PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
+ PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
+ PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
+ PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
+ PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
+ PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
+ PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
+ PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
+ PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
+ PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
+ PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
+ PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
+ PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
+ PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
+ PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
+ PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
+ PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
+ PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
+ PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
+ PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
+ PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
+ PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
+ PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
+ PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
+
+ /* IPSR4 */
+ PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
+ PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
+ PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
+ PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
+ PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
+ PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
+ PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
+ PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
+ PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
+ PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
+ PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
+ PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
+ PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
+ PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
+ PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
+ PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
+ PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
+ PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
+ PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
+ PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
+ PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
+ PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
+ PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
+ PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
+ PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
+ PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
+ PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
+ PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
+ PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
+ PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
+ PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
+ PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
+ PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
+ PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
+ PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
+ PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
+ PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
+ PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
+ PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
+ PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
+ PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
+ PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
+ PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
+ PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
+ PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
+ PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
+ PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
+ PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
+ PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
+ PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
+ PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
+ PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
+ PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
+ PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
+
+ /* IPSR6 */
+ PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
+ PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
+ PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
+ PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
+ PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
+ PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
+ PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
+ PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
+ PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
+ PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
+ PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
+ PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
+ PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
+ PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
+ PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
+ PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
+ PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
+ PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
+ PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
+ PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
+ PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
+ PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
+ PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
+ PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
+ PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
+ PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
+ PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
+ PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
+ PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
+ PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
+ PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
+ PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
+ PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
+ PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
+ PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
+ PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
+ PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
+ PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
+ PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
+ PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
+ PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
+ PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
+ PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
+ PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
+ PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
+ PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
+ PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
+ PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
+ PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
+ PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
+ PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
+ PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
+ PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
+ PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
+ PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
+ PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
+ PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
+ PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
+ PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
+ PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
+ PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
+ PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
+ PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
+ PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
+ PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
+ PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
+ PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
+ PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
+ PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
+
+ /* IPSR8 */
+ PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
+ PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
+ PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
+ PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
+ PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
+ PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
+ PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
+ PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
+ PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
+ PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
+ PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
+ PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
+ PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
+ PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
+ PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
+ PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
+ PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
+ PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
+ PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
+ PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
+ PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
+ PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
+ PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
+ PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
+ PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
+ PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
+ PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
+ PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
+ PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
+ PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
+ PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
+ PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
+ PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
+ PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
+ PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
+ PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
+ PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
+ PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
+ PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
+ PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
+ PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP9_7, QCLK),
+ PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
+ PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
+ PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
+ PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
+ PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
+ PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
+ PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
+ PINMUX_IPSR_GPSR(IP9_16, QPOLA),
+ PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
+ PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
+ PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
+ PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
+ PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
+ PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
+ PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
+ PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
+ PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
+ PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
+ PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
+ PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
+
+ /* IPSR10 */
+ PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
+ PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
+ PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
+ PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
+ PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
+ PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
+ PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
+ PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
+ PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
+ PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
+ PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
+ PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
+ PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
+ PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
+ PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
+ PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
+ PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
+ PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
+ PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
+ PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
+ PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
+ PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
+ PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
+ PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
+ PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
+ PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
+ PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
+ PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
+ PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
+ PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
+ PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
+ PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
+ PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
+ PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
+ PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
+ PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
+ PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
+ PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
+ PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
+ PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
+ PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
+
+ /* IPSR11 */
+ PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
+ PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
+ PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
+ PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
+ PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
+ PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
+ PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
+ PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
+ PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
+ PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
+ PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
+ PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
+ PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
+ PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
+ PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
+ PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
+ PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
+ PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
+ PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
+ PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
+ PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
+ PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
+ PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
+ PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
+ PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
+ PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
+ PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
+ PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
+ PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
+ PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
+ PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
+ PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
+
+ /* IPSR12 */
+ PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
+ PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
+ PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
+ PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
+ PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
+ PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
+ PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
+ PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
+ PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
+ PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
+ PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
+ PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
+ PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
+ PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
+ PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
+ PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
+ PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
+ PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
+ PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
+ PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
+ PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
+ PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
+ PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
+ PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
+ PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
+ PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
+ PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
+ PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
+ PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
+ PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
+ PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
+ PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
+ PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
+ PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
+ PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
+ PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
+ PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
+ PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
+ PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
+ PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
+ PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
+ PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
+ PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
+
+ /* IPSR13 */
+ PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
+ PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
+ PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
+ PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
+ PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
+ PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
+ PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
+ PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
+ PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
+ PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
+ PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
+ PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
+ PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
+ PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
+ PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
+ PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
+ PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
+ PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
+ PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
+ PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
+ PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
+ PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
+ PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
+ PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
+ PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
+ PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
+ PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
+ PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
+ PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
+ PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
+ PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
+ PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
+ PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
+ PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
+ PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
+ PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
+ PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
+ PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
+ PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
+ PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
+ PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
+ PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
+ PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
+ PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
+ PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
+ PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
+ PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
+ PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
+ PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
+
+ /* IPSR14 */
+ PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
+ PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
+ PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
+ PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
+ PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
+ PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
+ PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
+ PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
+ PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
+ PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
+ PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
+ PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
+ PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
+ PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
+ PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
+ PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
+ PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
+ PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
+ PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
+ PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
+ PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
+ PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
+ PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
+ PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
+ PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
+ PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
+ PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
+ PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
+ PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
+ PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
+ PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
+ PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
+ PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
+ PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
+ PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
+ PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
+
+ /* IPSR15 */
+ PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
+ PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
+ PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
+ PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
+ PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
+ PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
+ PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
+ PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
+ PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
+ PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
+ PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
+ PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
+ PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
+ PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
+ PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
+ PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
+ PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
+ PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
+ PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
+ PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
+ PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
+ PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
+ PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
+ PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
+ PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
+
+ /* IPSR16 */
+ PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
+ PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
+ PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
+ PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
+ PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
+ PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
+ PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
+ PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
+ PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
+ PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
+ PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
+ PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
+ PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
+ PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - ADI -------------------------------------------------------------------- */
+static const unsigned int adi_common_pins[] = {
+ /* ADIDATA, ADICS/SAMP, ADICLK */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
+};
+static const unsigned int adi_common_mux[] = {
+ /* ADIDATA, ADICS/SAMP, ADICLK */
+ ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
+};
+static const unsigned int adi_chsel0_pins[] = {
+ /* ADICHS 0 */
+ RCAR_GP_PIN(6, 27),
+};
+static const unsigned int adi_chsel0_mux[] = {
+ /* ADICHS 0 */
+ ADICHS0_MARK,
+};
+static const unsigned int adi_chsel1_pins[] = {
+ /* ADICHS 1 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int adi_chsel1_mux[] = {
+ /* ADICHS 1 */
+ ADICHS1_MARK,
+};
+static const unsigned int adi_chsel2_pins[] = {
+ /* ADICHS 2 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int adi_chsel2_mux[] = {
+ /* ADICHS 2 */
+ ADICHS2_MARK,
+};
+static const unsigned int adi_common_b_pins[] = {
+ /* ADIDATA B, ADICS/SAMP B, ADICLK B */
+ RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
+};
+static const unsigned int adi_common_b_mux[] = {
+ /* ADIDATA B, ADICS/SAMP B, ADICLK B */
+ ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
+};
+static const unsigned int adi_chsel0_b_pins[] = {
+ /* ADICHS B 0 */
+ RCAR_GP_PIN(5, 28),
+};
+static const unsigned int adi_chsel0_b_mux[] = {
+ /* ADICHS B 0 */
+ ADICHS0_B_MARK,
+};
+static const unsigned int adi_chsel1_b_pins[] = {
+ /* ADICHS B 1 */
+ RCAR_GP_PIN(5, 29),
+};
+static const unsigned int adi_chsel1_b_mux[] = {
+ /* ADICHS B 1 */
+ ADICHS1_B_MARK,
+};
+static const unsigned int adi_chsel2_b_pins[] = {
+ /* ADICHS B 2 */
+ RCAR_GP_PIN(5, 30),
+};
+static const unsigned int adi_chsel2_b_mux[] = {
+ /* ADICHS B 2 */
+ ADICHS2_B_MARK,
+};
+
+/* - Audio Clock ------------------------------------------------------------ */
+static const unsigned int audio_clk_a_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 28),
+};
+
+static const unsigned int audio_clk_a_mux[] = {
+ AUDIO_CLKA_MARK,
+};
+
+static const unsigned int audio_clk_b_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 29),
+};
+
+static const unsigned int audio_clk_b_mux[] = {
+ AUDIO_CLKB_MARK,
+};
+
+static const unsigned int audio_clk_b_b_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(7, 20),
+};
+
+static const unsigned int audio_clk_b_b_mux[] = {
+ AUDIO_CLKB_B_MARK,
+};
+
+static const unsigned int audio_clk_c_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 30),
+};
+
+static const unsigned int audio_clk_c_mux[] = {
+ AUDIO_CLKC_MARK,
+};
+
+static const unsigned int audio_clkout_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 31),
+};
+
+static const unsigned int audio_clkout_mux[] = {
+ AUDIO_CLKOUT_MARK,
+};
+
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ RCAR_GP_PIN(5, 14),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ RCAR_GP_PIN(5, 11),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+ RCAR_GP_PIN(5, 21),
+
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+ RCAR_GP_PIN(5, 3),
+
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
+ RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
+};
+static const unsigned int avb_mii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+ AVB_TX_CLK_MARK, AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+ RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
+ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
+ RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
+ RCAR_GP_PIN(5, 29),
+};
+static const unsigned int avb_gmii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+ AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+ AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+ AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+ AVB_COL_MARK,
+};
+
+/* - CAN -------------------------------------------------------------------- */
+
+static const unsigned int can0_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
+};
+
+static const unsigned int can0_data_mux[] = {
+ CAN0_TX_MARK, CAN0_RX_MARK,
+};
+
+static const unsigned int can0_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
+};
+
+static const unsigned int can0_data_b_mux[] = {
+ CAN0_TX_B_MARK, CAN0_RX_B_MARK,
+};
+
+static const unsigned int can0_data_c_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int can0_data_c_mux[] = {
+ CAN0_TX_C_MARK, CAN0_RX_C_MARK,
+};
+
+static const unsigned int can0_data_d_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
+};
+
+static const unsigned int can0_data_d_mux[] = {
+ CAN0_TX_D_MARK, CAN0_RX_D_MARK,
+};
+
+static const unsigned int can0_data_e_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
+};
+
+static const unsigned int can0_data_e_mux[] = {
+ CAN0_TX_E_MARK, CAN0_RX_E_MARK,
+};
+
+static const unsigned int can0_data_f_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
+};
+
+static const unsigned int can0_data_f_mux[] = {
+ CAN0_TX_F_MARK, CAN0_RX_F_MARK,
+};
+
+static const unsigned int can1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
+};
+
+static const unsigned int can1_data_mux[] = {
+ CAN1_TX_MARK, CAN1_RX_MARK,
+};
+
+static const unsigned int can1_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
+};
+
+static const unsigned int can1_data_b_mux[] = {
+ CAN1_TX_B_MARK, CAN1_RX_B_MARK,
+};
+
+static const unsigned int can1_data_c_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
+};
+
+static const unsigned int can1_data_c_mux[] = {
+ CAN1_TX_C_MARK, CAN1_RX_C_MARK,
+};
+
+static const unsigned int can1_data_d_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
+};
+
+static const unsigned int can1_data_d_mux[] = {
+ CAN1_TX_D_MARK, CAN1_RX_D_MARK,
+};
+
+static const unsigned int can_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(7, 2),
+};
+
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
+static const unsigned int can_clk_b_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(5, 21),
+};
+
+static const unsigned int can_clk_b_mux[] = {
+ CAN_CLK_B_MARK,
+};
+
+static const unsigned int can_clk_c_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(4, 30),
+};
+
+static const unsigned int can_clk_c_mux[] = {
+ CAN_CLK_C_MARK,
+};
+
+static const unsigned int can_clk_d_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(7, 19),
+};
+
+static const unsigned int can_clk_d_mux[] = {
+ CAN_CLK_D_MARK,
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(3, 25),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU1_DOTCLKOUT0_MARK
+};
+static const unsigned int du_clk_out_1_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int du_clk_out_1_mux[] = {
+ DU1_DOTCLKOUT1_MARK
+};
+static const unsigned int du_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
+};
+static const unsigned int du_sync_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
+};
+static const unsigned int du_oddf_pins[] = {
+ /* EXDISP/EXODDF/EXCDE */
+ RCAR_GP_PIN(3, 29),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(3, 31),
+};
+static const unsigned int du_cde_mux[] = {
+ DU1_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(3, 30),
+};
+static const unsigned int du_disp_mux[] = {
+ DU1_DISP_MARK,
+};
+static const unsigned int du0_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int du0_clk_in_mux[] = {
+ DU0_DOTCLKIN_MARK
+};
+static const unsigned int du1_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(3, 24),
+};
+static const unsigned int du1_clk_in_mux[] = {
+ DU1_DOTCLKIN_MARK
+};
+static const unsigned int du1_clk_in_b_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(7, 19),
+};
+static const unsigned int du1_clk_in_b_mux[] = {
+ DU1_DOTCLKIN_B_MARK,
+};
+static const unsigned int du1_clk_in_c_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(7, 20),
+};
+static const unsigned int du1_clk_in_c_mux[] = {
+ DU1_DOTCLKIN_C_MARK,
+};
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+ /* LINK */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int eth_link_mux[] = {
+ ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+ /* MAGIC */
+ RCAR_GP_PIN(5, 22),
+};
+static const unsigned int eth_magic_mux[] = {
+ ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+ /* MDC, MDIO */
+ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
+};
+static const unsigned int eth_mdio_mux[] = {
+ ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
+ RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
+};
+static const unsigned int eth_rmii_mux[] = {
+ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+static const unsigned int hscif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int hscif0_data_b_mux[] = {
+ HRX0_B_MARK, HTX0_B_MARK,
+};
+static const unsigned int hscif0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int hscif0_ctrl_b_mux[] = {
+ HRTS0_N_B_MARK, HCTS0_N_B_MARK,
+};
+static const unsigned int hscif0_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int hscif0_data_c_mux[] = {
+ HRX0_C_MARK, HTX0_C_MARK,
+};
+static const unsigned int hscif0_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int hscif0_clk_c_mux[] = {
+ HSCK0_C_MARK,
+};
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 7),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+static const unsigned int hscif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int hscif1_data_b_mux[] = {
+ HRX1_B_MARK, HTX1_B_MARK,
+};
+static const unsigned int hscif1_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
+};
+static const unsigned int hscif1_data_c_mux[] = {
+ HRX1_C_MARK, HTX1_C_MARK,
+};
+static const unsigned int hscif1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 16),
+};
+static const unsigned int hscif1_clk_c_mux[] = {
+ HSCK1_C_MARK,
+};
+static const unsigned int hscif1_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
+};
+static const unsigned int hscif1_ctrl_c_mux[] = {
+ HRTS1_N_C_MARK, HCTS1_N_C_MARK,
+};
+static const unsigned int hscif1_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int hscif1_data_d_mux[] = {
+ HRX1_D_MARK, HTX1_D_MARK,
+};
+static const unsigned int hscif1_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
+};
+static const unsigned int hscif1_data_e_mux[] = {
+ HRX1_C_MARK, HTX1_C_MARK,
+};
+static const unsigned int hscif1_clk_e_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int hscif1_clk_e_mux[] = {
+ HSCK1_E_MARK,
+};
+static const unsigned int hscif1_ctrl_e_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
+};
+static const unsigned int hscif1_ctrl_e_mux[] = {
+ HRTS1_N_E_MARK, HCTS1_N_E_MARK,
+};
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 15),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+static const unsigned int hscif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int hscif2_data_b_mux[] = {
+ HRX2_B_MARK, HTX2_B_MARK,
+};
+static const unsigned int hscif2_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int hscif2_ctrl_b_mux[] = {
+ HRTS2_N_B_MARK, HCTS2_N_B_MARK,
+};
+static const unsigned int hscif2_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int hscif2_data_c_mux[] = {
+ HRX2_C_MARK, HTX2_C_MARK,
+};
+static const unsigned int hscif2_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int hscif2_clk_c_mux[] = {
+ HSCK2_C_MARK,
+};
+static const unsigned int hscif2_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
+};
+static const unsigned int hscif2_data_d_mux[] = {
+ HRX2_B_MARK, HTX2_D_MARK,
+};
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int i2c0_mux[] = {
+ I2C0_SCL_MARK, I2C0_SDA_MARK,
+};
+static const unsigned int i2c0_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int i2c0_b_mux[] = {
+ I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
+};
+static const unsigned int i2c0_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int i2c0_c_mux[] = {
+ I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
+};
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
+};
+static const unsigned int i2c1_mux[] = {
+ I2C1_SCL_MARK, I2C1_SDA_MARK,
+};
+static const unsigned int i2c1_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int i2c1_b_mux[] = {
+ I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
+};
+static const unsigned int i2c1_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+};
+static const unsigned int i2c1_c_mux[] = {
+ I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
+};
+static const unsigned int i2c1_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+};
+static const unsigned int i2c1_d_mux[] = {
+ I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
+};
+static const unsigned int i2c1_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
+};
+static const unsigned int i2c1_e_mux[] = {
+ I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
+};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+static const unsigned int i2c2_mux[] = {
+ I2C2_SCL_MARK, I2C2_SDA_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int i2c2_b_mux[] = {
+ I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
+};
+static const unsigned int i2c2_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
+};
+static const unsigned int i2c2_c_mux[] = {
+ I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
+};
+static const unsigned int i2c2_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+static const unsigned int i2c2_d_mux[] = {
+ I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int i2c3_mux[] = {
+ I2C3_SCL_MARK, I2C3_SDA_MARK,
+};
+static const unsigned int i2c3_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int i2c3_b_mux[] = {
+ I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
+};
+static const unsigned int i2c3_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+};
+static const unsigned int i2c3_c_mux[] = {
+ I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
+};
+static const unsigned int i2c3_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+};
+static const unsigned int i2c3_d_mux[] = {
+ I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
+};
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+};
+static const unsigned int i2c4_mux[] = {
+ I2C4_SCL_MARK, I2C4_SDA_MARK,
+};
+static const unsigned int i2c4_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int i2c4_b_mux[] = {
+ I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
+};
+static const unsigned int i2c4_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
+};
+static const unsigned int i2c4_c_mux[] = {
+ I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
+};
+/* - I2C7 ------------------------------------------------------------------- */
+static const unsigned int i2c7_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int i2c7_mux[] = {
+ IIC0_SCL_MARK, IIC0_SDA_MARK,
+};
+static const unsigned int i2c7_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int i2c7_b_mux[] = {
+ IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
+};
+static const unsigned int i2c7_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+static const unsigned int i2c7_c_mux[] = {
+ IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
+};
+/* - I2C8 ------------------------------------------------------------------- */
+static const unsigned int i2c8_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+};
+static const unsigned int i2c8_mux[] = {
+ IIC1_SCL_MARK, IIC1_SDA_MARK,
+};
+static const unsigned int i2c8_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int i2c8_b_mux[] = {
+ IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
+};
+static const unsigned int i2c8_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
+};
+static const unsigned int i2c8_c_mux[] = {
+ IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 10),
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 11),
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 12),
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 13),
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+/* - MLB+ ------------------------------------------------------------------- */
+static const unsigned int mlb_3pin_pins[] = {
+ RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
+};
+static const unsigned int mlb_3pin_mux[] = {
+ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc_data1_pins[] = {
+ /* D[0] */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_data8_b_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
+};
+static const unsigned int mmc_data8_b_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 24),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(6, 25),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(6, 27),
+};
+static const unsigned int msiof0_rx_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+static const unsigned int msiof0_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(6, 26),
+};
+static const unsigned int msiof0_tx_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+
+static const unsigned int msiof0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof0_clk_b_mux[] = {
+ MSIOF0_SCK_B_MARK,
+};
+static const unsigned int msiof0_sync_b_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof0_sync_b_mux[] = {
+ MSIOF0_SYNC_B_MARK,
+};
+static const unsigned int msiof0_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof0_ss1_b_mux[] = {
+ MSIOF0_SS1_B_MARK,
+};
+static const unsigned int msiof0_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int msiof0_ss2_b_mux[] = {
+ MSIOF0_SS2_B_MARK,
+};
+static const unsigned int msiof0_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int msiof0_rx_b_mux[] = {
+ MSIOF0_RXD_B_MARK,
+};
+static const unsigned int msiof0_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int msiof0_tx_b_mux[] = {
+ MSIOF0_TXD_B_MARK,
+};
+
+static const unsigned int msiof0_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 26),
+};
+static const unsigned int msiof0_clk_c_mux[] = {
+ MSIOF0_SCK_C_MARK,
+};
+static const unsigned int msiof0_sync_c_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(5, 25),
+};
+static const unsigned int msiof0_sync_c_mux[] = {
+ MSIOF0_SYNC_C_MARK,
+};
+static const unsigned int msiof0_ss1_c_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(5, 27),
+};
+static const unsigned int msiof0_ss1_c_mux[] = {
+ MSIOF0_SS1_C_MARK,
+};
+static const unsigned int msiof0_ss2_c_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(5, 28),
+};
+static const unsigned int msiof0_ss2_c_mux[] = {
+ MSIOF0_SS2_C_MARK,
+};
+static const unsigned int msiof0_rx_c_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(5, 29),
+};
+static const unsigned int msiof0_rx_c_mux[] = {
+ MSIOF0_RXD_C_MARK,
+};
+static const unsigned int msiof0_tx_c_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(5, 30),
+};
+static const unsigned int msiof0_tx_c_mux[] = {
+ MSIOF0_TXD_C_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 22),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 23),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 24),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 25),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 27),
+};
+static const unsigned int msiof1_rx_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+static const unsigned int msiof1_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 26),
+};
+static const unsigned int msiof1_tx_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+
+static const unsigned int msiof1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 29),
+};
+static const unsigned int msiof1_clk_b_mux[] = {
+ MSIOF1_SCK_B_MARK,
+};
+static const unsigned int msiof1_sync_b_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(2, 30),
+};
+static const unsigned int msiof1_sync_b_mux[] = {
+ MSIOF1_SYNC_B_MARK,
+};
+static const unsigned int msiof1_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(2, 31),
+};
+static const unsigned int msiof1_ss1_b_mux[] = {
+ MSIOF1_SS1_B_MARK,
+};
+static const unsigned int msiof1_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(7, 16),
+};
+static const unsigned int msiof1_ss2_b_mux[] = {
+ MSIOF1_SS2_B_MARK,
+};
+static const unsigned int msiof1_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(7, 18),
+};
+static const unsigned int msiof1_rx_b_mux[] = {
+ MSIOF1_RXD_B_MARK,
+};
+static const unsigned int msiof1_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(7, 17),
+};
+static const unsigned int msiof1_tx_b_mux[] = {
+ MSIOF1_TXD_B_MARK,
+};
+
+static const unsigned int msiof1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int msiof1_clk_c_mux[] = {
+ MSIOF1_SCK_C_MARK,
+};
+static const unsigned int msiof1_sync_c_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int msiof1_sync_c_mux[] = {
+ MSIOF1_SYNC_C_MARK,
+};
+static const unsigned int msiof1_rx_c_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int msiof1_rx_c_mux[] = {
+ MSIOF1_RXD_C_MARK,
+};
+static const unsigned int msiof1_tx_c_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int msiof1_tx_c_mux[] = {
+ MSIOF1_TXD_C_MARK,
+};
+
+static const unsigned int msiof1_clk_d_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 28),
+};
+static const unsigned int msiof1_clk_d_mux[] = {
+ MSIOF1_SCK_D_MARK,
+};
+static const unsigned int msiof1_sync_d_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 30),
+};
+static const unsigned int msiof1_sync_d_mux[] = {
+ MSIOF1_SYNC_D_MARK,
+};
+static const unsigned int msiof1_ss1_d_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 29),
+};
+static const unsigned int msiof1_ss1_d_mux[] = {
+ MSIOF1_SS1_D_MARK,
+};
+static const unsigned int msiof1_rx_d_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 27),
+};
+static const unsigned int msiof1_rx_d_mux[] = {
+ MSIOF1_RXD_D_MARK,
+};
+static const unsigned int msiof1_tx_d_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 26),
+};
+static const unsigned int msiof1_tx_d_mux[] = {
+ MSIOF1_TXD_D_MARK,
+};
+
+static const unsigned int msiof1_clk_e_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int msiof1_clk_e_mux[] = {
+ MSIOF1_SCK_E_MARK,
+};
+static const unsigned int msiof1_sync_e_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int msiof1_sync_e_mux[] = {
+ MSIOF1_SYNC_E_MARK,
+};
+static const unsigned int msiof1_rx_e_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(5, 17),
+};
+static const unsigned int msiof1_rx_e_mux[] = {
+ MSIOF1_RXD_E_MARK,
+};
+static const unsigned int msiof1_tx_e_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int msiof1_tx_e_mux[] = {
+ MSIOF1_TXD_E_MARK,
+};
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int msiof2_rx_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+static const unsigned int msiof2_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof2_tx_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+
+static const unsigned int msiof2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof2_clk_b_mux[] = {
+ MSIOF2_SCK_B_MARK,
+};
+static const unsigned int msiof2_sync_b_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof2_sync_b_mux[] = {
+ MSIOF2_SYNC_B_MARK,
+};
+static const unsigned int msiof2_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int msiof2_ss1_b_mux[] = {
+ MSIOF2_SS1_B_MARK,
+};
+static const unsigned int msiof2_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int msiof2_ss2_b_mux[] = {
+ MSIOF2_SS2_B_MARK,
+};
+static const unsigned int msiof2_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(3, 17),
+};
+static const unsigned int msiof2_rx_b_mux[] = {
+ MSIOF2_RXD_B_MARK,
+};
+static const unsigned int msiof2_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int msiof2_tx_b_mux[] = {
+ MSIOF2_TXD_B_MARK,
+};
+
+static const unsigned int msiof2_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int msiof2_clk_c_mux[] = {
+ MSIOF2_SCK_C_MARK,
+};
+static const unsigned int msiof2_sync_c_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int msiof2_sync_c_mux[] = {
+ MSIOF2_SYNC_C_MARK,
+};
+static const unsigned int msiof2_rx_c_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof2_rx_c_mux[] = {
+ MSIOF2_RXD_C_MARK,
+};
+static const unsigned int msiof2_tx_c_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof2_tx_c_mux[] = {
+ MSIOF2_TXD_C_MARK,
+};
+
+static const unsigned int msiof2_clk_d_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int msiof2_clk_d_mux[] = {
+ MSIOF2_SCK_D_MARK,
+};
+static const unsigned int msiof2_sync_d_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int msiof2_sync_d_mux[] = {
+ MSIOF2_SYNC_D_MARK,
+};
+static const unsigned int msiof2_ss1_d_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int msiof2_ss1_d_mux[] = {
+ MSIOF2_SS1_D_MARK,
+};
+static const unsigned int msiof2_ss2_d_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(2, 19),
+};
+static const unsigned int msiof2_ss2_d_mux[] = {
+ MSIOF2_SS2_D_MARK,
+};
+static const unsigned int msiof2_rx_d_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int msiof2_rx_d_mux[] = {
+ MSIOF2_RXD_D_MARK,
+};
+static const unsigned int msiof2_tx_d_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int msiof2_tx_d_mux[] = {
+ MSIOF2_TXD_D_MARK,
+};
+
+static const unsigned int msiof2_clk_e_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 15),
+};
+static const unsigned int msiof2_clk_e_mux[] = {
+ MSIOF2_SCK_E_MARK,
+};
+static const unsigned int msiof2_sync_e_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(7, 16),
+};
+static const unsigned int msiof2_sync_e_mux[] = {
+ MSIOF2_SYNC_E_MARK,
+};
+static const unsigned int msiof2_rx_e_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(7, 14),
+};
+static const unsigned int msiof2_rx_e_mux[] = {
+ MSIOF2_RXD_E_MARK,
+};
+static const unsigned int msiof2_tx_e_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(7, 13),
+};
+static const unsigned int msiof2_tx_e_mux[] = {
+ MSIOF2_TXD_E_MARK,
+};
+/* - PWM -------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+ RCAR_GP_PIN(6, 14),
+};
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
+};
+static const unsigned int pwm0_b_pins[] = {
+ RCAR_GP_PIN(5, 30),
+};
+static const unsigned int pwm0_b_mux[] = {
+ PWM0_B_MARK,
+};
+static const unsigned int pwm1_pins[] = {
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int pwm1_mux[] = {
+ PWM1_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+static const unsigned int pwm2_pins[] = {
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int pwm2_mux[] = {
+ PWM2_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
+};
+static const unsigned int pwm3_pins[] = {
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int pwm3_mux[] = {
+ PWM3_MARK,
+};
+static const unsigned int pwm4_pins[] = {
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int pwm4_mux[] = {
+ PWM4_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+ RCAR_GP_PIN(3, 31),
+};
+static const unsigned int pwm4_b_mux[] = {
+ PWM4_B_MARK,
+};
+static const unsigned int pwm5_pins[] = {
+ RCAR_GP_PIN(7, 21),
+};
+static const unsigned int pwm5_mux[] = {
+ PWM5_MARK,
+};
+static const unsigned int pwm5_b_pins[] = {
+ RCAR_GP_PIN(7, 20),
+};
+static const unsigned int pwm5_b_mux[] = {
+ PWM5_B_MARK,
+};
+static const unsigned int pwm6_pins[] = {
+ RCAR_GP_PIN(7, 22),
+};
+static const unsigned int pwm6_mux[] = {
+ PWM6_MARK,
+};
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+ SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
+
+static const unsigned int qspi_ctrl_b_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int qspi_ctrl_b_mux[] = {
+ SPCLK_B_MARK, SSL_B_MARK,
+};
+static const unsigned int qspi_data2_b_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
+};
+static const unsigned int qspi_data2_b_mux[] = {
+ MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
+};
+static const unsigned int qspi_data4_b_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+ RCAR_GP_PIN(6, 4),
+};
+static const unsigned int qspi_data4_b_mux[] = {
+ SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
+ IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
+};
+static const unsigned int scif0_data_c_mux[] = {
+ RX0_C_MARK, TX0_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif0_data_d_mux[] = {
+ RX0_D_MARK, TX0_D_MARK,
+};
+static const unsigned int scif0_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
+};
+static const unsigned int scif0_data_e_mux[] = {
+ RX0_E_MARK, TX0_E_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCIF1_SCK_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif1_data_c_mux[] = {
+ RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int scif1_data_d_mux[] = {
+ RX1_D_MARK, TX1_D_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int scif2_data_b_mux[] = {
+ RX2_B_MARK, TX2_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int scif2_clk_b_mux[] = {
+ SCIF2_SCK_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int scif2_data_c_mux[] = {
+ RX2_C_MARK, TX2_C_MARK,
+};
+static const unsigned int scif2_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int scif2_data_e_mux[] = {
+ RX2_E_MARK, TX2_E_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 23),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCIF3_SCK_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_MARK, TX3_B_MARK,
+};
+static const unsigned int scif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scif3_clk_b_mux[] = {
+ SCIF3_SCK_B_MARK,
+};
+static const unsigned int scif3_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
+};
+static const unsigned int scif3_data_c_mux[] = {
+ RX3_C_MARK, TX3_C_MARK,
+};
+static const unsigned int scif3_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
+};
+static const unsigned int scif3_data_d_mux[] = {
+ RX3_D_MARK, TX3_D_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
+};
+static const unsigned int scif4_data_c_mux[] = {
+ RX4_C_MARK, TX4_C_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int scif5_data_mux[] = {
+ RX5_MARK, TX5_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scifa0_data_mux[] = {
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+ SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scifa1_data_mux[] = {
+ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int scifa1_clk_mux[] = {
+ SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+ SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+ SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+ SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
+};
+static const unsigned int scifa2_data_mux[] = {
+ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int scifa2_clk_mux[] = {
+ SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+ SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int scifa3_data_mux[] = {
+ SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 23),
+};
+static const unsigned int scifa3_clk_mux[] = {
+ SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+};
+static const unsigned int scifa3_data_b_mux[] = {
+ SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
+};
+static const unsigned int scifa3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifa3_clk_b_mux[] = {
+ SCIFA3_SCK_B_MARK,
+};
+static const unsigned int scifa3_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
+};
+static const unsigned int scifa3_data_c_mux[] = {
+ SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
+};
+static const unsigned int scifa3_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 22),
+};
+static const unsigned int scifa3_clk_c_mux[] = {
+ SCIFA3_SCK_C_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scifa4_data_mux[] = {
+ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+static const unsigned int scifa4_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scifa4_data_b_mux[] = {
+ SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
+};
+static const unsigned int scifa4_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
+};
+static const unsigned int scifa4_data_c_mux[] = {
+ SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int scifa5_data_mux[] = {
+ SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
+};
+static const unsigned int scifa5_data_b_mux[] = {
+ SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
+};
+static const unsigned int scifa5_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
+};
+static const unsigned int scifa5_data_c_mux[] = {
+ SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
+};
+static const unsigned int scifb0_data_mux[] = {
+ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int scifb0_clk_mux[] = {
+ SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+ SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+ SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+ SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+ SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+ SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+static const unsigned int scifb0_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 30),
+};
+static const unsigned int scifb0_clk_c_mux[] = {
+ SCIFB0_SCK_C_MARK,
+};
+static const unsigned int scifb0_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int scifb0_data_d_mux[] = {
+ SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
+};
+static const unsigned int scifb0_clk_d_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb0_clk_d_mux[] = {
+ SCIFB0_SCK_D_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
+};
+static const unsigned int scifb1_data_mux[] = {
+ SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 7),
+};
+static const unsigned int scifb1_clk_mux[] = {
+ SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+ SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+ SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+ SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+ SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 11),
+};
+static const unsigned int scifb1_clk_c_mux[] = {
+ SCIFB1_SCK_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+ SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb2_data_mux[] = {
+ SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 15),
+};
+static const unsigned int scifb2_clk_mux[] = {
+ SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+ SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+ SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+ SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+ SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+ SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+static const unsigned int scifb2_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 27),
+};
+static const unsigned int scifb2_clk_c_mux[] = {
+ SCIFB2_SCK_C_MARK,
+};
+static const unsigned int scifb2_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int scifb2_data_d_mux[] = {
+ SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(2, 29),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(7, 19),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DATA0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DATA0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SD2_DATA0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+ SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+ SD2_WP_MARK,
+};
+
+/* - SSI -------------------------------------------------------------------- */
+static const unsigned int ssi0_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 2),
+};
+
+static const unsigned int ssi0_data_mux[] = {
+ SSI_SDATA0_MARK,
+};
+
+static const unsigned int ssi0_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(3, 4),
+};
+
+static const unsigned int ssi0_data_b_mux[] = {
+ SSI_SDATA0_B_MARK,
+};
+
+static const unsigned int ssi0129_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+
+static const unsigned int ssi0129_ctrl_mux[] = {
+ SSI_SCK0129_MARK, SSI_WS0129_MARK,
+};
+
+static const unsigned int ssi0129_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int ssi0129_ctrl_b_mux[] = {
+ SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
+};
+
+static const unsigned int ssi1_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 5),
+};
+
+static const unsigned int ssi1_data_mux[] = {
+ SSI_SDATA1_MARK,
+};
+
+static const unsigned int ssi1_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(3, 7),
+};
+
+static const unsigned int ssi1_data_b_mux[] = {
+ SSI_SDATA1_B_MARK,
+};
+
+static const unsigned int ssi1_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+};
+
+static const unsigned int ssi1_ctrl_mux[] = {
+ SSI_SCK1_MARK, SSI_WS1_MARK,
+};
+
+static const unsigned int ssi1_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+};
+
+static const unsigned int ssi1_ctrl_b_mux[] = {
+ SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
+};
+
+static const unsigned int ssi2_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 8),
+};
+
+static const unsigned int ssi2_data_mux[] = {
+ SSI_SDATA2_MARK,
+};
+
+static const unsigned int ssi2_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+
+static const unsigned int ssi2_ctrl_mux[] = {
+ SSI_SCK2_MARK, SSI_WS2_MARK,
+};
+
+static const unsigned int ssi3_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int ssi3_data_mux[] = {
+ SSI_SDATA3_MARK,
+};
+
+static const unsigned int ssi34_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+};
+
+static const unsigned int ssi34_ctrl_mux[] = {
+ SSI_SCK34_MARK, SSI_WS34_MARK,
+};
+
+static const unsigned int ssi4_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 14),
+};
+
+static const unsigned int ssi4_data_mux[] = {
+ SSI_SDATA4_MARK,
+};
+
+static const unsigned int ssi4_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+
+static const unsigned int ssi4_ctrl_mux[] = {
+ SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+
+static const unsigned int ssi5_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 17),
+};
+
+static const unsigned int ssi5_data_mux[] = {
+ SSI_SDATA5_MARK,
+};
+
+static const unsigned int ssi5_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+};
+
+static const unsigned int ssi5_ctrl_mux[] = {
+ SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+
+static const unsigned int ssi6_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 20),
+};
+
+static const unsigned int ssi6_data_mux[] = {
+ SSI_SDATA6_MARK,
+};
+
+static const unsigned int ssi6_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+
+static const unsigned int ssi6_ctrl_mux[] = {
+ SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+
+static const unsigned int ssi7_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 23),
+};
+
+static const unsigned int ssi7_data_mux[] = {
+ SSI_SDATA7_MARK,
+};
+
+static const unsigned int ssi7_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int ssi7_data_b_mux[] = {
+ SSI_SDATA7_B_MARK,
+};
+
+static const unsigned int ssi78_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int ssi78_ctrl_mux[] = {
+ SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+
+static const unsigned int ssi78_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int ssi78_ctrl_b_mux[] = {
+ SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
+};
+
+static const unsigned int ssi8_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int ssi8_data_mux[] = {
+ SSI_SDATA8_MARK,
+};
+
+static const unsigned int ssi8_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int ssi8_data_b_mux[] = {
+ SSI_SDATA8_B_MARK,
+};
+
+static const unsigned int ssi9_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(2, 27),
+};
+
+static const unsigned int ssi9_data_mux[] = {
+ SSI_SDATA9_MARK,
+};
+
+static const unsigned int ssi9_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(3, 18),
+};
+
+static const unsigned int ssi9_data_b_mux[] = {
+ SSI_SDATA9_B_MARK,
+};
+
+static const unsigned int ssi9_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+};
+
+static const unsigned int ssi9_ctrl_mux[] = {
+ SSI_SCK9_MARK, SSI_WS9_MARK,
+};
+
+static const unsigned int ssi9_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int ssi9_ctrl_b_mux[] = {
+ SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+};
+
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ RCAR_GP_PIN(7, 23), /* PWEN */
+ RCAR_GP_PIN(7, 24), /* OVC */
+};
+static const unsigned int usb0_mux[] = {
+ USB0_PWEN_MARK,
+ USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ RCAR_GP_PIN(7, 25), /* PWEN */
+ RCAR_GP_PIN(6, 30), /* OVC */
+};
+static const unsigned int usb1_mux[] = {
+ USB1_PWEN_MARK,
+ USB1_OVC_MARK,
+};
+/* - VIN0 ------------------------------------------------------------------- */
+static const union vin_data vin0_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+ /* G */
+ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+ RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
+ /* R */
+ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
+ },
+};
+static const union vin_data vin0_data_mux = {
+ .data24 = {
+ /* B */
+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G0_MARK, VI0_G1_MARK,
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R0_MARK, VI0_R1_MARK,
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
+ },
+};
+static const unsigned int vin0_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+ /* G */
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+ RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
+ /* R */
+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int vin0_data18_mux[] = {
+ /* B */
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ RCAR_GP_PIN(4, 3), /* HSYNC */
+ RCAR_GP_PIN(4, 4), /* VSYNC */
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_HSYNC_N_MARK,
+ VI0_VSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ RCAR_GP_PIN(4, 2),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ RCAR_GP_PIN(4, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+/* - VIN1 ----------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+};
+static const unsigned int vin1_data8_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+ RCAR_GP_PIN(5, 0), /* HSYNC */
+ RCAR_GP_PIN(5, 1), /* VSYNC */
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_HSYNC_N_MARK,
+ VI1_VSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+static const union vin_data vin1_b_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+ /* G */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+ RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
+ /* R */
+ RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ },
+};
+static const union vin_data vin1_b_data_mux = {
+ .data24 = {
+ /* B */
+ VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
+ VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
+ VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
+ VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
+ /* G */
+ VI1_G0_B_MARK, VI1_G1_B_MARK,
+ VI1_G2_B_MARK, VI1_G3_B_MARK,
+ VI1_G4_B_MARK, VI1_G5_B_MARK,
+ VI1_G6_B_MARK, VI1_G7_B_MARK,
+ /* R */
+ VI1_R0_B_MARK, VI1_R1_B_MARK,
+ VI1_R2_B_MARK, VI1_R3_B_MARK,
+ VI1_R4_B_MARK, VI1_R5_B_MARK,
+ VI1_R6_B_MARK, VI1_R7_B_MARK,
+ },
+};
+static const unsigned int vin1_b_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+ /* G */
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+ RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
+ /* R */
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+};
+static const unsigned int vin1_b_data18_mux[] = {
+ /* B */
+ VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
+ VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
+ VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
+ VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
+ /* G */
+ VI1_G0_B_MARK, VI1_G1_B_MARK,
+ VI1_G2_B_MARK, VI1_G3_B_MARK,
+ VI1_G4_B_MARK, VI1_G5_B_MARK,
+ VI1_G6_B_MARK, VI1_G7_B_MARK,
+ /* R */
+ VI1_R0_B_MARK, VI1_R1_B_MARK,
+ VI1_R2_B_MARK, VI1_R3_B_MARK,
+ VI1_R4_B_MARK, VI1_R5_B_MARK,
+ VI1_R6_B_MARK, VI1_R7_B_MARK,
+};
+static const unsigned int vin1_b_sync_pins[] = {
+ RCAR_GP_PIN(3, 17), /* HSYNC */
+ RCAR_GP_PIN(3, 18), /* VSYNC */
+};
+static const unsigned int vin1_b_sync_mux[] = {
+ VI1_HSYNC_N_B_MARK,
+ VI1_VSYNC_N_B_MARK,
+};
+static const unsigned int vin1_b_field_pins[] = {
+ RCAR_GP_PIN(3, 20),
+};
+static const unsigned int vin1_b_field_mux[] = {
+ VI1_FIELD_B_MARK,
+};
+static const unsigned int vin1_b_clkenb_pins[] = {
+ RCAR_GP_PIN(3, 19),
+};
+static const unsigned int vin1_b_clkenb_mux[] = {
+ VI1_CLKENB_B_MARK,
+};
+static const unsigned int vin1_b_clk_pins[] = {
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin1_b_clk_mux[] = {
+ VI1_CLK_B_MARK,
+};
+/* - VIN2 ----------------------------------------------------------------- */
+static const unsigned int vin2_data8_pins[] = {
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+ RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
+ RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int vin2_data8_mux[] = {
+ VI2_DATA0_MARK, VI2_DATA1_MARK,
+ VI2_DATA2_MARK, VI2_DATA3_MARK,
+ VI2_DATA4_MARK, VI2_DATA5_MARK,
+ VI2_DATA6_MARK, VI2_DATA7_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+ RCAR_GP_PIN(4, 15), /* HSYNC */
+ RCAR_GP_PIN(4, 16), /* VSYNC */
+};
+static const unsigned int vin2_sync_mux[] = {
+ VI2_HSYNC_N_MARK,
+ VI2_VSYNC_N_MARK,
+};
+static const unsigned int vin2_field_pins[] = {
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int vin2_field_mux[] = {
+ VI2_FIELD_MARK,
+};
+static const unsigned int vin2_clkenb_pins[] = {
+ RCAR_GP_PIN(4, 17),
+};
+static const unsigned int vin2_clkenb_mux[] = {
+ VI2_CLKENB_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int vin2_clk_mux[] = {
+ VI2_CLK_MARK,
+};
+
+static const struct {
+ struct sh_pfc_pin_group common[342];
+ struct sh_pfc_pin_group r8a779x[9];
+} pinmux_groups = {
+ .common = {
+ SH_PFC_PIN_GROUP(audio_clk_a),
+ SH_PFC_PIN_GROUP(audio_clk_b),
+ SH_PFC_PIN_GROUP(audio_clk_b_b),
+ SH_PFC_PIN_GROUP(audio_clk_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(can0_data),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can0_data_c),
+ SH_PFC_PIN_GROUP(can0_data_d),
+ SH_PFC_PIN_GROUP(can0_data_e),
+ SH_PFC_PIN_GROUP(can0_data_f),
+ SH_PFC_PIN_GROUP(can1_data),
+ SH_PFC_PIN_GROUP(can1_data_b),
+ SH_PFC_PIN_GROUP(can1_data_c),
+ SH_PFC_PIN_GROUP(can1_data_d),
+ SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(can_clk_b),
+ SH_PFC_PIN_GROUP(can_clk_c),
+ SH_PFC_PIN_GROUP(can_clk_d),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in_b),
+ SH_PFC_PIN_GROUP(du1_clk_in_c),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif0_data_c),
+ SH_PFC_PIN_GROUP(hscif0_clk_c),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_data_c),
+ SH_PFC_PIN_GROUP(hscif1_clk_c),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_c),
+ SH_PFC_PIN_GROUP(hscif1_data_d),
+ SH_PFC_PIN_GROUP(hscif1_data_e),
+ SH_PFC_PIN_GROUP(hscif1_clk_e),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_e),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data_b),
+ SH_PFC_PIN_GROUP(hscif2_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif2_data_c),
+ SH_PFC_PIN_GROUP(hscif2_clk_c),
+ SH_PFC_PIN_GROUP(hscif2_data_d),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c0_b),
+ SH_PFC_PIN_GROUP(i2c0_c),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c1_d),
+ SH_PFC_PIN_GROUP(i2c1_e),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c3_b),
+ SH_PFC_PIN_GROUP(i2c3_c),
+ SH_PFC_PIN_GROUP(i2c3_d),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c4_b),
+ SH_PFC_PIN_GROUP(i2c4_c),
+ SH_PFC_PIN_GROUP(i2c7),
+ SH_PFC_PIN_GROUP(i2c7_b),
+ SH_PFC_PIN_GROUP(i2c7_c),
+ SH_PFC_PIN_GROUP(i2c8),
+ SH_PFC_PIN_GROUP(i2c8_b),
+ SH_PFC_PIN_GROUP(i2c8_c),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_data8_b),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof0_clk_b),
+ SH_PFC_PIN_GROUP(msiof0_sync_b),
+ SH_PFC_PIN_GROUP(msiof0_ss1_b),
+ SH_PFC_PIN_GROUP(msiof0_ss2_b),
+ SH_PFC_PIN_GROUP(msiof0_rx_b),
+ SH_PFC_PIN_GROUP(msiof0_tx_b),
+ SH_PFC_PIN_GROUP(msiof0_clk_c),
+ SH_PFC_PIN_GROUP(msiof0_sync_c),
+ SH_PFC_PIN_GROUP(msiof0_ss1_c),
+ SH_PFC_PIN_GROUP(msiof0_ss2_c),
+ SH_PFC_PIN_GROUP(msiof0_rx_c),
+ SH_PFC_PIN_GROUP(msiof0_tx_c),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_sync_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_rx_b),
+ SH_PFC_PIN_GROUP(msiof1_tx_b),
+ SH_PFC_PIN_GROUP(msiof1_clk_c),
+ SH_PFC_PIN_GROUP(msiof1_sync_c),
+ SH_PFC_PIN_GROUP(msiof1_rx_c),
+ SH_PFC_PIN_GROUP(msiof1_tx_c),
+ SH_PFC_PIN_GROUP(msiof1_clk_d),
+ SH_PFC_PIN_GROUP(msiof1_sync_d),
+ SH_PFC_PIN_GROUP(msiof1_ss1_d),
+ SH_PFC_PIN_GROUP(msiof1_rx_d),
+ SH_PFC_PIN_GROUP(msiof1_tx_d),
+ SH_PFC_PIN_GROUP(msiof1_clk_e),
+ SH_PFC_PIN_GROUP(msiof1_sync_e),
+ SH_PFC_PIN_GROUP(msiof1_rx_e),
+ SH_PFC_PIN_GROUP(msiof1_tx_e),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(msiof2_clk_b),
+ SH_PFC_PIN_GROUP(msiof2_sync_b),
+ SH_PFC_PIN_GROUP(msiof2_ss1_b),
+ SH_PFC_PIN_GROUP(msiof2_ss2_b),
+ SH_PFC_PIN_GROUP(msiof2_rx_b),
+ SH_PFC_PIN_GROUP(msiof2_tx_b),
+ SH_PFC_PIN_GROUP(msiof2_clk_c),
+ SH_PFC_PIN_GROUP(msiof2_sync_c),
+ SH_PFC_PIN_GROUP(msiof2_rx_c),
+ SH_PFC_PIN_GROUP(msiof2_tx_c),
+ SH_PFC_PIN_GROUP(msiof2_clk_d),
+ SH_PFC_PIN_GROUP(msiof2_sync_d),
+ SH_PFC_PIN_GROUP(msiof2_ss1_d),
+ SH_PFC_PIN_GROUP(msiof2_ss2_d),
+ SH_PFC_PIN_GROUP(msiof2_rx_d),
+ SH_PFC_PIN_GROUP(msiof2_tx_d),
+ SH_PFC_PIN_GROUP(msiof2_clk_e),
+ SH_PFC_PIN_GROUP(msiof2_sync_e),
+ SH_PFC_PIN_GROUP(msiof2_rx_e),
+ SH_PFC_PIN_GROUP(msiof2_tx_e),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(pwm5),
+ SH_PFC_PIN_GROUP(pwm5_b),
+ SH_PFC_PIN_GROUP(pwm6),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(qspi_ctrl_b),
+ SH_PFC_PIN_GROUP(qspi_data2_b),
+ SH_PFC_PIN_GROUP(qspi_data4_b),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif0_data_e),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_data_d),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_data_e),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif3_data_c),
+ SH_PFC_PIN_GROUP(scif3_data_d),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa3_data),
+ SH_PFC_PIN_GROUP(scifa3_clk),
+ SH_PFC_PIN_GROUP(scifa3_data_b),
+ SH_PFC_PIN_GROUP(scifa3_clk_b),
+ SH_PFC_PIN_GROUP(scifa3_data_c),
+ SH_PFC_PIN_GROUP(scifa3_clk_c),
+ SH_PFC_PIN_GROUP(scifa4_data),
+ SH_PFC_PIN_GROUP(scifa4_data_b),
+ SH_PFC_PIN_GROUP(scifa4_data_c),
+ SH_PFC_PIN_GROUP(scifa5_data),
+ SH_PFC_PIN_GROUP(scifa5_data_b),
+ SH_PFC_PIN_GROUP(scifa5_data_c),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb0_data_b),
+ SH_PFC_PIN_GROUP(scifb0_clk_b),
+ SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb0_data_c),
+ SH_PFC_PIN_GROUP(scifb0_clk_c),
+ SH_PFC_PIN_GROUP(scifb0_data_d),
+ SH_PFC_PIN_GROUP(scifb0_clk_d),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb1_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data_b),
+ SH_PFC_PIN_GROUP(scifb1_clk_b),
+ SH_PFC_PIN_GROUP(scifb1_data_c),
+ SH_PFC_PIN_GROUP(scifb1_clk_c),
+ SH_PFC_PIN_GROUP(scifb1_data_d),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scifb2_data_b),
+ SH_PFC_PIN_GROUP(scifb2_clk_b),
+ SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb2_data_c),
+ SH_PFC_PIN_GROUP(scifb2_clk_c),
+ SH_PFC_PIN_GROUP(scifb2_data_d),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0_data_b),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_data_b),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi7_data_b),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_data_b),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_data_b),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ SH_PFC_PIN_GROUP(vin1_data8),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 24),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 20),
+ SH_PFC_PIN_GROUP(vin1_b_data18),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 16),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_b_data, 8),
+ SH_PFC_PIN_GROUP(vin1_b_sync),
+ SH_PFC_PIN_GROUP(vin1_b_field),
+ SH_PFC_PIN_GROUP(vin1_b_clkenb),
+ SH_PFC_PIN_GROUP(vin1_b_clk),
+ SH_PFC_PIN_GROUP(vin2_data8),
+ SH_PFC_PIN_GROUP(vin2_sync),
+ SH_PFC_PIN_GROUP(vin2_field),
+ SH_PFC_PIN_GROUP(vin2_clkenb),
+ SH_PFC_PIN_GROUP(vin2_clk),
+ },
+ .r8a779x = {
+ SH_PFC_PIN_GROUP(adi_common),
+ SH_PFC_PIN_GROUP(adi_chsel0),
+ SH_PFC_PIN_GROUP(adi_chsel1),
+ SH_PFC_PIN_GROUP(adi_chsel2),
+ SH_PFC_PIN_GROUP(adi_common_b),
+ SH_PFC_PIN_GROUP(adi_chsel0_b),
+ SH_PFC_PIN_GROUP(adi_chsel1_b),
+ SH_PFC_PIN_GROUP(adi_chsel2_b),
+ SH_PFC_PIN_GROUP(mlb_3pin),
+ }
+};
+
+static const char * const adi_groups[] = {
+ "adi_common",
+ "adi_chsel0",
+ "adi_chsel1",
+ "adi_chsel2",
+ "adi_common_b",
+ "adi_chsel0_b",
+ "adi_chsel1_b",
+ "adi_chsel2_b",
+};
+
+static const char * const audio_clk_groups[] = {
+ "audio_clk_a",
+ "audio_clk_b",
+ "audio_clk_b_b",
+ "audio_clk_c",
+ "audio_clkout",
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_mii",
+ "avb_gmii",
+};
+
+static const char * const can0_groups[] = {
+ "can0_data",
+ "can0_data_b",
+ "can0_data_c",
+ "can0_data_d",
+ "can0_data_e",
+ "can0_data_f",
+ "can_clk",
+ "can_clk_b",
+ "can_clk_c",
+ "can_clk_d",
+};
+
+static const char * const can1_groups[] = {
+ "can1_data",
+ "can1_data_b",
+ "can1_data_c",
+ "can1_data_d",
+ "can_clk",
+ "can_clk_b",
+ "can_clk_c",
+ "can_clk_d",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_out_0",
+ "du_clk_out_1",
+ "du_sync",
+ "du_oddf",
+ "du_cde",
+ "du_disp",
+};
+
+static const char * const du0_groups[] = {
+ "du0_clk_in",
+};
+
+static const char * const du1_groups[] = {
+ "du1_clk_in",
+ "du1_clk_in_b",
+ "du1_clk_in_c",
+};
+
+static const char * const eth_groups[] = {
+ "eth_link",
+ "eth_magic",
+ "eth_mdio",
+ "eth_rmii",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+ "hscif0_data_b",
+ "hscif0_ctrl_b",
+ "hscif0_data_c",
+ "hscif0_clk_c",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+ "hscif1_data_b",
+ "hscif1_data_c",
+ "hscif1_clk_c",
+ "hscif1_ctrl_c",
+ "hscif1_data_d",
+ "hscif1_data_e",
+ "hscif1_clk_e",
+ "hscif1_ctrl_e",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+ "hscif2_data_b",
+ "hscif2_ctrl_b",
+ "hscif2_data_c",
+ "hscif2_clk_c",
+ "hscif2_data_d",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+ "i2c0_b",
+ "i2c0_c",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+ "i2c1_b",
+ "i2c1_c",
+ "i2c1_d",
+ "i2c1_e",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+ "i2c2_b",
+ "i2c2_c",
+ "i2c2_d",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+ "i2c3_b",
+ "i2c3_c",
+ "i2c3_d",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+ "i2c4_b",
+ "i2c4_c",
+};
+
+static const char * const i2c7_groups[] = {
+ "i2c7",
+ "i2c7_b",
+ "i2c7_c",
+};
+
+static const char * const i2c8_groups[] = {
+ "i2c8",
+ "i2c8_b",
+ "i2c8_c",
+};
+
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq1",
+ "intc_irq2",
+ "intc_irq3",
+};
+
+static const char * const mlb_groups[] = {
+ "mlb_3pin",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_data8_b",
+ "mmc_ctrl",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_rx",
+ "msiof0_tx",
+ "msiof0_clk_b",
+ "msiof0_sync_b",
+ "msiof0_ss1_b",
+ "msiof0_ss2_b",
+ "msiof0_rx_b",
+ "msiof0_tx_b",
+ "msiof0_clk_c",
+ "msiof0_sync_c",
+ "msiof0_ss1_c",
+ "msiof0_ss2_c",
+ "msiof0_rx_c",
+ "msiof0_tx_c",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_rx",
+ "msiof1_tx",
+ "msiof1_clk_b",
+ "msiof1_sync_b",
+ "msiof1_ss1_b",
+ "msiof1_ss2_b",
+ "msiof1_rx_b",
+ "msiof1_tx_b",
+ "msiof1_clk_c",
+ "msiof1_sync_c",
+ "msiof1_rx_c",
+ "msiof1_tx_c",
+ "msiof1_clk_d",
+ "msiof1_sync_d",
+ "msiof1_ss1_d",
+ "msiof1_rx_d",
+ "msiof1_tx_d",
+ "msiof1_clk_e",
+ "msiof1_sync_e",
+ "msiof1_rx_e",
+ "msiof1_tx_e",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_rx",
+ "msiof2_tx",
+ "msiof2_clk_b",
+ "msiof2_sync_b",
+ "msiof2_ss1_b",
+ "msiof2_ss2_b",
+ "msiof2_rx_b",
+ "msiof2_tx_b",
+ "msiof2_clk_c",
+ "msiof2_sync_c",
+ "msiof2_rx_c",
+ "msiof2_tx_c",
+ "msiof2_clk_d",
+ "msiof2_sync_d",
+ "msiof2_ss1_d",
+ "msiof2_ss2_d",
+ "msiof2_rx_d",
+ "msiof2_tx_d",
+ "msiof2_clk_e",
+ "msiof2_sync_e",
+ "msiof2_rx_e",
+ "msiof2_tx_e",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0",
+ "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2",
+ "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4",
+ "pwm4_b",
+};
+
+static const char * const pwm5_groups[] = {
+ "pwm5",
+ "pwm5_b",
+};
+
+static const char * const pwm6_groups[] = {
+ "pwm6",
+};
+
+static const char * const qspi_groups[] = {
+ "qspi_ctrl",
+ "qspi_data2",
+ "qspi_data4",
+ "qspi_ctrl_b",
+ "qspi_data2_b",
+ "qspi_data4_b",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_data_b",
+ "scif0_data_c",
+ "scif0_data_d",
+ "scif0_data_e",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_data_c",
+ "scif1_data_d",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_data_b",
+ "scif2_clk_b",
+ "scif2_data_c",
+ "scif2_data_e",
+};
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_data_b",
+ "scif3_clk_b",
+ "scif3_data_c",
+ "scif3_data_d",
+};
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_data_b",
+ "scif4_data_c",
+};
+static const char * const scif5_groups[] = {
+ "scif5_data",
+ "scif5_data_b",
+};
+static const char * const scifa0_groups[] = {
+ "scifa0_data",
+ "scifa0_data_b",
+};
+static const char * const scifa1_groups[] = {
+ "scifa1_data",
+ "scifa1_clk",
+ "scifa1_data_b",
+ "scifa1_clk_b",
+ "scifa1_data_c",
+};
+static const char * const scifa2_groups[] = {
+ "scifa2_data",
+ "scifa2_clk",
+ "scifa2_data_b",
+};
+static const char * const scifa3_groups[] = {
+ "scifa3_data",
+ "scifa3_clk",
+ "scifa3_data_b",
+ "scifa3_clk_b",
+ "scifa3_data_c",
+ "scifa3_clk_c",
+};
+static const char * const scifa4_groups[] = {
+ "scifa4_data",
+ "scifa4_data_b",
+ "scifa4_data_c",
+};
+static const char * const scifa5_groups[] = {
+ "scifa5_data",
+ "scifa5_data_b",
+ "scifa5_data_c",
+};
+static const char * const scifb0_groups[] = {
+ "scifb0_data",
+ "scifb0_clk",
+ "scifb0_ctrl",
+ "scifb0_data_b",
+ "scifb0_clk_b",
+ "scifb0_ctrl_b",
+ "scifb0_data_c",
+ "scifb0_clk_c",
+ "scifb0_data_d",
+ "scifb0_clk_d",
+};
+static const char * const scifb1_groups[] = {
+ "scifb1_data",
+ "scifb1_clk",
+ "scifb1_ctrl",
+ "scifb1_data_b",
+ "scifb1_clk_b",
+ "scifb1_data_c",
+ "scifb1_clk_c",
+ "scifb1_data_d",
+};
+static const char * const scifb2_groups[] = {
+ "scifb2_data",
+ "scifb2_clk",
+ "scifb2_ctrl",
+ "scifb2_data_b",
+ "scifb2_clk_b",
+ "scifb2_ctrl_b",
+ "scifb0_data_c",
+ "scifb2_clk_c",
+ "scifb2_data_d",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+ "scif_clk_b",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd",
+ "sdhi2_wp",
+};
+
+static const char * const ssi_groups[] = {
+ "ssi0_data",
+ "ssi0_data_b",
+ "ssi0129_ctrl",
+ "ssi0129_ctrl_b",
+ "ssi1_data",
+ "ssi1_data_b",
+ "ssi1_ctrl",
+ "ssi1_ctrl_b",
+ "ssi2_data",
+ "ssi2_ctrl",
+ "ssi3_data",
+ "ssi34_ctrl",
+ "ssi4_data",
+ "ssi4_ctrl",
+ "ssi5_data",
+ "ssi5_ctrl",
+ "ssi6_data",
+ "ssi6_ctrl",
+ "ssi7_data",
+ "ssi7_data_b",
+ "ssi78_ctrl",
+ "ssi78_ctrl_b",
+ "ssi8_data",
+ "ssi8_data_b",
+ "ssi9_data",
+ "ssi9_data_b",
+ "ssi9_ctrl",
+ "ssi9_ctrl_b",
+};
+
+static const char * const usb0_groups[] = {
+ "usb0",
+};
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data24",
+ "vin0_data20",
+ "vin0_data18",
+ "vin0_data16",
+ "vin0_data12",
+ "vin0_data10",
+ "vin0_data8",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data8",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+ "vin1_b_data24",
+ "vin1_b_data20",
+ "vin1_b_data18",
+ "vin1_b_data16",
+ "vin1_b_data12",
+ "vin1_b_data10",
+ "vin1_b_data8",
+ "vin1_b_sync",
+ "vin1_b_field",
+ "vin1_b_clkenb",
+ "vin1_b_clk",
+};
+
+static const char * const vin2_groups[] = {
+ "vin2_data8",
+ "vin2_sync",
+ "vin2_field",
+ "vin2_clkenb",
+ "vin2_clk",
+};
+
+static const struct {
+ struct sh_pfc_function common[56];
+ struct sh_pfc_function r8a779x[2];
+} pinmux_functions = {
+ .common = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c7),
+ SH_PFC_FUNCTION(i2c8),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifa3),
+ SH_PFC_FUNCTION(scifa4),
+ SH_PFC_FUNCTION(scifa5),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+ SH_PFC_FUNCTION(vin2),
+ },
+ .r8a779x = {
+ SH_PFC_FUNCTION(adi),
+ SH_PFC_FUNCTION(mlb),
+ }
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ GP_0_31_FN, FN_IP1_22_20,
+ GP_0_30_FN, FN_IP1_19_17,
+ GP_0_29_FN, FN_IP1_16_14,
+ GP_0_28_FN, FN_IP1_13_11,
+ GP_0_27_FN, FN_IP1_10_8,
+ GP_0_26_FN, FN_IP1_7_6,
+ GP_0_25_FN, FN_IP1_5_4,
+ GP_0_24_FN, FN_IP1_3_2,
+ GP_0_23_FN, FN_IP1_1_0,
+ GP_0_22_FN, FN_IP0_30_29,
+ GP_0_21_FN, FN_IP0_28_27,
+ GP_0_20_FN, FN_IP0_26_25,
+ GP_0_19_FN, FN_IP0_24_23,
+ GP_0_18_FN, FN_IP0_22_21,
+ GP_0_17_FN, FN_IP0_20_19,
+ GP_0_16_FN, FN_IP0_18_16,
+ GP_0_15_FN, FN_IP0_15,
+ GP_0_14_FN, FN_IP0_14,
+ GP_0_13_FN, FN_IP0_13,
+ GP_0_12_FN, FN_IP0_12,
+ GP_0_11_FN, FN_IP0_11,
+ GP_0_10_FN, FN_IP0_10,
+ GP_0_9_FN, FN_IP0_9,
+ GP_0_8_FN, FN_IP0_8,
+ GP_0_7_FN, FN_IP0_7,
+ GP_0_6_FN, FN_IP0_6,
+ GP_0_5_FN, FN_IP0_5,
+ GP_0_4_FN, FN_IP0_4,
+ GP_0_3_FN, FN_IP0_3,
+ GP_0_2_FN, FN_IP0_2,
+ GP_0_1_FN, FN_IP0_1,
+ GP_0_0_FN, FN_IP0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_25_FN, FN_IP3_21_20,
+ GP_1_24_FN, FN_IP3_19_18,
+ GP_1_23_FN, FN_IP3_17_16,
+ GP_1_22_FN, FN_IP3_15_14,
+ GP_1_21_FN, FN_IP3_13_12,
+ GP_1_20_FN, FN_IP3_11_9,
+ GP_1_19_FN, FN_RD_N,
+ GP_1_18_FN, FN_IP3_8_6,
+ GP_1_17_FN, FN_IP3_5_3,
+ GP_1_16_FN, FN_IP3_2_0,
+ GP_1_15_FN, FN_IP2_29_27,
+ GP_1_14_FN, FN_IP2_26_25,
+ GP_1_13_FN, FN_IP2_24_23,
+ GP_1_12_FN, FN_EX_CS0_N,
+ GP_1_11_FN, FN_IP2_22_21,
+ GP_1_10_FN, FN_IP2_20_19,
+ GP_1_9_FN, FN_IP2_18_16,
+ GP_1_8_FN, FN_IP2_15_13,
+ GP_1_7_FN, FN_IP2_12_10,
+ GP_1_6_FN, FN_IP2_9_7,
+ GP_1_5_FN, FN_IP2_6_5,
+ GP_1_4_FN, FN_IP2_4_3,
+ GP_1_3_FN, FN_IP2_2_0,
+ GP_1_2_FN, FN_IP1_31_29,
+ GP_1_1_FN, FN_IP1_28_26,
+ GP_1_0_FN, FN_IP1_25_23, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ GP_2_31_FN, FN_IP6_7_6,
+ GP_2_30_FN, FN_IP6_5_3,
+ GP_2_29_FN, FN_IP6_2_0,
+ GP_2_28_FN, FN_AUDIO_CLKA,
+ GP_2_27_FN, FN_IP5_31_29,
+ GP_2_26_FN, FN_IP5_28_26,
+ GP_2_25_FN, FN_IP5_25_24,
+ GP_2_24_FN, FN_IP5_23_22,
+ GP_2_23_FN, FN_IP5_21_20,
+ GP_2_22_FN, FN_IP5_19_17,
+ GP_2_21_FN, FN_IP5_16_15,
+ GP_2_20_FN, FN_IP5_14_12,
+ GP_2_19_FN, FN_IP5_11_9,
+ GP_2_18_FN, FN_IP5_8_6,
+ GP_2_17_FN, FN_IP5_5_3,
+ GP_2_16_FN, FN_IP5_2_0,
+ GP_2_15_FN, FN_IP4_30_28,
+ GP_2_14_FN, FN_IP4_27_26,
+ GP_2_13_FN, FN_IP4_25_24,
+ GP_2_12_FN, FN_IP4_23_22,
+ GP_2_11_FN, FN_IP4_21,
+ GP_2_10_FN, FN_IP4_20,
+ GP_2_9_FN, FN_IP4_19,
+ GP_2_8_FN, FN_IP4_18_16,
+ GP_2_7_FN, FN_IP4_15_13,
+ GP_2_6_FN, FN_IP4_12_10,
+ GP_2_5_FN, FN_IP4_9_8,
+ GP_2_4_FN, FN_IP4_7_5,
+ GP_2_3_FN, FN_IP4_4_2,
+ GP_2_2_FN, FN_IP4_1_0,
+ GP_2_1_FN, FN_IP3_30_28,
+ GP_2_0_FN, FN_IP3_27_25 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ GP_3_31_FN, FN_IP9_18_17,
+ GP_3_30_FN, FN_IP9_16,
+ GP_3_29_FN, FN_IP9_15_13,
+ GP_3_28_FN, FN_IP9_12,
+ GP_3_27_FN, FN_IP9_11,
+ GP_3_26_FN, FN_IP9_10_8,
+ GP_3_25_FN, FN_IP9_7,
+ GP_3_24_FN, FN_IP9_6,
+ GP_3_23_FN, FN_IP9_5_3,
+ GP_3_22_FN, FN_IP9_2_0,
+ GP_3_21_FN, FN_IP8_30_28,
+ GP_3_20_FN, FN_IP8_27_26,
+ GP_3_19_FN, FN_IP8_25_24,
+ GP_3_18_FN, FN_IP8_23_21,
+ GP_3_17_FN, FN_IP8_20_18,
+ GP_3_16_FN, FN_IP8_17_15,
+ GP_3_15_FN, FN_IP8_14_12,
+ GP_3_14_FN, FN_IP8_11_9,
+ GP_3_13_FN, FN_IP8_8_6,
+ GP_3_12_FN, FN_IP8_5_3,
+ GP_3_11_FN, FN_IP8_2_0,
+ GP_3_10_FN, FN_IP7_29_27,
+ GP_3_9_FN, FN_IP7_26_24,
+ GP_3_8_FN, FN_IP7_23_21,
+ GP_3_7_FN, FN_IP7_20_19,
+ GP_3_6_FN, FN_IP7_18_17,
+ GP_3_5_FN, FN_IP7_16_15,
+ GP_3_4_FN, FN_IP7_14_13,
+ GP_3_3_FN, FN_IP7_12_11,
+ GP_3_2_FN, FN_IP7_10_9,
+ GP_3_1_FN, FN_IP7_8_6,
+ GP_3_0_FN, FN_IP7_5_3 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ GP_4_31_FN, FN_IP15_5_4,
+ GP_4_30_FN, FN_IP15_3_2,
+ GP_4_29_FN, FN_IP15_1_0,
+ GP_4_28_FN, FN_IP11_8_6,
+ GP_4_27_FN, FN_IP11_5_3,
+ GP_4_26_FN, FN_IP11_2_0,
+ GP_4_25_FN, FN_IP10_31_29,
+ GP_4_24_FN, FN_IP10_28_27,
+ GP_4_23_FN, FN_IP10_26_25,
+ GP_4_22_FN, FN_IP10_24_22,
+ GP_4_21_FN, FN_IP10_21_19,
+ GP_4_20_FN, FN_IP10_18_17,
+ GP_4_19_FN, FN_IP10_16_15,
+ GP_4_18_FN, FN_IP10_14_12,
+ GP_4_17_FN, FN_IP10_11_9,
+ GP_4_16_FN, FN_IP10_8_6,
+ GP_4_15_FN, FN_IP10_5_3,
+ GP_4_14_FN, FN_IP10_2_0,
+ GP_4_13_FN, FN_IP9_31_29,
+ GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
+ GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
+ GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
+ GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
+ GP_4_8_FN, FN_IP9_28_27,
+ GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
+ GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
+ GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
+ GP_4_4_FN, FN_IP9_26_25,
+ GP_4_3_FN, FN_IP9_24_23,
+ GP_4_2_FN, FN_IP9_22_21,
+ GP_4_1_FN, FN_IP9_20_19,
+ GP_4_0_FN, FN_VI0_CLK }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ GP_5_31_FN, FN_IP3_24_22,
+ GP_5_30_FN, FN_IP13_9_7,
+ GP_5_29_FN, FN_IP13_6_5,
+ GP_5_28_FN, FN_IP13_4_3,
+ GP_5_27_FN, FN_IP13_2_0,
+ GP_5_26_FN, FN_IP12_29_27,
+ GP_5_25_FN, FN_IP12_26_24,
+ GP_5_24_FN, FN_IP12_23_22,
+ GP_5_23_FN, FN_IP12_21_20,
+ GP_5_22_FN, FN_IP12_19_18,
+ GP_5_21_FN, FN_IP12_17_16,
+ GP_5_20_FN, FN_IP12_15_13,
+ GP_5_19_FN, FN_IP12_12_10,
+ GP_5_18_FN, FN_IP12_9_7,
+ GP_5_17_FN, FN_IP12_6_4,
+ GP_5_16_FN, FN_IP12_3_2,
+ GP_5_15_FN, FN_IP12_1_0,
+ GP_5_14_FN, FN_IP11_31_30,
+ GP_5_13_FN, FN_IP11_29_28,
+ GP_5_12_FN, FN_IP11_27,
+ GP_5_11_FN, FN_IP11_26,
+ GP_5_10_FN, FN_IP11_25,
+ GP_5_9_FN, FN_IP11_24,
+ GP_5_8_FN, FN_IP11_23,
+ GP_5_7_FN, FN_IP11_22,
+ GP_5_6_FN, FN_IP11_21,
+ GP_5_5_FN, FN_IP11_20,
+ GP_5_4_FN, FN_IP11_19,
+ GP_5_3_FN, FN_IP11_18_17,
+ GP_5_2_FN, FN_IP11_16_15,
+ GP_5_1_FN, FN_IP11_14_12,
+ GP_5_0_FN, FN_IP11_11_9 }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ GP_6_31_FN, FN_DU0_DOTCLKIN,
+ GP_6_30_FN, FN_USB1_OVC,
+ GP_6_29_FN, FN_IP14_31_29,
+ GP_6_28_FN, FN_IP14_28_26,
+ GP_6_27_FN, FN_IP14_25_23,
+ GP_6_26_FN, FN_IP14_22_20,
+ GP_6_25_FN, FN_IP14_19_17,
+ GP_6_24_FN, FN_IP14_16_14,
+ GP_6_23_FN, FN_IP14_13_11,
+ GP_6_22_FN, FN_IP14_10_8,
+ GP_6_21_FN, FN_IP14_7,
+ GP_6_20_FN, FN_IP14_6,
+ GP_6_19_FN, FN_IP14_5,
+ GP_6_18_FN, FN_IP14_4,
+ GP_6_17_FN, FN_IP14_3,
+ GP_6_16_FN, FN_IP14_2,
+ GP_6_15_FN, FN_IP14_1_0,
+ GP_6_14_FN, FN_IP13_30_28,
+ GP_6_13_FN, FN_IP13_27,
+ GP_6_12_FN, FN_IP13_26,
+ GP_6_11_FN, FN_IP13_25,
+ GP_6_10_FN, FN_IP13_24_23,
+ GP_6_9_FN, FN_IP13_22,
+ GP_6_8_FN, FN_SD1_CLK,
+ GP_6_7_FN, FN_IP13_21_19,
+ GP_6_6_FN, FN_IP13_18_16,
+ GP_6_5_FN, FN_IP13_15,
+ GP_6_4_FN, FN_IP13_14,
+ GP_6_3_FN, FN_IP13_13,
+ GP_6_2_FN, FN_IP13_12,
+ GP_6_1_FN, FN_IP13_11,
+ GP_6_0_FN, FN_IP13_10 }
+ },
+ { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_7_25_FN, FN_USB1_PWEN,
+ GP_7_24_FN, FN_USB0_OVC,
+ GP_7_23_FN, FN_USB0_PWEN,
+ GP_7_22_FN, FN_IP15_14_12,
+ GP_7_21_FN, FN_IP15_11_9,
+ GP_7_20_FN, FN_IP15_8_6,
+ GP_7_19_FN, FN_IP7_2_0,
+ GP_7_18_FN, FN_IP6_29_27,
+ GP_7_17_FN, FN_IP6_26_24,
+ GP_7_16_FN, FN_IP6_23_21,
+ GP_7_15_FN, FN_IP6_20_19,
+ GP_7_14_FN, FN_IP6_18_16,
+ GP_7_13_FN, FN_IP6_15_14,
+ GP_7_12_FN, FN_IP6_13_12,
+ GP_7_11_FN, FN_IP6_11_10,
+ GP_7_10_FN, FN_IP6_9_8,
+ GP_7_9_FN, FN_IP16_11_10,
+ GP_7_8_FN, FN_IP16_9_8,
+ GP_7_7_FN, FN_IP16_7_6,
+ GP_7_6_FN, FN_IP16_5_3,
+ GP_7_5_FN, FN_IP16_2_0,
+ GP_7_4_FN, FN_IP15_29_27,
+ GP_7_3_FN, FN_IP15_26_24,
+ GP_7_2_FN, FN_IP15_23_21,
+ GP_7_1_FN, FN_IP15_20_18,
+ GP_7_0_FN, FN_IP15_17_15 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+ 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP0_31 [1] */
+ 0, 0,
+ /* IP0_30_29 [2] */
+ FN_A6, FN_MSIOF1_SCK,
+ 0, 0,
+ /* IP0_28_27 [2] */
+ FN_A5, FN_MSIOF0_RXD_B,
+ 0, 0,
+ /* IP0_26_25 [2] */
+ FN_A4, FN_MSIOF0_TXD_B,
+ 0, 0,
+ /* IP0_24_23 [2] */
+ FN_A3, FN_MSIOF0_SS2_B,
+ 0, 0,
+ /* IP0_22_21 [2] */
+ FN_A2, FN_MSIOF0_SS1_B,
+ 0, 0,
+ /* IP0_20_19 [2] */
+ FN_A1, FN_MSIOF0_SYNC_B,
+ 0, 0,
+ /* IP0_18_16 [3] */
+ FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
+ 0, 0, 0,
+ /* IP0_15 [1] */
+ FN_D15, 0,
+ /* IP0_14 [1] */
+ FN_D14, 0,
+ /* IP0_13 [1] */
+ FN_D13, 0,
+ /* IP0_12 [1] */
+ FN_D12, 0,
+ /* IP0_11 [1] */
+ FN_D11, 0,
+ /* IP0_10 [1] */
+ FN_D10, 0,
+ /* IP0_9 [1] */
+ FN_D9, 0,
+ /* IP0_8 [1] */
+ FN_D8, 0,
+ /* IP0_7 [1] */
+ FN_D7, 0,
+ /* IP0_6 [1] */
+ FN_D6, 0,
+ /* IP0_5 [1] */
+ FN_D5, 0,
+ /* IP0_4 [1] */
+ FN_D4, 0,
+ /* IP0_3 [1] */
+ FN_D3, 0,
+ /* IP0_2 [1] */
+ FN_D2, 0,
+ /* IP0_1 [1] */
+ FN_D1, 0,
+ /* IP0_0 [1] */
+ FN_D0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+ 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ /* IP1_31_29 [3] */
+ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
+ 0, 0, 0,
+ /* IP1_28_26 [3] */
+ FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
+ 0, 0, 0, 0,
+ /* IP1_25_23 [3] */
+ FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
+ 0, 0, 0,
+ /* IP1_22_20 [3] */
+ FN_A15, FN_BPFCLK_C,
+ 0, 0, 0, 0, 0, 0,
+ /* IP1_19_17 [3] */
+ FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
+ 0, 0, 0,
+ /* IP1_16_14 [3] */
+ FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
+ 0, 0, 0, 0,
+ /* IP1_13_11 [3] */
+ FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
+ 0, 0, 0, 0,
+ /* IP1_10_8 [3] */
+ FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
+ 0, 0, 0, 0,
+ /* IP1_7_6 [2] */
+ FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
+ /* IP1_5_4 [2] */
+ FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
+ /* IP1_3_2 [2] */
+ FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
+ /* IP1_1_0 [2] */
+ FN_A7, FN_MSIOF1_SYNC,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+ 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
+ /* IP2_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP2_29_27 [3] */
+ FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
+ FN_ATAG0_N, 0, FN_EX_WAIT1,
+ 0, 0,
+ /* IP2_26_25 [2] */
+ FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
+ /* IP2_24_23 [2] */
+ FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
+ /* IP2_22_21 [2] */
+ FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
+ /* IP2_20_19 [2] */
+ FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
+ /* IP2_18_16 [3] */
+ FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
+ 0, 0,
+ /* IP2_15_13 [3] */
+ FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
+ 0, 0, 0,
+ /* IP2_12_10 [3] */
+ FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
+ 0, 0, 0,
+ /* IP2_9_7 [3] */
+ FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
+ 0, 0, 0,
+ /* IP2_6_5 [2] */
+ FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
+ /* IP2_4_3 [2] */
+ FN_A20, FN_SPCLK, 0, 0,
+ /* IP2_2_0 [3] */
+ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
+ FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+ 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
+ /* IP3_31 [1] */
+ 0, 0,
+ /* IP3_30_28 [3] */
+ FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
+ FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
+ 0, 0, 0,
+ /* IP3_27_25 [3] */
+ FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
+ FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
+ 0, 0, 0,
+ /* IP3_24_22 [3] */
+ FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
+ FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
+ /* IP3_21_20 [2] */
+ FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
+ /* IP3_19_18 [2] */
+ FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
+ /* IP3_17_16 [2] */
+ FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
+ /* IP3_15_14 [2] */
+ FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
+ /* IP3_13_12 [2] */
+ FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
+ /* IP3_11_9 [3] */
+ FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
+ 0, 0, 0,
+ /* IP3_8_6 [3] */
+ FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
+ FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
+ /* IP3_5_3 [3] */
+ FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
+ FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
+ /* IP3_2_0 [3] */
+ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+ 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
+ /* IP4_31 [1] */
+ 0, 0,
+ /* IP4_30_28 [3] */
+ FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
+ FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
+ 0, 0,
+ /* IP4_27_26 [2] */
+ FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
+ /* IP4_25_24 [2] */
+ FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
+ /* IP4_23_22 [2] */
+ FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
+ /* IP4_21 [1] */
+ FN_SSI_SDATA3, 0,
+ /* IP4_20 [1] */
+ FN_SSI_WS34, 0,
+ /* IP4_19 [1] */
+ FN_SSI_SCK34, 0,
+ /* IP4_18_16 [3] */
+ FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
+ 0, 0, 0, 0,
+ /* IP4_15_13 [3] */
+ FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
+ FN_GLO_Q1_D, FN_HCTS1_N_E,
+ 0, 0,
+ /* IP4_12_10 [3] */
+ FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
+ 0, 0, 0,
+ /* IP4_9_8 [2] */
+ FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
+ /* IP4_7_5 [3] */
+ FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
+ FN_GLO_I1_D, 0, 0, 0,
+ /* IP4_4_2 [3] */
+ FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
+ FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
+ 0, 0, 0,
+ /* IP4_1_0 [2] */
+ FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+ 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
+ /* IP5_31_29 [3] */
+ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
+ 0, 0, 0, 0, 0,
+ /* IP5_28_26 [3] */
+ FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
+ 0, 0, 0, 0,
+ /* IP5_25_24 [2] */
+ FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
+ /* IP5_23_22 [2] */
+ FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
+ /* IP5_21_20 [2] */
+ FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
+ /* IP5_19_17 [3] */
+ FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
+ 0, 0, 0, 0,
+ /* IP5_16_15 [2] */
+ FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
+ /* IP5_14_12 [3] */
+ FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
+ 0, 0, 0, 0,
+ /* IP5_11_9 [3] */
+ FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
+ 0, 0, 0, 0,
+ /* IP5_8_6 [3] */
+ FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
+ FN_MSIOF2_RXD_D, FN_VI1_R5_B,
+ 0, 0,
+ /* IP5_5_3 [3] */
+ FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
+ FN_MSIOF2_SS1_D, FN_VI1_R4_B,
+ 0, 0,
+ /* IP5_2_0 [3] */
+ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
+ FN_MSIOF2_TXD_D, FN_VI1_R3_B,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+ 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
+ /* IP6_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP6_29_27 [3] */
+ FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
+ FN_GPS_SIGN_C, FN_GPS_SIGN_D,
+ 0, 0, 0,
+ /* IP6_26_24 [3] */
+ FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
+ FN_GPS_CLK_C, FN_GPS_CLK_D,
+ 0, 0, 0,
+ /* IP6_23_21 [3] */
+ FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
+ FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
+ 0, 0, 0,
+ /* IP6_20_19 [2] */
+ FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
+ /* IP6_18_16 [3] */
+ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
+ FN_INTC_IRQ4_N, 0, 0, 0,
+ /* IP6_15_14 [2] */
+ FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+ /* IP6_13_12 [2] */
+ FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
+ /* IP6_11_10 [2] */
+ FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
+ /* IP6_9_8 [2] */
+ FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
+ /* IP6_7_6 [2] */
+ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
+ /* IP6_5_3 [3] */
+ FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
+ FN_SCIFA2_RXD, FN_FMIN_E,
+ 0, 0,
+ /* IP6_2_0 [3] */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+ 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
+ /* IP7_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP7_29_27 [3] */
+ FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
+ FN_SCIFA1_SCK, FN_SSI_SCK78_B,
+ 0, 0,
+ /* IP7_26_24 [3] */
+ FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
+ FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
+ 0, 0,
+ /* IP7_23_21 [3] */
+ FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
+ FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
+ 0, 0,
+ /* IP7_20_19 [2] */
+ FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
+ /* IP7_18_17 [2] */
+ FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
+ /* IP7_16_15 [2] */
+ FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
+ /* IP7_14_13 [2] */
+ FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
+ /* IP7_12_11 [2] */
+ FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
+ /* IP7_10_9 [2] */
+ FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
+ /* IP7_8_6 [3] */
+ FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
+ FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
+ 0, 0,
+ /* IP7_5_3 [3] */
+ FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
+ FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
+ 0, 0,
+ /* IP7_2_0 [3] */
+ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
+ FN_SCIF_CLK_B, FN_GPS_MAG_D,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP8_31 [1] */
+ 0, 0,
+ /* IP8_30_28 [3] */
+ FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
+ 0, 0, 0,
+ /* IP8_27_26 [2] */
+ FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
+ /* IP8_25_24 [2] */
+ FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
+ /* IP8_23_21 [3] */
+ FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
+ FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
+ 0, 0,
+ /* IP8_20_18 [3] */
+ FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
+ FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
+ 0, 0,
+ /* IP8_17_15 [3] */
+ FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
+ FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
+ 0, 0,
+ /* IP8_14_12 [3] */
+ FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
+ FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
+ 0, 0, 0,
+ /* IP8_11_9 [3] */
+ FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
+ FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
+ 0, 0, 0,
+ /* IP8_8_6 [3] */
+ FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
+ FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
+ 0, 0,
+ /* IP8_5_3 [3] */
+ FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
+ FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
+ 0, 0,
+ /* IP8_2_0 [3] */
+ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+ 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
+ /* IP9_31_29 [3] */
+ FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
+ FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
+ /* IP9_28_27 [2] */
+ FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
+ /* IP9_26_25 [2] */
+ FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
+ /* IP9_24_23 [2] */
+ FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
+ /* IP9_22_21 [2] */
+ FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
+ /* IP9_20_19 [2] */
+ FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
+ /* IP9_18_17 [2] */
+ FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
+ /* IP9_16 [1] */
+ FN_DU1_DISP, FN_QPOLA,
+ /* IP9_15_13 [3] */
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
+ 0, 0, 0,
+ /* IP9_12 [1] */
+ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
+ /* IP9_11 [1] */
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
+ /* IP9_10_8 [3] */
+ FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
+ FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
+ 0, 0,
+ /* IP9_7 [1] */
+ FN_DU1_DOTCLKOUT0, FN_QCLK,
+ /* IP9_6 [1] */
+ FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
+ /* IP9_5_3 [3] */
+ FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
+ FN_SCIF3_SCK, FN_SCIFA3_SCK,
+ 0, 0, 0,
+ /* IP9_2_0 [3] */
+ FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+ 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+ /* IP10_31_29 [3] */
+ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
+ 0, 0, 0,
+ /* IP10_28_27 [2] */
+ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
+ /* IP10_26_25 [2] */
+ FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
+ /* IP10_24_22 [3] */
+ FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
+ 0, 0, 0,
+ /* IP10_21_19 [3] */
+ FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
+ FN_TS_SDATA0_C, FN_ATACS11_N,
+ 0, 0, 0,
+ /* IP10_18_17 [2] */
+ FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
+ /* IP10_16_15 [2] */
+ FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
+ /* IP10_14_12 [3] */
+ FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
+ FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
+ /* IP10_11_9 [3] */
+ FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
+ FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
+ 0, 0,
+ /* IP10_8_6 [3] */
+ FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
+ FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
+ /* IP10_5_3 [3] */
+ FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
+ FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
+ /* IP10_2_0 [3] */
+ FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
+ FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+ 3, 3, 3, 3, 3) {
+ /* IP11_31_30 [2] */
+ FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
+ /* IP11_29_28 [2] */
+ FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
+ /* IP11_27 [1] */
+ FN_VI1_DATA7, FN_AVB_MDC,
+ /* IP11_26 [1] */
+ FN_VI1_DATA6, FN_AVB_MAGIC,
+ /* IP11_25 [1] */
+ FN_VI1_DATA5, FN_AVB_RX_DV,
+ /* IP11_24 [1] */
+ FN_VI1_DATA4, FN_AVB_MDIO,
+ /* IP11_23 [1] */
+ FN_VI1_DATA3, FN_AVB_RX_ER,
+ /* IP11_22 [1] */
+ FN_VI1_DATA2, FN_AVB_RXD7,
+ /* IP11_21 [1] */
+ FN_VI1_DATA1, FN_AVB_RXD6,
+ /* IP11_20 [1] */
+ FN_VI1_DATA0, FN_AVB_RXD5,
+ /* IP11_19 [1] */
+ FN_VI1_CLK, FN_AVB_RXD4,
+ /* IP11_18_17 [2] */
+ FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
+ /* IP11_16_15 [2] */
+ FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
+ /* IP11_14_12 [3] */
+ FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
+ FN_RX4_B, FN_SCIFA4_RXD_B,
+ 0, 0, 0,
+ /* IP11_11_9 [3] */
+ FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
+ FN_TX4_B, FN_SCIFA4_TXD_B,
+ 0, 0, 0,
+ /* IP11_8_6 [3] */
+ FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+ FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
+ /* IP11_5_3 [3] */
+ FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
+ 0, 0, 0,
+ /* IP11_2_0 [3] */
+ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
+ FN_I2C1_SDA_D, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+ 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+ /* IP12_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP12_29_27 [3] */
+ FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+ FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+ 0, 0, 0,
+ /* IP12_26_24 [3] */
+ FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+ FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+ 0, 0, 0,
+ /* IP12_23_22 [2] */
+ FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
+ /* IP12_21_20 [2] */
+ FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
+ /* IP12_19_18 [2] */
+ FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
+ /* IP12_17_16 [2] */
+ FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+ /* IP12_15_13 [3] */
+ FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+ FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+ 0, 0, 0,
+ /* IP12_12_10 [3] */
+ FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+ FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+ 0, 0, 0,
+ /* IP12_9_7 [3] */
+ FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
+ FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
+ 0, 0, 0,
+ /* IP12_6_4 [3] */
+ FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+ FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
+ 0, 0, 0,
+ /* IP12_3_2 [2] */
+ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
+ /* IP12_1_0 [2] */
+ FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+ 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
+ 3, 2, 2, 3) {
+ /* IP13_31 [1] */
+ 0, 0,
+ /* IP13_30_28 [3] */
+ FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
+ 0, 0, 0, 0,
+ /* IP13_27 [1] */
+ FN_SD1_DATA3, FN_IERX_B,
+ /* IP13_26 [1] */
+ FN_SD1_DATA2, FN_IECLK_B,
+ /* IP13_25 [1] */
+ FN_SD1_DATA1, FN_IETX_B,
+ /* IP13_24_23 [2] */
+ FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
+ /* IP13_22 [1] */
+ FN_SD1_CMD, FN_REMOCON_B,
+ /* IP13_21_19 [3] */
+ FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
+ FN_SCIFA5_RXD_B, FN_RX3_C,
+ 0, 0,
+ /* IP13_18_16 [3] */
+ FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
+ FN_SCIFA5_TXD_B, FN_TX3_C,
+ 0, 0,
+ /* IP13_15 [1] */
+ FN_SD0_DATA3, FN_SSL_B,
+ /* IP13_14 [1] */
+ FN_SD0_DATA2, FN_IO3_B,
+ /* IP13_13 [1] */
+ FN_SD0_DATA1, FN_IO2_B,
+ /* IP13_12 [1] */
+ FN_SD0_DATA0, FN_MISO_IO1_B,
+ /* IP13_11 [1] */
+ FN_SD0_CMD, FN_MOSI_IO0_B,
+ /* IP13_10 [1] */
+ FN_SD0_CLK, FN_SPCLK_B,
+ /* IP13_9_7 [3] */
+ FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
+ FN_ADICHS2_B, FN_MSIOF0_TXD_C,
+ 0, 0, 0,
+ /* IP13_6_5 [2] */
+ FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
+ /* IP13_4_3 [2] */
+ FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
+ /* IP13_2_0 [3] */
+ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
+ FN_ADICLK_B, FN_MSIOF0_SS1_C,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+ 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
+ /* IP14_31_29 [3] */
+ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
+ FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
+ /* IP14_28_26 [3] */
+ FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
+ FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
+ /* IP14_25_23 [3] */
+ FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
+ 0, 0, 0,
+ /* IP14_22_20 [3] */
+ FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
+ 0, 0, 0,
+ /* IP14_19_17 [3] */
+ FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
+ FN_VI1_CLKENB_C, FN_VI1_G1_B,
+ 0, 0,
+ /* IP14_16_14 [3] */
+ FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
+ FN_VI1_CLK_C, FN_VI1_G0_B,
+ 0, 0,
+ /* IP14_13_11 [3] */
+ FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
+ 0, 0, 0,
+ /* IP14_10_8 [3] */
+ FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
+ 0, 0, 0,
+ /* IP14_7 [1] */
+ FN_SD2_DATA3, FN_MMC_D3,
+ /* IP14_6 [1] */
+ FN_SD2_DATA2, FN_MMC_D2,
+ /* IP14_5 [1] */
+ FN_SD2_DATA1, FN_MMC_D1,
+ /* IP14_4 [1] */
+ FN_SD2_DATA0, FN_MMC_D0,
+ /* IP14_3 [1] */
+ FN_SD2_CMD, FN_MMC_CMD,
+ /* IP14_2 [1] */
+ FN_SD2_CLK, FN_MMC_CLK,
+ /* IP14_1_0 [2] */
+ FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+ 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
+ /* IP15_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP15_29_27 [3] */
+ FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
+ FN_CAN0_TX_B, FN_VI1_DATA5_C,
+ 0, 0,
+ /* IP15_26_24 [3] */
+ FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
+ FN_CAN0_RX_B, FN_VI1_DATA4_C,
+ 0, 0,
+ /* IP15_23_21 [3] */
+ FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
+ FN_TCLK2, FN_VI1_DATA3_C, 0,
+ /* IP15_20_18 [3] */
+ FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
+ 0, 0, 0,
+ /* IP15_17_15 [3] */
+ FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
+ FN_TCLK1, FN_VI1_DATA1_C,
+ 0, 0,
+ /* IP15_14_12 [3] */
+ FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
+ FN_VI1_G7_B, FN_SCIFA3_SCK_C,
+ 0, 0,
+ /* IP15_11_9 [3] */
+ FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
+ FN_VI1_G6_B, FN_SCIFA3_RXD_C,
+ 0, 0,
+ /* IP15_8_6 [3] */
+ FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
+ FN_PWM5_B, FN_SCIFA3_TXD_C,
+ 0, 0, 0,
+ /* IP15_5_4 [2] */
+ FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
+ /* IP15_3_2 [2] */
+ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
+ /* IP15_1_0 [2] */
+ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+ 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
+ /* IP16_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_19_16 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_15_12 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_11_10 [2] */
+ FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
+ /* IP16_9_8 [2] */
+ FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
+ /* IP16_7_6 [2] */
+ FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
+ /* IP16_5_3 [3] */
+ FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
+ FN_GLO_SS_C, FN_VI1_DATA7_C,
+ 0, 0, 0,
+ /* IP16_2_0 [3] */
+ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
+ FN_GLO_SDATA_C, FN_VI1_DATA6_C,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
+ 3, 2, 2, 2, 1, 2, 2, 2) {
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_SCIF1 [2] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ /* SEL_SCIFB [2] */
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+ /* SEL_SCIFB2 [2] */
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
+ FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+ /* SEL_SCIFB1 [3] */
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
+ FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+ 0, 0, 0, 0,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+ /* SEL_SSI9 [1] */
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+ /* SEL_SCFA [1] */
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ /* SEL_QSP [1] */
+ FN_SEL_QSP_0, FN_SEL_QSP_1,
+ /* SEL_SSI7 [1] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+ /* SEL_HSCIF1 [3] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
+ FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
+ 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_VI1 [2] */
+ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_TMU [1] */
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ /* SEL_LBS [2] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_SOF0 [2] */
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 3, 1, 1, 3, 2, 1, 1, 2, 2,
+ 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+ /* SEL_SCIF0 [3] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
+ FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
+ 0, 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_SCIF [1] */
+ FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+ /* SEL_CAN0 [3] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+ 0, 0,
+ /* SEL_CAN1 [2] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_SCIFA2 [1] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ /* SEL_SCIF4 [2] */
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_ADG [1] */
+ FN_SEL_ADG_0, FN_SEL_ADG_1,
+ /* SEL_FM [3] */
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
+ FN_SEL_FM_3, FN_SEL_FM_4,
+ 0, 0, 0,
+ /* SEL_SCIFA5 [2] */
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_GPS [2] */
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+ /* SEL_SCIFA4 [2] */
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
+ /* SEL_SCIFA3 [2] */
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
+ /* SEL_SIM [1] */
+ FN_SEL_SIM_0, FN_SEL_SIM_1,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_SSI8 [1] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 1, 1, 2, 2, 3, 2, 2, 2, 1) {
+ /* SEL_HSCIF2 [2] */
+ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+ FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+ /* SEL_CANCLK [2] */
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+ FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+ /* SEL_IIC1 [2] */
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+ /* SEL_IIC0 [2] */
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
+ /* SEL_I2C4 [2] */
+ FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
+ /* SEL_I2C3 [2] */
+ FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
+ /* SEL_SCIF3 [2] */
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+ /* SEL_MMC [1] */
+ FN_SEL_MMC_0, FN_SEL_MMC_1,
+ /* SEL_SCIF5 [1] */
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_I2C2 [2] */
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ /* SEL_I2C1 [3] */
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
+ FN_SEL_I2C1_4,
+ 0, 0, 0,
+ /* SEL_I2C0 [2] */
+ FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* RESERVED [1] */
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
+ 3, 2, 2, 1, 1, 1, 1, 3, 2,
+ 2, 3, 1, 1, 1, 2, 2, 2, 2) {
+ /* SEL_SOF1 [3] */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+ FN_SEL_SOF1_4,
+ 0, 0, 0,
+ /* SEL_HSCIF0 [2] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
+ /* SEL_DIS [2] */
+ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_RAD [1] */
+ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ /* SEL_RCN [1] */
+ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* SEL_RSP [1] */
+ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ /* SEL_SCIF2 [3] */
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+ FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+ 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_SOF2 [3] */
+ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
+ FN_SEL_SOF2_3, FN_SEL_SOF2_4,
+ 0, 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_SSI1 [1] */
+ FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+ /* SEL_SSI0 [1] */
+ FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+ /* SEL_SSP [2] */
+ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0,
+ /* RESERVED [2] */
+ 0, 0, 0, 0, }
+ },
+ { },
+};
+
+static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
+ return -EINVAL;
+
+ *pocctrl = 0xe606008c;
+
+ return 31 - (pin & 0x1f);
+}
+
+static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
+ .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
+};
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7791
+const struct sh_pfc_soc_info r8a7791_pinmux_info = {
+ .name = "r8a77910_pfc",
+ .ops = &r8a7791_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.r8a779x),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.r8a779x),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7793
+const struct sh_pfc_soc_info r8a7793_pinmux_info = {
+ .name = "r8a77930_pfc",
+ .ops = &r8a7791_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.r8a779x),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.r8a779x),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
--- /dev/null
+/*
+ * r8a7792 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_29(0, fn, sfx), \
+ PORT_GP_23(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_28(3, fn, sfx), \
+ PORT_GP_17(4, fn, sfx), \
+ PORT_GP_17(5, fn, sfx), \
+ PORT_GP_17(6, fn, sfx), \
+ PORT_GP_17(7, fn, sfx), \
+ PORT_GP_17(8, fn, sfx), \
+ PORT_GP_17(9, fn, sfx), \
+ PORT_GP_32(10, fn, sfx), \
+ PORT_GP_30(11, fn, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
+ FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+ FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
+ FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
+ FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
+ FN_IP1_3, FN_IP1_4,
+
+ /* GPSR1 */
+ FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
+ FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
+ FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
+ FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
+
+ /* GPSR2 */
+ FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
+ FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
+ FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
+ FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
+
+ /* GPSR3 */
+ FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
+ FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
+ FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
+ FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
+ FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
+
+ /* GPSR4 */
+ FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
+ FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
+ FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
+ FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
+ FN_VI0_FIELD,
+
+ /* GPSR5 */
+ FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
+ FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
+ FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
+ FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
+ FN_VI1_FIELD,
+
+ /* GPSR6 */
+ FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
+ FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
+ FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
+
+ /* GPSR7 */
+ FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
+ FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
+ FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
+
+ /* GPSR8 */
+ FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
+ FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
+ FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
+
+ /* GPSR9 */
+ FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
+ FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
+ FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
+
+ /* GPSR10 */
+ FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
+ FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
+ FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
+ FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
+ FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
+ FN_CAN1_TX, FN_CAN1_RX,
+
+ /* GPSR11 */
+ FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
+ FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
+ FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
+ FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
+ FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
+ FN_ADICHS2, FN_AVS1, FN_AVS2,
+
+ /* IPSR0 */
+ FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
+ FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
+ FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
+ FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
+ FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
+ FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
+ FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
+ FN_DU0_DB7_C5,
+
+ /* IPSR1 */
+ FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
+ FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
+ FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
+ FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
+ FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
+ FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
+ FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
+
+ /* IPSR2 */
+ FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
+ FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
+ FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
+ FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
+ FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
+ FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
+ FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
+ FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
+ FN_VI2_FIELD, FN_AVB_TXD2,
+
+ /* IPSR3 */
+ FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
+ FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
+ FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
+ FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
+ FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
+ FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
+ FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
+ FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
+
+ /* IPSR4 */
+ FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
+ FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
+ FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
+ FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
+ FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
+ FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
+ FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
+ FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
+ FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
+ FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
+ FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
+ FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
+ FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
+
+ /* IPSR5 */
+ FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
+ FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
+ FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
+ FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
+ FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
+ FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
+
+ /* IPSR6 */
+ FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
+ FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
+ FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
+ FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
+ FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
+ FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
+
+ /* IPSR7 */
+ FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
+ FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
+ FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
+ FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
+ FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
+ FN_AUDIO_CLKA, FN_AUDIO_CLKB,
+
+ /* MOD_SEL */
+ FN_SEL_VI1_0, FN_SEL_VI1_1,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+ DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
+ DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
+ DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+ DU1_DISP_MARK, DU1_CDE_MARK,
+
+ D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
+ D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
+ D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
+ A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
+ A12_MARK, A13_MARK, A14_MARK, A15_MARK,
+
+ A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
+ EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
+ EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
+ WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
+ IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
+
+ VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
+ VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
+ VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
+ VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
+ VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
+ VI0_FIELD_MARK,
+
+ VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
+ VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
+ VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
+ VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
+ VI1_FIELD_MARK,
+
+ VI3_D10_Y2_MARK, VI3_FIELD_MARK,
+
+ VI4_CLK_MARK,
+
+ VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
+ VI5_FIELD_MARK,
+
+ HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
+ TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
+ TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
+ CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
+
+ SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
+ SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
+ ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
+ ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
+
+ /* IPSR0 */
+ DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
+ DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
+ DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
+ DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
+ DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
+ DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
+ DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
+ DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
+
+ /* IPSR1 */
+ DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
+ DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
+ DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
+ DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
+ DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
+ A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
+ A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
+
+ /* IPSR2 */
+ VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
+ VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
+ VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
+ VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
+ VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
+ VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
+ VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
+ VI2_D10_Y2_MARK, AVB_TXD0_MARK,
+ VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
+
+ /* IPSR3 */
+ VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
+ VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
+ VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
+ VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
+ VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
+ VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
+ VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
+ VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
+
+ /* IPSR4 */
+ VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
+ VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
+ RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
+ VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
+ VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
+ VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
+ VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
+ VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
+ VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
+ VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
+ VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
+
+ /* IPSR5 */
+ VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
+ VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
+ VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
+ VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
+ VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
+ VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
+ VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
+
+ /* IPSR6 */
+ MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
+ MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
+ MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
+ MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
+ DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
+ RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
+ RX3_MARK,
+
+ /* IPSR7 */
+ PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
+ FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
+ PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
+ SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
+ SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
+ AUDIO_CLKB_MARK,
+ PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_SINGLE(DU1_DB2_C0_DATA12),
+ PINMUX_SINGLE(DU1_DB3_C1_DATA13),
+ PINMUX_SINGLE(DU1_DB4_C2_DATA14),
+ PINMUX_SINGLE(DU1_DB5_C3_DATA15),
+ PINMUX_SINGLE(DU1_DB6_C4),
+ PINMUX_SINGLE(DU1_DB7_C5),
+ PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_SINGLE(DU1_DISP),
+ PINMUX_SINGLE(DU1_CDE),
+ PINMUX_SINGLE(D0),
+ PINMUX_SINGLE(D1),
+ PINMUX_SINGLE(D2),
+ PINMUX_SINGLE(D3),
+ PINMUX_SINGLE(D4),
+ PINMUX_SINGLE(D5),
+ PINMUX_SINGLE(D6),
+ PINMUX_SINGLE(D7),
+ PINMUX_SINGLE(D8),
+ PINMUX_SINGLE(D9),
+ PINMUX_SINGLE(D10),
+ PINMUX_SINGLE(D11),
+ PINMUX_SINGLE(D12),
+ PINMUX_SINGLE(D13),
+ PINMUX_SINGLE(D14),
+ PINMUX_SINGLE(D15),
+ PINMUX_SINGLE(A0),
+ PINMUX_SINGLE(A1),
+ PINMUX_SINGLE(A2),
+ PINMUX_SINGLE(A3),
+ PINMUX_SINGLE(A4),
+ PINMUX_SINGLE(A5),
+ PINMUX_SINGLE(A6),
+ PINMUX_SINGLE(A7),
+ PINMUX_SINGLE(A8),
+ PINMUX_SINGLE(A9),
+ PINMUX_SINGLE(A10),
+ PINMUX_SINGLE(A11),
+ PINMUX_SINGLE(A12),
+ PINMUX_SINGLE(A13),
+ PINMUX_SINGLE(A14),
+ PINMUX_SINGLE(A15),
+ PINMUX_SINGLE(A16),
+ PINMUX_SINGLE(A17),
+ PINMUX_SINGLE(A18),
+ PINMUX_SINGLE(A19),
+ PINMUX_SINGLE(CS1_N_A26),
+ PINMUX_SINGLE(EX_CS0_N),
+ PINMUX_SINGLE(EX_CS1_N),
+ PINMUX_SINGLE(EX_CS2_N),
+ PINMUX_SINGLE(EX_CS3_N),
+ PINMUX_SINGLE(EX_CS4_N),
+ PINMUX_SINGLE(EX_CS5_N),
+ PINMUX_SINGLE(BS_N),
+ PINMUX_SINGLE(RD_N),
+ PINMUX_SINGLE(RD_WR_N),
+ PINMUX_SINGLE(WE0_N),
+ PINMUX_SINGLE(WE1_N),
+ PINMUX_SINGLE(EX_WAIT0),
+ PINMUX_SINGLE(IRQ0),
+ PINMUX_SINGLE(IRQ1),
+ PINMUX_SINGLE(IRQ2),
+ PINMUX_SINGLE(IRQ3),
+ PINMUX_SINGLE(CS0_N),
+ PINMUX_SINGLE(VI0_CLK),
+ PINMUX_SINGLE(VI0_CLKENB),
+ PINMUX_SINGLE(VI0_HSYNC_N),
+ PINMUX_SINGLE(VI0_VSYNC_N),
+ PINMUX_SINGLE(VI0_D0_B0_C0),
+ PINMUX_SINGLE(VI0_D1_B1_C1),
+ PINMUX_SINGLE(VI0_D2_B2_C2),
+ PINMUX_SINGLE(VI0_D3_B3_C3),
+ PINMUX_SINGLE(VI0_D4_B4_C4),
+ PINMUX_SINGLE(VI0_D5_B5_C5),
+ PINMUX_SINGLE(VI0_D6_B6_C6),
+ PINMUX_SINGLE(VI0_D7_B7_C7),
+ PINMUX_SINGLE(VI0_D8_G0_Y0),
+ PINMUX_SINGLE(VI0_D9_G1_Y1),
+ PINMUX_SINGLE(VI0_D10_G2_Y2),
+ PINMUX_SINGLE(VI0_D11_G3_Y3),
+ PINMUX_SINGLE(VI0_FIELD),
+ PINMUX_SINGLE(VI1_CLK),
+ PINMUX_SINGLE(VI1_CLKENB),
+ PINMUX_SINGLE(VI1_HSYNC_N),
+ PINMUX_SINGLE(VI1_VSYNC_N),
+ PINMUX_SINGLE(VI1_D0_B0_C0),
+ PINMUX_SINGLE(VI1_D1_B1_C1),
+ PINMUX_SINGLE(VI1_D2_B2_C2),
+ PINMUX_SINGLE(VI1_D3_B3_C3),
+ PINMUX_SINGLE(VI1_D4_B4_C4),
+ PINMUX_SINGLE(VI1_D5_B5_C5),
+ PINMUX_SINGLE(VI1_D6_B6_C6),
+ PINMUX_SINGLE(VI1_D7_B7_C7),
+ PINMUX_SINGLE(VI1_D8_G0_Y0),
+ PINMUX_SINGLE(VI1_D9_G1_Y1),
+ PINMUX_SINGLE(VI1_D10_G2_Y2),
+ PINMUX_SINGLE(VI1_D11_G3_Y3),
+ PINMUX_SINGLE(VI1_FIELD),
+ PINMUX_SINGLE(VI3_D10_Y2),
+ PINMUX_SINGLE(VI3_FIELD),
+ PINMUX_SINGLE(VI4_CLK),
+ PINMUX_SINGLE(VI5_CLK),
+ PINMUX_SINGLE(VI5_D9_Y1),
+ PINMUX_SINGLE(VI5_D10_Y2),
+ PINMUX_SINGLE(VI5_D11_Y3),
+ PINMUX_SINGLE(VI5_FIELD),
+ PINMUX_SINGLE(HRTS0_N),
+ PINMUX_SINGLE(HCTS1_N),
+ PINMUX_SINGLE(SCK0),
+ PINMUX_SINGLE(CTS0_N),
+ PINMUX_SINGLE(RTS0_N),
+ PINMUX_SINGLE(TX0),
+ PINMUX_SINGLE(RX0),
+ PINMUX_SINGLE(SCK1),
+ PINMUX_SINGLE(CTS1_N),
+ PINMUX_SINGLE(RTS1_N),
+ PINMUX_SINGLE(TX1),
+ PINMUX_SINGLE(RX1),
+ PINMUX_SINGLE(SCIF_CLK),
+ PINMUX_SINGLE(CAN0_TX),
+ PINMUX_SINGLE(CAN0_RX),
+ PINMUX_SINGLE(CAN_CLK),
+ PINMUX_SINGLE(CAN1_TX),
+ PINMUX_SINGLE(CAN1_RX),
+ PINMUX_SINGLE(SD0_CLK),
+ PINMUX_SINGLE(SD0_CMD),
+ PINMUX_SINGLE(SD0_DAT0),
+ PINMUX_SINGLE(SD0_DAT1),
+ PINMUX_SINGLE(SD0_DAT2),
+ PINMUX_SINGLE(SD0_DAT3),
+ PINMUX_SINGLE(SD0_CD),
+ PINMUX_SINGLE(SD0_WP),
+ PINMUX_SINGLE(ADICLK),
+ PINMUX_SINGLE(ADICS_SAMP),
+ PINMUX_SINGLE(ADIDATA),
+ PINMUX_SINGLE(ADICHS0),
+ PINMUX_SINGLE(ADICHS1),
+ PINMUX_SINGLE(ADICHS2),
+ PINMUX_SINGLE(AVS1),
+ PINMUX_SINGLE(AVS2),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
+ PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
+ PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
+ PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
+ PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
+ PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
+ PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
+ PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
+ PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
+ PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
+ PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
+ PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
+ PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
+ PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
+ PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
+ PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
+ PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
+ PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
+ PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
+ PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
+ PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
+ PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
+ PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
+ PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
+ PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
+ PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
+ PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
+ PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
+ PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
+ PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
+ PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
+ PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
+ PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
+ PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
+ PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
+ PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
+ PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
+ PINMUX_IPSR_GPSR(IP1_17, A20),
+ PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
+ PINMUX_IPSR_GPSR(IP1_18, A21),
+ PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
+ PINMUX_IPSR_GPSR(IP1_19, A22),
+ PINMUX_IPSR_GPSR(IP1_19, IO2),
+ PINMUX_IPSR_GPSR(IP1_20, A23),
+ PINMUX_IPSR_GPSR(IP1_20, IO3),
+ PINMUX_IPSR_GPSR(IP1_21, A24),
+ PINMUX_IPSR_GPSR(IP1_21, SPCLK),
+ PINMUX_IPSR_GPSR(IP1_22, A25),
+ PINMUX_IPSR_GPSR(IP1_22, SSL),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
+ PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
+ PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
+ PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
+ PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
+ PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
+ PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
+ PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
+ PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
+ PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
+ PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
+ PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
+ PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
+ PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
+ PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
+ PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
+ PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
+ PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
+ PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
+ PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
+ PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
+ PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
+ PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
+ PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
+ PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
+ PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
+ PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
+ PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
+ PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
+ PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
+ PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
+ PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
+ PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
+ PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
+ PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
+ PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
+ PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
+ PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
+ PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
+ PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
+ PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
+ PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
+ PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
+ PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
+ PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
+ PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
+ PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
+ PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
+ PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
+ PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
+ PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
+ PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
+ PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
+ PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
+ PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
+ PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
+ PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
+ PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
+ PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
+ PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
+ PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
+ PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
+ PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
+ PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
+ PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
+ PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
+ PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
+ PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
+ PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
+ PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
+ PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
+ PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
+ PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
+ PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
+ PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
+ PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
+ PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
+ PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
+ PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
+ PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
+ PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
+ PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
+ PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
+ PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
+ PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
+ PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
+ PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
+ PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
+ PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
+ PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
+ PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
+ PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
+ PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
+ PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
+ PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
+ PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
+ PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
+ PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
+ PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
+ PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
+ PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
+ PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
+ PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
+ PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
+ PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
+ PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
+ PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
+ PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
+ PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
+ PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
+ PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP6_0, HSCK0),
+ PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
+ PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
+ PINMUX_IPSR_GPSR(IP6_2, HTX0),
+ PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
+ PINMUX_IPSR_GPSR(IP6_3, HRX0),
+ PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP6_4, HSCK1),
+ PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
+ PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP6_6, HTX1),
+ PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
+ PINMUX_IPSR_GPSR(IP6_7, HRX1),
+ PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
+ PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
+ PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
+ PINMUX_IPSR_GPSR(IP6_11_10, TX2),
+ PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
+ PINMUX_IPSR_GPSR(IP6_13_12, RX2),
+ PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
+ PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
+ PINMUX_IPSR_GPSR(IP6_16, TX3),
+ PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
+ PINMUX_IPSR_GPSR(IP6_18_17, RX3),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
+ PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
+ PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
+ PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
+ PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
+ PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
+ PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
+ PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
+ PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
+ PINMUX_IPSR_GPSR(IP7_6, PWM3),
+ PINMUX_IPSR_GPSR(IP7_7, PWM4),
+ PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
+ PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
+ PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
+ PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
+ PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ RCAR_GP_PIN(7, 9),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ RCAR_GP_PIN(7, 10),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ RCAR_GP_PIN(7, 11),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
+ RCAR_GP_PIN(6, 12),
+
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
+ RCAR_GP_PIN(6, 5),
+
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+ RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
+ RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
+};
+static const unsigned int avb_mii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+ AVB_TX_CLK_MARK, AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
+ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
+ RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
+
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
+ RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+ RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
+ RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
+ RCAR_GP_PIN(6, 11),
+};
+static const unsigned int avb_gmii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+ AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+ AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+ AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+ AVB_COL_MARK,
+};
+static const unsigned int avb_avtp_match_pins[] = {
+ RCAR_GP_PIN(7, 15),
+};
+static const unsigned int avb_avtp_match_mux[] = {
+ AVB_AVTP_MATCH_MARK,
+};
+/* - CAN -------------------------------------------------------------------- */
+static const unsigned int can0_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
+};
+static const unsigned int can0_data_mux[] = {
+ CAN0_TX_MARK, CAN0_RX_MARK,
+};
+static const unsigned int can1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
+};
+static const unsigned int can1_data_mux[] = {
+ CAN1_TX_MARK, CAN1_RX_MARK,
+};
+static const unsigned int can_clk_pins[] = {
+ /* CAN_CLK */
+ RCAR_GP_PIN(10, 29),
+};
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du0_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
+ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
+ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
+};
+static const unsigned int du0_rgb666_mux[] = {
+ DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
+ DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
+ DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
+ DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
+ DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
+ DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
+};
+static const unsigned int du0_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
+ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
+ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+};
+static const unsigned int du0_rgb888_mux[] = {
+ DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
+ DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
+ DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
+ DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
+ DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
+ DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
+ DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
+ DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
+ DU0_DB1_MARK, DU0_DB0_MARK,
+};
+static const unsigned int du0_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
+};
+static const unsigned int du0_sync_mux[] = {
+ DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
+};
+static const unsigned int du0_oddf_pins[] = {
+ /* EXODDF/ODDF/DISP/CDE */
+ RCAR_GP_PIN(0, 26),
+};
+static const unsigned int du0_oddf_mux[] = {
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(0, 27),
+};
+static const unsigned int du0_disp_mux[] = {
+ DU0_DISP_MARK,
+};
+static const unsigned int du0_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(0, 28),
+};
+static const unsigned int du0_cde_mux[] = {
+ DU0_CDE_MARK,
+};
+static const unsigned int du1_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int du1_rgb666_mux[] = {
+ DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
+ DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
+ DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
+ DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
+ DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
+ DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
+};
+static const unsigned int du1_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int du1_sync_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+};
+static const unsigned int du1_oddf_pins[] = {
+ /* EXODDF/ODDF/DISP/CDE */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int du1_oddf_mux[] = {
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int du1_disp_mux[] = {
+ DU1_DISP_MARK,
+};
+static const unsigned int du1_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int du1_cde_mux[] = {
+ DU1_CDE_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(3, 19),
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(3, 20),
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(3, 21),
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(3, 22),
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+/* - LBSC ------------------------------------------------------------------- */
+static const unsigned int lbsc_cs0_pins[] = {
+ /* CS0# */
+ RCAR_GP_PIN(3, 27),
+};
+static const unsigned int lbsc_cs0_mux[] = {
+ CS0_N_MARK,
+};
+static const unsigned int lbsc_cs1_pins[] = {
+ /* CS1#_A26 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int lbsc_cs1_mux[] = {
+ CS1_N_A26_MARK,
+};
+static const unsigned int lbsc_ex_cs0_pins[] = {
+ /* EX_CS0# */
+ RCAR_GP_PIN(3, 7),
+};
+static const unsigned int lbsc_ex_cs0_mux[] = {
+ EX_CS0_N_MARK,
+};
+static const unsigned int lbsc_ex_cs1_pins[] = {
+ /* EX_CS1# */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int lbsc_ex_cs1_mux[] = {
+ EX_CS1_N_MARK,
+};
+static const unsigned int lbsc_ex_cs2_pins[] = {
+ /* EX_CS2# */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int lbsc_ex_cs2_mux[] = {
+ EX_CS2_N_MARK,
+};
+static const unsigned int lbsc_ex_cs3_pins[] = {
+ /* EX_CS3# */
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int lbsc_ex_cs3_mux[] = {
+ EX_CS3_N_MARK,
+};
+static const unsigned int lbsc_ex_cs4_pins[] = {
+ /* EX_CS4# */
+ RCAR_GP_PIN(3, 11),
+};
+static const unsigned int lbsc_ex_cs4_mux[] = {
+ EX_CS4_N_MARK,
+};
+static const unsigned int lbsc_ex_cs5_pins[] = {
+ /* EX_CS5# */
+ RCAR_GP_PIN(3, 12),
+};
+static const unsigned int lbsc_ex_cs5_mux[] = {
+ EX_CS5_N_MARK,
+};
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(10, 0),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(10, 1),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(10, 4),
+};
+static const unsigned int msiof0_rx_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+static const unsigned int msiof0_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(10, 3),
+};
+static const unsigned int msiof0_tx_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(10, 5),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(10, 6),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(10, 9),
+};
+static const unsigned int msiof1_rx_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+static const unsigned int msiof1_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(10, 8),
+};
+static const unsigned int msiof1_tx_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+ SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int qspi_data2_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
+ RCAR_GP_PIN(3, 24),
+};
+static const unsigned int qspi_data4_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(10, 10),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_MARK, CTS0_N_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(10, 15),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_MARK, CTS1_N_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(10, 20),
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(10, 23),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* DAT0 */
+ RCAR_GP_PIN(11, 7),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* DAT[0-3] */
+ RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
+ RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(11, 11),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(11, 12),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - VIN0 ------------------------------------------------------------------- */
+static const union vin_data vin0_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+ /* G */
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+ RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
+ RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
+ /* R */
+ RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
+ RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
+ RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
+ },
+};
+static const union vin_data vin0_data_mux = {
+ .data24 = {
+ /* B */
+ VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
+ VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
+ VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
+ VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
+ /* G */
+ VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
+ VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
+ VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
+ VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
+ /* R */
+ VI0_D16_R0_MARK, VI0_D17_R1_MARK,
+ VI0_D18_R2_MARK, VI0_D19_R3_MARK,
+ VI0_D20_R4_MARK, VI0_D21_R5_MARK,
+ VI0_D22_R6_MARK, VI0_D23_R7_MARK,
+ },
+};
+static const unsigned int vin0_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+ /* G */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+ RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
+ RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
+ /* R */
+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
+ RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
+ RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
+};
+static const unsigned int vin0_data18_mux[] = {
+ /* B */
+ VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
+ VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
+ VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
+ /* G */
+ VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
+ VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
+ VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
+ /* R */
+ VI0_D18_R2_MARK, VI0_D19_R3_MARK,
+ VI0_D20_R4_MARK, VI0_D21_R5_MARK,
+ VI0_D22_R6_MARK, VI0_D23_R7_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ RCAR_GP_PIN(4, 16),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ RCAR_GP_PIN(4, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const union vin_data vin1_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+ /* G */
+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
+ /* R */
+ RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
+ RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
+ RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
+ RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
+ },
+};
+static const union vin_data vin1_data_mux = {
+ .data24 = {
+ /* B */
+ VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
+ VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
+ VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
+ /* G */
+ VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
+ VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
+ VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
+ VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
+ /* R */
+ VI1_D16_R0_MARK, VI1_D17_R1_MARK,
+ VI1_D18_R2_MARK, VI1_D19_R3_MARK,
+ VI1_D20_R4_MARK, VI1_D21_R5_MARK,
+ VI1_D22_R6_MARK, VI1_D23_R7_MARK,
+ },
+};
+static const unsigned int vin1_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+ /* G */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
+ /* R */
+ RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
+ RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
+ RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
+};
+static const unsigned int vin1_data18_mux[] = {
+ /* B */
+ VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
+ VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
+ /* G */
+ VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
+ VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
+ VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
+ /* R */
+ VI1_D18_R2_MARK, VI1_D19_R3_MARK,
+ VI1_D20_R4_MARK, VI1_D21_R5_MARK,
+ VI1_D22_R6_MARK, VI1_D23_R7_MARK,
+};
+static const union vin_data vin1_data_b_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+ /* G */
+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
+ RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
+ /* R */
+ RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
+ RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
+ RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
+ RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
+ },
+};
+static const union vin_data vin1_data_b_mux = {
+ .data24 = {
+ /* B */
+ VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
+ VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
+ VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
+ /* G */
+ VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
+ VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
+ VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
+ VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
+ /* R */
+ VI1_D16_R0_MARK, VI1_D17_R1_MARK,
+ VI1_D18_R2_MARK, VI1_D19_R3_MARK,
+ VI1_D20_R4_MARK, VI1_D21_R5_MARK,
+ VI1_D22_R6_MARK, VI1_D23_R7_MARK,
+ },
+};
+static const unsigned int vin1_data18_b_pins[] = {
+ /* B */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+ /* G */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
+ RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
+ /* R */
+ RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
+ RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
+ RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
+};
+static const unsigned int vin1_data18_b_mux[] = {
+ /* B */
+ VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
+ VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
+ /* G */
+ VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
+ VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
+ VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
+ /* R */
+ VI1_D18_R2_MARK, VI1_D19_R3_MARK,
+ VI1_D20_R4_MARK, VI1_D21_R5_MARK,
+ VI1_D22_R6_MARK, VI1_D23_R7_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ RCAR_GP_PIN(5, 1),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+/* - VIN2 ------------------------------------------------------------------- */
+static const union vin_data vin2_data_pins = {
+ .data16 = {
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+ RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
+ RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
+ },
+};
+static const union vin_data vin2_data_mux = {
+ .data16 = {
+ VI2_D0_C0_MARK, VI2_D1_C1_MARK,
+ VI2_D2_C2_MARK, VI2_D3_C3_MARK,
+ VI2_D4_C4_MARK, VI2_D5_C5_MARK,
+ VI2_D6_C6_MARK, VI2_D7_C7_MARK,
+ VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
+ VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
+ VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
+ VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
+ },
+};
+static const unsigned int vin2_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+};
+static const unsigned int vin2_sync_mux[] = {
+ VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
+};
+static const unsigned int vin2_field_pins[] = {
+ RCAR_GP_PIN(6, 16),
+};
+static const unsigned int vin2_field_mux[] = {
+ VI2_FIELD_MARK,
+};
+static const unsigned int vin2_clkenb_pins[] = {
+ RCAR_GP_PIN(6, 1),
+};
+static const unsigned int vin2_clkenb_mux[] = {
+ VI2_CLKENB_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+ RCAR_GP_PIN(6, 0),
+};
+static const unsigned int vin2_clk_mux[] = {
+ VI2_CLK_MARK,
+};
+/* - VIN3 ------------------------------------------------------------------- */
+static const union vin_data vin3_data_pins = {
+ .data16 = {
+ RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
+ RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
+ RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
+ RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
+ RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
+ RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
+ },
+};
+static const union vin_data vin3_data_mux = {
+ .data16 = {
+ VI3_D0_C0_MARK, VI3_D1_C1_MARK,
+ VI3_D2_C2_MARK, VI3_D3_C3_MARK,
+ VI3_D4_C4_MARK, VI3_D5_C5_MARK,
+ VI3_D6_C6_MARK, VI3_D7_C7_MARK,
+ VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
+ VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
+ VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
+ VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
+ },
+};
+static const unsigned int vin3_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
+};
+static const unsigned int vin3_sync_mux[] = {
+ VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
+};
+static const unsigned int vin3_field_pins[] = {
+ RCAR_GP_PIN(7, 16),
+};
+static const unsigned int vin3_field_mux[] = {
+ VI3_FIELD_MARK,
+};
+static const unsigned int vin3_clkenb_pins[] = {
+ RCAR_GP_PIN(7, 1),
+};
+static const unsigned int vin3_clkenb_mux[] = {
+ VI3_CLKENB_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+ RCAR_GP_PIN(7, 0),
+};
+static const unsigned int vin3_clk_mux[] = {
+ VI3_CLK_MARK,
+};
+/* - VIN4 ------------------------------------------------------------------- */
+static const union vin_data vin4_data_pins = {
+ .data12 = {
+ RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
+ RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
+ RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
+ RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
+ RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
+ },
+};
+static const union vin_data vin4_data_mux = {
+ .data12 = {
+ VI4_D0_C0_MARK, VI4_D1_C1_MARK,
+ VI4_D2_C2_MARK, VI4_D3_C3_MARK,
+ VI4_D4_C4_MARK, VI4_D5_C5_MARK,
+ VI4_D6_C6_MARK, VI4_D7_C7_MARK,
+ VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
+ VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
+ },
+};
+static const unsigned int vin4_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
+};
+static const unsigned int vin4_sync_mux[] = {
+ VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
+};
+static const unsigned int vin4_field_pins[] = {
+ RCAR_GP_PIN(8, 16),
+};
+static const unsigned int vin4_field_mux[] = {
+ VI4_FIELD_MARK,
+};
+static const unsigned int vin4_clkenb_pins[] = {
+ RCAR_GP_PIN(8, 1),
+};
+static const unsigned int vin4_clkenb_mux[] = {
+ VI4_CLKENB_MARK,
+};
+static const unsigned int vin4_clk_pins[] = {
+ RCAR_GP_PIN(8, 0),
+};
+static const unsigned int vin4_clk_mux[] = {
+ VI4_CLK_MARK,
+};
+/* - VIN5 ------------------------------------------------------------------- */
+static const union vin_data vin5_data_pins = {
+ .data12 = {
+ RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
+ RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
+ RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
+ RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
+ RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
+ RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
+ },
+};
+static const union vin_data vin5_data_mux = {
+ .data12 = {
+ VI5_D0_C0_MARK, VI5_D1_C1_MARK,
+ VI5_D2_C2_MARK, VI5_D3_C3_MARK,
+ VI5_D4_C4_MARK, VI5_D5_C5_MARK,
+ VI5_D6_C6_MARK, VI5_D7_C7_MARK,
+ VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
+ VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
+ },
+};
+static const unsigned int vin5_sync_pins[] = {
+ /* HSYNC#, VSYNC# */
+ RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
+};
+static const unsigned int vin5_sync_mux[] = {
+ VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
+};
+static const unsigned int vin5_field_pins[] = {
+ RCAR_GP_PIN(9, 16),
+};
+static const unsigned int vin5_field_mux[] = {
+ VI5_FIELD_MARK,
+};
+static const unsigned int vin5_clkenb_pins[] = {
+ RCAR_GP_PIN(9, 1),
+};
+static const unsigned int vin5_clkenb_mux[] = {
+ VI5_CLKENB_MARK,
+};
+static const unsigned int vin5_clk_pins[] = {
+ RCAR_GP_PIN(9, 0),
+};
+static const unsigned int vin5_clk_mux[] = {
+ VI5_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(avb_avtp_match),
+ SH_PFC_PIN_GROUP(can0_data),
+ SH_PFC_PIN_GROUP(can1_data),
+ SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(du0_rgb666),
+ SH_PFC_PIN_GROUP(du0_rgb888),
+ SH_PFC_PIN_GROUP(du0_sync),
+ SH_PFC_PIN_GROUP(du0_oddf),
+ SH_PFC_PIN_GROUP(du0_disp),
+ SH_PFC_PIN_GROUP(du0_cde),
+ SH_PFC_PIN_GROUP(du1_rgb666),
+ SH_PFC_PIN_GROUP(du1_sync),
+ SH_PFC_PIN_GROUP(du1_oddf),
+ SH_PFC_PIN_GROUP(du1_disp),
+ SH_PFC_PIN_GROUP(du1_cde),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(lbsc_cs0),
+ SH_PFC_PIN_GROUP(lbsc_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs0),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs2),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs3),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs4),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs5),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 24),
+ VIN_DATA_PIN_GROUP(vin1_data, 20),
+ SH_PFC_PIN_GROUP(vin1_data18),
+ VIN_DATA_PIN_GROUP(vin1_data, 16),
+ VIN_DATA_PIN_GROUP(vin1_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_data, 8),
+ VIN_DATA_PIN_GROUP(vin1_data_b, 24),
+ VIN_DATA_PIN_GROUP(vin1_data_b, 20),
+ SH_PFC_PIN_GROUP(vin1_data18_b),
+ VIN_DATA_PIN_GROUP(vin1_data_b, 16),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+ VIN_DATA_PIN_GROUP(vin2_data, 16),
+ VIN_DATA_PIN_GROUP(vin2_data, 12),
+ VIN_DATA_PIN_GROUP(vin2_data, 10),
+ VIN_DATA_PIN_GROUP(vin2_data, 8),
+ SH_PFC_PIN_GROUP(vin2_sync),
+ SH_PFC_PIN_GROUP(vin2_field),
+ SH_PFC_PIN_GROUP(vin2_clkenb),
+ SH_PFC_PIN_GROUP(vin2_clk),
+ VIN_DATA_PIN_GROUP(vin3_data, 16),
+ VIN_DATA_PIN_GROUP(vin3_data, 12),
+ VIN_DATA_PIN_GROUP(vin3_data, 10),
+ VIN_DATA_PIN_GROUP(vin3_data, 8),
+ SH_PFC_PIN_GROUP(vin3_sync),
+ SH_PFC_PIN_GROUP(vin3_field),
+ SH_PFC_PIN_GROUP(vin3_clkenb),
+ SH_PFC_PIN_GROUP(vin3_clk),
+ VIN_DATA_PIN_GROUP(vin4_data, 12),
+ VIN_DATA_PIN_GROUP(vin4_data, 10),
+ VIN_DATA_PIN_GROUP(vin4_data, 8),
+ SH_PFC_PIN_GROUP(vin4_sync),
+ SH_PFC_PIN_GROUP(vin4_field),
+ SH_PFC_PIN_GROUP(vin4_clkenb),
+ SH_PFC_PIN_GROUP(vin4_clk),
+ VIN_DATA_PIN_GROUP(vin5_data, 12),
+ VIN_DATA_PIN_GROUP(vin5_data, 10),
+ VIN_DATA_PIN_GROUP(vin5_data, 8),
+ SH_PFC_PIN_GROUP(vin5_sync),
+ SH_PFC_PIN_GROUP(vin5_field),
+ SH_PFC_PIN_GROUP(vin5_clkenb),
+ SH_PFC_PIN_GROUP(vin5_clk),
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_mii",
+ "avb_gmii",
+ "avb_avtp_match",
+};
+
+static const char * const can0_groups[] = {
+ "can0_data",
+ "can_clk",
+};
+
+static const char * const can1_groups[] = {
+ "can1_data",
+ "can_clk",
+};
+
+static const char * const du0_groups[] = {
+ "du0_rgb666",
+ "du0_rgb888",
+ "du0_sync",
+ "du0_oddf",
+ "du0_disp",
+ "du0_cde",
+};
+
+static const char * const du1_groups[] = {
+ "du1_rgb666",
+ "du1_sync",
+ "du1_oddf",
+ "du1_disp",
+ "du1_cde",
+};
+
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq1",
+ "intc_irq2",
+ "intc_irq3",
+};
+
+static const char * const lbsc_groups[] = {
+ "lbsc_cs0",
+ "lbsc_cs1",
+ "lbsc_ex_cs0",
+ "lbsc_ex_cs1",
+ "lbsc_ex_cs2",
+ "lbsc_ex_cs3",
+ "lbsc_ex_cs4",
+ "lbsc_ex_cs5",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_rx",
+ "msiof0_tx",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_rx",
+ "msiof1_tx",
+};
+
+static const char * const qspi_groups[] = {
+ "qspi_ctrl",
+ "qspi_data2",
+ "qspi_data4",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_clk",
+ "scif1_ctrl",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data24",
+ "vin0_data20",
+ "vin0_data18",
+ "vin0_data16",
+ "vin0_data12",
+ "vin0_data10",
+ "vin0_data8",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data24",
+ "vin1_data20",
+ "vin1_data18",
+ "vin1_data16",
+ "vin1_data12",
+ "vin1_data10",
+ "vin1_data8",
+ "vin1_data24_b",
+ "vin1_data20_b",
+ "vin1_data16_b",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+static const char * const vin2_groups[] = {
+ "vin2_data16",
+ "vin2_data12",
+ "vin2_data10",
+ "vin2_data8",
+ "vin2_sync",
+ "vin2_field",
+ "vin2_clkenb",
+ "vin2_clk",
+};
+
+static const char * const vin3_groups[] = {
+ "vin3_data16",
+ "vin3_data12",
+ "vin3_data10",
+ "vin3_data8",
+ "vin3_sync",
+ "vin3_field",
+ "vin3_clkenb",
+ "vin3_clk",
+};
+
+static const char * const vin4_groups[] = {
+ "vin4_data12",
+ "vin4_data10",
+ "vin4_data8",
+ "vin4_sync",
+ "vin4_field",
+ "vin4_clkenb",
+ "vin4_clk",
+};
+
+static const char * const vin5_groups[] = {
+ "vin5_data12",
+ "vin5_data10",
+ "vin5_data8",
+ "vin5_sync",
+ "vin5_field",
+ "vin5_clkenb",
+ "vin5_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(lbsc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+ SH_PFC_FUNCTION(vin2),
+ SH_PFC_FUNCTION(vin3),
+ SH_PFC_FUNCTION(vin4),
+ SH_PFC_FUNCTION(vin5),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_28_FN, FN_IP1_4,
+ GP_0_27_FN, FN_IP1_3,
+ GP_0_26_FN, FN_IP1_2,
+ GP_0_25_FN, FN_IP1_1,
+ GP_0_24_FN, FN_IP1_0,
+ GP_0_23_FN, FN_IP0_23,
+ GP_0_22_FN, FN_IP0_22,
+ GP_0_21_FN, FN_IP0_21,
+ GP_0_20_FN, FN_IP0_20,
+ GP_0_19_FN, FN_IP0_19,
+ GP_0_18_FN, FN_IP0_18,
+ GP_0_17_FN, FN_IP0_17,
+ GP_0_16_FN, FN_IP0_16,
+ GP_0_15_FN, FN_IP0_15,
+ GP_0_14_FN, FN_IP0_14,
+ GP_0_13_FN, FN_IP0_13,
+ GP_0_12_FN, FN_IP0_12,
+ GP_0_11_FN, FN_IP0_11,
+ GP_0_10_FN, FN_IP0_10,
+ GP_0_9_FN, FN_IP0_9,
+ GP_0_8_FN, FN_IP0_8,
+ GP_0_7_FN, FN_IP0_7,
+ GP_0_6_FN, FN_IP0_6,
+ GP_0_5_FN, FN_IP0_5,
+ GP_0_4_FN, FN_IP0_4,
+ GP_0_3_FN, FN_IP0_3,
+ GP_0_2_FN, FN_IP0_2,
+ GP_0_1_FN, FN_IP0_1,
+ GP_0_0_FN, FN_IP0_0 }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_22_FN, FN_DU1_CDE,
+ GP_1_21_FN, FN_DU1_DISP,
+ GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+ GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
+ GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
+ GP_1_17_FN, FN_DU1_DB7_C5,
+ GP_1_16_FN, FN_DU1_DB6_C4,
+ GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
+ GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
+ GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
+ GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
+ GP_1_11_FN, FN_IP1_16,
+ GP_1_10_FN, FN_IP1_15,
+ GP_1_9_FN, FN_IP1_14,
+ GP_1_8_FN, FN_IP1_13,
+ GP_1_7_FN, FN_IP1_12,
+ GP_1_6_FN, FN_IP1_11,
+ GP_1_5_FN, FN_IP1_10,
+ GP_1_4_FN, FN_IP1_9,
+ GP_1_3_FN, FN_IP1_8,
+ GP_1_2_FN, FN_IP1_7,
+ GP_1_1_FN, FN_IP1_6,
+ GP_1_0_FN, FN_IP1_5, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ GP_2_31_FN, FN_A15,
+ GP_2_30_FN, FN_A14,
+ GP_2_29_FN, FN_A13,
+ GP_2_28_FN, FN_A12,
+ GP_2_27_FN, FN_A11,
+ GP_2_26_FN, FN_A10,
+ GP_2_25_FN, FN_A9,
+ GP_2_24_FN, FN_A8,
+ GP_2_23_FN, FN_A7,
+ GP_2_22_FN, FN_A6,
+ GP_2_21_FN, FN_A5,
+ GP_2_20_FN, FN_A4,
+ GP_2_19_FN, FN_A3,
+ GP_2_18_FN, FN_A2,
+ GP_2_17_FN, FN_A1,
+ GP_2_16_FN, FN_A0,
+ GP_2_15_FN, FN_D15,
+ GP_2_14_FN, FN_D14,
+ GP_2_13_FN, FN_D13,
+ GP_2_12_FN, FN_D12,
+ GP_2_11_FN, FN_D11,
+ GP_2_10_FN, FN_D10,
+ GP_2_9_FN, FN_D9,
+ GP_2_8_FN, FN_D8,
+ GP_2_7_FN, FN_D7,
+ GP_2_6_FN, FN_D6,
+ GP_2_5_FN, FN_D5,
+ GP_2_4_FN, FN_D4,
+ GP_2_3_FN, FN_D3,
+ GP_2_2_FN, FN_D2,
+ GP_2_1_FN, FN_D1,
+ GP_2_0_FN, FN_D0 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_27_FN, FN_CS0_N,
+ GP_3_26_FN, FN_IP1_22,
+ GP_3_25_FN, FN_IP1_21,
+ GP_3_24_FN, FN_IP1_20,
+ GP_3_23_FN, FN_IP1_19,
+ GP_3_22_FN, FN_IRQ3,
+ GP_3_21_FN, FN_IRQ2,
+ GP_3_20_FN, FN_IRQ1,
+ GP_3_19_FN, FN_IRQ0,
+ GP_3_18_FN, FN_EX_WAIT0,
+ GP_3_17_FN, FN_WE1_N,
+ GP_3_16_FN, FN_WE0_N,
+ GP_3_15_FN, FN_RD_WR_N,
+ GP_3_14_FN, FN_RD_N,
+ GP_3_13_FN, FN_BS_N,
+ GP_3_12_FN, FN_EX_CS5_N,
+ GP_3_11_FN, FN_EX_CS4_N,
+ GP_3_10_FN, FN_EX_CS3_N,
+ GP_3_9_FN, FN_EX_CS2_N,
+ GP_3_8_FN, FN_EX_CS1_N,
+ GP_3_7_FN, FN_EX_CS0_N,
+ GP_3_6_FN, FN_CS1_N_A26,
+ GP_3_5_FN, FN_IP1_18,
+ GP_3_4_FN, FN_IP1_17,
+ GP_3_3_FN, FN_A19,
+ GP_3_2_FN, FN_A18,
+ GP_3_1_FN, FN_A17,
+ GP_3_0_FN, FN_A16 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_16_FN, FN_VI0_FIELD,
+ GP_4_15_FN, FN_VI0_D11_G3_Y3,
+ GP_4_14_FN, FN_VI0_D10_G2_Y2,
+ GP_4_13_FN, FN_VI0_D9_G1_Y1,
+ GP_4_12_FN, FN_VI0_D8_G0_Y0,
+ GP_4_11_FN, FN_VI0_D7_B7_C7,
+ GP_4_10_FN, FN_VI0_D6_B6_C6,
+ GP_4_9_FN, FN_VI0_D5_B5_C5,
+ GP_4_8_FN, FN_VI0_D4_B4_C4,
+ GP_4_7_FN, FN_VI0_D3_B3_C3,
+ GP_4_6_FN, FN_VI0_D2_B2_C2,
+ GP_4_5_FN, FN_VI0_D1_B1_C1,
+ GP_4_4_FN, FN_VI0_D0_B0_C0,
+ GP_4_3_FN, FN_VI0_VSYNC_N,
+ GP_4_2_FN, FN_VI0_HSYNC_N,
+ GP_4_1_FN, FN_VI0_CLKENB,
+ GP_4_0_FN, FN_VI0_CLK }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_16_FN, FN_VI1_FIELD,
+ GP_5_15_FN, FN_VI1_D11_G3_Y3,
+ GP_5_14_FN, FN_VI1_D10_G2_Y2,
+ GP_5_13_FN, FN_VI1_D9_G1_Y1,
+ GP_5_12_FN, FN_VI1_D8_G0_Y0,
+ GP_5_11_FN, FN_VI1_D7_B7_C7,
+ GP_5_10_FN, FN_VI1_D6_B6_C6,
+ GP_5_9_FN, FN_VI1_D5_B5_C5,
+ GP_5_8_FN, FN_VI1_D4_B4_C4,
+ GP_5_7_FN, FN_VI1_D3_B3_C3,
+ GP_5_6_FN, FN_VI1_D2_B2_C2,
+ GP_5_5_FN, FN_VI1_D1_B1_C1,
+ GP_5_4_FN, FN_VI1_D0_B0_C0,
+ GP_5_3_FN, FN_VI1_VSYNC_N,
+ GP_5_2_FN, FN_VI1_HSYNC_N,
+ GP_5_1_FN, FN_VI1_CLKENB,
+ GP_5_0_FN, FN_VI1_CLK }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_16_FN, FN_IP2_16,
+ GP_6_15_FN, FN_IP2_15,
+ GP_6_14_FN, FN_IP2_14,
+ GP_6_13_FN, FN_IP2_13,
+ GP_6_12_FN, FN_IP2_12,
+ GP_6_11_FN, FN_IP2_11,
+ GP_6_10_FN, FN_IP2_10,
+ GP_6_9_FN, FN_IP2_9,
+ GP_6_8_FN, FN_IP2_8,
+ GP_6_7_FN, FN_IP2_7,
+ GP_6_6_FN, FN_IP2_6,
+ GP_6_5_FN, FN_IP2_5,
+ GP_6_4_FN, FN_IP2_4,
+ GP_6_3_FN, FN_IP2_3,
+ GP_6_2_FN, FN_IP2_2,
+ GP_6_1_FN, FN_IP2_1,
+ GP_6_0_FN, FN_IP2_0 }
+ },
+ { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_7_16_FN, FN_VI3_FIELD,
+ GP_7_15_FN, FN_IP3_14,
+ GP_7_14_FN, FN_VI3_D10_Y2,
+ GP_7_13_FN, FN_IP3_13,
+ GP_7_12_FN, FN_IP3_12,
+ GP_7_11_FN, FN_IP3_11,
+ GP_7_10_FN, FN_IP3_10,
+ GP_7_9_FN, FN_IP3_9,
+ GP_7_8_FN, FN_IP3_8,
+ GP_7_7_FN, FN_IP3_7,
+ GP_7_6_FN, FN_IP3_6,
+ GP_7_5_FN, FN_IP3_5,
+ GP_7_4_FN, FN_IP3_4,
+ GP_7_3_FN, FN_IP3_3,
+ GP_7_2_FN, FN_IP3_2,
+ GP_7_1_FN, FN_IP3_1,
+ GP_7_0_FN, FN_IP3_0 }
+ },
+ { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_8_16_FN, FN_IP4_24,
+ GP_8_15_FN, FN_IP4_23,
+ GP_8_14_FN, FN_IP4_22,
+ GP_8_13_FN, FN_IP4_21,
+ GP_8_12_FN, FN_IP4_20_19,
+ GP_8_11_FN, FN_IP4_18_17,
+ GP_8_10_FN, FN_IP4_16_15,
+ GP_8_9_FN, FN_IP4_14_13,
+ GP_8_8_FN, FN_IP4_12_11,
+ GP_8_7_FN, FN_IP4_10_9,
+ GP_8_6_FN, FN_IP4_8_7,
+ GP_8_5_FN, FN_IP4_6_5,
+ GP_8_4_FN, FN_IP4_4,
+ GP_8_3_FN, FN_IP4_3_2,
+ GP_8_2_FN, FN_IP4_1,
+ GP_8_1_FN, FN_IP4_0,
+ GP_8_0_FN, FN_VI4_CLK }
+ },
+ { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_9_16_FN, FN_VI5_FIELD,
+ GP_9_15_FN, FN_VI5_D11_Y3,
+ GP_9_14_FN, FN_VI5_D10_Y2,
+ GP_9_13_FN, FN_VI5_D9_Y1,
+ GP_9_12_FN, FN_IP5_11,
+ GP_9_11_FN, FN_IP5_10,
+ GP_9_10_FN, FN_IP5_9,
+ GP_9_9_FN, FN_IP5_8,
+ GP_9_8_FN, FN_IP5_7,
+ GP_9_7_FN, FN_IP5_6,
+ GP_9_6_FN, FN_IP5_5,
+ GP_9_5_FN, FN_IP5_4,
+ GP_9_4_FN, FN_IP5_3,
+ GP_9_3_FN, FN_IP5_2,
+ GP_9_2_FN, FN_IP5_1,
+ GP_9_1_FN, FN_IP5_0,
+ GP_9_0_FN, FN_VI5_CLK }
+ },
+ { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
+ GP_10_31_FN, FN_CAN1_RX,
+ GP_10_30_FN, FN_CAN1_TX,
+ GP_10_29_FN, FN_CAN_CLK,
+ GP_10_28_FN, FN_CAN0_RX,
+ GP_10_27_FN, FN_CAN0_TX,
+ GP_10_26_FN, FN_SCIF_CLK,
+ GP_10_25_FN, FN_IP6_18_17,
+ GP_10_24_FN, FN_IP6_16,
+ GP_10_23_FN, FN_IP6_15_14,
+ GP_10_22_FN, FN_IP6_13_12,
+ GP_10_21_FN, FN_IP6_11_10,
+ GP_10_20_FN, FN_IP6_9_8,
+ GP_10_19_FN, FN_RX1,
+ GP_10_18_FN, FN_TX1,
+ GP_10_17_FN, FN_RTS1_N,
+ GP_10_16_FN, FN_CTS1_N,
+ GP_10_15_FN, FN_SCK1,
+ GP_10_14_FN, FN_RX0,
+ GP_10_13_FN, FN_TX0,
+ GP_10_12_FN, FN_RTS0_N,
+ GP_10_11_FN, FN_CTS0_N,
+ GP_10_10_FN, FN_SCK0,
+ GP_10_9_FN, FN_IP6_7,
+ GP_10_8_FN, FN_IP6_6,
+ GP_10_7_FN, FN_HCTS1_N,
+ GP_10_6_FN, FN_IP6_5,
+ GP_10_5_FN, FN_IP6_4,
+ GP_10_4_FN, FN_IP6_3,
+ GP_10_3_FN, FN_IP6_2,
+ GP_10_2_FN, FN_HRTS0_N,
+ GP_10_1_FN, FN_IP6_1,
+ GP_10_0_FN, FN_IP6_0 }
+ },
+ { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
+ 0, 0,
+ 0, 0,
+ GP_11_29_FN, FN_AVS2,
+ GP_11_28_FN, FN_AVS1,
+ GP_11_27_FN, FN_ADICHS2,
+ GP_11_26_FN, FN_ADICHS1,
+ GP_11_25_FN, FN_ADICHS0,
+ GP_11_24_FN, FN_ADIDATA,
+ GP_11_23_FN, FN_ADICS_SAMP,
+ GP_11_22_FN, FN_ADICLK,
+ GP_11_21_FN, FN_IP7_20,
+ GP_11_20_FN, FN_IP7_19,
+ GP_11_19_FN, FN_IP7_18,
+ GP_11_18_FN, FN_IP7_17,
+ GP_11_17_FN, FN_IP7_16,
+ GP_11_16_FN, FN_IP7_15_14,
+ GP_11_15_FN, FN_IP7_13_12,
+ GP_11_14_FN, FN_IP7_11_10,
+ GP_11_13_FN, FN_IP7_9_8,
+ GP_11_12_FN, FN_SD0_WP,
+ GP_11_11_FN, FN_SD0_CD,
+ GP_11_10_FN, FN_SD0_DAT3,
+ GP_11_9_FN, FN_SD0_DAT2,
+ GP_11_8_FN, FN_SD0_DAT1,
+ GP_11_7_FN, FN_SD0_DAT0,
+ GP_11_6_FN, FN_SD0_CMD,
+ GP_11_5_FN, FN_SD0_CLK,
+ GP_11_4_FN, FN_IP7_7,
+ GP_11_3_FN, FN_IP7_6,
+ GP_11_2_FN, FN_IP7_5_4,
+ GP_11_1_FN, FN_IP7_3_2,
+ GP_11_0_FN, FN_IP7_1_0 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
+ 4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP0_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP0_23 [1] */
+ FN_DU0_DB7_C5, 0,
+ /* IP0_22 [1] */
+ FN_DU0_DB6_C4, 0,
+ /* IP0_21 [1] */
+ FN_DU0_DB5_C3, 0,
+ /* IP0_20 [1] */
+ FN_DU0_DB4_C2, 0,
+ /* IP0_19 [1] */
+ FN_DU0_DB3_C1, 0,
+ /* IP0_18 [1] */
+ FN_DU0_DB2_C0, 0,
+ /* IP0_17 [1] */
+ FN_DU0_DB1, 0,
+ /* IP0_16 [1] */
+ FN_DU0_DB0, 0,
+ /* IP0_15 [1] */
+ FN_DU0_DG7_Y3_DATA15, 0,
+ /* IP0_14 [1] */
+ FN_DU0_DG6_Y2_DATA14, 0,
+ /* IP0_13 [1] */
+ FN_DU0_DG5_Y1_DATA13, 0,
+ /* IP0_12 [1] */
+ FN_DU0_DG4_Y0_DATA12, 0,
+ /* IP0_11 [1] */
+ FN_DU0_DG3_C7_DATA11, 0,
+ /* IP0_10 [1] */
+ FN_DU0_DG2_C6_DATA10, 0,
+ /* IP0_9 [1] */
+ FN_DU0_DG1_DATA9, 0,
+ /* IP0_8 [1] */
+ FN_DU0_DG0_DATA8, 0,
+ /* IP0_7 [1] */
+ FN_DU0_DR7_Y9_DATA7, 0,
+ /* IP0_6 [1] */
+ FN_DU0_DR6_Y8_DATA6, 0,
+ /* IP0_5 [1] */
+ FN_DU0_DR5_Y7_DATA5, 0,
+ /* IP0_4 [1] */
+ FN_DU0_DR4_Y6_DATA4, 0,
+ /* IP0_3 [1] */
+ FN_DU0_DR3_Y5_DATA3, 0,
+ /* IP0_2 [1] */
+ FN_DU0_DR2_Y4_DATA2, 0,
+ /* IP0_1 [1] */
+ FN_DU0_DR1_DATA1, 0,
+ /* IP0_0 [1] */
+ FN_DU0_DR0_DATA0, 0 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
+ 4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP1_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP1_23 [1] */
+ 0, 0,
+ /* IP1_22 [1] */
+ FN_A25, FN_SSL,
+ /* IP1_21 [1] */
+ FN_A24, FN_SPCLK,
+ /* IP1_20 [1] */
+ FN_A23, FN_IO3,
+ /* IP1_19 [1] */
+ FN_A22, FN_IO2,
+ /* IP1_18 [1] */
+ FN_A21, FN_MISO_IO1,
+ /* IP1_17 [1] */
+ FN_A20, FN_MOSI_IO0,
+ /* IP1_16 [1] */
+ FN_DU1_DG7_Y3_DATA11, 0,
+ /* IP1_15 [1] */
+ FN_DU1_DG6_Y2_DATA10, 0,
+ /* IP1_14 [1] */
+ FN_DU1_DG5_Y1_DATA9, 0,
+ /* IP1_13 [1] */
+ FN_DU1_DG4_Y0_DATA8, 0,
+ /* IP1_12 [1] */
+ FN_DU1_DG3_C7_DATA7, 0,
+ /* IP1_11 [1] */
+ FN_DU1_DG2_C6_DATA6, 0,
+ /* IP1_10 [1] */
+ FN_DU1_DR7_DATA5, 0,
+ /* IP1_9 [1] */
+ FN_DU1_DR6_DATA4, 0,
+ /* IP1_8 [1] */
+ FN_DU1_DR5_Y7_DATA3, 0,
+ /* IP1_7 [1] */
+ FN_DU1_DR4_Y6_DATA2, 0,
+ /* IP1_6 [1] */
+ FN_DU1_DR3_Y5_DATA1, 0,
+ /* IP1_5 [1] */
+ FN_DU1_DR2_Y4_DATA0, 0,
+ /* IP1_4 [1] */
+ FN_DU0_CDE, 0,
+ /* IP1_3 [1] */
+ FN_DU0_DISP, 0,
+ /* IP1_2 [1] */
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
+ /* IP1_1 [1] */
+ FN_DU0_EXVSYNC_DU0_VSYNC, 0,
+ /* IP1_0 [1] */
+ FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
+ 4, 4,
+ 4, 3, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP2_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_19_17 [3] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_16 [1] */
+ FN_VI2_FIELD, FN_AVB_TXD2,
+ /* IP2_15 [1] */
+ FN_VI2_D11_Y3, FN_AVB_TXD1,
+ /* IP2_14 [1] */
+ FN_VI2_D10_Y2, FN_AVB_TXD0,
+ /* IP2_13 [1] */
+ FN_VI2_D9_Y1, FN_AVB_TX_EN,
+ /* IP2_12 [1] */
+ FN_VI2_D8_Y0, FN_AVB_TXD3,
+ /* IP2_11 [1] */
+ FN_VI2_D7_C7, FN_AVB_COL,
+ /* IP2_10 [1] */
+ FN_VI2_D6_C6, FN_AVB_RX_ER,
+ /* IP2_9 [1] */
+ FN_VI2_D5_C5, FN_AVB_RXD7,
+ /* IP2_8 [1] */
+ FN_VI2_D4_C4, FN_AVB_RXD6,
+ /* IP2_7 [1] */
+ FN_VI2_D3_C3, FN_AVB_RXD5,
+ /* IP2_6 [1] */
+ FN_VI2_D2_C2, FN_AVB_RXD4,
+ /* IP2_5 [1] */
+ FN_VI2_D1_C1, FN_AVB_RXD3,
+ /* IP2_4 [1] */
+ FN_VI2_D0_C0, FN_AVB_RXD2,
+ /* IP2_3 [1] */
+ FN_VI2_VSYNC_N, FN_AVB_RXD1,
+ /* IP2_2 [1] */
+ FN_VI2_HSYNC_N, FN_AVB_RXD0,
+ /* IP2_1 [1] */
+ FN_VI2_CLKENB, FN_AVB_RX_DV,
+ /* IP2_0 [1] */
+ FN_VI2_CLK, FN_AVB_RX_CLK }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
+ 4, 4,
+ 4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP3_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP3_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP3_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP3_19_16 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP3_15 [1] */
+ 0, 0,
+ /* IP3_14 [1] */
+ FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
+ /* IP3_13 [1] */
+ FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
+ /* IP3_12 [1] */
+ FN_VI3_D8_Y0, FN_AVB_CRS,
+ /* IP3_11 [1] */
+ FN_VI3_D7_C7, FN_AVB_PHY_INT,
+ /* IP3_10 [1] */
+ FN_VI3_D6_C6, FN_AVB_MAGIC,
+ /* IP3_9 [1] */
+ FN_VI3_D5_C5, FN_AVB_LINK,
+ /* IP3_8 [1] */
+ FN_VI3_D4_C4, FN_AVB_MDIO,
+ /* IP3_7 [1] */
+ FN_VI3_D3_C3, FN_AVB_MDC,
+ /* IP3_6 [1] */
+ FN_VI3_D2_C2, FN_AVB_GTX_CLK,
+ /* IP3_5 [1] */
+ FN_VI3_D1_C1, FN_AVB_TX_ER,
+ /* IP3_4 [1] */
+ FN_VI3_D0_C0, FN_AVB_TXD7,
+ /* IP3_3 [1] */
+ FN_VI3_VSYNC_N, FN_AVB_TXD6,
+ /* IP3_2 [1] */
+ FN_VI3_HSYNC_N, FN_AVB_TXD5,
+ /* IP3_1 [1] */
+ FN_VI3_CLKENB, FN_AVB_TXD4,
+ /* IP3_0 [1] */
+ FN_VI3_CLK, FN_AVB_TX_CLK }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
+ 4, 3, 1,
+ 1, 1, 1, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 2, 1, 1) {
+ /* IP4_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP4_27_25 [3] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP4_24 [1] */
+ FN_VI4_FIELD, FN_VI3_D15_Y7,
+ /* IP4_23 [1] */
+ FN_VI4_D11_Y3, FN_VI3_D14_Y6,
+ /* IP4_22 [1] */
+ FN_VI4_D10_Y2, FN_VI3_D13_Y5,
+ /* IP4_21 [1] */
+ FN_VI4_D9_Y1, FN_VI3_D12_Y4,
+ /* IP4_20_19 [2] */
+ FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
+ /* IP4_18_17 [2] */
+ FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
+ /* IP4_16_15 [2] */
+ FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
+ /* IP4_14_13 [2] */
+ FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
+ /* IP4_12_11 [2] */
+ FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
+ /* IP4_10_9 [2] */
+ FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
+ /* IP4_8_7 [2] */
+ FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
+ /* IP4_6_5 [2] */
+ FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
+ /* IP4_4 [1] */
+ FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
+ /* IP4_3_2 [2] */
+ FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
+ /* IP4_1 [1] */
+ FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
+ /* IP4_0 [1] */
+ FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
+ 4, 4,
+ 4, 4,
+ 4, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP5_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP5_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP5_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP5_19_16 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP5_15_12 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP5_11 [1] */
+ FN_VI5_D8_Y0, FN_VI1_D23_R7,
+ /* IP5_10 [1] */
+ FN_VI5_D7_C7, FN_VI1_D22_R6,
+ /* IP5_9 [1] */
+ FN_VI5_D6_C6, FN_VI1_D21_R5,
+ /* IP5_8 [1] */
+ FN_VI5_D5_C5, FN_VI1_D20_R4,
+ /* IP5_7 [1] */
+ FN_VI5_D4_C4, FN_VI1_D19_R3,
+ /* IP5_6 [1] */
+ FN_VI5_D3_C3, FN_VI1_D18_R2,
+ /* IP5_5 [1] */
+ FN_VI5_D2_C2, FN_VI1_D17_R1,
+ /* IP5_4 [1] */
+ FN_VI5_D1_C1, FN_VI1_D16_R0,
+ /* IP5_3 [1] */
+ FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
+ /* IP5_2 [1] */
+ FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
+ /* IP5_1 [1] */
+ FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
+ /* IP5_0 [1] */
+ FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
+ 4, 4,
+ 4, 1, 2, 1,
+ 2, 2, 2, 2,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP6_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP6_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP6_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP6_19 [1] */
+ 0, 0,
+ /* IP6_18_17 [2] */
+ FN_DREQ1_N, FN_RX3, 0, 0,
+ /* IP6_16 [1] */
+ FN_TX3, 0,
+ /* IP6_15_14 [2] */
+ FN_DACK1, FN_SCK3, 0, 0,
+ /* IP6_13_12 [2] */
+ FN_DREQ0_N, FN_RX2, 0, 0,
+ /* IP6_11_10 [2] */
+ FN_DACK0, FN_TX2, 0, 0,
+ /* IP6_9_8 [2] */
+ FN_DRACK0, FN_SCK2, 0, 0,
+ /* IP6_7 [1] */
+ FN_MSIOF1_RXD, FN_HRX1,
+ /* IP6_6 [1] */
+ FN_MSIOF1_TXD, FN_HTX1,
+ /* IP6_5 [1] */
+ FN_MSIOF1_SYNC, FN_HRTS1_N,
+ /* IP6_4 [1] */
+ FN_MSIOF1_SCK, FN_HSCK1,
+ /* IP6_3 [1] */
+ FN_MSIOF0_RXD, FN_HRX0,
+ /* IP6_2 [1] */
+ FN_MSIOF0_TXD, FN_HTX0,
+ /* IP6_1 [1] */
+ FN_MSIOF0_SYNC, FN_HCTS0_N,
+ /* IP6_0 [1] */
+ FN_MSIOF0_SCK, FN_HSCK0 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
+ 4, 4,
+ 3, 1, 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 1, 1, 2, 2, 2) {
+ /* IP7_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_23_21 [3] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_20 [1] */
+ FN_AUDIO_CLKB, 0,
+ /* IP7_19 [1] */
+ FN_AUDIO_CLKA, 0,
+ /* IP7_18 [1] */
+ FN_AUDIO_CLKOUT, 0,
+ /* IP7_17 [1] */
+ FN_SSI_SDATA4, 0,
+ /* IP7_16 [1] */
+ FN_SSI_WS4, 0,
+ /* IP7_15_14 [2] */
+ FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
+ /* IP7_13_12 [2] */
+ FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
+ /* IP7_11_10 [2] */
+ FN_SSI_WS34, FN_TPU0TO1, 0, 0,
+ /* IP7_9_8 [2] */
+ FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
+ /* IP7_7 [1] */
+ FN_PWM4, 0,
+ /* IP7_6 [1] */
+ FN_PWM3, 0,
+ /* IP7_5_4 [2] */
+ FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
+ /* IP7_3_2 [2] */
+ FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
+ /* IP7_1_0 [2] */
+ FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
+ },
+ { },
+};
+
+const struct sh_pfc_soc_info r8a7792_pinmux_info = {
+ .name = "r8a77920_pfc",
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
--- /dev/null
+/*
+ * r8a7794/r8a7745 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Renesas Solutions Corp.
+ * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_32(0, fn, sfx), \
+ PORT_GP_26(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_32(3, fn, sfx), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_28(5, fn, sfx), \
+ PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_1(6, 24, fn, sfx), \
+ PORT_GP_1(6, 25, fn, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
+ FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
+ FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
+ FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
+ FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
+ FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
+ FN_IP2_17_16,
+
+ /* GPSR1 */
+ FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
+ FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
+ FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
+ FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
+ FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
+
+ /* GPSR2 */
+ FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
+ FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
+ FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
+ FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
+ FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
+ FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
+ FN_IP6_5_4, FN_IP6_7_6,
+
+ /* GPSR3 */
+ FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
+ FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
+ FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
+ FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
+ FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
+ FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
+ FN_IP8_22_20,
+
+ /* GPSR4 */
+ FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
+ FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
+ FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
+ FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
+ FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
+ FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
+ FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
+
+ /* GPSR5 */
+ FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
+ FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
+ FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
+ FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
+ FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
+ FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
+
+ /* GPSR6 */
+ FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
+ FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
+ FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
+ FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
+ FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
+
+ /* IPSR0 */
+ FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
+ FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
+ FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
+ FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
+ FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
+ FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
+ FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
+ FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
+
+ /* IPSR1 */
+ FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
+ FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
+ FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
+ FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
+ FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
+ FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
+ FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
+ FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
+ FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
+ FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
+ FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
+ FN_A1, FN_SCIFB1_TXD,
+ FN_A3, FN_SCIFB0_SCK,
+ FN_A4, FN_SCIFB0_TXD,
+ FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
+ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
+
+ /* IPSR2 */
+ FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
+ FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
+ FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
+ FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
+ FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
+ FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
+ FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
+ FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
+ FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
+ FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
+ FN_TPUTO2_B,
+ FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
+ FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
+ FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
+ FN_A20, FN_SPCLK,
+
+ /* IPSR3 */
+ FN_A21, FN_MOSI_IO0,
+ FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
+ FN_A23, FN_IO2, FN_ATAWR1_N,
+ FN_A24, FN_IO3, FN_EX_WAIT2,
+ FN_A25, FN_SSL, FN_ATARD1_N,
+ FN_CS0_N, FN_VI1_DATA8,
+ FN_CS1_N_A26, FN_VI1_DATA9,
+ FN_EX_CS0_N, FN_VI1_DATA10,
+ FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
+ FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
+ FN_SCIFB2_TXD,
+ FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
+ FN_SCIFB2_SCK,
+ FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
+ FN_SCIFB2_CTS_N,
+ FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
+ FN_SCIFB2_RTS_N,
+ FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
+ FN_RD_N, FN_ATACS11_N,
+ FN_RD_WR_N, FN_ATAG1_N,
+
+ /* IPSR4 */
+ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
+ FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
+ FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
+ FN_DU0_DR2, FN_LCDOUT18,
+ FN_DU0_DR3, FN_LCDOUT19,
+ FN_DU0_DR4, FN_LCDOUT20,
+ FN_DU0_DR5, FN_LCDOUT21,
+ FN_DU0_DR6, FN_LCDOUT22,
+ FN_DU0_DR7, FN_LCDOUT23,
+ FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
+ FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
+ FN_DU0_DG2, FN_LCDOUT10,
+ FN_DU0_DG3, FN_LCDOUT11,
+ FN_DU0_DG4, FN_LCDOUT12,
+
+ /* IPSR5 */
+ FN_DU0_DG5, FN_LCDOUT13,
+ FN_DU0_DG6, FN_LCDOUT14,
+ FN_DU0_DG7, FN_LCDOUT15,
+ FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
+ FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
+ FN_DU0_DB2, FN_LCDOUT2,
+ FN_DU0_DB3, FN_LCDOUT3,
+ FN_DU0_DB4, FN_LCDOUT4,
+ FN_DU0_DB5, FN_LCDOUT5,
+ FN_DU0_DB6, FN_LCDOUT6,
+ FN_DU0_DB7, FN_LCDOUT7,
+ FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
+ FN_DU0_DOTCLKOUT0, FN_QCLK,
+ FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
+ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
+
+ /* IPSR6 */
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_DU0_DISP, FN_QPOLA,
+ FN_DU0_CDE, FN_QPOLB,
+ FN_VI0_CLK, FN_AVB_RX_CLK,
+ FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
+ FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
+ FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
+ FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
+ FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
+ FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
+ FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+ FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
+ FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
+ FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
+ FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
+ FN_AVB_TX_EN,
+ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
+ FN_ADIDATA,
+
+ /* IPSR7 */
+ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
+ FN_ADICS_SAMP,
+ FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
+ FN_ADICLK,
+ FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
+ FN_ADICHS0,
+ FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
+ FN_ADICHS1,
+ FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
+ FN_ADICHS2,
+ FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
+ FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
+ FN_SSI_WS5_B,
+ FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
+ FN_SSI_SDATA5_B,
+ FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
+ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
+ FN_SSI_WS6_B,
+ FN_DREQ0_N, FN_SCIFB1_RXD,
+
+ /* IPSR8 */
+ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
+ FN_SSI_SDATA6_B,
+ FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
+ FN_SSI_SCK78_B,
+ FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
+ FN_SSI_WS78_B,
+ FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+ FN_AVB_MAGIC, FN_SSI_SDATA7_B,
+ FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
+ FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
+ FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+ FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
+ FN_CAN1_RX_D, FN_TPUTO0_B,
+ FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
+ FN_CAN1_TX_D,
+ FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
+ FN_TPUTO1_B,
+ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
+ FN_BPFCLK_C,
+ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
+ FN_FMCLK_C,
+
+ /* IPSR9 */
+ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
+ FN_FMIN_C,
+ FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
+ FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
+ FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
+ FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
+ FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
+ FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
+ FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
+ FN_SPEEDIN_B,
+ FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
+ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
+ FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
+
+ /* IPSR10 */
+ FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
+ FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
+ FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
+ FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
+ FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
+ FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
+ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
+ FN_SSI_SCK4_B,
+ FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
+ FN_SSI_WS4_B,
+ FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
+ FN_SSI_SDATA4_B,
+ FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
+
+ /* IPSR11 */
+ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+ FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+ FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
+ FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+ FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+ FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
+ FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
+ FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
+ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
+ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
+
+ /* IPSR12 */
+ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
+ FN_DREQ1_N_B,
+ FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
+ FN_CAN1_RX_C, FN_DACK1_B,
+ FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
+ FN_CAN1_TX_C, FN_DREQ2_N,
+ FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
+ FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
+ FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
+ FN_DACK2, FN_ETH_MDIO_B,
+ FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
+ FN_ETH_CRS_DV_B,
+ FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
+ FN_ETH_RX_ER_B,
+ FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
+ FN_ETH_RXD0_B,
+ FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
+
+ /* IPSR13 */
+ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
+ FN_ATACS00_N, FN_ETH_LINK_B,
+ FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
+ FN_ATACS10_N, FN_ETH_REFCLK_B,
+ FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
+ FN_ETH_TXD1_B,
+ FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
+ FN_ETH_TX_EN_B,
+ FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
+ FN_ATADIR0_N, FN_ETH_MAGIC_B,
+ FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
+ FN_TS_SDATA_C, FN_ETH_TXD0_B,
+ FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
+ FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
+ FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
+ FN_TS_SDEN_C, FN_FMCLK_E,
+ FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
+ FN_TS_SPSYNC_C, FN_FMIN_E,
+
+ /* MOD_SEL */
+ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
+ FN_SEL_DARC_4,
+ FN_SEL_ETH_0, FN_SEL_ETH_1,
+ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+ FN_SEL_I2C00_4,
+ FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+ FN_SEL_I2C01_4,
+ FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+ FN_SEL_I2C02_4,
+ FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+ FN_SEL_I2C03_4,
+ FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+ FN_SEL_I2C04_4,
+ FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
+
+ /* MOD_SEL2 */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
+ FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
+ FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
+ FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
+ FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
+ FN_SEL_TMU_0, FN_SEL_TMU_1,
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+
+ /* MOD_SEL3 */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
+ FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+ FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
+ FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
+ FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
+ FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
+ FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
+ FN_SEL_SSI9_1,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+ A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+
+ SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
+ SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
+
+ SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
+ SD1_DATA2_MARK, SD1_DATA3_MARK,
+
+ /* IPSR0 */
+ SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
+ MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
+ SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
+ SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
+ MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
+ CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
+ CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
+ SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
+ SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
+ SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
+
+ /* IPSR1 */
+ D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
+ D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
+ D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
+ D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
+ D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
+ D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
+ D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
+ D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
+ D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
+ D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
+ A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
+ A1_MARK, SCIFB1_TXD_MARK,
+ A3_MARK, SCIFB0_SCK_MARK,
+ A4_MARK, SCIFB0_TXD_MARK,
+ A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
+ A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
+
+ /* IPSR2 */
+ A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
+ A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
+ A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
+ A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
+ A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
+ A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
+ A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
+ A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
+ A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
+ A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
+ CAN_CLK_C_MARK, TPUTO2_B_MARK,
+ A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
+ A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
+ A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
+ A20_MARK, SPCLK_MARK,
+
+ /* IPSR3 */
+ A21_MARK, MOSI_IO0_MARK,
+ A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
+ A23_MARK, IO2_MARK, ATAWR1_N_MARK,
+ A24_MARK, IO3_MARK, EX_WAIT2_MARK,
+ A25_MARK, SSL_MARK, ATARD1_N_MARK,
+ CS0_N_MARK, VI1_DATA8_MARK,
+ CS1_N_A26_MARK, VI1_DATA9_MARK,
+ EX_CS0_N_MARK, VI1_DATA10_MARK,
+ EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
+ EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
+ TPUTO3_MARK, SCIFB2_TXD_MARK,
+ EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
+ BPFCLK_MARK, SCIFB2_SCK_MARK,
+ EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
+ FMCLK_MARK, SCIFB2_CTS_N_MARK,
+ EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
+ FMIN_MARK, SCIFB2_RTS_N_MARK,
+ BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
+ RD_N_MARK, ATACS11_N_MARK,
+ RD_WR_N_MARK, ATAG1_N_MARK,
+
+ /* IPSR4 */
+ EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
+ DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
+ DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
+ DU0_DR2_MARK, LCDOUT18_MARK,
+ DU0_DR3_MARK, LCDOUT19_MARK,
+ DU0_DR4_MARK, LCDOUT20_MARK,
+ DU0_DR5_MARK, LCDOUT21_MARK,
+ DU0_DR6_MARK, LCDOUT22_MARK,
+ DU0_DR7_MARK, LCDOUT23_MARK,
+ DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
+ DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
+ DU0_DG2_MARK, LCDOUT10_MARK,
+ DU0_DG3_MARK, LCDOUT11_MARK,
+ DU0_DG4_MARK, LCDOUT12_MARK,
+
+ /* IPSR5 */
+ DU0_DG5_MARK, LCDOUT13_MARK,
+ DU0_DG6_MARK, LCDOUT14_MARK,
+ DU0_DG7_MARK, LCDOUT15_MARK,
+ DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
+ CAN0_RX_C_MARK,
+ DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
+ CAN0_TX_C_MARK,
+ DU0_DB2_MARK, LCDOUT2_MARK,
+ DU0_DB3_MARK, LCDOUT3_MARK,
+ DU0_DB4_MARK, LCDOUT4_MARK,
+ DU0_DB5_MARK, LCDOUT5_MARK,
+ DU0_DB6_MARK, LCDOUT6_MARK,
+ DU0_DB7_MARK, LCDOUT7_MARK,
+ DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
+ DU0_DOTCLKOUT0_MARK, QCLK_MARK,
+ DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
+ DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
+
+ /* IPSR6 */
+ DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
+ VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
+ VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
+ VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
+ VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
+ VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
+ VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
+ VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
+ VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
+ VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
+ AVB_RXD7_MARK,
+ VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
+ AVB_RX_ER_MARK,
+ VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
+ AVB_COL_MARK,
+ VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
+ AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
+ ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
+ AVB_TX_CLK_MARK, ADIDATA_MARK,
+
+ /* IPSR7 */
+ ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
+ AVB_TXD0_MARK, ADICS_SAMP_MARK,
+ ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
+ AVB_TXD1_MARK, ADICLK_MARK,
+ ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
+ AVB_TXD2_MARK, ADICHS0_MARK,
+ ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
+ AVB_TXD3_MARK, ADICHS1_MARK,
+ ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
+ AVB_TXD4_MARK, ADICHS2_MARK,
+ ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
+ SSI_SCK5_B_MARK,
+ ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
+ AVB_TXD6_MARK, SSI_WS5_B_MARK,
+ ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
+ AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
+ ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
+ SSI_SCK6_B_MARK,
+ ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
+ AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
+ DREQ0_N_MARK, SCIFB1_RXD_MARK,
+
+ /* IPSR8 */
+ ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
+ AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
+ I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
+ HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
+ AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
+ SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
+ HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
+ AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
+ HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
+ I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
+ AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
+ SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
+ CAN1_TX_D_MARK,
+ I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
+ TS_SDATA_D_MARK, TPUTO1_B_MARK,
+ I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
+ BPFCLK_C_MARK,
+ MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
+ TS_SDEN_D_MARK, FMCLK_C_MARK,
+
+ /* IPSR9 */
+ MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
+ TS_SPSYNC_D_MARK, FMIN_C_MARK,
+ MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
+ MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
+ MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
+ FMCLK_B_MARK,
+ MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
+ FMIN_B_MARK,
+ HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
+ HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
+ HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
+ SPEEDIN_B_MARK,
+ HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
+ SSI_SCK1_B_MARK,
+ HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
+ SSI_WS1_B_MARK,
+ SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
+ CAN_TXCLK_MARK,
+
+ /* IPSR10 */
+ SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
+ SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
+ SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
+ SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
+ SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
+ SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
+ SSI_SDATA9_B_MARK,
+ SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
+ AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
+ SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
+ AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
+ I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
+ SSI_SDATA4_B_MARK,
+ I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
+ SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
+
+ /* IPSR11 */
+ SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
+ SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
+ SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK,
+ SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+ SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
+ SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
+ SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
+ CAN_CLK_D_MARK,
+ SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
+ SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
+ SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
+
+ /* IPSR12 */
+ SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
+ DREQ1_N_B_MARK,
+ SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
+ CAN1_RX_C_MARK, DACK1_B_MARK,
+ SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
+ CAN1_TX_C_MARK, DREQ2_N_MARK,
+ SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
+ SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
+ SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
+ SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
+ DACK2_MARK, ETH_MDIO_B_MARK,
+ SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
+ CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
+ SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
+ CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
+ SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
+ ETH_RXD0_B_MARK,
+ SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
+ ETH_RXD1_B_MARK,
+
+ /* IPSR13 */
+ SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
+ ATACS00_N_MARK, ETH_LINK_B_MARK,
+ SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
+ VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
+ SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
+ EX_WAIT1_MARK, ETH_TXD1_B_MARK,
+ SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
+ ATARD0_N_MARK, ETH_TX_EN_B_MARK,
+ SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
+ ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
+ AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
+ TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
+ AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
+ TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
+ AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
+ TS_SDEN_C_MARK, FMCLK_E_MARK,
+ AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
+ TS_SPSYNC_C_MARK, FMIN_E_MARK,
+ PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_SINGLE(A2),
+ PINMUX_SINGLE(WE0_N),
+ PINMUX_SINGLE(WE1_N),
+ PINMUX_SINGLE(DACK0),
+ PINMUX_SINGLE(USB0_PWEN),
+ PINMUX_SINGLE(USB0_OVC),
+ PINMUX_SINGLE(USB1_PWEN),
+ PINMUX_SINGLE(USB1_OVC),
+ PINMUX_SINGLE(SD0_CLK),
+ PINMUX_SINGLE(SD0_CMD),
+ PINMUX_SINGLE(SD0_DATA0),
+ PINMUX_SINGLE(SD0_DATA1),
+ PINMUX_SINGLE(SD0_DATA2),
+ PINMUX_SINGLE(SD0_DATA3),
+ PINMUX_SINGLE(SD0_CD),
+ PINMUX_SINGLE(SD0_WP),
+ PINMUX_SINGLE(SD1_CLK),
+ PINMUX_SINGLE(SD1_CMD),
+ PINMUX_SINGLE(SD1_DATA0),
+ PINMUX_SINGLE(SD1_DATA1),
+ PINMUX_SINGLE(SD1_DATA2),
+ PINMUX_SINGLE(SD1_DATA3),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
+ PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
+ PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
+ PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
+ PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
+ PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
+ PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
+ PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
+ PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
+ PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
+ PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
+ PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
+ PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
+ PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
+ PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
+ PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
+ PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
+ PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
+ PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
+ PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
+ PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
+ PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
+ PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP0_23_22, D0),
+ PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
+ PINMUX_IPSR_GPSR(IP0_24, D1),
+ PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_GPSR(IP0_25, D2),
+ PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_GPSR(IP0_27_26, D3),
+ PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
+ PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
+ PINMUX_IPSR_GPSR(IP0_29_28, D4),
+ PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
+ PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
+ PINMUX_IPSR_GPSR(IP0_31_30, D5),
+ PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_1_0, D6),
+ PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
+ PINMUX_IPSR_GPSR(IP1_3_2, D7),
+ PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
+ PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
+ PINMUX_IPSR_GPSR(IP1_5_4, D8),
+ PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
+ PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
+ PINMUX_IPSR_GPSR(IP1_7_6, D9),
+ PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
+ PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
+ PINMUX_IPSR_GPSR(IP1_10_8, D10),
+ PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
+ PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
+ PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
+ PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
+ PINMUX_IPSR_GPSR(IP1_12_11, D11),
+ PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
+ PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
+ PINMUX_IPSR_GPSR(IP1_14_13, D12),
+ PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
+ PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
+ PINMUX_IPSR_GPSR(IP1_17_15, D13),
+ PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
+ PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
+ PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
+ PINMUX_IPSR_GPSR(IP1_19_18, D14),
+ PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
+ PINMUX_IPSR_GPSR(IP1_21_20, D15),
+ PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
+ PINMUX_IPSR_GPSR(IP1_23_22, A0),
+ PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
+ PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
+ PINMUX_IPSR_GPSR(IP1_24, A1),
+ PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
+ PINMUX_IPSR_GPSR(IP1_26, A3),
+ PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
+ PINMUX_IPSR_GPSR(IP1_27, A4),
+ PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
+ PINMUX_IPSR_GPSR(IP1_29_28, A5),
+ PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
+ PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
+ PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
+ PINMUX_IPSR_GPSR(IP1_31_30, A6),
+ PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
+ PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
+ PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_1_0, A7),
+ PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
+ PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
+ PINMUX_IPSR_GPSR(IP2_3_2, A8),
+ PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
+ PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
+ PINMUX_IPSR_GPSR(IP2_5_4, A9),
+ PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
+ PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
+ PINMUX_IPSR_GPSR(IP2_7_6, A10),
+ PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
+ PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
+ PINMUX_IPSR_GPSR(IP2_9_8, A11),
+ PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
+ PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
+ PINMUX_IPSR_GPSR(IP2_11_10, A12),
+ PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
+ PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
+ PINMUX_IPSR_GPSR(IP2_13_12, A13),
+ PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
+ PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
+ PINMUX_IPSR_GPSR(IP2_15_14, A14),
+ PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
+ PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
+ PINMUX_IPSR_GPSR(IP2_17_16, A15),
+ PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
+ PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
+ PINMUX_IPSR_GPSR(IP2_20_18, A16),
+ PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
+ PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
+ PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
+ PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
+ PINMUX_IPSR_GPSR(IP2_23_21, A17),
+ PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
+ PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
+ PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
+ PINMUX_IPSR_GPSR(IP2_26_24, A18),
+ PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
+ PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
+ PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
+ PINMUX_IPSR_GPSR(IP2_29_27, A19),
+ PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
+ PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
+ PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
+ PINMUX_IPSR_GPSR(IP2_31_30, A20),
+ PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_1_0, A21),
+ PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
+ PINMUX_IPSR_GPSR(IP3_3_2, A22),
+ PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
+ PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
+ PINMUX_IPSR_GPSR(IP3_5_4, A23),
+ PINMUX_IPSR_GPSR(IP3_5_4, IO2),
+ PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
+ PINMUX_IPSR_GPSR(IP3_7_6, A24),
+ PINMUX_IPSR_GPSR(IP3_7_6, IO3),
+ PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_9_8, A25),
+ PINMUX_IPSR_GPSR(IP3_9_8, SSL),
+ PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
+ PINMUX_IPSR_GPSR(IP3_10, CS0_N),
+ PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
+ PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
+ PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
+ PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
+ PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
+ PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
+ PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
+ PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
+ PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
+ PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
+ PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
+ PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
+ PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
+ PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
+ PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
+ PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
+ PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
+ PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
+ PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
+ PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
+ PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
+ PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
+ PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
+ PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
+ PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
+ PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
+ PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
+ PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
+ PINMUX_IPSR_GPSR(IP3_30, RD_N),
+ PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
+ PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
+ PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
+ PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
+ PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
+ PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
+ PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
+ PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
+ PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
+ PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
+ PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
+ PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
+ PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
+ PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
+ PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
+ PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
+ PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
+ PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
+ PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
+ PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
+ PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
+ PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
+ PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
+ PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
+ PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
+ PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
+ PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
+ PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
+ PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
+ PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
+ PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
+ PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
+ PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
+ PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
+ PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
+ PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
+ PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
+ PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
+ PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
+ PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
+ PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
+ PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
+ PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
+ PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
+ PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
+ PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
+ PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
+ PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
+ PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
+ PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
+ PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
+ PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
+ PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
+ PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
+ PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
+ PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
+ PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
+ PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
+ PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
+ PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
+ PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
+ PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
+ PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
+ PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
+ PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
+ PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
+ PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
+ PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
+ PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
+ PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
+ PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
+ PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
+ PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
+ PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
+ PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
+ PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
+ PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
+ PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
+ PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
+ PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
+ PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
+
+ /* IPSR7 */
+ PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
+ PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
+ PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
+ PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
+ PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
+ PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
+ PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
+ PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
+ PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
+ PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
+ PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
+ PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
+ PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
+ PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
+ PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
+ PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
+ PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
+ PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
+ PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
+ PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
+ PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
+ PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
+ PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
+ PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
+ PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
+ PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
+ PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
+ PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
+ PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
+ PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
+ PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
+ PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
+ PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
+ PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
+ PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
+ PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
+
+ /* IPSR8 */
+ PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
+ PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
+ PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
+ PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
+ PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
+ PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
+ PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
+ PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
+ PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
+ PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
+ PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
+ PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
+ PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
+ PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
+ PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
+ PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
+ PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
+ PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
+ PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
+ PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
+ PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
+ PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
+ PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
+ PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
+ PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
+ PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
+ PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
+ PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
+ PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
+ PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
+ PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
+ PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
+ PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
+ PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
+ PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
+ PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
+ PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
+ PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
+ PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
+ PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
+ PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
+ PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
+ PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
+ PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
+ PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+ PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
+ PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
+ PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
+ PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
+ PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
+ PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+ PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
+ PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
+ PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
+ PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
+ PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
+ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
+ PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
+ PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
+ PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
+ PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
+ PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
+ PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
+ PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
+ PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
+ PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
+ PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
+ PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
+ PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
+ PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
+ PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
+ PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
+ PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
+ PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
+ PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
+ PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
+ PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
+ PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
+ PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
+ PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
+ PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
+ PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
+ PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
+ PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
+ PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
+ PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
+ PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
+ PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
+ PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
+ PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
+ PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
+ PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
+ PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
+ PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
+
+ /* IPSR10 */
+ PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
+ PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
+ PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
+ PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
+ PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
+ PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
+ PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
+ PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
+ PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
+ PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
+ PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
+ PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
+ PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
+ PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
+ PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
+ PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
+ PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
+ PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
+ PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
+ PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
+ PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
+ PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
+ PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
+ PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
+ PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
+ PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
+ PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
+ PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
+ PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
+ PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
+ PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
+ PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
+ PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
+ PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
+ PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
+ PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
+ PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
+ PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
+
+ /* IPSR11 */
+ PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
+ PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
+ PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
+ PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
+ PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
+ PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
+ PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
+ PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
+ PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
+ PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
+ PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
+ PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
+ PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
+ PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
+ PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
+ PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
+ PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
+ PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
+ PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
+ PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
+ PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
+ PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
+ PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
+ PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
+ PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
+ PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
+ PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
+ PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
+ PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
+ PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
+
+ /* IPSR12 */
+ PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
+ PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
+ PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
+ PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
+ PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
+ PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
+ PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
+ PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
+ PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
+ PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
+ PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
+ PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
+ PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
+ PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
+ PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
+ PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
+ PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
+ PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
+ PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
+ PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
+ PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
+ PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
+ PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
+ PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
+ PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
+ PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
+ PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
+ PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
+ PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
+ PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
+ PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
+ PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
+ PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
+ PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
+ PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
+ PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
+
+ /* IPSR13 */
+ PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
+ PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
+ PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
+ PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
+ PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
+ PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
+ PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
+ PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
+ PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
+ PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
+ PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
+ PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
+ PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
+ PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
+ PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
+ PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
+ PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
+ PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
+ PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
+ PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
+ PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
+ PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
+ PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
+ PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
+ PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
+ PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
+ PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
+ PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
+ PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
+ PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
+ PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - Audio Clock ------------------------------------------------------------ */
+static const unsigned int audio_clka_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int audio_clka_mux[] = {
+ AUDIO_CLKA_MARK,
+};
+static const unsigned int audio_clka_b_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(3, 25),
+};
+static const unsigned int audio_clka_b_mux[] = {
+ AUDIO_CLKA_B_MARK,
+};
+static const unsigned int audio_clka_c_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int audio_clka_c_mux[] = {
+ AUDIO_CLKA_C_MARK,
+};
+static const unsigned int audio_clka_d_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int audio_clka_d_mux[] = {
+ AUDIO_CLKA_D_MARK,
+};
+static const unsigned int audio_clkb_pins[] = {
+ /* CLKB */
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clkb_mux[] = {
+ AUDIO_CLKB_MARK,
+};
+static const unsigned int audio_clkb_b_pins[] = {
+ /* CLKB */
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int audio_clkb_b_mux[] = {
+ AUDIO_CLKB_B_MARK,
+};
+static const unsigned int audio_clkb_c_pins[] = {
+ /* CLKB */
+ RCAR_GP_PIN(4, 21),
+};
+static const unsigned int audio_clkb_c_mux[] = {
+ AUDIO_CLKB_C_MARK,
+};
+static const unsigned int audio_clkc_pins[] = {
+ /* CLKC */
+ RCAR_GP_PIN(5, 22),
+};
+static const unsigned int audio_clkc_mux[] = {
+ AUDIO_CLKC_MARK,
+};
+static const unsigned int audio_clkc_b_pins[] = {
+ /* CLKC */
+ RCAR_GP_PIN(3, 29),
+};
+static const unsigned int audio_clkc_b_mux[] = {
+ AUDIO_CLKC_B_MARK,
+};
+static const unsigned int audio_clkc_c_pins[] = {
+ /* CLKC */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int audio_clkc_c_mux[] = {
+ AUDIO_CLKC_C_MARK,
+};
+static const unsigned int audio_clkout_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 23),
+};
+static const unsigned int audio_clkout_mux[] = {
+ AUDIO_CLKOUT_MARK,
+};
+static const unsigned int audio_clkout_b_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(3, 12),
+};
+static const unsigned int audio_clkout_b_mux[] = {
+ AUDIO_CLKOUT_B_MARK,
+};
+static const unsigned int audio_clkout_c_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int audio_clkout_c_mux[] = {
+ AUDIO_CLKOUT_C_MARK,
+};
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ RCAR_GP_PIN(3, 27),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ RCAR_GP_PIN(3, 28),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+ RCAR_GP_PIN(3, 17),
+
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+ RCAR_GP_PIN(3, 5),
+
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_mii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+ AVB_TX_CLK_MARK, AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_gmii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+ AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+ AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+ AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+ AVB_COL_MARK,
+};
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du0_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
+};
+static const unsigned int du0_rgb666_mux[] = {
+ DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+ DU0_DR3_MARK, DU0_DR2_MARK,
+ DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+ DU0_DG3_MARK, DU0_DG2_MARK,
+ DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+ DU0_DB3_MARK, DU0_DB2_MARK,
+};
+static const unsigned int du0_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
+};
+static const unsigned int du0_rgb888_mux[] = {
+ DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+ DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
+ DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+ DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
+ DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+ DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
+};
+static const unsigned int du0_clk0_out_pins[] = {
+ /* DOTCLKOUT0 */
+ RCAR_GP_PIN(2, 25),
+};
+static const unsigned int du0_clk0_out_mux[] = {
+ DU0_DOTCLKOUT0_MARK
+};
+static const unsigned int du0_clk1_out_pins[] = {
+ /* DOTCLKOUT1 */
+ RCAR_GP_PIN(2, 26),
+};
+static const unsigned int du0_clk1_out_mux[] = {
+ DU0_DOTCLKOUT1_MARK
+};
+static const unsigned int du0_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(2, 24),
+};
+static const unsigned int du0_clk_in_mux[] = {
+ DU0_DOTCLKIN_MARK
+};
+static const unsigned int du0_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
+};
+static const unsigned int du0_sync_mux[] = {
+ DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
+};
+static const unsigned int du0_oddf_pins[] = {
+ /* EXODDF/ODDF/DISP/CDE */
+ RCAR_GP_PIN(2, 29),
+};
+static const unsigned int du0_oddf_mux[] = {
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du0_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(2, 31),
+};
+static const unsigned int du0_cde_mux[] = {
+ DU0_CDE_MARK,
+};
+static const unsigned int du0_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(2, 30),
+};
+static const unsigned int du0_disp_mux[] = {
+ DU0_DISP_MARK
+};
+static const unsigned int du1_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int du1_rgb666_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK,
+};
+static const unsigned int du1_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
+ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int du1_rgb888_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
+};
+static const unsigned int du1_clk0_out_pins[] = {
+ /* DOTCLKOUT0 */
+ RCAR_GP_PIN(4, 25),
+};
+static const unsigned int du1_clk0_out_mux[] = {
+ DU1_DOTCLKOUT0_MARK
+};
+static const unsigned int du1_clk1_out_pins[] = {
+ /* DOTCLKOUT1 */
+ RCAR_GP_PIN(4, 26),
+};
+static const unsigned int du1_clk1_out_mux[] = {
+ DU1_DOTCLKOUT1_MARK
+};
+static const unsigned int du1_clk_in_pins[] = {
+ /* DOTCLKIN */
+ RCAR_GP_PIN(4, 24),
+};
+static const unsigned int du1_clk_in_mux[] = {
+ DU1_DOTCLKIN_MARK
+};
+static const unsigned int du1_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int du1_sync_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
+};
+static const unsigned int du1_oddf_pins[] = {
+ /* EXODDF/ODDF/DISP/CDE */
+ RCAR_GP_PIN(4, 29),
+};
+static const unsigned int du1_oddf_mux[] = {
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du1_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(4, 31),
+};
+static const unsigned int du1_cde_mux[] = {
+ DU1_CDE_MARK
+};
+static const unsigned int du1_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(4, 30),
+};
+static const unsigned int du1_disp_mux[] = {
+ DU1_DISP_MARK
+};
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+ /* LINK */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int eth_link_mux[] = {
+ ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+ /* MAGIC */
+ RCAR_GP_PIN(3, 22),
+};
+static const unsigned int eth_magic_mux[] = {
+ ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+ /* MDC, MDIO */
+ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int eth_mdio_mux[] = {
+ ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
+ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int eth_rmii_mux[] = {
+ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
+};
+static const unsigned int eth_link_b_pins[] = {
+ /* LINK */
+ RCAR_GP_PIN(5, 15),
+};
+static const unsigned int eth_link_b_mux[] = {
+ ETH_LINK_B_MARK,
+};
+static const unsigned int eth_magic_b_pins[] = {
+ /* MAGIC */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int eth_magic_b_mux[] = {
+ ETH_MAGIC_B_MARK,
+};
+static const unsigned int eth_mdio_b_pins[] = {
+ /* MDC, MDIO */
+ RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int eth_mdio_b_mux[] = {
+ ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
+};
+static const unsigned int eth_rmii_b_pins[] = {
+ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int eth_rmii_b_mux[] = {
+ ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
+ ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
+};
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 29),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCIF0_HSCK_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
+};
+static const unsigned int hscif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
+};
+static const unsigned int hscif0_data_b_mux[] = {
+ HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
+};
+static const unsigned int hscif0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int hscif0_clk_b_mux[] = {
+ HSCIF0_HSCK_B_MARK,
+};
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 10),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCIF1_HSCK_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
+};
+static const unsigned int hscif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
+};
+static const unsigned int hscif1_data_b_mux[] = {
+ HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
+};
+static const unsigned int hscif1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
+};
+static const unsigned int hscif1_ctrl_b_mux[] = {
+ HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
+};
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 10),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCIF2_HSCK_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
+};
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+};
+static const unsigned int i2c0_mux[] = {
+ I2C0_SCL_MARK, I2C0_SDA_MARK,
+};
+static const unsigned int i2c0_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
+};
+static const unsigned int i2c0_b_mux[] = {
+ I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
+};
+static const unsigned int i2c0_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int i2c0_c_mux[] = {
+ I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
+};
+static const unsigned int i2c0_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+static const unsigned int i2c0_d_mux[] = {
+ I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
+};
+static const unsigned int i2c0_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
+};
+static const unsigned int i2c0_e_mux[] = {
+ I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
+};
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int i2c1_mux[] = {
+ I2C1_SCL_MARK, I2C1_SDA_MARK,
+};
+static const unsigned int i2c1_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+};
+static const unsigned int i2c1_b_mux[] = {
+ I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
+};
+static const unsigned int i2c1_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int i2c1_c_mux[] = {
+ I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
+};
+static const unsigned int i2c1_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
+};
+static const unsigned int i2c1_d_mux[] = {
+ I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
+};
+static const unsigned int i2c1_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int i2c1_e_mux[] = {
+ I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
+};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int i2c2_mux[] = {
+ I2C2_SCL_MARK, I2C2_SDA_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int i2c2_b_mux[] = {
+ I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
+};
+static const unsigned int i2c2_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int i2c2_c_mux[] = {
+ I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
+};
+static const unsigned int i2c2_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int i2c2_d_mux[] = {
+ I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
+};
+static const unsigned int i2c2_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int i2c2_e_mux[] = {
+ I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
+};
+static const unsigned int i2c3_mux[] = {
+ I2C3_SCL_MARK, I2C3_SDA_MARK,
+};
+static const unsigned int i2c3_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int i2c3_b_mux[] = {
+ I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
+};
+static const unsigned int i2c3_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+};
+static const unsigned int i2c3_c_mux[] = {
+ I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
+};
+static const unsigned int i2c3_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int i2c3_d_mux[] = {
+ I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
+};
+static const unsigned int i2c3_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+};
+static const unsigned int i2c3_e_mux[] = {
+ I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
+};
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+};
+static const unsigned int i2c4_mux[] = {
+ I2C4_SCL_MARK, I2C4_SDA_MARK,
+};
+static const unsigned int i2c4_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
+};
+static const unsigned int i2c4_b_mux[] = {
+ I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
+};
+static const unsigned int i2c4_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int i2c4_c_mux[] = {
+ I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
+};
+static const unsigned int i2c4_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+};
+static const unsigned int i2c4_d_mux[] = {
+ I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
+};
+static const unsigned int i2c4_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
+};
+static const unsigned int i2c4_e_mux[] = {
+ I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(0, 7),
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int intc_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int intc_irq5_mux[] = {
+ IRQ5_MARK,
+};
+static const unsigned int intc_irq6_pins[] = {
+ /* IRQ6 */
+ RCAR_GP_PIN(0, 10),
+};
+static const unsigned int intc_irq6_mux[] = {
+ IRQ6_MARK,
+};
+static const unsigned int intc_irq7_pins[] = {
+ /* IRQ7 */
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int intc_irq7_mux[] = {
+ IRQ7_MARK,
+};
+static const unsigned int intc_irq8_pins[] = {
+ /* IRQ8 */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int intc_irq8_mux[] = {
+ IRQ8_MARK,
+};
+static const unsigned int intc_irq9_pins[] = {
+ /* IRQ9 */
+ RCAR_GP_PIN(5, 10),
+};
+static const unsigned int intc_irq9_mux[] = {
+ IRQ9_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc_data1_pins[] = {
+ /* D[0] */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(4, 6),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(4, 7),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(4, 2),
+};
+static const unsigned int msiof0_rx_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+static const unsigned int msiof0_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(4, 3),
+};
+static const unsigned int msiof0_tx_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 26),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 27),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 28),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 29),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 24),
+};
+static const unsigned int msiof1_rx_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+static const unsigned int msiof1_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 25),
+};
+static const unsigned int msiof1_tx_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int msiof1_clk_b_mux[] = {
+ MSIOF1_SCK_B_MARK,
+};
+static const unsigned int msiof1_sync_b_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int msiof1_sync_b_mux[] = {
+ MSIOF1_SYNC_B_MARK,
+};
+static const unsigned int msiof1_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(5, 5),
+};
+static const unsigned int msiof1_ss1_b_mux[] = {
+ MSIOF1_SS1_B_MARK,
+};
+static const unsigned int msiof1_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(5, 6),
+};
+static const unsigned int msiof1_ss2_b_mux[] = {
+ MSIOF1_SS2_B_MARK,
+};
+static const unsigned int msiof1_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(5, 1),
+};
+static const unsigned int msiof1_rx_b_mux[] = {
+ MSIOF1_RXD_B_MARK,
+};
+static const unsigned int msiof1_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int msiof1_tx_b_mux[] = {
+ MSIOF1_TXD_B_MARK,
+};
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 30),
+};
+static const unsigned int msiof2_rx_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+static const unsigned int msiof2_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 31),
+};
+static const unsigned int msiof2_tx_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int msiof2_clk_b_mux[] = {
+ MSIOF2_SCK_B_MARK,
+};
+static const unsigned int msiof2_sync_b_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int msiof2_sync_b_mux[] = {
+ MSIOF2_SYNC_B_MARK,
+};
+static const unsigned int msiof2_ss1_b_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(3, 17),
+};
+static const unsigned int msiof2_ss1_b_mux[] = {
+ MSIOF2_SS1_B_MARK,
+};
+static const unsigned int msiof2_ss2_b_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int msiof2_ss2_b_mux[] = {
+ MSIOF2_SS2_B_MARK,
+};
+static const unsigned int msiof2_rx_b_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(3, 13),
+};
+static const unsigned int msiof2_rx_b_mux[] = {
+ MSIOF2_RXD_B_MARK,
+};
+static const unsigned int msiof2_tx_b_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(3, 14),
+};
+static const unsigned int msiof2_tx_b_mux[] = {
+ MSIOF2_TXD_B_MARK,
+};
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+ SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+ MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int scif0_data_mux[] = {
+ SCIF0_RXD_MARK, SCIF0_TXD_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scif0_data_b_mux[] = {
+ SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+};
+static const unsigned int scif0_data_c_mux[] = {
+ SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
+};
+static const unsigned int scif0_data_d_mux[] = {
+ SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int scif1_data_mux[] = {
+ SCIF1_RXD_MARK, SCIF1_TXD_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 13),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCIF1_SCK_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 10),
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCIF1_SCK_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
+};
+static const unsigned int scif1_data_c_mux[] = {
+ SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
+};
+static const unsigned int scif1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif1_clk_c_mux[] = {
+ SCIF1_SCK_C_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scif2_data_mux[] = {
+ SCIF2_RXD_MARK, SCIF2_TXD_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCIF2_SCK_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+};
+static const unsigned int scif2_data_b_mux[] = {
+ SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 17),
+};
+static const unsigned int scif2_clk_b_mux[] = {
+ SCIF2_SCK_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int scif2_data_c_mux[] = {
+ SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
+};
+static const unsigned int scif2_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif2_clk_c_mux[] = {
+ SCIF2_SCK_C_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scif3_data_mux[] = {
+ SCIF3_RXD_MARK, SCIF3_TXD_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCIF3_SCK_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
+};
+static const unsigned int scif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 22),
+};
+static const unsigned int scif3_clk_b_mux[] = {
+ SCIF3_SCK_B_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif4_data_mux[] = {
+ SCIF4_RXD_MARK, SCIF4_TXD_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+static const unsigned int scif4_data_b_mux[] = {
+ SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scif4_data_c_mux[] = {
+ SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
+};
+static const unsigned int scif4_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
+};
+static const unsigned int scif4_data_d_mux[] = {
+ SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
+};
+static const unsigned int scif4_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+};
+static const unsigned int scif4_data_e_mux[] = {
+ SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int scif5_data_mux[] = {
+ SCIF5_RXD_MARK, SCIF5_TXD_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int scif5_data_b_mux[] = {
+ SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
+};
+static const unsigned int scif5_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int scif5_data_c_mux[] = {
+ SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
+};
+static const unsigned int scif5_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif5_data_d_mux[] = {
+ SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+};
+static const unsigned int scifa0_data_mux[] = {
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+ SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scifa0_data_c_mux[] = {
+ SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
+};
+static const unsigned int scifa0_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa0_data_d_mux[] = {
+ SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifa1_data_mux[] = {
+ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 13),
+};
+static const unsigned int scifa1_clk_mux[] = {
+ SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+ SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+ SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+ SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+ SCIFA1_SCK_C_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int scifa2_data_mux[] = {
+ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scifa2_clk_mux[] = {
+ SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+ SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa2_clk_b_mux[] = {
+ SCIFA2_SCK_B_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+};
+static const unsigned int scifa3_data_mux[] = {
+ SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifa3_clk_mux[] = {
+ SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int scifa3_data_b_mux[] = {
+ SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
+};
+static const unsigned int scifa3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int scifa3_clk_b_mux[] = {
+ SCIFA3_SCK_B_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int scifa4_data_mux[] = {
+ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+static const unsigned int scifa4_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa4_data_b_mux[] = {
+ SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
+};
+static const unsigned int scifa4_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+};
+static const unsigned int scifa4_data_c_mux[] = {
+ SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
+};
+static const unsigned int scifa4_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
+};
+static const unsigned int scifa4_data_d_mux[] = {
+ SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifa5_data_mux[] = {
+ SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
+};
+static const unsigned int scifa5_data_b_mux[] = {
+ SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
+};
+static const unsigned int scifa5_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
+};
+static const unsigned int scifa5_data_c_mux[] = {
+ SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
+};
+static const unsigned int scifa5_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
+};
+static const unsigned int scifa5_data_d_mux[] = {
+ SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
+};
+static const unsigned int scifb0_data_mux[] = {
+ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int scifb0_clk_mux[] = {
+ SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+ SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
+};
+static const unsigned int scifb1_data_mux[] = {
+ SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int scifb1_clk_mux[] = {
+ SCIFB1_SCK_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+};
+static const unsigned int scifb2_data_mux[] = {
+ SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scifb2_clk_mux[] = {
+ SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+ SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(3, 29),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DATA0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DATA0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SD2_DATA0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+ SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+ SD2_WP_MARK,
+};
+/* - SSI -------------------------------------------------------------------- */
+static const unsigned int ssi0_data_pins[] = {
+ /* SDATA0 */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int ssi0_data_mux[] = {
+ SSI_SDATA0_MARK,
+};
+static const unsigned int ssi0129_ctrl_pins[] = {
+ /* SCK0129, WS0129 */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int ssi0129_ctrl_mux[] = {
+ SSI_SCK0129_MARK, SSI_WS0129_MARK,
+};
+static const unsigned int ssi1_data_pins[] = {
+ /* SDATA1 */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int ssi1_data_mux[] = {
+ SSI_SDATA1_MARK,
+};
+static const unsigned int ssi1_ctrl_pins[] = {
+ /* SCK1, WS1 */
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+};
+static const unsigned int ssi1_ctrl_mux[] = {
+ SSI_SCK1_MARK, SSI_WS1_MARK,
+};
+static const unsigned int ssi1_data_b_pins[] = {
+ /* SDATA1 */
+ RCAR_GP_PIN(4, 13),
+};
+static const unsigned int ssi1_data_b_mux[] = {
+ SSI_SDATA1_B_MARK,
+};
+static const unsigned int ssi1_ctrl_b_pins[] = {
+ /* SCK1, WS1 */
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int ssi1_ctrl_b_mux[] = {
+ SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
+};
+static const unsigned int ssi2_data_pins[] = {
+ /* SDATA2 */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int ssi2_data_mux[] = {
+ SSI_SDATA2_MARK,
+};
+static const unsigned int ssi2_ctrl_pins[] = {
+ /* SCK2, WS2 */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+static const unsigned int ssi2_ctrl_mux[] = {
+ SSI_SCK2_MARK, SSI_WS2_MARK,
+};
+static const unsigned int ssi2_data_b_pins[] = {
+ /* SDATA2 */
+ RCAR_GP_PIN(4, 16),
+};
+static const unsigned int ssi2_data_b_mux[] = {
+ SSI_SDATA2_B_MARK,
+};
+static const unsigned int ssi2_ctrl_b_pins[] = {
+ /* SCK2, WS2 */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int ssi2_ctrl_b_mux[] = {
+ SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
+};
+static const unsigned int ssi3_data_pins[] = {
+ /* SDATA3 */
+ RCAR_GP_PIN(5, 6),
+};
+static const unsigned int ssi3_data_mux[] = {
+ SSI_SDATA3_MARK
+};
+static const unsigned int ssi34_ctrl_pins[] = {
+ /* SCK34, WS34 */
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int ssi34_ctrl_mux[] = {
+ SSI_SCK34_MARK, SSI_WS34_MARK,
+};
+static const unsigned int ssi4_data_pins[] = {
+ /* SDATA4 */
+ RCAR_GP_PIN(5, 9),
+};
+static const unsigned int ssi4_data_mux[] = {
+ SSI_SDATA4_MARK,
+};
+static const unsigned int ssi4_ctrl_pins[] = {
+ /* SCK4, WS4 */
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+};
+static const unsigned int ssi4_ctrl_mux[] = {
+ SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+static const unsigned int ssi4_data_b_pins[] = {
+ /* SDATA4 */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int ssi4_data_b_mux[] = {
+ SSI_SDATA4_B_MARK,
+};
+static const unsigned int ssi4_ctrl_b_pins[] = {
+ /* SCK4, WS4 */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int ssi4_ctrl_b_mux[] = {
+ SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
+};
+static const unsigned int ssi5_data_pins[] = {
+ /* SDATA5 */
+ RCAR_GP_PIN(4, 26),
+};
+static const unsigned int ssi5_data_mux[] = {
+ SSI_SDATA5_MARK,
+};
+static const unsigned int ssi5_ctrl_pins[] = {
+ /* SCK5, WS5 */
+ RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
+};
+static const unsigned int ssi5_ctrl_mux[] = {
+ SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+static const unsigned int ssi5_data_b_pins[] = {
+ /* SDATA5 */
+ RCAR_GP_PIN(3, 21),
+};
+static const unsigned int ssi5_data_b_mux[] = {
+ SSI_SDATA5_B_MARK,
+};
+static const unsigned int ssi5_ctrl_b_pins[] = {
+ /* SCK5, WS5 */
+ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
+};
+static const unsigned int ssi5_ctrl_b_mux[] = {
+ SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
+};
+static const unsigned int ssi6_data_pins[] = {
+ /* SDATA6 */
+ RCAR_GP_PIN(4, 29),
+};
+static const unsigned int ssi6_data_mux[] = {
+ SSI_SDATA6_MARK,
+};
+static const unsigned int ssi6_ctrl_pins[] = {
+ /* SCK6, WS6 */
+ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int ssi6_ctrl_mux[] = {
+ SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+static const unsigned int ssi6_data_b_pins[] = {
+ /* SDATA6 */
+ RCAR_GP_PIN(3, 24),
+};
+static const unsigned int ssi6_data_b_mux[] = {
+ SSI_SDATA6_B_MARK,
+};
+static const unsigned int ssi6_ctrl_b_pins[] = {
+ /* SCK6, WS6 */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+};
+static const unsigned int ssi6_ctrl_b_mux[] = {
+ SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
+};
+static const unsigned int ssi7_data_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int ssi7_data_mux[] = {
+ SSI_SDATA7_MARK,
+};
+static const unsigned int ssi78_ctrl_pins[] = {
+ /* SCK78, WS78 */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
+};
+static const unsigned int ssi78_ctrl_mux[] = {
+ SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+static const unsigned int ssi7_data_b_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(3, 27),
+};
+static const unsigned int ssi7_data_b_mux[] = {
+ SSI_SDATA7_B_MARK,
+};
+static const unsigned int ssi78_ctrl_b_pins[] = {
+ /* SCK78, WS78 */
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int ssi78_ctrl_b_mux[] = {
+ SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
+};
+static const unsigned int ssi8_data_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(5, 10),
+};
+static const unsigned int ssi8_data_mux[] = {
+ SSI_SDATA8_MARK,
+};
+static const unsigned int ssi8_data_b_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(3, 28),
+};
+static const unsigned int ssi8_data_b_mux[] = {
+ SSI_SDATA8_B_MARK,
+};
+static const unsigned int ssi9_data_pins[] = {
+ /* SDATA9 */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int ssi9_data_mux[] = {
+ SSI_SDATA9_MARK,
+};
+static const unsigned int ssi9_ctrl_pins[] = {
+ /* SCK9, WS9 */
+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+static const unsigned int ssi9_ctrl_mux[] = {
+ SSI_SCK9_MARK, SSI_WS9_MARK,
+};
+static const unsigned int ssi9_data_b_pins[] = {
+ /* SDATA9 */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int ssi9_data_b_mux[] = {
+ SSI_SDATA9_B_MARK,
+};
+static const unsigned int ssi9_ctrl_b_pins[] = {
+ /* SCK9, WS9 */
+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int ssi9_ctrl_b_mux[] = {
+ SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ RCAR_GP_PIN(5, 24), /* PWEN */
+ RCAR_GP_PIN(5, 25), /* OVC */
+};
+static const unsigned int usb0_mux[] = {
+ USB0_PWEN_MARK,
+ USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ RCAR_GP_PIN(5, 26), /* PWEN */
+ RCAR_GP_PIN(5, 27), /* OVC */
+};
+static const unsigned int usb1_mux[] = {
+ USB1_PWEN_MARK,
+ USB1_OVC_MARK,
+};
+/* - VIN0 ------------------------------------------------------------------- */
+static const union vin_data vin0_data_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+ /* G */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
+ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
+ /* R */
+ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
+ },
+};
+static const union vin_data vin0_data_mux = {
+ .data24 = {
+ /* B */
+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G0_MARK, VI0_G1_MARK,
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R0_MARK, VI0_R1_MARK,
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
+ },
+};
+static const unsigned int vin0_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+ /* G */
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
+ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
+ /* R */
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
+};
+static const unsigned int vin0_data18_mux[] = {
+ /* B */
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ RCAR_GP_PIN(3, 11), /* HSYNC */
+ RCAR_GP_PIN(3, 12), /* VSYNC */
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_HSYNC_N_MARK,
+ VI0_VSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const union vin_data vin1_data_pins = {
+ .data12 = {
+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ },
+};
+static const union vin_data vin1_data_mux = {
+ .data12 = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+ VI1_DATA10_MARK, VI1_DATA11_MARK,
+ },
+};
+static const unsigned int vin1_sync_pins[] = {
+ RCAR_GP_PIN(5, 22), /* HSYNC */
+ RCAR_GP_PIN(5, 23), /* VSYNC */
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_HSYNC_N_MARK,
+ VI1_VSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ RCAR_GP_PIN(5, 11),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clka),
+ SH_PFC_PIN_GROUP(audio_clka_b),
+ SH_PFC_PIN_GROUP(audio_clka_c),
+ SH_PFC_PIN_GROUP(audio_clka_d),
+ SH_PFC_PIN_GROUP(audio_clkb),
+ SH_PFC_PIN_GROUP(audio_clkb_b),
+ SH_PFC_PIN_GROUP(audio_clkb_c),
+ SH_PFC_PIN_GROUP(audio_clkc),
+ SH_PFC_PIN_GROUP(audio_clkc_b),
+ SH_PFC_PIN_GROUP(audio_clkc_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(du0_rgb666),
+ SH_PFC_PIN_GROUP(du0_rgb888),
+ SH_PFC_PIN_GROUP(du0_clk0_out),
+ SH_PFC_PIN_GROUP(du0_clk1_out),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du0_sync),
+ SH_PFC_PIN_GROUP(du0_oddf),
+ SH_PFC_PIN_GROUP(du0_cde),
+ SH_PFC_PIN_GROUP(du0_disp),
+ SH_PFC_PIN_GROUP(du1_rgb666),
+ SH_PFC_PIN_GROUP(du1_rgb888),
+ SH_PFC_PIN_GROUP(du1_clk0_out),
+ SH_PFC_PIN_GROUP(du1_clk1_out),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du1_sync),
+ SH_PFC_PIN_GROUP(du1_oddf),
+ SH_PFC_PIN_GROUP(du1_cde),
+ SH_PFC_PIN_GROUP(du1_disp),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(eth_link_b),
+ SH_PFC_PIN_GROUP(eth_magic_b),
+ SH_PFC_PIN_GROUP(eth_mdio_b),
+ SH_PFC_PIN_GROUP(eth_rmii_b),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_clk_b),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c0_b),
+ SH_PFC_PIN_GROUP(i2c0_c),
+ SH_PFC_PIN_GROUP(i2c0_d),
+ SH_PFC_PIN_GROUP(i2c0_e),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c1_d),
+ SH_PFC_PIN_GROUP(i2c1_e),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c2_e),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c3_b),
+ SH_PFC_PIN_GROUP(i2c3_c),
+ SH_PFC_PIN_GROUP(i2c3_d),
+ SH_PFC_PIN_GROUP(i2c3_e),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c4_b),
+ SH_PFC_PIN_GROUP(i2c4_c),
+ SH_PFC_PIN_GROUP(i2c4_d),
+ SH_PFC_PIN_GROUP(i2c4_e),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(intc_irq4),
+ SH_PFC_PIN_GROUP(intc_irq5),
+ SH_PFC_PIN_GROUP(intc_irq6),
+ SH_PFC_PIN_GROUP(intc_irq7),
+ SH_PFC_PIN_GROUP(intc_irq8),
+ SH_PFC_PIN_GROUP(intc_irq9),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_sync_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_rx_b),
+ SH_PFC_PIN_GROUP(msiof1_tx_b),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(msiof2_clk_b),
+ SH_PFC_PIN_GROUP(msiof2_sync_b),
+ SH_PFC_PIN_GROUP(msiof2_ss1_b),
+ SH_PFC_PIN_GROUP(msiof2_ss2_b),
+ SH_PFC_PIN_GROUP(msiof2_rx_b),
+ SH_PFC_PIN_GROUP(msiof2_tx_b),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_clk_c),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_clk_c),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif4_data_d),
+ SH_PFC_PIN_GROUP(scif4_data_e),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_data_c),
+ SH_PFC_PIN_GROUP(scif5_data_d),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data_c),
+ SH_PFC_PIN_GROUP(scifa0_data_d),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa1_clk_c),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa2_clk_b),
+ SH_PFC_PIN_GROUP(scifa3_data),
+ SH_PFC_PIN_GROUP(scifa3_clk),
+ SH_PFC_PIN_GROUP(scifa3_data_b),
+ SH_PFC_PIN_GROUP(scifa3_clk_b),
+ SH_PFC_PIN_GROUP(scifa4_data),
+ SH_PFC_PIN_GROUP(scifa4_data_b),
+ SH_PFC_PIN_GROUP(scifa4_data_c),
+ SH_PFC_PIN_GROUP(scifa4_data_d),
+ SH_PFC_PIN_GROUP(scifa5_data),
+ SH_PFC_PIN_GROUP(scifa5_data_b),
+ SH_PFC_PIN_GROUP(scifa5_data_c),
+ SH_PFC_PIN_GROUP(scifa5_data_d),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data_b),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_data_b),
+ SH_PFC_PIN_GROUP(ssi2_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data_b),
+ SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data_b),
+ SH_PFC_PIN_GROUP(ssi5_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data_b),
+ SH_PFC_PIN_GROUP(ssi6_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data_b),
+ SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_data_b),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(ssi9_data_b),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_data, 8),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+};
+
+static const char * const audio_clk_groups[] = {
+ "audio_clka",
+ "audio_clka_b",
+ "audio_clka_c",
+ "audio_clka_d",
+ "audio_clkb",
+ "audio_clkb_b",
+ "audio_clkb_c",
+ "audio_clkc",
+ "audio_clkc_b",
+ "audio_clkc_c",
+ "audio_clkout",
+ "audio_clkout_b",
+ "audio_clkout_c",
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_mii",
+ "avb_gmii",
+};
+
+static const char * const du0_groups[] = {
+ "du0_rgb666",
+ "du0_rgb888",
+ "du0_clk0_out",
+ "du0_clk1_out",
+ "du0_clk_in",
+ "du0_sync",
+ "du0_oddf",
+ "du0_cde",
+ "du0_disp",
+};
+
+static const char * const du1_groups[] = {
+ "du1_rgb666",
+ "du1_rgb888",
+ "du1_clk0_out",
+ "du1_clk1_out",
+ "du1_clk_in",
+ "du1_sync",
+ "du1_oddf",
+ "du1_cde",
+ "du1_disp",
+};
+
+static const char * const eth_groups[] = {
+ "eth_link",
+ "eth_magic",
+ "eth_mdio",
+ "eth_rmii",
+ "eth_link_b",
+ "eth_magic_b",
+ "eth_mdio_b",
+ "eth_rmii_b",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+ "hscif0_data_b",
+ "hscif0_clk_b",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+ "hscif1_data_b",
+ "hscif1_ctrl_b",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+ "i2c0_b",
+ "i2c0_c",
+ "i2c0_d",
+ "i2c0_e",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+ "i2c1_b",
+ "i2c1_c",
+ "i2c1_d",
+ "i2c1_e",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+ "i2c2_b",
+ "i2c2_c",
+ "i2c2_d",
+ "i2c2_e",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+ "i2c3_b",
+ "i2c3_c",
+ "i2c3_d",
+ "i2c3_e",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+ "i2c4_b",
+ "i2c4_c",
+ "i2c4_d",
+ "i2c4_e",
+};
+
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq1",
+ "intc_irq2",
+ "intc_irq3",
+ "intc_irq4",
+ "intc_irq5",
+ "intc_irq6",
+ "intc_irq7",
+ "intc_irq8",
+ "intc_irq9",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_rx",
+ "msiof0_tx",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_rx",
+ "msiof1_tx",
+ "msiof1_clk_b",
+ "msiof1_sync_b",
+ "msiof1_ss1_b",
+ "msiof1_ss2_b",
+ "msiof1_rx_b",
+ "msiof1_tx_b",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_rx",
+ "msiof2_tx",
+ "msiof2_clk_b",
+ "msiof2_sync_b",
+ "msiof2_ss1_b",
+ "msiof2_ss2_b",
+ "msiof2_rx_b",
+ "msiof2_tx_b",
+};
+
+static const char * const qspi_groups[] = {
+ "qspi_ctrl",
+ "qspi_data2",
+ "qspi_data4",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_data_b",
+ "scif0_data_c",
+ "scif0_data_d",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_clk",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_data_c",
+ "scif1_clk_c",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+ "scif2_data_b",
+ "scif2_clk_b",
+ "scif2_data_c",
+ "scif2_clk_c",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_data_b",
+ "scif3_clk_b",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_data_b",
+ "scif4_data_c",
+ "scif4_data_d",
+ "scif4_data_e",
+};
+
+static const char * const scif5_groups[] = {
+ "scif5_data",
+ "scif5_data_b",
+ "scif5_data_c",
+ "scif5_data_d",
+};
+
+static const char * const scifa0_groups[] = {
+ "scifa0_data",
+ "scifa0_data_b",
+ "scifa0_data_c",
+ "scifa0_data_d",
+};
+
+static const char * const scifa1_groups[] = {
+ "scifa1_data",
+ "scifa1_clk",
+ "scifa1_data_b",
+ "scifa1_clk_b",
+ "scifa1_data_c",
+ "scifa1_clk_c",
+};
+
+static const char * const scifa2_groups[] = {
+ "scifa2_data",
+ "scifa2_clk",
+ "scifa2_data_b",
+ "scifa2_clk_b",
+};
+
+static const char * const scifa3_groups[] = {
+ "scifa3_data",
+ "scifa3_clk",
+ "scifa3_data_b",
+ "scifa3_clk_b",
+};
+
+static const char * const scifa4_groups[] = {
+ "scifa4_data",
+ "scifa4_data_b",
+ "scifa4_data_c",
+ "scifa4_data_d",
+};
+
+static const char * const scifa5_groups[] = {
+ "scifa5_data",
+ "scifa5_data_b",
+ "scifa5_data_c",
+ "scifa5_data_d",
+};
+
+static const char * const scifb0_groups[] = {
+ "scifb0_data",
+ "scifb0_clk",
+ "scifb0_ctrl",
+};
+
+static const char * const scifb1_groups[] = {
+ "scifb1_data",
+ "scifb1_clk",
+};
+
+static const char * const scifb2_groups[] = {
+ "scifb2_data",
+ "scifb2_clk",
+ "scifb2_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+ "scif_clk_b",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd",
+ "sdhi2_wp",
+};
+
+static const char * const ssi_groups[] = {
+ "ssi0_data",
+ "ssi0129_ctrl",
+ "ssi1_data",
+ "ssi1_ctrl",
+ "ssi1_data_b",
+ "ssi1_ctrl_b",
+ "ssi2_data",
+ "ssi2_ctrl",
+ "ssi2_data_b",
+ "ssi2_ctrl_b",
+ "ssi3_data",
+ "ssi34_ctrl",
+ "ssi4_data",
+ "ssi4_ctrl",
+ "ssi4_data_b",
+ "ssi4_ctrl_b",
+ "ssi5_data",
+ "ssi5_ctrl",
+ "ssi5_data_b",
+ "ssi5_ctrl_b",
+ "ssi6_data",
+ "ssi6_ctrl",
+ "ssi6_data_b",
+ "ssi6_ctrl_b",
+ "ssi7_data",
+ "ssi78_ctrl",
+ "ssi7_data_b",
+ "ssi78_ctrl_b",
+ "ssi8_data",
+ "ssi8_data_b",
+ "ssi9_data",
+ "ssi9_ctrl",
+ "ssi9_data_b",
+ "ssi9_ctrl_b",
+};
+
+static const char * const usb0_groups[] = {
+ "usb0",
+};
+
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data24",
+ "vin0_data20",
+ "vin0_data18",
+ "vin0_data16",
+ "vin0_data12",
+ "vin0_data10",
+ "vin0_data8",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data12",
+ "vin1_data10",
+ "vin1_data8",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifa3),
+ SH_PFC_FUNCTION(scifa4),
+ SH_PFC_FUNCTION(scifa5),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ GP_0_31_FN, FN_IP2_17_16,
+ GP_0_30_FN, FN_IP2_15_14,
+ GP_0_29_FN, FN_IP2_13_12,
+ GP_0_28_FN, FN_IP2_11_10,
+ GP_0_27_FN, FN_IP2_9_8,
+ GP_0_26_FN, FN_IP2_7_6,
+ GP_0_25_FN, FN_IP2_5_4,
+ GP_0_24_FN, FN_IP2_3_2,
+ GP_0_23_FN, FN_IP2_1_0,
+ GP_0_22_FN, FN_IP1_31_30,
+ GP_0_21_FN, FN_IP1_29_28,
+ GP_0_20_FN, FN_IP1_27,
+ GP_0_19_FN, FN_IP1_26,
+ GP_0_18_FN, FN_A2,
+ GP_0_17_FN, FN_IP1_24,
+ GP_0_16_FN, FN_IP1_23_22,
+ GP_0_15_FN, FN_IP1_21_20,
+ GP_0_14_FN, FN_IP1_19_18,
+ GP_0_13_FN, FN_IP1_17_15,
+ GP_0_12_FN, FN_IP1_14_13,
+ GP_0_11_FN, FN_IP1_12_11,
+ GP_0_10_FN, FN_IP1_10_8,
+ GP_0_9_FN, FN_IP1_7_6,
+ GP_0_8_FN, FN_IP1_5_4,
+ GP_0_7_FN, FN_IP1_3_2,
+ GP_0_6_FN, FN_IP1_1_0,
+ GP_0_5_FN, FN_IP0_31_30,
+ GP_0_4_FN, FN_IP0_29_28,
+ GP_0_3_FN, FN_IP0_27_26,
+ GP_0_2_FN, FN_IP0_25,
+ GP_0_1_FN, FN_IP0_24,
+ GP_0_0_FN, FN_IP0_23_22, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_25_FN, FN_DACK0,
+ GP_1_24_FN, FN_IP7_31,
+ GP_1_23_FN, FN_IP4_1_0,
+ GP_1_22_FN, FN_WE1_N,
+ GP_1_21_FN, FN_WE0_N,
+ GP_1_20_FN, FN_IP3_31,
+ GP_1_19_FN, FN_IP3_30,
+ GP_1_18_FN, FN_IP3_29_27,
+ GP_1_17_FN, FN_IP3_26_24,
+ GP_1_16_FN, FN_IP3_23_21,
+ GP_1_15_FN, FN_IP3_20_18,
+ GP_1_14_FN, FN_IP3_17_15,
+ GP_1_13_FN, FN_IP3_14_13,
+ GP_1_12_FN, FN_IP3_12,
+ GP_1_11_FN, FN_IP3_11,
+ GP_1_10_FN, FN_IP3_10,
+ GP_1_9_FN, FN_IP3_9_8,
+ GP_1_8_FN, FN_IP3_7_6,
+ GP_1_7_FN, FN_IP3_5_4,
+ GP_1_6_FN, FN_IP3_3_2,
+ GP_1_5_FN, FN_IP3_1_0,
+ GP_1_4_FN, FN_IP2_31_30,
+ GP_1_3_FN, FN_IP2_29_27,
+ GP_1_2_FN, FN_IP2_26_24,
+ GP_1_1_FN, FN_IP2_23_21,
+ GP_1_0_FN, FN_IP2_20_18, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ GP_2_31_FN, FN_IP6_7_6,
+ GP_2_30_FN, FN_IP6_5_4,
+ GP_2_29_FN, FN_IP6_3_2,
+ GP_2_28_FN, FN_IP6_1_0,
+ GP_2_27_FN, FN_IP5_31_30,
+ GP_2_26_FN, FN_IP5_29_28,
+ GP_2_25_FN, FN_IP5_27_26,
+ GP_2_24_FN, FN_IP5_25_24,
+ GP_2_23_FN, FN_IP5_23_22,
+ GP_2_22_FN, FN_IP5_21_20,
+ GP_2_21_FN, FN_IP5_19_18,
+ GP_2_20_FN, FN_IP5_17_16,
+ GP_2_19_FN, FN_IP5_15_14,
+ GP_2_18_FN, FN_IP5_13_12,
+ GP_2_17_FN, FN_IP5_11_9,
+ GP_2_16_FN, FN_IP5_8_6,
+ GP_2_15_FN, FN_IP5_5_4,
+ GP_2_14_FN, FN_IP5_3_2,
+ GP_2_13_FN, FN_IP5_1_0,
+ GP_2_12_FN, FN_IP4_31_30,
+ GP_2_11_FN, FN_IP4_29_28,
+ GP_2_10_FN, FN_IP4_27_26,
+ GP_2_9_FN, FN_IP4_25_23,
+ GP_2_8_FN, FN_IP4_22_20,
+ GP_2_7_FN, FN_IP4_19_18,
+ GP_2_6_FN, FN_IP4_17_16,
+ GP_2_5_FN, FN_IP4_15_14,
+ GP_2_4_FN, FN_IP4_13_12,
+ GP_2_3_FN, FN_IP4_11_10,
+ GP_2_2_FN, FN_IP4_9_8,
+ GP_2_1_FN, FN_IP4_7_5,
+ GP_2_0_FN, FN_IP4_4_2 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ GP_3_31_FN, FN_IP8_22_20,
+ GP_3_30_FN, FN_IP8_19_17,
+ GP_3_29_FN, FN_IP8_16_15,
+ GP_3_28_FN, FN_IP8_14_12,
+ GP_3_27_FN, FN_IP8_11_9,
+ GP_3_26_FN, FN_IP8_8_6,
+ GP_3_25_FN, FN_IP8_5_3,
+ GP_3_24_FN, FN_IP8_2_0,
+ GP_3_23_FN, FN_IP7_29_27,
+ GP_3_22_FN, FN_IP7_26_24,
+ GP_3_21_FN, FN_IP7_23_21,
+ GP_3_20_FN, FN_IP7_20_18,
+ GP_3_19_FN, FN_IP7_17_15,
+ GP_3_18_FN, FN_IP7_14_12,
+ GP_3_17_FN, FN_IP7_11_9,
+ GP_3_16_FN, FN_IP7_8_6,
+ GP_3_15_FN, FN_IP7_5_3,
+ GP_3_14_FN, FN_IP7_2_0,
+ GP_3_13_FN, FN_IP6_31_29,
+ GP_3_12_FN, FN_IP6_28_26,
+ GP_3_11_FN, FN_IP6_25_23,
+ GP_3_10_FN, FN_IP6_22_20,
+ GP_3_9_FN, FN_IP6_19_17,
+ GP_3_8_FN, FN_IP6_16,
+ GP_3_7_FN, FN_IP6_15,
+ GP_3_6_FN, FN_IP6_14,
+ GP_3_5_FN, FN_IP6_13,
+ GP_3_4_FN, FN_IP6_12,
+ GP_3_3_FN, FN_IP6_11,
+ GP_3_2_FN, FN_IP6_10,
+ GP_3_1_FN, FN_IP6_9,
+ GP_3_0_FN, FN_IP6_8 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ GP_4_31_FN, FN_IP11_17_16,
+ GP_4_30_FN, FN_IP11_15_14,
+ GP_4_29_FN, FN_IP11_13_11,
+ GP_4_28_FN, FN_IP11_10_8,
+ GP_4_27_FN, FN_IP11_7_6,
+ GP_4_26_FN, FN_IP11_5_3,
+ GP_4_25_FN, FN_IP11_2_0,
+ GP_4_24_FN, FN_IP10_31_30,
+ GP_4_23_FN, FN_IP10_29_27,
+ GP_4_22_FN, FN_IP10_26_24,
+ GP_4_21_FN, FN_IP10_23_21,
+ GP_4_20_FN, FN_IP10_20_18,
+ GP_4_19_FN, FN_IP10_17_15,
+ GP_4_18_FN, FN_IP10_14_12,
+ GP_4_17_FN, FN_IP10_11_9,
+ GP_4_16_FN, FN_IP10_8_6,
+ GP_4_15_FN, FN_IP10_5_3,
+ GP_4_14_FN, FN_IP10_2_0,
+ GP_4_13_FN, FN_IP9_30_28,
+ GP_4_12_FN, FN_IP9_27_25,
+ GP_4_11_FN, FN_IP9_24_22,
+ GP_4_10_FN, FN_IP9_21_19,
+ GP_4_9_FN, FN_IP9_18_17,
+ GP_4_8_FN, FN_IP9_16_15,
+ GP_4_7_FN, FN_IP9_14_12,
+ GP_4_6_FN, FN_IP9_11_9,
+ GP_4_5_FN, FN_IP9_8_6,
+ GP_4_4_FN, FN_IP9_5_3,
+ GP_4_3_FN, FN_IP9_2_0,
+ GP_4_2_FN, FN_IP8_31_29,
+ GP_4_1_FN, FN_IP8_28_26,
+ GP_4_0_FN, FN_IP8_25_23 }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_27_FN, FN_USB1_OVC,
+ GP_5_26_FN, FN_USB1_PWEN,
+ GP_5_25_FN, FN_USB0_OVC,
+ GP_5_24_FN, FN_USB0_PWEN,
+ GP_5_23_FN, FN_IP13_26_24,
+ GP_5_22_FN, FN_IP13_23_21,
+ GP_5_21_FN, FN_IP13_20_18,
+ GP_5_20_FN, FN_IP13_17_15,
+ GP_5_19_FN, FN_IP13_14_12,
+ GP_5_18_FN, FN_IP13_11_9,
+ GP_5_17_FN, FN_IP13_8_6,
+ GP_5_16_FN, FN_IP13_5_3,
+ GP_5_15_FN, FN_IP13_2_0,
+ GP_5_14_FN, FN_IP12_29_27,
+ GP_5_13_FN, FN_IP12_26_24,
+ GP_5_12_FN, FN_IP12_23_21,
+ GP_5_11_FN, FN_IP12_20_18,
+ GP_5_10_FN, FN_IP12_17_15,
+ GP_5_9_FN, FN_IP12_14_13,
+ GP_5_8_FN, FN_IP12_12_11,
+ GP_5_7_FN, FN_IP12_10_9,
+ GP_5_6_FN, FN_IP12_8_6,
+ GP_5_5_FN, FN_IP12_5_3,
+ GP_5_4_FN, FN_IP12_2_0,
+ GP_5_3_FN, FN_IP11_29_27,
+ GP_5_2_FN, FN_IP11_26_24,
+ GP_5_1_FN, FN_IP11_23_21,
+ GP_5_0_FN, FN_IP11_20_18 }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_25_FN, FN_IP0_21_20,
+ GP_6_24_FN, FN_IP0_19_18,
+ GP_6_23_FN, FN_IP0_17,
+ GP_6_22_FN, FN_IP0_16,
+ GP_6_21_FN, FN_IP0_15,
+ GP_6_20_FN, FN_IP0_14,
+ GP_6_19_FN, FN_IP0_13,
+ GP_6_18_FN, FN_IP0_12,
+ GP_6_17_FN, FN_IP0_11,
+ GP_6_16_FN, FN_IP0_10,
+ GP_6_15_FN, FN_IP0_9_8,
+ GP_6_14_FN, FN_IP0_0,
+ GP_6_13_FN, FN_SD1_DATA3,
+ GP_6_12_FN, FN_SD1_DATA2,
+ GP_6_11_FN, FN_SD1_DATA1,
+ GP_6_10_FN, FN_SD1_DATA0,
+ GP_6_9_FN, FN_SD1_CMD,
+ GP_6_8_FN, FN_SD1_CLK,
+ GP_6_7_FN, FN_SD0_WP,
+ GP_6_6_FN, FN_SD0_CD,
+ GP_6_5_FN, FN_SD0_DATA3,
+ GP_6_4_FN, FN_SD0_DATA2,
+ GP_6_3_FN, FN_SD0_DATA1,
+ GP_6_2_FN, FN_SD0_DATA0,
+ GP_6_1_FN, FN_SD0_CMD,
+ GP_6_0_FN, FN_SD0_CLK }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+ 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP0_31_30 [2] */
+ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
+ /* IP0_29_28 [2] */
+ FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
+ /* IP0_27_26 [2] */
+ FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
+ /* IP0_25 [1] */
+ FN_D2, FN_SCIFA3_TXD_B,
+ /* IP0_24 [1] */
+ FN_D1, FN_SCIFA3_RXD_B,
+ /* IP0_23_22 [2] */
+ FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
+ /* IP0_21_20 [2] */
+ FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
+ /* IP0_19_18 [2] */
+ FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
+ /* IP0_17 [1] */
+ FN_MMC_D5, FN_SD2_WP,
+ /* IP0_16 [1] */
+ FN_MMC_D4, FN_SD2_CD,
+ /* IP0_15 [1] */
+ FN_MMC_D3, FN_SD2_DATA3,
+ /* IP0_14 [1] */
+ FN_MMC_D2, FN_SD2_DATA2,
+ /* IP0_13 [1] */
+ FN_MMC_D1, FN_SD2_DATA1,
+ /* IP0_12 [1] */
+ FN_MMC_D0, FN_SD2_DATA0,
+ /* IP0_11 [1] */
+ FN_MMC_CMD, FN_SD2_CMD,
+ /* IP0_10 [1] */
+ FN_MMC_CLK, FN_SD2_CLK,
+ /* IP0_9_8 [2] */
+ FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
+ /* IP0_7 [1] */
+ 0, 0,
+ /* IP0_6 [1] */
+ 0, 0,
+ /* IP0_5 [1] */
+ 0, 0,
+ /* IP0_4 [1] */
+ 0, 0,
+ /* IP0_3 [1] */
+ 0, 0,
+ /* IP0_2 [1] */
+ 0, 0,
+ /* IP0_1 [1] */
+ 0, 0,
+ /* IP0_0 [1] */
+ FN_SD1_CD, FN_CAN0_RX, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+ 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
+ 2, 2) {
+ /* IP1_31_30 [2] */
+ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
+ /* IP1_29_28 [2] */
+ FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
+ /* IP1_27 [1] */
+ FN_A4, FN_SCIFB0_TXD,
+ /* IP1_26 [1] */
+ FN_A3, FN_SCIFB0_SCK,
+ /* IP1_25 [1] */
+ 0, 0,
+ /* IP1_24 [1] */
+ FN_A1, FN_SCIFB1_TXD,
+ /* IP1_23_22 [2] */
+ FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
+ /* IP1_21_20 [2] */
+ FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
+ /* IP1_19_18 [2] */
+ FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
+ /* IP1_17_15 [3] */
+ FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
+ 0, 0, 0,
+ /* IP1_14_13 [2] */
+ FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
+ /* IP1_12_11 [2] */
+ FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
+ /* IP1_10_8 [3] */
+ FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
+ 0, 0, 0,
+ /* IP1_7_6 [2] */
+ FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
+ /* IP1_5_4 [2] */
+ FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
+ /* IP1_3_2 [2] */
+ FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
+ /* IP1_1_0 [2] */
+ FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+ 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
+ /* IP2_31_30 [2] */
+ FN_A20, FN_SPCLK, 0, 0,
+ /* IP2_29_27 [3] */
+ FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
+ 0, 0, 0, 0,
+ /* IP2_26_24 [3] */
+ FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
+ 0, 0, 0, 0,
+ /* IP2_23_21 [3] */
+ FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
+ 0, 0, 0, 0,
+ /* IP2_20_18 [3] */
+ FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
+ 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
+ /* IP2_17_16 [2] */
+ FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
+ /* IP2_15_14 [2] */
+ FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
+ /* IP2_13_12 [2] */
+ FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
+ /* IP2_11_10 [2] */
+ FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
+ /* IP2_9_8 [2] */
+ FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
+ /* IP2_7_6 [2] */
+ FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
+ /* IP2_5_4 [2] */
+ FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
+ /* IP2_3_2 [2] */
+ FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
+ /* IP2_1_0 [2] */
+ FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+ 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
+ /* IP3_31 [1] */
+ FN_RD_WR_N, FN_ATAG1_N,
+ /* IP3_30 [1] */
+ FN_RD_N, FN_ATACS11_N,
+ /* IP3_29_27 [3] */
+ FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
+ 0, 0, 0,
+ /* IP3_26_24 [3] */
+ FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
+ 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
+ /* IP3_23_21 [3] */
+ FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
+ 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
+ /* IP3_20_18 [3] */
+ FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
+ 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
+ /* IP3_17_15 [3] */
+ FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
+ 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
+ /* IP3_14_13 [2] */
+ FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
+ /* IP3_12 [1] */
+ FN_EX_CS0_N, FN_VI1_DATA10,
+ /* IP3_11 [1] */
+ FN_CS1_N_A26, FN_VI1_DATA9,
+ /* IP3_10 [1] */
+ FN_CS0_N, FN_VI1_DATA8,
+ /* IP3_9_8 [2] */
+ FN_A25, FN_SSL, FN_ATARD1_N, 0,
+ /* IP3_7_6 [2] */
+ FN_A24, FN_IO3, FN_EX_WAIT2, 0,
+ /* IP3_5_4 [2] */
+ FN_A23, FN_IO2, 0, FN_ATAWR1_N,
+ /* IP3_3_2 [2] */
+ FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
+ /* IP3_1_0 [2] */
+ FN_A21, FN_MOSI_IO0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+ 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
+ /* IP4_31_30 [2] */
+ FN_DU0_DG4, FN_LCDOUT12, 0, 0,
+ /* IP4_29_28 [2] */
+ FN_DU0_DG3, FN_LCDOUT11, 0, 0,
+ /* IP4_27_26 [2] */
+ FN_DU0_DG2, FN_LCDOUT10, 0, 0,
+ /* IP4_25_23 [3] */
+ FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
+ 0, 0, 0, 0,
+ /* IP4_22_20 [3] */
+ FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
+ 0, 0, 0, 0,
+ /* IP4_19_18 [2] */
+ FN_DU0_DR7, FN_LCDOUT23, 0, 0,
+ /* IP4_17_16 [2] */
+ FN_DU0_DR6, FN_LCDOUT22, 0, 0,
+ /* IP4_15_14 [2] */
+ FN_DU0_DR5, FN_LCDOUT21, 0, 0,
+ /* IP4_13_12 [2] */
+ FN_DU0_DR4, FN_LCDOUT20, 0, 0,
+ /* IP4_11_10 [2] */
+ FN_DU0_DR3, FN_LCDOUT19, 0, 0,
+ /* IP4_9_8 [2] */
+ FN_DU0_DR2, FN_LCDOUT18, 0, 0,
+ /* IP4_7_5 [3] */
+ FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
+ 0, 0, 0, 0,
+ /* IP4_4_2 [3] */
+ FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
+ 0, 0, 0, 0,
+ /* IP4_1_0 [2] */
+ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
+ /* IP5_31_30 [2] */
+ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
+ /* IP5_29_28 [2] */
+ FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
+ /* IP5_27_26 [2] */
+ FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
+ /* IP5_25_24 [2] */
+ FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
+ /* IP5_23_22 [2] */
+ FN_DU0_DB7, FN_LCDOUT7, 0, 0,
+ /* IP5_21_20 [2] */
+ FN_DU0_DB6, FN_LCDOUT6, 0, 0,
+ /* IP5_19_18 [2] */
+ FN_DU0_DB5, FN_LCDOUT5, 0, 0,
+ /* IP5_17_16 [2] */
+ FN_DU0_DB4, FN_LCDOUT4, 0, 0,
+ /* IP5_15_14 [2] */
+ FN_DU0_DB3, FN_LCDOUT3, 0, 0,
+ /* IP5_13_12 [2] */
+ FN_DU0_DB2, FN_LCDOUT2, 0, 0,
+ /* IP5_11_9 [3] */
+ FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
+ FN_CAN0_TX_C, 0, 0, 0,
+ /* IP5_8_6 [3] */
+ FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
+ FN_CAN0_RX_C, 0, 0, 0,
+ /* IP5_5_4 [2] */
+ FN_DU0_DG7, FN_LCDOUT15, 0, 0,
+ /* IP5_3_2 [2] */
+ FN_DU0_DG6, FN_LCDOUT14, 0, 0,
+ /* IP5_1_0 [2] */
+ FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+ 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+ 2, 2) {
+ /* IP6_31_29 [3] */
+ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
+ FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
+ /* IP6_28_26 [3] */
+ FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
+ FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
+ /* IP6_25_23 [3] */
+ FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
+ FN_AVB_COL, 0, 0, 0,
+ /* IP6_22_20 [3] */
+ FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
+ FN_AVB_RX_ER, 0, 0, 0,
+ /* IP6_19_17 [3] */
+ FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
+ FN_AVB_RXD7, 0, 0, 0,
+ /* IP6_16 [1] */
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+ /* IP6_15 [1] */
+ FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
+ /* IP6_14 [1] */
+ FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
+ /* IP6_13 [1] */
+ FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
+ /* IP6_12 [1] */
+ FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
+ /* IP6_11 [1] */
+ FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
+ /* IP6_10 [1] */
+ FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
+ /* IP6_9 [1] */
+ FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
+ /* IP6_8 [1] */
+ FN_VI0_CLK, FN_AVB_RX_CLK,
+ /* IP6_7_6 [2] */
+ FN_DU0_CDE, FN_QPOLB, 0, 0,
+ /* IP6_5_4 [2] */
+ FN_DU0_DISP, FN_QPOLA, 0, 0,
+ /* IP6_3_2 [2] */
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
+ 0,
+ /* IP6_1_0 [2] */
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+ 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP7_31 [1] */
+ FN_DREQ0_N, FN_SCIFB1_RXD,
+ /* IP7_30 [1] */
+ 0, 0,
+ /* IP7_29_27 [3] */
+ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
+ FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
+ /* IP7_26_24 [3] */
+ FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
+ FN_SSI_SCK6_B, 0, 0, 0,
+ /* IP7_23_21 [3] */
+ FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
+ FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
+ /* IP7_20_18 [3] */
+ FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
+ FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
+ /* IP7_17_15 [3] */
+ FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
+ FN_SSI_SCK5_B, 0, 0, 0,
+ /* IP7_14_12 [3] */
+ FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+ FN_AVB_TXD4, FN_ADICHS2, 0, 0,
+ /* IP7_11_9 [3] */
+ FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
+ FN_AVB_TXD3, FN_ADICHS1, 0, 0,
+ /* IP7_8_6 [3] */
+ FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
+ FN_AVB_TXD2, FN_ADICHS0, 0, 0,
+ /* IP7_5_3 [3] */
+ FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
+ FN_AVB_TXD1, FN_ADICLK, 0, 0,
+ /* IP7_2_0 [3] */
+ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
+ FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
+ /* IP8_31_29 [3] */
+ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+ 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
+ /* IP8_28_26 [3] */
+ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+ 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
+ /* IP8_25_23 [3] */
+ FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
+ 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
+ /* IP8_22_20 [3] */
+ FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
+ FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
+ /* IP8_19_17 [3] */
+ FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
+ FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
+ /* IP8_16_15 [2] */
+ FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+ /* IP8_14_12 [3] */
+ FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
+ FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
+ /* IP8_11_9 [3] */
+ FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+ FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
+ /* IP8_8_6 [3] */
+ FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
+ FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
+ /* IP8_5_3 [3] */
+ FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
+ FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
+ /* IP8_2_0 [3] */
+ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
+ FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+ 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
+ /* IP9_31 [1] */
+ 0, 0,
+ /* IP9_30_28 [3] */
+ FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
+ FN_SSI_SDATA1_B, 0, 0, 0,
+ /* IP9_27_25 [3] */
+ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
+ FN_SSI_WS1_B, 0, 0, 0,
+ /* IP9_24_22 [3] */
+ FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
+ FN_SSI_SCK1_B, 0, 0, 0,
+ /* IP9_21_19 [3] */
+ FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
+ FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
+ /* IP9_18_17 [2] */
+ FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
+ /* IP9_16_15 [2] */
+ FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
+ /* IP9_14_12 [3] */
+ FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
+ 0, FN_FMIN_B, 0, 0,
+ /* IP9_11_9 [3] */
+ FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
+ 0, FN_FMCLK_B, 0, 0,
+ /* IP9_8_6 [3] */
+ FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
+ 0, FN_BPFCLK_B, 0, 0,
+ /* IP9_5_3 [3] */
+ FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
+ 0, FN_TPUTO1_C, 0, 0,
+ /* IP9_2_0 [3] */
+ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
+ 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+ 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP10_31_30 [2] */
+ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
+ /* IP10_29_27 [3] */
+ FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+ 0, 0, 0, 0,
+ /* IP10_26_24 [3] */
+ FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
+ FN_SSI_SDATA4_B, 0, 0, 0,
+ /* IP10_23_21 [3] */
+ FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
+ FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
+ /* IP10_20_18 [3] */
+ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
+ FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
+ /* IP10_17_15 [3] */
+ FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
+ FN_SSI_SDATA9_B, 0, 0, 0,
+ /* IP10_14_12 [3] */
+ FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
+ 0, 0, 0, 0,
+ /* IP10_11_9 [3] */
+ FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
+ 0, 0, 0, 0,
+ /* IP10_8_6 [3] */
+ FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
+ 0, 0, 0, 0,
+ /* IP10_5_3 [3] */
+ FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
+ 0, 0, 0, 0,
+ /* IP10_2_0 [3] */
+ FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
+ 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
+ /* IP11_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP11_29_27 [3] */
+ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
+ 0, 0, 0, 0,
+ /* IP11_26_24 [3] */
+ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
+ 0, 0, 0, 0,
+ /* IP11_23_21 [3] */
+ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+ 0, 0, 0, 0,
+ /* IP11_20_18 [3] */
+ FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
+ FN_CAN_CLK_D, 0, 0, 0,
+ /* IP11_17_16 [2] */
+ FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
+ /* IP11_15_14 [2] */
+ FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
+ /* IP11_13_11 [3] */
+ FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
+ /* IP11_10_8 [3] */
+ FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
+ FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
+ /* IP11_7_6 [2] */
+ FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
+ /* IP11_5_3 [3] */
+ FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+ 0, 0, 0, 0,
+ /* IP11_2_0 [3] */
+ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+ 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+ 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
+ /* IP12_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP12_29_27 [3] */
+ FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
+ FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
+ /* IP12_26_24 [3] */
+ FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
+ FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
+ /* IP12_23_21 [3] */
+ FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
+ FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
+ /* IP12_20_18 [3] */
+ FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
+ FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
+ /* IP12_17_15 [3] */
+ FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
+ FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
+ /* IP12_14_13 [2] */
+ FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
+ /* IP12_12_11 [2] */
+ FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
+ /* IP12_10_9 [2] */
+ FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
+ /* IP12_8_6 [3] */
+ FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
+ FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
+ /* IP12_5_3 [3] */
+ FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
+ FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
+ /* IP12_2_0 [3] */
+ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
+ 0, FN_DREQ1_N_B, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+ 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP13_31 [1] */
+ 0, 0,
+ /* IP13_30 [1] */
+ 0, 0,
+ /* IP13_29 [1] */
+ 0, 0,
+ /* IP13_28 [1] */
+ 0, 0,
+ /* IP13_27 [1] */
+ 0, 0,
+ /* IP13_26_24 [3] */
+ FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
+ FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
+ /* IP13_23_21 [3] */
+ FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
+ FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
+ /* IP13_20_18 [3] */
+ FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
+ FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
+ /* IP13_17_15 [3] */
+ FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
+ FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
+ /* IP13_14_12 [3] */
+ FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
+ FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
+ /* IP13_11_9 [3] */
+ FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
+ FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
+ /* IP13_8_6 [3] */
+ FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
+ 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
+ /* IP13_5_3 [2] */
+ FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
+ FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
+ /* IP13_2_0 [3] */
+ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
+ 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
+ 2, 1) {
+ /* SEL_ADG [2] */
+ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_CAN [2] */
+ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+ /* SEL_DARC [3] */
+ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
+ FN_SEL_DARC_4, 0, 0, 0,
+ /* RESERVED [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* SEL_ETH [1] */
+ FN_SEL_ETH_0, FN_SEL_ETH_1,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_IC200 [3] */
+ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+ FN_SEL_I2C00_4, 0, 0, 0,
+ /* SEL_I2C01 [3] */
+ FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+ FN_SEL_I2C01_4, 0, 0, 0,
+ /* SEL_I2C02 [3] */
+ FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+ FN_SEL_I2C02_4, 0, 0, 0,
+ /* SEL_I2C03 [3] */
+ FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+ FN_SEL_I2C03_4, 0, 0, 0,
+ /* SEL_I2C04 [3] */
+ FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+ FN_SEL_I2C04_4, 0, 0, 0,
+ /* SEL_I2C05 [2] */
+ FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
+ /* RESERVED [1] */
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
+ 2, 2, 2, 1, 1, 2) {
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+ /* SEL_IIC0 [2] */
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
+ /* SEL_LBS [1] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1,
+ /* SEL_MSI1 [1] */
+ FN_SEL_MSI1_0, FN_SEL_MSI1_1,
+ /* SEL_MSI2 [1] */
+ FN_SEL_MSI2_0, FN_SEL_MSI2_1,
+ /* SEL_RAD [1] */
+ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ /* SEL_RCN [1] */
+ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* SEL_RSP [1] */
+ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ /* SEL_SCIFA0 [2] */
+ FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
+ FN_SEL_SCIFA0_3,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+ /* SEL_SCIFA2 [1] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ /* SEL_SCIFA3 [1] */
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+ /* SEL_SCIFA4 [2] */
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+ FN_SEL_SCIFA4_3,
+ /* SEL_SCIFA5 [2] */
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+ FN_SEL_SCIFA5_3,
+ /* RESERVED [1] */
+ 0, 0,
+ /* SEL_TMU [1] */
+ FN_SEL_TMU_0, FN_SEL_TMU_1,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_CAN0 [2] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ /* SEL_CAN1 [2] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ /* SEL_HSCIF0 [1] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+ /* SEL_HSCIF1 [1] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ /* RESERVED [2] */
+ 0, 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* SEL_SCIF0 [2] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ /* SEL_SCIF1 [2] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
+ /* SEL_SCIF2 [2] */
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
+ /* SEL_SCIF3 [1] */
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+ /* SEL_SCIF4 [3] */
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+ FN_SEL_SCIF4_4, 0, 0, 0,
+ /* SEL_SCIF5 [2] */
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+ /* SEL_SSI1 [1] */
+ FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+ /* SEL_SSI2 [1] */
+ FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+ /* SEL_SSI4 [1] */
+ FN_SEL_SSI4_0, FN_SEL_SSI4_1,
+ /* SEL_SSI5 [1] */
+ FN_SEL_SSI5_0, FN_SEL_SSI5_1,
+ /* SEL_SSI6 [1] */
+ FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+ /* SEL_SSI7 [1] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+ /* SEL_SSI8 [1] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+ /* SEL_SSI9 [1] */
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0,
+ /* RESERVED [1] */
+ 0, 0, }
+ },
+ { },
+};
+
+static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ *pocctrl = 0xe606006c;
+
+ switch (pin & 0x1f) {
+ case 6: return 23;
+ case 7: return 16;
+ case 14: return 15;
+ case 15: return 8;
+ case 0 ... 5:
+ case 8 ... 13:
+ return 22 - (pin & 0x1f);
+ case 16 ... 23:
+ return 47 - (pin & 0x1f);
+ }
+
+ return -EINVAL;
+}
+
+static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
+ .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
+};
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7745
+const struct sh_pfc_soc_info r8a7745_pinmux_info = {
+ .name = "r8a77450_pfc",
+ .ops = &r8a7794_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7794
+const struct sh_pfc_soc_info r8a7794_pinmux_info = {
+ .name = "r8a77940_pfc",
+ .ops = &r8a7794_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
DECLARE_GLOBAL_DATA_PTR;
enum sh_pfc_model {
- SH_PFC_R8A7795 = 0,
+ SH_PFC_R8A7790 = 0,
+ SH_PFC_R8A7791,
+ SH_PFC_R8A7792,
+ SH_PFC_R8A7793,
+ SH_PFC_R8A7794,
+ SH_PFC_R8A7795,
SH_PFC_R8A7796,
SH_PFC_R8A77970,
SH_PFC_R8A77995,
if (!priv->pfc.regs)
return -ENOMEM;
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+ if (model == SH_PFC_R8A7790)
+ priv->pfc.info = &r8a7790_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7791
+ if (model == SH_PFC_R8A7791)
+ priv->pfc.info = &r8a7791_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7792
+ if (model == SH_PFC_R8A7792)
+ priv->pfc.info = &r8a7792_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7793
+ if (model == SH_PFC_R8A7793)
+ priv->pfc.info = &r8a7793_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7794
+ if (model == SH_PFC_R8A7794)
+ priv->pfc.info = &r8a7794_pinmux_info;
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7795
if (model == SH_PFC_R8A7795)
priv->pfc.info = &r8a7795_pinmux_info;
}
static const struct udevice_id sh_pfc_pinctrl_ids[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+ {
+ .compatible = "renesas,pfc-r8a7790",
+ .data = SH_PFC_R8A7790,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7791
+ {
+ .compatible = "renesas,pfc-r8a7791",
+ .data = SH_PFC_R8A7791,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7792
+ {
+ .compatible = "renesas,pfc-r8a7792",
+ .data = SH_PFC_R8A7792,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7793
+ {
+ .compatible = "renesas,pfc-r8a7793",
+ .data = SH_PFC_R8A7793,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7794
+ {
+ .compatible = "renesas,pfc-r8a7794",
+ .data = SH_PFC_R8A7794,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7795
{
.compatible = "renesas,pfc-r8a7795",
unsigned int num, unsigned int pin);
int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
DECLARE_GLOBAL_DATA_PTR;
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A7_SHIFT = 14,
+ GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
+ GPIO0A7_GPIO = 0,
+ GPIO0A7_I2C3_SDA,
+ GPIO0A7_HDMI_DDCSDA,
+
+ GPIO0A6_SHIFT = 12,
+ GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
+ GPIO0A6_GPIO = 0,
+ GPIO0A6_I2C3_SCL,
+ GPIO0A6_HDMI_DDCSCL,
+
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+ GPIO0A3_SDIO_CMD,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B7_SHIFT = 14,
+ GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
+ GPIO0B7_GPIO = 0,
+ GPIO0B7_HDMI_HDP,
+
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_I2S_SDI,
+ GPIO0B6_SPI_CSN0,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_I2S_SDO,
+ GPIO0B5_SPI_RXD,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_I2S1_LRCKRX,
+ GPIO0B3_SPI_TXD,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_I2S_SCLK,
+ GPIO0B1_SPI_CLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_I2S_MCLK,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_HDMI_CECSDA,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_UART0_RSTN,
+ GPIO0C1_CLK_OUT1,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SDIO_PWREN,
+ GPIO0D6_PWM11,
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_PWM2,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM1,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A7_SHIFT = 14,
+ GPIO1A7_MASK = 1,
+ GPIO1A7_GPIO = 0,
+ GPIO1A7_SDMMC_WRPRT,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SDMMC_CMD,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SDMMC_PWREN,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_SPI_CSN1,
+ GPIO1B4_PWM12,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_UART1_RSTN,
+ GPIO1B3_PWM13,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART1_SIN,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_SHIFT = 14,
+ GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_NAND_CS3,
+ GPIO1C7_EMMC_RSTNOUT,
+
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_NAND_CS2,
+ GPIO1C6_EMMC_CMD,
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_SDMMC_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_SDMMC_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_SDMMC_D1,
+ GPIO1C3_UART2_SIN,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_SDMMC_D0,
+ GPIO1C2_UART2_SOUT,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_SDMMC_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_SDMMC_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_NAND_DQS,
+ GPIO2A7_EMMC_CLKOUT,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_NAND_WP,
+ GPIO2A5_EMMC_PWREN,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SPI1_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SPI1_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_SPI1_TXD,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI1_RXD,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_GMAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_GMAC_CLK,
+ GPIO2B6_MAC_LINK,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_GMAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_GMAC_MDIO,
+
+ GPIO2B3_SHIFT = 6,
+ GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO = 0,
+ GPIO2B3_GMAC_RXCLK,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_GMAC_CRS,
+
+ GPIO2B1_SHIFT = 2,
+ GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO = 0,
+ GPIO2B1_GMAC_TXCLK,
+
+ GPIO2B0_SHIFT = 0,
+ GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO = 0,
+ GPIO2B0_GMAC_RXDV,
+ GPIO2B0_MAC_SPEED_IOUT,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C7_SHIFT = 14,
+ GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_GMAC_TXD3,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_GMAC_TXD2,
+
+ GPIO2C5_SHIFT = 10,
+ GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL,
+ GPIO2C5_GMAC_RXD2,
+
+ GPIO2C4_SHIFT = 8,
+ GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA,
+ GPIO2C4_GMAC_RXD3,
+
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_GMAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_GMAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_GMAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_GMAC_MDC,
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = 3,
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_GMAC_COL,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_DRV_VBUS1,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_PWM10,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_DRV_VBUS,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_PWM3,
+};
+
+/* GRF_CON_IOMUX */
+enum {
+ CON_IOMUX_GMACSEL_SHIFT = 15,
+ CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
+ CON_IOMUX_GMACSEL_1 = 1,
+ CON_IOMUX_UART1SEL_SHIFT = 11,
+ CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
+ CON_IOMUX_UART2SEL_SHIFT = 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ CON_IOMUX_EMMCSEL_SHIFT = 7,
+ CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
+ CON_IOMUX_PWM3SEL_SHIFT = 3,
+ CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
+ CON_IOMUX_PWM2SEL_SHIFT = 2,
+ CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
+ CON_IOMUX_PWM1SEL_SHIFT = 1,
+ CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
+ CON_IOMUX_PWM0SEL_SHIFT = 0,
+ CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
+};
+
+/* GRF_GPIO2B_E */
+enum {
+ GRF_GPIO2B0_E_SHIFT = 0,
+ GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
+ GRF_GPIO2B1_E_SHIFT = 2,
+ GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
+ GRF_GPIO2B3_E_SHIFT = 6,
+ GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
+ GRF_GPIO2B4_E_SHIFT = 8,
+ GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
+ GRF_GPIO2B5_E_SHIFT = 10,
+ GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
+ GRF_GPIO2B6_E_SHIFT = 12,
+ GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
+};
+
+/* GRF_GPIO2C_E */
+enum {
+ GRF_GPIO2C0_E_SHIFT = 0,
+ GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
+ GRF_GPIO2C1_E_SHIFT = 2,
+ GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
+ GRF_GPIO2C2_E_SHIFT = 4,
+ GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
+ GRF_GPIO2C3_E_SHIFT = 6,
+ GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
+ GRF_GPIO2C4_E_SHIFT = 8,
+ GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
+ GRF_GPIO2C5_E_SHIFT = 10,
+ GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
+ GRF_GPIO2C6_E_SHIFT = 12,
+ GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
+ GRF_GPIO2C7_E_SHIFT = 14,
+ GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
+};
+
+/* GRF_GPIO2D_E */
+enum {
+ GRF_GPIO2D1_E_SHIFT = 2,
+ GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
+};
+
struct rk322x_pinctrl_priv {
struct rk322x_grf *grf;
};
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii pins mux */
+ rk_clrsetreg(&grf->gpio2b_iomux,
+ GPIO2B0_MASK |
+ GPIO2B1_MASK |
+ GPIO2B3_MASK |
+ GPIO2B4_MASK |
+ GPIO2B5_MASK |
+ GPIO2B6_MASK,
+ GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
+ GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
+ GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
+ GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
+ GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
+ GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C0_MASK |
+ GPIO2C1_MASK |
+ GPIO2C2_MASK |
+ GPIO2C3_MASK |
+ GPIO2C4_MASK |
+ GPIO2C5_MASK |
+ GPIO2C6_MASK |
+ GPIO2C7_MASK,
+ GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
+ GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
+ GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
+ GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
+ GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
+ GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
+ GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
+ GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D1_MASK,
+ GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
+
+ /*
+ * set rgmii tx pins to 12ma drive-strength,
+ * clean others with 2ma.
+ */
+ rk_clrsetreg(&grf->gpio2_e[1],
+ GRF_GPIO2B0_E_MASK |
+ GRF_GPIO2B1_E_MASK |
+ GRF_GPIO2B3_E_MASK |
+ GRF_GPIO2B4_E_MASK |
+ GRF_GPIO2B5_E_MASK |
+ GRF_GPIO2B6_E_MASK,
+ GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2_e[2],
+ GRF_GPIO2C0_E_MASK |
+ GRF_GPIO2C1_E_MASK |
+ GRF_GPIO2C2_E_MASK |
+ GRF_GPIO2C3_E_MASK |
+ GRF_GPIO2C4_E_MASK |
+ GRF_GPIO2C5_E_MASK |
+ GRF_GPIO2C6_E_MASK |
+ GRF_GPIO2C7_E_MASK,
+ GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2_e[3],
+ GRF_GPIO2D1_E_MASK,
+ GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
+ break;
+ default:
+ debug("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+#endif
+
static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
case PERIPH_ID_SDMMC1:
pinctrl_rk322x_sdmmc_config(priv->grf, func);
break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk322x_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
return PERIPH_ID_UART1;
case 57:
return PERIPH_ID_UART2;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 24:
+ return PERIPH_ID_GMAC;
+#endif
}
return -ENOENT;
}
DECLARE_GLOBAL_DATA_PTR;
+enum {
+ /* GPIO0A_IOMUX */
+ GPIO0A5_SEL_SHIFT = 10,
+ GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
+ GPIO0A5_I2C3_SCL = 2,
+
+ GPIO0A6_SEL_SHIFT = 12,
+ GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
+ GPIO0A6_I2C3_SDA = 2,
+
+ GPIO0A7_SEL_SHIFT = 14,
+ GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
+ GPIO0A7_EMMC_DATA0 = 2,
+
+ /* GPIO0B_IOMUX*/
+ GPIO0B0_SEL_SHIFT = 0,
+ GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
+ GPIO0B0_GAMC_CLKTXM0 = 1,
+
+ GPIO0B4_SEL_SHIFT = 8,
+ GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
+ GPIO0B4_GAMC_TXENM0 = 1,
+
+ /* GPIO0C_IOMUX*/
+ GPIO0C0_SEL_SHIFT = 0,
+ GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
+ GPIO0C0_GAMC_TXD1M0 = 1,
+
+ GPIO0C1_SEL_SHIFT = 2,
+ GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
+ GPIO0C1_GAMC_TXD0M0 = 1,
+
+ GPIO0C6_SEL_SHIFT = 12,
+ GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
+ GPIO0C6_GAMC_TXD2M0 = 1,
+
+ GPIO0C7_SEL_SHIFT = 14,
+ GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
+ GPIO0C7_GAMC_TXD3M0 = 1,
+
+ /* GPIO0D_IOMUX*/
+ GPIO0D0_SEL_SHIFT = 0,
+ GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
+ GPIO0D0_GMAC_CLKM0 = 1,
+
+ GPIO0D6_SEL_SHIFT = 12,
+ GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SDMMC0_PWRENM1 = 3,
+
+ /* GPIO1A_IOMUX */
+ GPIO1A0_SEL_SHIFT = 0,
+ GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
+ GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
+
+ /* GPIO1B_IOMUX */
+ GPIO1B0_SEL_SHIFT = 0,
+ GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
+ GPIO1B0_GMAC_TXD1M1 = 2,
+
+ GPIO1B1_SEL_SHIFT = 2,
+ GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
+ GPIO1B1_GMAC_TXD0M1 = 2,
+
+ GPIO1B2_SEL_SHIFT = 4,
+ GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
+ GPIO1B2_GMAC_RXD1M1 = 2,
+
+ GPIO1B3_SEL_SHIFT = 6,
+ GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
+ GPIO1B3_GMAC_RXD0M1 = 2,
+
+ GPIO1B4_SEL_SHIFT = 8,
+ GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
+ GPIO1B4_GMAC_TXCLKM1 = 2,
+
+ GPIO1B5_SEL_SHIFT = 10,
+ GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
+ GPIO1B5_GMAC_RXCLKM1 = 2,
+
+ GPIO1B6_SEL_SHIFT = 12,
+ GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
+ GPIO1B6_GMAC_RXD3M1 = 2,
+
+ GPIO1B7_SEL_SHIFT = 14,
+ GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
+ GPIO1B7_GMAC_RXD2M1 = 2,
+
+ /* GPIO1C_IOMUX */
+ GPIO1C0_SEL_SHIFT = 0,
+ GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
+ GPIO1C0_GMAC_TXD3M1 = 2,
+
+ GPIO1C1_SEL_SHIFT = 2,
+ GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
+ GPIO1C1_GMAC_TXD2M1 = 2,
+
+ GPIO1C3_SEL_SHIFT = 6,
+ GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
+ GPIO1C3_GMAC_MDIOM1 = 2,
+
+ GPIO1C5_SEL_SHIFT = 10,
+ GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
+ GPIO1C5_GMAC_CLKM1 = 2,
+
+ GPIO1C6_SEL_SHIFT = 12,
+ GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
+ GPIO1C6_GMAC_RXDVM1 = 2,
+
+ GPIO1C7_SEL_SHIFT = 14,
+ GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
+ GPIO1C7_GMAC_MDCM1 = 2,
+
+ /* GPIO1D_IOMUX */
+ GPIO1D1_SEL_SHIFT = 2,
+ GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
+ GPIO1D1_GMAC_TXENM1 = 2,
+
+ /* GPIO2A_IOMUX */
+ GPIO2A0_SEL_SHIFT = 0,
+ GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
+ GPIO2A0_UART2_TX_M1 = 1,
+
+ GPIO2A1_SEL_SHIFT = 2,
+ GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
+ GPIO2A1_UART2_RX_M1 = 1,
+
+ GPIO2A2_SEL_SHIFT = 4,
+ GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
+ GPIO2A2_PWM_IR = 1,
+
+ GPIO2A4_SEL_SHIFT = 8,
+ GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
+ GPIO2A4_PWM_0 = 1,
+ GPIO2A4_I2C1_SDA,
+
+ GPIO2A5_SEL_SHIFT = 10,
+ GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
+ GPIO2A5_PWM_1 = 1,
+ GPIO2A5_I2C1_SCL,
+
+ GPIO2A6_SEL_SHIFT = 12,
+ GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
+ GPIO2A6_PWM_2 = 1,
+
+ GPIO2A7_SEL_SHIFT = 14,
+ GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_SDMMC0_PWRENM0,
+
+ /* GPIO2BL_IOMUX */
+ GPIO2BL0_SEL_SHIFT = 0,
+ GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
+ GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
+
+ GPIO2BL3_SEL_SHIFT = 6,
+ GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
+ GPIO2BL3_SPI_CSN0_M0 = 1,
+
+ GPIO2BL4_SEL_SHIFT = 8,
+ GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
+ GPIO2BL4_SPI_CSN1_M0 = 1,
+
+ GPIO2BL5_SEL_SHIFT = 10,
+ GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
+ GPIO2BL5_I2C2_SDA = 1,
+
+ GPIO2BL6_SEL_SHIFT = 12,
+ GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
+ GPIO2BL6_I2C2_SCL = 1,
+
+ /* GPIO2D_IOMUX */
+ GPIO2D0_SEL_SHIFT = 0,
+ GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
+ GPIO2D0_I2C0_SCL = 1,
+
+ GPIO2D1_SEL_SHIFT = 2,
+ GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
+ GPIO2D1_I2C0_SDA = 1,
+
+ GPIO2D4_SEL_SHIFT = 8,
+ GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
+ GPIO2D4_EMMC_DATA1234 = 0xaa,
+
+ /* GPIO3C_IOMUX */
+ GPIO3C0_SEL_SHIFT = 0,
+ GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
+ GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
+
+ /* COM_IOMUX */
+ IOMUX_SEL_UART2_SHIFT = 0,
+ IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
+ IOMUX_SEL_UART2_M0 = 0,
+ IOMUX_SEL_UART2_M1,
+
+ IOMUX_SEL_GMAC_SHIFT = 2,
+ IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT,
+ IOMUX_SEL_GMAC_M0 = 0,
+ IOMUX_SEL_GMAC_M1,
+
+ IOMUX_SEL_SPI_SHIFT = 4,
+ IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
+ IOMUX_SEL_SPI_M0 = 0,
+ IOMUX_SEL_SPI_M1,
+ IOMUX_SEL_SPI_M2,
+
+ IOMUX_SEL_SDMMC_SHIFT = 7,
+ IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
+ IOMUX_SEL_SDMMC_M0 = 0,
+ IOMUX_SEL_SDMMC_M1,
+
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
+
+ /* GRF_GPIO1B_E */
+ GRF_GPIO1B0_E_SHIFT = 0,
+ GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT,
+ GRF_GPIO1B1_E_SHIFT = 2,
+ GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT,
+ GRF_GPIO1B2_E_SHIFT = 4,
+ GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT,
+ GRF_GPIO1B3_E_SHIFT = 6,
+ GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT,
+ GRF_GPIO1B4_E_SHIFT = 8,
+ GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT,
+ GRF_GPIO1B5_E_SHIFT = 10,
+ GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT,
+ GRF_GPIO1B6_E_SHIFT = 12,
+ GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT,
+ GRF_GPIO1B7_E_SHIFT = 14,
+ GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT,
+
+ /* GRF_GPIO1C_E */
+ GRF_GPIO1C0_E_SHIFT = 0,
+ GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT,
+ GRF_GPIO1C1_E_SHIFT = 2,
+ GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT,
+ GRF_GPIO1C3_E_SHIFT = 6,
+ GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT,
+ GRF_GPIO1C5_E_SHIFT = 10,
+ GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT,
+ GRF_GPIO1C6_E_SHIFT = 12,
+ GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT,
+ GRF_GPIO1C7_E_SHIFT = 14,
+ GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT,
+
+ /* GRF_GPIO1D_E */
+ GRF_GPIO1D1_E_SHIFT = 2,
+ GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
+};
+
struct rk3328_pinctrl_priv {
struct rk3328_grf_regs *grf;
};
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii m1 pins mux */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B0_SEL_MASK |
+ GPIO1B1_SEL_MASK |
+ GPIO1B2_SEL_MASK |
+ GPIO1B3_SEL_MASK |
+ GPIO1B4_SEL_MASK |
+ GPIO1B5_SEL_MASK |
+ GPIO1B6_SEL_MASK |
+ GPIO1B7_SEL_MASK,
+ GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
+ GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
+ GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
+ GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
+ GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
+ GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
+ GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
+ GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C0_SEL_MASK |
+ GPIO1C1_SEL_MASK |
+ GPIO1C3_SEL_MASK |
+ GPIO1C5_SEL_MASK |
+ GPIO1C6_SEL_MASK |
+ GPIO1C7_SEL_MASK,
+ GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
+ GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
+ GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
+ GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
+ GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
+ GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D1_SEL_MASK,
+ GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
+
+ /* set rgmii m0 tx pins mux */
+ rk_clrsetreg(&grf->gpio0b_iomux,
+ GPIO0B0_SEL_MASK |
+ GPIO0B4_SEL_MASK,
+ GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
+ GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0c_iomux,
+ GPIO0C0_SEL_MASK |
+ GPIO0C1_SEL_MASK |
+ GPIO0C6_SEL_MASK |
+ GPIO0C7_SEL_MASK,
+ GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
+ GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
+ GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
+ GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0d_iomux,
+ GPIO0D0_SEL_MASK,
+ GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
+
+ /* set com mux */
+ rk_clrsetreg(&grf->com_iomux,
+ IOMUX_SEL_GMAC_MASK |
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
+ IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
+
+ /*
+ * set rgmii m1 tx pins to 12ma drive-strength,
+ * and clean others to 2ma.
+ */
+ rk_clrsetreg(&grf->gpio1b_e,
+ GRF_GPIO1B0_E_MASK |
+ GRF_GPIO1B1_E_MASK |
+ GRF_GPIO1B2_E_MASK |
+ GRF_GPIO1B3_E_MASK |
+ GRF_GPIO1B4_E_MASK |
+ GRF_GPIO1B5_E_MASK |
+ GRF_GPIO1B6_E_MASK |
+ GRF_GPIO1B7_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_e,
+ GRF_GPIO1C0_E_MASK |
+ GRF_GPIO1C1_E_MASK |
+ GRF_GPIO1C3_E_MASK |
+ GRF_GPIO1C5_E_MASK |
+ GRF_GPIO1C6_E_MASK |
+ GRF_GPIO1C7_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_e,
+ GRF_GPIO1D1_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
+ break;
+ default:
+ debug("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+#endif
+
static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
case PERIPH_ID_SDMMC1:
pinctrl_rk3328_sdmmc_config(priv->grf, func);
break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3328_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
return PERIPH_ID_SDCARD;
case 14:
return PERIPH_ID_EMMC;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 24:
+ return PERIPH_ID_GMAC;
+#endif
}
return -ENOENT;
struct rv1108_grf *grf;
};
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_LCDC_D12,
+ GPIO1B7_I2S_SDIO2_M0,
+ GPIO1B7_GMAC_RXDV,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_LCDC_D13,
+ GPIO1B6_I2S_LRCLKTX_M0,
+ GPIO1B6_GMAC_RXD1,
+
+ GPIO1B5_SHIFT = 10,
+ GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
+ GPIO1B5_GPIO = 0,
+ GPIO1B5_LCDC_D14,
+ GPIO1B5_I2S_SDIO1_M0,
+ GPIO1B5_GMAC_RXD0,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_LCDC_D15,
+ GPIO1B4_I2S_MCLK_M0,
+ GPIO1B4_GMAC_TXEN,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_LCDC_D16,
+ GPIO1B3_I2S_SCLK_M0,
+ GPIO1B3_GMAC_TXD1,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_LCDC_D17,
+ GPIO1B2_I2S_SDIO_M0,
+ GPIO1B2_GMAC_TXD0,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_LCDC_D9,
+ GPIO1B1_PWM7,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_LCDC_D8,
+ GPIO1B0_PWM6,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_SHIFT = 14,
+ GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_CIF_D5,
+ GPIO1C7_I2S_SDIO2_M1,
+
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_CIF_D4,
+ GPIO1C6_I2S_LRCLKTX_M1,
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_LCDC_CLK,
+ GPIO1C5_GMAC_CLK,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_LCDC_HSYNC,
+ GPIO1C4_GMAC_MDC,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_LCDC_VSYNC,
+ GPIO1C3_GMAC_MDIO,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_LCDC_EN,
+ GPIO1C2_I2S_SDIO3_M0,
+ GPIO1C2_GMAC_RXER,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_LCDC_D10,
+ GPIO1C1_I2S_SDI_M0,
+ GPIO1C1_PWM4,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 3,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_LCDC_D11,
+ GPIO1C0_I2S_LRCLKRX_M0,
+};
+
+/* GRF_GPIO1D_OIMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_HDMI_CEC,
+ GPIO1D7_DSP_RTCK,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_HDMI_HPD_M0,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_UART2_RTSN,
+ GPIO1D5_HDMI_SDA_M0,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_UART2_CTSN,
+ GPIO1D4_HDMI_SCL_M0,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_UART0_SOUT,
+ GPIO1D3_SPI_TXD_M0,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_UART0_SIN,
+ GPIO1D2_SPI_RXD_M0,
+ GPIO1D2_DSP_TDI,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_UART0_RTSN,
+ GPIO1D1_SPI_CSN0_M0,
+ GPIO1D1_DSP_TMS,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_UART0_CTSN,
+ GPIO1D0_SPI_CLK_M0,
+ GPIO1D0_DSP_TCK,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_FLASH_D7,
+ GPIO2A7_EMMC_D7,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_FLASH_D6,
+ GPIO2A6_EMMC_D6,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_FLASH_D5,
+ GPIO2A5_EMMC_D5,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_FLASH_D4,
+ GPIO2A4_EMMC_D4,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_FLASH_D3,
+ GPIO2A3_EMMC_D3,
+ GPIO2A3_SFC_HOLD_IO3,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_FLASH_D2,
+ GPIO2A2_EMMC_D2,
+ GPIO2A2_SFC_WP_IO2,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_FLASH_D1,
+ GPIO2A1_EMMC_D1,
+ GPIO2A1_SFC_SO_IO1,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_FLASH_D0,
+ GPIO2A0_EMMC_D0,
+ GPIO2A0_SFC_SI_IO0,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_FLASH_CS1,
+ GPIO2B7_SFC_CLK,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_EMMC_CLKO,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_FLASH_CS0,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_FLASH_RDY,
+ GPIO2B4_EMMC_CMD,
+ GPIO2B4_SFC_CSN0,
+
+ GPIO2B3_SHIFT = 6,
+ GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO = 0,
+ GPIO2B3_FLASH_RDN,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_FLASH_WRN,
+
+ GPIO2B1_SHIFT = 2,
+ GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO = 0,
+ GPIO2B1_FLASH_CLE,
+
+ GPIO2B0_SHIFT = 0,
+ GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO = 0,
+ GPIO2B0_FLASH_ALE,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D7_SHIFT = 14,
+ GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
+ GPIO2D7_GPIO = 0,
+ GPIO2D7_SDIO_D0,
+
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_SDIO_CMD,
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_SDIO_CLKO,
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_I2C1_SCL,
+
+ GPIO2D3_SHIFT = 6,
+ GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
+ GPIO2D3_GPIO = 0,
+ GPIO2D3_I2C1_SDA,
+
+ GPIO2D2_SHIFT = 4,
+ GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
+ GPIO2D2_GPIO = 0,
+ GPIO2D2_UART2_SOUT_M0,
+ GPIO2D2_JTAG_TCK,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART2_SIN_M0,
+ GPIO2D1_JTAG_TMS,
+ GPIO2D1_DSP_TMS,
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = 3,
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_CTSN,
+ GPIO2D0_SPI_CLK_M0,
+ GPIO2D0_DSP_TCK,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
+ GPIO3A7_GPIO = 0,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
+ GPIO3A6_GPIO = 0,
+ GPIO3A6_UART1_SOUT,
+
+ GPIO3A5_SHIFT = 10,
+ GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
+ GPIO3A5_GPIO = 0,
+ GPIO3A5_UART1_SIN,
+
+ GPIO3A4_SHIFT = 8,
+ GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
+ GPIO3A4_GPIO = 0,
+ GPIO3A4_UART1_CTSN,
+
+ GPIO3A3_SHIFT = 6,
+ GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_UART1_RTSN,
+
+ GPIO3A2_SHIFT = 4,
+ GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_SDIO_D3,
+
+ GPIO3A1_SHIFT = 2,
+ GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_SDIO_D2,
+
+ GPIO3A0_SHIFT = 0,
+ GPIO3A0_MASK = 1,
+ GPIO3A0_GPIO = 0,
+ GPIO3A0_SDIO_D1,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C7_SHIFT = 14,
+ GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
+ GPIO3C7_GPIO = 0,
+ GPIO3C7_CIF_CLKI,
+
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_CIF_VSYNC,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_SDMMC_CMD,
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_SDMMC_CLKO,
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_SDMMC_D0,
+ GPIO3C3_UART2_SOUT_M1,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_SDMMC_D1,
+ GPIO3C2_UART2_SIN_M1,
+
+ GPIOC1_SHIFT = 2,
+ GPIOC1_MASK = 1 << GPIOC1_SHIFT,
+ GPIOC1_GPIO = 0,
+ GPIOC1_SDMMC_D2,
+
+ GPIOC0_SHIFT = 0,
+ GPIOC0_MASK = 1,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_SDMMC_D3,
+};
+
static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
{
switch (uart_id) {
DECLARE_GLOBAL_DATA_PTR;
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = S2MPS11_OF_LDO_PREFIX, .driver = S2MPS11_LDO_DRIVER },
+ { .prefix = S2MPS11_OF_BUCK_PREFIX, .driver = S2MPS11_BUCK_DRIVER },
+ { },
+};
+
static int s2mps11_reg_count(struct udevice *dev)
{
return S2MPS11_REG_COUNT;
return ret;
}
+static int s2mps11_probe(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "voltage-regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ return 0;
+}
+
static struct dm_pmic_ops s2mps11_ops = {
.reg_count = s2mps11_reg_count,
.read = s2mps11_read,
.id = UCLASS_PMIC,
.of_match = s2mps11_ids,
.ops = &s2mps11_ops,
+ .probe = s2mps11_probe,
};
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
+config DM_REGULATOR_S2MPS11
+ bool "Enable driver for S2MPS11 regulator"
+ depends on DM_REGULATOR && PMIC_S2MPS11
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR S2MPS11.
+ The driver implements get/set api for: value and enable.
+
config REGULATOR_S5M8767
bool "Enable support for S5M8767 regulator"
depends on DM_REGULATOR && PMIC_S5M8767
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o
+obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
--- /dev/null
+/*
+ * Copyright (C) 2018 Samsung Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODE(_id, _val, _name) { \
+ .id = _id, \
+ .register_value = _val, \
+ .name = _name, \
+}
+
+/* BUCK : 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 */
+static struct dm_regulator_mode s2mps11_buck_modes[] = {
+ MODE(OP_OFF, S2MPS11_BUCK_MODE_OFF, "OFF"),
+ MODE(OP_STANDBY, S2MPS11_BUCK_MODE_STANDBY, "ON/OFF"),
+ MODE(OP_ON, S2MPS11_BUCK_MODE_STANDBY, "ON"),
+};
+
+static struct dm_regulator_mode s2mps11_ldo_modes[] = {
+ MODE(OP_OFF, S2MPS11_LDO_MODE_OFF, "OFF"),
+ MODE(OP_STANDBY, S2MPS11_LDO_MODE_STANDBY, "ON/OFF"),
+ MODE(OP_STANDBY_LPM, S2MPS11_LDO_MODE_STANDBY_LPM, "ON/LPM"),
+ MODE(OP_ON, S2MPS11_LDO_MODE_ON, "ON"),
+};
+
+static const char s2mps11_buck_ctrl[] = {
+ 0xff, 0x25, 0x27, 0x29, 0x2b, 0x2d, 0x33, 0x35, 0x37, 0x39, 0x3b
+};
+
+static const char s2mps11_buck_out[] = {
+ 0xff, 0x26, 0x28, 0x2a, 0x2c, 0x2f, 0x34, 0x36, 0x38, 0x3a, 0x3c
+};
+
+static int s2mps11_buck_hex2volt(int buck, int hex)
+{
+ unsigned int uV = 0;
+
+ if (hex < 0)
+ goto bad;
+
+ switch (buck) {
+ case 7:
+ case 8:
+ case 10:
+ if (hex > S2MPS11_BUCK7_8_10_VOLT_MAX_HEX)
+ goto bad;
+
+ uV = hex * S2MPS11_BUCK_HSTEP + S2MPS11_BUCK_UV_HMIN;
+ break;
+ case 9:
+ if (hex > S2MPS11_BUCK9_VOLT_MAX_HEX)
+ goto bad;
+ uV = hex * S2MPS11_BUCK9_STEP * 2 + S2MPS11_BUCK9_UV_MIN;
+ break;
+ default:
+ if (buck == 5 && hex > S2MPS11_BUCK5_VOLT_MAX_HEX)
+ goto bad;
+ else if (buck != 5 && hex > S2MPS11_BUCK_VOLT_MAX_HEX)
+ goto bad;
+
+ uV = hex * S2MPS11_BUCK_LSTEP + S2MPS11_BUCK_UV_MIN;
+ break;
+ }
+
+ return uV;
+bad:
+ pr_err("Value: %#x is wrong for BUCK%d", hex, buck);
+ return -EINVAL;
+}
+
+static int s2mps11_buck_volt2hex(int buck, int uV)
+{
+ int hex;
+
+ switch (buck) {
+ case 7:
+ case 8:
+ case 10:
+ hex = (uV - S2MPS11_BUCK_UV_HMIN) / S2MPS11_BUCK_HSTEP;
+ if (hex > S2MPS11_BUCK7_8_10_VOLT_MAX_HEX)
+ goto bad;
+
+ break;
+ case 9:
+ hex = (uV - S2MPS11_BUCK9_UV_MIN) / S2MPS11_BUCK9_STEP;
+ if (hex > S2MPS11_BUCK9_VOLT_MAX_HEX)
+ goto bad;
+ break;
+ default:
+ hex = (uV - S2MPS11_BUCK_UV_MIN) / S2MPS11_BUCK_LSTEP;
+ if (buck == 5 && hex > S2MPS11_BUCK5_VOLT_MAX_HEX)
+ goto bad;
+ else if (buck != 5 && hex > S2MPS11_BUCK_VOLT_MAX_HEX)
+ goto bad;
+ break;
+ };
+
+ if (hex >= 0)
+ return hex;
+
+bad:
+ pr_err("Value: %d uV is wrong for BUCK%d", uV, buck);
+ return -EINVAL;
+}
+
+static int s2mps11_buck_val(struct udevice *dev, int op, int *uV)
+{
+ int hex, buck, ret;
+ u32 mask, addr;
+ u8 val;
+
+ buck = dev->driver_data;
+ if (buck < 1 || buck > S2MPS11_BUCK_NUM) {
+ pr_err("Wrong buck number: %d\n", buck);
+ return -EINVAL;
+ }
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ addr = s2mps11_buck_out[buck];
+
+ switch (buck) {
+ case 9:
+ mask = S2MPS11_BUCK9_VOLT_MASK;
+ break;
+ default:
+ mask = S2MPS11_BUCK_VOLT_MASK;
+ break;
+ }
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= mask;
+ ret = s2mps11_buck_hex2volt(buck, val);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = s2mps11_buck_volt2hex(buck, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~mask;
+ val |= hex;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_buck_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned int addr, mode;
+ unsigned char val;
+ int buck, ret;
+
+ buck = dev->driver_data;
+ if (buck < 1 || buck > S2MPS11_BUCK_NUM) {
+ pr_err("Wrong buck number: %d\n", buck);
+ return -EINVAL;
+ }
+
+ addr = s2mps11_buck_ctrl[buck];
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= (S2MPS11_BUCK_MODE_MASK << S2MPS11_BUCK_MODE_SHIFT);
+ switch (val) {
+ case S2MPS11_BUCK_MODE_OFF:
+ *opmode = OP_OFF;
+ break;
+ case S2MPS11_BUCK_MODE_STANDBY:
+ *opmode = OP_STANDBY;
+ break;
+ case S2MPS11_BUCK_MODE_ON:
+ *opmode = OP_ON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ switch (*opmode) {
+ case OP_OFF:
+ mode = S2MPS11_BUCK_MODE_OFF;
+ break;
+ case OP_STANDBY:
+ mode = S2MPS11_BUCK_MODE_STANDBY;
+ break;
+ case OP_ON:
+ mode = S2MPS11_BUCK_MODE_ON;
+ break;
+ default:
+ pr_err("Wrong mode: %d for buck: %d\n", *opmode, buck);
+ return -EINVAL;
+ }
+
+ val &= ~(S2MPS11_BUCK_MODE_MASK << S2MPS11_BUCK_MODE_SHIFT);
+ val |= mode;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret, on_off;
+
+ if (op == PMIC_OP_GET) {
+ ret = s2mps11_buck_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ case OP_OFF:
+ *enable = false;
+ break;
+ case OP_ON:
+ *enable = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ on_off = OP_ON;
+ else
+ on_off = OP_OFF;
+
+ ret = s2mps11_buck_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = s2mps11_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return s2mps11_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = s2mps11_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return s2mps11_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int buck_get_mode(struct udevice *dev)
+{
+ int mode;
+ int ret;
+
+ ret = s2mps11_buck_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+
+ return mode;
+}
+
+static int buck_set_mode(struct udevice *dev, int mode)
+{
+ return s2mps11_buck_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static int s2mps11_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ uc_pdata->mode = s2mps11_buck_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(s2mps11_buck_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops s2mps11_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+ .get_mode = buck_get_mode,
+ .set_mode = buck_set_mode,
+};
+
+U_BOOT_DRIVER(s2mps11_buck) = {
+ .name = S2MPS11_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &s2mps11_buck_ops,
+ .probe = s2mps11_buck_probe,
+};
+
+static int s2mps11_ldo_hex2volt(int ldo, int hex)
+{
+ unsigned int uV = 0;
+
+ if (hex > S2MPS11_LDO_VOLT_MAX_HEX) {
+ pr_err("Value: %#x is wrong for LDO%d", hex, ldo);
+ return -EINVAL;
+ }
+
+ switch (ldo) {
+ case 1:
+ case 6:
+ case 11:
+ case 22:
+ case 23:
+ uV = hex * S2MPS11_LDO_STEP + S2MPS11_LDO_UV_MIN;
+ break;
+ default:
+ uV = hex * S2MPS11_LDO_STEP * 2 + S2MPS11_LDO_UV_MIN;
+ break;
+ }
+
+ return uV;
+}
+
+static int s2mps11_ldo_volt2hex(int ldo, int uV)
+{
+ int hex = 0;
+
+ switch (ldo) {
+ case 1:
+ case 6:
+ case 11:
+ case 22:
+ case 23:
+ hex = (uV - S2MPS11_LDO_UV_MIN) / S2MPS11_LDO_STEP;
+ break;
+ default:
+ hex = (uV - S2MPS11_LDO_UV_MIN) / (S2MPS11_LDO_STEP * 2);
+ break;
+ }
+
+ if (hex >= 0 && hex <= S2MPS11_LDO_VOLT_MAX_HEX)
+ return hex;
+
+ pr_err("Value: %d uV is wrong for LDO%d", uV, ldo);
+ return -EINVAL;
+
+ return 0;
+}
+
+static int s2mps11_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int addr;
+ unsigned char val;
+ int hex, ldo, ret;
+
+ ldo = dev->driver_data;
+ if (ldo < 1 || ldo > S2MPS11_LDO_NUM) {
+ pr_err("Wrong ldo number: %d\n", ldo);
+ return -EINVAL;
+ }
+
+ addr = S2MPS11_REG_L1CTRL + ldo - 1;
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+ val &= S2MPS11_LDO_VOLT_MASK;
+ ret = s2mps11_ldo_hex2volt(ldo, val);
+ if (ret < 0)
+ return ret;
+
+ *uV = ret;
+ return 0;
+ }
+
+ hex = s2mps11_ldo_volt2hex(ldo, *uV);
+ if (hex < 0)
+ return hex;
+
+ val &= ~S2MPS11_LDO_VOLT_MASK;
+ val |= hex;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_ldo_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned int addr, mode;
+ unsigned char val;
+ int ldo, ret;
+
+ ldo = dev->driver_data;
+ if (ldo < 1 || ldo > S2MPS11_LDO_NUM) {
+ pr_err("Wrong ldo number: %d\n", ldo);
+ return -EINVAL;
+ }
+ addr = S2MPS11_REG_L1CTRL + ldo - 1;
+
+ ret = pmic_read(dev->parent, addr, &val, 1);
+ if (ret)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ val &= (S2MPS11_LDO_MODE_MASK << S2MPS11_LDO_MODE_SHIFT);
+ switch (val) {
+ case S2MPS11_LDO_MODE_OFF:
+ *opmode = OP_OFF;
+ break;
+ case S2MPS11_LDO_MODE_STANDBY:
+ *opmode = OP_STANDBY;
+ break;
+ case S2MPS11_LDO_MODE_STANDBY_LPM:
+ *opmode = OP_STANDBY_LPM;
+ break;
+ case S2MPS11_LDO_MODE_ON:
+ *opmode = OP_ON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ switch (*opmode) {
+ case OP_OFF:
+ mode = S2MPS11_LDO_MODE_OFF;
+ break;
+ case OP_STANDBY:
+ mode = S2MPS11_LDO_MODE_STANDBY;
+ break;
+ case OP_STANDBY_LPM:
+ mode = S2MPS11_LDO_MODE_STANDBY_LPM;
+ break;
+ case OP_ON:
+ mode = S2MPS11_LDO_MODE_ON;
+ break;
+ default:
+ pr_err("Wrong mode: %d for ldo: %d\n", *opmode, ldo);
+ return -EINVAL;
+ }
+
+ val &= ~(S2MPS11_LDO_MODE_MASK << S2MPS11_LDO_MODE_SHIFT);
+ val |= mode;
+ ret = pmic_write(dev->parent, addr, &val, 1);
+
+ return ret;
+}
+
+static int s2mps11_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret, on_off;
+
+ if (op == PMIC_OP_GET) {
+ ret = s2mps11_ldo_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ case OP_OFF:
+ *enable = false;
+ break;
+ case OP_ON:
+ *enable = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ on_off = OP_ON;
+ else
+ on_off = OP_OFF;
+
+ ret = s2mps11_ldo_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = s2mps11_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return s2mps11_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = s2mps11_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int ldo_get_mode(struct udevice *dev)
+{
+ int mode, ret;
+
+ ret = s2mps11_ldo_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+ return mode;
+}
+
+static int ldo_set_mode(struct udevice *dev, int mode)
+{
+ return s2mps11_ldo_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static int s2mps11_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ uc_pdata->mode = s2mps11_ldo_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(s2mps11_ldo_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops s2mps11_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+ .get_mode = ldo_get_mode,
+ .set_mode = ldo_set_mode,
+};
+
+U_BOOT_DRIVER(s2mps11_ldo) = {
+ .name = S2MPS11_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &s2mps11_ldo_ops,
+ .probe = s2mps11_ldo_probe,
+};
#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+#define SDRAM_6318_SPACE_SHIFT 4
+#define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
#define MEMC_CFG_REG 0x4
#define MEMC_CFG_32B_SHIFT 1
const struct bmips_ram_hw *hw;
};
+static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
+{
+ u32 val;
+
+ val = readl_be(priv->regs + SDRAM_CFG_REG);
+ val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
+
+ return (1 << (val + 20));
+}
+
static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
{
return readl_be(priv->regs + DDR_CSEND_REG) << 24;
.get_info = bmips_ram_get_info,
};
+static const struct bmips_ram_hw bmips_ram_bcm6318 = {
+ .get_ram_size = bcm6318_get_ram_size,
+};
+
static const struct bmips_ram_hw bmips_ram_bcm6328 = {
.get_ram_size = bcm6328_get_ram_size,
};
static const struct udevice_id bmips_ram_ids[] = {
{
+ .compatible = "brcm,bcm6318-mc",
+ .data = (ulong)&bmips_ram_bcm6318,
+ }, {
.compatible = "brcm,bcm6328-mc",
.data = (ulong)&bmips_ram_bcm6328,
}, {
return 0;
reg = (void __iomem *)base + ch->ack_offset;
- if (wait_for_bit(__func__, reg, BIT(ch->ack_bit), ctrl_val,
- 1000, false)) {
+ if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
+ 1000, false)) {
pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
reset_ctl, reset_ctl->dev, reset_ctl->id);
help
The size of the RX buffer (needs to be power of 2)
+config SERIAL_SEARCH_ALL
+ bool "Search for serial devices after default one failed"
+ depends on DM_SERIAL
+ help
+ The serial subsystem only searches for a single serial device
+ that was instantiated, but does not check whether it was probed
+ correctly. With this option set, we make successful probing
+ mandatory and search for fallback serial devices if the default
+ device does not work.
+
+ If unsure, say N.
+
config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL
configured in the device tree, and input clock frequency can
be got from the clk node.
+config BCM283X_MU_SERIAL
+ bool "Support for BCM283x Mini-UART"
+ depends on DM_SERIAL && ARCH_BCM283X
+ default y
+ help
+ Select this to enable Mini-UART support on BCM283X family of SoCs.
+
+config BCM283X_PL011_SERIAL
+ bool "Support for BCM283x PL011 UART"
+ depends on PL01X_SERIAL && ARCH_BCM283X
+ default y
+ help
+ Select this to enable an overriding PL011 driver for BCM283X SoCs
+ that supports automatic disable, so that it only gets used when
+ the UART is actually muxed.
+
config BCM6345_SERIAL
bool "Support for BCM6345 UART"
depends on DM_SERIAL && ARCH_BMIPS
Select this to enable a UART for Intel MID platforms.
This uses the ns16550 driver as a library.
+config PL010_SERIAL
+ bool "ARM PL010 driver"
+ depends on !DM_SERIAL
+ help
+ Select this to enable a UART for platforms using PL010.
+
+config PL011_SERIAL
+ bool "ARM PL011 driver"
+ depends on !DM_SERIAL
+ help
+ Select this to enable a UART for platforms using PL011.
+
+config PL01X_SERIAL
+ bool "ARM PL010 and PL011 driver"
+ depends on DM_SERIAL
+ help
+ Select this to enable a UART for platforms using PL010 or PL011.
+
config ROCKCHIP_SERIAL
bool "Rockchip on-chip UART support"
depends on DM_SERIAL && SPL_OF_PLATDATA
on STiH410 SoC. This is a basic implementation, it supports
following baudrate 9600, 19200, 38400, 57600 and 115200.
-config STM32X7_SERIAL
+config STM32_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
help
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
-obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
+obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
+obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
struct NS16550 *const com_port = dev_get_priv(dev);
if (input)
- return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0;
+ return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
else
- return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1;
+ return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
}
static int ns16550_serial_getc(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct udevice *dev;
+#ifdef CONFIG_SERIAL_SEARCH_ALL
+ int ret;
+#endif
if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
uclass_first_device(UCLASS_SERIAL, &dev);
* from 1!).
*
* Failing that, get the device with sequence number 0, or in
- * extremis just the first serial device we can find. But we
- * insist on having a console (even if it is silent).
+ * extremis just the first working serial device we can find.
+ * But we insist on having a console (even if it is silent).
*/
#ifdef CONFIG_CONS_INDEX
#define INDEX (CONFIG_CONS_INDEX - 1)
#else
#define INDEX 0
#endif
+
+#ifdef CONFIG_SERIAL_SEARCH_ALL
+ if (!uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) ||
+ !uclass_get_device(UCLASS_SERIAL, INDEX, &dev)) {
+ if (dev->flags & DM_FLAG_ACTIVATED) {
+ gd->cur_serial_dev = dev;
+ return;
+ }
+ }
+
+ /* Search for any working device */
+ for (ret = uclass_first_device_check(UCLASS_SERIAL, &dev);
+ dev;
+ ret = uclass_next_device_check(&dev)) {
+ if (!ret) {
+ /* Device did succeed probing */
+ gd->cur_serial_dev = dev;
+ return;
+ }
+ }
+#else
if (!uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) ||
!uclass_get_device(UCLASS_SERIAL, INDEX, &dev) ||
(!uclass_first_device(UCLASS_SERIAL, &dev) && dev)) {
gd->cur_serial_dev = dev;
return;
}
+#endif
+
#undef INDEX
}
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <serial.h>
#include <dm/platform_data/serial_bcm283x_mu.h>
+#include <dm/pinctrl.h>
#include <linux/compiler.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
struct bcm283x_mu_regs {
u32 io;
struct bcm283x_mu_regs *regs = priv->regs;
u32 divider;
- if (plat->disabled || plat->skip_init)
+ if (plat->skip_init)
return 0;
divider = plat->clock / (baudrate * 8);
struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
- if (plat->disabled)
- return -ENODEV;
-
priv->regs = (struct bcm283x_mu_regs *)plat->base;
return 0;
static int bcm283x_mu_serial_getc(struct udevice *dev)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
u32 data;
- if (plat->disabled)
- return -EAGAIN;
-
/* Wait until there is data in the FIFO */
if (!(readl(®s->lsr) & BCM283X_MU_LSR_RX_READY))
return -EAGAIN;
static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
- if (plat->disabled)
- return 0;
-
/* Wait until there is space in the FIFO */
if (!(readl(®s->lsr) & BCM283X_MU_LSR_TX_EMPTY))
return -EAGAIN;
static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
unsigned int lsr;
- if (plat->disabled)
- return 0;
-
lsr = readl(®s->lsr);
if (input) {
{}
};
+/*
+ * Check if this serial device is muxed
+ *
+ * The serial device will only work properly if it has been muxed to the serial
+ * pins by firmware. Check whether that happened here.
+ *
+ * @return true if serial device is muxed, false if not
+ */
+static bool bcm283x_is_serial_muxed(void)
+{
+ int serial_gpio = 15;
+ struct udevice *dev;
+
+ if (uclass_first_device(UCLASS_PINCTRL, &dev) || !dev)
+ return false;
+
+ if (pinctrl_get_gpio_mux(dev, 0, serial_gpio) != BCM2835_GPIO_ALT5)
+ return false;
+
+ return true;
+}
+
static int bcm283x_mu_serial_ofdata_to_platdata(struct udevice *dev)
{
struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
+ /* Don't spawn the device if it's not muxed */
+ if (!bcm283x_is_serial_muxed())
+ return -ENODEV;
+
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
- 1);
- plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
- "skip-init");
- plat->disabled = false;
+ plat->clock = dev_read_u32_default(dev, "clock", 1);
+
+ /*
+ * TODO: Reinitialization doesn't always work for now, just skip
+ * init always - we know we're already initialized
+ */
+ plat->skip_init = true;
+
return 0;
}
#endif
--- /dev/null
+/*
+ * Copyright (c) 2018 Alexander Graf <agraf@suse.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include "serial_pl01x_internal.h"
+
+/*
+ * Check if this serial device is muxed
+ *
+ * The serial device will only work properly if it has been muxed to the serial
+ * pins by firmware. Check whether that happened here.
+ *
+ * @return true if serial device is muxed, false if not
+ */
+static bool bcm283x_is_serial_muxed(void)
+{
+ int serial_gpio = 15;
+ struct udevice *dev;
+
+ if (uclass_first_device(UCLASS_PINCTRL, &dev) || !dev)
+ return false;
+
+ if (pinctrl_get_gpio_mux(dev, 0, serial_gpio) != BCM2835_GPIO_ALT0)
+ return false;
+
+ return true;
+}
+
+static int bcm283x_pl011_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ /* Don't spawn the device if it's not muxed */
+ if (!bcm283x_is_serial_muxed())
+ return -ENODEV;
+
+ ret = pl01x_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+
+ /*
+ * TODO: Reinitialization doesn't always work for now, just skip
+ * init always - we know we're already initialized
+ */
+ plat->skip_init = true;
+
+ return 0;
+}
+
+static const struct udevice_id bcm283x_pl011_serial_id[] = {
+ {.compatible = "brcm,bcm2835-pl011", .data = TYPE_PL011},
+ {}
+};
+
+U_BOOT_DRIVER(bcm283x_pl011_uart) = {
+ .name = "bcm283x_pl011",
+ .id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(bcm283x_pl011_serial_id),
+ .ofdata_to_platdata = of_match_ptr(bcm283x_pl011_serial_ofdata_to_platdata),
+ .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
+ .probe = pl01x_serial_probe,
+ .ops = &pl01x_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto_alloc_size = sizeof(struct pl01x_priv),
+};
lpuart_read32(plat->flags, &base->data, &val);
- if (plat->devtype & DEV_MX7ULP) {
- lpuart_read32(plat->flags, &base->stat, &stat);
- if (stat & STAT_OR)
- lpuart_write32(plat->flags, &base->stat, STAT_OR);
- }
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ if (stat & STAT_OR)
+ lpuart_write32(plat->flags, &base->stat, STAT_OR);
return val & 0x3ff;
}
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat;
- if (plat->devtype & DEV_MX7ULP) {
- if (c == '\n')
- serial_putc('\r');
- }
+ if (c == '\n')
+ serial_putc('\r');
while (true) {
lpuart_read32(plat->flags, &base->stat, &stat);
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype & DEV_MX7ULP) {
+ if (plat->devtype == DEV_MX7ULP) {
_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
struct lpuart_serial_platdata *plat = dev->platdata;
if (is_lpuart32(dev)) {
- if (plat->devtype & DEV_MX7ULP)
+ if (plat->devtype == DEV_MX7ULP)
_lpuart32_serial_setbrg_7ulp(plat, baudrate);
else
_lpuart32_serial_setbrg(plat, baudrate);
u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
/* wait for TX FIFO to empty */
- wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY,
- true, CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(base + U_STA, UART_TX_EMPTY,
+ true, CONFIG_SYS_HZ, false);
/* send break */
writel(UART_TX_BRK, base + U_STASET);
#include <dm/platform_data/serial_pl01x.h>
#include <linux/compiler.h>
#include "serial_pl01x_internal.h"
-#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DM_SERIAL
-struct pl01x_priv {
- struct pl01x_regs *regs;
- enum pl01x_type type;
-};
-
static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
return 0;
}
-static int pl01x_serial_probe(struct udevice *dev)
+int pl01x_serial_probe(struct udevice *dev)
{
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
return fr & UART_PL01x_FR_TXFF ? 0 : 1;
}
-static const struct dm_serial_ops pl01x_serial_ops = {
+const struct dm_serial_ops pl01x_serial_ops = {
.putc = pl01x_serial_putc,
.pending = pl01x_serial_pending,
.getc = pl01x_serial_getc,
{}
};
-static int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
+int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
{
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
return -EINVAL;
plat->base = addr;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
- 1);
+ plat->clock = dev_read_u32_default(dev, "clock", 1);
plat->type = dev_get_driver_data(dev);
- plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
- "skip-init");
+ plat->skip_init = dev_read_bool(dev, "skip-init");
+
return 0;
}
#endif
u32 pl011_lcrh; /* 0x2C Line control register */
u32 pl011_cr; /* 0x30 Control register */
};
-#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+int pl01x_serial_ofdata_to_platdata(struct udevice *dev);
+int pl01x_serial_probe(struct udevice *dev);
+extern const struct dm_serial_ops pl01x_serial_ops;
+
+struct pl01x_priv {
+ struct pl01x_regs *regs;
+ enum pl01x_type type;
+};
+
+#endif /* CONFIG_DM_SERIAL */
+#endif /* !__ASSEMBLY__ */
#define UART_PL01x_RSR_OE 0x08
#define UART_PL01x_RSR_BE 0x04
fdt_addr_t addr;
int ret;
- addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
- if (addr == FDT_ADDR_T_NONE)
+ addr = devfdt_get_addr(dev);
+ if (!addr)
return -EINVAL;
plat->base = addr;
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
- defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
+ defined(CONFIG_R7S72100)
# if defined(CONFIG_SCIF_A)
# define SCIF_ORER 0x0200
# else
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# if defined(CONFIG_SCIF_A)
# define SCIF_RFDC_MASK 0x007f
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCLSR, 0x24, 16)
SCIF_FNS(DL, 0x00, 0) /* dummy */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
/* SCIFA and SCIF register offsets and size */
SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+#elif defined(CONFIG_RCAR_GEN2)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#if defined(CONFIG_SCIF_A)
#define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
-#include "serial_stm32x7.h"
+#include "serial_stm32.h"
DECLARE_GLOBAL_DATA_PTR;
};
U_BOOT_DRIVER(serial_stm32) = {
- .name = "serial_stm32x7",
+ .name = "serial_stm32",
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(stm32_serial_id),
.ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _SERIAL_STM32_X7_
-#define _SERIAL_STM32_X7_
+#ifndef _SERIAL_STM32_
+#define _SERIAL_STM32_
#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
many AT91 (ARM) chips. This driver can be used to access
the SPI Flash, such as AT25DF321.
+config BCM63XX_HSSPI
+ bool "BCM63XX HSSPI driver"
+ depends on ARCH_BMIPS
+ help
+ Enable the BCM6328 HSSPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Broadcom
+ SPI core.
+
+config BCM63XX_SPI
+ bool "BCM6348 SPI driver"
+ depends on ARCH_BMIPS
+ help
+ Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding these Broadcom
+ SPI cores.
+
config CADENCE_QSPI
bool "Cadence QSPI driver"
help
used to access the SPI flash on AE3XX and AE250 platforms embedding
this Andestech IP core.
+config DAVINCI_SPI
+ bool "Davinci & Keystone SPI driver"
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
+ help
+ Enable the Davinci SPI driver
+
config TI_QSPI
bool "TI QSPI driver"
help
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
+obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
* Wait until the transfer is completely done before
* we deactivate CS.
*/
- wait_for_bit(__func__, ®_base->sr,
- ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
+ wait_for_bit_le32(®_base->sr,
+ ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
atmel_spi_cs_deactivate(dev);
}
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
+ * Copyright (C) 2000-2010 Broadcom Corporation
+ * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <spi.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HSSPI_PP 0
+
+#define SPI_MAX_SYNC_CLOCK 30000000
+
+/* SPI Control register */
+#define SPI_CTL_REG 0x000
+#define SPI_CTL_CS_POL_SHIFT 0
+#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
+#define SPI_CTL_CLK_GATE_SHIFT 16
+#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
+#define SPI_CTL_CLK_POL_SHIFT 17
+#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
+
+/* SPI Interrupts registers */
+#define SPI_IR_STAT_REG 0x008
+#define SPI_IR_ST_MASK_REG 0x00c
+#define SPI_IR_MASK_REG 0x010
+
+#define SPI_IR_CLEAR_ALL 0xff001f1f
+
+/* SPI Ping-Pong Command registers */
+#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
+#define SPI_CMD_OP_SHIFT 0
+#define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
+#define SPI_CMD_PFL_SHIFT 8
+#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
+#define SPI_CMD_SLAVE_SHIFT 12
+#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
+
+/* SPI Ping-Pong Status registers */
+#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
+#define SPI_STAT_SRCBUSY_SHIFT 1
+#define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
+
+/* SPI Profile Clock registers */
+#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
+#define SPI_PFL_CLK_FREQ_SHIFT 0
+#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
+#define SPI_PFL_CLK_RSTLOOP_SHIFT 15
+#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
+
+/* SPI Profile Signal registers */
+#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
+#define SPI_PFL_SIG_LATCHRIS_SHIFT 12
+#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
+#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
+#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
+#define SPI_PFL_SIG_ASYNCIN_SHIFT 16
+#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
+
+/* SPI Profile Mode registers */
+#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
+#define SPI_PFL_MODE_FILL_SHIFT 0
+#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
+#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
+#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
+#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
+#define SPI_PFL_MODE_3WIRE_SHIFT 20
+#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
+
+/* SPI Ping-Pong FIFO registers */
+#define HSSPI_FIFO_SIZE 0x200
+#define HSSPI_FIFO_BASE (0x200 + \
+ (HSSPI_FIFO_SIZE * HSSPI_PP))
+
+/* SPI Ping-Pong FIFO OP register */
+#define HSSPI_FIFO_OP_SIZE 0x2
+#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
+#define HSSPI_FIFO_OP_BYTES_SHIFT 0
+#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
+#define HSSPI_FIFO_OP_MBIT_SHIFT 11
+#define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
+#define HSSPI_FIFO_OP_CODE_SHIFT 13
+#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
+
+struct bcm63xx_hsspi_priv {
+ void __iomem *regs;
+ ulong clk_rate;
+ uint8_t num_cs;
+ uint8_t cs_pols;
+ uint speed;
+};
+
+static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
+
+ if (cs >= priv->num_cs) {
+ printf("no cs %u\n", cs);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
+
+ /* clock polarity */
+ if (mode & SPI_CPOL)
+ setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+ else
+ clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+
+ return 0;
+}
+
+static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
+{
+ struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
+
+ priv->speed = speed;
+
+ return 0;
+}
+
+static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
+ struct dm_spi_slave_platdata *plat)
+{
+ uint32_t clr, set;
+
+ /* profile clock */
+ set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
+ set = DIV_ROUND_UP(2048, set);
+ set &= SPI_PFL_CLK_FREQ_MASK;
+ set |= SPI_PFL_CLK_RSTLOOP_MASK;
+ writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
+
+ /* profile signal */
+ set = 0;
+ clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
+ SPI_PFL_SIG_LATCHRIS_MASK |
+ SPI_PFL_SIG_ASYNCIN_MASK;
+
+ /* latch/launch config */
+ if (plat->mode & SPI_CPHA)
+ set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
+ else
+ set |= SPI_PFL_SIG_LATCHRIS_MASK;
+
+ /* async clk */
+ if (priv->speed > SPI_MAX_SYNC_CLOCK)
+ set |= SPI_PFL_SIG_ASYNCIN_MASK;
+
+ clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
+
+ /* global control */
+ set = 0;
+ clr = 0;
+
+ /* invert cs polarity */
+ if (priv->cs_pols & BIT(plat->cs))
+ clr |= BIT(plat->cs);
+ else
+ set |= BIT(plat->cs);
+
+ /* invert dummy cs polarity */
+ if (priv->cs_pols & BIT(!plat->cs))
+ clr |= BIT(!plat->cs);
+ else
+ set |= BIT(!plat->cs);
+
+ clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);
+}
+
+static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
+{
+ /* restore cs polarities */
+ clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
+ priv->cs_pols);
+}
+
+/*
+ * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
+ * because they are controlled by HW.
+ * However, it provides a mechanism to prepend write transfers prior to read
+ * transfers (with a maximum prepend of 15 bytes), which is usually enough for
+ * SPI-connected flashes since reading requires prepending a write transfer of
+ * 5 bytes. On the other hand it also provides a way to invert each CS
+ * polarity, not only between transfers like the older BCM63xx SPI driver, but
+ * also the rest of the time.
+ *
+ * Instead of using the prepend mechanism, this implementation inverts the
+ * polarity of both the desired CS and another dummy CS when the bus is
+ * claimed. This way, the dummy CS is restored to its inactive value when
+ * transfers are issued and the desired CS is preserved in its active value
+ * all the time. This hack is also used in the upstream linux driver and
+ * allows keeping CS active between trasnfers even if the HW doesn't give
+ * this possibility.
+ */
+static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ size_t data_bytes = bitlen / 8;
+ size_t step_size = HSSPI_FIFO_SIZE;
+ uint16_t opcode = 0;
+ uint32_t val;
+ const uint8_t *tx = dout;
+ uint8_t *rx = din;
+
+ if (flags & SPI_XFER_BEGIN)
+ bcm63xx_hsspi_activate_cs(priv, plat);
+
+ /* fifo operation */
+ if (tx && rx)
+ opcode = HSSPI_FIFO_OP_READ_WRITE;
+ else if (rx)
+ opcode = HSSPI_FIFO_OP_CODE_R;
+ else if (tx)
+ opcode = HSSPI_FIFO_OP_CODE_W;
+
+ if (opcode != HSSPI_FIFO_OP_CODE_R)
+ step_size -= HSSPI_FIFO_OP_SIZE;
+
+ /* dual mode */
+ if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
+ (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
+ opcode |= HSSPI_FIFO_OP_MBIT_MASK;
+
+ /* profile mode */
+ val = SPI_PFL_MODE_FILL_MASK |
+ SPI_PFL_MODE_MDRDSZ_MASK |
+ SPI_PFL_MODE_MDWRSZ_MASK;
+ if (plat->mode & SPI_3WIRE)
+ val |= SPI_PFL_MODE_3WIRE_MASK;
+ writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
+
+ /* transfer loop */
+ while (data_bytes > 0) {
+ size_t curr_step = min(step_size, data_bytes);
+ int ret;
+
+ /* copy tx data */
+ if (tx) {
+ memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
+ HSSPI_FIFO_OP_SIZE, tx, curr_step);
+ tx += curr_step;
+ }
+
+ /* set fifo operation */
+ writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK),
+ priv->regs + HSSPI_FIFO_OP_REG);
+
+ /* issue the transfer */
+ val = SPI_CMD_OP_START;
+ val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
+ SPI_CMD_PFL_MASK;
+ val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
+ SPI_CMD_SLAVE_MASK;
+ writel_be(val, priv->regs + SPI_CMD_REG);
+
+ /* wait for completion */
+ ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG,
+ SPI_STAT_SRCBUSY_MASK, false,
+ 1000, false);
+ if (ret) {
+ printf("interrupt timeout\n");
+ return ret;
+ }
+
+ /* copy rx data */
+ if (rx) {
+ memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
+ curr_step);
+ rx += curr_step;
+ }
+
+ data_bytes -= curr_step;
+ }
+
+ if (flags & SPI_XFER_END)
+ bcm63xx_hsspi_deactivate_cs(priv);
+
+ return 0;
+}
+
+static const struct dm_spi_ops bcm63xx_hsspi_ops = {
+ .cs_info = bcm63xx_hsspi_cs_info,
+ .set_mode = bcm63xx_hsspi_set_mode,
+ .set_speed = bcm63xx_hsspi_set_speed,
+ .xfer = bcm63xx_hsspi_xfer,
+};
+
+static const struct udevice_id bcm63xx_hsspi_ids[] = {
+ { .compatible = "brcm,bcm6328-hsspi", },
+ { /* sentinel */ }
+};
+
+static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
+{
+ struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+
+ /* check cs */
+ if (plat->cs >= priv->num_cs) {
+ printf("no cs %u\n", plat->cs);
+ return -ENODEV;
+ }
+
+ /* cs polarity */
+ if (plat->mode & SPI_CS_HIGH)
+ priv->cs_pols |= BIT(plat->cs);
+ else
+ priv->cs_pols &= ~BIT(plat->cs);
+
+ return 0;
+}
+
+static int bcm63xx_hsspi_probe(struct udevice *dev)
+{
+ struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
+ "num-cs", 8);
+
+ /* enable clock */
+ ret = clk_get_by_name(dev, "hsspi", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* get clock rate */
+ ret = clk_get_by_name(dev, "pll", &clk);
+ if (ret < 0)
+ return ret;
+
+ priv->clk_rate = clk_get_rate(&clk);
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ /* initialize hardware */
+ writel_be(0, priv->regs + SPI_IR_MASK_REG);
+
+ /* clear pending interrupts */
+ writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
+
+ /* enable clk gate */
+ setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
+
+ /* read default cs polarities */
+ priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &
+ SPI_CTL_CS_POL_MASK;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm63xx_hsspi) = {
+ .name = "bcm63xx_hsspi",
+ .id = UCLASS_SPI,
+ .of_match = bcm63xx_hsspi_ids,
+ .ops = &bcm63xx_hsspi_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
+ .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
+ .probe = bcm63xx_hsspi_probe,
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx.c:
+ * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <spi.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* BCM6348 SPI core */
+#define SPI_6348_CLK 0x06
+#define SPI_6348_CMD 0x00
+#define SPI_6348_CTL 0x40
+#define SPI_6348_CTL_SHIFT 6
+#define SPI_6348_FILL 0x07
+#define SPI_6348_IR_MASK 0x04
+#define SPI_6348_IR_STAT 0x02
+#define SPI_6348_RX 0x80
+#define SPI_6348_RX_SIZE 0x3f
+#define SPI_6348_TX 0x41
+#define SPI_6348_TX_SIZE 0x3f
+
+/* BCM6358 SPI core */
+#define SPI_6358_CLK 0x706
+#define SPI_6358_CMD 0x700
+#define SPI_6358_CTL 0x000
+#define SPI_6358_CTL_SHIFT 14
+#define SPI_6358_FILL 0x707
+#define SPI_6358_IR_MASK 0x702
+#define SPI_6358_IR_STAT 0x704
+#define SPI_6358_RX 0x400
+#define SPI_6358_RX_SIZE 0x220
+#define SPI_6358_TX 0x002
+#define SPI_6358_TX_SIZE 0x21e
+
+/* SPI Clock register */
+#define SPI_CLK_SHIFT 0
+#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT)
+#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT)
+#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT)
+#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT)
+#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT)
+#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT)
+#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT)
+#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT)
+#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT)
+#define SPI_CLK_SSOFF_SHIFT 3
+#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT)
+#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
+#define SPI_CLK_BSWAP_SHIFT 7
+#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
+
+/* SPI Command register */
+#define SPI_CMD_OP_SHIFT 0
+#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT)
+#define SPI_CMD_SLAVE_SHIFT 4
+#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT)
+#define SPI_CMD_PREPEND_SHIFT 8
+#define SPI_CMD_PREPEND_BYTES 0xf
+#define SPI_CMD_3WIRE_SHIFT 12
+#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)
+
+/* SPI Control register */
+#define SPI_CTL_TYPE_FD_RW 0
+#define SPI_CTL_TYPE_HD_W 1
+#define SPI_CTL_TYPE_HD_R 2
+
+/* SPI Interrupt registers */
+#define SPI_IR_DONE_SHIFT 0
+#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT)
+#define SPI_IR_RXOVER_SHIFT 1
+#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT)
+#define SPI_IR_TXUNDER_SHIFT 2
+#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT)
+#define SPI_IR_TXOVER_SHIFT 3
+#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT)
+#define SPI_IR_RXUNDER_SHIFT 4
+#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT)
+#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\
+ SPI_IR_RXOVER_MASK |\
+ SPI_IR_TXUNDER_MASK |\
+ SPI_IR_TXOVER_MASK |\
+ SPI_IR_RXUNDER_MASK)
+
+enum bcm63xx_regs_spi {
+ SPI_CLK,
+ SPI_CMD,
+ SPI_CTL,
+ SPI_CTL_SHIFT,
+ SPI_FILL,
+ SPI_IR_MASK,
+ SPI_IR_STAT,
+ SPI_RX,
+ SPI_RX_SIZE,
+ SPI_TX,
+ SPI_TX_SIZE,
+};
+
+struct bcm63xx_spi_priv {
+ const unsigned long *regs;
+ void __iomem *base;
+ size_t tx_bytes;
+ uint8_t num_cs;
+};
+
+#define SPI_CLK_CNT 8
+static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {
+ { 25000000, SPI_CLK_25MHZ },
+ { 20000000, SPI_CLK_20MHZ },
+ { 12500000, SPI_CLK_12_50MHZ },
+ { 6250000, SPI_CLK_6_250MHZ },
+ { 3125000, SPI_CLK_3_125MHZ },
+ { 1563000, SPI_CLK_1_563MHZ },
+ { 781000, SPI_CLK_0_781MHZ },
+ { 391000, SPI_CLK_0_391MHZ }
+};
+
+static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
+
+ if (cs >= priv->num_cs) {
+ printf("no cs %u\n", cs);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
+ const unsigned long *regs = priv->regs;
+
+ if (mode & SPI_LSB_FIRST)
+ setbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
+ else
+ clrbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
+
+ return 0;
+}
+
+static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
+ const unsigned long *regs = priv->regs;
+ uint8_t clk_cfg;
+ int i;
+
+ /* default to lowest clock configuration */
+ clk_cfg = SPI_CLK_0_391MHZ;
+
+ /* find the closest clock configuration */
+ for (i = 0; i < SPI_CLK_CNT; i++) {
+ if (speed >= bcm63xx_spi_freq_table[i][0]) {
+ clk_cfg = bcm63xx_spi_freq_table[i][1];
+ break;
+ }
+ }
+
+ /* write clock configuration */
+ clrsetbits_8(priv->base + regs[SPI_CLK],
+ SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
+ clk_cfg | SPI_CLK_SSOFF_2);
+
+ return 0;
+}
+
+/*
+ * BCM63xx SPI driver doesn't allow keeping CS active between transfers since
+ * they are HW controlled.
+ * However, it provides a mechanism to prepend write transfers prior to read
+ * transfers (with a maximum prepend of 15 bytes), which is usually enough for
+ * SPI-connected flashes since reading requires prepending a write transfer of
+ * 5 bytes.
+ *
+ * This implementation takes advantage of the prepend mechanism and combines
+ * multiple transfers into a single one where possible (single/multiple write
+ * transfer(s) followed by a final read/write transfer).
+ * However, it's not possible to buffer reads, which means that read transfers
+ * should always be done as the final ones.
+ * On the other hand, take into account that combining write transfers into
+ * a single one is just buffering and doesn't require prepend mechanism.
+ */
+static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
+ const unsigned long *regs = priv->regs;
+ size_t data_bytes = bitlen / 8;
+
+ if (flags & SPI_XFER_BEGIN) {
+ /* clear prepends */
+ priv->tx_bytes = 0;
+
+ /* initialize hardware */
+ writeb_be(0, priv->base + regs[SPI_IR_MASK]);
+ }
+
+ if (din) {
+ /* buffering reads not possible since cs is hw controlled */
+ if (!(flags & SPI_XFER_END)) {
+ printf("unable to buffer reads\n");
+ return -EINVAL;
+ }
+
+ /* check rx size */
+ if (data_bytes > regs[SPI_RX_SIZE]) {
+ printf("max rx bytes exceeded\n");
+ return -EMSGSIZE;
+ }
+ }
+
+ if (dout) {
+ /* check tx size */
+ if (priv->tx_bytes + data_bytes > regs[SPI_TX_SIZE]) {
+ printf("max tx bytes exceeded\n");
+ return -EMSGSIZE;
+ }
+
+ /* copy tx data */
+ memcpy_toio(priv->base + regs[SPI_TX] + priv->tx_bytes,
+ dout, data_bytes);
+ priv->tx_bytes += data_bytes;
+ }
+
+ if (flags & SPI_XFER_END) {
+ struct dm_spi_slave_platdata *plat =
+ dev_get_parent_platdata(dev);
+ uint16_t val, cmd;
+ int ret;
+
+ /* determine control config */
+ if (dout && !din) {
+ /* buffered write transfers */
+ val = priv->tx_bytes;
+ val |= (SPI_CTL_TYPE_HD_W << regs[SPI_CTL_SHIFT]);
+ priv->tx_bytes = 0;
+ } else {
+ if (dout && din && (flags & SPI_XFER_ONCE)) {
+ /* full duplex read/write */
+ val = data_bytes;
+ val |= (SPI_CTL_TYPE_FD_RW <<
+ regs[SPI_CTL_SHIFT]);
+ priv->tx_bytes = 0;
+ } else {
+ /* prepended write transfer */
+ val = data_bytes;
+ val |= (SPI_CTL_TYPE_HD_R <<
+ regs[SPI_CTL_SHIFT]);
+ if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
+ printf("max prepend bytes exceeded\n");
+ return -EMSGSIZE;
+ }
+ }
+ }
+
+ if (regs[SPI_CTL_SHIFT] >= 8)
+ writew_be(val, priv->base + regs[SPI_CTL]);
+ else
+ writeb_be(val, priv->base + regs[SPI_CTL]);
+
+ /* clear interrupts */
+ writeb_be(SPI_IR_CLEAR_MASK, priv->base + regs[SPI_IR_STAT]);
+
+ /* issue the transfer */
+ cmd = SPI_CMD_OP_START;
+ cmd |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
+ cmd |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
+ if (plat->mode & SPI_3WIRE)
+ cmd |= SPI_CMD_3WIRE_MASK;
+ writew_be(cmd, priv->base + regs[SPI_CMD]);
+
+ /* enable interrupts */
+ writeb_be(SPI_IR_DONE_MASK, priv->base + regs[SPI_IR_MASK]);
+
+ ret = wait_for_bit_8(priv->base + regs[SPI_IR_STAT],
+ SPI_IR_DONE_MASK, true, 1000, false);
+ if (ret) {
+ printf("interrupt timeout\n");
+ return ret;
+ }
+
+ /* copy rx data */
+ if (din)
+ memcpy_fromio(din, priv->base + regs[SPI_RX],
+ data_bytes);
+ }
+
+ return 0;
+}
+
+static const struct dm_spi_ops bcm63xx_spi_ops = {
+ .cs_info = bcm63xx_spi_cs_info,
+ .set_mode = bcm63xx_spi_set_mode,
+ .set_speed = bcm63xx_spi_set_speed,
+ .xfer = bcm63xx_spi_xfer,
+};
+
+static const unsigned long bcm6348_spi_regs[] = {
+ [SPI_CLK] = SPI_6348_CLK,
+ [SPI_CMD] = SPI_6348_CMD,
+ [SPI_CTL] = SPI_6348_CTL,
+ [SPI_CTL_SHIFT] = SPI_6348_CTL_SHIFT,
+ [SPI_FILL] = SPI_6348_FILL,
+ [SPI_IR_MASK] = SPI_6348_IR_MASK,
+ [SPI_IR_STAT] = SPI_6348_IR_STAT,
+ [SPI_RX] = SPI_6348_RX,
+ [SPI_RX_SIZE] = SPI_6348_RX_SIZE,
+ [SPI_TX] = SPI_6348_TX,
+ [SPI_TX_SIZE] = SPI_6348_TX_SIZE,
+};
+
+static const unsigned long bcm6358_spi_regs[] = {
+ [SPI_CLK] = SPI_6358_CLK,
+ [SPI_CMD] = SPI_6358_CMD,
+ [SPI_CTL] = SPI_6358_CTL,
+ [SPI_CTL_SHIFT] = SPI_6358_CTL_SHIFT,
+ [SPI_FILL] = SPI_6358_FILL,
+ [SPI_IR_MASK] = SPI_6358_IR_MASK,
+ [SPI_IR_STAT] = SPI_6358_IR_STAT,
+ [SPI_RX] = SPI_6358_RX,
+ [SPI_RX_SIZE] = SPI_6358_RX_SIZE,
+ [SPI_TX] = SPI_6358_TX,
+ [SPI_TX_SIZE] = SPI_6358_TX_SIZE,
+};
+
+static const struct udevice_id bcm63xx_spi_ids[] = {
+ {
+ .compatible = "brcm,bcm6348-spi",
+ .data = (ulong)&bcm6348_spi_regs,
+ }, {
+ .compatible = "brcm,bcm6358-spi",
+ .data = (ulong)&bcm6358_spi_regs,
+ }, { /* sentinel */ }
+};
+
+static int bcm63xx_spi_child_pre_probe(struct udevice *dev)
+{
+ struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
+ const unsigned long *regs = priv->regs;
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+
+ /* check cs */
+ if (plat->cs >= priv->num_cs) {
+ printf("no cs %u\n", plat->cs);
+ return -ENODEV;
+ }
+
+ /* max read/write sizes */
+ slave->max_read_size = regs[SPI_RX_SIZE];
+ slave->max_write_size = regs[SPI_TX_SIZE];
+
+ return 0;
+}
+
+static int bcm63xx_spi_probe(struct udevice *dev)
+{
+ struct bcm63xx_spi_priv *priv = dev_get_priv(dev);
+ const unsigned long *regs =
+ (const unsigned long *)dev_get_driver_data(dev);
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = regs;
+ priv->base = ioremap(addr, size);
+ priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
+ "num-cs", 8);
+
+ /* enable clock */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ /* initialize hardware */
+ writeb_be(0, priv->base + regs[SPI_IR_MASK]);
+
+ /* set fill register */
+ writeb_be(0xff, priv->base + regs[SPI_FILL]);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm63xx_spi) = {
+ .name = "bcm63xx_spi",
+ .id = UCLASS_SPI,
+ .of_match = bcm63xx_spi_ids,
+ .ops = &bcm63xx_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv),
+ .child_pre_probe = bcm63xx_spi_child_pre_probe,
+ .probe = bcm63xx_spi_probe,
+};
/* Set Chip select */
cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
- CONFIG_CQSPI_DECODER);
+ plat->is_decoded_cs);
if ((flags & SPI_XFER_END) || (flags == 0)) {
if (priv->cmd_len == 0) {
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
- plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
+ plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs");
+ plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128);
+ plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4);
+ plat->trigger_address = fdtdec_get_uint(blob, node,
+ "cdns,trigger-address", 0);
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
500000);
/* Read other parameters from DT */
- plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
- plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
- plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
- plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
- plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
- plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
+ plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256);
+ plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16);
+ plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200);
+ plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255);
+ plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20);
+ plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
unsigned int max_hz;
void *regbase;
void *ahbbase;
+ bool is_decoded_cs;
+ u32 fifo_depth;
+ u32 fifo_width;
+ u32 trigger_address;
+ /* Flash parameters */
u32 page_size;
u32 block_size;
u32 tshsl_ns;
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
- u32 sram_size;
};
struct cadence_spi_priv {
#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
-#include <bouncebuf.h>
+#include <malloc.h>
#include "cadence_qspi.h"
#define CQSPI_REG_POLL_US 1 /* 1us */
#define CQSPI_REG_RETRY 10000
#define CQSPI_POLL_IDLE_RETRY 3
-#define CQSPI_FIFO_WIDTH 4
-
-#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
-
/* Transfer mode */
#define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
-#define CQSPI_REG_SRAM_FILL_THRESHOLD \
- ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
-
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/
writel(0, plat->regbase + CQSPI_REG_REMAP);
/* Indirect mode configurations */
- writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+ writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
{
unsigned int remaining = n_rx;
unsigned int bytes_to_read = 0;
- struct bounce_buffer bb;
- u8 *bb_rxbuf;
int ret;
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD);
- ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
- if (ret)
- return ret;
- bb_rxbuf = bb.bounce_buffer;
-
while (remaining > 0) {
ret = cadence_qspi_wait_for_data(plat);
if (ret < 0) {
bytes_to_read = ret;
while (bytes_to_read != 0) {
- bytes_to_read *= CQSPI_FIFO_WIDTH;
+ bytes_to_read *= plat->fifo_width;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
- readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
- if (bytes_to_read % 4)
- readsb(plat->ahbbase,
- bb_rxbuf + rounddown(bytes_to_read, 4),
- bytes_to_read % 4);
-
- bb_rxbuf += bytes_to_read;
+ /*
+ * Handle non-4-byte aligned access to avoid
+ * data abort.
+ */
+ if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
+ readsb(plat->ahbbase, rxbuf, bytes_to_read);
+ else
+ readsl(plat->ahbbase, rxbuf,
+ bytes_to_read >> 2);
+ rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
}
}
/* Check indirect done status */
- ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+ CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
if (ret) {
printf("Indirect read completion error (%i)\n", ret);
goto failrd;
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
- bounce_buffer_stop(&bb);
return 0;
/* Cancel the indirect read */
writel(CQSPI_REG_INDIRECTRD_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTRD);
- bounce_buffer_stop(&bb);
return ret;
}
return -EINVAL;
}
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
{
unsigned int page_size = plat->page_size;
unsigned int remaining = n_tx;
+ const u8 *bb_txbuf = txbuf;
+ void *bounce_buf = NULL;
unsigned int write_bytes;
int ret;
- struct bounce_buffer bb;
- u8 *bb_txbuf;
/*
- * Handle non-4-byte aligned accesses via bounce buffer to
- * avoid data abort.
+ * Use bounce buffer for non 32 bit aligned txbuf to avoid data
+ * aborts
*/
- ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
- if (ret)
- return ret;
- bb_txbuf = bb.bounce_buffer;
+ if ((uintptr_t)txbuf % 4) {
+ bounce_buf = malloc(n_tx);
+ if (!bounce_buf)
+ return -ENOMEM;
+ memcpy(bounce_buf, txbuf, n_tx);
+ bb_txbuf = bounce_buf;
+ }
/* Configure the indirect read transfer bytes */
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
bb_txbuf + rounddown(write_bytes, 4),
write_bytes % 4);
- ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
- CQSPI_REG_SDRAMLEVEL_WR_MASK <<
- CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
+ CQSPI_REG_SDRAMLEVEL_WR_MASK <<
+ CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
if (ret) {
printf("Indirect write timed out (%i)\n", ret);
goto failwr;
}
/* Check indirect done status */
- ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
- CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+ CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
if (ret) {
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
}
- bounce_buffer_stop(&bb);
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ if (bounce_buf)
+ free(bounce_buf);
return 0;
failwr:
/* Cancel the indirect write */
writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR);
- bounce_buffer_stop(&bb);
+ if (bounce_buf)
+ free(bounce_buf);
return ret;
}
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <fdtdec.h>
#include <linux/compat.h>
#include <asm/io.h>
-#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
void __iomem *regs;
unsigned int freq; /* Default frequency */
unsigned int mode;
+ struct clk clk;
+ unsigned long bus_clk_rate;
int bits_per_word;
u8 cs; /* chip select pin */
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
}
+/*
+ * We define dw_spi_get_clk function as 'weak' as some targets
+ * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
+ * and implement dw_spi_get_clk their own way in their clock manager.
+ */
+__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+ return ret;
+
+ *rate = clk_get_rate(&priv->clk);
+ if (!*rate)
+ goto err_rate;
+
+ debug("%s: get spi controller clk via device tree: %lu Hz\n",
+ __func__, *rate);
+
+ return 0;
+
+err_rate:
+ clk_disable(&priv->clk);
+ clk_free(&priv->clk);
+
+ return -EINVAL;
+}
+
static int dw_spi_probe(struct udevice *bus)
{
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
priv->regs = plat->regs;
priv->freq = plat->frequency;
+ ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
+ if (ret)
+ return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
spi_enable_chip(priv, 0);
/* clk_div doesn't support odd number */
- clk_div = cm_get_spi_controller_clk_hz() / speed;
+ clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_writel(priv, DW_SPI_BAUDR, clk_div);
priv->num_chipselect = plat->num_chipselect;
/* make sure controller is not busy anywhere */
- ret = wait_for_bit(__func__, &priv->regs->sr,
- QSPI_SR_BUSY_MASK |
- QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK,
- false, 100, false);
+ ret = wait_for_bit_le32(&priv->regs->sr,
+ QSPI_SR_BUSY_MASK |
+ QSPI_SR_AHB_ACC_MASK |
+ QSPI_SR_IP_ACC_MASK,
+ false, 100, false);
if (ret) {
debug("ERROR : The controller is busy\n");
priv = dev_get_priv(bus);
/* make sure controller is not busy anywhere */
- ret = wait_for_bit(__func__, &priv->regs->sr,
- QSPI_SR_BUSY_MASK |
- QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK,
- false, 100, false);
+ ret = wait_for_bit_le32(&priv->regs->sr,
+ QSPI_SR_BUSY_MASK |
+ QSPI_SR_AHB_ACC_MASK |
+ QSPI_SR_IP_ACC_MASK,
+ false, 100, false);
if (ret) {
debug("ERROR : The controller is busy\n");
/* Here now the DM part */
+struct mvebu_spi_dev {
+ bool is_errata_50mhz_ac;
+};
+
struct mvebu_spi_platdata {
struct kwspi_registers *spireg;
};
return 0;
}
+static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data;
+
+ /*
+ * Erratum description: (Erratum NO. FE-9144572) The device
+ * SPI interface supports frequencies of up to 50 MHz.
+ * However, due to this erratum, when the device core clock is
+ * 250 MHz and the SPI interfaces is configured for 50MHz SPI
+ * clock and CPOL=CPHA=1 there might occur data corruption on
+ * reads from the SPI device.
+ * Erratum Workaround:
+ * Work in one of the following configurations:
+ * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
+ * Register".
+ * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
+ * Register" before setting the interface.
+ */
+ data = readl(®->timing1);
+ data &= ~KW_SPI_TMISO_SAMPLE_MASK;
+
+ if (CONFIG_SYS_TCLK == 250000000 &&
+ mode & SPI_CPOL &&
+ mode & SPI_CPHA)
+ data |= KW_SPI_TMISO_SAMPLE_2;
+ else
+ data |= KW_SPI_TMISO_SAMPLE_1;
+
+ writel(data, ®->timing1);
+}
+
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
struct kwspi_registers *reg = plat->spireg;
+ const struct mvebu_spi_dev *drvdata;
u32 data = readl(®->cfg);
data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
writel(data, ®->cfg);
+ drvdata = (struct mvebu_spi_dev *)dev_get_driver_data(bus);
+ if (drvdata->is_errata_50mhz_ac)
+ mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
+
return 0;
}
*/
};
+static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
+ .is_errata_50mhz_ac = false,
+};
+
+static const struct mvebu_spi_dev armada_375_spi_dev_data = {
+ .is_errata_50mhz_ac = false,
+};
+
+static const struct mvebu_spi_dev armada_380_spi_dev_data = {
+ .is_errata_50mhz_ac = true,
+};
+
static const struct udevice_id mvebu_spi_ids[] = {
- { .compatible = "marvell,armada-375-spi" },
- { .compatible = "marvell,armada-380-spi" },
- { .compatible = "marvell,armada-xp-spi" },
+ {
+ .compatible = "marvell,armada-375-spi",
+ .data = (ulong)&armada_375_spi_dev_data
+ },
+ {
+ .compatible = "marvell,armada-380-spi",
+ .data = (ulong)&armada_380_spi_dev_data
+ },
+ {
+ .compatible = "marvell,armada-xp-spi",
+ .data = (ulong)&armada_xp_spi_dev_data
+ },
{ }
};
din_8 = din;
while (bytelen) {
- ret = wait_for_bit(__func__, ®->ctrl,
- MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+ ret = wait_for_bit_le32(®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true,100, false);
if (ret)
return ret;
writel(pending_dout, ®->dout);
if (din) {
- ret = wait_for_bit(__func__, ®->ctrl,
- MVEBU_SPI_A3700_XFER_RDY,
- true, 100, false);
+ ret = wait_for_bit_le32(®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true, 100, false);
if (ret)
return ret;
/* Deactivate CS */
if (flags & SPI_XFER_END) {
- ret = wait_for_bit(__func__, ®->ctrl,
- MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+ ret = wait_for_bit_le32(®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true, 100, false);
if (ret)
return ret;
/* Flush read/write FIFO */
data = readl(®->cfg);
writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, ®->cfg);
- ret = wait_for_bit(__func__, ®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
- false, 1000, false);
+ ret = wait_for_bit_le32(®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
+ false, 1000, false);
if (ret)
return ret;
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
struct spi_slave *slave = dev_get_parent_priv(dev);
int speed;
- int ret;
speed = slave->max_hz;
if (spi->max_hz) {
if (!speed)
speed = 100000;
if (speed != slave->speed) {
- ret = spi_set_speed_mode(bus, speed, slave->mode);
+ int ret = spi_set_speed_mode(bus, speed, slave->mode);
+
if (ret)
return ret;
slave->speed = speed;
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
-
if (ops->claim_bus)
ops->claim_bus += gd->reloc_off;
if (ops->release_bus)
}
/* Compatibility function - to be removed */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
- int bus_node)
-{
- struct udevice *bus, *dev;
- int ret;
-
- ret = uclass_get_device_by_of_offset(UCLASS_SPI, bus_node, &bus);
- if (ret)
- return NULL;
- ret = device_get_child_by_of_offset(bus, node, &dev);
- if (ret)
- return NULL;
- return dev_get_parent_priv(dev);
-}
-
-/* Compatibility function - to be removed */
struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
unsigned int speed, unsigned int mode)
{
int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen)
{
if (wordlen == 0 || wordlen > 32) {
- printf("spi: invalid wordlen %d\n", wordlen);
+ printf("spi: invalid wordlen %u\n", wordlen);
return -1;
}
void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
unsigned int cs)
{
- struct spi_slave *slave;
- void *ptr;
+ u8 *ptr;
ptr = malloc(size);
if (ptr) {
+ struct spi_slave *slave;
+
memset(ptr, '\0', size);
slave = (struct spi_slave *)(ptr + offset);
slave->bus = bus;
return ptr;
}
-
-#ifdef CONFIG_OF_SPI
-struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
- int node)
-{
- int cs, max_hz, mode = 0;
-
- cs = fdtdec_get_int(blob, node, "reg", -1);
- max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 100000);
- if (fdtdec_get_bool(blob, node, "spi-cpol"))
- mode |= SPI_CPOL;
- if (fdtdec_get_bool(blob, node, "spi-cpha"))
- mode |= SPI_CPHA;
- if (fdtdec_get_bool(blob, node, "spi-cs-high"))
- mode |= SPI_CS_HIGH;
- if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
- mode |= SPI_PREAMBLE;
- return spi_setup_slave(busnum, cs, max_hz, mode);
-}
-#endif
source "drivers/usb/dwc3/Kconfig"
+source "drivers/usb/musb/Kconfig"
+
source "drivers/usb/musb-new/Kconfig"
source "drivers/usb/emul/Kconfig"
+source "drivers/usb/phy/Kconfig"
+
source "drivers/usb/ulpi/Kconfig"
comment "USB peripherals"
obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o
obj-$(CONFIG_USB_ATMEL) += ohci-at91.o
obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
-obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
®s->grstctl);
- ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
+ false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
int ret;
writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
- ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
+ false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
int ret;
/* Wait for AHB master IDLE state. */
- ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
+ true, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
/* Core Soft Reset */
writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
- ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
+ false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
clrsetbits_le32(®s->hc_regs[i].hcchar,
DWC2_HCCHAR_EPDIR,
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
- ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar,
- DWC2_HCCHAR_CHEN, false, 1000, false);
+ ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
+ DWC2_HCCHAR_CHEN, false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
}
int ret;
uint32_t hcint, hctsiz;
- ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
- 1000, false);
+ ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
+ 1000, false);
if (ret)
return ret;
setbits_le32(&ehci->usbcmd, CMD_RESET);
/* Wait for reset */
- if (wait_for_bit(__func__, &ehci->usbcmd, CMD_RESET, false, 30,
- false)) {
+ if (wait_for_bit_le32(&ehci->usbcmd, CMD_RESET, false, 30, false)) {
printf("Stuck on USB reset.\n");
return -ETIMEDOUT;
}
/* Stop then Reset */
clrbits_le32(usb_cmd, UCMD_RUN_STOP);
- ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
- false);
+ ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
if (ret)
return ret;
setbits_le32(usb_cmd, UCMD_RESET);
- ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
+ ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
if (ret)
return ret;
tmp = ehci_readl(&hcor->or_usbcmd);
tmp &= ~CMD_RUN;
- ehci_writel(tmp, &hcor->or_usbcmd);
+ ehci_writel(&hcor->or_usbcmd, tmp);
/* Disable the PHY */
tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
+++ /dev/null
-/*
- * ISP116x HCD (Host Controller Driver) for u-boot.
- *
- * Copyright (C) 2006-2007 Rodolfo Giometti <giometti@linux.it>
- * Copyright (C) 2006-2007 Eurotech S.p.A. <info@eurotech.it>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
- * (original copyright message follows):
- *
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This code is based on linux driver for sl811hs chip, source at
- * drivers/usb/host/sl811.c:
- *
- * SL811 Host Controller Interface driver for USB.
- *
- * Copyright (c) 2003/06, Courage Co., Ltd.
- *
- * Based on:
- * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap,
- * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber,
- * Adam Richter, Gregory P. Smith;
- * 2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com>
- * 3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn>
- *
- * [[GNU/GPL disclaimer]]
- *
- * and in part from AU1x00 OHCI HCD driver "u-boot/arch/mips/cpu/au1x00_usb_ohci.c"
- * (original copyright message follows):
- *
- * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * [[GNU/GPL disclaimer]]
- *
- * Note: Part of this code has been derived from linux
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <usb.h>
-#include <malloc.h>
-#include <linux/list.h>
-
-/*
- * ISP116x chips require certain delays between accesses to its
- * registers. The following timing options exist.
- *
- * 1. Configure your memory controller (the best)
- * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
- *
- * Value is in microseconds.
- */
-#ifdef ISP116X_HCD_USE_UDELAY
-#define UDELAY 1
-#endif
-
-/*
- * On some (slowly?) machines an extra delay after data packing into
- * controller's FIFOs is required, * otherwise you may get the following
- * error:
- *
- * uboot> usb start
- * (Re)start USB...
- * USB: scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
- * isp116x: isp116x_submit_job: ****** FIFO not ready! ******
- *
- * USB device not responding, giving up (status=4)
- * isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- * isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- * isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- * 3 USB Device(s) found
- * scanning bus for storage devices... 0 Storage Device(s) found
- *
- * Value is in milliseconds.
- */
-#ifdef ISP116X_HCD_USE_EXTRA_DELAY
-#define EXTRA_DELAY 2
-#endif
-
-/*
- * Enable the following defines if you wish enable debugging messages.
- */
-#undef DEBUG /* enable debugging messages */
-#undef TRACE /* enable tracing code */
-#undef VERBOSE /* verbose debugging messages */
-
-#include "isp116x.h"
-
-#define DRIVER_VERSION "08 Jan 2007"
-static const char hcd_name[] = "isp116x-hcd";
-
-struct isp116x isp116x_dev;
-struct isp116x_platform_data isp116x_board;
-static int got_rhsc; /* root hub status change */
-struct usb_device *devgone; /* device which was disconnected */
-static int rh_devnum; /* address of Root Hub endpoint */
-
-/* ------------------------------------------------------------------------- */
-
-static int isp116x_reset(struct isp116x *isp116x);
-
-/* --- Debugging functions ------------------------------------------------- */
-
-#define isp116x_show_reg(d, r) { \
- if ((r) < 0x20) { \
- DBG("%-12s[%02x]: %08x", #r, \
- r, isp116x_read_reg32(d, r)); \
- } else { \
- DBG("%-12s[%02x]: %04x", #r, \
- r, isp116x_read_reg16(d, r)); \
- } \
-}
-
-#define isp116x_show_regs(d) { \
- isp116x_show_reg(d, HCREVISION); \
- isp116x_show_reg(d, HCCONTROL); \
- isp116x_show_reg(d, HCCMDSTAT); \
- isp116x_show_reg(d, HCINTSTAT); \
- isp116x_show_reg(d, HCINTENB); \
- isp116x_show_reg(d, HCFMINTVL); \
- isp116x_show_reg(d, HCFMREM); \
- isp116x_show_reg(d, HCFMNUM); \
- isp116x_show_reg(d, HCLSTHRESH); \
- isp116x_show_reg(d, HCRHDESCA); \
- isp116x_show_reg(d, HCRHDESCB); \
- isp116x_show_reg(d, HCRHSTATUS); \
- isp116x_show_reg(d, HCRHPORT1); \
- isp116x_show_reg(d, HCRHPORT2); \
- isp116x_show_reg(d, HCHWCFG); \
- isp116x_show_reg(d, HCDMACFG); \
- isp116x_show_reg(d, HCXFERCTR); \
- isp116x_show_reg(d, HCuPINT); \
- isp116x_show_reg(d, HCuPINTENB); \
- isp116x_show_reg(d, HCCHIPID); \
- isp116x_show_reg(d, HCSCRATCH); \
- isp116x_show_reg(d, HCITLBUFLEN); \
- isp116x_show_reg(d, HCATLBUFLEN); \
- isp116x_show_reg(d, HCBUFSTAT); \
- isp116x_show_reg(d, HCRDITL0LEN); \
- isp116x_show_reg(d, HCRDITL1LEN); \
-}
-
-#if defined(TRACE)
-
-static int isp116x_get_current_frame_number(struct usb_device *usb_dev)
-{
- struct isp116x *isp116x = &isp116x_dev;
-
- return isp116x_read_reg32(isp116x, HCFMNUM);
-}
-
-static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int len, char *str)
-{
-#if defined(VERBOSE)
- int i;
-#endif
-
- DBG("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d stat:%#lx",
- str,
- isp116x_get_current_frame_number(dev),
- usb_pipedevice(pipe),
- usb_pipeendpoint(pipe),
- usb_pipeout(pipe) ? 'O' : 'I',
- usb_pipetype(pipe) < 2 ?
- (usb_pipeint(pipe) ?
- "INTR" : "ISOC") :
- (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status);
-#if defined(VERBOSE)
- if (len > 0 && buffer) {
- printf(__FILE__ ": data(%d):", len);
- for (i = 0; i < 16 && i < len; i++)
- printf(" %02x", ((__u8 *) buffer)[i]);
- printf("%s\n", i < len ? "..." : "");
- }
-#endif
-}
-
-#define PTD_DIR_STR(ptd) ({char __c; \
- switch(PTD_GET_DIR(ptd)){ \
- case 0: __c = 's'; break; \
- case 1: __c = 'o'; break; \
- default: __c = 'i'; break; \
- }; __c;})
-
-/*
- Dump PTD info. The code documents the format
- perfectly, right :)
-*/
-static inline void dump_ptd(struct ptd *ptd)
-{
-#if defined(VERBOSE)
- int k;
-#endif
-
- DBG("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x",
- PTD_GET_CC(ptd),
- PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
- PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
- PTD_GET_TOGGLE(ptd),
- PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
-#if defined(VERBOSE)
- printf("isp116x: %s: PTD(byte): ", __FUNCTION__);
- for (k = 0; k < sizeof(struct ptd); ++k)
- printf("%02x ", ((u8 *) ptd)[k]);
- printf("\n");
-#endif
-}
-
-static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
-{
-#if defined(VERBOSE)
- int k;
-
- if (type == 0 /* 0ut data */ ) {
- printf("isp116x: %s: out data: ", __FUNCTION__);
- for (k = 0; k < PTD_GET_LEN(ptd); ++k)
- printf("%02x ", ((u8 *) buf)[k]);
- printf("\n");
- }
- if (type == 1 /* 1n data */ ) {
- printf("isp116x: %s: in data: ", __FUNCTION__);
- for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
- printf("%02x ", ((u8 *) buf)[k]);
- printf("\n");
- }
-
- if (PTD_GET_LAST(ptd))
- DBG("--- last PTD ---");
-#endif
-}
-
-#else
-
-#define dump_msg(dev, pipe, buffer, len, str) do { } while (0)
-#define dump_pkt(dev, pipe, buffer, len, setup, str, small) do {} while (0)
-
-#define dump_ptd(ptd) do {} while (0)
-#define dump_ptd_data(ptd, buf, type) do {} while (0)
-
-#endif
-
-/* --- Virtual Root Hub ---------------------------------------------------- */
-
-#include <usbroothubdes.h>
-
-/*
- * Hub class-specific descriptor is constructed dynamically
- */
-
-/* --- Virtual root hub management functions ------------------------------- */
-
-static int rh_check_port_status(struct isp116x *isp116x)
-{
- u32 temp, ndp, i;
- int res;
-
- res = -1;
- temp = isp116x_read_reg32(isp116x, HCRHSTATUS);
- ndp = (temp & RH_A_NDP);
- for (i = 0; i < ndp; i++) {
- temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i);
- /* check for a device disconnect */
- if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
- (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
- res = i;
- break;
- }
- }
- return res;
-}
-
-/* --- HC management functions --------------------------------------------- */
-
-/* Write len bytes to fifo, pad till 32-bit boundary
- */
-static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len)
-{
- u8 *dp = (u8 *) buf;
- u16 *dp2 = (u16 *) buf;
- u16 w;
- int quot = len % 4;
-
- if ((unsigned long)dp2 & 1) {
- /* not aligned */
- for (; len > 1; len -= 2) {
- w = *dp++;
- w |= *dp++ << 8;
- isp116x_raw_write_data16(isp116x, w);
- }
- if (len)
- isp116x_write_data16(isp116x, (u16) * dp);
- } else {
- /* aligned */
- for (; len > 1; len -= 2)
- isp116x_raw_write_data16(isp116x, *dp2++);
- if (len)
- isp116x_write_data16(isp116x, 0xff & *((u8 *) dp2));
- }
- if (quot == 1 || quot == 2)
- isp116x_raw_write_data16(isp116x, 0);
-}
-
-/* Read len bytes from fifo and then read till 32-bit boundary
- */
-static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len)
-{
- u8 *dp = (u8 *) buf;
- u16 *dp2 = (u16 *) buf;
- u16 w;
- int quot = len % 4;
-
- if ((unsigned long)dp2 & 1) {
- /* not aligned */
- for (; len > 1; len -= 2) {
- w = isp116x_raw_read_data16(isp116x);
- *dp++ = w & 0xff;
- *dp++ = (w >> 8) & 0xff;
- }
- if (len)
- *dp = 0xff & isp116x_read_data16(isp116x);
- } else {
- /* aligned */
- for (; len > 1; len -= 2)
- *dp2++ = isp116x_raw_read_data16(isp116x);
- if (len)
- *(u8 *) dp2 = 0xff & isp116x_read_data16(isp116x);
- }
- if (quot == 1 || quot == 2)
- isp116x_raw_read_data16(isp116x);
-}
-
-/* Write PTD's and data for scheduled transfers into the fifo ram.
- * Fifo must be empty and ready */
-static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev,
- unsigned long pipe, struct ptd *ptd, int n, void *data,
- int len)
-{
- int buflen = n * sizeof(struct ptd) + len;
- int i, done;
-
- DBG("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
-
- isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
- isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
- isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
-
- done = 0;
- for (i = 0; i < n; i++) {
- DBG("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
-
- dump_ptd(&ptd[i]);
- isp116x_write_data16(isp116x, ptd[i].count);
- isp116x_write_data16(isp116x, ptd[i].mps);
- isp116x_write_data16(isp116x, ptd[i].len);
- isp116x_write_data16(isp116x, ptd[i].faddr);
-
- dump_ptd_data(&ptd[i], (__u8 *) data + done, 0);
- write_ptddata_to_fifo(isp116x,
- (__u8 *) data + done,
- PTD_GET_LEN(&ptd[i]));
-
- done += PTD_GET_LEN(&ptd[i]);
- }
-}
-
-/* Read the processed PTD's and data from fifo ram back to URBs' buffers.
- * Fifo must be full and done */
-static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
- unsigned long pipe, struct ptd *ptd, int n, void *data,
- int len)
-{
- int buflen = n * sizeof(struct ptd) + len;
- int i, done, cc, ret;
-
- isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
- isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
- isp116x_write_addr(isp116x, HCATLPORT);
-
- ret = TD_CC_NOERROR;
- done = 0;
- for (i = 0; i < n; i++) {
- DBG("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
-
- ptd[i].count = isp116x_read_data16(isp116x);
- ptd[i].mps = isp116x_read_data16(isp116x);
- ptd[i].len = isp116x_read_data16(isp116x);
- ptd[i].faddr = isp116x_read_data16(isp116x);
- dump_ptd(&ptd[i]);
-
- read_ptddata_from_fifo(isp116x,
- (__u8 *) data + done,
- PTD_GET_LEN(&ptd[i]));
- dump_ptd_data(&ptd[i], (__u8 *) data + done, 1);
-
- done += PTD_GET_LEN(&ptd[i]);
-
- cc = PTD_GET_CC(&ptd[i]);
-
- /* Data underrun means basically that we had more buffer space than
- * the function had data. It is perfectly normal but upper levels have
- * to know how much we actually transferred.
- */
- if (cc == TD_NOTACCESSED ||
- (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
- ret = cc;
- }
-
- DBG("--- unpack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
-
- return ret;
-}
-
-/* Interrupt handling
- */
-static int isp116x_interrupt(struct isp116x *isp116x)
-{
- u16 irqstat;
- u32 intstat;
- int ret = 0;
-
- isp116x_write_reg16(isp116x, HCuPINTENB, 0);
- irqstat = isp116x_read_reg16(isp116x, HCuPINT);
- isp116x_write_reg16(isp116x, HCuPINT, irqstat);
- DBG("------ irqstat %x ------", irqstat);
-
- if (irqstat & HCuPINT_ATL) {
- DBG("------ HCuPINT_ATL ------");
- udelay(500);
- ret = 1;
- }
-
- if (irqstat & HCuPINT_OPR) {
- intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
- isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
- DBG("------ HCuPINT_OPR %x ------", intstat);
-
- if (intstat & HCINT_UE) {
- ERR("unrecoverable error, controller disabled");
-
- /* FIXME: be optimistic, hope that bug won't repeat
- * often. Make some non-interrupt context restart the
- * controller. Count and limit the retries though;
- * either hardware or software errors can go forever...
- */
- isp116x_reset(isp116x);
- ret = -1;
- return -1;
- }
-
- if (intstat & HCINT_RHSC) {
- got_rhsc = 1;
- ret = 1;
- /* When root hub or any of its ports is going
- to come out of suspend, it may take more
- than 10ms for status bits to stabilize. */
- mdelay(20);
- }
-
- if (intstat & HCINT_SO) {
- ERR("schedule overrun");
- ret = -1;
- }
-
- irqstat &= ~HCuPINT_OPR;
- }
-
- return ret;
-}
-
-/* With one PTD we can transfer almost 1K in one go;
- * HC does the splitting into endpoint digestible transactions
- */
-struct ptd ptd[1];
-
-static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
-{
- unsigned mpck = usb_maxpacket(dev, pipe);
-
- /* One PTD can transfer 1023 bytes but try to always
- * transfer multiples of endpoint buffer size
- */
- return 1023 / mpck * mpck;
-}
-
-/* Do an USB transfer
- */
-static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
- int dir, void *buffer, int len)
-{
- struct isp116x *isp116x = &isp116x_dev;
- int type = usb_pipetype(pipe);
- int epnum = usb_pipeendpoint(pipe);
- int max = usb_maxpacket(dev, pipe);
- int dir_out = usb_pipeout(pipe);
- int speed_low = (dev->speed == USB_SPEED_LOW);
- int i, done = 0, stat, timeout, cc;
-
- /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
- int retries = 500;
-
- DBG("------------------------------------------------");
- dump_msg(dev, pipe, buffer, len, "SUBMIT");
- DBG("------------------------------------------------");
-
- if (len >= 1024) {
- ERR("Too big job");
- dev->status = USB_ST_CRC_ERR;
- return -1;
- }
-
- if (isp116x->disabled) {
- ERR("EPIPE");
- dev->status = USB_ST_CRC_ERR;
- return -1;
- }
-
- /* device pulled? Shortcut the action. */
- if (devgone == dev) {
- ERR("ENODEV");
- dev->status = USB_ST_CRC_ERR;
- return USB_ST_CRC_ERR;
- }
-
- if (!max) {
- ERR("pipesize for pipe %lx is zero", pipe);
- dev->status = USB_ST_CRC_ERR;
- return -1;
- }
-
- if (type == PIPE_ISOCHRONOUS) {
- ERR("isochronous transfers not supported");
- dev->status = USB_ST_CRC_ERR;
- return -1;
- }
-
- /* FIFO not empty? */
- if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
- ERR("****** FIFO not empty! ******");
- dev->status = USB_ST_BUF_ERR;
- return -1;
- }
-
- retry:
- isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
-
- /* Prepare the PTD data */
- ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
- PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
- ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
- ptd->len = PTD_LEN(len) | PTD_DIR(dir);
- ptd->faddr = PTD_FA(usb_pipedevice(pipe));
-
-retry_same:
- /* Pack data into FIFO ram */
- pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
-#ifdef EXTRA_DELAY
- mdelay(EXTRA_DELAY);
-#endif
-
- /* Start the data transfer */
-
- /* Allow more time for a BULK device to react - some are slow */
- if (usb_pipebulk(pipe))
- timeout = 5000;
- else
- timeout = 100;
-
- /* Wait for it to complete */
- for (;;) {
- /* Check whether the controller is done */
- stat = isp116x_interrupt(isp116x);
-
- if (stat < 0) {
- dev->status = USB_ST_CRC_ERR;
- break;
- }
- if (stat > 0)
- break;
-
- /* Check the timeout */
- if (--timeout)
- udelay(1);
- else {
- ERR("CTL:TIMEOUT ");
- stat = USB_ST_CRC_ERR;
- break;
- }
- }
-
- /* We got an Root Hub Status Change interrupt */
- if (got_rhsc) {
- isp116x_show_regs(isp116x);
-
- got_rhsc = 0;
-
- /* Abuse timeout */
- timeout = rh_check_port_status(isp116x);
- if (timeout >= 0) {
- /*
- * FIXME! NOTE! AAAARGH!
- * This is potentially dangerous because it assumes
- * that only one device is ever plugged in!
- */
- devgone = dev;
- }
- }
-
- /* Ok, now we can read transfer status */
-
- /* FIFO not ready? */
- if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) {
- ERR("****** FIFO not ready! ******");
- dev->status = USB_ST_BUF_ERR;
- return -1;
- }
-
- /* Unpack data from FIFO ram */
- cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
-
- i = PTD_GET_COUNT(ptd);
- done += i;
- buffer += i;
- len -= i;
-
- /* There was some kind of real problem; Prepare the PTD again
- * and retry from the failed transaction on
- */
- if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
- if (retries >= 100) {
- retries -= 100;
- /* The chip will have toggled the toggle bit for the failed
- * transaction too. We have to toggle it back.
- */
- usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
- goto retry;
- }
- }
- /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
- * the transactions from the first on for the whole frame. It may be busy and we retry
- * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
- * PTD didn't make it because the function was busy or the frame ended before the PTD
- * finished. We prepare the rest of the data and try again.
- */
- else if (cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || (cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
- if (retries) {
- --retries;
- if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) goto retry_same;
- usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
- goto retry;
- }
- }
-
- if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
- DBG("****** completition code error %x ******", cc);
- switch (cc) {
- case TD_CC_BITSTUFFING:
- dev->status = USB_ST_BIT_ERR;
- break;
- case TD_CC_STALL:
- dev->status = USB_ST_STALLED;
- break;
- case TD_BUFFEROVERRUN:
- case TD_BUFFERUNDERRUN:
- dev->status = USB_ST_BUF_ERR;
- break;
- default:
- dev->status = USB_ST_CRC_ERR;
- }
- return -cc;
- }
- else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
-
- dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
-
- dev->status = 0;
- return done;
-}
-
-/* Adapted from au1x00_usb_ohci.c
- */
-static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len,
- struct devrequest *cmd)
-{
- struct isp116x *isp116x = &isp116x_dev;
- u32 tmp = 0;
-
- int leni = transfer_len;
- int len = 0;
- int stat = 0;
- u32 datab[4];
- u8 *data_buf = (u8 *) datab;
- u16 bmRType_bReq;
- u16 wValue;
- u16 wIndex;
- u16 wLength;
-
- if (usb_pipeint(pipe)) {
- INFO("Root-Hub submit IRQ: NOT implemented");
- return 0;
- }
-
- bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = swap_16(cmd->value);
- wIndex = swap_16(cmd->index);
- wLength = swap_16(cmd->length);
-
- DBG("--- HUB ----------------------------------------");
- DBG("submit rh urb, req=%x val=%#x index=%#x len=%d",
- bmRType_bReq, wValue, wIndex, wLength);
- dump_msg(dev, pipe, buffer, transfer_len, "RH");
- DBG("------------------------------------------------");
-
- switch (bmRType_bReq) {
- case RH_GET_STATUS:
- DBG("RH_GET_STATUS");
-
- *(__u16 *) data_buf = swap_16(1);
- len = 2;
- break;
-
- case RH_GET_STATUS | RH_INTERFACE:
- DBG("RH_GET_STATUS | RH_INTERFACE");
-
- *(__u16 *) data_buf = swap_16(0);
- len = 2;
- break;
-
- case RH_GET_STATUS | RH_ENDPOINT:
- DBG("RH_GET_STATUS | RH_ENDPOINT");
-
- *(__u16 *) data_buf = swap_16(0);
- len = 2;
- break;
-
- case RH_GET_STATUS | RH_CLASS:
- DBG("RH_GET_STATUS | RH_CLASS");
-
- tmp = isp116x_read_reg32(isp116x, HCRHSTATUS);
-
- *(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE));
- len = 4;
- break;
-
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- DBG("RH_GET_STATUS | RH_OTHER | RH_CLASS");
-
- tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1);
- *(__u32 *) data_buf = swap_32(tmp);
- isp116x_show_regs(isp116x);
- len = 4;
- break;
-
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- DBG("RH_CLEAR_FEATURE | RH_ENDPOINT");
-
- switch (wValue) {
- case RH_ENDPOINT_STALL:
- DBG("C_HUB_ENDPOINT_STALL");
- len = 0;
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- DBG("RH_CLEAR_FEATURE | RH_CLASS");
-
- switch (wValue) {
- case RH_C_HUB_LOCAL_POWER:
- DBG("C_HUB_LOCAL_POWER");
- len = 0;
- break;
-
- case RH_C_HUB_OVER_CURRENT:
- DBG("C_HUB_OVER_CURRENT");
- isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC);
- len = 0;
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- DBG("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS");
-
- switch (wValue) {
- case RH_PORT_ENABLE:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_CCS);
- len = 0;
- break;
-
- case RH_PORT_SUSPEND:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_POCI);
- len = 0;
- break;
-
- case RH_PORT_POWER:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_LSDA);
- len = 0;
- break;
-
- case RH_C_PORT_CONNECTION:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_CSC);
- len = 0;
- break;
-
- case RH_C_PORT_ENABLE:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PESC);
- len = 0;
- break;
-
- case RH_C_PORT_SUSPEND:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PSSC);
- len = 0;
- break;
-
- case RH_C_PORT_OVER_CURRENT:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_POCI);
- len = 0;
- break;
-
- case RH_C_PORT_RESET:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PRSC);
- len = 0;
- break;
-
- default:
- ERR("invalid wValue");
- stat = USB_ST_STALLED;
- }
-
- isp116x_show_regs(isp116x);
-
- break;
-
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- DBG("RH_SET_FEATURE | RH_OTHER | RH_CLASS");
-
- switch (wValue) {
- case RH_PORT_SUSPEND:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PSS);
- len = 0;
- break;
-
- case RH_PORT_RESET:
- /* Spin until any current reset finishes */
- while (1) {
- tmp =
- isp116x_read_reg32(isp116x,
- HCRHPORT1 + wIndex - 1);
- if (!(tmp & RH_PS_PRS))
- break;
- mdelay(1);
- }
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PRS);
- mdelay(10);
-
- len = 0;
- break;
-
- case RH_PORT_POWER:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PPS);
- len = 0;
- break;
-
- case RH_PORT_ENABLE:
- isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
- RH_PS_PES);
- len = 0;
- break;
-
- default:
- ERR("invalid wValue");
- stat = USB_ST_STALLED;
- }
-
- isp116x_show_regs(isp116x);
-
- break;
-
- case RH_SET_ADDRESS:
- DBG("RH_SET_ADDRESS");
-
- rh_devnum = wValue;
- len = 0;
- break;
-
- case RH_GET_DESCRIPTOR:
- DBG("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength);
-
- switch (wValue) {
- case (USB_DT_DEVICE << 8): /* device descriptor */
- len = min_t(unsigned int,
- leni, min_t(unsigned int,
- sizeof(root_hub_dev_des),
- wLength));
- data_buf = root_hub_dev_des;
- break;
-
- case (USB_DT_CONFIG << 8): /* configuration descriptor */
- len = min_t(unsigned int,
- leni, min_t(unsigned int,
- sizeof(root_hub_config_des),
- wLength));
- data_buf = root_hub_config_des;
- break;
-
- case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
- len = min_t(unsigned int,
- leni, min_t(unsigned int,
- sizeof(root_hub_str_index0),
- wLength));
- data_buf = root_hub_str_index0;
- break;
-
- case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
- len = min_t(unsigned int,
- leni, min_t(unsigned int,
- sizeof(root_hub_str_index1),
- wLength));
- data_buf = root_hub_str_index1;
- break;
-
- default:
- ERR("invalid wValue");
- stat = USB_ST_STALLED;
- }
-
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- DBG("RH_GET_DESCRIPTOR | RH_CLASS");
-
- tmp = isp116x_read_reg32(isp116x, HCRHDESCA);
-
- data_buf[0] = 0x09; /* min length; */
- data_buf[1] = 0x29;
- data_buf[2] = tmp & RH_A_NDP;
- data_buf[3] = 0;
- if (tmp & RH_A_PSM) /* per-port power switching? */
- data_buf[3] |= 0x01;
- if (tmp & RH_A_NOCP) /* no overcurrent reporting? */
- data_buf[3] |= 0x10;
- else if (tmp & RH_A_OCPM) /* per-port overcurrent rep? */
- data_buf[3] |= 0x08;
-
- /* Corresponds to data_buf[4-7] */
- datab[1] = 0;
- data_buf[5] = (tmp & RH_A_POTPGT) >> 24;
-
- tmp = isp116x_read_reg32(isp116x, HCRHDESCB);
-
- data_buf[7] = tmp & RH_B_DR;
- if (data_buf[2] < 7)
- data_buf[8] = 0xff;
- else {
- data_buf[0] += 2;
- data_buf[8] = (tmp & RH_B_DR) >> 8;
- data_buf[10] = data_buf[9] = 0xff;
- }
-
- len = min_t(unsigned int, leni,
- min_t(unsigned int, data_buf[0], wLength));
- break;
-
- case RH_GET_CONFIGURATION:
- DBG("RH_GET_CONFIGURATION");
-
- *(__u8 *) data_buf = 0x01;
- len = 1;
- break;
-
- case RH_SET_CONFIGURATION:
- DBG("RH_SET_CONFIGURATION");
-
- isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC);
- len = 0;
- break;
-
- default:
- ERR("*** *** *** unsupported root hub command *** *** ***");
- stat = USB_ST_STALLED;
- }
-
- len = min_t(int, len, leni);
- if (buffer != data_buf)
- memcpy(buffer, data_buf, len);
-
- dev->act_len = len;
- dev->status = stat;
- DBG("dev act_len %d, status %d", dev->act_len, dev->status);
-
- dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)");
-
- return stat;
-}
-
-/* --- Transfer functions -------------------------------------------------- */
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int len, int interval)
-{
- DBG("dev=%p pipe=%#lx buf=%p size=%d int=%d",
- dev, pipe, buffer, len, interval);
-
- return -1;
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int len, struct devrequest *setup)
-{
- int devnum = usb_pipedevice(pipe);
- int epnum = usb_pipeendpoint(pipe);
- int max = max_transfer_len(dev, pipe);
- int dir_in = usb_pipein(pipe);
- int done, ret;
-
- /* Control message is for the HUB? */
- if (devnum == rh_devnum)
- return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup);
-
- /* Ok, no HUB message so send the message to the device */
-
- /* Setup phase */
- DBG("--- SETUP PHASE --------------------------------");
- usb_settoggle(dev, epnum, 1, 0);
- ret = isp116x_submit_job(dev, pipe,
- PTD_DIR_SETUP,
- setup, sizeof(struct devrequest));
- if (ret < 0) {
- DBG("control setup phase error (ret = %d", ret);
- return -1;
- }
-
- /* Data phase */
- DBG("--- DATA PHASE ---------------------------------");
- done = 0;
- usb_settoggle(dev, epnum, !dir_in, 1);
- while (done < len) {
- ret = isp116x_submit_job(dev, pipe,
- dir_in ? PTD_DIR_IN : PTD_DIR_OUT,
- (__u8 *) buffer + done,
- max > len - done ? len - done : max);
- if (ret < 0) {
- DBG("control data phase error (ret = %d)", ret);
- return -1;
- }
- done += ret;
-
- if (dir_in && ret < max) /* short packet */
- break;
- }
-
- /* Status phase */
- DBG("--- STATUS PHASE -------------------------------");
- usb_settoggle(dev, epnum, !dir_in, 1);
- ret = isp116x_submit_job(dev, pipe,
- !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0);
- if (ret < 0) {
- DBG("control status phase error (ret = %d", ret);
- return -1;
- }
-
- dev->act_len = done;
-
- dump_msg(dev, pipe, buffer, len, "DEV(ret)");
-
- return done;
-}
-
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int len)
-{
- int dir_out = usb_pipeout(pipe);
- int max = max_transfer_len(dev, pipe);
- int done, ret;
-
- DBG("--- BULK ---------------------------------------");
- DBG("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d",
- usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out);
-
- done = 0;
- while (done < len) {
- ret = isp116x_submit_job(dev, pipe,
- !dir_out ? PTD_DIR_IN : PTD_DIR_OUT,
- (__u8 *) buffer + done,
- max > len - done ? len - done : max);
- if (ret < 0) {
- DBG("error on bulk message (ret = %d)", ret);
- return -1;
- }
-
- done += ret;
-
- if (!dir_out && ret < max) /* short packet */
- break;
- }
-
- dev->act_len = done;
-
- return 0;
-}
-
-/* --- Basic functions ----------------------------------------------------- */
-
-static int isp116x_sw_reset(struct isp116x *isp116x)
-{
- int retries = 15;
- int ret = 0;
-
- DBG("");
-
- isp116x->disabled = 1;
-
- isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC);
- isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR);
- while (--retries) {
- /* It usually resets within 1 ms */
- mdelay(1);
- if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR))
- break;
- }
- if (!retries) {
- ERR("software reset timeout");
- ret = -1;
- }
- return ret;
-}
-
-static int isp116x_reset(struct isp116x *isp116x)
-{
- unsigned long t;
- u16 clkrdy = 0;
- int ret, timeout = 15 /* ms */ ;
-
- DBG("");
-
- ret = isp116x_sw_reset(isp116x);
- if (ret)
- return ret;
-
- for (t = 0; t < timeout; t++) {
- clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY;
- if (clkrdy)
- break;
- mdelay(1);
- }
- if (!clkrdy) {
- ERR("clock not ready after %dms", timeout);
- /* After sw_reset the clock won't report to be ready, if
- H_WAKEUP pin is high. */
- ERR("please make sure that the H_WAKEUP pin is pulled low!");
- ret = -1;
- }
- return ret;
-}
-
-static void isp116x_stop(struct isp116x *isp116x)
-{
- u32 val;
-
- DBG("");
-
- isp116x_write_reg16(isp116x, HCuPINTENB, 0);
-
- /* Switch off ports' power, some devices don't come up
- after next 'start' without this */
- val = isp116x_read_reg32(isp116x, HCRHDESCA);
- val &= ~(RH_A_NPS | RH_A_PSM);
- isp116x_write_reg32(isp116x, HCRHDESCA, val);
- isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS);
-
- isp116x_sw_reset(isp116x);
-}
-
-/*
- * Configure the chip. The chip must be successfully reset by now.
- */
-static int isp116x_start(struct isp116x *isp116x)
-{
- struct isp116x_platform_data *board = isp116x->board;
- u32 val;
-
- DBG("");
-
- /* Clear interrupt status and disable all interrupt sources */
- isp116x_write_reg16(isp116x, HCuPINT, 0xff);
- isp116x_write_reg16(isp116x, HCuPINTENB, 0);
-
- isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE);
- isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE);
-
- /* Hardware configuration */
- val = HCHWCFG_DBWIDTH(1);
- if (board->sel15Kres)
- val |= HCHWCFG_15KRSEL;
- /* Remote wakeup won't work without working clock */
- if (board->remote_wakeup_enable)
- val |= HCHWCFG_CLKNOTSTOP;
- if (board->oc_enable)
- val |= HCHWCFG_ANALOG_OC;
- isp116x_write_reg16(isp116x, HCHWCFG, val);
-
- /* --- Root hub configuration */
- val = (25 << 24) & RH_A_POTPGT;
- /* AN10003_1.pdf recommends RH_A_NPS (no power switching) to
- be always set. Yet, instead, we request individual port
- power switching. */
- val |= RH_A_PSM;
- /* Report overcurrent per port */
- val |= RH_A_OCPM;
- isp116x_write_reg32(isp116x, HCRHDESCA, val);
- isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA);
-
- val = RH_B_PPCM;
- isp116x_write_reg32(isp116x, HCRHDESCB, val);
- isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB);
-
- val = 0;
- if (board->remote_wakeup_enable)
- val |= RH_HS_DRWE;
- isp116x_write_reg32(isp116x, HCRHSTATUS, val);
- isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS);
-
- isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf);
-
- /* Go operational */
- val = HCCONTROL_USB_OPER;
- if (board->remote_wakeup_enable)
- val |= HCCONTROL_RWE;
- isp116x_write_reg32(isp116x, HCCONTROL, val);
-
- /* Disable ports to avoid race in device enumeration */
- isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS);
- isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS);
-
- isp116x_show_regs(isp116x);
-
- isp116x->disabled = 0;
-
- return 0;
-}
-
-/* --- Init functions ------------------------------------------------------ */
-
-int isp116x_check_id(struct isp116x *isp116x)
-{
- int val;
-
- val = isp116x_read_reg16(isp116x, HCCHIPID);
- if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) {
- ERR("invalid chip ID %04x", val);
- return -1;
- }
-
- return 0;
-}
-
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller))
-{
- struct isp116x *isp116x = &isp116x_dev;
-
- DBG("");
-
- got_rhsc = rh_devnum = 0;
-
- /* Init device registers addr */
- isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
- isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;
-
- /* Setup specific board settings */
-#ifdef ISP116X_HCD_SEL15kRES
- isp116x_board.sel15Kres = 1;
-#endif
-#ifdef ISP116X_HCD_OC_ENABLE
- isp116x_board.oc_enable = 1;
-#endif
-#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE
- isp116x_board.remote_wakeup_enable = 1;
-#endif
- isp116x->board = &isp116x_board;
-
- /* Try to get ISP116x silicon chip ID */
- if (isp116x_check_id(isp116x) < 0)
- return -1;
-
- isp116x->disabled = 1;
- isp116x->sleeping = 0;
-
- isp116x_reset(isp116x);
- isp116x_start(isp116x);
-
- return 0;
-}
-
-int usb_lowlevel_stop(int index)
-{
- struct isp116x *isp116x = &isp116x_dev;
-
- DBG("");
-
- if (!isp116x->disabled)
- isp116x_stop(isp116x);
-
- return 0;
-}
+++ /dev/null
-/*
- * ISP116x register declarations and HCD data structures
- *
- * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
- * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
- * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
- * Portions:
- * Copyright (C) 2004 Lothar Wassmann
- * Copyright (C) 2004 Psion Teklogix
- * Copyright (C) 2004 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef DEBUG
-#define DBG(fmt, args...) \
- printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
-#else
-#define DBG(fmt, args...) do {} while (0)
-#endif
-
-#ifdef VERBOSE
-# define VDBG DBG
-#else
-# define VDBG(fmt, args...) do {} while (0)
-#endif
-
-#define ERR(fmt, args...) \
- printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
-#define WARN(fmt, args...) \
- printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
-#define INFO(fmt, args...) \
- printf("isp116x: " fmt "\n" , ## args)
-
-/* ------------------------------------------------------------------------- */
-
-/* us of 1ms frame */
-#define MAX_LOAD_LIMIT 850
-
-/* Full speed: max # of bytes to transfer for a single urb
- at a time must be < 1024 && must be multiple of 64.
- 832 allows transfering 4kiB within 5 frames. */
-#define MAX_TRANSFER_SIZE_FULLSPEED 832
-
-/* Low speed: there is no reason to schedule in very big
- chunks; often the requested long transfers are for
- string descriptors containing short strings. */
-#define MAX_TRANSFER_SIZE_LOWSPEED 64
-
-/* Bytetime (us), a rough indication of how much time it
- would take to transfer a byte of useful data over USB */
-#define BYTE_TIME_FULLSPEED 1
-#define BYTE_TIME_LOWSPEED 20
-
-/* Buffer sizes */
-#define ISP116x_BUF_SIZE 4096
-#define ISP116x_ITL_BUFSIZE 0
-#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
-
-#define ISP116x_WRITE_OFFSET 0x80
-
-/* --- ISP116x registers/bits ---------------------------------------------- */
-
-#define HCREVISION 0x00
-#define HCCONTROL 0x01
-#define HCCONTROL_HCFS (3 << 6) /* host controller
- functional state */
-#define HCCONTROL_USB_RESET (0 << 6)
-#define HCCONTROL_USB_RESUME (1 << 6)
-#define HCCONTROL_USB_OPER (2 << 6)
-#define HCCONTROL_USB_SUSPEND (3 << 6)
-#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
-#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
-#define HCCMDSTAT 0x02
-#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
-#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
-#define HCINTSTAT 0x03
-#define HCINT_SO (1 << 0) /* scheduling overrun */
-#define HCINT_WDH (1 << 1) /* writeback of done_head */
-#define HCINT_SF (1 << 2) /* start frame */
-#define HCINT_RD (1 << 3) /* resume detect */
-#define HCINT_UE (1 << 4) /* unrecoverable error */
-#define HCINT_FNO (1 << 5) /* frame number overflow */
-#define HCINT_RHSC (1 << 6) /* root hub status change */
-#define HCINT_OC (1 << 30) /* ownership change */
-#define HCINT_MIE (1 << 31) /* master interrupt enable */
-#define HCINTENB 0x04
-#define HCINTDIS 0x05
-#define HCFMINTVL 0x0d
-#define HCFMREM 0x0e
-#define HCFMNUM 0x0f
-#define HCLSTHRESH 0x11
-#define HCRHDESCA 0x12
-#define RH_A_NDP (0x3 << 0) /* # downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* overcurrent protection
- mode */
-#define RH_A_NOCP (1 << 12) /* no overcurrent protection */
-#define RH_A_POTPGT (0xff << 24) /* power on -> power good
- time */
-#define HCRHDESCB 0x13
-#define RH_B_DR (0xffff << 0) /* device removable flags */
-#define RH_B_PPCM (0xffff << 16) /* port power control mask */
-#define HCRHSTATUS 0x14
-#define RH_HS_LPS (1 << 0) /* local power status */
-#define RH_HS_OCI (1 << 1) /* over current indicator */
-#define RH_HS_DRWE (1 << 15) /* device remote wakeup
- enable */
-#define RH_HS_LPSC (1 << 16) /* local power status change */
-#define RH_HS_OCIC (1 << 17) /* over current indicator
- change */
-#define RH_HS_CRWE (1 << 31) /* clear remote wakeup
- enable */
-#define HCRHPORT1 0x15
-#define RH_PS_CCS (1 << 0) /* current connect status */
-#define RH_PS_PES (1 << 1) /* port enable status */
-#define RH_PS_PSS (1 << 2) /* port suspend status */
-#define RH_PS_POCI (1 << 3) /* port over current
- indicator */
-#define RH_PS_PRS (1 << 4) /* port reset status */
-#define RH_PS_PPS (1 << 8) /* port power status */
-#define RH_PS_LSDA (1 << 9) /* low speed device attached */
-#define RH_PS_CSC (1 << 16) /* connect status change */
-#define RH_PS_PESC (1 << 17) /* port enable status change */
-#define RH_PS_PSSC (1 << 18) /* port suspend status
- change */
-#define RH_PS_OCIC (1 << 19) /* over current indicator
- change */
-#define RH_PS_PRSC (1 << 20) /* port reset status change */
-#define HCRHPORT_CLRMASK (0x1f << 16)
-#define HCRHPORT2 0x16
-#define HCHWCFG 0x20
-#define HCHWCFG_15KRSEL (1 << 12)
-#define HCHWCFG_CLKNOTSTOP (1 << 11)
-#define HCHWCFG_ANALOG_OC (1 << 10)
-#define HCHWCFG_DACK_MODE (1 << 8)
-#define HCHWCFG_EOT_POL (1 << 7)
-#define HCHWCFG_DACK_POL (1 << 6)
-#define HCHWCFG_DREQ_POL (1 << 5)
-#define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
-#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
-#define HCHWCFG_INT_POL (1 << 2)
-#define HCHWCFG_INT_TRIGGER (1 << 1)
-#define HCHWCFG_INT_ENABLE (1 << 0)
-#define HCDMACFG 0x21
-#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
-#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
-#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
-#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
-#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
-#define HCDMACFG_DMA_ENABLE (1 << 4)
-#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
-#define HCDMACFG_CTR_SEL (1 << 2)
-#define HCDMACFG_ITLATL_SEL (1 << 1)
-#define HCDMACFG_DMA_RW_SELECT (1 << 0)
-#define HCXFERCTR 0x22
-#define HCuPINT 0x24
-#define HCuPINT_SOF (1 << 0)
-#define HCuPINT_ATL (1 << 1)
-#define HCuPINT_AIIEOT (1 << 2)
-#define HCuPINT_OPR (1 << 4)
-#define HCuPINT_SUSP (1 << 5)
-#define HCuPINT_CLKRDY (1 << 6)
-#define HCuPINTENB 0x25
-#define HCCHIPID 0x27
-#define HCCHIPID_MASK 0xff00
-#define HCCHIPID_MAGIC 0x6100
-#define HCSCRATCH 0x28
-#define HCSWRES 0x29
-#define HCSWRES_MAGIC 0x00f6
-#define HCITLBUFLEN 0x2a
-#define HCATLBUFLEN 0x2b
-#define HCBUFSTAT 0x2c
-#define HCBUFSTAT_ITL0_FULL (1 << 0)
-#define HCBUFSTAT_ITL1_FULL (1 << 1)
-#define HCBUFSTAT_ATL_FULL (1 << 2)
-#define HCBUFSTAT_ITL0_DONE (1 << 3)
-#define HCBUFSTAT_ITL1_DONE (1 << 4)
-#define HCBUFSTAT_ATL_DONE (1 << 5)
-#define HCRDITL0LEN 0x2d
-#define HCRDITL1LEN 0x2e
-#define HCITLPORT 0x40
-#define HCATLPORT 0x41
-
-/* PTD accessor macros. */
-#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
-#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
-#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
-#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
-#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
-#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
-#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
-#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
-#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
-#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
-#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
-#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
-#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
-#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
-#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
-#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
-#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
-#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
-#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
-#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
-#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
-#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
-#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
-#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
-#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
-#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
-
-/* Hardware transfer status codes -- CC from ptd->count */
-#define TD_CC_NOERROR 0x00
-#define TD_CC_CRC 0x01
-#define TD_CC_BITSTUFFING 0x02
-#define TD_CC_DATATOGGLEM 0x03
-#define TD_CC_STALL 0x04
-#define TD_DEVNOTRESP 0x05
-#define TD_PIDCHECKFAIL 0x06
-#define TD_UNEXPECTEDPID 0x07
-#define TD_DATAOVERRUN 0x08
-#define TD_DATAUNDERRUN 0x09
- /* 0x0A, 0x0B reserved for hardware */
-#define TD_BUFFEROVERRUN 0x0C
-#define TD_BUFFERUNDERRUN 0x0D
- /* 0x0E, 0x0F reserved for HCD */
-#define TD_NOTACCESSED 0x0F
-
-/* ------------------------------------------------------------------------- */
-
-#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
-#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
-
-/* Philips transfer descriptor */
-struct ptd {
- u16 count;
-#define PTD_COUNT_MSK (0x3ff << 0)
-#define PTD_TOGGLE_MSK (1 << 10)
-#define PTD_ACTIVE_MSK (1 << 11)
-#define PTD_CC_MSK (0xf << 12)
- u16 mps;
-#define PTD_MPS_MSK (0x3ff << 0)
-#define PTD_SPD_MSK (1 << 10)
-#define PTD_LAST_MSK (1 << 11)
-#define PTD_EP_MSK (0xf << 12)
- u16 len;
-#define PTD_LEN_MSK (0x3ff << 0)
-#define PTD_DIR_MSK (3 << 10)
-#define PTD_DIR_SETUP (0)
-#define PTD_DIR_OUT (1)
-#define PTD_DIR_IN (2)
-#define PTD_B5_5_MSK (1 << 13)
- u16 faddr;
-#define PTD_FA_MSK (0x7f << 0)
-#define PTD_FMT_MSK (1 << 7)
-} __attribute__ ((packed, aligned(2)));
-
-struct isp116x_ep {
- struct usb_device *udev;
- struct ptd ptd;
-
- u8 maxpacket;
- u8 epnum;
- u8 nextpid;
-
- u16 length; /* of current packet */
- unsigned char *data; /* to databuf */
-
- u16 error_count;
-};
-
-/* URB struct */
-#define N_URB_TD 48
-#define URB_DEL 1
-typedef struct {
- struct isp116x_ep *ed;
- void *transfer_buffer; /* (in) associated data buffer */
- int actual_length; /* (return) actual transfer length */
- unsigned long pipe; /* (in) pipe information */
-#if 0
- int state;
-#endif
-} urb_priv_t;
-
-struct isp116x_platform_data {
- /* Enable internal resistors on downstream ports */
- unsigned sel15Kres:1;
- /* On-chip overcurrent detection */
- unsigned oc_enable:1;
- /* Enable wakeup by devices on usb bus (e.g. wakeup
- by attachment/detachment or by device activity
- such as moving a mouse). When chosen, this option
- prevents stopping internal clock, increasing
- thereby power consumption in suspended state. */
- unsigned remote_wakeup_enable:1;
-};
-
-struct isp116x {
- u16 *addr_reg;
- u16 *data_reg;
-
- struct isp116x_platform_data *board;
-
- struct dentry *dentry;
- unsigned long stat1, stat2, stat4, stat8, stat16;
-
- /* Status flags */
- unsigned disabled:1;
- unsigned sleeping:1;
-
- /* Root hub registers */
- u32 rhdesca;
- u32 rhdescb;
- u32 rhstatus;
- u32 rhport[2];
-
- /* Schedule for the current frame */
- struct isp116x_ep *atl_active;
- int atl_buflen;
- int atl_bufshrt;
- int atl_last_dir;
- int atl_finishing;
-};
-
-/* ------------------------------------------------- */
-
-/* Inter-io delay (ns). The chip is picky about access timings; it
- * expects at least:
- * 150ns delay between consecutive accesses to DATA_REG,
- * 300ns delay between access to ADDR_REG and DATA_REG
- * OE, WE MUST NOT be changed during these intervals
- */
-#if defined(UDELAY)
-#define isp116x_delay(h,d) udelay(d)
-#else
-#define isp116x_delay(h,d) do {} while (0)
-#endif
-
-static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
-{
- writew(reg & 0xff, isp116x->addr_reg);
- isp116x_delay(isp116x, UDELAY);
-}
-
-static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
-{
- writew(val, isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
-}
-
-static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
-{
- __raw_writew(val, isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
-}
-
-static inline u16 isp116x_read_data16(struct isp116x *isp116x)
-{
- u16 val;
-
- val = readw(isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
- return val;
-}
-
-static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
-{
- u16 val;
-
- val = __raw_readw(isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
- return val;
-}
-
-static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
-{
- writew(val & 0xffff, isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
- writew(val >> 16, isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
-}
-
-static inline u32 isp116x_read_data32(struct isp116x *isp116x)
-{
- u32 val;
-
- val = (u32) readw(isp116x->data_reg);
- isp116x_delay(isp116x, UDELAY);
- val |= ((u32) readw(isp116x->data_reg)) << 16;
- isp116x_delay(isp116x, UDELAY);
- return val;
-}
-
-/* Let's keep register access functions out of line. Hint:
- we wait at least 150 ns at every access.
-*/
-static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
-{
- isp116x_write_addr(isp116x, reg);
- return isp116x_read_data16(isp116x);
-}
-
-static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
-{
- isp116x_write_addr(isp116x, reg);
- return isp116x_read_data32(isp116x);
-}
-
-static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
- unsigned val)
-{
- isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
- isp116x_write_data16(isp116x, (u16) (val & 0xffff));
-}
-
-static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
- unsigned val)
-{
- isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
- isp116x_write_data32(isp116x, (u32) val);
-}
-
-/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
-
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
- ret = wait_for_bit(__func__, &clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
- true, CONFIG_SYS_HZ, false);
+ ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
+ true, CONFIG_SYS_HZ, false);
if (ret)
return ret;
/* enable I2C clock */
writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
- ret = wait_for_bit(__func__, &otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
- CONFIG_SYS_HZ, false);
+ ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
+ CONFIG_SYS_HZ, false);
if (ret)
return ret;
OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
writel(mask, &otg->otg_clk_ctrl);
- ret = wait_for_bit(__func__, &otg->otg_clk_sts, mask, true,
- CONFIG_SYS_HZ, false);
+ ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true,
+ CONFIG_SYS_HZ, false);
if (ret)
return ret;
#define R8A66597_DPRINT(...)
#endif
-static const char hcd_name[] = "r8a66597_hcd";
static struct r8a66597 gr8a66597;
static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport)
setbits_le32(regs + RCAR_USB3_DL_CTRL,
RCAR_USB3_DL_CTRL_FW_SET_DATA0);
- ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
- RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
- 10, false);
+ ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
+ 10, false);
if (ret)
break;
}
clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
- ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
- RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
- 10, false);
+ ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
+ 10, false);
return ret;
}
{
int num_trbs = 0;
struct xhci_generic_trb *start_trb;
- bool first_trb = 0;
+ bool first_trb = false;
int start_cycle;
u32 field = 0;
u32 length_field = 0;
speed USB controller based on the Mentor Graphics
silicon IP.
+config USB_MUSB_OMAP2PLUS
+ tristate "OMAP2430 and onwards"
+ depends on ARCH_OMAP2PLUS
+
+config USB_MUSB_AM35X
+ bool "AM35x"
+
+config USB_MUSB_DSPS
+ bool "TI DSPS platforms"
+
if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_PIC32
used on almost all sunxi boards.
endif
+
+config USB_MUSB_PIO_ONLY
+ bool "Disable DMA (always use PIO)"
+ default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS || USB_MUSB_DSPS || USB_MUSB_SUNXI
+ help
+ All data is copied between memory and FIFO by the CPU.
+ DMA controllers are ignored.
--- /dev/null
+#
+# (C) Copyright 2017
+# Adam Ford, Logic PD, aford173@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+comment "Legacy MUSB Support"
+
+config USB_MUSB_HCD
+ bool "Legacy MUSB Host Controller"
+
+config USB_MUSB_UDC
+ bool "Legacy USB Device Controller"
+
+config USB_DAVINCI
+ bool "Legacy MUSB DaVinci"
+
+config USB_OMAP3
+ bool "Legacy MUSB OMAP3 / OMAP4"
+ depends on ARCH_OMAP2PLUS
+
+config USB_DA8XX
+ bool "Legacy MUSB DA8xx/OMAP-L1x"
+ depends on ARCH_DAVINCI
+
+config USB_AM35X
+ bool"Legacy MUSB AM35x"
+ depends on ARCH_OMAP2PLUS && !USB_OMAP3
--- /dev/null
+#
+# (C) Copyright 2017
+# Adam Ford, Logic PD, aford173@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+comment "USB Phy"
+
+config TWL4030_USB
+ bool "TWL4030 PHY"
+
+config OMAP_USB_PHY
+ bool "OMAP PHY"
+
+config ROCKCHIP_USB2_PHY
+ bool "Rockchip USB2 PHY"
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
+ default n if ARCH_SUNXI
default y if DM_VIDEO
help
Support drawing text and bitmaps onto a 8-bit-per-pixel display.
config VIDEO_BPP16
bool "Support 16-bit-per-pixel displays"
depends on DM_VIDEO
+ default n if ARCH_SUNXI
default y if DM_VIDEO
help
Support drawing text and bitmaps onto a 16-bit-per-pixel display.
/* Disable DISP signal */
writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable synchronization */
writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable pixel clock */
writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable PWM */
writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Enable LCD */
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable DISP signal */
writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable synchronization */
writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable pixel clock */
writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable PWM */
writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
- false, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ false, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Enable LCD */
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
value = readl(®s->lcdc_lcden);
writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
- ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
- true, 1000, false);
+ ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ true, 1000, false);
if (ret)
printf("%s: %d: Timeout!\n", __func__, __LINE__);
}
timing->vback_porch.typ = mode->upper_margin;
timing->vsync_len.typ = mode->vsync_len;
+ timing->flags = 0;
+
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else
menu "Environment"
-choice
- prompt "Select the location of the environment"
- default ENV_IS_IN_MMC if ARCH_SUNXI
- default ENV_IS_IN_MMC if ARCH_EXYNOS4
- default ENV_IS_IN_MMC if MX6SX || MX7D
- default ENV_IS_IN_MMC if TEGRA30 || TEGRA124
- default ENV_IS_IN_MMC if TEGRA_ARMV8_COMMON
- default ENV_IS_IN_FLASH if ARCH_CINTEGRATOR
- default ENV_IS_IN_FLASH if ARCH_INTEGRATOR_CP
- default ENV_IS_IN_FLASH if M548x || M547x || M5282 || MCF547x_8x
- default ENV_IS_IN_FLASH if MCF532x || MCF52x2
- default ENV_IS_IN_FLASH if MPC86xx || MPC83xx
- default ENV_IS_IN_FLASH if ARCH_MPC8572 || ARCH_MPC8548 || ARCH_MPC8641
- default ENV_IS_IN_FLASH if SH && !CPU_SH4
- default ENV_IS_IN_SPI_FLASH if ARMADA_XP
- default ENV_IS_IN_SPI_FLASH if INTEL_BAYTRAIL
- default ENV_IS_IN_SPI_FLASH if INTEL_BRASWELL
- default ENV_IS_IN_SPI_FLASH if INTEL_BROADWELL
- default ENV_IS_IN_SPI_FLASH if NORTHBRIDGE_INTEL_IVYBRIDGE
- default ENV_IS_IN_SPI_FLASH if INTEL_QUARK
- default ENV_IS_IN_SPI_FLASH if INTEL_QUEENSBAY
- default ENV_IS_IN_FAT if ARCH_BCM283X
- default ENV_IS_IN_FAT if MMC_OMAP_HS && TI_COMMON_CMD_OPTIONS
- default ENV_IS_NOWHERE
- help
- At present the environment can be stored in only one place. Use this
- option to select the location. This is either a device (where the
- environemnt information is simply written to a fixed location or
- partition on the device) or a filesystem (where the environment
- information is written to a file).
-
config ENV_IS_NOWHERE
bool "Environment is not stored"
+ depends on !ENV_IS_IN_EEPROM
+ depends on !ENV_IS_IN_FAT
+ depends on !ENV_IS_IN_FLASH
+ depends on !ENV_IS_IN_MMC
+ depends on !ENV_IS_IN_NAND
+ depends on !ENV_IS_IN_NVRAM
+ depends on !ENV_IS_IN_ONENAND
+ depends on !ENV_IS_IN_REMOTE
+ depends on !ENV_IS_IN_SPI_FLASH
+ depends on !ENV_IS_IN_UBI
+ default y
help
Define this if you don't want to or can't have an environment stored
on a storage medium. In this case the environemnt will still exist
config ENV_IS_IN_FAT
bool "Environment is in a FAT filesystem"
depends on !CHAIN_OF_TRUST
+ default y if ARCH_BCM283X
+ default y if ARCH_SUNXI && MMC
+ default y if MMC_OMAP_HS && TI_COMMON_CMD_OPTIONS
+ select FS_FAT
select FAT_WRITE
help
Define this if you want to use the FAT file system for the environment.
- - CONFIG_FAT_WRITE:
- This must be enabled. Otherwise it cannot save the environment file.
-
config ENV_IS_IN_EXT4
bool "Environment is in a EXT4 filesystem"
depends on !CHAIN_OF_TRUST
config ENV_IS_IN_FLASH
bool "Environment in flash memory"
depends on !CHAIN_OF_TRUST
+ default y if ARCH_CINTEGRATOR
+ default y if ARCH_INTEGRATOR_CP
+ default y if M548x || M547x || M5282 || MCF547x_8x
+ default y if MCF532x || MCF52x2
+ default y if MPC86xx || MPC83xx
+ default y if ARCH_MPC8572 || ARCH_MPC8548 || ARCH_MPC8641
+ default y if SH && !CPU_SH4
help
Define this if you have a flash device which you want to use for the
environment.
config ENV_IS_IN_MMC
bool "Environment in an MMC device"
depends on !CHAIN_OF_TRUST
+ depends on MMC
+ default y if ARCH_SUNXI
+ default y if ARCH_EXYNOS4
+ default y if MX6SX || MX7D
+ default y if TEGRA30 || TEGRA124
+ default y if TEGRA_ARMV8_COMMON
help
Define this if you have an MMC device which you want to use for the
environment.
config ENV_IS_IN_SPI_FLASH
bool "Environment is in SPI flash"
depends on !CHAIN_OF_TRUST
+ default y if ARMADA_XP
+ default y if INTEL_BAYTRAIL
+ default y if INTEL_BRASWELL
+ default y if INTEL_BROADWELL
+ default y if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default y if INTEL_QUARK
+ default y if INTEL_QUEENSBAY
help
Define this if you have a SPI Flash memory device which you
want to use for the environment.
You will probably want to define these to avoid a really noisy system
when storing the env in UBI.
-endchoice
-
config ENV_FAT_INTERFACE
string "Name of the block device for the environment"
depends on ENV_IS_IN_FAT
+ default "mmc" if ARCH_SUNXI
default "mmc" if TI_COMMON_CMD_OPTIONS || ARCH_ZYNQMP || ARCH_AT91
help
Define this to a string that is the name of the block device.
depends on ENV_IS_IN_FAT
default "0:1" if TI_COMMON_CMD_OPTIONS
default "0:auto" if ARCH_ZYNQMP
+ default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
+ default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
default "0" if ARCH_AT91
help
Define this to a string to specify the partition of the device. It can
puts(s);
}
} else {
- puts("Using default environment\n\n");
+ debug("Using default environment\n");
}
if (himport_r(&env_htab, (char *)default_environment,
DECLARE_GLOBAL_DATA_PTR;
-static struct env_driver *env_driver_lookup(enum env_location loc)
+static struct env_driver *_env_driver_lookup(enum env_location loc)
{
struct env_driver *drv;
const int n_ents = ll_entry_count(struct env_driver, env_driver);
return NULL;
}
-static enum env_location env_get_default_location(void)
+static enum env_location env_locations[] = {
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+ ENVL_EEPROM,
+#endif
+#ifdef CONFIG_ENV_IS_IN_EXT4
+ ENVL_EXT4,
+#endif
+#ifdef CONFIG_ENV_IS_IN_FAT
+ ENVL_FAT,
+#endif
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ ENVL_FLASH,
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+ ENVL_MMC,
+#endif
+#ifdef CONFIG_ENV_IS_IN_NAND
+ ENVL_NAND,
+#endif
+#ifdef CONFIG_ENV_IS_IN_NVRAM
+ ENVL_NVRAM,
+#endif
+#ifdef CONFIG_ENV_IS_IN_REMOTE
+ ENVL_REMOTE,
+#endif
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ ENVL_SPI_FLASH,
+#endif
+#ifdef CONFIG_ENV_IS_IN_UBI
+ ENVL_UBI,
+#endif
+#ifdef CONFIG_ENV_IS_NOWHERE
+ ENVL_NOWHERE,
+#endif
+};
+
+static enum env_location env_load_location = ENVL_UNKNOWN;
+
+static bool env_has_inited(enum env_location location)
{
- if IS_ENABLED(CONFIG_ENV_IS_IN_EEPROM)
- return ENVL_EEPROM;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_FAT)
- return ENVL_FAT;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)
- return ENVL_EXT4;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_FLASH)
- return ENVL_FLASH;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
- return ENVL_MMC;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_NAND)
- return ENVL_NAND;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_NVRAM)
- return ENVL_NVRAM;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_REMOTE)
- return ENVL_REMOTE;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)
- return ENVL_SPI_FLASH;
- else if IS_ENABLED(CONFIG_ENV_IS_IN_UBI)
- return ENVL_UBI;
- else if IS_ENABLED(CONFIG_ENV_IS_NOWHERE)
- return ENVL_NOWHERE;
- else
- return ENVL_UNKNOWN;
+ return gd->env_has_init & BIT(location);
}
-struct env_driver *env_driver_lookup_default(void)
+static void env_set_inited(enum env_location location)
{
- enum env_location loc = env_get_default_location();
+ /*
+ * We're using a 32-bits bitmask stored in gd (env_has_init)
+ * using the above enum value as the bit index. We need to
+ * make sure that we're not overflowing it.
+ */
+ BUILD_BUG_ON(ARRAY_SIZE(env_locations) > BITS_PER_LONG);
+
+ gd->env_has_init |= BIT(location);
+}
+
+/**
+ * env_get_location() - Returns the best env location for a board
+ * @op: operations performed on the environment
+ * @prio: priority between the multiple environments, 0 being the
+ * highest priority
+ *
+ * This will return the preferred environment for the given priority.
+ * This is overridable by boards if they need to.
+ *
+ * All implementations are free to use the operation, the priority and
+ * any other data relevant to their choice, but must take into account
+ * the fact that the lowest prority (0) is the most important location
+ * in the system. The following locations should be returned by order
+ * of descending priorities, from the highest to the lowest priority.
+ *
+ * Returns:
+ * an enum env_location value on success, a negative error code otherwise
+ */
+__weak enum env_location env_get_location(enum env_operation op, int prio)
+{
+ switch (op) {
+ case ENVOP_GET_CHAR:
+ case ENVOP_INIT:
+ case ENVOP_LOAD:
+ if (prio >= ARRAY_SIZE(env_locations))
+ return ENVL_UNKNOWN;
+
+ env_load_location = env_locations[prio];
+ return env_load_location;
+
+ case ENVOP_SAVE:
+ return env_load_location;
+ }
+
+ return ENVL_UNKNOWN;
+}
+
+
+/**
+ * env_driver_lookup() - Finds the most suited environment location
+ * @op: operations performed on the environment
+ * @prio: priority between the multiple environments, 0 being the
+ * highest priority
+ *
+ * This will try to find the available environment with the highest
+ * priority in the system.
+ *
+ * Returns:
+ * NULL on error, a pointer to a struct env_driver otherwise
+ */
+static struct env_driver *env_driver_lookup(enum env_operation op, int prio)
+{
+ enum env_location loc = env_get_location(op, prio);
struct env_driver *drv;
- drv = env_driver_lookup(loc);
+ if (loc == ENVL_UNKNOWN)
+ return NULL;
+
+ drv = _env_driver_lookup(loc);
if (!drv) {
debug("%s: No environment driver for location %d\n", __func__,
loc);
int env_get_char(int index)
{
- struct env_driver *drv = env_driver_lookup_default();
- int ret;
+ struct env_driver *drv;
+ int prio;
if (gd->env_valid == ENV_INVALID)
return default_environment[index];
- if (!drv)
- return -ENODEV;
- if (!drv->get_char)
- return *(uchar *)(gd->env_addr + index);
- ret = drv->get_char(index);
- if (ret < 0) {
- debug("%s: Environment failed to load (err=%d)\n",
- __func__, ret);
+
+ for (prio = 0; (drv = env_driver_lookup(ENVOP_GET_CHAR, prio)); prio++) {
+ int ret;
+
+ if (!drv->get_char)
+ continue;
+
+ if (!env_has_inited(drv->location))
+ continue;
+
+ ret = drv->get_char(index);
+ if (!ret)
+ return 0;
+
+ debug("%s: Environment %s failed to load (err=%d)\n", __func__,
+ drv->name, ret);
}
- return ret;
+ return -ENODEV;
}
int env_load(void)
{
- struct env_driver *drv = env_driver_lookup_default();
- int ret = 0;
+ struct env_driver *drv;
+ int prio;
- if (!drv)
- return -ENODEV;
- if (!drv->load)
- return 0;
- ret = drv->load();
- if (ret) {
- debug("%s: Environment failed to load (err=%d)\n", __func__,
- ret);
- return ret;
+ for (prio = 0; (drv = env_driver_lookup(ENVOP_LOAD, prio)); prio++) {
+ int ret;
+
+ if (!drv->load)
+ continue;
+
+ if (!env_has_inited(drv->location))
+ continue;
+
+ printf("Loading Environment from %s... ", drv->name);
+ ret = drv->load();
+ if (ret)
+ printf("Failed (%d)\n", ret);
+ else
+ printf("OK\n");
+
+ if (!ret)
+ return 0;
}
- return 0;
+ return -ENODEV;
}
int env_save(void)
{
- struct env_driver *drv = env_driver_lookup_default();
- int ret;
+ struct env_driver *drv;
+ int prio;
- if (!drv)
- return -ENODEV;
- if (!drv->save)
- return -ENOSYS;
- ret = drv->save();
- if (ret) {
- debug("%s: Environment failed to save (err=%d)\n", __func__,
- ret);
- return ret;
+ for (prio = 0; (drv = env_driver_lookup(ENVOP_SAVE, prio)); prio++) {
+ int ret;
+
+ if (!drv->save)
+ continue;
+
+ if (!env_has_inited(drv->location))
+ continue;
+
+ printf("Saving Environment to %s... ", drv->name);
+ ret = drv->save();
+ if (ret)
+ printf("Failed (%d)\n", ret);
+ else
+ printf("OK\n");
+
+ if (!ret)
+ return 0;
}
- return 0;
+ return -ENODEV;
}
int env_init(void)
{
- struct env_driver *drv = env_driver_lookup_default();
+ struct env_driver *drv;
int ret = -ENOENT;
+ int prio;
+
+ for (prio = 0; (drv = env_driver_lookup(ENVOP_INIT, prio)); prio++) {
+ if (!drv->init || !(ret = drv->init()))
+ env_set_inited(drv->location);
+
+ debug("%s: Environment %s init done (ret=%d)\n", __func__,
+ drv->name, ret);
+ }
- if (!drv)
+ if (!prio)
return -ENODEV;
- if (drv->init)
- ret = drv->init();
+
if (ret == -ENOENT) {
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = ENV_VALID;
return 0;
- } else if (ret) {
- debug("%s: Environment failed to init (err=%d)\n", __func__,
- ret);
- return ret;
}
- return 0;
+ return ret;
}
dev = dev_desc->devnum;
if (fat_set_blk_dev(dev_desc, &info) != 0) {
- printf("\n** Unable to use %s %d:%d for saveenv **\n",
+ /*
+ * This printf is embedded in the messages from env_save that
+ * will calling it. The missing \n is intentional.
+ */
+ printf("Unable to use %s %d:%d... ",
CONFIG_ENV_FAT_INTERFACE, dev, part);
return 1;
}
err = file_fat_write(CONFIG_ENV_FAT_FILE, (void *)&env_new, 0, sizeof(env_t),
&size);
if (err == -1) {
- printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
+ /*
+ * This printf is embedded in the messages from env_save that
+ * will calling it. The missing \n is intentional.
+ */
+ printf("Unable to write \"%s\" from %s%d:%d... ",
CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part);
return 1;
}
- puts("done\n");
return 0;
}
#endif /* CMD_SAVEENV */
dev = dev_desc->devnum;
if (fat_set_blk_dev(dev_desc, &info) != 0) {
- printf("\n** Unable to use %s %d:%d for loading the env **\n",
+ /*
+ * This printf is embedded in the messages from env_save that
+ * will calling it. The missing \n is intentional.
+ */
+ printf("Unable to use %s %d:%d... ",
CONFIG_ENV_FAT_INTERFACE, dev, part);
goto err_env_relocate;
}
err = file_fat_read(CONFIG_ENV_FAT_FILE, buf, CONFIG_ENV_SIZE);
if (err == -1) {
- printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
+ /*
+ * This printf is embedded in the messages from env_save that
+ * will calling it. The missing \n is intentional.
+ */
+ printf("Unable to read \"%s\" from %s%d:%d... ",
CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part);
goto err_env_relocate;
}
goto fini;
}
- puts("done\n");
ret = 0;
#ifdef CONFIG_ENV_OFFSET_REDUND
#ifndef CONFIG_SPL_BUILD
#define CMD_SAVEENV
+#define INITENV
#endif
#ifdef CONFIG_ENV_OFFSET_REDUND
}
#endif
+#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
+static int env_sf_init(void)
+{
+ env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR);
+
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_valid = 1;
+ } else {
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+ }
+
+ return 0;
+}
+#endif
+
U_BOOT_ENV_LOCATION(sf) = {
.location = ENVL_SPI_FLASH,
ENV_NAME("SPI Flash")
#ifdef CMD_SAVEENV
.save = env_save_ptr(env_sf_save),
#endif
+#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
+ .init = env_sf_init,
+#endif
};
# SPDX-License-Identifier: GPL-2.0+
#
+# Provide symbol API_BUILD to signal that the API example is being built.
+KBUILD_CPPFLAGS += -DAPI_BUILD
+
ifeq ($(ARCH),powerpc)
LOAD_ADDR = 0x40000
endif
#include "btrfs.h"
#include <linux/lzo.h>
#include <u-boot/zlib.h>
+#include <asm/unaligned.h>
static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
{
if (clen < 4)
return -1;
- tot_len = le32_to_cpu(*(u32 *) cbuf);
+ tot_len = le32_to_cpu(get_unaligned((u32 *)cbuf));
cbuf += 4;
clen -= 4;
tot_len -= 4;
res = 0;
while (tot_len > 4) {
- in_len = le32_to_cpu(*(u32 *) cbuf);
+ in_len = le32_to_cpu(get_unaligned((u32 *)cbuf));
cbuf += 4;
clen -= 4;
#include "btrfs.h"
#include <u-boot/crc.h>
+#include <asm/unaligned.h>
static u32 btrfs_crc32c_table[256];
void btrfs_csum_final(u32 crc, void *result)
{
- *((u32 *) result) = cpu_to_le32(~crc);
+ put_unaligned(cpu_to_le32(~crc), (u32 *)result);
}
if (sb->sys_chunk_array_size < sizeof(struct btrfs_key) +
sizeof(struct btrfs_chunk)) {
- printf("%s: system chunk array too small %u < %lu\n", __func__,
- sb->sys_chunk_array_size, (u32) sizeof(struct btrfs_key)
+ printf("%s: system chunk array too small %u < %zu\n", __func__,
+ sb->sys_chunk_array_size, sizeof(struct btrfs_key)
+ sizeof(struct btrfs_chunk));
ret = -1;
}
+config FS_EXT4
+ bool "Enable ext4 filesystem support"
+ help
+ This provides support for reading images from the ext4 filesystem.
+ ext4 is a widely used general-purpose filesystem for Linux.
+ You can also enable CMD_EXT4 to get access to ext4 commands.
+
+config EXT4_WRITE
+ bool "Enable ext4 filesystem write support"
+ depends on FS_EXT4
+ help
+ This provides support for creating and writing new files to an
+ existing ext4 filesystem partition.
existing FAT filesystem partition.
config FS_FAT_MAX_CLUSTSIZE
- int "Set maximum possible clusersize"
+ int "Set maximum possible clustersize"
default 65536
depends on FS_FAT
help
#include <linux/compiler.h>
#include <linux/ctype.h>
-#ifdef CONFIG_SUPPORT_VFAT
-static const int vfat_enabled = 1;
-#else
-static const int vfat_enabled = 0;
-#endif
-
/*
* Convert a string to lowercase. Converts at most 'len' characters,
* 'len' may be larger than the length of 'str' if 'str' is NULL
return -1;
}
- if (vfat_enabled)
- debug("VFAT Support enabled\n");
-
debug("FAT%d, fat_sect: %d, fatlength: %d\n",
mydata->fatsize, mydata->fat_sect, mydata->fatlength);
debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
continue;
if (dent->attr & ATTR_VOLUME) {
- if (vfat_enabled &&
- (dent->attr & ATTR_VFAT) == ATTR_VFAT &&
+ if ((dent->attr & ATTR_VFAT) == ATTR_VFAT &&
(dent->name[0] & LAST_LONG_ENTRY_MASK)) {
dent = extract_vfat_name(itr);
if (!dent)
if (ret)
goto out_free_both;
- printf("reading %s\n", filename);
+ debug("reading %s\n", filename);
ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
out_free_both:
continue;
}
if ((dentptr->attr & ATTR_VOLUME)) {
- if (vfat_enabled &&
- (dentptr->attr & ATTR_VFAT) &&
+ if ((dentptr->attr & ATTR_VFAT) &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
get_long_file_name(mydata, curclust,
get_dentfromdir_block,
/* If we requested a specific number of bytes, check we got it */
if (ret == 0 && len && *actread != len)
- printf("** %s shorter than offset + len **\n", filename);
+ debug("** %s shorter than offset + len **\n", filename);
fs_close();
return ret;
atomic64_sub(i, v);
}
+#ifndef __UBOOT__
static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
(atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
#define atomic_long_xchg(v, new) \
(atomic64_xchg((atomic64_t *)(v), (new)))
+#endif /* __UBOOT__ */
#else /* BITS_PER_LONG == 64 */
#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Environment valid? enum env_valid */
+ unsigned long env_has_init; /* Bitmask of boolean of struct env_location offsets */
unsigned long ram_top; /* Top address of RAM used by U-Boot */
unsigned long relocaddr; /* Start address of U-Boot in RAM */
IF_TYPE_HOST,
IF_TYPE_SYSTEMACE,
IF_TYPE_NVME,
+ IF_TYPE_EFI,
IF_TYPE_COUNT, /* Number of interface types */
};
*/
ulong (*set_rate)(struct clk *clk, ulong rate);
/**
+ * set_parent() - Set current clock parent
+ *
+ * @clk: The clock to manipulate.
+ * @parent: New clock parent.
+ * @return zero on success, or -ve error code.
+ */
+ int (*set_parent)(struct clk *clk, struct clk *parent);
+ /**
* enable() - Enable a clock.
*
* @clk: The clock to manipulate.
#endif
+#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
+ CONFIG_IS_ENABLED(CLK)
+/**
+ * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}'
+ * properties to configure clocks
+ *
+ * @dev: A device to process (the ofnode associated with this device
+ * will be processed).
+ */
+int clk_set_defaults(struct udevice *dev);
+#else
+static inline int clk_set_defaults(struct udevice *dev)
+{
+ return 0;
+}
+#endif
+
/**
* clk_request - Request a clock by provider-specific ID.
*
ulong clk_set_rate(struct clk *clk, ulong rate);
/**
+ * clk_set_parent() - Set current clock parent.
+ *
+ * @clk: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @parent: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @return new rate, or -ve error code.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent);
+
+/**
* clk_enable() - Enable (turn on) a clock.
*
* @clk: A clock struct that was previously successfully requested by
int misc_init_f (void);
int misc_init_r (void);
+#if defined(CONFIG_VID)
+int init_func_vid(void);
+#endif
/* common/exports.c */
void jumptable_init(void);
#ifdef CONFIG_CMD_UBIFS
#define BOOTENV_SHARED_UBIFS \
"ubifs_boot=" \
- "if ubi part UBI && ubifsmount ubi${devnum}:boot; then " \
- "setenv devtype ubi; " \
- "setenv bootpart 0; " \
- "run scan_dev_for_boot; " \
+ "env exists bootubipart || " \
+ "env set bootubipart UBI; " \
+ "env exists bootubivol || " \
+ "env set bootubivol boot; " \
+ "if ubi part ${bootubipart} && " \
+ "ubifsmount ubi${devnum}:${bootubivol}; " \
+ "then " \
+ "setenv devtype ubi; " \
+ "run scan_dev_for_boot; " \
"fi\0"
#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV
"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \
"if fdt addr ${fdt_addr_r}; then " \
"bootefi ${kernel_addr_r} ${fdt_addr_r};" \
- "else " \
+ "else " \
"bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
"fi\0" \
\
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
-#if defined(CONFIG_ENV_IS_IN_FAT) && !defined(CONFIG_FS_FAT)
-#define CONFIG_FS_FAT
-#endif
-
-#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
- !defined(CONFIG_FS_EXT4)
-#define CONFIG_FS_EXT4
-#endif
-
-#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)
-#define CONFIG_EXT4_WRITE
-#endif
-
/* Rather than repeat this expression each time, add a define for it */
#if defined(CONFIG_IDE) || \
defined(CONFIG_SATA) || \
defined(CONFIG_MMC) || \
defined(CONFIG_NVME) || \
defined(CONFIG_SYSTEMACE) || \
+ (defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)) || \
defined(CONFIG_SANDBOX)
#define HAVE_BLOCK_DEVICE
#endif
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_M52277EVB /* M52277EVB board */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#ifndef _M5253DEMO_H
#define _M5253DEMO_H
-#define CONFIG_M5253DEMO /* define board type */
-
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#ifndef _M5253EVBE_H
#define _M5253EVBE_H
-#define CONFIG_M5253EVBE /* define board type */
-
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_M5275EVB /* define board type */
#define CONFIG_MCFTMR
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_M54418TWR /* M54418TWR board */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
- || defined(CONFIG_USB_STORAGE)
- #define CONFIG_SUPPORT_VFAT
-#endif
-
-#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
-#endif
-
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC834x 1 /* MPC834x specific */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_TQM834X 1 /* TQM834X board specific */
#define CONFIG_SYS_TEXT_BASE 0x80000000
/*
* CPU and Board Configuration Options
*/
-#define CONFIG_ADP_AG101P
-
#define CONFIG_USE_INTERRUPT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define __ALT_H
#undef DEBUG
-#define CONFIG_R8A7794
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
#include "rcar-gen2-common.h"
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
/* settings we don;t want on this board */
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
-#undef CONFIG_CMD_EXT4
-#undef CONFIG_CMD_EXT4_WRITE
#undef CONFIG_CMD_SPI
#define CONFIG_CMD_CACHE
* Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
* Enable CONFIG_USB_MUSB_UDC for Device functionalities.
*/
-#define CONFIG_USB_AM35X 1
-#define CONFIG_USB_MUSB_HCD 1
#ifdef CONFIG_USB_AM35X
#endif /* CONFIG_USB_AM35X */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* Board NAND Info.
* Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
*/
-#define CONFIG_USB_MUSB_AM35X
-#define CONFIG_USB_MUSB_PIO_ONLY
#ifdef CONFIG_USB_MUSB_AM35X
#endif /* CONFIG_USB_MUSB_AM35X */
/* I2C */
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* Ethernet */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
#endif
#endif
#ifdef CONFIG_QSPI_BOOT
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
-#endif
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
/* SATA */
#ifndef __AMCORE_CONFIG_H
#define __AMCORE_CONFIG_H
-#define CONFIG_AMCORE
#define CONFIG_HOSTNAME AMCORE
#define CONFIG_MCFTMR
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_SUPPORT_VFAT
/*
* Ethernet (on SOC imx FEC)
#define __ARMADILLO_800EVA_H
#undef DEBUG
-#define CONFIG_R8A7740
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
#define CONFIG_SH_GPIO_PFC
#error No card type defined!
#endif
-#define CONFIG_ASTRO5373L /* define board type */
-
/* Command line configuration */
/*
* CONFIG_RAM defines if u-boot is loaded via BDM (or started from
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN SZ_2M
-#define CONFIG_SYS_BOOTM_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
#define CONFIG_MTD_DEVICE
/* I2C configuration */
-#undef CONFIG_SYS_OMAP24_I2C_SPEED
-#define CONFIG_SYS_OMAP24_I2C_SPEED 1000
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define __BLANCHE_H
#undef DEBUG
-#define CONFIG_R8A7792
#define CONFIG_RMOBILE_BOARD_STRING "Blanche"
#include "rcar-gen2-common.h"
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6318_H
+#define __CONFIG_BMIPS_BCM6318_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6318_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6368_H
+#define __CONFIG_BMIPS_BCM6368_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0xb8000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+
+#endif /* __CONFIG_BMIPS_BCM6368_H */
#endif /* CONFIG_NAND */
/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#else
#error "no storage for Environment defined!"
#endif
-/*
- * Common filesystems support. When we have removable storage we
- * enabled a number of useful commands and support.
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-#endif /* CONFIG_MMC, ... */
#endif /* ! __CONFIG_BRPPT1_H__ */
#define CONFIG_INITRD_TAG
/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
/* I2C */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* Our platforms make use of SPL to initalize the hardware (primarily
/*
* SoC Configuration
*/
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE 0x60000000
-#define CONFIG_DA850_LOWLEVEL
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM \
((calimain_get_osc_freq() == 25000000) ? 23 : 24)
/* NAND: SPL related configs */
/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
/* USB Networking options */
*/
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
-/* Partition support */
-
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-/* USB */
-#define CONFIG_USB_OMAP3
-#define CONFIG_USB_MUSB_UDC
-#define CONFIG_TWL4030_USB
-
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
115200}
/* USB */
-#define CONFIG_USB_MUSB_AM35X
#ifndef CONFIG_USB_MUSB_AM35X
-#define CONFIG_USB_OMAP3
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
-#else /* !CONFIG_USB_MUSB_AM35X */
-#define CONFIG_USB_MUSB_PIO_ONLY
#endif /* CONFIG_USB_MUSB_AM35X */
/* commands to include */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* USB support */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
/* SPI Flash support */
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6318.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6368.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_CYRUS
-
#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_DA8XX_GPIO
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
-#define CONFIG_DA850_LOWLEVEL
#else
#define CONFIG_SYS_TEXT_BASE 0xc1080000
#endif
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_CLOCKS
#endif
-#ifndef CONFIG_DRIVER_TI_EMAC
-#endif
-
#ifdef CONFIG_USE_NAND
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
-#ifdef CONFIG_USE_SPIFLASH
-#endif
-
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_SYS_ALT_MEMTEST
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-/* Partition support */
-
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* Partition support */
-
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_MVEBU
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
/* SATA */
"pxefile_addr_r=0x90100000\0"\
BOOTENV
-#define CONFIG_EXT4_WRITE
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#endif
/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
-#define CONFIG_SUPPORT_VFAT
#define CONFIG_SYS_MVFS
/*
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#include "tam3517-common.h"
-#undef CONFIG_USB_OMAP3
-
/* Our console port is port3 */
#undef CONFIG_CONS_INDEX
#undef CONFIG_SYS_NS16550_COM1
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
/* Serial port hardware configuration */
-#define CONFIG_PL010_SERIAL
#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
115200, 230400}
*/
#ifdef CONFIG_CMD_USB
#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
-#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/*
#define __GOSE_H
#undef DEBUG
-#define CONFIG_R8A7793
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"
#include "rcar-gen2-common.h"
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */
-#define CONFIG_SUPPORT_VFAT
-
#endif /* __CONFIG_GPLUGD_H */
*/
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 150000000
#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
#define CONFIG_CONS_INDEX 0
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-/* Serial port PL010/PL011 through the device model */
-#define CONFIG_PL01X_SERIAL
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
/* SD/MMC configuration */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FS_EXT4
-
/* Command line configuration */
#define CONFIG_MTD_PARTITIONS
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN SZ_2M
-#define CONFIG_SYS_BOOTM_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
*/
#define CONFIG_MPC831x
#define CONFIG_MPC8313
-#define CONFIG_IDS8313
#define CONFIG_FSL_ELBC
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
-/* Serial port PL010/PL011 through the device model */
-#define CONFIG_PL01X_SERIAL
#define CONFIG_CONS_INDEX 0
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 24
"findfdt="\
"if test $board_name = 66AK2GGP; then " \
"setenv name_fdt keystone-k2g-evm.dtb; " \
+ "else if test $board_name = 66AK2GG1; then " \
+ "setenv name_fdt keystone-k2g-evm.dtb; " \
"else if test $board_name = 66AK2GIC; then " \
"setenv name_fdt keystone-k2g-ice.dtb; " \
"else if test $name_fdt = undefined; then " \
"echo WARNING: Could not determine device tree to use;"\
- "fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
+ "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
"name_mon=skern-k2g.bin\0" \
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
#endif
/* SPL SPI Loader Configuration */
-#define CONFIG_SPL_TEXT_BASE 0x0c080000
+#define CONFIG_SPL_TEXT_BASE 0x0c0a0000
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_REF_CLK 384000000
-#define CONFIG_CQSPI_DECODER 0x0
-#define CONFIG_BOUNCE_BUFFER
#endif
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
/*
* USB gadget
*/
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_OMAP2PLUS
-
/*
* Environment
*/
#define __KOELSCH_H
#undef DEBUG
-#define CONFIG_R8A7791
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Koelsch"
#include "rcar-gen2-common.h"
#define __LAGER_H
#undef DEBUG
-#define CONFIG_R8A7790
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
#include "rcar-gen2-common.h"
/*
* SoC Configuration
*/
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 50000000
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012A2G5RDB_H__
+#define __LS1012A2G5RDB_H__
+
+#include "ls1012a_common.h"
+
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR 0x2
+#define EMAC2_PHY_ADDR 0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
+#endif
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_NET_MULTI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x00f00000\0" \
+ "kernel_addr=0x01000000\0" \
+ "kernelheader_addr=0x800000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernelheader_size=0x40000\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV \
+ "boot_scripts=ls1012ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;" \
+ "\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "installer=load mmc 0:2 $load_addr " \
+ "/flex_installer_arm64.itb; " \
+ "bootm $load_addr#$board\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_addr $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#endif
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A2G5RDB_H__ */
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#include <config_distro_defaults.h>
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
+ func(SCSI, scsi, 0) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#endif
+/* SATA */
+#ifndef SPL_NO_SATA
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
/* Command line configuration */
/* MMC */
#include <config_distro_defaults.h>
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
+ func(SCSI, scsi, 0) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#define CFG_LPUART_EN 0x2
#endif
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/*
* IFC Definitions
*/
#endif
#endif
-/* SATA */
-#ifndef SPL_NO_SATA
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_SUPPORT_RAW_INITRD
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
+ CONFIG_ENV_OFFSET)
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#define QIXIS_LBMAP_DFLTBANK 0x0e
#define QIXIS_LBMAP_ALTBANK 0x2e
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
+#define QIXIS_LBMAP_IFC 0x00
#define QIXIS_LBMAP_SD_QSPI 0x0e
#define QIXIS_LBMAP_QSPI 0x0e
+#define QIXIS_RCW_SRC_IFC 0x25
#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_EMMC 0x41
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define I2C_SVDD_MONITOR_ADDR 0x4F
+
+#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088AQDS */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+
+#define PWM_CHANNEL0 0x0
+
/*
* RTC configuration
*/
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#endif
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_BRDCFG4_OFFSET 0x54
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x20
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
#define QIXIS_LBMAP_SD_QSPI 0x00
#define QIXIS_LBMAP_QSPI 0x00
#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_EMMC 0x41
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define I2C_SVDD_MONITOR_ADDR 0x4F
+
+#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088ARDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+
+#define PWM_CHANNEL0 0x0
+
/*
* I2C bus multiplexer
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* RTC */
#define CONFIG_RTC_DS1337
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFC000000
#endif
/*
- * Common USB/EHCI configuration
- */
-#if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM)
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
-
-/*
* File system
*/
#ifdef CONFIG_SYS_MVFS
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SUPPORT_VFAT
-
#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func) \
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SUPPORT_VFAT
-
/*
* PCI configuration
*/
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
-/* U-Boot commands */
-
-/* Filesystem support */
-#define CONFIG_FS_EXT4
-
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
* DUART Serial Driver.
* Conflicts with AUART driver which can be set by board.
*/
-#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/*
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
-/* USB */
-#define CONFIG_USB_MUSB_UDC
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_OMAP3
-#define CONFIG_TWL4030_USB
-
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USBD_VENDORID 0x0421
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* TWL4030
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#include <configs/ti_omap3_common.h>
+
/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs. We use this rather than the inherited defines from
- * ti_armv7_common.h for backwards compatibility.
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE 0x40200000
-#include <configs/ti_omap3_common.h>
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
-#define CONFIG_REVISION_TAG 1
+/* NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
+/* NAND: SPL falcon mode configs */
+#if defined(CONFIG_SPL_OS_BOOT)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#endif /* CONFIG_SPL_OS_BOOT */
+#endif /* CONFIG_NAND */
-/* Status LED */
-
-/* Enable Multi Bus support for I2C */
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* Probe all devices */
-#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
-
-/* USB */
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_TWL4030_USB 1
+/* MUSB */
+#define CONFIG_USB_OMAP3
/* USB EHCI */
-
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-/* commands to include */
-
-#define CONFIG_VIDEO_OMAP3 /* DSS Support */
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_LED 1
+/* DSS Support */
+#define CONFIG_VIDEO_OMAP3
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
+/* TWL4030 LED Support */
+#define CONFIG_TWL4030_LED
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
"run bootscript; " \
"else " \
"if run loadimage; then " \
+ "run loadfdt;" \
"run mmcboot;" \
"fi;" \
"fi; " \
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "kernel_addr_r=0x80200000\0" \
- "rdaddr=0x81000000\0" \
- "initrd_addr_r=0x81000000\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"fdt_high=0xffffffff\0" \
- "fdtaddr=0x80f80000\0" \
- "fdt_addr_r=0x80f80000\0" \
"usbtty=cdc_acm\0" \
"bootfile=uImage\0" \
"ramdisk=ramdisk.gz\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
"nandroot=ubi0:rootfs ubi.mtd=4\0" \
"nandrootfstype=ubifs\0" \
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
"loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=echo Booting from mmc ...; " \
+ "mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
"run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"userbutton_nonxm=gpio input 7;\0" \
BOOTENV
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-/* Defines for SPL */
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
#endif /* __CONFIG_H */
#endif /* CONFIG_NAND */
/* MUSB */
-#define CONFIG_USB_OMAP3
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_MUSB_PIO_ONLY
/* USB EHCI */
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
-#if defined(CONFIG_NAND)
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"run nandboot\0"
-
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
#devtypel #instance " "
-#endif /* CONFIG_NAND */
-#define BOOTENV_DEV_UIMAGE_MMC(devtypeu, devtypel, instance) \
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
- "setenv mmcdev " #instance"; " \
- "run mmcboot\0"
-
-#define BOOTENV_DEV_NAME_UIMAGE_MMC(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#define BOOTENV_DEV_ZIMAGE_MMC(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "setenv mmcdev " #instance"; " \
- "run mmcbootz\0"
-
-#define BOOTENV_DEV_NAME_ZIMAGE_MMC(devtypeu, devtypel, instance) \
+ "setenv mmcdev " #instance "; " \
+ "setenv bootpart " #instance ":${mmcpart} ; " \
+ "run mmcboot\0"
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
#devtypel #instance " "
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(ZIMAGE_MMC, zimage_mmc, 0) \
- func(UIMAGE_MMC, uimage_mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(UBIFS, ubifs, 0) \
func(NAND, nand, 0)
#include <config_distro_bootcmd.h>
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"fdt_high=0xffffffff\0" \
+ "bootdir=/boot\0" \
"bootenv=uEnv.txt\0" \
+ "bootfile=zImage\0" \
+ "bootubivol=rootfs\0" \
+ "bootubipart=rootfs\0" \
"optargs=\0" \
"mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "bootpart=${mmcdev}:${mmcpart}\0" \
"console=ttyO0,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"${mtdparts} " \
"root=ubi0:rootfs rw ubi.mtd=rootfs noinitrd " \
"rootfstype=ubifs rootwait\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
- "mmcbootenv=" \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan && run loadbootenv; then " \
- "run importbootenv; " \
+ "mmcbootenv=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "run loadbootenv && run importbootenv; " \
+ "run ext4bootenv && run importbootenv; " \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...; " \
"run uenvcmd; " \
"fi; " \
"fi\0" \
- "loaduimage=setenv bootfile uImage; " \
- "fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "loadzimage=setenv bootfile zImage; " \
- "fatload mmc ${mmcdev} ${loadaddr} zImage\0" \
- "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+ "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loaddtb=ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=run mmcbootenv; " \
- "if run loaduimage && run loaddtb; then " \
- "echo Booting ${bootfile} from mmc ...; " \
+ "if run loadimage && run loaddtb; then " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
"run mmcargs; " \
- "bootm ${loadaddr} - ${fdtaddr}; " \
+ "if test ${bootfile} = uImage; then " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
+ "fi; " \
+ "if test ${bootfile} = zImage; then " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi; " \
"fi\0" \
- "mmcbootz=run mmcbootenv; " \
- "if run loadzimage && run loaddtb; then " \
- "echo Booting ${bootfile} from mmc ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr};" \
+ "nandboot=" \
+ "if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+ "echo Booting uImage from NAND MTD 'kernel' partition ...; " \
+ "run nandargs; " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
"fi\0" \
- "nandboot=echo Booting uImage from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} kernel; " \
- "nand read ${fdtaddr} dtb; " \
- "bootm ${loadaddr} - ${fdtaddr}\0" \
BOOTENV
#endif /* __CONFIG_H */
#define GPIO_IGEP00X0_BOARD_DETECTION 28
#define GPIO_IGEP00X0_REVISION_DETECTION 129
-/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_TWL4030_USB 1
-
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
/* Hardware drivers */
-#define CONFIG_USB_OMAP3
-
/* I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
-/* USB */
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_MUSB_PIO_ONLY
-
-/* TWL4030 */
-#define CONFIG_TWL4030_USB
-
/* Board NAND Info. */
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
* Hardware drivers
*/
-/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_TWL4030_USB 1
-
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
*/
#define CONFIG_MACH_OMAPL138_LCDK
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
#define CONFIG_SYS_DA850_PLL0_PLLM 37
#define CONFIG_SYS_DA850_PLL1_PLLM 21
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
/*
* USB configuration
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
--- /dev/null
+/*
+ * pdu001.h
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_PDU001_H
+#define __CONFIG_PDU001_H
+
+#include <configs/ti_am335x_common.h>
+
+/* No more need for I2C legacy compatibility for this board.
+ * CONFIG_DM_I2C_COMPAT is defined in ti_armv7_common.h. See the comment there
+ * for the right moment to delete the following line.
+ */
+#undef CONFIG_DM_I2C_COMPAT
+
+/* Using 32K of volatile storage for environment */
+#define CONFIG_ENV_SIZE 0x4000
+
+#define MACH_TYPE_PDU001 5075
+#define CONFIG_MACH_TYPE MACH_TYPE_PDU001
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#if CONFIG_CONS_INDEX == 1
+ #define CONSOLE_DEV "ttyO0"
+#elif CONFIG_CONS_INDEX == 2
+ #define CONSOLE_DEV "ttyO1"
+#elif CONFIG_CONS_INDEX == 3
+ #define CONSOLE_DEV "ttyO2"
+#elif CONFIG_CONS_INDEX == 4
+ #define CONSOLE_DEV "ttyO3"
+#elif CONFIG_CONS_INDEX == 5
+ #define CONSOLE_DEV "ttyO4"
+#elif CONFIG_CONS_INDEX == 6
+ #define CONSOLE_DEV "ttyO5"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "run eval_boot_device;" \
+ "setenv bootargs console=${console} " \
+ "vt.global_cursor_default=0 " \
+ "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \
+ "rootfstype=ext4 " \
+ "rootwait " \
+ "rootdelay=1;" \
+ "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \
+ "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \
+ "bootz ${loadaddr} - ${fdtaddr}"
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "fdtfile=am335x-pdu001.dtb\0" \
+ "bootfile=zImage\0" \
+ "console=" CONSOLE_DEV ",115200n8\0" \
+ "root_fs_partition=2\0" \
+ "eval_boot_device=" \
+ "if test $boot_device = emmc; then " \
+ "setenv mmc_boot 0;" \
+ "elif test $boot_device = sdcard; then " \
+ "setenv mmc_boot 1;" \
+ "else " \
+ "echo Bootdevice is neither MMC0 nor MMC1;" \
+ "reset;" \
+ "fi;" \
+ "\0"
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 UART1_BASE
+#define CONFIG_SYS_NS16550_COM3 UART2_BASE
+#define CONFIG_SYS_NS16550_COM4 UART3_BASE
+#define CONFIG_SYS_NS16550_COM5 UART4_BASE
+#define CONFIG_SYS_NS16550_COM6 UART5_BASE
+#define CONFIG_BAUDRATE 115200
+
+#endif /* ! __CONFIG_PDU001_H */
* board schematic and physical port wired to each. Then for host we
* add mass storage support.
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
/*--------------------------------------------------
* USB Configuration
*/
-#define CONFIG_USB_MUSB_PIO_ONLY
-
-/*-----------------------------------------------------------------------
- * File System Configuration
- */
-/* FAT FS */
-#define CONFIG_SUPPORT_VFAT
-
-/* EXT4 FS */
-#define CONFIG_FS_EXT4
/* -------------------------------------------------
* Environment
/* ATF bl33.bin load address (must match) */
#define CONFIG_SYS_TEXT_BASE 0x37000000
-/* PL010/PL011 */
-#define CONFIG_PL01X_SERIAL
-
/* USB configuration */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (0x780 * 512) /* env_mmc_blknum */
#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */
-#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
/* Monitor Command Prompt */
#define __PORTER_H
#undef DEBUG
-#define CONFIG_R8A7791
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
#include "rcar-gen2-common.h"
#endif
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
+#define CONFIG_SYS_INIT_SP_ADDR 0x7023FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
#endif
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* SD */
-#define CONFIG_SH_SDHI_FREQ 97500000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
-
#endif /* __PORTER_H */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
#define CONFIG_SYS_MALLOC_LEN SZ_16M
-/* QEMU's PL011 serial port is detected via FDT using the device model */
-#define CONFIG_PL01X_SERIAL
-
/* QEMU implements a 62.5MHz architected timer */
/* FIXME: can we rely on CNTFREQ instead of hardcoding this fact here? */
#define CONFIG_SYS_ARCH_TIMER
#include <asm/arch/rmobile.h>
-/* Support File sytems */
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_TMU_TIMER
+#ifndef CONFIG_PINCTRL_PFC
#define CONFIG_SH_GPIO_PFC
+#endif
/* console */
/* boot option */
#define CONFIG_SUPPORT_RAW_INITRD
-/* Support File sytems */
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#ifndef CONFIG_SPL_BUILD
/* usb otg */
-#define CONFIG_ROCKCHIP_USB2_PHY
/* usb host support */
#define ENV_MEM_LAYOUT_SETTINGS \
#ifndef CONFIG_SPL_BUILD
/* usb otg */
-#define CONFIG_ROCKCHIP_USB2_PHY
/* usb mass storage */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_EXT4
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_MISC_INIT_R
#endif
-/* Console UART */
-#if defined (CONFIG_BCM2837) || defined(CONFIG_TARGET_RPI_0_W)
-#define CONFIG_BCM283X_MU_SERIAL
-#else
-#define CONFIG_PL01X_SERIAL
-#endif
-
/* Console configuration */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SAMSUNG_ONENAND 1
#define CONFIG_SYS_ONENAND_BASE 0xB0000000
-/* write support for filesystems */
-#define CONFIG_EXT4_WRITE
-
-/* GPT */
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_LMB
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
#define CONFIG_HOST_MAX_DEVICES 4
/*
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
#define CONFIG_SYS_TEXT_BASE 0xFF800000
/*
* High Level Configuration Options
*/
-#define CONFIG_SBC8548 1 /* SBC8548 board specific */
/*
* If you want to boot from the SODIMM flash, instead of the soldered
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
/*
* USB configuration
*/
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define __SILK_H
#undef DEBUG
-#define CONFIG_R8A7794
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk"
#include "rcar-gen2-common.h"
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
/*
115200 }
/*
- * USB gadget
- */
-
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_TWL4030_USB
-
-/*
* Environment
*/
#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
#endif
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-
/*
* Cache
*/
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
-#define CONFIG_CQSPI_DECODER 0
-#define CONFIG_BOUNCE_BUFFER
/*
* Designware SPI support
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
#ifdef CONFIG_CMD_PXE
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_PXE(func) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_DEVICES_DHCP(func)
#include <config_distro_bootcmd.h>
* Serial Configuration (PL011)
* CONFIG_PL01x_PORTS is defined in specific files
*/
-#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
#define CONFIG_STM32_FLASH
-#define CONFIG_STM32_HSE_HZ 8000000
-
#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
--- /dev/null
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_RAM_FREQ_DIV 2
+#define CONFIG_SYS_RAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0x00400000
+#define CONFIG_LOADADDR 0x00400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT 12
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (128 << 10)
+#define CONFIG_ENV_SIZE (8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE 1024
+
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+#define CONFIG_BOOTCOMMAND \
+ "run boot_sd"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32429i-eval.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#endif /* __CONFIG_H */
#define CONFIG_STM32_FLASH
-#define CONFIG_STM32_HSE_HZ 8000000
#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_MII
#define CONFIG_PHY_SMSC
-#define CONFIG_STM32_HSE_HZ 25000000
#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_SPL_LEN 0x00008000
#ifndef __STMARK2_CONFIG_H
#define __STMARK2_CONFIG_H
-#define CONFIG_STMARK2
#define CONFIG_HOSTNAME stmark2
#define CONFIG_MCFUART
#define __STOUT_H
#undef DEBUG
-#define CONFIG_R8A7790
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout"
#include "rcar-gen2-common.h"
(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
-/* serial port (PL011) configuration */
-#define CONFIG_PL01X_SERIAL
-
/* user interface */
#define CONFIG_SYS_CBSIZE 1024
+ * QSPI support
+ */
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
-#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
-#define CONFIG_BOUNCE_BUFFER
#endif
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
+
+#ifdef CONFIG_ARM64
+/*
+ * This is actually (CONFIG_ENV_OFFSET -
+ * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used
+ * directly in a makefile, without the preprocessor expansion.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT 0x7e000
+#endif
+
#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
/* If we have two devices (most likely eMMC + MMC), favour the eMMC */
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
-#ifdef CONFIG_USB_MUSB_SUNXI
-#define CONFIG_USB_MUSB_PIO_ONLY
-#endif
-
#ifdef CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
/*
#ifdef CONFIG_CMD_I2C
#endif
-/* remove partitions/filesystems */
-#ifdef CONFIG_FS_EXT4
-#undef CONFIG_FS_EXT4
-#endif
-
/* remove USB */
#ifdef CONFIG_USB_EHCI_TEGRA
#undef CONFIG_USB_EHCI_TEGRA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* PCIe support */
#ifdef CONFIG_CMD_PCI
#ifndef CONFIG_SPL_BUILD
/* PL011 Serial Configuration */
-#define CONFIG_PL01X_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_CONS_INDEX 1
#endif
/* SPI Configuration */
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
"${bootdir}/${fit_bootfile}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
- "burn_uboot_spi=sf probe; sf erase 0 0x90000; " \
+ "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
#define __CONFIG_TI_ARMV7_OMAP_H__
/* I2C IP block */
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* GPMC NAND block. We support 1 device and the physical address to
#endif
/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
/* I2C */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* EEPROM */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
* Commands
*/
#if defined(CONFIG_CMD_USB)
-#define CONFIG_SUPPORT_VFAT
/*
* USB/EHCI
#define CONFIG_E300 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
-#define CONFIG_VE8313 1
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfe000000
/* PL011 Serial Configuration */
#define CONFIG_CONS_INDEX 0
-#define CONFIG_PL01X_SERIAL
-#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7273800
#else
#define CONFIG_SYS_TIMER_COUNTS_DOWN
/* PL011 Serial Configuration */
-#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
#define CONFIG_SYS_SERIAL1 0xD0080000
#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1 }
-#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
#define CONFIG_USB_EHCI_SPEAR
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-/* Filesystem support (for USB key) */
-#define CONFIG_SUPPORT_VFAT
-
-
/*
* U-Boot Environment placing definitions.
*/
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SUPPORT_VFAT
-
/*-----------------------------------------------------------------------
* Command line configuration.
*/
+#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200
/*
* High Level Configuration Options
*/
-#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
/*
* High Level Configuration Options
*/
-#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
/*
* High Level Configuration Options
*/
-#define CONFIG_XPEDITE550X 1
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/* SDRAM */
# define DFU_ALT_INFO
#endif
-#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQ_USB)
-# define CONFIG_SUPPORT_VFAT
-#endif
-
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
#define CONFIG_SYS_I2C_ZYNQ
#endif
ofnode_valid(node); \
node = ofnode_next_subnode(node))
+/**
+ * ofnode_translate_address() - Tranlate a device-tree address
+ *
+ * Translate an address from the device-tree into a CPU physical address. This
+ * function walks up the tree and applies the various bus mappings along the
+ * way.
+ *
+ * @ofnode: Device tree node giving the context in which to translate the
+ * address
+ * @in_addr: pointer to the address to translate
+ * @return the translated address; OF_BAD_ADDR on error
+ */
+u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr);
#endif
/**
* Generic pin configuration paramters
*
+ * enum pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
+ * weakly drives the last value on a tristate bus, also known as a "bus
+ * holder", "bus keeper" or "repeater". This allows another device on the
+ * bus to change the value by driving the bus high or low and switching to
+ * tristate. The argument is ignored.
* @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
* transition from say pull-up to pull-down implies that you disable
* pull-up in the process, this setting disables all biasing.
* if for example some other pin is going to drive the signal connected
* to it for a while. Pins used for input are usually always high
* impedance.
- * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
- * weakly drives the last value on a tristate bus, also known as a "bus
- * holder", "bus keeper" or "repeater". This allows another device on the
- * bus to change the value by driving the bus high or low and switching to
- * tristate. The argument is ignored.
- * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
- * impedance to VDD). If the argument is != 0 pull-up is enabled,
- * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
* @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
* impedance to GROUND). If the argument is != 0 pull-down is enabled,
* if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
* If the argument is != 0 pull up/down is enabled, if it is 0, the
* configuration is ignored. The proper way to disable it is to use
* @PIN_CONFIG_BIAS_DISABLE.
- * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
- * low, this is the most typical case and is typically achieved with two
- * active transistors on the output. Setting this config will enable
- * push-pull mode, the argument is ignored.
+ * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
+ * impedance to VDD). If the argument is != 0 pull-up is enabled,
+ * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
* @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
* collector) which means it is usually wired with other output ports
* which are then pulled up with an external resistor. Setting this
* @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
* (open emitter). Setting this config will enable open source mode, the
* argument is ignored.
+ * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ * low, this is the most typical case and is typically achieved with two
+ * active transistors on the output. Setting this config will enable
+ * push-pull mode, the argument is ignored.
* @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
* passed as argument. The argument is in mA.
+ * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
+ * which means it will wait for signals to settle when reading inputs. The
+ * argument gives the debounce time in usecs. Setting the
+ * argument to zero turns debouncing off.
* @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not
* affect the pin's ability to drive output. 1 enables input, 0 disables
* input.
- * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
- * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
- * schmitt-trigger mode is disabled.
* @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
* schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
* the threshold value is given on a custom format as argument when
* setting pins to this mode.
- * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
- * which means it will wait for signals to settle when reading inputs. The
- * argument gives the debounce time in usecs. Setting the
- * argument to zero turns debouncing off.
+ * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
+ * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
+ * schmitt-trigger mode is disabled.
+ * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
+ * operation, if several modes of operation are supported these can be
+ * passed in the argument on a custom form, else just use argument 1
+ * to indicate low power mode, argument 0 turns low power mode off.
+ * @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
+ * without driving a value there. For most platforms this reduces to
+ * enable the output buffers and then let the pin controller current
+ * configuration (eg. the currently selected mux function) drive values on
+ * the line. Use argument 1 to enable output mode, argument 0 to disable
+ * it.
+ * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
+ * value on the line. Use argument 1 to indicate high level, argument 0 to
+ * indicate low level. (Please see Documentation/driver-api/pinctl.rst,
+ * section "GPIO mode pitfalls" for a discussion around this parameter.)
* @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
* supplies, the argument to this parameter (on a custom format) tells
* the driver which alternative power source to use.
+ * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state.
* @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
* this parameter (on a custom format) tells the driver which alternative
* slew rate to use.
- * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
- * operation, if several modes of operation are supported these can be
- * passed in the argument on a custom form, else just use argument 1
- * to indicate low power mode, argument 0 turns low power mode off.
- * @PIN_CONFIG_OUTPUT: this will configure the pin as an output. Use argument
- * 1 to indicate high level, argument 0 to indicate low level. (Please
- * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a
- * discussion around this parameter.)
+ * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
+ * or latch delay (on outputs) this parameter (in a custom format)
+ * specifies the clock skew or latch delay. It typically controls how
+ * many double inverters are put in front of the line.
* @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
* you need to pass in custom configurations to the pin controller, use
* PIN_CONFIG_END+1 as the base offset.
+ * @PIN_CONFIG_MAX: this is the maximum configuration value that can be
+ * presented using the packed format.
*/
-#define PIN_CONFIG_BIAS_DISABLE 0
-#define PIN_CONFIG_BIAS_HIGH_IMPEDANCE 1
-#define PIN_CONFIG_BIAS_BUS_HOLD 2
-#define PIN_CONFIG_BIAS_PULL_UP 3
-#define PIN_CONFIG_BIAS_PULL_DOWN 4
-#define PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 5
-#define PIN_CONFIG_DRIVE_PUSH_PULL 6
-#define PIN_CONFIG_DRIVE_OPEN_DRAIN 7
-#define PIN_CONFIG_DRIVE_OPEN_SOURCE 8
-#define PIN_CONFIG_DRIVE_STRENGTH 9
-#define PIN_CONFIG_INPUT_ENABLE 10
-#define PIN_CONFIG_INPUT_SCHMITT_ENABLE 11
-#define PIN_CONFIG_INPUT_SCHMITT 12
-#define PIN_CONFIG_INPUT_DEBOUNCE 13
-#define PIN_CONFIG_POWER_SOURCE 14
-#define PIN_CONFIG_SLEW_RATE 15
-#define PIN_CONFIG_LOW_POWER_MODE 16
-#define PIN_CONFIG_OUTPUT 17
-#define PIN_CONFIG_END 0x7FFF
+enum pin_config_param {
+ PIN_CONFIG_BIAS_BUS_HOLD,
+ PIN_CONFIG_BIAS_DISABLE,
+ PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+ PIN_CONFIG_BIAS_PULL_DOWN,
+ PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
+ PIN_CONFIG_BIAS_PULL_UP,
+ PIN_CONFIG_DRIVE_OPEN_DRAIN,
+ PIN_CONFIG_DRIVE_OPEN_SOURCE,
+ PIN_CONFIG_DRIVE_PUSH_PULL,
+ PIN_CONFIG_DRIVE_STRENGTH,
+ PIN_CONFIG_INPUT_DEBOUNCE,
+ PIN_CONFIG_INPUT_ENABLE,
+ PIN_CONFIG_INPUT_SCHMITT,
+ PIN_CONFIG_INPUT_SCHMITT_ENABLE,
+ PIN_CONFIG_LOW_POWER_MODE,
+ PIN_CONFIG_OUTPUT_ENABLE,
+ PIN_CONFIG_OUTPUT,
+ PIN_CONFIG_POWER_SOURCE,
+ PIN_CONFIG_SLEEP_HARDWARE_STATE,
+ PIN_CONFIG_SLEW_RATE,
+ PIN_CONFIG_SKEW_DELAY,
+ PIN_CONFIG_END = 0x7F,
+ PIN_CONFIG_MAX = 0xFF,
+};
#if CONFIG_IS_ENABLED(PINCTRL_GENERIC)
/**
unsigned long base;
unsigned int clock;
bool skip_init;
- bool disabled;
};
#endif
#ifndef CONFIG_DM_DEV_READ_INLINE
/**
+ * dev_read_u32() - read a 32-bit integer from a device's DT property
+ *
+ * @dev: device to read DT property from
+ * @propname: name of the property to read from
+ * @outp: place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp);
+
+/**
* dev_read_u32_default() - read a 32-bit integer from a device's DT property
*
* @dev: device to read DT property from
* This walks back up the tree to find the closest #address-cells property
* which controls the given node.
*
- * @dev: devioe to check
+ * @dev: device to check
* @return number of address cells this node uses
*/
int dev_read_addr_cells(struct udevice *dev);
* This walks back up the tree to find the closest #size-cells property
* which controls the given node.
*
- * @dev: devioe to check
+ * @dev: device to check
* @return number of size cells this node uses
*/
int dev_read_size_cells(struct udevice *dev);
*
* This function matches fdt_address_cells().
*
- * @dev: devioe to check
+ * @dev: device to check
* @return number of address cells this node uses
*/
int dev_read_simple_addr_cells(struct udevice *dev);
*
* This function matches fdt_size_cells().
*
- * @dev: devioe to check
+ * @dev: device to check
* @return number of size cells this node uses
*/
int dev_read_simple_size_cells(struct udevice *dev);
int dev_read_resource_byname(struct udevice *dev, const char *name,
struct resource *res);
+/**
+ * dev_translate_address() - Tranlate a device-tree address
+ *
+ * Translate an address from the device-tree into a CPU physical address. This
+ * function walks up the tree and applies the various bus mappings along the
+ * way.
+ *
+ * @dev: device giving the context in which to translate the address
+ * @in_addr: pointer to the address to translate
+ * @return the translated address; OF_BAD_ADDR on error
+ */
+u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr);
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
+static inline int dev_read_u32(struct udevice *dev,
+ const char *propname, u32 *outp)
+{
+ return ofnode_read_u32(dev_ofnode(dev), propname, outp);
+}
+
static inline int dev_read_u32_default(struct udevice *dev,
const char *propname, int def)
{
return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
}
+static inline u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_address(dev_ofnode(dev), in_addr);
+}
+
#endif /* CONFIG_DM_DEV_READ_INLINE */
/**
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_DMA, /* Direct Memory Access */
+ UCLASS_EFI, /* EFI managed devices */
UCLASS_ETH, /* Ethernet device */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_FIRMWARE, /* Firmware */
* then this will be automatically allocated.
* @per_child_auto_alloc_size: Each child device (of a parent in this
* uclass) can hold parent data for the device/uclass. This value is only
- * used as a falback if this member is 0 in the driver.
+ * used as a fallback if this member is 0 in the driver.
* @per_child_platdata_auto_alloc_size: A bus likes to store information about
* its children. If non-zero this is the size of this data, to be allocated
* in the child device's parent_platdata pointer. This value is only used as
- * a falback if this member is 0 in the driver.
+ * a fallback if this member is 0 in the driver.
* @ops: Uclass operations, providing the consistent interface to devices
* within the uclass.
* @flags: Flags for this uclass (DM_UC_...)
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
+#define __DT_BINDINGS_CLOCK_BCM6318_H
+
+#define BCM6318_CLK_ADSL_ASB 0
+#define BCM6318_CLK_USB_ASB 1
+#define BCM6318_CLK_MIPS_ASB 2
+#define BCM6318_CLK_PCIE_ASB 3
+#define BCM6318_CLK_PHYMIPS_ASB 4
+#define BCM6318_CLK_ROBOSW_ASB 5
+#define BCM6318_CLK_SAR_ASB 6
+#define BCM6318_CLK_SDR_ASB 7
+#define BCM6318_CLK_SWREG_ASB 8
+#define BCM6318_CLK_PERIPH_ASB 9
+#define BCM6318_CLK_CPUBUS160 10
+#define BCM6318_CLK_ADSL 11
+#define BCM6318_CLK_SAR125 12
+#define BCM6318_CLK_MIPS 13
+#define BCM6318_CLK_PCIE 14
+#define BCM6318_CLK_ROBOSW250 16
+#define BCM6318_CLK_ROBOSW025 17
+#define BCM6318_CLK_SDR 19
+#define BCM6318_CLK_USB 20
+#define BCM6318_CLK_HSSPI 25
+#define BCM6318_CLK_PCIE25 27
+#define BCM6318_CLK_PHYMIPS 28
+#define BCM6318_CLK_AFE 29
+#define BCM6318_CLK_QPROC 30
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
+#define __DT_BINDINGS_CLOCK_BCM6368_H
+
+#define BCM6368_CLK_VDSL_QPROC 2
+#define BCM6368_CLK_VDSL_AFE 3
+#define BCM6368_CLK_VDSL_BONDING 4
+#define BCM6368_CLK_VDSL 5
+#define BCM6368_CLK_PHYMIPS 6
+#define BCM6368_CLK_SWPKT_USB 7
+#define BCM6368_CLK_SWPKT_SAR 8
+#define BCM6368_CLK_SPI 9
+#define BCM6368_CLK_USBD 10
+#define BCM6368_CLK_SAR 11
+#define BCM6368_CLK_ROBOSW 12
+#define BCM6368_CLK_UTOPIA 13
+#define BCM6368_CLK_PCM 14
+#define BCM6368_CLK_USBH 15
+#define BCM6368_CLK_GLESS 16
+#define BCM6368_CLK_NAND 17
+#define BCM6368_CLK_IPSEC 18
+#define BCM6368_CLK_USBH_IDDQ 19
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */
--- /dev/null
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN 0
+#define R8A7790_CLK_PLL0 1
+#define R8A7790_CLK_PLL1 2
+#define R8A7790_CLK_PLL3 3
+#define R8A7790_CLK_LB 4
+#define R8A7790_CLK_QSPI 5
+#define R8A7790_CLK_SDH 6
+#define R8A7790_CLK_SD0 7
+#define R8A7790_CLK_SD1 8
+#define R8A7790_CLK_Z 9
+#define R8A7790_CLK_RCAN 10
+#define R8A7790_CLK_ADSP 11
+
+/* MSTP0 */
+#define R8A7790_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7790_CLK_VCP1 0
+#define R8A7790_CLK_VCP0 1
+#define R8A7790_CLK_VPC1 2
+#define R8A7790_CLK_VPC0 3
+#define R8A7790_CLK_JPU 6
+#define R8A7790_CLK_SSP1 9
+#define R8A7790_CLK_TMU1 11
+#define R8A7790_CLK_3DG 12
+#define R8A7790_CLK_2DDMAC 15
+#define R8A7790_CLK_FDP1_2 17
+#define R8A7790_CLK_FDP1_1 18
+#define R8A7790_CLK_FDP1_0 19
+#define R8A7790_CLK_TMU3 21
+#define R8A7790_CLK_TMU2 22
+#define R8A7790_CLK_CMT0 24
+#define R8A7790_CLK_TMU0 25
+#define R8A7790_CLK_VSP1_DU1 27
+#define R8A7790_CLK_VSP1_DU0 28
+#define R8A7790_CLK_VSP1_R 30
+#define R8A7790_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2 2
+#define R8A7790_CLK_SCIFA1 3
+#define R8A7790_CLK_SCIFA0 4
+#define R8A7790_CLK_MSIOF2 5
+#define R8A7790_CLK_SCIFB0 6
+#define R8A7790_CLK_SCIFB1 7
+#define R8A7790_CLK_MSIOF1 8
+#define R8A7790_CLK_MSIOF3 15
+#define R8A7790_CLK_SCIFB2 16
+#define R8A7790_CLK_SYS_DMAC1 18
+#define R8A7790_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7790_CLK_IIC2 0
+#define R8A7790_CLK_TPU0 4
+#define R8A7790_CLK_MMCIF1 5
+#define R8A7790_CLK_SCIF2 10
+#define R8A7790_CLK_SDHI3 11
+#define R8A7790_CLK_SDHI2 12
+#define R8A7790_CLK_SDHI1 13
+#define R8A7790_CLK_SDHI0 14
+#define R8A7790_CLK_MMCIF0 15
+#define R8A7790_CLK_IIC0 18
+#define R8A7790_CLK_PCIEC 19
+#define R8A7790_CLK_IIC1 23
+#define R8A7790_CLK_SSUSB 28
+#define R8A7790_CLK_CMT1 29
+#define R8A7790_CLK_USBDMAC0 30
+#define R8A7790_CLK_USBDMAC1 31
+
+/* MSTP4 */
+#define R8A7790_CLK_IRQC 7
+#define R8A7790_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1 1
+#define R8A7790_CLK_AUDIO_DMAC0 2
+#define R8A7790_CLK_ADSP_MOD 6
+#define R8A7790_CLK_THERMAL 22
+#define R8A7790_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI 3
+#define R8A7790_CLK_HSUSB 4
+#define R8A7790_CLK_HSCIF1 16
+#define R8A7790_CLK_HSCIF0 17
+#define R8A7790_CLK_SCIF1 20
+#define R8A7790_CLK_SCIF0 21
+#define R8A7790_CLK_DU2 22
+#define R8A7790_CLK_DU1 23
+#define R8A7790_CLK_DU0 24
+#define R8A7790_CLK_LVDS1 25
+#define R8A7790_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7790_CLK_MLB 2
+#define R8A7790_CLK_VIN3 8
+#define R8A7790_CLK_VIN2 9
+#define R8A7790_CLK_VIN1 10
+#define R8A7790_CLK_VIN0 11
+#define R8A7790_CLK_ETHERAVB 12
+#define R8A7790_CLK_ETHER 13
+#define R8A7790_CLK_SATA1 14
+#define R8A7790_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5 7
+#define R8A7790_CLK_GPIO4 8
+#define R8A7790_CLK_GPIO3 9
+#define R8A7790_CLK_GPIO2 10
+#define R8A7790_CLK_GPIO1 11
+#define R8A7790_CLK_GPIO0 12
+#define R8A7790_CLK_RCAN1 15
+#define R8A7790_CLK_RCAN0 16
+#define R8A7790_CLK_QSPI_MOD 17
+#define R8A7790_CLK_IICDVFS 26
+#define R8A7790_CLK_I2C3 28
+#define R8A7790_CLK_I2C2 29
+#define R8A7790_CLK_I2C1 30
+#define R8A7790_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL 5
+#define R8A7790_CLK_SSI9 6
+#define R8A7790_CLK_SSI8 7
+#define R8A7790_CLK_SSI7 8
+#define R8A7790_CLK_SSI6 9
+#define R8A7790_CLK_SSI5 10
+#define R8A7790_CLK_SSI4 11
+#define R8A7790_CLK_SSI3 12
+#define R8A7790_CLK_SSI2 13
+#define R8A7790_CLK_SSI1 14
+#define R8A7790_CLK_SSI0 15
+#define R8A7790_CLK_SCU_ALL 17
+#define R8A7790_CLK_SCU_DVC1 18
+#define R8A7790_CLK_SCU_DVC0 19
+#define R8A7790_CLK_SCU_CTU1_MIX1 20
+#define R8A7790_CLK_SCU_CTU0_MIX0 21
+#define R8A7790_CLK_SCU_SRC9 22
+#define R8A7790_CLK_SCU_SRC8 23
+#define R8A7790_CLK_SCU_SRC7 24
+#define R8A7790_CLK_SCU_SRC6 25
+#define R8A7790_CLK_SCU_SRC5 26
+#define R8A7790_CLK_SCU_SRC4 27
+#define R8A7790_CLK_SCU_SRC3 28
+#define R8A7790_CLK_SCU_SRC2 29
+#define R8A7790_CLK_SCU_SRC1 30
+#define R8A7790_CLK_SCU_SRC0 31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z 0
+#define R8A7790_CLK_Z2 1
+#define R8A7790_CLK_ZG 2
+#define R8A7790_CLK_ZTR 3
+#define R8A7790_CLK_ZTRD2 4
+#define R8A7790_CLK_ZT 5
+#define R8A7790_CLK_ZX 6
+#define R8A7790_CLK_ZS 7
+#define R8A7790_CLK_HP 8
+#define R8A7790_CLK_I 9
+#define R8A7790_CLK_B 10
+#define R8A7790_CLK_LB 11
+#define R8A7790_CLK_P 12
+#define R8A7790_CLK_CL 13
+#define R8A7790_CLK_M2 14
+#define R8A7790_CLK_ADSP 15
+#define R8A7790_CLK_IMP 16
+#define R8A7790_CLK_ZB3 17
+#define R8A7790_CLK_ZB3D2 18
+#define R8A7790_CLK_DDR 19
+#define R8A7790_CLK_SDH 20
+#define R8A7790_CLK_SD0 21
+#define R8A7790_CLK_SD1 22
+#define R8A7790_CLK_SD2 23
+#define R8A7790_CLK_SD3 24
+#define R8A7790_CLK_MMC0 25
+#define R8A7790_CLK_MMC1 26
+#define R8A7790_CLK_MP 27
+#define R8A7790_CLK_SSP 28
+#define R8A7790_CLK_SSPRS 29
+#define R8A7790_CLK_QSPI 30
+#define R8A7790_CLK_CP 31
+#define R8A7790_CLK_RCAN 32
+#define R8A7790_CLK_R 33
+#define R8A7790_CLK_OSC 34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_H__
+
+/* CPG */
+#define R8A7791_CLK_MAIN 0
+#define R8A7791_CLK_PLL0 1
+#define R8A7791_CLK_PLL1 2
+#define R8A7791_CLK_PLL3 3
+#define R8A7791_CLK_LB 4
+#define R8A7791_CLK_QSPI 5
+#define R8A7791_CLK_SDH 6
+#define R8A7791_CLK_SD0 7
+#define R8A7791_CLK_Z 8
+#define R8A7791_CLK_RCAN 9
+#define R8A7791_CLK_ADSP 10
+
+/* MSTP0 */
+#define R8A7791_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7791_CLK_VCP0 1
+#define R8A7791_CLK_VPC0 3
+#define R8A7791_CLK_JPU 6
+#define R8A7791_CLK_SSP1 9
+#define R8A7791_CLK_TMU1 11
+#define R8A7791_CLK_3DG 12
+#define R8A7791_CLK_2DDMAC 15
+#define R8A7791_CLK_FDP1_1 18
+#define R8A7791_CLK_FDP1_0 19
+#define R8A7791_CLK_TMU3 21
+#define R8A7791_CLK_TMU2 22
+#define R8A7791_CLK_CMT0 24
+#define R8A7791_CLK_TMU0 25
+#define R8A7791_CLK_VSP1_DU1 27
+#define R8A7791_CLK_VSP1_DU0 28
+#define R8A7791_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7791_CLK_SCIFA2 2
+#define R8A7791_CLK_SCIFA1 3
+#define R8A7791_CLK_SCIFA0 4
+#define R8A7791_CLK_MSIOF2 5
+#define R8A7791_CLK_SCIFB0 6
+#define R8A7791_CLK_SCIFB1 7
+#define R8A7791_CLK_MSIOF1 8
+#define R8A7791_CLK_SCIFB2 16
+#define R8A7791_CLK_SYS_DMAC1 18
+#define R8A7791_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7791_CLK_TPU0 4
+#define R8A7791_CLK_SDHI2 11
+#define R8A7791_CLK_SDHI1 12
+#define R8A7791_CLK_SDHI0 14
+#define R8A7791_CLK_MMCIF0 15
+#define R8A7791_CLK_IIC0 18
+#define R8A7791_CLK_PCIEC 19
+#define R8A7791_CLK_IIC1 23
+#define R8A7791_CLK_SSUSB 28
+#define R8A7791_CLK_CMT1 29
+#define R8A7791_CLK_USBDMAC0 30
+#define R8A7791_CLK_USBDMAC1 31
+
+/* MSTP4 */
+#define R8A7791_CLK_IRQC 7
+#define R8A7791_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7791_CLK_AUDIO_DMAC1 1
+#define R8A7791_CLK_AUDIO_DMAC0 2
+#define R8A7791_CLK_ADSP_MOD 6
+#define R8A7791_CLK_THERMAL 22
+#define R8A7791_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7791_CLK_EHCI 3
+#define R8A7791_CLK_HSUSB 4
+#define R8A7791_CLK_HSCIF2 13
+#define R8A7791_CLK_SCIF5 14
+#define R8A7791_CLK_SCIF4 15
+#define R8A7791_CLK_HSCIF1 16
+#define R8A7791_CLK_HSCIF0 17
+#define R8A7791_CLK_SCIF3 18
+#define R8A7791_CLK_SCIF2 19
+#define R8A7791_CLK_SCIF1 20
+#define R8A7791_CLK_SCIF0 21
+#define R8A7791_CLK_DU1 23
+#define R8A7791_CLK_DU0 24
+#define R8A7791_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7791_CLK_IPMMU_SGX 0
+#define R8A7791_CLK_MLB 2
+#define R8A7791_CLK_VIN2 9
+#define R8A7791_CLK_VIN1 10
+#define R8A7791_CLK_VIN0 11
+#define R8A7791_CLK_ETHERAVB 12
+#define R8A7791_CLK_ETHER 13
+#define R8A7791_CLK_SATA1 14
+#define R8A7791_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7791_CLK_GYROADC 1
+#define R8A7791_CLK_GPIO7 4
+#define R8A7791_CLK_GPIO6 5
+#define R8A7791_CLK_GPIO5 7
+#define R8A7791_CLK_GPIO4 8
+#define R8A7791_CLK_GPIO3 9
+#define R8A7791_CLK_GPIO2 10
+#define R8A7791_CLK_GPIO1 11
+#define R8A7791_CLK_GPIO0 12
+#define R8A7791_CLK_RCAN1 15
+#define R8A7791_CLK_RCAN0 16
+#define R8A7791_CLK_QSPI_MOD 17
+#define R8A7791_CLK_I2C5 25
+#define R8A7791_CLK_IICDVFS 26
+#define R8A7791_CLK_I2C4 27
+#define R8A7791_CLK_I2C3 28
+#define R8A7791_CLK_I2C2 29
+#define R8A7791_CLK_I2C1 30
+#define R8A7791_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL 5
+#define R8A7791_CLK_SSI9 6
+#define R8A7791_CLK_SSI8 7
+#define R8A7791_CLK_SSI7 8
+#define R8A7791_CLK_SSI6 9
+#define R8A7791_CLK_SSI5 10
+#define R8A7791_CLK_SSI4 11
+#define R8A7791_CLK_SSI3 12
+#define R8A7791_CLK_SSI2 13
+#define R8A7791_CLK_SSI1 14
+#define R8A7791_CLK_SSI0 15
+#define R8A7791_CLK_SCU_ALL 17
+#define R8A7791_CLK_SCU_DVC1 18
+#define R8A7791_CLK_SCU_DVC0 19
+#define R8A7791_CLK_SCU_CTU1_MIX1 20
+#define R8A7791_CLK_SCU_CTU0_MIX0 21
+#define R8A7791_CLK_SCU_SRC9 22
+#define R8A7791_CLK_SCU_SRC8 23
+#define R8A7791_CLK_SCU_SRC7 24
+#define R8A7791_CLK_SCU_SRC6 25
+#define R8A7791_CLK_SCU_SRC5 26
+#define R8A7791_CLK_SCU_SRC4 27
+#define R8A7791_CLK_SCU_SRC3 28
+#define R8A7791_CLK_SCU_SRC2 29
+#define R8A7791_CLK_SCU_SRC1 30
+#define R8A7791_CLK_SCU_SRC0 31
+
+/* MSTP11 */
+#define R8A7791_CLK_SCIFA3 6
+#define R8A7791_CLK_SCIFA4 7
+#define R8A7791_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7791 CPG Core Clocks */
+#define R8A7791_CLK_Z 0
+#define R8A7791_CLK_ZG 1
+#define R8A7791_CLK_ZTR 2
+#define R8A7791_CLK_ZTRD2 3
+#define R8A7791_CLK_ZT 4
+#define R8A7791_CLK_ZX 5
+#define R8A7791_CLK_ZS 6
+#define R8A7791_CLK_HP 7
+#define R8A7791_CLK_I 8
+#define R8A7791_CLK_B 9
+#define R8A7791_CLK_LB 10
+#define R8A7791_CLK_P 11
+#define R8A7791_CLK_CL 12
+#define R8A7791_CLK_M2 13
+#define R8A7791_CLK_ADSP 14
+#define R8A7791_CLK_ZB3 15
+#define R8A7791_CLK_ZB3D2 16
+#define R8A7791_CLK_DDR 17
+#define R8A7791_CLK_SDH 18
+#define R8A7791_CLK_SD0 19
+#define R8A7791_CLK_SD2 20
+#define R8A7791_CLK_SD3 21
+#define R8A7791_CLK_MMC0 22
+#define R8A7791_CLK_MP 23
+#define R8A7791_CLK_SSP 24
+#define R8A7791_CLK_SSPRS 25
+#define R8A7791_CLK_QSPI 26
+#define R8A7791_CLK_CP 27
+#define R8A7791_CLK_RCAN 28
+#define R8A7791_CLK_R 29
+#define R8A7791_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_H__
+
+/* CPG */
+#define R8A7792_CLK_MAIN 0
+#define R8A7792_CLK_PLL0 1
+#define R8A7792_CLK_PLL1 2
+#define R8A7792_CLK_PLL3 3
+#define R8A7792_CLK_LB 4
+#define R8A7792_CLK_QSPI 5
+
+/* MSTP0 */
+#define R8A7792_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7792_CLK_JPU 6
+#define R8A7792_CLK_TMU1 11
+#define R8A7792_CLK_TMU3 21
+#define R8A7792_CLK_TMU2 22
+#define R8A7792_CLK_CMT0 24
+#define R8A7792_CLK_TMU0 25
+#define R8A7792_CLK_VSP1DU1 27
+#define R8A7792_CLK_VSP1DU0 28
+#define R8A7792_CLK_VSP1_SY 31
+
+/* MSTP2 */
+#define R8A7792_CLK_MSIOF1 8
+#define R8A7792_CLK_SYS_DMAC1 18
+#define R8A7792_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7792_CLK_TPU0 4
+#define R8A7792_CLK_SDHI0 14
+#define R8A7792_CLK_CMT1 29
+
+/* MSTP4 */
+#define R8A7792_CLK_IRQC 7
+#define R8A7792_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7792_CLK_AUDIO_DMAC0 2
+#define R8A7792_CLK_THERMAL 22
+#define R8A7792_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7792_CLK_HSCIF1 16
+#define R8A7792_CLK_HSCIF0 17
+#define R8A7792_CLK_SCIF3 18
+#define R8A7792_CLK_SCIF2 19
+#define R8A7792_CLK_SCIF1 20
+#define R8A7792_CLK_SCIF0 21
+#define R8A7792_CLK_DU1 23
+#define R8A7792_CLK_DU0 24
+
+/* MSTP8 */
+#define R8A7792_CLK_VIN5 4
+#define R8A7792_CLK_VIN4 5
+#define R8A7792_CLK_VIN3 8
+#define R8A7792_CLK_VIN2 9
+#define R8A7792_CLK_VIN1 10
+#define R8A7792_CLK_VIN0 11
+#define R8A7792_CLK_ETHERAVB 12
+
+/* MSTP9 */
+#define R8A7792_CLK_GPIO7 4
+#define R8A7792_CLK_GPIO6 5
+#define R8A7792_CLK_GPIO5 7
+#define R8A7792_CLK_GPIO4 8
+#define R8A7792_CLK_GPIO3 9
+#define R8A7792_CLK_GPIO2 10
+#define R8A7792_CLK_GPIO1 11
+#define R8A7792_CLK_GPIO0 12
+#define R8A7792_CLK_GPIO11 13
+#define R8A7792_CLK_GPIO10 14
+#define R8A7792_CLK_CAN1 15
+#define R8A7792_CLK_CAN0 16
+#define R8A7792_CLK_QSPI_MOD 17
+#define R8A7792_CLK_GPIO9 19
+#define R8A7792_CLK_GPIO8 21
+#define R8A7792_CLK_I2C5 25
+#define R8A7792_CLK_IICDVFS 26
+#define R8A7792_CLK_I2C4 27
+#define R8A7792_CLK_I2C3 28
+#define R8A7792_CLK_I2C2 29
+#define R8A7792_CLK_I2C1 30
+#define R8A7792_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7792_CLK_SSI_ALL 5
+#define R8A7792_CLK_SSI4 11
+#define R8A7792_CLK_SSI3 12
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7792 CPG Core Clocks */
+#define R8A7792_CLK_Z 0
+#define R8A7792_CLK_ZG 1
+#define R8A7792_CLK_ZTR 2
+#define R8A7792_CLK_ZTRD2 3
+#define R8A7792_CLK_ZT 4
+#define R8A7792_CLK_ZX 5
+#define R8A7792_CLK_ZS 6
+#define R8A7792_CLK_HP 7
+#define R8A7792_CLK_I 8
+#define R8A7792_CLK_B 9
+#define R8A7792_CLK_LB 10
+#define R8A7792_CLK_P 11
+#define R8A7792_CLK_CL 12
+#define R8A7792_CLK_M2 13
+#define R8A7792_CLK_IMP 14
+#define R8A7792_CLK_ZB3 15
+#define R8A7792_CLK_ZB3D2 16
+#define R8A7792_CLK_DDR 17
+#define R8A7792_CLK_SD 18
+#define R8A7792_CLK_MP 19
+#define R8A7792_CLK_QSPI 20
+#define R8A7792_CLK_CP 21
+#define R8A7792_CLK_CPEX 22
+#define R8A7792_CLK_RCAN 23
+#define R8A7792_CLK_R 24
+#define R8A7792_CLK_OSC 25
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * r8a7793 clock definition
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_H__
+
+/* CPG */
+#define R8A7793_CLK_MAIN 0
+#define R8A7793_CLK_PLL0 1
+#define R8A7793_CLK_PLL1 2
+#define R8A7793_CLK_PLL3 3
+#define R8A7793_CLK_LB 4
+#define R8A7793_CLK_QSPI 5
+#define R8A7793_CLK_SDH 6
+#define R8A7793_CLK_SD0 7
+#define R8A7793_CLK_Z 8
+#define R8A7793_CLK_RCAN 9
+#define R8A7793_CLK_ADSP 10
+
+/* MSTP0 */
+#define R8A7793_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7793_CLK_VCP0 1
+#define R8A7793_CLK_VPC0 3
+#define R8A7793_CLK_SSP1 9
+#define R8A7793_CLK_TMU1 11
+#define R8A7793_CLK_3DG 12
+#define R8A7793_CLK_2DDMAC 15
+#define R8A7793_CLK_FDP1_1 18
+#define R8A7793_CLK_FDP1_0 19
+#define R8A7793_CLK_TMU3 21
+#define R8A7793_CLK_TMU2 22
+#define R8A7793_CLK_CMT0 24
+#define R8A7793_CLK_TMU0 25
+#define R8A7793_CLK_VSP1_DU1 27
+#define R8A7793_CLK_VSP1_DU0 28
+#define R8A7793_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7793_CLK_SCIFA2 2
+#define R8A7793_CLK_SCIFA1 3
+#define R8A7793_CLK_SCIFA0 4
+#define R8A7793_CLK_MSIOF2 5
+#define R8A7793_CLK_SCIFB0 6
+#define R8A7793_CLK_SCIFB1 7
+#define R8A7793_CLK_MSIOF1 8
+#define R8A7793_CLK_SCIFB2 16
+#define R8A7793_CLK_SYS_DMAC1 18
+#define R8A7793_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7793_CLK_TPU0 4
+#define R8A7793_CLK_SDHI2 11
+#define R8A7793_CLK_SDHI1 12
+#define R8A7793_CLK_SDHI0 14
+#define R8A7793_CLK_MMCIF0 15
+#define R8A7793_CLK_IIC0 18
+#define R8A7793_CLK_PCIEC 19
+#define R8A7793_CLK_IIC1 23
+#define R8A7793_CLK_SSUSB 28
+#define R8A7793_CLK_CMT1 29
+#define R8A7793_CLK_USBDMAC0 30
+#define R8A7793_CLK_USBDMAC1 31
+
+/* MSTP4 */
+#define R8A7793_CLK_IRQC 7
+#define R8A7793_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7793_CLK_AUDIO_DMAC1 1
+#define R8A7793_CLK_AUDIO_DMAC0 2
+#define R8A7793_CLK_ADSP_MOD 6
+#define R8A7793_CLK_THERMAL 22
+#define R8A7793_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7793_CLK_EHCI 3
+#define R8A7793_CLK_HSUSB 4
+#define R8A7793_CLK_HSCIF2 13
+#define R8A7793_CLK_SCIF5 14
+#define R8A7793_CLK_SCIF4 15
+#define R8A7793_CLK_HSCIF1 16
+#define R8A7793_CLK_HSCIF0 17
+#define R8A7793_CLK_SCIF3 18
+#define R8A7793_CLK_SCIF2 19
+#define R8A7793_CLK_SCIF1 20
+#define R8A7793_CLK_SCIF0 21
+#define R8A7793_CLK_DU1 23
+#define R8A7793_CLK_DU0 24
+#define R8A7793_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7793_CLK_IPMMU_SGX 0
+#define R8A7793_CLK_VIN2 9
+#define R8A7793_CLK_VIN1 10
+#define R8A7793_CLK_VIN0 11
+#define R8A7793_CLK_ETHER 13
+#define R8A7793_CLK_SATA1 14
+#define R8A7793_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7793_CLK_GPIO7 4
+#define R8A7793_CLK_GPIO6 5
+#define R8A7793_CLK_GPIO5 7
+#define R8A7793_CLK_GPIO4 8
+#define R8A7793_CLK_GPIO3 9
+#define R8A7793_CLK_GPIO2 10
+#define R8A7793_CLK_GPIO1 11
+#define R8A7793_CLK_GPIO0 12
+#define R8A7793_CLK_RCAN1 15
+#define R8A7793_CLK_RCAN0 16
+#define R8A7793_CLK_QSPI_MOD 17
+#define R8A7793_CLK_I2C5 25
+#define R8A7793_CLK_IICDVFS 26
+#define R8A7793_CLK_I2C4 27
+#define R8A7793_CLK_I2C3 28
+#define R8A7793_CLK_I2C2 29
+#define R8A7793_CLK_I2C1 30
+#define R8A7793_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7793_CLK_SSI_ALL 5
+#define R8A7793_CLK_SSI9 6
+#define R8A7793_CLK_SSI8 7
+#define R8A7793_CLK_SSI7 8
+#define R8A7793_CLK_SSI6 9
+#define R8A7793_CLK_SSI5 10
+#define R8A7793_CLK_SSI4 11
+#define R8A7793_CLK_SSI3 12
+#define R8A7793_CLK_SSI2 13
+#define R8A7793_CLK_SSI1 14
+#define R8A7793_CLK_SSI0 15
+#define R8A7793_CLK_SCU_ALL 17
+#define R8A7793_CLK_SCU_DVC1 18
+#define R8A7793_CLK_SCU_DVC0 19
+#define R8A7793_CLK_SCU_CTU1_MIX1 20
+#define R8A7793_CLK_SCU_CTU0_MIX0 21
+#define R8A7793_CLK_SCU_SRC9 22
+#define R8A7793_CLK_SCU_SRC8 23
+#define R8A7793_CLK_SCU_SRC7 24
+#define R8A7793_CLK_SCU_SRC6 25
+#define R8A7793_CLK_SCU_SRC5 26
+#define R8A7793_CLK_SCU_SRC4 27
+#define R8A7793_CLK_SCU_SRC3 28
+#define R8A7793_CLK_SCU_SRC2 29
+#define R8A7793_CLK_SCU_SRC1 30
+#define R8A7793_CLK_SCU_SRC0 31
+
+/* MSTP11 */
+#define R8A7793_CLK_SCIFA3 6
+#define R8A7793_CLK_SCIFA4 7
+#define R8A7793_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7793 CPG Core Clocks */
+#define R8A7793_CLK_Z 0
+#define R8A7793_CLK_ZG 1
+#define R8A7793_CLK_ZTR 2
+#define R8A7793_CLK_ZTRD2 3
+#define R8A7793_CLK_ZT 4
+#define R8A7793_CLK_ZX 5
+#define R8A7793_CLK_ZS 6
+#define R8A7793_CLK_HP 7
+#define R8A7793_CLK_I 8
+#define R8A7793_CLK_B 9
+#define R8A7793_CLK_LB 10
+#define R8A7793_CLK_P 11
+#define R8A7793_CLK_CL 12
+#define R8A7793_CLK_M2 13
+#define R8A7793_CLK_ADSP 14
+#define R8A7793_CLK_ZB3 15
+#define R8A7793_CLK_ZB3D2 16
+#define R8A7793_CLK_DDR 17
+#define R8A7793_CLK_SDH 18
+#define R8A7793_CLK_SD0 19
+#define R8A7793_CLK_SD2 20
+#define R8A7793_CLK_SD3 21
+#define R8A7793_CLK_MMC0 22
+#define R8A7793_CLK_MP 23
+#define R8A7793_CLK_SSP 24
+#define R8A7793_CLK_SSPRS 25
+#define R8A7793_CLK_QSPI 26
+#define R8A7793_CLK_CP 27
+#define R8A7793_CLK_RCAN 28
+#define R8A7793_CLK_R 29
+#define R8A7793_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN 0
+#define R8A7794_CLK_PLL0 1
+#define R8A7794_CLK_PLL1 2
+#define R8A7794_CLK_PLL3 3
+#define R8A7794_CLK_LB 4
+#define R8A7794_CLK_QSPI 5
+#define R8A7794_CLK_SDH 6
+#define R8A7794_CLK_SD0 7
+#define R8A7794_CLK_RCAN 8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7794_CLK_VCP0 1
+#define R8A7794_CLK_VPC0 3
+#define R8A7794_CLK_TMU1 11
+#define R8A7794_CLK_3DG 12
+#define R8A7794_CLK_2DDMAC 15
+#define R8A7794_CLK_FDP1_0 19
+#define R8A7794_CLK_TMU3 21
+#define R8A7794_CLK_TMU2 22
+#define R8A7794_CLK_CMT0 24
+#define R8A7794_CLK_TMU0 25
+#define R8A7794_CLK_VSP1_DU0 28
+#define R8A7794_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2 2
+#define R8A7794_CLK_SCIFA1 3
+#define R8A7794_CLK_SCIFA0 4
+#define R8A7794_CLK_MSIOF2 5
+#define R8A7794_CLK_SCIFB0 6
+#define R8A7794_CLK_SCIFB1 7
+#define R8A7794_CLK_MSIOF1 8
+#define R8A7794_CLK_SCIFB2 16
+#define R8A7794_CLK_SYS_DMAC1 18
+#define R8A7794_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7794_CLK_SDHI2 11
+#define R8A7794_CLK_SDHI1 12
+#define R8A7794_CLK_SDHI0 14
+#define R8A7794_CLK_MMCIF0 15
+#define R8A7794_CLK_IIC0 18
+#define R8A7794_CLK_IIC1 23
+#define R8A7794_CLK_CMT1 29
+#define R8A7794_CLK_USBDMAC0 30
+#define R8A7794_CLK_USBDMAC1 31
+
+/* MSTP4 */
+#define R8A7794_CLK_IRQC 7
+#define R8A7794_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7794_CLK_AUDIO_DMAC0 2
+#define R8A7794_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7794_CLK_EHCI 3
+#define R8A7794_CLK_HSUSB 4
+#define R8A7794_CLK_HSCIF2 13
+#define R8A7794_CLK_SCIF5 14
+#define R8A7794_CLK_SCIF4 15
+#define R8A7794_CLK_HSCIF1 16
+#define R8A7794_CLK_HSCIF0 17
+#define R8A7794_CLK_SCIF3 18
+#define R8A7794_CLK_SCIF2 19
+#define R8A7794_CLK_SCIF1 20
+#define R8A7794_CLK_SCIF0 21
+#define R8A7794_CLK_DU1 23
+#define R8A7794_CLK_DU0 24
+
+/* MSTP8 */
+#define R8A7794_CLK_VIN1 10
+#define R8A7794_CLK_VIN0 11
+#define R8A7794_CLK_ETHERAVB 12
+#define R8A7794_CLK_ETHER 13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6 5
+#define R8A7794_CLK_GPIO5 7
+#define R8A7794_CLK_GPIO4 8
+#define R8A7794_CLK_GPIO3 9
+#define R8A7794_CLK_GPIO2 10
+#define R8A7794_CLK_GPIO1 11
+#define R8A7794_CLK_GPIO0 12
+#define R8A7794_CLK_RCAN1 15
+#define R8A7794_CLK_RCAN0 16
+#define R8A7794_CLK_QSPI_MOD 17
+#define R8A7794_CLK_I2C5 25
+#define R8A7794_CLK_I2C4 27
+#define R8A7794_CLK_I2C3 28
+#define R8A7794_CLK_I2C2 29
+#define R8A7794_CLK_I2C1 30
+#define R8A7794_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7794_CLK_SSI_ALL 5
+#define R8A7794_CLK_SSI9 6
+#define R8A7794_CLK_SSI8 7
+#define R8A7794_CLK_SSI7 8
+#define R8A7794_CLK_SSI6 9
+#define R8A7794_CLK_SSI5 10
+#define R8A7794_CLK_SSI4 11
+#define R8A7794_CLK_SSI3 12
+#define R8A7794_CLK_SSI2 13
+#define R8A7794_CLK_SSI1 14
+#define R8A7794_CLK_SSI0 15
+#define R8A7794_CLK_SCU_ALL 17
+#define R8A7794_CLK_SCU_DVC1 18
+#define R8A7794_CLK_SCU_DVC0 19
+#define R8A7794_CLK_SCU_CTU1_MIX1 20
+#define R8A7794_CLK_SCU_CTU0_MIX0 21
+#define R8A7794_CLK_SCU_SRC6 25
+#define R8A7794_CLK_SCU_SRC5 26
+#define R8A7794_CLK_SCU_SRC4 27
+#define R8A7794_CLK_SCU_SRC3 28
+#define R8A7794_CLK_SCU_SRC2 29
+#define R8A7794_CLK_SCU_SRC1 30
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3 6
+#define R8A7794_CLK_SCIFA4 7
+#define R8A7794_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7794 CPG Core Clocks */
+#define R8A7794_CLK_Z2 0
+#define R8A7794_CLK_ZG 1
+#define R8A7794_CLK_ZTR 2
+#define R8A7794_CLK_ZTRD2 3
+#define R8A7794_CLK_ZT 4
+#define R8A7794_CLK_ZX 5
+#define R8A7794_CLK_ZS 6
+#define R8A7794_CLK_HP 7
+#define R8A7794_CLK_I 8
+#define R8A7794_CLK_B 9
+#define R8A7794_CLK_LB 10
+#define R8A7794_CLK_P 11
+#define R8A7794_CLK_CL 12
+#define R8A7794_CLK_CP 13
+#define R8A7794_CLK_M2 14
+#define R8A7794_CLK_ADSP 15
+#define R8A7794_CLK_ZB3 16
+#define R8A7794_CLK_ZB3D2 17
+#define R8A7794_CLK_DDR 18
+#define R8A7794_CLK_SDH 19
+#define R8A7794_CLK_SD0 20
+#define R8A7794_CLK_SD2 21
+#define R8A7794_CLK_SD3 22
+#define R8A7794_CLK_MMC0 23
+#define R8A7794_CLK_MP 24
+#define R8A7794_CLK_QSPI 25
+#define R8A7794_CLK_CPEX 26
+#define R8A7794_CLK_RCAN 27
+#define R8A7794_CLK_R 28
+#define R8A7794_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
+#define SCLK_MAC_PLL 150
#define SCLK_MAC 151
#define SCLK_MACREF_OUT 152
#define SCLK_USB3OTG_SUSPEND 97
#define SCLK_REF_USB3OTG_SRC 98
#define SCLK_MAC2IO_SRC 99
+#define SCLK_MAC2IO 100
+#define SCLK_MAC2PHY 101
+#define SCLK_MAC2IO_EXT 102
/* dclk gates */
#define DCLK_LCDC 180
#define CLK_NR_CLKS (HCLK_HDCP + 1)
-#define SCLK_MAC2IO 0
-#define SCLK_MAC2PHY 1
-
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
#define CLK_SYS_UART_REF 18
#define CLK_SYS_EBI_REF 19
#define CLK_TUN_PLL 20
-#define CLK_TUN 21
-#define CLK_HDMI_PLL 22
-#define CLK_HDMI 23
+#define CLK_TUN_TUN 21
+#define CLK_TUN_ROM 22
+#define CLK_TUN_PWM 23
+#define CLK_HDMI_PLL 24
+#define CLK_HDMI 25
#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
--- /dev/null
+/*
+ * This header provides constants for pca9532 LED bindings.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _DT_BINDINGS_LEDS_PCA9532_H
+#define _DT_BINDINGS_LEDS_PCA9532_H
+
+#define PCA9532_TYPE_NONE 0
+#define PCA9532_TYPE_LED 1
+#define PCA9532_TYPE_N2100_BEEP 2
+#define PCA9532_TYPE_GPIO 3
+#define PCA9532_LED_TIMER2 4
+
+#endif /* _DT_BINDINGS_LEDS_PCA9532_H */
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
+
+#define BCM6318_PWR_PCIE 0
+#define BCM6318_PWR_USB 1
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */
--- /dev/null
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7790_PD_CA15_CPU0 0
+#define R8A7790_PD_CA15_CPU1 1
+#define R8A7790_PD_CA15_CPU2 2
+#define R8A7790_PD_CA15_CPU3 3
+#define R8A7790_PD_CA7_CPU0 5
+#define R8A7790_PD_CA7_CPU1 6
+#define R8A7790_PD_CA7_CPU2 7
+#define R8A7790_PD_CA7_CPU3 8
+#define R8A7790_PD_CA15_SCU 12
+#define R8A7790_PD_SH_4A 16
+#define R8A7790_PD_RGX 20
+#define R8A7790_PD_CA7_SCU 21
+#define R8A7790_PD_IMP 24
+
+/* Always-on power area */
+#define R8A7790_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7791_PD_CA15_CPU0 0
+#define R8A7791_PD_CA15_CPU1 1
+#define R8A7791_PD_CA15_SCU 12
+#define R8A7791_PD_SH_4A 16
+#define R8A7791_PD_SGX 20
+
+/* Always-on power area */
+#define R8A7791_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7792_PD_CA15_CPU0 0
+#define R8A7792_PD_CA15_CPU1 1
+#define R8A7792_PD_CA15_SCU 12
+#define R8A7792_PD_SGX 20
+#define R8A7792_PD_IMP 24
+
+/* Always-on power area */
+#define R8A7792_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ *
+ * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
+ */
+
+#define R8A7793_PD_CA15_CPU0 0
+#define R8A7793_PD_CA15_CPU1 1
+#define R8A7793_PD_CA15_SCU 12
+#define R8A7793_PD_SH_4A 16
+#define R8A7793_PD_SGX 20
+
+/* Always-on power area */
+#define R8A7793_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7794_PD_CA7_CPU0 5
+#define R8A7794_PD_CA7_CPU1 6
+#define R8A7794_PD_SH_4A 16
+#define R8A7794_PD_SGX 20
+#define R8A7794_PD_CA7_SCU 21
+
+/* Always-on power area */
+#define R8A7794_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6318_H
+#define __DT_BINDINGS_RESET_BCM6318_H
+
+#define BCM6318_RST_SPI 0
+#define BCM6318_RST_EPHY 1
+#define BCM6318_RST_SAR 2
+#define BCM6318_RST_ENETSW 3
+#define BCM6318_RST_USBD 4
+#define BCM6318_RST_USBH 5
+#define BCM6318_RST_PCIE_CORE 6
+#define BCM6318_RST_PCIE 7
+#define BCM6318_RST_PCIE_EXT 8
+#define BCM6318_RST_PCIE_HARD 9
+#define BCM6318_RST_ADSL 10
+#define BCM6318_RST_PHYMIPS 11
+#define BCM6318_RST_HOSTMIPS 11
+
+#endif /* __DT_BINDINGS_RESET_BCM6318_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6368_H
+#define __DT_BINDINGS_RESET_BCM6368_H
+
+#define BCM6368_RST_SPI 0
+#define BCM6368_RST_MPI 3
+#define BCM6368_RST_IPSEC 4
+#define BCM6368_RST_EPHY 6
+#define BCM6368_RST_SAR 7
+#define BCM6368_RST_SWITCH 10
+#define BCM6368_RST_USBD 11
+#define BCM6368_RST_USBH 12
+#define BCM6368_RST_PCM 13
+
+#endif /* __DT_BINDINGS_RESET_BCM6368_H */
#include <linux/string.h>
#include <linux/types.h>
-#ifdef CONFIG_EFI_STUB_64BIT
+#if CONFIG_EFI_STUB_64BIT || (!defined(CONFIG_EFI_STUB) && defined(__x86_64__))
/* EFI uses the Microsoft ABI which is not the default for GCC */
#define EFIAPI __attribute__((ms_abi))
#else
efi_status_t (EFIAPI *reinstall_protocol_interface)(
void *handle, const efi_guid_t *protocol,
void *old_interface, void *new_interface);
- efi_status_t (EFIAPI *uninstall_protocol_interface)(void *handle,
- const efi_guid_t *protocol, void *protocol_interface);
- efi_status_t (EFIAPI *handle_protocol)(efi_handle_t,
- const efi_guid_t *protocol,
- void **protocol_interface);
+ efi_status_t (EFIAPI *uninstall_protocol_interface)(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ void *protocol_interface);
+ efi_status_t (EFIAPI *handle_protocol)(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ void **protocol_interface);
void *reserved;
efi_status_t (EFIAPI *register_protocol_notify)(
const efi_guid_t *protocol, struct efi_event *event,
efi_status_t (EFIAPI *exit)(efi_handle_t handle,
efi_status_t exit_status,
unsigned long exitdata_size, s16 *exitdata);
- efi_status_t (EFIAPI *unload_image)(void *image_handle);
+ efi_status_t (EFIAPI *unload_image)(efi_handle_t image_handle);
efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t, unsigned long);
efi_status_t (EFIAPI *get_next_monotonic_count)(u64 *count);
efi_handle_t *driver_image_handle,
struct efi_device_path *remaining_device_path,
bool recursive);
- efi_status_t (EFIAPI *disconnect_controller)(void *controller_handle,
- void *driver_image_handle, void *child_handle);
+ efi_status_t (EFIAPI *disconnect_controller)(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ efi_handle_t child_handle);
#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001
#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002
#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004
const efi_guid_t *protocol, void **interface,
efi_handle_t agent_handle,
efi_handle_t controller_handle, u32 attributes);
- efi_status_t (EFIAPI *close_protocol)(void *handle,
- const efi_guid_t *protocol, void *agent_handle,
- void *controller_handle);
+ efi_status_t (EFIAPI *close_protocol)(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ efi_handle_t agent_handle,
+ efi_handle_t controller_handle);
efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle,
const efi_guid_t *protocol,
struct efi_open_protocol_info_entry **entry_buffer,
struct efi_table_hdr hdr;
unsigned long fw_vendor; /* physical addr of wchar_t vendor string */
u32 fw_revision;
- unsigned long con_in_handle;
+ efi_handle_t con_in_handle;
struct efi_simple_input_interface *con_in;
- unsigned long con_out_handle;
+ efi_handle_t con_out_handle;
struct efi_simple_text_output_protocol *con_out;
- unsigned long stderr_handle;
+ efi_handle_t stderr_handle;
struct efi_simple_text_output_protocol *std_err;
struct efi_runtime_services *runtime;
struct efi_boot_services *boottime;
} __packed;
#define DEVICE_PATH_TYPE_MESSAGING_DEVICE 0x03
+# define DEVICE_PATH_SUB_TYPE_MSG_ATAPI 0x01
+# define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02
# define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05
# define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b
# define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f
# define DEVICE_PATH_SUB_TYPE_MSG_SD 0x1a
# define DEVICE_PATH_SUB_TYPE_MSG_MMC 0x1d
+struct efi_device_path_atapi {
+ struct efi_device_path dp;
+ u8 primary_secondary;
+ u8 slave_master;
+ u16 logical_unit_number;
+} __packed;
+
+struct efi_device_path_scsi {
+ struct efi_device_path dp;
+ u16 target_id;
+ u16 logical_unit_number;
+} __packed;
+
struct efi_device_path_usb {
struct efi_device_path dp;
u8 parent_port_number;
u32 io_align;
u8 pad2[4];
u64 last_block;
+ /* Added in revision 2 of the protocol */
+ u64 lowest_aligned_lba;
+ u32 logical_blocks_per_physical_block;
+ /* Added in revision 3 of the protocol */
+ u32 optimal_transfer_length_granualarity;
};
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001f
+
struct efi_block_io {
u64 revision;
struct efi_block_io_media *media;
efi_status_t (EFIAPI *reset)(struct efi_block_io *this,
char extended_verification);
efi_status_t (EFIAPI *read_blocks)(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer);
efi_status_t (EFIAPI *write_blocks)(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer);
efi_status_t (EFIAPI *flush_blocks)(struct efi_block_io *this);
};
s16 file_name[0];
};
+#define EFI_DRIVER_BINDING_PROTOCOL_GUID \
+ EFI_GUID(0x18a031ab, 0xb443, 0x4d1a,\
+ 0xa5, 0xc0, 0x0c, 0x09, 0x26, 0x1e, 0x9f, 0x71)
+struct efi_driver_binding_protocol {
+ efi_status_t (EFIAPI * supported)(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path);
+ efi_status_t (EFIAPI * start)(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path);
+ efi_status_t (EFIAPI * stop)(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ efi_uintn_t number_of_children,
+ efi_handle_t *child_handle_buffer);
+ u32 version;
+ efi_handle_t image_handle;
+ efi_handle_t driver_binding_handle;
+};
+
#endif
--- /dev/null
+/*
+ * EFI application loader
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EFI_DRIVER_H
+#define _EFI_DRIVER_H 1
+
+#include <common.h>
+#include <dm.h>
+#include <efi_loader.h>
+
+struct efi_driver_ops {
+ const efi_guid_t *protocol;
+ const efi_guid_t *child_protocol;
+ int (*bind)(efi_handle_t handle, void *interface);
+};
+
+/*
+ * This structure adds internal fields to the driver binding protocol.
+ */
+struct efi_driver_binding_extended_protocol {
+ struct efi_driver_binding_protocol bp;
+ const struct efi_driver_ops *ops;
+};
+
+#endif /* _EFI_DRIVER_H */
} while(0)
/*
- * Write GUID
+ * Write an indented message with EFI prefix
*/
-#define EFI_PRINT_GUID(txt, guid) ({ \
- debug("%sEFI: %s %pUl\n", __efi_nesting(), txt, guid); \
+#define EFI_PRINT(format, ...) ({ \
+ debug("%sEFI: " format, __efi_nesting(), \
+ ##__VA_ARGS__); \
})
extern struct efi_runtime_services efi_runtime_services;
uint16_t *efi_dp_str(struct efi_device_path *dp);
+/* GUID of the EFI_BLOCK_IO_PROTOCOL */
+extern const efi_guid_t efi_block_io_guid;
extern const efi_guid_t efi_global_variable_guid;
extern const efi_guid_t efi_guid_console_control;
extern const efi_guid_t efi_guid_device_path;
+/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
+extern const efi_guid_t efi_guid_driver_binding_protocol;
extern const efi_guid_t efi_guid_loaded_image;
extern const efi_guid_t efi_guid_device_path_to_text_protocol;
extern const efi_guid_t efi_simple_file_system_protocol_guid;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
/*
+ * When a protocol is opened a open protocol info entry is created.
+ * These are maintained in a list.
+ */
+struct efi_open_protocol_info_item {
+ /* Link to the list of open protocol info entries of a protocol */
+ struct list_head link;
+ struct efi_open_protocol_info_entry info;
+};
+
+/*
* When the UEFI payload wants to open a protocol on an object to get its
* interface (usually a struct with callback functions), this struct maps the
- * protocol GUID to the respective protocol interface */
+ * protocol GUID to the respective protocol interface
+ */
struct efi_handler {
/* Link to the list of protocols of a handle */
struct list_head link;
const efi_guid_t *guid;
void *protocol_interface;
+ /* Link to the list of open protocol info items */
+ struct list_head open_infos;
};
/*
int efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
int efi_disk_register(void);
+/* Create handles and protocols for the partitions of a block device */
+int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
+ const char *if_typename, int diskid,
+ const char *pdevname);
/* Called by bootefi to make GOP (graphical) interface available */
int efi_gop_register(void);
/* Called by bootefi to make the network interface available */
/* Add a new object to the object list. */
void efi_add_handle(struct efi_object *obj);
/* Create handle */
-efi_status_t efi_create_handle(void **handle);
+efi_status_t efi_create_handle(efi_handle_t *handle);
/* Delete handle */
void efi_delete_handle(struct efi_object *obj);
/* Call this to validate a handle and find the EFI object for it */
-struct efi_object *efi_search_obj(const void *handle);
+struct efi_object *efi_search_obj(const efi_handle_t handle);
/* Find a protocol on a handle */
-efi_status_t efi_search_protocol(const void *handle,
+efi_status_t efi_search_protocol(const efi_handle_t handle,
const efi_guid_t *protocol_guid,
struct efi_handler **handler);
/* Install new protocol on a handle */
-efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_add_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface);
/* Delete protocol from a handle */
-efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_remove_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface);
/* Delete all protocols from a handle */
-efi_status_t efi_remove_all_protocols(const void *handle);
+efi_status_t efi_remove_all_protocols(const efi_handle_t handle);
/* Call this to create an event */
efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
void (EFIAPI *notify_function) (
efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
uint64_t trigger_time);
/* Call this to signal an event */
-void efi_signal_event(struct efi_event *event);
+void efi_signal_event(struct efi_event *event, bool check_tpl);
/* open file system: */
struct efi_simple_file_system_protocol *efi_simple_file_system(
/* Adds a range into the EFI memory map */
uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
bool overlap_only_ram);
+/* Called by board init to initialize the EFI drivers */
+int efi_driver_init(void);
/* Called by board init to initialize the EFI memory map */
int efi_memory_init(void);
/* Adds new or overrides configuration table entry to the system table */
struct efi_device_path *efi_dp_from_dev(struct udevice *dev);
struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part);
+/* Create a device node for a block device partition. */
+struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part);
struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part,
const char *path);
struct efi_device_path *efi_dp_from_eth(void);
struct efi_device_path *efi_dp_from_mem(uint32_t mem_type,
uint64_t start_address,
uint64_t end_address);
-void efi_dp_split_file_path(struct efi_device_path *full_path,
- struct efi_device_path **device_path,
- struct efi_device_path **file_path);
+/* Determine the last device path node that is not the end node. */
+const struct efi_device_path *efi_dp_last_node(
+ const struct efi_device_path *dp);
+efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
+ struct efi_device_path **device_path,
+ struct efi_device_path **file_path);
#define EFI_DP_TYPE(_dp, _type, _subtype) \
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
#define EFI_ST_FAILURE 1
/*
+ * Prints a message.
+ */
+#define efi_st_printf(...) \
+ (efi_st_printc(-1, __VA_ARGS__))
+
+/*
* Prints an error message.
*
* @... format string followed by fields to print
*/
#define efi_st_error(...) \
- (efi_st_printf("%s(%u):\nERROR: ", __FILE__, __LINE__), \
- efi_st_printf(__VA_ARGS__)) \
+ (efi_st_printc(EFI_LIGHTRED, "%s(%u):\nERROR: ", __FILE__, __LINE__), \
+ efi_st_printc(EFI_LIGHTRED, __VA_ARGS__))
/*
* Prints a TODO message.
* @... format string followed by fields to print
*/
#define efi_st_todo(...) \
- (efi_st_printf("%s(%u):\nTODO: ", __FILE__, __LINE__), \
- efi_st_printf(__VA_ARGS__)) \
+ (efi_st_printc(EFI_YELLOW, "%s(%u):\nTODO: ", __FILE__, __LINE__), \
+ efi_st_printc(EFI_YELLOW, __VA_ARGS__)) \
/*
* A test may be setup and executed at boottime,
void efi_st_exit_boot_services(void);
/*
- * Print a pointer to an u16 string
+ * Print a colored message
*
- * @pointer: pointer
- * @buf: pointer to buffer address
- * on return position of terminating zero word
+ * @color color, see constants in efi_api.h, use -1 for no color
+ * @fmt printf format
+ * @... arguments to be printed
+ * on return position of terminating zero word
*/
-void efi_st_printf(const char *fmt, ...)
- __attribute__ ((format (__printf__, 1, 2)));
+void efi_st_printc(int color, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 2, 3)));
/*
* Compare memory.
ENVL_UNKNOWN,
};
+/* value for the various operations we want to perform on the env */
+enum env_operation {
+ ENVOP_GET_CHAR, /* we want to call the get_char function */
+ ENVOP_INIT, /* we want to call the init function */
+ ENVOP_LOAD, /* we want to call the load function */
+ ENVOP_SAVE, /* we want to call the save function */
+};
+
struct env_driver {
const char *name;
enum env_location location;
#endif
/**
- * env_driver_lookup_default() - Look up the default environment driver
- *
- * @return pointer to driver, or NULL if none (which should not happen)
- */
-struct env_driver *env_driver_lookup_default(void);
-
-/**
* env_get_char() - Get a character from the early environment
*
* This reads from the pre-relocation environemnt
"setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = dra71x; then " \
"setenv fdtfile dra71-evm.dtb; fi;" \
- "if test $board_name = dra76x; then " \
+ "if test $board_name = dra76x_acd; then " \
"setenv fdtfile dra76-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
"if test $board_name = am572x_idk; then " \
"setenv fdtfile am572x-idk.dtb; fi;" \
+ "if test $board_name = am574x_idk; then " \
+ "setenv fdtfile am574x-idk.dtb; fi;" \
"if test $board_name = am57xx_evm; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"if test $board_name = am57xx_evm_reva3; then " \
#include <asm/byteorder.h>
#include <fs.h>
-#define CONFIG_SUPPORT_VFAT
/* Maximum Long File Name length supported here is 128 UTF-16 code units */
#define VFAT_MAXLEN_BYTES 256 /* Maximum LFN buffer in bytes */
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
* return codes from flash_write():
*/
#define ERR_OK 0
-#define ERR_TIMOUT 1
+#define ERR_TIMEOUT 1
#define ERR_NOT_ERASED 2
#define ERR_PROTECTED 4
#define ERR_INVAL 8
-#include "../lib/libfdt/libfdt.h"
+#ifndef UBOOT_LIBFDT_H
+#define UBOOT_LIBFDT_H
+/*
+ * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
+ */
+
+#ifdef USE_HOSTCC
+#include "../scripts/dtc/libfdt/libfdt.h"
+#else
+#include <linux/libfdt.h>
+#endif
+
+/* U-Boot local hacks */
+
+#ifndef SWIG /* Not available in Python */
+struct fdt_region {
+ int offset;
+ int size;
+};
+
+/*
+ * Flags for fdt_find_regions()
+ *
+ * Add a region for the string table (always the last region)
+ */
+#define FDT_REG_ADD_STRING_TAB (1 << 0)
+
+/*
+ * Add all supernodes of a matching node/property, useful for creating a
+ * valid subset tree
+ */
+#define FDT_REG_SUPERNODES (1 << 1)
+
+/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */
+#define FDT_REG_DIRECT_SUBNODES (1 << 2)
+
+/* Add all subnodes of a matching node */
+#define FDT_REG_ALL_SUBNODES (1 << 3)
+
+/* Add a region for the mem_rsvmap table (always the first region) */
+#define FDT_REG_ADD_MEM_RSVMAP (1 << 4)
+
+/* Indicates what an fdt part is (node, property, value) */
+#define FDT_IS_NODE (1 << 0)
+#define FDT_IS_PROP (1 << 1)
+#define FDT_IS_VALUE (1 << 2) /* not supported */
+#define FDT_IS_COMPAT (1 << 3) /* used internally */
+#define FDT_NODE_HAS_PROP (1 << 4) /* node contains prop */
+
+#define FDT_ANY_GLOBAL (FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \
+ FDT_IS_COMPAT)
+#define FDT_IS_ANY 0x1f /* all the above */
+
+/* We set a reasonable limit on the number of nested nodes */
+#define FDT_MAX_DEPTH 32
+
+/* Decribes what we want to include from the current tag */
+enum want_t {
+ WANT_NOTHING,
+ WANT_NODES_ONLY, /* No properties */
+ WANT_NODES_AND_PROPS, /* Everything for one level */
+ WANT_ALL_NODES_AND_PROPS /* Everything for all levels */
+};
+
+/* Keeps track of the state at parent nodes */
+struct fdt_subnode_stack {
+ int offset; /* Offset of node */
+ enum want_t want; /* The 'want' value here */
+ int included; /* 1 if we included this node, 0 if not */
+};
+
+struct fdt_region_ptrs {
+ int depth; /* Current tree depth */
+ int done; /* What we have completed scanning */
+ enum want_t want; /* What we are currently including */
+ char *end; /* Pointer to end of full node path */
+ int nextoffset; /* Next node offset to check */
+};
+
+/* The state of our finding algortihm */
+struct fdt_region_state {
+ struct fdt_subnode_stack stack[FDT_MAX_DEPTH]; /* node stack */
+ struct fdt_region *region; /* Contains list of regions found */
+ int count; /* Numnber of regions found */
+ const void *fdt; /* FDT blob */
+ int max_regions; /* Maximum regions to find */
+ int can_merge; /* 1 if we can merge with previous region */
+ int start; /* Start position of current region */
+ struct fdt_region_ptrs ptrs; /* Pointers for what we are up to */
+};
+
+/**
+ * fdt_find_regions() - find regions in device tree
+ *
+ * Given a list of nodes to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ *
+ * Nodes which are given in 'inc' are included in the region list, as
+ * are the names of the immediate subnodes nodes (but not the properties
+ * or subnodes of those subnodes).
+ *
+ * For eaxample "/" means to include the root node, all root properties
+ * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter
+ * ensures that we capture the names of the subnodes. In a hashing situation
+ * it prevents the root node from changing at all Any change to non-excluded
+ * properties, names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too.
+ *
+ * The device tree header is not included in the list.
+ *
+ * @fdt: Device tree to check
+ * @inc: List of node paths to included
+ * @inc_count: Number of node paths in list
+ * @exc_prop: List of properties names to exclude
+ * @exc_prop_count: Number of properties in exclude list
+ * @region: Returns list of regions
+ * @max_region: Maximum length of region list
+ * @path: Pointer to a temporary string for the function to use for
+ * building path names
+ * @path_len: Length of path, must be large enough to hold the longest
+ * path in the tree
+ * @add_string_tab: 1 to add a region for the string table
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again.
+ */
+int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
+ char * const exc_prop[], int exc_prop_count,
+ struct fdt_region region[], int max_regions,
+ char *path, int path_len, int add_string_tab);
+
+/**
+ * fdt_first_region() - find regions in device tree
+ *
+ * Given a nodes and properties to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The use for this function is twofold. Firstly it provides a convenient
+ * way of performing a structure-aware grep of the tree. For example it is
+ * possible to grep for a node and get all the properties associated with
+ * that node. Trees can be subsetted easily, by specifying the nodes that
+ * are required, and then writing out the regions returned by this function.
+ * This is useful for small resource-constrained systems, such as boot
+ * loaders, which want to use an FDT but do not need to know about all of
+ * it.
+ *
+ * Secondly it makes it easy to hash parts of the tree and detect changes.
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ * Note that semantically null changes in order could still cause false
+ * hash misses. Such reordering might happen if the tree is regenerated
+ * from source, and nodes are reordered (the bytes-stream will be emitted
+ * in a different order and many hash functions will detect this). However
+ * if an existing tree is modified using libfdt functions, such as
+ * fdt_add_subnode() and fdt_setprop(), then this problem is avoided.
+ *
+ * The nodes/properties to include/exclude are defined by a function
+ * provided by the caller. This function is called for each node and
+ * property, and must return:
+ *
+ * 0 - to exclude this part
+ * 1 - to include this part
+ * -1 - for FDT_IS_PROP only: no information is available, so include
+ * if its containing node is included
+ *
+ * The last case is only used to deal with properties. Often a property is
+ * included if its containing node is included - this is the case where
+ * -1 is returned.. However if the property is specifically required to be
+ * included/excluded, then 0 or 1 can be returned. Note that including a
+ * property when the FDT_REG_SUPERNODES flag is given will force its
+ * containing node to be included since it is not valid to have a property
+ * that is not in a node.
+ *
+ * Using the information provided, the inclusion of a node can be controlled
+ * either by a node name or its compatible string, or any other property
+ * that the function can determine.
+ *
+ * As an example, including node "/" means to include the root node and all
+ * root properties. A flag provides a way of also including supernodes (of
+ * which there is none for the root node), and another flag includes
+ * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and
+ * FDT_END_NODE of all subnodes of /.
+ *
+ * The subnode feature helps in a hashing situation since it prevents the
+ * root node from changing at all. Any change to non-excluded properties,
+ * names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too. This is always
+ * the last region.
+ *
+ * The FDT also has a mem_rsvmap table which can also be included, and is
+ * always the first region if so.
+ *
+ * The device tree header is not included in the region list. Since the
+ * contents of the FDT are changing (shrinking, often), the caller will need
+ * to regenerate the header anyway.
+ *
+ * @fdt: Device tree to check
+ * @h_include: Function to call to determine whether to include a part or
+ * not:
+ *
+ * @priv: Private pointer as passed to fdt_find_regions()
+ * @fdt: Pointer to FDT blob
+ * @offset: Offset of this node / property
+ * @type: Type of this part, FDT_IS_...
+ * @data: Pointer to data (node name, property name, compatible
+ * string, value (not yet supported)
+ * @size: Size of data, or 0 if none
+ * @return 0 to exclude, 1 to include, -1 if no information is
+ * available
+ * @priv: Private pointer passed to h_include
+ * @region: Returns list of regions, sorted by offset
+ * @max_regions: Maximum length of region list
+ * @path: Pointer to a temporary string for the function to use for
+ * building path names
+ * @path_len: Length of path, must be large enough to hold the longest
+ * path in the tree
+ * @flags: Various flags that control the region algortihm, see
+ * FDT_REG_...
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again. Only the first max_regions elements are available in the
+ * array.
+ *
+ * On error a -ve value is return, which can be:
+ *
+ * -FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags
+ * -FDT_ERR_BADLAYOUT
+ * -FDT_ERR_NOSPACE (path area is too small)
+ */
+int fdt_first_region(const void *fdt,
+ int (*h_include)(void *priv, const void *fdt, int offset,
+ int type, const char *data, int size),
+ void *priv, struct fdt_region *region,
+ char *path, int path_len, int flags,
+ struct fdt_region_state *info);
+
+/** fdt_next_region() - find next region
+ *
+ * See fdt_first_region() for full description. This function finds the
+ * next region according to the provided parameters, which must be the same
+ * as passed to fdt_first_region().
+ *
+ * This function can additionally return -FDT_ERR_NOTFOUND when there are no
+ * more regions
+ */
+int fdt_next_region(const void *fdt,
+ int (*h_include)(void *priv, const void *fdt, int offset,
+ int type, const char *data, int size),
+ void *priv, struct fdt_region *region,
+ char *path, int path_len, int flags,
+ struct fdt_region_state *info);
+
+/**
+ * fdt_add_alias_regions() - find aliases that point to existing regions
+ *
+ * Once a device tree grep is complete some of the nodes will be present
+ * and some will have been dropped. This function checks all the alias nodes
+ * to figure out which points point to nodes which are still present. These
+ * aliases need to be kept, along with the nodes they reference.
+ *
+ * Given a list of regions function finds the aliases that still apply and
+ * adds more regions to the list for these. This function is called after
+ * fdt_next_region() has finished returning regions and requires the same
+ * state.
+ *
+ * @fdt: Device tree file to reference
+ * @region: List of regions that will be kept
+ * @count: Number of regions
+ * @max_regions: Number of entries that can fit in @region
+ * @info: Region state as returned from fdt_next_region()
+ * @return new number of regions in @region (i.e. count + the number added)
+ * or -FDT_ERR_NOSPACE if there was not enough space.
+ */
+int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
+ int max_regions, struct fdt_region_state *info);
+#endif /* SWIG */
+
+extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
+
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD 0x80
+
+#endif /* UBOOT_LIBFDT_H */
-/*
- * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
- * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
- * Original version written by David Gibson, IBM Corporation.
- *
- * SPDX-License-Identifier: LGPL-2.1+
- */
-
-#ifndef _LIBFDT_ENV_H
-#define _LIBFDT_ENV_H
-
-#include "compiler.h"
-#include "linux/types.h"
-
-extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
-
-typedef __be16 fdt16_t;
-typedef __be32 fdt32_t;
-typedef __be64 fdt64_t;
-
-#define fdt32_to_cpu(x) be32_to_cpu(x)
-#define cpu_to_fdt32(x) cpu_to_be32(x)
-#define fdt64_to_cpu(x) be64_to_cpu(x)
-#define cpu_to_fdt64(x) cpu_to_be64(x)
-
-/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
-#define FDT_RAMDISK_OVERHEAD 0x80
-
-#endif /* _LIBFDT_ENV_H */
+#ifdef USE_HOSTCC
+#include "../scripts/dtc/libfdt/libfdt_env.h"
+#else
+#include <linux/libfdt_env.h>
+#endif
-#ifndef _LIBFDT_ENV_H
-#define _LIBFDT_ENV_H
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _INCLUDE_LIBFDT_H_
+#define _INCLUDE_LIBFDT_H_
-#include <linux/string.h>
+#include <linux/libfdt_env.h>
+#include "../../scripts/dtc/libfdt/libfdt.h"
-#include <asm/byteorder.h>
-
-typedef __be16 fdt16_t;
-typedef __be32 fdt32_t;
-typedef __be64 fdt64_t;
-
-#define fdt32_to_cpu(x) be32_to_cpu(x)
-#define cpu_to_fdt32(x) cpu_to_be32(x)
-#define fdt64_to_cpu(x) be64_to_cpu(x)
-#define cpu_to_fdt64(x) cpu_to_be64(x)
-
-#endif /* _LIBFDT_ENV_H */
+#endif /* _INCLUDE_LIBFDT_H_ */
ulong or;
} pcmcia_win_t;
-/*
- * Definitions for PCMCIA control registers to operate in IDE mode
- *
- * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
- * to be done later (depending on CPU clock)
- */
-
-/* Window 0:
- * Base: 0xFE100000 CS1
- * Port Size: 2 Bytes
- * Port Size: 16 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
-#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
- | PCMCIA_PPS_16 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 1:
- * Base: 0xFE100080 CS1
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
-#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 2:
- * Base: 0xFE100100 CS2
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
-#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 3:
- * not used
- */
-#define CONFIG_SYS_PCMCIA_PBR3 0
-#define CONFIG_SYS_PCMCIA_POR3 0
-
-/* Window 4:
- * Base: 0xFE100C00 CS1
- * Port Size: 2 Bytes
- * Port Size: 16 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
-#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
- | PCMCIA_PPS_16 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 5:
- * Base: 0xFE100C80 CS1
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
-#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 6:
- * Base: 0xFE100D00 CS2
- * Port Size: 8 Bytes
- * Port Size: 8 Bit
- * Common Memory Space
- */
-
-#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
-#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
- | PCMCIA_PPS_8 \
- | PCMCIA_PRS_MEM \
- | PCMCIA_SLOT_x \
- | PCMCIA_PV \
- )
-
-/* Window 7:
- * not used
- */
-#define CONFIG_SYS_PCMCIA_PBR7 0
-#define CONFIG_SYS_PCMCIA_POR7 0
-
/**********************************************************************/
/*
#define S2MPS11_LDO26_ENABLE 0xec
+#define S2MPS11_LDO_NUM 26
+#define S2MPS11_BUCK_NUM 10
+
+/* Driver name */
+#define S2MPS11_BUCK_DRIVER "s2mps11_buck"
+#define S2MPS11_OF_BUCK_PREFIX "BUCK"
+#define S2MPS11_LDO_DRIVER "s2mps11_ldo"
+#define S2MPS11_OF_LDO_PREFIX "LDO"
+
+/* BUCK */
+#define S2MPS11_BUCK_VOLT_MASK 0xff
+#define S2MPS11_BUCK9_VOLT_MASK 0x1f
+
+#define S2MPS11_BUCK_LSTEP 6250
+#define S2MPS11_BUCK_HSTEP 12500
+#define S2MPS11_BUCK9_STEP 25000
+
+#define S2MPS11_BUCK_UV_MIN 600000
+#define S2MPS11_BUCK_UV_HMIN 750000
+#define S2MPS11_BUCK9_UV_MIN 1400000
+
+#define S2MPS11_BUCK_VOLT_MAX_HEX 0xA0
+#define S2MPS11_BUCK5_VOLT_MAX_HEX 0xDF
+#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX 0xDC
+#define S2MPS11_BUCK9_VOLT_MAX_HEX 0x5F
+
+#define S2MPS11_BUCK_MODE_SHIFT 6
+#define S2MPS11_BUCK_MODE_MASK (0x3)
+#define S2MPS11_BUCK_MODE_OFF (0x0 << 6)
+#define S2MPS11_BUCK_MODE_STANDBY (0x1 << 6)
+#define S2MPS11_BUCK_MODE_ON (0x3 << 6)
+
+/* LDO */
+#define S2MPS11_LDO_VOLT_MASK 0x3F
+#define S2MPS11_LDO_VOLT_MAX_HEX 0x3F
+
+#define S2MPS11_LDO_STEP 25000
+#define S2MPS11_LDO_UV_MIN 800000
+
+#define S2MPS11_LDO_MODE_MASK 0x3
+#define S2MPS11_LDO_MODE_SHIFT 6
+
+#define S2MPS11_LDO_MODE_OFF (0x0 << 6)
+#define S2MPS11_LDO_MODE_STANDBY (0x1 << 6)
+#define S2MPS11_LDO_MODE_STANDBY_LPM (0x2 << 6)
+#define S2MPS11_LDO_MODE_ON (0x3 << 6)
+
+enum {
+ OP_OFF = 0,
+ OP_LPM,
+ OP_STANDBY,
+ OP_STANDBY_LPM,
+ OP_ON,
+};
+
#endif
* @cs: ID of the chip select connected to the slave.
* @mode: SPI mode to use for this slave (see SPI mode flags)
* @wordlen: Size of SPI word in number of bits
+ * @max_read_size: If non-zero, the maximum number of bytes which can
+ * be read at once.
* @max_write_size: If non-zero, the maximum number of bytes which can
- * be written at once, excluding command bytes.
+ * be written at once.
* @memory_map: Address of read-only SPI flash access.
* @flags: Indication of SPI flags.
*/
#endif
uint mode;
unsigned int wordlen;
+ unsigned int max_read_size;
unsigned int max_write_size;
void *memory_map;
return ret < 0 ? ret : din[1];
}
-/**
- * Set up a SPI slave for a particular device tree node
- *
- * This calls spi_setup_slave() with the correct bus number. Call
- * spi_free_slave() to free it later.
- *
- * @param blob: Device tree blob
- * @param slave_node: Slave node to use
- * @param spi_node: SPI peripheral node to use
- * @return pointer to new spi_slave structure
- */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
- int spi_node);
-
-/**
- * spi_base_setup_slave_fdt() - helper function to set up a SPI slace
- *
- * This decodes SPI properties from the slave node to determine the
- * chip select and SPI parameters.
- *
- * @blob: Device tree blob
- * @busnum: Bus number to use
- * @node: Device tree node for the SPI bus
- */
-struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
- int node);
-
#ifdef CONFIG_DM_SPI
/**
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
-/**
- * Set up a new SPI flash from an fdt node
- *
- * @param blob Device tree blob
- * @param slave_node Pointer to this SPI slave node in the device tree
- * @param spi_node Cached pointer to the SPI interface this node belongs
- * to
- * @return 0 if ok, -1 on error
- */
-struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
- int spi_node);
-
void spi_flash_free(struct spi_flash *flash);
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
* aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC.
*
* @key_exp Expanded key to use
+ * @iv Initialization vector
* @src Source data to encrypt
* @dst Destination buffer
* @num_aes_blocks Number of AES blocks to encrypt
*/
-void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks);
/**
* Decrypt multiple blocks of data with AES CBC.
*
* @key_exp Expanded key to use
+ * @iv Initialization vector
* @src Source data to decrypt
* @dst Destination buffer
* @num_aes_blocks Number of AES blocks to decrypt
*/
-void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks);
#endif /* _AES_REF_H_ */
#include <asm/io.h>
/**
- * wait_for_bit() waits for bit set/cleared in register
+ * wait_for_bit_x() waits for bit set/cleared in register
*
* Function polls register waiting for specific bit(s) change
* (either 0->1 or 1->0). It can fail under two conditions:
* Function succeeds only if all bits of masked register are set/cleared
* (depending on set option).
*
- * @param prefix Prefix added to timeout messagge (message visible only
- * with debug enabled)
- * @param reg Register that will be read (using readl())
+ * @param reg Register that will be read (using read_x())
* @param mask Bit(s) of register that must be active
* @param set Selects wait condition (bit set or clear)
- * @param timeout_ms Timeout (in miliseconds)
+ * @param timeout_ms Timeout (in milliseconds)
* @param breakable Enables CTRL-C interruption
* @return 0 on success, -ETIMEDOUT or -EINTR on failure
*/
-static inline int wait_for_bit(const char *prefix, const u32 *reg,
- const u32 mask, const bool set,
- const unsigned int timeout_ms,
- const bool breakable)
-{
- u32 val;
- unsigned long start = get_timer(0);
- while (1) {
- val = readl(reg);
-
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- if (get_timer(start) > timeout_ms)
- break;
-
- if (breakable && ctrlc()) {
- puts("Abort\n");
- return -EINTR;
- }
-
- udelay(1);
- WATCHDOG_RESET();
- }
-
- debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
- set);
-
- return -ETIMEDOUT;
+#define BUILD_WAIT_FOR_BIT(sfx, type, read) \
+ \
+static inline int wait_for_bit_##sfx(const void *reg, \
+ const type mask, \
+ const bool set, \
+ const unsigned int timeout_ms, \
+ const bool breakable) \
+{ \
+ type val; \
+ unsigned long start = get_timer(0); \
+ \
+ while (1) { \
+ val = read(reg); \
+ \
+ if (!set) \
+ val = ~val; \
+ \
+ if ((val & mask) == mask) \
+ return 0; \
+ \
+ if (get_timer(start) > timeout_ms) \
+ break; \
+ \
+ if (breakable && ctrlc()) { \
+ puts("Abort\n"); \
+ return -EINTR; \
+ } \
+ \
+ udelay(1); \
+ WATCHDOG_RESET(); \
+ } \
+ \
+ debug("%s: Timeout (reg=%p mask=%x wait_set=%i)\n", __func__, \
+ reg, mask, set); \
+ \
+ return -ETIMEDOUT; \
}
+BUILD_WAIT_FOR_BIT(8, u8, readb)
+BUILD_WAIT_FOR_BIT(le16, u16, readw)
+#ifdef readw_be
+BUILD_WAIT_FOR_BIT(be16, u16, readw_be)
+#endif
+BUILD_WAIT_FOR_BIT(le32, u32, readl)
+#ifdef readl_be
+BUILD_WAIT_FOR_BIT(be32, u32, readl_be)
+#endif
#endif
config REGEX
bool "Enable regular expression support"
+ default n if ARCH_SUNXI
default y if NET
help
If this variable is defined, U-Boot is linked against the
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_EFI) += efi/
+obj-$(CONFIG_EFI_LOADER) += efi_driver/
obj-$(CONFIG_EFI_LOADER) += efi_loader/
obj-$(CONFIG_EFI_LOADER) += efi_selftest/
obj-$(CONFIG_LZMA) += lzma/
*dst++ = *src++ ^ *cbc_chain_data++;
}
-void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks)
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
{
- u8 zero_key[AES_KEY_LENGTH] = { 0 };
u8 tmp_data[AES_KEY_LENGTH];
- /* Convenient array of 0's for IV */
- u8 *cbc_chain_data = zero_key;
+ u8 *cbc_chain_data = iv;
u32 i;
for (i = 0; i < num_aes_blocks; i++) {
}
}
-void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks)
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
{
u8 tmp_data[AES_KEY_LENGTH], tmp_block[AES_KEY_LENGTH];
/* Convenient array of 0's for IV */
- u8 cbc_chain_data[AES_KEY_LENGTH] = { 0 };
+ u8 cbc_chain_data[AES_KEY_LENGTH];
u32 i;
+ memcpy(cbc_chain_data, iv, AES_KEY_LENGTH);
for (i = 0; i < num_aes_blocks; i++) {
debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
debug_print_vector("AES Src", AES_KEY_LENGTH, src);
--- /dev/null
+#
+# (C) Copyright 2017 Heinrich Schuchardt
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# This file only gets included with CONFIG_EFI_LOADER set, so all
+# object inclusion implicitly depends on it
+
+obj-y += efi_uclass.o
+ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
+obj-y += efi_block_device.o
+endif
--- /dev/null
+/*
+ * EFI block driver
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The EFI uclass creates a handle for this driver and installs the
+ * driver binding protocol on it.
+ *
+ * The EFI block driver binds to controllers implementing the block io
+ * protocol.
+ *
+ * When the bind function of the EFI block driver is called it creates a
+ * new U-Boot block device. It installs child handles for all partitions and
+ * installs the simple file protocol on these.
+ *
+ * The read and write functions of the EFI block driver delegate calls to the
+ * controller that it is bound to.
+ *
+ * A usage example is as following:
+ *
+ * U-Boot loads the iPXE snp.efi executable. iPXE connects an iSCSI drive and
+ * exposes a handle with the block IO protocol. It calls ConnectController.
+ *
+ * Now the EFI block driver installs the partitions with the simple file
+ * protocol.
+ *
+ * iPXE uses the simple file protocol to load Grub or the Linux Kernel.
+ */
+
+#include <efi_driver.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+
+/*
+ * EFI attributes of the udevice handled by this driver.
+ *
+ * handle handle of the controller on which this driver is installed
+ * io block io protocol proxied by this driver
+ */
+struct efi_blk_priv {
+ efi_handle_t handle;
+ struct efi_block_io *io;
+};
+
+/*
+ * Read from block device
+ *
+ * @dev device
+ * @blknr first block to be read
+ * @blkcnt number of blocks to read
+ * @buffer output buffer
+ * @return number of blocks transferred
+ */
+static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ struct efi_blk_priv *priv = dev->priv;
+ struct efi_block_io *io = priv->io;
+ efi_status_t ret;
+
+ EFI_PRINT("%s: read '%s', from block " LBAFU ", " LBAFU " blocks\n",
+ __func__, dev->name, blknr, blkcnt);
+ ret = EFI_CALL(io->read_blocks(
+ io, io->media->media_id, (u64)blknr,
+ (efi_uintn_t)blkcnt *
+ (efi_uintn_t)io->media->block_size, buffer));
+ EFI_PRINT("%s: r = %u\n", __func__,
+ (unsigned int)(ret & ~EFI_ERROR_MASK));
+ if (ret != EFI_SUCCESS)
+ return 0;
+ return blkcnt;
+}
+
+/*
+ * Write to block device
+ *
+ * @dev device
+ * @blknr first block to be write
+ * @blkcnt number of blocks to write
+ * @buffer input buffer
+ * @return number of blocks transferred
+ */
+static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ struct efi_blk_priv *priv = dev->priv;
+ struct efi_block_io *io = priv->io;
+ efi_status_t ret;
+
+ EFI_PRINT("%s: write '%s', from block " LBAFU ", " LBAFU " blocks\n",
+ __func__, dev->name, blknr, blkcnt);
+ ret = EFI_CALL(io->write_blocks(
+ io, io->media->media_id, (u64)blknr,
+ (efi_uintn_t)blkcnt *
+ (efi_uintn_t)io->media->block_size,
+ (void *)buffer));
+ EFI_PRINT("%s: r = %u\n", __func__,
+ (unsigned int)(ret & ~EFI_ERROR_MASK));
+ if (ret != EFI_SUCCESS)
+ return 0;
+ return blkcnt;
+}
+
+/*
+ * Create partions for the block device.
+ *
+ * @handle EFI handle of the block device
+ * @dev udevice of the block device
+ */
+static int efi_bl_bind_partitions(efi_handle_t handle, struct udevice *dev)
+{
+ struct blk_desc *desc;
+ const char *if_typename;
+
+ desc = dev_get_uclass_platdata(dev);
+ if_typename = blk_get_if_type_name(desc->if_type);
+
+ return efi_disk_create_partitions(handle, desc, if_typename,
+ desc->devnum, dev->name);
+}
+
+/*
+ * Create a block device for a handle
+ *
+ * @handle handle
+ * @interface block io protocol
+ * @return 0 = success
+ */
+static int efi_bl_bind(efi_handle_t handle, void *interface)
+{
+ struct udevice *bdev, *parent = dm_root();
+ int ret, devnum;
+ char *name;
+ struct efi_object *obj = efi_search_obj(handle);
+ struct efi_block_io *io = interface;
+ int disks;
+ struct efi_blk_priv *priv;
+
+ EFI_PRINT("%s: handle %p, interface %p\n", __func__, handle, io);
+
+ if (!obj)
+ return -ENOENT;
+
+ devnum = blk_find_max_devnum(IF_TYPE_EFI);
+ if (devnum == -ENODEV)
+ devnum = 0;
+ else if (devnum < 0)
+ return devnum;
+
+ name = calloc(1, 18); /* strlen("efiblk#2147483648") + 1 */
+ if (!name)
+ return -ENOMEM;
+ sprintf(name, "efiblk#%d", devnum);
+
+ /* Create driver model udevice for the EFI block io device */
+ ret = blk_create_device(parent, "efi_blk", name, IF_TYPE_EFI, devnum,
+ io->media->block_size,
+ (lbaint_t)io->media->last_block, &bdev);
+ if (ret)
+ return ret;
+ if (!bdev)
+ return -ENOENT;
+ /* Allocate priv */
+ ret = device_probe(bdev);
+ if (ret)
+ return ret;
+ EFI_PRINT("%s: block device '%s' created\n", __func__, bdev->name);
+
+ priv = bdev->priv;
+ priv->handle = handle;
+ priv->io = interface;
+
+ ret = blk_prepare_device(bdev);
+
+ /* Create handles for the partions of the block device */
+ disks = efi_bl_bind_partitions(handle, bdev);
+ EFI_PRINT("Found %d partitions\n", disks);
+
+ return 0;
+}
+
+/* Block device driver operators */
+static const struct blk_ops efi_blk_ops = {
+ .read = efi_bl_read,
+ .write = efi_bl_write,
+};
+
+/* Identify as block device driver */
+U_BOOT_DRIVER(efi_blk) = {
+ .name = "efi_blk",
+ .id = UCLASS_BLK,
+ .ops = &efi_blk_ops,
+ .priv_auto_alloc_size = sizeof(struct efi_blk_priv),
+};
+
+/* EFI driver operators */
+static const struct efi_driver_ops driver_ops = {
+ .protocol = &efi_block_io_guid,
+ .child_protocol = &efi_block_io_guid,
+ .bind = efi_bl_bind,
+};
+
+/* Identify as EFI driver */
+U_BOOT_DRIVER(efi_block) = {
+ .name = "EFI block driver",
+ .id = UCLASS_EFI,
+ .ops = &driver_ops,
+};
--- /dev/null
+/*
+ * Uclass for EFI drivers
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For each EFI driver the uclass
+ * - creates a handle
+ * - installs the driver binding protocol
+ *
+ * The uclass provides the bind, start, and stop entry points for the driver
+ * binding protocol.
+ *
+ * In bind() and stop() it checks if the controller implements the protocol
+ * supported by the EFI driver. In the start() function it calls the bind()
+ * function of the EFI driver. In the stop() function it destroys the child
+ * controllers.
+ */
+
+#include <efi_driver.h>
+
+/*
+ * Check node type. We do not support partitions as controller handles.
+ *
+ * @handle handle to be checked
+ * @return status code
+ */
+static efi_status_t check_node_type(efi_handle_t handle)
+{
+ efi_status_t r, ret = EFI_SUCCESS;
+ const struct efi_device_path *dp;
+
+ /* Open the device path protocol */
+ r = EFI_CALL(systab.boottime->open_protocol(
+ handle, &efi_guid_device_path, (void **)&dp,
+ NULL, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (r == EFI_SUCCESS && dp) {
+ /* Get the last node */
+ const struct efi_device_path *node = efi_dp_last_node(dp);
+ /* We do not support partitions as controller */
+ if (!node || node->type == DEVICE_PATH_TYPE_MEDIA_DEVICE)
+ ret = EFI_UNSUPPORTED;
+ }
+ return ret;
+}
+
+/*
+ * Check if the driver supports the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_uc_supported(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ efi_status_t r, ret;
+ void *interface;
+ struct efi_driver_binding_extended_protocol *bp =
+ (struct efi_driver_binding_extended_protocol *)this;
+
+ EFI_ENTRY("%p, %p, %ls", this, controller_handle,
+ efi_dp_str(remaining_device_path));
+
+ ret = EFI_CALL(systab.boottime->open_protocol(
+ controller_handle, bp->ops->protocol,
+ &interface, this->driver_binding_handle,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER));
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ goto out;
+ case EFI_SUCCESS:
+ break;
+ default:
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ ret = check_node_type(controller_handle);
+
+ r = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, bp->ops->protocol,
+ this->driver_binding_handle,
+ controller_handle));
+ if (r != EFI_SUCCESS)
+ ret = EFI_UNSUPPORTED;
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * Create child controllers and attach driver.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_uc_start(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ efi_status_t r, ret;
+ void *interface = NULL;
+ struct efi_driver_binding_extended_protocol *bp =
+ (struct efi_driver_binding_extended_protocol *)this;
+
+ EFI_ENTRY("%p, %pUl, %ls", this, controller_handle,
+ efi_dp_str(remaining_device_path));
+
+ /* Attach driver to controller */
+ ret = EFI_CALL(systab.boottime->open_protocol(
+ controller_handle, bp->ops->protocol,
+ &interface, this->driver_binding_handle,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER));
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ goto out;
+ case EFI_SUCCESS:
+ break;
+ default:
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+ ret = check_node_type(controller_handle);
+ if (ret != EFI_SUCCESS) {
+ r = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, bp->ops->protocol,
+ this->driver_binding_handle,
+ controller_handle));
+ if (r != EFI_SUCCESS)
+ EFI_PRINT("Failure to close handle\n");
+ goto out;
+ }
+
+ /* TODO: driver specific stuff */
+ bp->ops->bind(controller_handle, interface);
+
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * Remove a single child controller from the parent controller.
+ *
+ * @controller_handle parent controller
+ * @child_handle child controller
+ * @return status code
+ */
+static efi_status_t disconnect_child(efi_handle_t controller_handle,
+ efi_handle_t child_handle)
+{
+ efi_status_t ret;
+ efi_guid_t *guid_controller = NULL;
+ efi_guid_t *guid_child_controller = NULL;
+
+ ret = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, guid_controller,
+ child_handle, child_handle));
+ if (ret != EFI_SUCCESS) {
+ EFI_PRINT("Cannot close protocol\n");
+ return ret;
+ }
+ ret = EFI_CALL(systab.boottime->uninstall_protocol_interface(
+ child_handle, guid_child_controller, NULL));
+ if (ret != EFI_SUCCESS) {
+ EFI_PRINT("Cannot uninstall protocol interface\n");
+ return ret;
+ }
+ return ret;
+}
+
+/*
+ * Remove child controllers and disconnect the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @number_of_children number of child controllers to remove
+ * @child_handle_buffer handles of the child controllers to remove
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_uc_stop(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ size_t number_of_children,
+ efi_handle_t *child_handle_buffer)
+{
+ efi_status_t ret;
+ efi_uintn_t count;
+ struct efi_open_protocol_info_entry *entry_buffer;
+ efi_guid_t *guid_controller = NULL;
+
+ EFI_ENTRY("%p, %pUl, %zu, %p", this, controller_handle,
+ number_of_children, child_handle_buffer);
+
+ /* Destroy provided child controllers */
+ if (number_of_children) {
+ efi_uintn_t i;
+
+ for (i = 0; i < number_of_children; ++i) {
+ ret = disconnect_child(controller_handle,
+ child_handle_buffer[i]);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ return EFI_SUCCESS;
+ }
+
+ /* Destroy all children */
+ ret = EFI_CALL(systab.boottime->open_protocol_information(
+ controller_handle, guid_controller,
+ &entry_buffer, &count));
+ if (ret != EFI_SUCCESS)
+ goto out;
+ while (count) {
+ if (entry_buffer[--count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ ret = disconnect_child(
+ controller_handle,
+ entry_buffer[count].agent_handle);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+ }
+ ret = EFI_CALL(systab.boottime->free_pool(entry_buffer));
+ if (ret != EFI_SUCCESS)
+ printf("%s(%u) %s: ERROR: Cannot free pool\n",
+ __FILE__, __LINE__, __func__);
+
+ /* Detach driver from controller */
+ ret = EFI_CALL(systab.boottime->close_protocol(
+ controller_handle, guid_controller,
+ this->driver_binding_handle, controller_handle));
+out:
+ return EFI_EXIT(ret);
+}
+
+static efi_status_t efi_add_driver(struct driver *drv)
+{
+ efi_status_t ret;
+ const struct efi_driver_ops *ops = drv->ops;
+ struct efi_driver_binding_extended_protocol *bp;
+
+ debug("EFI: Adding driver '%s'\n", drv->name);
+ if (!ops->protocol) {
+ printf("EFI: ERROR: protocol GUID missing for driver '%s'\n",
+ drv->name);
+ return EFI_INVALID_PARAMETER;
+ }
+ bp = calloc(1, sizeof(struct efi_driver_binding_extended_protocol));
+ if (!bp)
+ return EFI_OUT_OF_RESOURCES;
+
+ bp->bp.supported = efi_uc_supported;
+ bp->bp.start = efi_uc_start;
+ bp->bp.stop = efi_uc_stop;
+ bp->bp.version = 0xffffffff;
+ bp->ops = drv->ops;
+
+ ret = efi_create_handle(&bp->bp.driver_binding_handle);
+ if (ret != EFI_SUCCESS) {
+ free(bp);
+ goto out;
+ }
+ bp->bp.image_handle = bp->bp.driver_binding_handle;
+ ret = efi_add_protocol(bp->bp.driver_binding_handle,
+ &efi_guid_driver_binding_protocol, bp);
+ if (ret != EFI_SUCCESS) {
+ efi_delete_handle(bp->bp.driver_binding_handle);
+ free(bp);
+ goto out;
+ }
+out:
+ return ret;
+}
+
+/*
+ * Initialize the EFI drivers.
+ * Called by board_init_r().
+ *
+ * @return 0 = success, any other value will stop further execution
+ */
+int efi_driver_init(void)
+{
+ struct driver *drv;
+ int ret = 0;
+
+ /* Save 'gd' pointer */
+ efi_save_gd();
+
+ debug("EFI: Initializing EFI driver framework\n");
+ for (drv = ll_entry_start(struct driver, driver);
+ drv < ll_entry_end(struct driver, driver); ++drv) {
+ if (drv->id == UCLASS_EFI) {
+ ret = efi_add_driver(drv);
+ if (ret) {
+ printf("EFI: ERROR: failed to add driver %s\n",
+ drv->name);
+ break;
+ }
+ }
+ }
+ return ret;
+}
+
+static int efi_uc_init(struct uclass *class)
+{
+ printf("EFI: Initializing UCLASS_EFI\n");
+ return 0;
+}
+
+static int efi_uc_destroy(struct uclass *class)
+{
+ printf("Destroying UCLASS_EFI\n");
+ return 0;
+}
+
+UCLASS_DRIVER(efi) = {
+ .name = "efi",
+ .id = UCLASS_EFI,
+ .init = efi_uc_init,
+ .destroy = efi_uc_destroy,
+};
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
depends on (ARM || X86) && OF_LIBFDT
+ # We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
+ depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
+ # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
+ depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
default y
help
Select this option if you want to run EFI applications (like grub2)
if (lo.attributes & LOAD_OPTION_ACTIVE) {
efi_status_t ret;
- u16 *str = NULL;
- debug("%s: trying to load \"%ls\" from: %ls\n", __func__,
- lo.label, (str = efi_dp_str(lo.file_path)));
- efi_free_pool(str);
+ debug("%s: trying to load \"%ls\" from %pD\n",
+ __func__, lo.label, lo.file_path);
ret = efi_load_image_from_path(lo.file_path, &image);
static int entry_count;
static int nesting_level;
+/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
+const efi_guid_t efi_guid_driver_binding_protocol =
+ EFI_DRIVER_BINDING_PROTOCOL_GUID;
+
+static efi_status_t EFIAPI efi_disconnect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ efi_handle_t child_handle);
/* Called on every callback entry */
int __efi_entry_check(void)
}
/*
- * Two spaces per indent level, maxing out at 10.. which ought to be
- * enough for anyone ;-)
+ * Return a string for indenting with two spaces per level. A maximum of ten
+ * indent levels is supported. Higher indent levels will be truncated.
+ *
+ * @level indent level
+ * @return indent string
*/
static const char *indent_string(int level)
{
* For the SignalEvent service see efi_signal_event_ext.
*
* @event event to signal
+ * @check_tpl check the TPL level
*/
-void efi_signal_event(struct efi_event *event)
+void efi_signal_event(struct efi_event *event, bool check_tpl)
{
if (event->notify_function) {
event->is_queued = true;
/* Check TPL */
- if (efi_tpl >= event->notify_tpl)
+ if (check_tpl && efi_tpl >= event->notify_tpl)
return;
EFI_CALL_VOID(event->notify_function(event,
event->notify_context));
* @handle new handle
* @return status code
*/
-efi_status_t efi_create_handle(void **handle)
+efi_status_t efi_create_handle(efi_handle_t *handle)
{
struct efi_object *obj;
efi_status_t r;
* @handler reference to the protocol
* @return status code
*/
-efi_status_t efi_search_protocol(const void *handle,
+efi_status_t efi_search_protocol(const efi_handle_t handle,
const efi_guid_t *protocol_guid,
struct efi_handler **handler)
{
* @protocol_interface interface of the protocol implementation
* @return status code
*/
-efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_remove_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface)
{
struct efi_handler *handler;
* @handle handle from which the protocols shall be deleted
* @return status code
*/
-efi_status_t efi_remove_all_protocols(const void *handle)
+efi_status_t efi_remove_all_protocols(const efi_handle_t handle)
{
struct efi_object *efiobj;
- struct list_head *lhandle;
- struct list_head *pos;
+ struct efi_handler *protocol;
+ struct efi_handler *pos;
efiobj = efi_search_obj(handle);
if (!efiobj)
return EFI_INVALID_PARAMETER;
- list_for_each_safe(lhandle, pos, &efiobj->protocols) {
- struct efi_handler *protocol;
+ list_for_each_entry_safe(protocol, pos, &efiobj->protocols, link) {
efi_status_t ret;
- protocol = list_entry(lhandle, struct efi_handler, link);
-
ret = efi_remove_protocol(handle, protocol->guid,
protocol->protocol_interface);
if (ret != EFI_SUCCESS)
if (!efi_events[i].type)
continue;
if (efi_events[i].is_queued)
- efi_signal_event(&efi_events[i]);
+ efi_signal_event(&efi_events[i], true);
if (!(efi_events[i].type & EVT_TIMER) ||
now < efi_events[i].trigger_next)
continue;
continue;
}
efi_events[i].is_signaled = true;
- efi_signal_event(&efi_events[i]);
+ efi_signal_event(&efi_events[i], true);
}
WATCHDOG_RESET();
}
if (!event[i]->type || event[i]->type & EVT_NOTIFY_SIGNAL)
return EFI_EXIT(EFI_INVALID_PARAMETER);
if (!event[i]->is_signaled)
- efi_signal_event(event[i]);
+ efi_signal_event(event[i], true);
}
/* Wait for signal */
break;
event->is_signaled = true;
if (event->type & EVT_NOTIFY_SIGNAL)
- efi_signal_event(event);
+ efi_signal_event(event, true);
break;
}
return EFI_EXIT(EFI_SUCCESS);
if (!event->type || event->type & EVT_NOTIFY_SIGNAL)
break;
if (!event->is_signaled)
- efi_signal_event(event);
+ efi_signal_event(event, true);
if (event->is_signaled)
return EFI_EXIT(EFI_SUCCESS);
return EFI_EXIT(EFI_NOT_READY);
* @handle handle to find
* @return EFI object
*/
-struct efi_object *efi_search_obj(const void *handle)
+struct efi_object *efi_search_obj(const efi_handle_t handle)
{
struct efi_object *efiobj;
}
/*
+ * Create open protocol info entry and add it to a protocol.
+ *
+ * @handler handler of a protocol
+ * @return open protocol info entry
+ */
+static struct efi_open_protocol_info_entry *efi_create_open_info(
+ struct efi_handler *handler)
+{
+ struct efi_open_protocol_info_item *item;
+
+ item = calloc(1, sizeof(struct efi_open_protocol_info_item));
+ if (!item)
+ return NULL;
+ /* Append the item to the open protocol info list. */
+ list_add_tail(&item->link, &handler->open_infos);
+
+ return &item->info;
+}
+
+/*
+ * Remove an open protocol info entry from a protocol.
+ *
+ * @handler handler of a protocol
+ * @return status code
+ */
+static efi_status_t efi_delete_open_info(
+ struct efi_open_protocol_info_item *item)
+{
+ list_del(&item->link);
+ free(item);
+ return EFI_SUCCESS;
+}
+
+/*
* Install new protocol on a handle.
*
* @handle handle on which the protocol shall be installed
* @protocol_interface interface of the protocol implementation
* @return status code
*/
-efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol,
+efi_status_t efi_add_protocol(const efi_handle_t handle,
+ const efi_guid_t *protocol,
void *protocol_interface)
{
struct efi_object *efiobj;
return EFI_OUT_OF_RESOURCES;
handler->guid = protocol;
handler->protocol_interface = protocol_interface;
+ INIT_LIST_HEAD(&handler->open_infos);
list_add_tail(&handler->link, &efiobj->protocols);
+ if (!guidcmp(&efi_guid_device_path, protocol))
+ EFI_PRINT("installed device path '%pD'\n", protocol_interface);
return EFI_SUCCESS;
}
* @new_interface interface to be installed
* @return status code
*/
-static efi_status_t EFIAPI efi_reinstall_protocol_interface(void *handle,
- const efi_guid_t *protocol, void *old_interface,
- void *new_interface)
+static efi_status_t EFIAPI efi_reinstall_protocol_interface(
+ efi_handle_t handle, const efi_guid_t *protocol,
+ void *old_interface, void *new_interface)
{
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, old_interface,
new_interface);
}
/*
+ * Get all drivers associated to a controller.
+ * The allocated buffer has to be freed with free().
+ *
+ * @efiobj handle of the controller
+ * @protocol protocol guid (optional)
+ * @number_of_drivers number of child controllers
+ * @driver_handle_buffer handles of the the drivers
+ * @return status code
+ */
+static efi_status_t efi_get_drivers(struct efi_object *efiobj,
+ const efi_guid_t *protocol,
+ efi_uintn_t *number_of_drivers,
+ efi_handle_t **driver_handle_buffer)
+{
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ efi_uintn_t count = 0, i;
+ bool duplicate;
+
+ /* Count all driver associations */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ if (protocol && guidcmp(handler->guid, protocol))
+ continue;
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_DRIVER)
+ ++count;
+ }
+ }
+ /*
+ * Create buffer. In case of duplicate driver assignments the buffer
+ * will be too large. But that does not harm.
+ */
+ *number_of_drivers = 0;
+ *driver_handle_buffer = calloc(count, sizeof(efi_handle_t));
+ if (!*driver_handle_buffer)
+ return EFI_OUT_OF_RESOURCES;
+ /* Collect unique driver handles */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ if (protocol && guidcmp(handler->guid, protocol))
+ continue;
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_DRIVER) {
+ /* Check this is a new driver */
+ duplicate = false;
+ for (i = 0; i < *number_of_drivers; ++i) {
+ if ((*driver_handle_buffer)[i] ==
+ item->info.agent_handle)
+ duplicate = true;
+ }
+ /* Copy handle to buffer */
+ if (!duplicate) {
+ i = (*number_of_drivers)++;
+ (*driver_handle_buffer)[i] =
+ item->info.agent_handle;
+ }
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Disconnect all drivers from a controller.
+ *
+ * This function implements the DisconnectController service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @efiobj handle of the controller
+ * @protocol protocol guid (optional)
+ * @child_handle handle of the child to destroy
+ * @return status code
+ */
+static efi_status_t efi_disconnect_all_drivers(
+ struct efi_object *efiobj,
+ const efi_guid_t *protocol,
+ efi_handle_t child_handle)
+{
+ efi_uintn_t number_of_drivers;
+ efi_handle_t *driver_handle_buffer;
+ efi_status_t r, ret;
+
+ ret = efi_get_drivers(efiobj, protocol, &number_of_drivers,
+ &driver_handle_buffer);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_NOT_FOUND;
+ while (number_of_drivers) {
+ r = EFI_CALL(efi_disconnect_controller(
+ efiobj->handle,
+ driver_handle_buffer[--number_of_drivers],
+ child_handle));
+ if (r == EFI_SUCCESS)
+ ret = r;
+ }
+ free(driver_handle_buffer);
+ return ret;
+}
+
+/*
* Uninstall protocol interface.
*
* This function implements the UninstallProtocolInterface service.
* @return status code
*/
static efi_status_t EFIAPI efi_uninstall_protocol_interface(
- void *handle, const efi_guid_t *protocol,
+ efi_handle_t handle, const efi_guid_t *protocol,
void *protocol_interface)
{
+ struct efi_object *efiobj;
struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ struct efi_open_protocol_info_item *pos;
efi_status_t r;
EFI_ENTRY("%p, %pUl, %p", handle, protocol, protocol_interface);
- if (!handle || !protocol) {
+ /* Check handle */
+ efiobj = efi_search_obj(handle);
+ if (!efiobj) {
r = EFI_INVALID_PARAMETER;
goto out;
}
-
/* Find the protocol on the handle */
r = efi_search_protocol(handle, protocol, &handler);
if (r != EFI_SUCCESS)
goto out;
- if (handler->protocol_interface) {
- /* TODO disconnect controllers */
+ /* Disconnect controllers */
+ efi_disconnect_all_drivers(efiobj, protocol, NULL);
+ if (!list_empty(&handler->open_infos)) {
r = EFI_ACCESS_DENIED;
- } else {
- r = efi_remove_protocol(handle, protocol, protocol_interface);
+ goto out;
+ }
+ /* Close protocol */
+ list_for_each_entry_safe(item, pos, &handler->open_infos, link) {
+ if (item->info.attributes ==
+ EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL ||
+ item->info.attributes == EFI_OPEN_PROTOCOL_GET_PROTOCOL ||
+ item->info.attributes == EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ list_del(&item->link);
+ }
+ if (!list_empty(&handler->open_infos)) {
+ r = EFI_ACCESS_DENIED;
+ goto out;
}
+ r = efi_remove_protocol(handle, protocol, protocol_interface);
out:
return EFI_EXIT(r);
}
obj->handle = info;
info->file_path = file_path;
- if (device_path)
- info->device_handle = efi_dp_find_obj(device_path, NULL);
- /*
- * When asking for the device path interface, return
- * bootefi_device_path
- */
- ret = efi_add_protocol(obj->handle, &efi_guid_device_path, device_path);
- if (ret != EFI_SUCCESS)
- goto failure;
+ if (device_path) {
+ info->device_handle = efi_dp_find_obj(device_path, NULL);
+ /*
+ * When asking for the device path interface, return
+ * bootefi_device_path
+ */
+ ret = efi_add_protocol(obj->handle, &efi_guid_device_path,
+ device_path);
+ if (ret != EFI_SUCCESS)
+ goto failure;
+ }
/*
* When asking for the loaded_image interface, just
* for details.
*
* @boot_policy true for request originating from the boot manager
- * @parent_image the calles's image handle
+ * @parent_image the caller's image handle
* @file_path the path of the image to load
* @source_buffer memory location from which the image is installed
* @source_size size of the memory area from which the image is
struct efi_object *obj;
efi_status_t ret;
- EFI_ENTRY("%d, %p, %p, %p, %ld, %p", boot_policy, parent_image,
+ EFI_ENTRY("%d, %p, %pD, %p, %ld, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
info = calloc(1, sizeof(*info));
unsigned long *exit_data_size,
s16 **exit_data)
{
- ulong (*entry)(void *image_handle, struct efi_system_table *st);
+ EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
+ struct efi_system_table *st);
struct efi_loaded_image *info = image_handle;
+ efi_status_t ret;
EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data);
entry = info->reserved;
/* call the image! */
if (setjmp(&info->exit_jmp)) {
- /* We returned from the child image */
+ /*
+ * We called the entry point of the child image with EFI_CALL
+ * in the lines below. The child image called the Exit() boot
+ * service efi_exit() which executed the long jump that brought
+ * us to the current line. This implies that the second half
+ * of the EFI_CALL macro has not been executed.
+ */
+#ifdef CONFIG_ARM
+ /*
+ * efi_exit() called efi_restore_gd(). We have to undo this
+ * otherwise __efi_entry_check() will put the wrong value into
+ * app_gd.
+ */
+ gd = app_gd;
+#endif
+ /*
+ * To get ready to call EFI_EXIT below we have to execute the
+ * missed out steps of EFI_CALL.
+ */
+ assert(__efi_entry_check());
+ debug("%sEFI: %lu returned by started image\n",
+ __efi_nesting_dec(),
+ (unsigned long)((uintptr_t)info->exit_status &
+ ~EFI_ERROR_MASK));
return EFI_EXIT(info->exit_status);
}
- __efi_nesting_dec();
- __efi_exit_check();
- entry(image_handle, &systab);
- __efi_entry_check();
- __efi_nesting_inc();
+ ret = EFI_CALL(entry(image_handle, &systab));
- /* Should usually never get here */
- return EFI_EXIT(EFI_SUCCESS);
+ /*
+ * Usually UEFI applications call Exit() instead of returning.
+ * But because the world doesn not consist of ponies and unicorns,
+ * we're happy to emulate that behavior on behalf of a payload
+ * that forgot.
+ */
+ return EFI_CALL(systab.boottime->exit(image_handle, ret, 0, NULL));
}
/*
exit_data_size, exit_data);
/* Make sure entry/exit counts for EFI world cross-overs match */
- __efi_exit_check();
+ EFI_EXIT(exit_status);
/*
* But longjmp out with the U-Boot gd, not the application's, as
* @image_handle handle of the image to be unloaded
* @return status code
*/
-static efi_status_t EFIAPI efi_unload_image(void *image_handle)
+static efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
{
struct efi_object *efiobj;
}
/*
- * Stop boot services.
+ * Stop all boot services.
*
* This function implements the ExitBootServices service.
* See the Unified Extensible Firmware Interface (UEFI) specification
* for details.
*
+ * All timer events are disabled.
+ * For exit boot services events the notification function is called.
+ * The boot services are disabled in the system table.
+ *
* @image_handle handle of the loaded image
* @map_key key of the memory map
* @return status code
*/
-static efi_status_t EFIAPI efi_exit_boot_services(void *image_handle,
+static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
unsigned long map_key)
{
int i;
EFI_ENTRY("%p, %ld", image_handle, map_key);
+ /* Make sure that notification functions are not called anymore */
+ efi_tpl = TPL_HIGH_LEVEL;
+
+ /* Check if ExitBootServices has already been called */
+ if (!systab.boottime)
+ return EFI_EXIT(EFI_SUCCESS);
+
/* Notify that ExitBootServices is invoked. */
for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
if (efi_events[i].type != EVT_SIGNAL_EXIT_BOOT_SERVICES)
continue;
- efi_signal_event(&efi_events[i]);
+ efi_events[i].is_signaled = true;
+ efi_signal_event(&efi_events[i], false);
}
- /* Make sure that notification functions are not called anymore */
- efi_tpl = TPL_HIGH_LEVEL;
- /* XXX Should persist EFI variables here */
+ /* TODO Should persist EFI variables here */
board_quiesce_devices();
/* This stops all lingering devices */
bootm_disable_interrupts();
+ /* Disable boottime services */
+ systab.con_in_handle = NULL;
+ systab.con_in = NULL;
+ systab.con_out_handle = NULL;
+ systab.con_out = NULL;
+ systab.stderr_handle = NULL;
+ systab.std_err = NULL;
+ systab.boottime = NULL;
+
+ /* Recalculate CRC32 */
+ systab.hdr.crc32 = 0;
+ systab.hdr.crc32 = crc32(0, (const unsigned char *)&systab,
+ sizeof(struct efi_system_table));
+
/* Give the payload some time to boot */
efi_set_watchdog(0);
WATCHDOG_RESET();
}
/*
- * Connect a controller to a driver.
- *
- * This function implements the ConnectController service.
- * See the Unified Extensible Firmware Interface (UEFI) specification
- * for details.
- *
- * @controller_handle handle of the controller
- * @driver_image_handle handle of the driver
- * @remain_device_path device path of a child controller
- * @recursive true to connect all child controllers
- * @return status code
- */
-static efi_status_t EFIAPI efi_connect_controller(
- efi_handle_t controller_handle,
- efi_handle_t *driver_image_handle,
- struct efi_device_path *remain_device_path,
- bool recursive)
-{
- EFI_ENTRY("%p, %p, %p, %d", controller_handle, driver_image_handle,
- remain_device_path, recursive);
- return EFI_EXIT(EFI_NOT_FOUND);
-}
-
-/*
- * Disconnect a controller from a driver.
- *
- * This function implements the DisconnectController service.
- * See the Unified Extensible Firmware Interface (UEFI) specification
- * for details.
- *
- * @controller_handle handle of the controller
- * @driver_image_handle handle of the driver
- * @child_handle handle of the child to destroy
- * @return status code
- */
-static efi_status_t EFIAPI efi_disconnect_controller(void *controller_handle,
- void *driver_image_handle,
- void *child_handle)
-{
- EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle,
- child_handle);
- return EFI_EXIT(EFI_INVALID_PARAMETER);
-}
-
-/*
* Close a protocol.
*
* This function implements the CloseProtocol service.
* @controller_handle handle of the controller
* @return status code
*/
-static efi_status_t EFIAPI efi_close_protocol(void *handle,
+static efi_status_t EFIAPI efi_close_protocol(efi_handle_t handle,
const efi_guid_t *protocol,
- void *agent_handle,
- void *controller_handle)
+ efi_handle_t agent_handle,
+ efi_handle_t controller_handle)
{
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ struct efi_open_protocol_info_item *pos;
+ efi_status_t r;
+
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, agent_handle,
controller_handle);
- return EFI_EXIT(EFI_NOT_FOUND);
+
+ if (!agent_handle) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ r = efi_search_protocol(handle, protocol, &handler);
+ if (r != EFI_SUCCESS)
+ goto out;
+
+ r = EFI_NOT_FOUND;
+ list_for_each_entry_safe(item, pos, &handler->open_infos, link) {
+ if (item->info.agent_handle == agent_handle &&
+ item->info.controller_handle == controller_handle) {
+ efi_delete_open_info(item);
+ r = EFI_SUCCESS;
+ break;
+ }
+ }
+out:
+ return EFI_EXIT(r);
}
/*
struct efi_open_protocol_info_entry **entry_buffer,
efi_uintn_t *entry_count)
{
+ unsigned long buffer_size;
+ unsigned long count;
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ efi_status_t r;
+
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, entry_buffer,
entry_count);
- return EFI_EXIT(EFI_NOT_FOUND);
+
+ /* Check parameters */
+ if (!entry_buffer) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ r = efi_search_protocol(handle, protocol, &handler);
+ if (r != EFI_SUCCESS)
+ goto out;
+
+ /* Count entries */
+ count = 0;
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.open_count)
+ ++count;
+ }
+ *entry_count = count;
+ *entry_buffer = NULL;
+ if (!count) {
+ r = EFI_SUCCESS;
+ goto out;
+ }
+
+ /* Copy entries */
+ buffer_size = count * sizeof(struct efi_open_protocol_info_entry);
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, buffer_size,
+ (void **)entry_buffer);
+ if (r != EFI_SUCCESS)
+ goto out;
+ list_for_each_entry_reverse(item, &handler->open_infos, link) {
+ if (item->info.open_count)
+ (*entry_buffer)[--count] = item->info;
+ }
+out:
+ return EFI_EXIT(r);
}
/*
* @protocol_buffer_count number of entries in the buffer
* @return status code
*/
-static efi_status_t EFIAPI efi_protocols_per_handle(void *handle,
- efi_guid_t ***protocol_buffer,
+static efi_status_t EFIAPI efi_protocols_per_handle(
+ efi_handle_t handle, efi_guid_t ***protocol_buffer,
efi_uintn_t *protocol_buffer_count)
{
unsigned long buffer_size;
r = efi_locate_handle(search_type, protocol, search_key, &buffer_size,
*buffer);
if (r == EFI_SUCCESS)
- *no_handles = buffer_size / sizeof(void *);
+ *no_handles = buffer_size / sizeof(efi_handle_t);
out:
return EFI_EXIT(r);
}
/*
* Open protocol interface on a handle.
*
+ * @handler handler of a protocol
+ * @protocol_interface interface implementing the protocol
+ * @agent_handle handle of the driver
+ * @controller_handle handle of the controller
+ * @attributes attributes indicating how to open the protocol
+ * @return status code
+ */
+static efi_status_t efi_protocol_open(
+ struct efi_handler *handler,
+ void **protocol_interface, void *agent_handle,
+ void *controller_handle, uint32_t attributes)
+{
+ struct efi_open_protocol_info_item *item;
+ struct efi_open_protocol_info_entry *match = NULL;
+ bool opened_by_driver = false;
+ bool opened_exclusive = false;
+
+ /* If there is no agent, only return the interface */
+ if (!agent_handle)
+ goto out;
+
+ /* For TEST_PROTOCOL ignore interface attribute */
+ if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ *protocol_interface = NULL;
+
+ /*
+ * Check if the protocol is already opened by a driver with the same
+ * attributes or opened exclusively
+ */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == agent_handle) {
+ if ((attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) &&
+ (item->info.attributes == attributes))
+ return EFI_ALREADY_STARTED;
+ }
+ if (item->info.attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE)
+ opened_exclusive = true;
+ }
+
+ /* Only one controller can open the protocol exclusively */
+ if (opened_exclusive && attributes &
+ (EFI_OPEN_PROTOCOL_EXCLUSIVE | EFI_OPEN_PROTOCOL_BY_DRIVER))
+ return EFI_ACCESS_DENIED;
+
+ /* Prepare exclusive opening */
+ if (attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) {
+ /* Try to disconnect controllers */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes ==
+ EFI_OPEN_PROTOCOL_BY_DRIVER)
+ EFI_CALL(efi_disconnect_controller(
+ item->info.controller_handle,
+ item->info.agent_handle,
+ NULL));
+ }
+ opened_by_driver = false;
+ /* Check if all controllers are disconnected */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes & EFI_OPEN_PROTOCOL_BY_DRIVER)
+ opened_by_driver = true;
+ }
+ /* Only one controller can be conncected */
+ if (opened_by_driver)
+ return EFI_ACCESS_DENIED;
+ }
+
+ /* Find existing entry */
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == agent_handle &&
+ item->info.controller_handle == controller_handle)
+ match = &item->info;
+ }
+ /* None found, create one */
+ if (!match) {
+ match = efi_create_open_info(handler);
+ if (!match)
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ match->agent_handle = agent_handle;
+ match->controller_handle = controller_handle;
+ match->attributes = attributes;
+ match->open_count++;
+
+out:
+ /* For TEST_PROTOCOL ignore interface attribute. */
+ if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ *protocol_interface = handler->protocol_interface;
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Open protocol interface on a handle.
+ *
* This function implements the OpenProtocol interface.
* See the Unified Extensible Firmware Interface (UEFI) specification
* for details.
case EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER:
if (controller_handle == handle)
goto out;
+ /* fall-through */
case EFI_OPEN_PROTOCOL_BY_DRIVER:
case EFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE:
- if (controller_handle == NULL)
+ /* Check that the controller handle is valid */
+ if (!efi_search_obj(controller_handle))
goto out;
+ /* fall-through */
case EFI_OPEN_PROTOCOL_EXCLUSIVE:
- if (agent_handle == NULL)
+ /* Check that the agent handle is valid */
+ if (!efi_search_obj(agent_handle))
goto out;
break;
default:
if (r != EFI_SUCCESS)
goto out;
- if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
- *protocol_interface = handler->protocol_interface;
+ r = efi_protocol_open(handler, protocol_interface, agent_handle,
+ controller_handle, attributes);
out:
return EFI_EXIT(r);
}
* @protocol_interface interface implementing the protocol
* @return status code
*/
-static efi_status_t EFIAPI efi_handle_protocol(void *handle,
+static efi_status_t EFIAPI efi_handle_protocol(efi_handle_t handle,
const efi_guid_t *protocol,
void **protocol_interface)
{
NULL, EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL);
}
+static efi_status_t efi_bind_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ struct efi_device_path *remain_device_path)
+{
+ struct efi_driver_binding_protocol *binding_protocol;
+ efi_status_t r;
+
+ r = EFI_CALL(efi_open_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ (void **)&binding_protocol,
+ driver_image_handle, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (r != EFI_SUCCESS)
+ return r;
+ r = EFI_CALL(binding_protocol->supported(binding_protocol,
+ controller_handle,
+ remain_device_path));
+ if (r == EFI_SUCCESS)
+ r = EFI_CALL(binding_protocol->start(binding_protocol,
+ controller_handle,
+ remain_device_path));
+ EFI_CALL(efi_close_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ driver_image_handle, NULL));
+ return r;
+}
+
+static efi_status_t efi_connect_single_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t *driver_image_handle,
+ struct efi_device_path *remain_device_path)
+{
+ efi_handle_t *buffer;
+ size_t count;
+ size_t i;
+ efi_status_t r;
+ size_t connected = 0;
+
+ /* Get buffer with all handles with driver binding protocol */
+ r = EFI_CALL(efi_locate_handle_buffer(BY_PROTOCOL,
+ &efi_guid_driver_binding_protocol,
+ NULL, &count, &buffer));
+ if (r != EFI_SUCCESS)
+ return r;
+
+ /* Context Override */
+ if (driver_image_handle) {
+ for (; *driver_image_handle; ++driver_image_handle) {
+ for (i = 0; i < count; ++i) {
+ if (buffer[i] == *driver_image_handle) {
+ buffer[i] = NULL;
+ r = efi_bind_controller(
+ controller_handle,
+ *driver_image_handle,
+ remain_device_path);
+ /*
+ * For drivers that do not support the
+ * controller or are already connected
+ * we receive an error code here.
+ */
+ if (r == EFI_SUCCESS)
+ ++connected;
+ }
+ }
+ }
+ }
+
+ /*
+ * TODO: Some overrides are not yet implemented:
+ * - Platform Driver Override
+ * - Driver Family Override Search
+ * - Bus Specific Driver Override
+ */
+
+ /* Driver Binding Search */
+ for (i = 0; i < count; ++i) {
+ if (buffer[i]) {
+ r = efi_bind_controller(controller_handle,
+ buffer[i],
+ remain_device_path);
+ if (r == EFI_SUCCESS)
+ ++connected;
+ }
+ }
+
+ efi_free_pool(buffer);
+ if (!connected)
+ return EFI_NOT_FOUND;
+ return EFI_SUCCESS;
+}
+
+/*
+ * Connect a controller to a driver.
+ *
+ * This function implements the ConnectController service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * First all driver binding protocol handles are tried for binding drivers.
+ * Afterwards all handles that have openened a protocol of the controller
+ * with EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER are connected to drivers.
+ *
+ * @controller_handle handle of the controller
+ * @driver_image_handle handle of the driver
+ * @remain_device_path device path of a child controller
+ * @recursive true to connect all child controllers
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_connect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t *driver_image_handle,
+ struct efi_device_path *remain_device_path,
+ bool recursive)
+{
+ efi_status_t r;
+ efi_status_t ret = EFI_NOT_FOUND;
+ struct efi_object *efiobj;
+
+ EFI_ENTRY("%p, %p, %p, %d", controller_handle, driver_image_handle,
+ remain_device_path, recursive);
+
+ efiobj = efi_search_obj(controller_handle);
+ if (!efiobj) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ r = efi_connect_single_controller(controller_handle,
+ driver_image_handle,
+ remain_device_path);
+ if (r == EFI_SUCCESS)
+ ret = EFI_SUCCESS;
+ if (recursive) {
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ r = EFI_CALL(efi_connect_controller(
+ item->info.controller_handle,
+ driver_image_handle,
+ remain_device_path,
+ recursive));
+ if (r == EFI_SUCCESS)
+ ret = EFI_SUCCESS;
+ }
+ }
+ }
+ }
+ /* Check for child controller specified by end node */
+ if (ret != EFI_SUCCESS && remain_device_path &&
+ remain_device_path->type == DEVICE_PATH_TYPE_END)
+ ret = EFI_SUCCESS;
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * Get all child controllers associated to a driver.
+ * The allocated buffer has to be freed with free().
+ *
+ * @efiobj handle of the controller
+ * @driver_handle handle of the driver
+ * @number_of_children number of child controllers
+ * @child_handle_buffer handles of the the child controllers
+ */
+static efi_status_t efi_get_child_controllers(
+ struct efi_object *efiobj,
+ efi_handle_t driver_handle,
+ efi_uintn_t *number_of_children,
+ efi_handle_t **child_handle_buffer)
+{
+ struct efi_handler *handler;
+ struct efi_open_protocol_info_item *item;
+ efi_uintn_t count = 0, i;
+ bool duplicate;
+
+ /* Count all child controller associations */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == driver_handle &&
+ item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
+ ++count;
+ }
+ }
+ /*
+ * Create buffer. In case of duplicate child controller assignments
+ * the buffer will be too large. But that does not harm.
+ */
+ *number_of_children = 0;
+ *child_handle_buffer = calloc(count, sizeof(efi_handle_t));
+ if (!*child_handle_buffer)
+ return EFI_OUT_OF_RESOURCES;
+ /* Copy unique child handles */
+ list_for_each_entry(handler, &efiobj->protocols, link) {
+ list_for_each_entry(item, &handler->open_infos, link) {
+ if (item->info.agent_handle == driver_handle &&
+ item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ /* Check this is a new child controller */
+ duplicate = false;
+ for (i = 0; i < *number_of_children; ++i) {
+ if ((*child_handle_buffer)[i] ==
+ item->info.controller_handle)
+ duplicate = true;
+ }
+ /* Copy handle to buffer */
+ if (!duplicate) {
+ i = (*number_of_children)++;
+ (*child_handle_buffer)[i] =
+ item->info.controller_handle;
+ }
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Disconnect a controller from a driver.
+ *
+ * This function implements the DisconnectController service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @controller_handle handle of the controller
+ * @driver_image_handle handle of the driver
+ * @child_handle handle of the child to destroy
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_disconnect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t driver_image_handle,
+ efi_handle_t child_handle)
+{
+ struct efi_driver_binding_protocol *binding_protocol;
+ efi_handle_t *child_handle_buffer = NULL;
+ size_t number_of_children = 0;
+ efi_status_t r;
+ size_t stop_count = 0;
+ struct efi_object *efiobj;
+
+ EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle,
+ child_handle);
+
+ efiobj = efi_search_obj(controller_handle);
+ if (!efiobj) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ if (child_handle && !efi_search_obj(child_handle)) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* If no driver handle is supplied, disconnect all drivers */
+ if (!driver_image_handle) {
+ r = efi_disconnect_all_drivers(efiobj, NULL, child_handle);
+ goto out;
+ }
+
+ /* Create list of child handles */
+ if (child_handle) {
+ number_of_children = 1;
+ child_handle_buffer = &child_handle;
+ } else {
+ efi_get_child_controllers(efiobj,
+ driver_image_handle,
+ &number_of_children,
+ &child_handle_buffer);
+ }
+
+ /* Get the driver binding protocol */
+ r = EFI_CALL(efi_open_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ (void **)&binding_protocol,
+ driver_image_handle, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (r != EFI_SUCCESS)
+ goto out;
+ /* Remove the children */
+ if (number_of_children) {
+ r = EFI_CALL(binding_protocol->stop(binding_protocol,
+ controller_handle,
+ number_of_children,
+ child_handle_buffer));
+ if (r == EFI_SUCCESS)
+ ++stop_count;
+ }
+ /* Remove the driver */
+ if (!child_handle)
+ r = EFI_CALL(binding_protocol->stop(binding_protocol,
+ controller_handle,
+ 0, NULL));
+ if (r == EFI_SUCCESS)
+ ++stop_count;
+ EFI_CALL(efi_close_protocol(driver_image_handle,
+ &efi_guid_driver_binding_protocol,
+ driver_image_handle, NULL));
+
+ if (stop_count)
+ r = EFI_SUCCESS;
+ else
+ r = EFI_NOT_FOUND;
+out:
+ if (!child_handle)
+ free(child_handle_buffer);
+ return EFI_EXIT(r);
+}
+
static const struct efi_boot_services efi_boot_services = {
.hdr = {
.headersize = sizeof(struct efi_table_hdr),
};
-static uint16_t __efi_runtime_data firmware_vendor[] =
- { 'D','a','s',' ','U','-','b','o','o','t',0 };
+static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
struct efi_system_table __efi_runtime_data systab = {
.hdr = {
{
}
+/*
+ * Notification function of the console timer event.
+ *
+ * event: console timer event
+ * context: not used
+ */
static void EFIAPI efi_console_timer_notify(struct efi_event *event,
void *context)
{
EFI_ENTRY("%p, %p", event, context);
+
+ /* Check if input is available */
if (tstc()) {
+ /* Queue the wait for key event */
efi_con_in.wait_for_key->is_signaled = true;
- efi_signal_event(efi_con_in.wait_for_key);
- }
+ efi_signal_event(efi_con_in.wait_for_key, true);
+ }
EFI_EXIT(EFI_SUCCESS);
}
-
/* This gets called from do_bootefi_exec(). */
int efi_console_register(void)
{
struct efi_object *efi_console_input_obj;
/* Create handles */
- r = efi_create_handle((void **)&efi_console_control_obj);
+ r = efi_create_handle((efi_handle_t *)&efi_console_control_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
r = efi_add_protocol(efi_console_control_obj->handle,
&efi_guid_console_control, &efi_console_control);
if (r != EFI_SUCCESS)
goto out_of_memory;
- r = efi_create_handle((void **)&efi_console_output_obj);
+ r = efi_create_handle((efi_handle_t *)&efi_console_output_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
r = efi_add_protocol(efi_console_output_obj->handle,
&efi_guid_text_output_protocol, &efi_con_out);
if (r != EFI_SUCCESS)
goto out_of_memory;
- r = efi_create_handle((void **)&efi_console_input_obj);
+ r = efi_create_handle((efi_handle_t *)&efi_console_input_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
r = efi_add_protocol(efi_console_input_obj->handle,
* SPDX-License-Identifier: GPL-2.0+
*/
+#define LOG_CATEGORY LOGL_ERR
+
#include <common.h>
#include <blk.h>
#include <dm.h>
{
void *buf;
- if (efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, sz, &buf) != EFI_SUCCESS)
+ if (efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, sz, &buf) !=
+ EFI_SUCCESS) {
+ debug("EFI: ERROR: out of memory in %s\n", __func__);
return NULL;
+ }
return buf;
}
}
}
-
/*
* See UEFI spec (section 3.1.2, about short-form device-paths..
* tl;dr: we can have a device-path that starts with a USB WWID
return NULL;
}
-
/*
* Find an efiobj from device-path, if 'rem' is not NULL, returns the
* remaining part of the device path after the matched object.
return efiobj;
}
+/*
+ * Determine the last device path node that is not the end node.
+ *
+ * @dp device path
+ * @return last node before the end node if it exists
+ * otherwise NULL
+ */
+const struct efi_device_path *efi_dp_last_node(const struct efi_device_path *dp)
+{
+ struct efi_device_path *ret;
+
+ if (!dp || dp->type == DEVICE_PATH_TYPE_END)
+ return NULL;
+ while (dp) {
+ ret = (struct efi_device_path *)dp;
+ dp = efi_dp_next(dp);
+ }
+ return ret;
+}
+
/* return size not including End node: */
unsigned efi_dp_size(const struct efi_device_path *dp)
{
return NULL;
ndp = dp_alloc(sz);
+ if (!ndp)
+ return NULL;
memcpy(ndp, dp, sz);
return ndp;
unsigned sz1 = efi_dp_size(dp1);
unsigned sz2 = efi_dp_size(dp2);
void *p = dp_alloc(sz1 + sz2 + sizeof(END));
+ if (!p)
+ return NULL;
memcpy(p, dp1, sz1);
memcpy(p + sz1, dp2, sz2);
memcpy(p + sz1 + sz2, &END, sizeof(END));
} else if (!dp) {
unsigned sz = node->length;
void *p = dp_alloc(sz + sizeof(END));
+ if (!p)
+ return NULL;
memcpy(p, node, sz);
memcpy(p + sz, &END, sizeof(END));
ret = p;
/* both dp and node are non-null */
unsigned sz = efi_dp_size(dp);
void *p = dp_alloc(sz + node->length + sizeof(END));
+ if (!p)
+ return NULL;
memcpy(p, dp, sz);
memcpy(p + sz, node, node->length);
memcpy(p + sz + node->length, &END, sizeof(END));
case UCLASS_SIMPLE_BUS:
/* stop traversing parents at this point: */
return sizeof(ROOT);
+ case UCLASS_ETH:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_mac_addr);
+#ifdef CONFIG_BLK
+ case UCLASS_BLK:
+ switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_IDE
+ case UCLASS_IDE:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_atapi);
+#endif
+#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+ case UCLASS_SCSI:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_scsi);
+#endif
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+ case UCLASS_MMC:
+ return dp_size(dev->parent) +
+ sizeof(struct efi_device_path_sd_mmc_path);
+#endif
+ default:
+ return dp_size(dev->parent);
+ }
+#endif
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
+#endif
case UCLASS_MASS_STORAGE:
case UCLASS_USB_HUB:
return dp_size(dev->parent) +
}
}
+/*
+ * Recursively build a device path.
+ *
+ * @buf pointer to the end of the device path
+ * @dev device
+ * @return pointer to the end of the device path
+ */
static void *dp_fill(void *buf, struct udevice *dev)
{
if (!dev || !dev->driver)
*vdp = ROOT;
return &vdp[1];
}
+#ifdef CONFIG_DM_ETH
+ case UCLASS_ETH: {
+ struct efi_device_path_mac_addr *dp =
+ dp_fill(buf, dev->parent);
+ struct eth_pdata *pdata = dev->platdata;
+
+ dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
+ dp->dp.length = sizeof(*dp);
+ memset(&dp->mac, 0, sizeof(dp->mac));
+ /* We only support IPv4 */
+ memcpy(&dp->mac, &pdata->enetaddr, ARP_HLEN);
+ /* Ethernet */
+ dp->if_type = 1;
+ return &dp[1];
+ }
+#endif
+#ifdef CONFIG_BLK
+ case UCLASS_BLK:
+ switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_IDE
+ case UCLASS_IDE: {
+ struct efi_device_path_atapi *dp =
+ dp_fill(buf, dev->parent);
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_ATAPI;
+ dp->dp.length = sizeof(*dp);
+ dp->logical_unit_number = desc->devnum;
+ dp->primary_secondary = IDE_BUS(desc->devnum);
+ dp->slave_master = desc->devnum %
+ (CONFIG_SYS_IDE_MAXDEVICE /
+ CONFIG_SYS_IDE_MAXBUS);
+ return &dp[1];
+ }
+#endif
+#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+ case UCLASS_SCSI: {
+ struct efi_device_path_scsi *dp =
+ dp_fill(buf, dev->parent);
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SCSI;
+ dp->dp.length = sizeof(*dp);
+ dp->logical_unit_number = desc->lun;
+ dp->target_id = desc->target;
+ return &dp[1];
+ }
+#endif
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+ case UCLASS_MMC: {
+ struct efi_device_path_sd_mmc_path *sddp =
+ dp_fill(buf, dev->parent);
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ sddp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ sddp->dp.sub_type = is_sd(desc) ?
+ DEVICE_PATH_SUB_TYPE_MSG_SD :
+ DEVICE_PATH_SUB_TYPE_MSG_MMC;
+ sddp->dp.length = sizeof(*sddp);
+ sddp->slot_number = dev->seq;
+ return &sddp[1];
+ }
+#endif
+ default:
+ debug("%s(%u) %s: unhandled parent class: %s (%u)\n",
+ __FILE__, __LINE__, __func__,
+ dev->name, dev->parent->uclass->uc_drv->id);
+ return dp_fill(buf, dev->parent);
+ }
+#endif
#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
return &udp[1];
}
default:
- debug("unhandled device class: %s (%u)\n",
+ debug("%s(%u) %s: unhandled device class: %s (%u)\n",
+ __FILE__, __LINE__, __func__,
dev->name, dev->driver->id);
return dp_fill(buf, dev->parent);
}
void *buf, *start;
start = buf = dp_alloc(dp_size(dev) + sizeof(END));
+ if (!buf)
+ return NULL;
buf = dp_fill(buf, dev);
*((struct efi_device_path *)buf) = END;
unsigned dpsize;
#ifdef CONFIG_BLK
- dpsize = dp_size(desc->bdev->parent);
+ {
+ struct udevice *dev;
+ int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+ if (ret)
+ dev = desc->bdev->parent;
+ dpsize = dp_size(dev);
+ }
#else
dpsize = sizeof(ROOT) + sizeof(struct efi_device_path_usb);
#endif
}
/*
- * Create a device path for a block device or one of its partitions.
+ * Create a device node for a block device partition.
*
* @buf buffer to which the device path is wirtten
* @desc block device descriptor
* @part partition number, 0 identifies a block device
*/
-static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
+static void *dp_part_node(void *buf, struct blk_desc *desc, int part)
{
disk_partition_t info;
-#ifdef CONFIG_BLK
- buf = dp_fill(buf, desc->bdev->parent);
-#else
- /*
- * We *could* make a more accurate path, by looking at if_type
- * and handling all the different cases like we do for non-
- * legacy (ie CONFIG_BLK=y) case. But most important thing
- * is just to have a unique device-path for if_type+devnum.
- * So map things to a fictitious USB device.
- */
- struct efi_device_path_usb *udp;
-
- memcpy(buf, &ROOT, sizeof(ROOT));
- buf += sizeof(ROOT);
-
- udp = buf;
- udp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- udp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_USB;
- udp->dp.length = sizeof(*udp);
- udp->parent_port_number = desc->if_type;
- udp->usb_interface = desc->devnum;
- buf = &udp[1];
-#endif
-
- if (part == 0) /* the actual disk, not a partition */
- return buf;
-
part_get_info(desc, part, &info);
if (desc->part_type == PART_TYPE_ISO) {
return buf;
}
+/*
+ * Create a device path for a block device or one of its partitions.
+ *
+ * @buf buffer to which the device path is wirtten
+ * @desc block device descriptor
+ * @part partition number, 0 identifies a block device
+ */
+static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
+{
+#ifdef CONFIG_BLK
+ {
+ struct udevice *dev;
+ int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+ if (ret)
+ dev = desc->bdev->parent;
+ buf = dp_fill(buf, dev);
+ }
+#else
+ /*
+ * We *could* make a more accurate path, by looking at if_type
+ * and handling all the different cases like we do for non-
+ * legacy (ie CONFIG_BLK=y) case. But most important thing
+ * is just to have a unique device-path for if_type+devnum.
+ * So map things to a fictitious USB device.
+ */
+ struct efi_device_path_usb *udp;
+
+ memcpy(buf, &ROOT, sizeof(ROOT));
+ buf += sizeof(ROOT);
+
+ udp = buf;
+ udp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ udp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_USB;
+ udp->dp.length = sizeof(*udp);
+ udp->parent_port_number = desc->if_type;
+ udp->usb_interface = desc->devnum;
+ buf = &udp[1];
+#endif
+
+ if (part == 0) /* the actual disk, not a partition */
+ return buf;
+
+ return dp_part_node(buf, desc, part);
+}
/* Construct a device-path from a partition on a blk device: */
struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part)
void *buf, *start;
start = buf = dp_alloc(dp_part_size(desc, part) + sizeof(END));
+ if (!buf)
+ return NULL;
buf = dp_part_fill(buf, desc, part);
return start;
}
+/*
+ * Create a device node for a block device partition.
+ *
+ * @buf buffer to which the device path is wirtten
+ * @desc block device descriptor
+ * @part partition number, 0 identifies a block device
+ */
+struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part)
+{
+ efi_uintn_t dpsize;
+ void *buf;
+
+ if (desc->part_type == PART_TYPE_ISO)
+ dpsize = sizeof(struct efi_device_path_cdrom_path);
+ else
+ dpsize = sizeof(struct efi_device_path_hard_drive_path);
+ buf = dp_alloc(dpsize);
+
+ dp_part_node(buf, desc, part);
+
+ return buf;
+}
+
/* convert path to an UEFI style path (ie. DOS style backslashes and utf16) */
static void path_to_uefi(u16 *uefi, const char *path)
{
dpsize += fpsize;
start = buf = dp_alloc(dpsize + sizeof(END));
+ if (!buf)
+ return NULL;
if (desc)
buf = dp_part_fill(buf, desc, part);
dpsize += sizeof(*ndp);
start = buf = dp_alloc(dpsize + sizeof(END));
+ if (!buf)
+ return NULL;
#ifdef CONFIG_DM_ETH
buf = dp_fill(buf, eth_get_dev());
void *buf, *start;
start = buf = dp_alloc(sizeof(*mdp) + sizeof(END));
+ if (!buf)
+ return NULL;
mdp = buf;
mdp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
* Helper to split a full device path (containing both device and file
* parts) into it's constituent parts.
*/
-void efi_dp_split_file_path(struct efi_device_path *full_path,
- struct efi_device_path **device_path,
- struct efi_device_path **file_path)
+efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
+ struct efi_device_path **device_path,
+ struct efi_device_path **file_path)
{
struct efi_device_path *p, *dp, *fp;
+ *device_path = NULL;
+ *file_path = NULL;
dp = efi_dp_dup(full_path);
+ if (!dp)
+ return EFI_OUT_OF_RESOURCES;
p = dp;
- while (!EFI_DP_TYPE(p, MEDIA_DEVICE, FILE_PATH))
+ while (!EFI_DP_TYPE(p, MEDIA_DEVICE, FILE_PATH)) {
p = efi_dp_next(p);
+ if (!p)
+ return EFI_OUT_OF_RESOURCES;
+ }
fp = efi_dp_dup(p);
-
+ if (!fp)
+ return EFI_OUT_OF_RESOURCES;
p->type = DEVICE_PATH_TYPE_END;
p->sub_type = DEVICE_PATH_SUB_TYPE_END;
p->length = sizeof(*p);
*device_path = dp;
*file_path = fp;
+ return EFI_SUCCESS;
}
static char *dp_msging(char *s, struct efi_device_path *dp)
{
switch (dp->sub_type) {
+ case DEVICE_PATH_SUB_TYPE_MSG_ATAPI: {
+ struct efi_device_path_atapi *ide =
+ (struct efi_device_path_atapi *)dp;
+ s += sprintf(s, "Ata(%d,%d,%d)", ide->primary_secondary,
+ ide->slave_master, ide->logical_unit_number);
+ break;
+ }
+ case DEVICE_PATH_SUB_TYPE_MSG_SCSI: {
+ struct efi_device_path_scsi *ide =
+ (struct efi_device_path_scsi *)dp;
+ s += sprintf(s, "Scsi(%u,%u)", ide->target_id,
+ ide->logical_unit_number);
+ break;
+ }
case DEVICE_PATH_SUB_TYPE_MSG_USB: {
struct efi_device_path_usb *udp =
(struct efi_device_path_usb *)dp;
case DEVICE_PATH_TYPE_MEDIA_DEVICE:
str = dp_media(str, dp);
break;
+ case DEVICE_PATH_TYPE_END:
+ break;
default:
str = dp_unknown(str, dp);
}
#include <part.h>
#include <malloc.h>
-static const efi_guid_t efi_block_io_guid = BLOCK_IO_GUID;
+const efi_guid_t efi_block_io_guid = BLOCK_IO_GUID;
struct efi_disk_obj {
/* Generic EFI object parent class data */
}
static efi_status_t EFIAPI efi_disk_read_blocks(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer)
{
void *real_buffer = buffer;
real_buffer = efi_bounce_buffer;
#endif
- EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ EFI_ENTRY("%p, %x, %" PRIx64 ", %zx, %p", this, media_id, lba,
buffer_size, buffer);
r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
}
static efi_status_t EFIAPI efi_disk_write_blocks(struct efi_block_io *this,
- u32 media_id, u64 lba, unsigned long buffer_size,
+ u32 media_id, u64 lba, efi_uintn_t buffer_size,
void *buffer)
{
void *real_buffer = buffer;
real_buffer = efi_bounce_buffer;
#endif
- EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ EFI_ENTRY("%p, %x, %" PRIx64 ", %zx, %p", this, media_id, lba,
buffer_size, buffer);
/* Populate bounce buffer if necessary */
};
/*
- * Find filesystem from a device-path. The passed in path 'p' probably
- * contains one or more /File(name) nodes, so the comparison stops at
- * the first /File() node, and returns the pointer to that via 'rp'.
- * This is mostly intended to be a helper to map a device-path to an
- * efi_file_handle object.
+ * Get the simple file system protocol for a file device path.
+ *
+ * The full path provided is split into device part and into a file
+ * part. The device part is used to find the handle on which the
+ * simple file system protocol is installed.
+ *
+ * @full_path device path including device and file
+ * @return simple file system protocol
*/
struct efi_simple_file_system_protocol *
-efi_fs_from_path(struct efi_device_path *fp)
+efi_fs_from_path(struct efi_device_path *full_path)
{
struct efi_object *efiobj;
- struct efi_disk_obj *diskobj;
+ struct efi_handler *handler;
+ struct efi_device_path *device_path;
+ struct efi_device_path *file_path;
+ efi_status_t ret;
- efiobj = efi_dp_find_obj(fp, NULL);
+ /* Split the path into a device part and a file part */
+ ret = efi_dp_split_file_path(full_path, &device_path, &file_path);
+ if (ret != EFI_SUCCESS)
+ return NULL;
+ efi_free_pool(file_path);
+
+ /* Get the EFI object for the partition */
+ efiobj = efi_dp_find_obj(device_path, NULL);
+ efi_free_pool(device_path);
if (!efiobj)
return NULL;
- diskobj = container_of(efiobj, struct efi_disk_obj, parent);
+ /* Find the simple file system protocol */
+ ret = efi_search_protocol(efiobj, &efi_simple_file_system_protocol_guid,
+ &handler);
+ if (ret != EFI_SUCCESS)
+ return NULL;
- return diskobj->volume;
+ /* Return the simple file system protocol for the partition */
+ return handler->protocol_interface;
}
/*
- * Create a device for a disk
+ * Create a handle for a partition or disk
*
- * @name not used
+ * @parent parent handle
+ * @dp_parent parent device path
* @if_typename interface name for block device
* @desc internal block device
* @dev_index device index for block device
* @offset offset into disk for simple partitions
+ * @return disk object
*/
-static void efi_disk_add_dev(const char *name,
- const char *if_typename,
- struct blk_desc *desc,
- int dev_index,
- lbaint_t offset,
- unsigned int part)
+static struct efi_disk_obj *efi_disk_add_dev(
+ efi_handle_t parent,
+ struct efi_device_path *dp_parent,
+ const char *if_typename,
+ struct blk_desc *desc,
+ int dev_index,
+ lbaint_t offset,
+ unsigned int part)
{
struct efi_disk_obj *diskobj;
efi_status_t ret;
/* Don't add empty devices */
if (!desc->lba)
- return;
+ return NULL;
diskobj = calloc(1, sizeof(*diskobj));
if (!diskobj)
efi_add_handle(&diskobj->parent);
/* Fill in object data */
- diskobj->dp = efi_dp_from_part(desc, part);
+ if (part) {
+ struct efi_device_path *node = efi_dp_part_node(desc, part);
+
+ diskobj->dp = efi_dp_append_node(dp_parent, node);
+ efi_free_pool(node);
+ } else {
+ diskobj->dp = efi_dp_from_part(desc, part);
+ }
diskobj->part = part;
ret = efi_add_protocol(diskobj->parent.handle, &efi_block_io_guid,
&diskobj->ops);
diskobj->dp);
ret = efi_add_protocol(diskobj->parent.handle,
&efi_simple_file_system_protocol_guid,
- &diskobj->volume);
+ diskobj->volume);
if (ret != EFI_SUCCESS)
goto out_of_memory;
}
if (part != 0)
diskobj->media.logical_partition = 1;
diskobj->ops.media = &diskobj->media;
- return;
+ return diskobj;
out_of_memory:
printf("ERROR: Out of memory\n");
+ return NULL;
}
-static int efi_disk_create_partitions(struct blk_desc *desc,
- const char *if_typename,
- int diskid,
- const char *pdevname)
+/*
+ * Create handles and protocols for the partitions of a block device
+ *
+ * @parent handle of the parent disk
+ * @blk_desc block device
+ * @if_typename interface type
+ * @diskid device number
+ * @pdevname device name
+ * @return number of partitions created
+ */
+int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
+ const char *if_typename, int diskid,
+ const char *pdevname)
{
int disks = 0;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
disk_partition_t info;
int part;
+ struct efi_device_path *dp = NULL;
+ efi_status_t ret;
+ struct efi_handler *handler;
+
+ /* Get the device path of the parent */
+ ret = efi_search_protocol(parent, &efi_guid_device_path, &handler);
+ if (ret == EFI_SUCCESS)
+ dp = handler->protocol_interface;
/* Add devices for each partition */
for (part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
continue;
snprintf(devname, sizeof(devname), "%s:%d", pdevname,
part);
- efi_disk_add_dev(devname, if_typename, desc, diskid,
+ efi_disk_add_dev(parent, dp, if_typename, desc, diskid,
info.start, part);
disks++;
}
*/
int efi_disk_register(void)
{
+ struct efi_disk_obj *disk;
int disks = 0;
#ifdef CONFIG_BLK
struct udevice *dev;
dev;
uclass_next_device_check(&dev)) {
struct blk_desc *desc = dev_get_uclass_platdata(dev);
- const char *if_typename = dev->driver->name;
+ const char *if_typename = blk_get_if_type_name(desc->if_type);
printf("Scanning disk %s...\n", dev->name);
/* Add block device for the full device */
- efi_disk_add_dev(dev->name, if_typename, desc,
- desc->devnum, 0, 0);
-
+ disk = efi_disk_add_dev(NULL, NULL, if_typename,
+ desc, desc->devnum, 0, 0);
+ if (!disk)
+ return -ENOMEM;
disks++;
/* Partitions show up as block devices in EFI */
- disks += efi_disk_create_partitions(desc, if_typename,
- desc->devnum, dev->name);
+ disks += efi_disk_create_partitions(
+ disk->parent.handle, desc, if_typename,
+ desc->devnum, dev->name);
}
#else
int i, if_type;
if_typename, i);
/* Add block device for the full device */
- efi_disk_add_dev(devname, if_typename, desc, i, 0, 0);
+ disk = efi_disk_add_dev(NULL, NULL, if_typename, desc,
+ i, 0, 0);
+ if (!disk)
+ return -ENOMEM;
disks++;
/* Partitions show up as block devices in EFI */
- disks += efi_disk_create_partitions(desc, if_typename,
- i, devname);
+ disks += efi_disk_create_partitions(
+ disk->parent.handle, desc,
+ if_typename, i, devname);
}
}
#endif
}
/*
+ * Determine the memory types to be used for code and data.
+ *
+ * @loaded_image_info image descriptor
+ * @image_type field Subsystem of the optional header for
+ * Windows specific field
+ */
+static void efi_set_code_and_data_type(
+ struct efi_loaded_image *loaded_image_info,
+ uint16_t image_type)
+{
+ switch (image_type) {
+ case IMAGE_SUBSYSTEM_EFI_APPLICATION:
+ loaded_image_info->image_code_type = EFI_LOADER_CODE;
+ loaded_image_info->image_data_type = EFI_LOADER_DATA;
+ break;
+ case IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER:
+ loaded_image_info->image_code_type = EFI_BOOT_SERVICES_CODE;
+ loaded_image_info->image_data_type = EFI_BOOT_SERVICES_DATA;
+ break;
+ case IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER:
+ case IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER:
+ loaded_image_info->image_code_type = EFI_RUNTIME_SERVICES_CODE;
+ loaded_image_info->image_data_type = EFI_RUNTIME_SERVICES_DATA;
+ break;
+ default:
+ printf("%s: invalid image type: %u\n", __func__, image_type);
+ /* Let's assume it is an application */
+ loaded_image_info->image_code_type = EFI_LOADER_CODE;
+ loaded_image_info->image_data_type = EFI_LOADER_DATA;
+ break;
+ }
+}
+
+/*
* This function loads all sections from a PE binary into a newly reserved
* piece of memory. On successful load it then returns the entry point for
* the binary. Otherwise NULL.
unsigned long virt_size = 0;
bool can_run_nt64 = true;
bool can_run_nt32 = true;
- uint16_t image_type;
#if defined(CONFIG_ARM64)
can_run_nt32 = false;
IMAGE_NT_HEADERS64 *nt64 = (void *)nt;
IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader;
image_size = opt->SizeOfImage;
- efi_reloc = efi_alloc(virt_size, EFI_LOADER_DATA);
+ efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ efi_reloc = efi_alloc(virt_size,
+ loaded_image_info->image_code_type);
if (!efi_reloc) {
- printf("%s: Could not allocate %ld bytes\n",
- __func__, virt_size);
+ printf("%s: Could not allocate %lu bytes\n",
+ __func__, virt_size);
return NULL;
}
entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
- image_type = opt->Subsystem;
} else if (can_run_nt32 &&
(nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader;
image_size = opt->SizeOfImage;
- efi_reloc = efi_alloc(virt_size, EFI_LOADER_DATA);
+ efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ efi_reloc = efi_alloc(virt_size,
+ loaded_image_info->image_code_type);
if (!efi_reloc) {
- printf("%s: Could not allocate %ld bytes\n",
- __func__, virt_size);
+ printf("%s: Could not allocate %lu bytes\n",
+ __func__, virt_size);
return NULL;
}
entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
- image_type = opt->Subsystem;
} else {
printf("%s: Invalid optional header magic %x\n", __func__,
nt->OptionalHeader.Magic);
return NULL;
}
- switch (image_type) {
- case IMAGE_SUBSYSTEM_EFI_APPLICATION:
- loaded_image_info->image_code_type = EFI_LOADER_CODE;
- loaded_image_info->image_data_type = EFI_LOADER_DATA;
- break;
- case IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER:
- loaded_image_info->image_code_type = EFI_BOOT_SERVICES_CODE;
- loaded_image_info->image_data_type = EFI_BOOT_SERVICES_DATA;
- break;
- case IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER:
- case IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER:
- loaded_image_info->image_code_type = EFI_RUNTIME_SERVICES_CODE;
- loaded_image_info->image_data_type = EFI_RUNTIME_SERVICES_DATA;
- break;
- default:
- printf("%s: invalid image type: %u\n", __func__, image_type);
- break;
- }
-
/* Load sections into RAM */
for (i = num_sections - 1; i >= 0; i--) {
IMAGE_SECTION_HEADER *sec = §ions[i];
return 0;
}
+/*
+ * Allocate memory pages.
+ *
+ * @type type of allocation to be performed
+ * @memory_type usage type of the allocated memory
+ * @pages number of pages to be allocated
+ * @memory allocated memory
+ * @return status code
+ */
efi_status_t efi_allocate_pages(int type, int memory_type,
efi_uintn_t pages, uint64_t *memory)
{
return NULL;
}
+/*
+ * Free memory pages.
+ *
+ * @memory start of the memory area to be freed
+ * @pages number of pages to be freed
+ * @return status code
+ */
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
uint64_t r = 0;
return EFI_NOT_FOUND;
}
-efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size,
- void **buffer)
+/*
+ * Allocate memory from pool.
+ *
+ * @pool_type type of the pool from which memory is to be allocated
+ * @size number of bytes to be allocated
+ * @buffer allocated memory
+ * @return status code
+ */
+efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer)
{
efi_status_t r;
efi_physical_addr_t t;
return r;
}
+/*
+ * Free memory from pool.
+ *
+ * @buffer start of memory to be freed
+ * @return status code
+ */
efi_status_t efi_free_pool(void *buffer)
{
efi_status_t r;
return r;
}
+/*
+ * Get map describing memory usage.
+ *
+ * @memory_map_size on entry the size, in bytes, of the memory map buffer,
+ * on exit the size of the copied memory map
+ * @memory_map buffer to which the memory map is written
+ * @map_key key for the memory map
+ * @descriptor_size size of an individual memory descriptor
+ * @descriptor_version version number of the memory descriptor structure
+ * @return status code
+ */
efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
struct efi_mem_desc *memory_map,
efi_uintn_t *map_key,
#include <efi_api.h>
static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
+static const efi_guid_t fdt_guid = EFI_FDT_GUID;
+static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
+
+static int hw_memcmp(const void *buf1, const void *buf2, size_t length)
+{
+ const u8 *pos1 = buf1;
+ const u8 *pos2 = buf2;
+
+ for (; length; --length) {
+ if (*pos1 != *pos2)
+ return *pos1 - *pos2;
+ ++pos1;
+ ++pos2;
+ }
+ return 0;
+}
/*
* Entry point of the EFI application.
struct efi_boot_services *boottime = systable->boottime;
struct efi_loaded_image *loaded_image;
efi_status_t ret;
+ efi_uintn_t i;
con_out->output_string(con_out, L"Hello, world!\n");
L"Cannot open loaded image protocol\n");
goto out;
}
+ /* Find configuration tables */
+ for (i = 0; i < systable->nr_tables; ++i) {
+ if (!hw_memcmp(&systable->tables[i].guid, &fdt_guid,
+ sizeof(efi_guid_t)))
+ con_out->output_string(con_out, L"Have device tree\n");
+ if (!hw_memcmp(&systable->tables[i].guid, &smbios_guid,
+ sizeof(efi_guid_t)))
+ con_out->output_string(con_out, L"Have SMBIOS table\n");
+ }
/* Output the load options */
con_out->output_string(con_out, L"Load options: ");
if (loaded_image->load_options_size && loaded_image->load_options)
--- /dev/null
+efi_miniapp_file_image.h
+*.efi
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+CFLAGS_efi_selftest_miniapp.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_efi_selftest_miniapp.o := $(CFLAGS_NON_EFI) -Os
+
obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \
efi_selftest.o \
+efi_selftest_controllers.o \
efi_selftest_console.o \
efi_selftest_devicepath.o \
efi_selftest_events.o \
efi_selftest_tpl.o \
efi_selftest_util.o \
efi_selftest_watchdog.o
+
+ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
+obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest_block_device.o
+endif
+
+# TODO: As of v2018.01 the relocation code for the EFI application cannot
+# be built on x86_64.
+ifeq ($(CONFIG_X86_64),)
+
+ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST),)
+
+obj-y += \
+efi_selftest_startimage_exit.o \
+efi_selftest_startimage_return.o
+
+targets += \
+efi_miniapp_file_image_exit.h \
+efi_miniapp_file_image_return.h \
+efi_selftest_miniapp_exit.efi \
+efi_selftest_miniapp_return.efi
+
+$(obj)/efi_miniapp_file_image_exit.h: $(obj)/efi_selftest_miniapp_exit.efi
+ $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exit.efi > \
+ $(obj)/efi_miniapp_file_image_exit.h
+
+$(obj)/efi_miniapp_file_image_return.h: $(obj)/efi_selftest_miniapp_return.efi
+ $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_return.efi > \
+ $(obj)/efi_miniapp_file_image_return.h
+
+$(obj)/efi_selftest_startimage_exit.o: $(obj)/efi_miniapp_file_image_exit.h
+
+$(obj)/efi_selftest_startimage_return.o: $(obj)/efi_miniapp_file_image_return.h
+
+endif
+
+endif
efi_st_error("ExitBootServices did not return EFI_SUCCESS\n");
return;
}
- efi_st_printf("\nBoot services terminated\n");
+ efi_st_printc(EFI_WHITE, "\nBoot services terminated\n");
}
/*
if (!test->setup)
return EFI_ST_SUCCESS;
- efi_st_printf("\nSetting up '%s'\n", test->name);
+ efi_st_printc(EFI_LIGHTBLUE, "\nSetting up '%s'\n", test->name);
ret = test->setup(handle, systable);
if (ret != EFI_ST_SUCCESS) {
efi_st_error("Setting up '%s' failed\n", test->name);
++*failures;
} else {
- efi_st_printf("Setting up '%s' succeeded\n", test->name);
+ efi_st_printc(EFI_LIGHTGREEN,
+ "Setting up '%s' succeeded\n", test->name);
}
return ret;
}
if (!test->execute)
return EFI_ST_SUCCESS;
- efi_st_printf("\nExecuting '%s'\n", test->name);
+ efi_st_printc(EFI_LIGHTBLUE, "\nExecuting '%s'\n", test->name);
ret = test->execute();
if (ret != EFI_ST_SUCCESS) {
efi_st_error("Executing '%s' failed\n", test->name);
++*failures;
} else {
- efi_st_printf("Executing '%s' succeeded\n", test->name);
+ efi_st_printc(EFI_LIGHTGREEN,
+ "Executing '%s' succeeded\n", test->name);
}
return ret;
}
if (!test->teardown)
return EFI_ST_SUCCESS;
- efi_st_printf("\nTearing down '%s'\n", test->name);
+ efi_st_printc(EFI_LIGHTBLUE, "\nTearing down '%s'\n", test->name);
ret = test->teardown();
if (ret != EFI_ST_SUCCESS) {
efi_st_error("Tearing down '%s' failed\n", test->name);
++*failures;
} else {
- efi_st_printf("Tearing down '%s' succeeded\n", test->name);
+ efi_st_printc(EFI_LIGHTGREEN,
+ "Tearing down '%s' succeeded\n", test->name);
}
return ret;
}
}
}
- efi_st_printf("\nTesting EFI API implementation\n");
+ efi_st_printc(EFI_WHITE, "\nTesting EFI API implementation\n");
if (testname)
- efi_st_printf("\nSelected test: '%ps'\n", testname);
+ efi_st_printc(EFI_WHITE, "\nSelected test: '%ps'\n", testname);
else
- efi_st_printf("\nNumber of tests to execute: %u\n",
+ efi_st_printc(EFI_WHITE, "\nNumber of tests to execute: %u\n",
ll_entry_count(struct efi_unit_test,
efi_unit_test));
&failures);
/* Give feedback */
- efi_st_printf("\nSummary: %u failures\n\n", failures);
+ efi_st_printc(EFI_WHITE, "\nSummary: %u failures\n\n", failures);
/* Reset system */
efi_st_printf("Preparing for reset. Press any key.\n");
--- /dev/null
+/*
+ * efi_selftest_block
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the driver for block IO devices.
+ * A disk image is created in memory.
+ * A handle is created for the new block IO device.
+ * The block I/O protocol is installed on the handle.
+ * ConnectController is used to setup partitions and to install the simple
+ * file protocol.
+ * A known file is read from the file system and verified.
+ */
+
+#include <efi_selftest.h>
+#include "efi_selftest_disk_image.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+static struct efi_boot_services *boottime;
+
+static const efi_guid_t block_io_protocol_guid = BLOCK_IO_GUID;
+static const efi_guid_t guid_device_path = DEVICE_PATH_GUID;
+static const efi_guid_t guid_simple_file_system_protocol =
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
+static efi_guid_t guid_vendor =
+ EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
+ 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xb7, 0xb8);
+
+static struct efi_device_path *dp;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed disk image */
+struct compressed_disk_image {
+ size_t length;
+ struct line lines[];
+};
+
+static const struct compressed_disk_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed disk image */
+static u8 *image;
+
+/*
+ * Reset service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @return status code
+ */
+static efi_status_t EFIAPI reset(
+ struct efi_block_io *this,
+ char extended_verification)
+{
+ return EFI_SUCCESS;
+}
+
+/*
+ * Read service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @media_id media id
+ * @lba start of the read in logical blocks
+ * @buffer_size number of bytes to read
+ * @buffer target buffer
+ * @return status code
+ */
+static efi_status_t EFIAPI read_blocks(
+ struct efi_block_io *this, u32 media_id, u64 lba,
+ efi_uintn_t buffer_size, void *buffer)
+{
+ u8 *start;
+
+ if ((lba << LB_BLOCK_SIZE) + buffer_size > img.length)
+ return EFI_INVALID_PARAMETER;
+ start = image + (lba << LB_BLOCK_SIZE);
+
+ boottime->copy_mem(buffer, start, buffer_size);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Write service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @media_id media id
+ * @lba start of the write in logical blocks
+ * @buffer_size number of bytes to read
+ * @buffer source buffer
+ * @return status code
+ */
+static efi_status_t EFIAPI write_blocks(
+ struct efi_block_io *this, u32 media_id, u64 lba,
+ efi_uintn_t buffer_size, void *buffer)
+{
+ u8 *start;
+
+ if ((lba << LB_BLOCK_SIZE) + buffer_size > img.length)
+ return EFI_INVALID_PARAMETER;
+ start = image + (lba << LB_BLOCK_SIZE);
+
+ boottime->copy_mem(start, buffer, buffer_size);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Flush service of the block IO protocol.
+ *
+ * @this block IO protocol
+ * @return status code
+ */
+static efi_status_t EFIAPI flush_blocks(struct efi_block_io *this)
+{
+ return EFI_SUCCESS;
+}
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+static struct efi_block_io_media media;
+
+static struct efi_block_io block_io = {
+ .media = &media,
+ .reset = reset,
+ .read_blocks = read_blocks,
+ .write_blocks = write_blocks,
+ .flush_blocks = flush_blocks,
+};
+
+/* Handle for the block IO device */
+static efi_handle_t disk_handle;
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ struct efi_device_path_vendor vendor_node;
+ struct efi_device_path end_node;
+
+ boottime = systable->boottime;
+
+ decompress(&image);
+
+ block_io.media->block_size = 1 << LB_BLOCK_SIZE;
+ block_io.media->last_block = img.length >> LB_BLOCK_SIZE;
+
+ ret = boottime->install_protocol_interface(
+ &disk_handle, &block_io_protocol_guid,
+ EFI_NATIVE_INTERFACE, &block_io);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to install block I/O protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ sizeof(struct efi_device_path_vendor) +
+ sizeof(struct efi_device_path),
+ (void **)&dp);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return EFI_ST_FAILURE;
+ }
+ vendor_node.dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+ vendor_node.dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+ vendor_node.dp.length = sizeof(struct efi_device_path_vendor);
+
+ boottime->copy_mem(&vendor_node.guid, &guid_vendor,
+ sizeof(efi_guid_t));
+ boottime->copy_mem(dp, &vendor_node,
+ sizeof(struct efi_device_path_vendor));
+ end_node.type = DEVICE_PATH_TYPE_END;
+ end_node.sub_type = DEVICE_PATH_SUB_TYPE_END;
+ end_node.length = sizeof(struct efi_device_path);
+
+ boottime->copy_mem((char *)dp + sizeof(struct efi_device_path_vendor),
+ &end_node, sizeof(struct efi_device_path));
+ ret = boottime->install_protocol_interface(&disk_handle,
+ &guid_device_path,
+ EFI_NATIVE_INTERFACE,
+ dp);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (disk_handle) {
+ r = boottime->uninstall_protocol_interface(disk_handle,
+ &guid_device_path,
+ dp);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Uninstall device path failed\n");
+ return EFI_ST_FAILURE;
+ }
+ r = boottime->uninstall_protocol_interface(
+ disk_handle, &block_io_protocol_guid,
+ &block_io);
+ if (r != EFI_SUCCESS) {
+ efi_st_todo(
+ "Failed to uninstall block I/O protocol\n");
+ return EFI_ST_SUCCESS;
+ }
+ }
+
+ if (image) {
+ r = efi_free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return r;
+}
+
+/*
+ * Get length of device path without end tag.
+ *
+ * @dp device path
+ * @return length of device path in bytes
+ */
+static efi_uintn_t dp_size(struct efi_device_path *dp)
+{
+ struct efi_device_path *pos = dp;
+
+ while (pos->type != DEVICE_PATH_TYPE_END)
+ pos = (struct efi_device_path *)((char *)pos + pos->length);
+ return (char *)pos - (char *)dp;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_uintn_t no_handles, i, len;
+ efi_handle_t *handles;
+ efi_handle_t handle_partition = NULL;
+ struct efi_device_path *dp_partition;
+ struct efi_simple_file_system_protocol *file_system;
+ struct efi_file_handle *root, *file;
+ u64 buf_size;
+ char buf[16] __aligned(ARCH_DMA_MINALIGN);
+
+ ret = boottime->connect_controller(disk_handle, NULL, NULL, 1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to connect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->locate_handle_buffer(
+ BY_PROTOCOL, &guid_device_path, NULL,
+ &no_handles, &handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to locate handles\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dp_size(dp);
+ for (i = 0; i < no_handles; ++i) {
+ ret = boottime->open_protocol(handles[i], &guid_device_path,
+ (void **)&dp_partition,
+ NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open device path protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ if (len >= dp_size(dp_partition))
+ continue;
+ if (efi_st_memcmp(dp, dp_partition, len))
+ continue;
+ handle_partition = handles[i];
+ break;
+ }
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free pool memory\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!handle_partition) {
+ efi_st_error("Partition handle not found\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol(handle_partition,
+ &guid_simple_file_system_protocol,
+ (void **)&file_system, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open simple file system protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = file_system->open_volume(file_system, &root);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open volume\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = root->open(root, &file, (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
+ 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open file\n");
+ return EFI_ST_FAILURE;
+ }
+ buf_size = sizeof(buf) - 1;
+ ret = file->read(file, &buf_size, buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to read file\n");
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_memcmp(buf, "Hello world!", 12)) {
+ efi_st_error("Unexpected file content\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = file->close(file);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close file\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = root->close(root);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close volume\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(blkdev) = {
+ .name = "block device",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
}
/*
- * Print a formatted string to the EFI console
+ * Print a colored formatted string to the EFI console
*
- * @fmt: format string
- * @...: optional arguments
+ * @color color, see constants in efi_api.h, use -1 for no color
+ * @fmt format string
+ * @... optional arguments
*/
-void efi_st_printf(const char *fmt, ...)
+void efi_st_printc(int color, const char *fmt, ...)
{
va_list args;
u16 buf[160];
const char *c;
u16 *pos = buf;
const char *s;
- const u16 *u;
+ u16 *u;
va_start(args, fmt);
+ if (color >= 0)
+ con_out->set_attribute(con_out, (unsigned long)color);
c = fmt;
for (; *c; ++c) {
switch (*c) {
/* u16 string */
case 's':
u = va_arg(args, u16*);
- /* Ensure string fits into buffer */
- for (; *u && pos < buf + 120; ++u)
- *pos++ = *u;
+ if (pos > buf) {
+ *pos = 0;
+ con_out->output_string(con_out,
+ buf);
+ }
+ con_out->output_string(con_out, u);
+ pos = buf;
break;
default:
--c;
va_end(args);
*pos = 0;
con_out->output_string(con_out, buf);
+ if (color >= 0)
+ con_out->set_attribute(con_out, EFI_LIGHTGRAY);
}
/*
--- /dev/null
+/*
+ * efi_selftest_controllers
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This unit test checks the following protocol services:
+ * ConnectController, DisconnectController,
+ * InstallProtocol, UninstallProtocol,
+ * OpenProtocol, CloseProtcol, OpenProtocolInformation
+ */
+
+#include <efi_selftest.h>
+
+#define NUMBER_OF_CHILD_CONTROLLERS 4
+
+static struct efi_boot_services *boottime;
+const efi_guid_t guid_driver_binding_protocol =
+ EFI_DRIVER_BINDING_PROTOCOL_GUID;
+static efi_guid_t guid_controller =
+ EFI_GUID(0xe6ab1d96, 0x6bff, 0xdb42,
+ 0xaa, 0x05, 0xc8, 0x1f, 0x7f, 0x45, 0x26, 0x34);
+static efi_guid_t guid_child_controller =
+ EFI_GUID(0x1d41f6f5, 0x2c41, 0xddfb,
+ 0xe2, 0x9b, 0xb8, 0x0e, 0x2e, 0xe8, 0x3a, 0x85);
+static efi_handle_t handle_controller;
+static efi_handle_t handle_child_controller[NUMBER_OF_CHILD_CONTROLLERS];
+static efi_handle_t handle_driver;
+
+/*
+ * Count child controllers
+ *
+ * @handle handle on which child controllers are installed
+ * @protocol protocol for which the child controlles where installed
+ * @count number of child controllers
+ * @return status code
+ */
+static efi_status_t count_child_controllers(efi_handle_t handle,
+ efi_guid_t *protocol,
+ efi_uintn_t *count)
+{
+ efi_status_t ret;
+ efi_uintn_t entry_count;
+ struct efi_open_protocol_info_entry *entry_buffer;
+
+ *count = 0;
+ ret = boottime->open_protocol_information(handle, protocol,
+ &entry_buffer, &entry_count);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (!entry_count)
+ return EFI_SUCCESS;
+ while (entry_count) {
+ if (entry_buffer[--entry_count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
+ ++*count;
+ }
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS)
+ efi_st_error("Cannot free buffer\n");
+ return ret;
+}
+
+/*
+ * Check if the driver supports the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI supported(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ efi_status_t ret;
+ void *interface;
+
+ ret = boottime->open_protocol(
+ controller_handle, &guid_controller,
+ &interface, handle_driver,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ return ret;
+ case EFI_SUCCESS:
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+ ret = boottime->close_protocol(
+ controller_handle, &guid_controller,
+ handle_driver, controller_handle);
+ if (ret != EFI_SUCCESS)
+ ret = EFI_UNSUPPORTED;
+ return ret;
+}
+
+/*
+ * Create child controllers and attach driver.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * @return status code
+ */
+static efi_status_t EFIAPI start(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_device_path)
+{
+ size_t i;
+ efi_status_t ret;
+ void *interface;
+
+ /* Attach driver to controller */
+ ret = boottime->open_protocol(
+ controller_handle, &guid_controller,
+ &interface, handle_driver,
+ controller_handle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ switch (ret) {
+ case EFI_ACCESS_DENIED:
+ case EFI_ALREADY_STARTED:
+ return ret;
+ case EFI_SUCCESS:
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ /* Create child controllers */
+ for (i = 0; i < NUMBER_OF_CHILD_CONTROLLERS; ++i) {
+ ret = boottime->install_protocol_interface(
+ &handle_child_controller[i], &guid_child_controller,
+ EFI_NATIVE_INTERFACE, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol(
+ controller_handle, &guid_controller,
+ &interface, handle_child_controller[i],
+ handle_child_controller[i],
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return ret;
+}
+
+/*
+ * Remove a single child controller from the parent controller.
+ *
+ * @controller_handle parent controller
+ * @child_handle child controller
+ * @return status code
+ */
+static efi_status_t disconnect_child(efi_handle_t controller_handle,
+ efi_handle_t child_handle)
+{
+ efi_status_t ret;
+
+ ret = boottime->close_protocol(
+ controller_handle, &guid_controller,
+ child_handle, child_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot close protocol\n");
+ return ret;
+ }
+ ret = boottime->uninstall_protocol_interface(
+ child_handle, &guid_child_controller, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot uninstall protocol interface\n");
+ return ret;
+ }
+ return ret;
+}
+
+/*
+ * Remove child controllers and disconnect the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @number_of_children number of child controllers to remove
+ * @child_handle_buffer handles of the child controllers to remove
+ * @return status code
+ */
+static efi_status_t EFIAPI stop(
+ struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ size_t number_of_children,
+ efi_handle_t *child_handle_buffer)
+{
+ efi_status_t ret;
+ efi_uintn_t count;
+ struct efi_open_protocol_info_entry *entry_buffer;
+
+ /* Destroy provided child controllers */
+ if (number_of_children) {
+ efi_uintn_t i;
+
+ for (i = 0; i < number_of_children; ++i) {
+ ret = disconnect_child(controller_handle,
+ child_handle_buffer[i]);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ return EFI_SUCCESS;
+ }
+
+ /* Destroy all children */
+ ret = boottime->open_protocol_information(
+ controller_handle, &guid_controller,
+ &entry_buffer, &count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocolInformation failed\n");
+ return ret;
+ }
+ while (count) {
+ if (entry_buffer[--count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {
+ ret = disconnect_child(
+ controller_handle,
+ entry_buffer[count].agent_handle);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ }
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS)
+ efi_st_error("Cannot free buffer\n");
+
+ /* Detach driver from controller */
+ ret = boottime->close_protocol(
+ controller_handle, &guid_controller,
+ handle_driver, controller_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot close protocol\n");
+ return ret;
+ }
+ return EFI_SUCCESS;
+}
+
+/* Driver binding protocol interface */
+static struct efi_driver_binding_protocol binding_interface = {
+ supported,
+ start,
+ stop,
+ 0xffffffff,
+ NULL,
+ NULL,
+ };
+
+/*
+ * Setup unit test.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ /* Create controller handle */
+ ret = boottime->install_protocol_interface(
+ &handle_controller, &guid_controller,
+ EFI_NATIVE_INTERFACE, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Create driver handle */
+ ret = boottime->install_protocol_interface(
+ &handle_driver, &guid_driver_binding_protocol,
+ EFI_NATIVE_INTERFACE, &binding_interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * The number of child controllers is checked after each of the following
+ * actions:
+ *
+ * Connect a controller to a driver.
+ * Disconnect and destroy a child controller.
+ * Disconnect and destroy the remaining child controllers.
+ *
+ * Connect a controller to a driver.
+ * Uninstall the driver protocol from the controller.
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_uintn_t count;
+
+ /* Connect controller to driver */
+ ret = boottime->connect_controller(handle_controller, NULL, NULL, 1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to connect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS) {
+ efi_st_error("Number of children %u != %u\n",
+ (unsigned int)count, NUMBER_OF_CHILD_CONTROLLERS);
+ }
+ /* Destroy second child controller */
+ ret = boottime->disconnect_controller(handle_controller,
+ handle_driver,
+ handle_child_controller[1]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to disconnect child controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS - 1) {
+ efi_st_error("Destroying single child controller failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Destroy remaining child controllers and disconnect controller */
+ ret = boottime->disconnect_controller(handle_controller, NULL, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to disconnect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count) {
+ efi_st_error("Destroying child controllers failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Connect controller to driver */
+ ret = boottime->connect_controller(handle_controller, NULL, NULL, 1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to connect controller\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret != EFI_SUCCESS || count != NUMBER_OF_CHILD_CONTROLLERS) {
+ efi_st_error("Number of children %u != %u\n",
+ (unsigned int)count, NUMBER_OF_CHILD_CONTROLLERS);
+ }
+ /* Uninstall controller protocol */
+ ret = boottime->uninstall_protocol_interface(handle_controller,
+ &guid_controller, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to uninstall protocols\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check number of child controllers */
+ ret = count_child_controllers(handle_controller, &guid_controller,
+ &count);
+ if (ret == EFI_SUCCESS)
+ efi_st_error("Uninstall failed\n");
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(controllers) = {
+ .name = "controllers",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
{
efi_status_t ret;
- ret = boottime->uninstall_protocol_interface(&handle1,
+ ret = boottime->uninstall_protocol_interface(handle1,
&guid_device_path,
dp1);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle1,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle1,
&guid_protocol,
&interface);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle2,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle2,
&guid_device_path,
dp2);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle2,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle2,
&guid_protocol,
&interface);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
- ret = boottime->uninstall_protocol_interface(&handle3,
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface(handle3,
&guid_device_path,
dp3);
- if (ret != EFI_SUCCESS)
- efi_st_todo("UninstallProtocolInterface failed\n");
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
if (dp1) {
ret = boottime->free_pool(dp1);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
return EFI_ST_FAILURE;
}
- ret = boottime->close_protocol(handles[i], &guid_device_path,
- NULL, NULL);
- if (ret != EFI_SUCCESS)
- efi_st_todo("Cannot close device path protocol.\n");
+ /*
+ * CloseProtocol cannot be called without agent handle.
+ * There is no need to close the device path protocol.
+ */
}
ret = boottime->free_pool(handles);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("\n");
/* Test ConvertDevicePathToText */
string = device_path_to_text->convert_device_path_to_text(
efi_st_error("ConvertDevicePathToText failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("dp2: %ps\n", string);
if (efi_st_strcmp_16_8(
string,
"/VenHw(dbca4c98-6cb0-694d-0872-819c650cbbb1)/VenHw(dbca4c98-6cb0-694d-0872-819c650cbba2)")
) {
+ efi_st_printf("dp2: %ps\n", string);
efi_st_error("Incorrect text from ConvertDevicePathToText\n");
return EFI_ST_FAILURE;
}
-
ret = boottime->free_pool(string);
if (ret != EFI_SUCCESS) {
efi_st_error("FreePool failed\n");
efi_st_error("ConvertDeviceNodeToText failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("dp_node: %ps\n", string);
- ret = boottime->free_pool(string);
- if (ret != EFI_SUCCESS) {
- efi_st_error("FreePool failed\n");
- return EFI_ST_FAILURE;
- }
if (efi_st_strcmp_16_8(string, "u-boot")) {
+ efi_st_printf("dp_node: %ps\n", string);
efi_st_error(
"Incorrect conversion by ConvertDeviceNodeToText\n");
return EFI_ST_FAILURE;
}
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
/* Test LocateDevicePath */
remaining_dp = (struct efi_device_path *)dp3;
efi_st_error("ConvertDevicePathToText failed\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("remaining device path: %ps\n", string);
if (efi_st_strcmp_16_8(string,
"/VenHw(dbca4c98-6cb0-694d-0872-819c650cbbc3)")
) {
+ efi_st_printf("remaining device path: %ps\n", string);
efi_st_error("LocateDevicePath: wrong remaining device path\n");
return EFI_ST_FAILURE;
}
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
return EFI_ST_SUCCESS;
}
--- /dev/null
+/*
+ * Non-zero 8 byte strings of a disk image
+ *
+ * Generated with tools/file2include
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define EFI_ST_DISK_IMG { 0x00010000, { \
+ {0x000001b8, "\x94\x37\x69\xfc\x00\x00\x00\x00"}, /* .7i..... */ \
+ {0x000001c0, "\x02\x00\x83\x02\x02\x00\x01\x00"}, /* ........ */ \
+ {0x000001c8, "\x00\x00\x7f\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x000001f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
+ {0x00000200, "\xeb\x3c\x90\x6d\x6b\x66\x73\x2e"}, /* .<.mkfs. */ \
+ {0x00000208, "\x66\x61\x74\x00\x02\x04\x01\x00"}, /* fat..... */ \
+ {0x00000210, "\x02\x00\x02\x7f\x00\xf8\x01\x00"}, /* ........ */ \
+ {0x00000218, "\x20\x00\x40\x00\x00\x00\x00\x00"}, /* .@..... */ \
+ {0x00000220, "\x00\x00\x00\x00\x80\x00\x29\x86"}, /* ......). */ \
+ {0x00000228, "\xe8\x82\x80\x4e\x4f\x20\x4e\x41"}, /* ...NO NA */ \
+ {0x00000230, "\x4d\x45\x20\x20\x20\x20\x46\x41"}, /* ME FA */ \
+ {0x00000238, "\x54\x31\x32\x20\x20\x20\x0e\x1f"}, /* T12 .. */ \
+ {0x00000240, "\xbe\x5b\x7c\xac\x22\xc0\x74\x0b"}, /* .[|.".t. */ \
+ {0x00000248, "\x56\xb4\x0e\xbb\x07\x00\xcd\x10"}, /* V....... */ \
+ {0x00000250, "\x5e\xeb\xf0\x32\xe4\xcd\x16\xcd"}, /* ^..2.... */ \
+ {0x00000258, "\x19\xeb\xfe\x54\x68\x69\x73\x20"}, /* ...This */ \
+ {0x00000260, "\x69\x73\x20\x6e\x6f\x74\x20\x61"}, /* is not a */ \
+ {0x00000268, "\x20\x62\x6f\x6f\x74\x61\x62\x6c"}, /* bootabl */ \
+ {0x00000270, "\x65\x20\x64\x69\x73\x6b\x2e\x20"}, /* e disk. */ \
+ {0x00000278, "\x20\x50\x6c\x65\x61\x73\x65\x20"}, /* Please */ \
+ {0x00000280, "\x69\x6e\x73\x65\x72\x74\x20\x61"}, /* insert a */ \
+ {0x00000288, "\x20\x62\x6f\x6f\x74\x61\x62\x6c"}, /* bootabl */ \
+ {0x00000290, "\x65\x20\x66\x6c\x6f\x70\x70\x79"}, /* e floppy */ \
+ {0x00000298, "\x20\x61\x6e\x64\x0d\x0a\x70\x72"}, /* and..pr */ \
+ {0x000002a0, "\x65\x73\x73\x20\x61\x6e\x79\x20"}, /* ess any */ \
+ {0x000002a8, "\x6b\x65\x79\x20\x74\x6f\x20\x74"}, /* key to t */ \
+ {0x000002b0, "\x72\x79\x20\x61\x67\x61\x69\x6e"}, /* ry again */ \
+ {0x000002b8, "\x20\x2e\x2e\x2e\x20\x0d\x0a\x00"}, /* ... ... */ \
+ {0x000003f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
+ {0x00000400, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \
+ {0x00000408, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000600, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \
+ {0x00000608, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \
+ {0x00000800, "\xe5\x70\x00\x00\x00\xff\xff\xff"}, /* .p...... */ \
+ {0x00000808, "\xff\xff\xff\x0f\x00\x0e\xff\xff"}, /* ........ */ \
+ {0x00000810, "\xff\xff\xff\xff\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000818, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000820, "\xe5\x2e\x00\x68\x00\x65\x00\x6c"}, /* ...h.e.l */ \
+ {0x00000828, "\x00\x6c\x00\x0f\x00\x0e\x6f\x00"}, /* .l....o. */ \
+ {0x00000830, "\x2e\x00\x74\x00\x78\x00\x74\x00"}, /* ..t.x.t. */ \
+ {0x00000838, "\x2e\x00\x00\x00\x73\x00\x77\x00"}, /* ....s.w. */ \
+ {0x00000840, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \
+ {0x00000848, "\x53\x57\x50\x20\x00\x64\xd0\x8a"}, /* SWP .d.. */ \
+ {0x00000850, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \
+ {0x00000858, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \
+ {0x00000860, "\x41\x68\x00\x65\x00\x6c\x00\x6c"}, /* Ah.e.l.l */ \
+ {0x00000868, "\x00\x6f\x00\x0f\x00\xf1\x2e\x00"}, /* .o...... */ \
+ {0x00000870, "\x74\x00\x78\x00\x74\x00\x00\x00"}, /* t.x.t... */ \
+ {0x00000878, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \
+ {0x00000880, "\x48\x45\x4c\x4c\x4f\x20\x20\x20"}, /* HELLO */ \
+ {0x00000888, "\x54\x58\x54\x20\x00\x64\xd4\x8a"}, /* TXT .d.. */ \
+ {0x00000890, "\x92\x4b\x92\x4b\x00\x00\xd4\x8a"}, /* .K.K.... */ \
+ {0x00000898, "\x92\x4b\x05\x00\x0d\x00\x00\x00"}, /* .K...... */ \
+ {0x000008a0, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \
+ {0x000008a8, "\x53\x57\x58\x20\x00\x64\xd0\x8a"}, /* SWX .d.. */ \
+ {0x000008b0, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \
+ {0x000008b8, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \
+ {0x00006000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \
+ {0x00006008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \
+ {0, NULL} } }
efi_st_error("WaitForEvent returned wrong index\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count periodic: %u\n", timer_ticks);
if (timer_ticks < 8 || timer_ticks > 12) {
+ efi_st_printf("Notification count periodic: %u\n", timer_ticks);
efi_st_error("Incorrect timing of events\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not wait for event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count single shot: %u\n", timer_ticks);
if (timer_ticks != 1) {
+ efi_st_printf("Notification count single shot: %u\n",
+ timer_ticks);
efi_st_error("Single shot timer failed\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not wait for event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count stopped timer: %u\n", timer_ticks);
if (timer_ticks != 1) {
+ efi_st_printf("Notification count stopped timer: %u\n",
+ timer_ticks);
efi_st_error("Stopped timer fired\n");
return EFI_ST_FAILURE;
}
&guid3, &interface3,
NULL);
if (ret == EFI_SUCCESS) {
- efi_st_todo("UninstallMultipleProtocolInterfaces did not catch error\n");
+ efi_st_error("UninstallMultipleProtocolInterfaces did not catch error\n");
return EFI_ST_FAILURE;
}
&guid2, &interface2,
NULL);
if (ret != EFI_SUCCESS) {
- efi_st_todo("UninstallMultipleProtocolInterfaces failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallMultipleProtocolInterfaces failed\n");
+ return EFI_ST_FAILURE;
}
/*
* Check that the protocols are really uninstalled.
return EFI_ST_FAILURE;
}
if (count != 1) {
- efi_st_todo("UninstallMultipleProtocolInterfaces failed to uninstall protocols\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallMultipleProtocolInterfaces failed to uninstall protocols\n");
+ return EFI_ST_FAILURE;
}
ret = find_in_buffer(handle1, count, buffer);
if (ret != EFI_SUCCESS) {
ret = boottime->uninstall_protocol_interface(handle1, &guid1,
&interface1);
if (ret != EFI_SUCCESS) {
- efi_st_todo("UninstallProtocolInterface failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
}
ret = boottime->handle_protocol(handle1, &guid1, (void **)&interface);
if (ret == EFI_SUCCESS) {
- efi_st_todo("UninstallProtocolInterface failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
}
ret = boottime->uninstall_protocol_interface(handle1, &guid3,
&interface1);
if (ret != EFI_SUCCESS) {
- efi_st_todo("UninstallProtocolInterface failed\n");
- /* This test is known to fail due to missing implementation */
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
}
return EFI_ST_SUCCESS;
--- /dev/null
+/*
+ * efi_selftest_miniapp_exit
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This EFI application is run by the StartImage selftest.
+ * It uses the Exit boot service to return.
+ */
+
+#include <common.h>
+#include <efi_api.h>
+
+/*
+ * Entry point of the EFI application.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ * @return status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systable)
+{
+ struct efi_simple_text_output_protocol *con_out = systable->con_out;
+
+ con_out->output_string(con_out, L"EFI application calling Exit\n");
+
+ /* The return value is checked by the calling test */
+ systable->boottime->exit(handle, EFI_UNSUPPORTED, 0, NULL);
+
+ /*
+ * This statement should not be reached.
+ * To enable testing use a different return value.
+ */
+ return EFI_SUCCESS;
+}
--- /dev/null
+/*
+ * efi_selftest_miniapp_return
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This EFI application is run by the StartImage selftest.
+ * It returns directly without calling the Exit boot service.
+ */
+
+#include <common.h>
+#include <efi_api.h>
+
+/*
+ * Entry point of the EFI application.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ * @return status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systable)
+{
+ struct efi_simple_text_output_protocol *con_out = systable->con_out;
+
+ con_out->output_string(con_out,
+ L"EFI application returning w/o calling Exit\n");
+
+ /* The return value is checked by the calling test */
+ return EFI_INCOMPATIBLE_VERSION;
+}
--- /dev/null
+/*
+ * efi_selftest_start_image
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the StartImage boot service.
+ * The efi_selftest_miniapp_exit.efi application is loaded into memory
+ * and started.
+ */
+
+#include <efi_selftest.h>
+/* Include containing the miniapp.efi application */
+#include "efi_miniapp_file_image_exit.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+static efi_handle_t image_handle;
+static struct efi_boot_services *boottime;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed file image */
+static u8 *image;
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ image_handle = handle;
+ boottime = systable->boottime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (image) {
+ r = efi_free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return r;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Load and start the application image.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+
+ ret = boottime->load_image(false, image_handle, NULL, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->start_image(handle, NULL, NULL);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(startimage_exit) = {
+ .name = "start image exit",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
--- /dev/null
+/*
+ * efi_selftest_start_image
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This test checks the StartImage boot service.
+ * The efi_selftest_miniapp_return.efi application is loaded into memory
+ * and started.
+ */
+
+#include <efi_selftest.h>
+/* Include containing the miniapp.efi application */
+#include "efi_miniapp_file_image_return.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+static efi_handle_t image_handle;
+static struct efi_boot_services *boottime;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed file image */
+static u8 *image;
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ image_handle = handle;
+ boottime = systable->boottime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t r = EFI_ST_SUCCESS;
+
+ if (image) {
+ r = efi_free_pool(image);
+ if (r != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return r;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Load and start the application image.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+
+ ret = boottime->load_image(false, image_handle, NULL, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->start_image(handle, NULL, NULL);
+ if (ret != EFI_INCOMPATIBLE_VERSION) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(startimage) = {
+ .name = "start image return",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
efi_st_error("WaitForEvent returned wrong index\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count with TPL level TPL_APPLICATION: %u\n",
- notification_count);
if (notification_count < 8 || notification_count > 12) {
+ efi_st_printf(
+ "Notification count with TPL level TPL_APPLICATION: %u\n",
+ notification_count);
efi_st_error("Incorrect timing of events\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not check event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count with TPL level TPL_CALLBACK: %u\n",
- notification_count);
if (notification_count != 0) {
+ efi_st_printf(
+ "Notification count with TPL level TPL_CALLBACK: %u\n",
+ notification_count);
efi_st_error("Suppressed timer fired\n");
return EFI_ST_FAILURE;
}
efi_st_error("Could not wait for event\n");
return EFI_ST_FAILURE;
}
- efi_st_printf("Notification count with TPL level TPL_APPLICATION: %u\n",
- notification_count);
if (notification_count < 1) {
+ efi_st_printf(
+ "Notification count with TPL level TPL_APPLICATION: %u\n",
+ notification_count);
efi_st_error("Queued timer event did not fire\n");
return EFI_ST_FAILURE;
}
}
fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
- const char *prop_name, int index, int na, int ns,
- fdt_size_t *sizep, bool translate)
+ const char *prop_name, int index, int na,
+ int ns, fdt_size_t *sizep,
+ bool translate)
{
const fdt32_t *prop, *prop_end;
const fdt32_t *prop_addr, *prop_size, *prop_after_size;
}
fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
- int node, const char *prop_name, int index, fdt_size_t *sizep,
- bool translate)
+ int node, const char *prop_name,
+ int index, fdt_size_t *sizep,
+ bool translate)
{
int na, ns;
}
fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
- const char *prop_name, int index, fdt_size_t *sizep,
- bool translate)
+ const char *prop_name, int index,
+ fdt_size_t *sizep,
+ bool translate)
{
int parent;
}
fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
- const char *prop_name, fdt_size_t *sizep)
+ const char *prop_name, fdt_size_t *sizep)
{
int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
ns, sizep, false);
}
-fdt_addr_t fdtdec_get_addr(const void *blob, int node,
- const char *prop_name)
+fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
{
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
- const char *prop_name, struct fdt_pci_addr *addr)
+ const char *prop_name, struct fdt_pci_addr *addr)
{
const u32 *cell;
int len;
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[1]);
break;
- } else {
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
}
+
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
}
if (i == num) {
}
return 0;
- } else {
- ret = -EINVAL;
}
+ ret = -EINVAL;
+
fail:
debug("(not found)\n");
return ret;
end = list + len;
while (list < end) {
- char *s;
-
len = strlen(list);
if (len >= strlen("pciVVVV,DDDD")) {
- s = strstr(list, "pci");
+ char *s = strstr(list, "pci");
/*
* check if the string is something like pciVVVV,DDDD.RR
/* extract the bar number from fdt_pci_addr */
barnum = addr->phys_hi & 0xff;
- if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS))
+ if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
#endif
uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
- uint64_t default_val)
+ uint64_t default_val)
{
const uint64_t *cell64;
int length;
*/
cell = fdt_getprop(blob, node, "status", NULL);
if (cell)
- return 0 == strcmp(cell, "okay");
+ return strcmp(cell, "okay") == 0;
return 1;
}
/* Search our drivers */
for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
- if (0 == fdt_node_check_compatible(blob, node,
- compat_names[id]))
+ if (fdt_node_check_compatible(blob, node,
+ compat_names[id]) == 0)
return id;
return COMPAT_UNKNOWN;
}
-int fdtdec_next_compatible(const void *blob, int node,
- enum fdt_compat_id id)
+int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id)
{
return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
}
int fdtdec_next_compatible_subnode(const void *blob, int node,
- enum fdt_compat_id id, int *depthp)
+ enum fdt_compat_id id, int *depthp)
{
do {
node = fdt_next_node(blob, node, depthp);
return -FDT_ERR_NOTFOUND;
}
-int fdtdec_next_alias(const void *blob, const char *name,
- enum fdt_compat_id id, int *upto)
+int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id,
+ int *upto)
{
#define MAX_STR_LEN 20
char str[MAX_STR_LEN + 20];
}
int fdtdec_find_aliases_for_id(const void *blob, const char *name,
- enum fdt_compat_id id, int *node_list, int maxcount)
+ enum fdt_compat_id id, int *node_list,
+ int maxcount)
{
memset(node_list, '\0', sizeof(*node_list) * maxcount);
/* TODO: Can we tighten this code up a little? */
int fdtdec_add_aliases_for_id(const void *blob, const char *name,
- enum fdt_compat_id id, int *node_list, int maxcount)
+ enum fdt_compat_id id, int *node_list,
+ int maxcount)
{
int name_len = strlen(name);
int nodes[maxcount];
}
if (node >= 0)
debug("%s: warning: maxcount exceeded with alias '%s'\n",
- __func__, name);
+ __func__, name);
/* Now find all the aliases */
for (offset = fdt_first_property_offset(blob, alias_node);
number = simple_strtoul(path + name_len, NULL, 10);
if (number < 0 || number >= maxcount) {
debug("%s: warning: alias '%s' is out of range\n",
- __func__, path);
+ __func__, path);
continue;
}
if (!node_list[i]) {
for (; j < maxcount; j++)
if (nodes[j] &&
- fdtdec_get_is_enabled(blob, nodes[j]))
+ fdtdec_get_is_enabled(blob, nodes[j]))
break;
/* Have we run out of nodes to add? */
* @return pointer to cell, which is only valid if err == 0
*/
static const void *get_prop_check_min_len(const void *blob, int node,
- const char *prop_name, int min_len, int *err)
+ const char *prop_name, int min_len,
+ int *err)
{
const void *cell;
int len;
}
int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
- u32 *array, int count)
+ u32 *array, int count)
{
const u32 *cell;
- int i, err = 0;
+ int err = 0;
debug("%s: %s\n", __func__, prop_name);
cell = get_prop_check_min_len(blob, node, prop_name,
sizeof(u32) * count, &err);
if (!err) {
+ int i;
+
for (i = 0; i < count; i++)
array[i] = fdt32_to_cpu(cell[i]);
}
}
int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
- u8 *array, int count)
+ u8 *array, int count)
{
const u8 *cell;
int err;
}
const u8 *fdtdec_locate_byte_array(const void *blob, int node,
- const char *prop_name, int count)
+ const char *prop_name, int count)
{
const u8 *cell;
int err;
}
int fdtdec_get_config_int(const void *blob, const char *prop_name,
- int default_val)
+ int default_val)
{
int config_node;
while (ptr + na + ns <= end) {
if (i == index) {
- res->start = res->end = fdtdec_get_number(ptr, na);
+ res->start = fdtdec_get_number(ptr, na);
+ res->end = res->start;
res->end += fdtdec_get_number(&ptr[na], ns) - 1;
return 0;
}
fdt_wip.o \
fdt_strerror.o \
fdt_sw.o \
+ fdt_rw.o \
fdt_empty_tree.o \
fdt_addresses.o
# Locally modified for U-Boot.
# TODO: split out the local modifiction.
-obj-y += \
- fdt_ro.o \
- fdt_rw.o
+obj-y += fdt_ro.o
# U-Boot own file
obj-y += fdt_region.o
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
- */
-#include <libfdt_env.h>
-
-#ifndef USE_HOSTCC
-#include <fdt.h>
-#include <libfdt.h>
-#else
-#include "fdt_host.h"
-#endif
-
-#include "libfdt_internal.h"
-
-static int _fdt_blocks_misordered(const void *fdt,
- int mem_rsv_size, int struct_size)
-{
- return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
- || (fdt_off_dt_struct(fdt) <
- (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
- || (fdt_off_dt_strings(fdt) <
- (fdt_off_dt_struct(fdt) + struct_size))
- || (fdt_totalsize(fdt) <
- (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
-}
-
-static int _fdt_rw_check_header(void *fdt)
-{
- FDT_CHECK_HEADER(fdt);
-
- if (fdt_version(fdt) < 17)
- return -FDT_ERR_BADVERSION;
- if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
- fdt_size_dt_struct(fdt)))
- return -FDT_ERR_BADLAYOUT;
- if (fdt_version(fdt) > 17)
- fdt_set_version(fdt, 17);
-
- return 0;
-}
-
-#define FDT_RW_CHECK_HEADER(fdt) \
- { \
- int __err; \
- if ((__err = _fdt_rw_check_header(fdt)) != 0) \
- return __err; \
- }
-
-static inline int _fdt_data_size(void *fdt)
-{
- return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
-}
-
-static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
-{
- char *p = splicepoint;
- char *end = (char *)fdt + _fdt_data_size(fdt);
-
- if (((p + oldlen) < p) || ((p + oldlen) > end))
- return -FDT_ERR_BADOFFSET;
- if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt))
- return -FDT_ERR_BADOFFSET;
- if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
- return -FDT_ERR_NOSPACE;
- memmove(p + newlen, p + oldlen, end - p - oldlen);
- return 0;
-}
-
-static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
- int oldn, int newn)
-{
- int delta = (newn - oldn) * sizeof(*p);
- int err;
- err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
- if (err)
- return err;
- fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
- fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
- return 0;
-}
-
-static int _fdt_splice_struct(void *fdt, void *p,
- int oldlen, int newlen)
-{
- int delta = newlen - oldlen;
- int err;
-
- if ((err = _fdt_splice(fdt, p, oldlen, newlen)))
- return err;
-
- fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
- fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
- return 0;
-}
-
-static int _fdt_splice_string(void *fdt, int newlen)
-{
- void *p = (char *)fdt
- + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
- int err;
-
- if ((err = _fdt_splice(fdt, p, 0, newlen)))
- return err;
-
- fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
- return 0;
-}
-
-static int _fdt_find_add_string(void *fdt, const char *s)
-{
- char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
- const char *p;
- char *new;
- int len = strlen(s) + 1;
- int err;
-
- p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s);
- if (p)
- /* found it */
- return (p - strtab);
-
- new = strtab + fdt_size_dt_strings(fdt);
- err = _fdt_splice_string(fdt, len);
- if (err)
- return err;
-
- memcpy(new, s, len);
- return (new - strtab);
-}
-
-int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
-{
- struct fdt_reserve_entry *re;
- int err;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
- err = _fdt_splice_mem_rsv(fdt, re, 0, 1);
- if (err)
- return err;
-
- re->address = cpu_to_fdt64(address);
- re->size = cpu_to_fdt64(size);
- return 0;
-}
-
-int fdt_del_mem_rsv(void *fdt, int n)
-{
- struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
-
- FDT_RW_CHECK_HEADER(fdt);
-
- if (n >= fdt_num_mem_rsv(fdt))
- return -FDT_ERR_NOTFOUND;
-
- return _fdt_splice_mem_rsv(fdt, re, 1, 0);
-}
-
-static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
- int len, struct fdt_property **prop)
-{
- int oldlen;
- int err;
-
- *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
- if (!*prop)
- return oldlen;
-
- if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
- FDT_TAGALIGN(len))))
- return err;
-
- (*prop)->len = cpu_to_fdt32(len);
- return 0;
-}
-
-static int _fdt_add_property(void *fdt, int nodeoffset, const char *name,
- int len, struct fdt_property **prop)
-{
- int proplen;
- int nextoffset;
- int namestroff;
- int err;
-
- if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
- return nextoffset;
-
- namestroff = _fdt_find_add_string(fdt, name);
- if (namestroff < 0)
- return namestroff;
-
- *prop = _fdt_offset_ptr_w(fdt, nextoffset);
- proplen = sizeof(**prop) + FDT_TAGALIGN(len);
-
- err = _fdt_splice_struct(fdt, *prop, 0, proplen);
- if (err)
- return err;
-
- (*prop)->tag = cpu_to_fdt32(FDT_PROP);
- (*prop)->nameoff = cpu_to_fdt32(namestroff);
- (*prop)->len = cpu_to_fdt32(len);
- return 0;
-}
-
-int fdt_set_name(void *fdt, int nodeoffset, const char *name)
-{
- char *namep;
- int oldlen, newlen;
- int err;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
- if (!namep)
- return oldlen;
-
- newlen = strlen(name);
-
- err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1),
- FDT_TAGALIGN(newlen+1));
- if (err)
- return err;
-
- memcpy(namep, name, newlen+1);
- return 0;
-}
-
-int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
- int len, void **prop_data)
-{
- struct fdt_property *prop;
- int err;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop);
- if (err == -FDT_ERR_NOTFOUND)
- err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
- if (err)
- return err;
-
- *prop_data = prop->data;
- return 0;
-}
-
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
- const void *val, int len)
-{
- void *prop_data;
- int err;
-
- err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data);
- if (err)
- return err;
-
- if (len)
- memcpy(prop_data, val, len);
- return 0;
-}
-
-int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
- const void *val, int len)
-{
- struct fdt_property *prop;
- int err, oldlen, newlen;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
- if (prop) {
- newlen = len + oldlen;
- err = _fdt_splice_struct(fdt, prop->data,
- FDT_TAGALIGN(oldlen),
- FDT_TAGALIGN(newlen));
- if (err)
- return err;
- prop->len = cpu_to_fdt32(newlen);
- memcpy(prop->data + oldlen, val, len);
- } else {
- err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
- if (err)
- return err;
- memcpy(prop->data, val, len);
- }
- return 0;
-}
-
-int fdt_delprop(void *fdt, int nodeoffset, const char *name)
-{
- struct fdt_property *prop;
- int len, proplen;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
- if (!prop)
- return len;
-
- proplen = sizeof(*prop) + FDT_TAGALIGN(len);
- return _fdt_splice_struct(fdt, prop, proplen, 0);
-}
-
-int fdt_add_subnode_namelen(void *fdt, int parentoffset,
- const char *name, int namelen)
-{
- struct fdt_node_header *nh;
- int offset, nextoffset;
- int nodelen;
- int err;
- uint32_t tag;
- fdt32_t *endtag;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
- if (offset >= 0)
- return -FDT_ERR_EXISTS;
- else if (offset != -FDT_ERR_NOTFOUND)
- return offset;
-
- /* Try to place the new node after the parent's properties */
- fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
- do {
- offset = nextoffset;
- tag = fdt_next_tag(fdt, offset, &nextoffset);
- } while ((tag == FDT_PROP) || (tag == FDT_NOP));
-
- nh = _fdt_offset_ptr_w(fdt, offset);
- nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
-
- err = _fdt_splice_struct(fdt, nh, 0, nodelen);
- if (err)
- return err;
-
- nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
- memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
- memcpy(nh->name, name, namelen);
- endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
- *endtag = cpu_to_fdt32(FDT_END_NODE);
-
- return offset;
-}
-
-int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
-{
- return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
-}
-
-int fdt_del_node(void *fdt, int nodeoffset)
-{
- int endoffset;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- endoffset = _fdt_node_end_offset(fdt, nodeoffset);
- if (endoffset < 0)
- return endoffset;
-
- return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
- endoffset - nodeoffset, 0);
-}
-
-static void _fdt_packblocks(const char *old, char *new,
- int mem_rsv_size, int struct_size)
-{
- int mem_rsv_off, struct_off, strings_off;
-
- mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
- struct_off = mem_rsv_off + mem_rsv_size;
- strings_off = struct_off + struct_size;
-
- memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
- fdt_set_off_mem_rsvmap(new, mem_rsv_off);
-
- memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
- fdt_set_off_dt_struct(new, struct_off);
- fdt_set_size_dt_struct(new, struct_size);
-
- memmove(new + strings_off, old + fdt_off_dt_strings(old),
- fdt_size_dt_strings(old));
- fdt_set_off_dt_strings(new, strings_off);
- fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
-}
-
-int fdt_open_into(const void *fdt, void *buf, int bufsize)
-{
- int err;
- int mem_rsv_size, struct_size;
- int newsize;
- const char *fdtstart = fdt;
- const char *fdtend = fdtstart + fdt_totalsize(fdt);
- char *tmp;
-
- FDT_CHECK_HEADER(fdt);
-
- mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
- * sizeof(struct fdt_reserve_entry);
-
- if (fdt_version(fdt) >= 17) {
- struct_size = fdt_size_dt_struct(fdt);
- } else {
- struct_size = 0;
- while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)
- ;
- if (struct_size < 0)
- return struct_size;
- }
-
- if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) {
- /* no further work necessary */
- err = fdt_move(fdt, buf, bufsize);
- if (err)
- return err;
- fdt_set_version(buf, 17);
- fdt_set_size_dt_struct(buf, struct_size);
- fdt_set_totalsize(buf, bufsize);
- return 0;
- }
-
- /* Need to reorder */
- newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
- + struct_size + fdt_size_dt_strings(fdt);
-
- if (bufsize < newsize)
- return -FDT_ERR_NOSPACE;
-
- /* First attempt to build converted tree at beginning of buffer */
- tmp = buf;
- /* But if that overlaps with the old tree... */
- if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {
- /* Try right after the old tree instead */
- tmp = (char *)(uintptr_t)fdtend;
- if ((tmp + newsize) > ((char *)buf + bufsize))
- return -FDT_ERR_NOSPACE;
- }
-
- _fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size);
- memmove(buf, tmp, newsize);
-
- fdt_set_magic(buf, FDT_MAGIC);
- fdt_set_totalsize(buf, bufsize);
- fdt_set_version(buf, 17);
- fdt_set_last_comp_version(buf, 16);
- fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));
-
- return 0;
-}
-
-int fdt_pack(void *fdt)
-{
- int mem_rsv_size;
-
- FDT_RW_CHECK_HEADER(fdt);
-
- mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
- * sizeof(struct fdt_reserve_entry);
- _fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
- fdt_set_totalsize(fdt, _fdt_data_size(fdt));
-
- return 0;
-}
-
-int fdt_remove_unused_strings(const void *old, void *new)
-{
- const struct fdt_property *old_prop;
- struct fdt_property *new_prop;
- int size = fdt_totalsize(old);
- int next_offset, offset;
- const char *str;
- int ret;
- int tag = FDT_PROP;
-
- /* Make a copy and remove the strings */
- memcpy(new, old, size);
- fdt_set_size_dt_strings(new, 0);
-
- /* Add every property name back into the new string table */
- for (offset = 0; tag != FDT_END; offset = next_offset) {
- tag = fdt_next_tag(old, offset, &next_offset);
- if (tag != FDT_PROP)
- continue;
- old_prop = fdt_get_property_by_offset(old, offset, NULL);
- new_prop = (struct fdt_property *)(unsigned long)
- fdt_get_property_by_offset(new, offset, NULL);
- str = fdt_string(old, fdt32_to_cpu(old_prop->nameoff));
- ret = _fdt_find_add_string(new, str);
- if (ret < 0)
- return ret;
- new_prop->nameoff = cpu_to_fdt32(ret);
- }
-
- return 0;
-}
+#include <linux/libfdt_env.h>
+#include "../../scripts/dtc/libfdt/fdt_rw.c"
+++ /dev/null
-#ifndef _LIBFDT_H
-#define _LIBFDT_H
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
- */
-
-#include <libfdt_env.h>
-#include <fdt.h>
-
-#define FDT_FIRST_SUPPORTED_VERSION 0x10
-#define FDT_LAST_SUPPORTED_VERSION 0x11
-
-/* Error codes: informative error codes */
-#define FDT_ERR_NOTFOUND 1
- /* FDT_ERR_NOTFOUND: The requested node or property does not exist */
-#define FDT_ERR_EXISTS 2
- /* FDT_ERR_EXISTS: Attempted to create a node or property which
- * already exists */
-#define FDT_ERR_NOSPACE 3
- /* FDT_ERR_NOSPACE: Operation needed to expand the device
- * tree, but its buffer did not have sufficient space to
- * contain the expanded tree. Use fdt_open_into() to move the
- * device tree to a buffer with more space. */
-
-/* Error codes: codes for bad parameters */
-#define FDT_ERR_BADOFFSET 4
- /* FDT_ERR_BADOFFSET: Function was passed a structure block
- * offset which is out-of-bounds, or which points to an
- * unsuitable part of the structure for the operation. */
-#define FDT_ERR_BADPATH 5
- /* FDT_ERR_BADPATH: Function was passed a badly formatted path
- * (e.g. missing a leading / for a function which requires an
- * absolute path) */
-#define FDT_ERR_BADPHANDLE 6
- /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle.
- * This can be caused either by an invalid phandle property
- * length, or the phandle value was either 0 or -1, which are
- * not permitted. */
-#define FDT_ERR_BADSTATE 7
- /* FDT_ERR_BADSTATE: Function was passed an incomplete device
- * tree created by the sequential-write functions, which is
- * not sufficiently complete for the requested operation. */
-
-/* Error codes: codes for bad device tree blobs */
-#define FDT_ERR_TRUNCATED 8
- /* FDT_ERR_TRUNCATED: Structure block of the given device tree
- * ends without an FDT_END tag. */
-#define FDT_ERR_BADMAGIC 9
- /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
- * device tree at all - it is missing the flattened device
- * tree magic number. */
-#define FDT_ERR_BADVERSION 10
- /* FDT_ERR_BADVERSION: Given device tree has a version which
- * can't be handled by the requested operation. For
- * read-write functions, this may mean that fdt_open_into() is
- * required to convert the tree to the expected version. */
-#define FDT_ERR_BADSTRUCTURE 11
- /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
- * structure block or other serious error (e.g. misnested
- * nodes, or subnodes preceding properties). */
-#define FDT_ERR_BADLAYOUT 12
- /* FDT_ERR_BADLAYOUT: For read-write functions, the given
- * device tree has it's sub-blocks in an order that the
- * function can't handle (memory reserve map, then structure,
- * then strings). Use fdt_open_into() to reorganize the tree
- * into a form suitable for the read-write operations. */
-
-/* "Can't happen" error indicating a bug in libfdt */
-#define FDT_ERR_INTERNAL 13
- /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
- * Should never be returned, if it is, it indicates a bug in
- * libfdt itself. */
-
-/* Errors in device tree content */
-#define FDT_ERR_BADNCELLS 14
- /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells
- * or similar property with a bad format or value */
-
-#define FDT_ERR_BADVALUE 15
- /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected
- * value. For example: a property expected to contain a string list
- * is not NUL-terminated within the length of its value. */
-
-#define FDT_ERR_BADOVERLAY 16
- /* FDT_ERR_BADOVERLAY: The device tree overlay, while
- * correctly structured, cannot be applied due to some
- * unexpected or missing value, property or node. */
-
-#define FDT_ERR_NOPHANDLES 17
- /* FDT_ERR_NOPHANDLES: The device tree doesn't have any
- * phandle available anymore without causing an overflow */
-
-#define FDT_ERR_MAX 17
-
-/**********************************************************************/
-/* Low-level functions (you probably don't need these) */
-/**********************************************************************/
-
-#ifndef SWIG /* This function is not useful in Python */
-const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
-#endif
-static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
-{
- return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
-}
-
-uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
-
-/**********************************************************************/
-/* Traversal functions */
-/**********************************************************************/
-
-int fdt_next_node(const void *fdt, int offset, int *depth);
-
-/**
- * fdt_first_subnode() - get offset of first direct subnode
- *
- * @fdt: FDT blob
- * @offset: Offset of node to check
- * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none
- */
-int fdt_first_subnode(const void *fdt, int offset);
-
-/**
- * fdt_next_subnode() - get offset of next direct subnode
- *
- * After first calling fdt_first_subnode(), call this function repeatedly to
- * get direct subnodes of a parent node.
- *
- * @fdt: FDT blob
- * @offset: Offset of previous subnode
- * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more
- * subnodes
- */
-int fdt_next_subnode(const void *fdt, int offset);
-
-/**
- * fdt_for_each_subnode - iterate over all subnodes of a parent
- *
- * @node: child node (int, lvalue)
- * @fdt: FDT blob (const void *)
- * @parent: parent node (int)
- *
- * This is actually a wrapper around a for loop and would be used like so:
- *
- * fdt_for_each_subnode(node, fdt, parent) {
- * Use node
- * ...
- * }
- *
- * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) {
- * Error handling
- * }
- *
- * Note that this is implemented as a macro and @node is used as
- * iterator in the loop. The parent variable be constant or even a
- * literal.
- *
- */
-#define fdt_for_each_subnode(node, fdt, parent) \
- for (node = fdt_first_subnode(fdt, parent); \
- node >= 0; \
- node = fdt_next_subnode(fdt, node))
-
-/**********************************************************************/
-/* General functions */
-/**********************************************************************/
-#define fdt_get_header(fdt, field) \
- (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
-#define fdt_magic(fdt) (fdt_get_header(fdt, magic))
-#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize))
-#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct))
-#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings))
-#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap))
-#define fdt_version(fdt) (fdt_get_header(fdt, version))
-#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version))
-#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys))
-#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings))
-#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct))
-
-#define __fdt_set_hdr(name) \
- static inline void fdt_set_##name(void *fdt, uint32_t val) \
- { \
- struct fdt_header *fdth = (struct fdt_header *)fdt; \
- fdth->name = cpu_to_fdt32(val); \
- }
-__fdt_set_hdr(magic);
-__fdt_set_hdr(totalsize);
-__fdt_set_hdr(off_dt_struct);
-__fdt_set_hdr(off_dt_strings);
-__fdt_set_hdr(off_mem_rsvmap);
-__fdt_set_hdr(version);
-__fdt_set_hdr(last_comp_version);
-__fdt_set_hdr(boot_cpuid_phys);
-__fdt_set_hdr(size_dt_strings);
-__fdt_set_hdr(size_dt_struct);
-#undef __fdt_set_hdr
-
-/**
- * fdt_check_header - sanity check a device tree or possible device tree
- * @fdt: pointer to data which might be a flattened device tree
- *
- * fdt_check_header() checks that the given buffer contains what
- * appears to be a flattened device tree with sane information in its
- * header.
- *
- * returns:
- * 0, if the buffer appears to contain a valid device tree
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE, standard meanings, as above
- */
-int fdt_check_header(const void *fdt);
-
-/**
- * fdt_move - move a device tree around in memory
- * @fdt: pointer to the device tree to move
- * @buf: pointer to memory where the device is to be moved
- * @bufsize: size of the memory space at buf
- *
- * fdt_move() relocates, if possible, the device tree blob located at
- * fdt to the buffer at buf of size bufsize. The buffer may overlap
- * with the existing device tree blob at fdt. Therefore,
- * fdt_move(fdt, fdt, fdt_totalsize(fdt))
- * should always succeed.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_move(const void *fdt, void *buf, int bufsize);
-
-/**********************************************************************/
-/* Read-only functions */
-/**********************************************************************/
-
-/**
- * fdt_string - retrieve a string from the strings block of a device tree
- * @fdt: pointer to the device tree blob
- * @stroffset: offset of the string within the strings block (native endian)
- *
- * fdt_string() retrieves a pointer to a single string from the
- * strings block of the device tree blob at fdt.
- *
- * returns:
- * a pointer to the string, on success
- * NULL, if stroffset is out of bounds
- */
-const char *fdt_string(const void *fdt, int stroffset);
-
-/**
- * fdt_get_max_phandle - retrieves the highest phandle in a tree
- * @fdt: pointer to the device tree blob
- *
- * fdt_get_max_phandle retrieves the highest phandle in the given
- * device tree. This will ignore badly formatted phandles, or phandles
- * with a value of 0 or -1.
- *
- * returns:
- * the highest phandle on success
- * 0, if no phandle was found in the device tree
- * -1, if an error occurred
- */
-uint32_t fdt_get_max_phandle(const void *fdt);
-
-/**
- * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
- * @fdt: pointer to the device tree blob
- *
- * Returns the number of entries in the device tree blob's memory
- * reservation map. This does not include the terminating 0,0 entry
- * or any other (0,0) entries reserved for expansion.
- *
- * returns:
- * the number of entries
- */
-int fdt_num_mem_rsv(const void *fdt);
-
-/**
- * fdt_get_mem_rsv - retrieve one memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @address, @size: pointers to 64-bit variables
- *
- * On success, *address and *size will contain the address and size of
- * the n-th reserve map entry from the device tree blob, in
- * native-endian format.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
-
-/**
- * fdt_subnode_offset_namelen - find a subnode based on substring
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_subnode_offset(), but only examine the first
- * namelen characters of name for matching the subnode name. This is
- * useful for finding subnodes based on a portion of a larger string,
- * such as a full path.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
- const char *name, int namelen);
-#endif
-/**
- * fdt_subnode_offset - find a subnode of a given node
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- *
- * fdt_subnode_offset() finds a subnode of the node at structure block
- * offset parentoffset with the given name. name may include a unit
- * address, in which case fdt_subnode_offset() will find the subnode
- * with that unit address, or the unit address may be omitted, in
- * which case fdt_subnode_offset() will find an arbitrary subnode
- * whose name excluding unit address matches the given name.
- *
- * returns:
- * structure block offset of the requested subnode (>=0), on success
- * -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
- * tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
-
-/**
- * fdt_path_offset_namelen - find a tree node by its full path
- * @fdt: pointer to the device tree blob
- * @path: full path of the node to locate
- * @namelen: number of characters of path to consider
- *
- * Identical to fdt_path_offset(), but only consider the first namelen
- * characters of path as the path name.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen);
-#endif
-
-/**
- * fdt_path_offset - find a tree node by its full path
- * @fdt: pointer to the device tree blob
- * @path: full path of the node to locate
- *
- * fdt_path_offset() finds a node of a given path in the device tree.
- * Each path component may omit the unit address portion, but the
- * results of this are undefined if any such path component is
- * ambiguous (that is if there are multiple nodes at the relevant
- * level matching the given component, differentiated only by unit
- * address).
- *
- * returns:
- * structure block offset of the node with the requested path (>=0), on
- * success
- * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
- * -FDT_ERR_NOTFOUND, if the requested node does not exist
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_path_offset(const void *fdt, const char *path);
-
-/**
- * fdt_get_name - retrieve the name of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of the starting node
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_name() retrieves the name (including unit address) of the
- * device tree node at structure block offset nodeoffset. If lenp is
- * non-NULL, the length of this name is also returned, in the integer
- * pointed to by lenp.
- *
- * returns:
- * pointer to the node's name, on success
- * If lenp is non-NULL, *lenp contains the length of that name
- * (>=0)
- * NULL, on error
- * if lenp is non-NULL *lenp contains an error code (<0):
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- * tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE, standard meanings
- */
-const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
-
-/**
- * fdt_first_property_offset - find the offset of a node's first property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of a node
- *
- * fdt_first_property_offset() finds the first property of the node at
- * the given structure block offset.
- *
- * returns:
- * structure block offset of the property (>=0), on success
- * -FDT_ERR_NOTFOUND, if the requested node has no properties
- * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_first_property_offset(const void *fdt, int nodeoffset);
-
-/**
- * fdt_next_property_offset - step through a node's properties
- * @fdt: pointer to the device tree blob
- * @offset: structure block offset of a property
- *
- * fdt_next_property_offset() finds the property immediately after the
- * one at the given structure block offset. This will be a property
- * of the same node as the given property.
- *
- * returns:
- * structure block offset of the next property (>=0), on success
- * -FDT_ERR_NOTFOUND, if the given property is the last in its node
- * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_next_property_offset(const void *fdt, int offset);
-
-/**
- * fdt_for_each_property_offset - iterate over all properties of a node
- *
- * @property_offset: property offset (int, lvalue)
- * @fdt: FDT blob (const void *)
- * @node: node offset (int)
- *
- * This is actually a wrapper around a for loop and would be used like so:
- *
- * fdt_for_each_property_offset(property, fdt, node) {
- * Use property
- * ...
- * }
- *
- * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) {
- * Error handling
- * }
- *
- * Note that this is implemented as a macro and property is used as
- * iterator in the loop. The node variable can be constant or even a
- * literal.
- */
-#define fdt_for_each_property_offset(property, fdt, node) \
- for (property = fdt_first_property_offset(fdt, node); \
- property >= 0; \
- property = fdt_next_property_offset(fdt, property))
-
-/**
- * fdt_get_property_by_offset - retrieve the property at a given offset
- * @fdt: pointer to the device tree blob
- * @offset: offset of the property to retrieve
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_property_by_offset() retrieves a pointer to the
- * fdt_property structure within the device tree blob at the given
- * offset. If lenp is non-NULL, the length of the property value is
- * also returned, in the integer pointed to by lenp.
- *
- * returns:
- * pointer to the structure representing the property
- * if lenp is non-NULL, *lenp contains the length of the property
- * value (>=0)
- * NULL, on error
- * if lenp is non-NULL, *lenp contains an error code (<0):
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
- int offset,
- int *lenp);
-
-/**
- * fdt_get_property_namelen - find a property based on substring
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @namelen: number of characters of name to consider
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * Identical to fdt_get_property(), but only examine the first namelen
- * characters of name for matching the property name.
- */
-#ifndef SWIG /* Not available in Python */
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
- int nodeoffset,
- const char *name,
- int namelen, int *lenp);
-#endif
-
-/**
- * fdt_get_property - find a given property in a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_property() retrieves a pointer to the fdt_property
- * structure within the device tree blob corresponding to the property
- * named 'name' of the node at offset nodeoffset. If lenp is
- * non-NULL, the length of the property value is also returned, in the
- * integer pointed to by lenp.
- *
- * returns:
- * pointer to the structure representing the property
- * if lenp is non-NULL, *lenp contains the length of the property
- * value (>=0)
- * NULL, on error
- * if lenp is non-NULL, *lenp contains an error code (<0):
- * -FDT_ERR_NOTFOUND, node does not have named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- * tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
- const char *name, int *lenp);
-static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
- const char *name,
- int *lenp)
-{
- return (struct fdt_property *)(uintptr_t)
- fdt_get_property(fdt, nodeoffset, name, lenp);
-}
-
-/**
- * fdt_getprop_by_offset - retrieve the value of a property at a given offset
- * @fdt: pointer to the device tree blob
- * @ffset: offset of the property to read
- * @namep: pointer to a string variable (will be overwritten) or NULL
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_getprop_by_offset() retrieves a pointer to the value of the
- * property at structure block offset 'offset' (this will be a pointer
- * to within the device blob itself, not a copy of the value). If
- * lenp is non-NULL, the length of the property value is also
- * returned, in the integer pointed to by lenp. If namep is non-NULL,
- * the property's namne will also be returned in the char * pointed to
- * by namep (this will be a pointer to within the device tree's string
- * block, not a new copy of the name).
- *
- * returns:
- * pointer to the property's value
- * if lenp is non-NULL, *lenp contains the length of the property
- * value (>=0)
- * if namep is non-NULL *namep contiains a pointer to the property
- * name.
- * NULL, on error
- * if lenp is non-NULL, *lenp contains an error code (<0):
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-#ifndef SWIG /* This function is not useful in Python */
-const void *fdt_getprop_by_offset(const void *fdt, int offset,
- const char **namep, int *lenp);
-#endif
-
-/**
- * fdt_getprop_namelen - get property value based on substring
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @namelen: number of characters of name to consider
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * Identical to fdt_getprop(), but only examine the first namelen
- * characters of name for matching the property name.
- */
-#ifndef SWIG /* Not available in Python */
-const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
- const char *name, int namelen, int *lenp);
-static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset,
- const char *name, int namelen,
- int *lenp)
-{
- return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name,
- namelen, lenp);
-}
-#endif
-
-/**
- * fdt_getprop - retrieve the value of a given property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_getprop() retrieves a pointer to the value of the property
- * named 'name' of the node at offset nodeoffset (this will be a
- * pointer to within the device blob itself, not a copy of the value).
- * If lenp is non-NULL, the length of the property value is also
- * returned, in the integer pointed to by lenp.
- *
- * returns:
- * pointer to the property's value
- * if lenp is non-NULL, *lenp contains the length of the property
- * value (>=0)
- * NULL, on error
- * if lenp is non-NULL, *lenp contains an error code (<0):
- * -FDT_ERR_NOTFOUND, node does not have named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- * tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-const void *fdt_getprop(const void *fdt, int nodeoffset,
- const char *name, int *lenp);
-static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
- const char *name, int *lenp)
-{
- return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
-}
-
-/**
- * fdt_get_phandle - retrieve the phandle of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of the node
- *
- * fdt_get_phandle() retrieves the phandle of the device tree node at
- * structure block offset nodeoffset.
- *
- * returns:
- * the phandle of the node at nodeoffset, on success (!= 0, != -1)
- * 0, if the node has no phandle, or another error occurs
- */
-uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
-
-/**
- * fdt_get_alias_namelen - get alias based on substring
- * @fdt: pointer to the device tree blob
- * @name: name of the alias th look up
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_get_alias(), but only examine the first namelen
- * characters of name for matching the alias name.
- */
-#ifndef SWIG /* Not available in Python */
-const char *fdt_get_alias_namelen(const void *fdt,
- const char *name, int namelen);
-#endif
-
-/**
- * fdt_get_alias - retrieve the path referenced by a given alias
- * @fdt: pointer to the device tree blob
- * @name: name of the alias th look up
- *
- * fdt_get_alias() retrieves the value of a given alias. That is, the
- * value of the property named 'name' in the node /aliases.
- *
- * returns:
- * a pointer to the expansion of the alias named 'name', if it exists
- * NULL, if the given alias or the /aliases node does not exist
- */
-const char *fdt_get_alias(const void *fdt, const char *name);
-
-/**
- * fdt_get_path - determine the full path of a node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose path to find
- * @buf: character buffer to contain the returned path (will be overwritten)
- * @buflen: size of the character buffer at buf
- *
- * fdt_get_path() computes the full path of the node at offset
- * nodeoffset, and records that path in the buffer at buf.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- * 0, on success
- * buf contains the absolute path of the node at
- * nodeoffset, as a NUL-terminated string.
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
- * characters and will not fit in the given buffer.
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
-
-/**
- * fdt_supernode_atdepth_offset - find a specific ancestor of a node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- * @supernodedepth: depth of the ancestor to find
- * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_supernode_atdepth_offset() finds an ancestor of the given node
- * at a specific depth from the root (where the root itself has depth
- * 0, its immediate subnodes depth 1 and so forth). So
- * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
- * will always return 0, the offset of the root node. If the node at
- * nodeoffset has depth D, then:
- * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
- * will return nodeoffset itself.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- * structure block offset of the node at node offset's ancestor
- * of depth supernodedepth (>=0), on success
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of
- * nodeoffset
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
- int supernodedepth, int *nodedepth);
-
-/**
- * fdt_node_depth - find the depth of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- *
- * fdt_node_depth() finds the depth of a given node. The root node
- * has depth 0, its immediate subnodes depth 1 and so forth.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- * depth of the node at nodeoffset (>=0), on success
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_depth(const void *fdt, int nodeoffset);
-
-/**
- * fdt_parent_offset - find the parent of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- *
- * fdt_parent_offset() locates the parent node of a given node (that
- * is, it finds the offset of the node which contains the node at
- * nodeoffset as a subnode).
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset, *twice*.
- *
- * returns:
- * structure block offset of the parent of the node at nodeoffset
- * (>=0), on success
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_parent_offset(const void *fdt, int nodeoffset);
-
-/**
- * fdt_node_offset_by_prop_value - find nodes with a given property value
- * @fdt: pointer to the device tree blob
- * @startoffset: only find nodes after this offset
- * @propname: property name to check
- * @propval: property value to search for
- * @proplen: length of the value in propval
- *
- * fdt_node_offset_by_prop_value() returns the offset of the first
- * node after startoffset, which has a property named propname whose
- * value is of length proplen and has value equal to propval; or if
- * startoffset is -1, the very first such node in the tree.
- *
- * To iterate through all nodes matching the criterion, the following
- * idiom can be used:
- * offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
- * propval, proplen);
- * while (offset != -FDT_ERR_NOTFOUND) {
- * // other code here
- * offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
- * propval, proplen);
- * }
- *
- * Note the -1 in the first call to the function, if 0 is used here
- * instead, the function will never locate the root node, even if it
- * matches the criterion.
- *
- * returns:
- * structure block offset of the located node (>= 0, >startoffset),
- * on success
- * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
- * tree after startoffset
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
- const char *propname,
- const void *propval, int proplen);
-
-/**
- * fdt_node_offset_by_phandle - find the node with a given phandle
- * @fdt: pointer to the device tree blob
- * @phandle: phandle value
- *
- * fdt_node_offset_by_phandle() returns the offset of the node
- * which has the given phandle value. If there is more than one node
- * in the tree with the given phandle (an invalid tree), results are
- * undefined.
- *
- * returns:
- * structure block offset of the located node (>= 0), on success
- * -FDT_ERR_NOTFOUND, no node with that phandle exists
- * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
-
-/**
- * fdt_node_check_compatible: check a node's compatible property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @compatible: string to match against
- *
- *
- * fdt_node_check_compatible() returns 0 if the given node contains a
- * 'compatible' property with the given string as one of its elements,
- * it returns non-zero otherwise, or on error.
- *
- * returns:
- * 0, if the node has a 'compatible' property listing the given string
- * 1, if the node has a 'compatible' property, but it does not list
- * the given string
- * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
- * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_check_compatible(const void *fdt, int nodeoffset,
- const char *compatible);
-
-/**
- * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
- * @fdt: pointer to the device tree blob
- * @startoffset: only find nodes after this offset
- * @compatible: 'compatible' string to match against
- *
- * fdt_node_offset_by_compatible() returns the offset of the first
- * node after startoffset, which has a 'compatible' property which
- * lists the given compatible string; or if startoffset is -1, the
- * very first such node in the tree.
- *
- * To iterate through all nodes matching the criterion, the following
- * idiom can be used:
- * offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
- * while (offset != -FDT_ERR_NOTFOUND) {
- * // other code here
- * offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
- * }
- *
- * Note the -1 in the first call to the function, if 0 is used here
- * instead, the function will never locate the root node, even if it
- * matches the criterion.
- *
- * returns:
- * structure block offset of the located node (>= 0, >startoffset),
- * on success
- * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
- * tree after startoffset
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
- const char *compatible);
-
-/**
- * fdt_stringlist_contains - check a string list property for a string
- * @strlist: Property containing a list of strings to check
- * @listlen: Length of property
- * @str: String to search for
- *
- * This is a utility function provided for convenience. The list contains
- * one or more strings, each terminated by \0, as is found in a device tree
- * "compatible" property.
- *
- * @return: 1 if the string is found in the list, 0 not found, or invalid list
- */
-int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
-
-/**
- * fdt_stringlist_count - count the number of strings in a string list
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @return:
- * the number of strings in the given property
- * -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- * -FDT_ERR_NOTFOUND if the property does not exist
- */
-int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property);
-
-/**
- * fdt_stringlist_search - find a string in a string list and return its index
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @string: string to look up in the string list
- *
- * Note that it is possible for this function to succeed on property values
- * that are not NUL-terminated. That's because the function will stop after
- * finding the first occurrence of @string. This can for example happen with
- * small-valued cell properties, such as #address-cells, when searching for
- * the empty string.
- *
- * @return:
- * the index of the string in the list of strings
- * -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- * -FDT_ERR_NOTFOUND if the property does not exist or does not contain
- * the given string
- */
-int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
- const char *string);
-
-/**
- * fdt_stringlist_get() - obtain the string at a given index in a string list
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @index: index of the string to return
- * @lenp: return location for the string length or an error code on failure
- *
- * Note that this will successfully extract strings from properties with
- * non-NUL-terminated values. For example on small-valued cell properties
- * this function will return the empty string.
- *
- * If non-NULL, the length of the string (on success) or a negative error-code
- * (on failure) will be stored in the integer pointer to by lenp.
- *
- * @return:
- * A pointer to the string at the given index in the string list or NULL on
- * failure. On success the length of the string will be stored in the memory
- * location pointed to by the lenp parameter, if non-NULL. On failure one of
- * the following negative error codes will be returned in the lenp parameter
- * (if non-NULL):
- * -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- * -FDT_ERR_NOTFOUND if the property does not exist
- */
-const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
- const char *property, int index,
- int *lenp);
-
-/**********************************************************************/
-/* Read-only functions (addressing related) */
-/**********************************************************************/
-
-/**
- * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells
- *
- * This is the maximum value for #address-cells, #size-cells and
- * similar properties that will be processed by libfdt. IEE1275
- * requires that OF implementations handle values up to 4.
- * Implementations may support larger values, but in practice higher
- * values aren't used.
- */
-#define FDT_MAX_NCELLS 4
-
-/**
- * fdt_address_cells - retrieve address size for a bus represented in the tree
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to find the address size for
- *
- * When the node has a valid #address-cells property, returns its value.
- *
- * returns:
- * 0 <= n < FDT_MAX_NCELLS, on success
- * 2, if the node has no #address-cells property
- * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
- * #address-cells property
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_address_cells(const void *fdt, int nodeoffset);
-
-/**
- * fdt_size_cells - retrieve address range size for a bus represented in the
- * tree
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to find the address range size for
- *
- * When the node has a valid #size-cells property, returns its value.
- *
- * returns:
- * 0 <= n < FDT_MAX_NCELLS, on success
- * 2, if the node has no #address-cells property
- * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
- * #size-cells property
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_size_cells(const void *fdt, int nodeoffset);
-
-
-/**********************************************************************/
-/* Write-in-place functions */
-/**********************************************************************/
-
-/**
- * fdt_setprop_inplace_namelen_partial - change a property's value,
- * but not its size
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @namelen: number of characters of name to consider
- * @idx: index of the property to change in the array
- * @val: pointer to data to replace the property value with
- * @len: length of the property value
- *
- * Identical to fdt_setprop_inplace(), but modifies the given property
- * starting from the given index, and using only the first characters
- * of the name. It is useful when you want to manipulate only one value of
- * an array and you have a string that doesn't end with \0.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
- const char *name, int namelen,
- uint32_t idx, const void *val,
- int len);
-#endif
-
-/**
- * fdt_setprop_inplace - change a property's value, but not its size
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: pointer to data to replace the property value with
- * @len: length of the property value
- *
- * fdt_setprop_inplace() replaces the value of a given property with
- * the data in val, of length len. This function cannot change the
- * size of a property, and so will only work if len is equal to the
- * current length of the property.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, if len is not equal to the property's current length
- * -FDT_ERR_NOTFOUND, node does not have the named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
- const void *val, int len);
-#endif
-
-/**
- * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value to replace the property with
- *
- * fdt_setprop_inplace_u32() replaces the value of a given property
- * with the 32-bit integer value in val, converting val to big-endian
- * if necessary. This function cannot change the size of a property,
- * and so will only work if the property already exists and has length
- * 4.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, if the property's length is not equal to 4
- * -FDT_ERR_NOTFOUND, node does not have the named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
- const char *name, uint32_t val)
-{
- fdt32_t tmp = cpu_to_fdt32(val);
- return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value to replace the property with
- *
- * fdt_setprop_inplace_u64() replaces the value of a given property
- * with the 64-bit integer value in val, converting val to big-endian
- * if necessary. This function cannot change the size of a property,
- * and so will only work if the property already exists and has length
- * 8.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, if the property's length is not equal to 8
- * -FDT_ERR_NOTFOUND, node does not have the named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
- const char *name, uint64_t val)
-{
- fdt64_t tmp = cpu_to_fdt64(val);
- return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_inplace_cell - change the value of a single-cell property
- *
- * This is an alternative name for fdt_setprop_inplace_u32()
- */
-static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
- const char *name, uint32_t val)
-{
- return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_nop_property - replace a property with nop tags
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to nop
- * @name: name of the property to nop
- *
- * fdt_nop_property() will replace a given property's representation
- * in the blob with FDT_NOP tags, effectively removing it from the
- * tree.
- *
- * This function will alter only the bytes in the blob which contain
- * the property, and will not alter or move any other part of the
- * tree.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOTFOUND, node does not have the named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_nop_node - replace a node (subtree) with nop tags
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to nop
- *
- * fdt_nop_node() will replace a given node's representation in the
- * blob, including all its subnodes, if any, with FDT_NOP tags,
- * effectively removing it from the tree.
- *
- * This function will alter only the bytes in the blob which contain
- * the node and its properties and subnodes, and will not alter or
- * move any other part of the tree.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_nop_node(void *fdt, int nodeoffset);
-
-/**********************************************************************/
-/* Sequential write functions */
-/**********************************************************************/
-
-int fdt_create(void *buf, int bufsize);
-int fdt_resize(void *fdt, void *buf, int bufsize);
-int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
-int fdt_finish_reservemap(void *fdt);
-int fdt_begin_node(void *fdt, const char *name);
-int fdt_property(void *fdt, const char *name, const void *val, int len);
-static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
-{
- fdt32_t tmp = cpu_to_fdt32(val);
- return fdt_property(fdt, name, &tmp, sizeof(tmp));
-}
-static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
-{
- fdt64_t tmp = cpu_to_fdt64(val);
- return fdt_property(fdt, name, &tmp, sizeof(tmp));
-}
-static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
-{
- return fdt_property_u32(fdt, name, val);
-}
-
-/**
- * fdt_property_placeholder - add a new property and return a ptr to its value
- *
- * @fdt: pointer to the device tree blob
- * @name: name of property to add
- * @len: length of property value in bytes
- * @valp: returns a pointer to where where the value should be placed
- *
- * returns:
- * 0, on success
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_NOSPACE, standard meanings
- */
-int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp);
-
-#define fdt_property_string(fdt, name, str) \
- fdt_property(fdt, name, str, strlen(str)+1)
-int fdt_end_node(void *fdt);
-int fdt_finish(void *fdt);
-
-/**********************************************************************/
-/* Read-write functions */
-/**********************************************************************/
-
-int fdt_create_empty_tree(void *buf, int bufsize);
-int fdt_open_into(const void *fdt, void *buf, int bufsize);
-int fdt_pack(void *fdt);
-
-/**
- * fdt_add_mem_rsv - add one memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @address, @size: 64-bit values (native endian)
- *
- * Adds a reserve map entry to the given blob reserving a region at
- * address address of length size.
- *
- * This function will insert data into the reserve map and will
- * therefore change the indexes of some entries in the table.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new reservation entry
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
-
-/**
- * fdt_del_mem_rsv - remove a memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @n: entry to remove
- *
- * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
- * the blob.
- *
- * This function will delete data from the reservation table and will
- * therefore change the indexes of some entries in the table.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
- * are less than n+1 reserve map entries)
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_del_mem_rsv(void *fdt, int n);
-
-/**
- * fdt_set_name - change the name of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of a node
- * @name: name to give the node
- *
- * fdt_set_name() replaces the name (including unit address, if any)
- * of the given node with the given string. NOTE: this function can't
- * efficiently check if the new name is unique amongst the given
- * node's siblings; results are undefined if this function is invoked
- * with a name equal to one of the given node's siblings.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob
- * to contain the new name
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_set_name(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_setprop - create or change a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: pointer to data to set the property value to
- * @len: length of the property value
- *
- * fdt_setprop() sets the value of the named property in the given
- * node to the given value and length, creating the property if it
- * does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
- const void *val, int len);
-
-/**
- * fdt_setprop _placeholder - allocate space for a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @len: length of the property value
- * @prop_data: return pointer to property data
- *
- * fdt_setprop_placeholer() allocates the named property in the given node.
- * If the property exists it is resized. In either case a pointer to the
- * property data is returned.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
- int len, void **prop_data);
-
-/**
- * fdt_setprop_u32 - set a property to a 32-bit integer
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value for the property (native endian)
- *
- * fdt_setprop_u32() sets the value of the named property in the given
- * node to the given 32-bit integer value (converting to big-endian if
- * necessary), or creates a new property with that value if it does
- * not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
- uint32_t val)
-{
- fdt32_t tmp = cpu_to_fdt32(val);
- return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_u64 - set a property to a 64-bit integer
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value for the property (native endian)
- *
- * fdt_setprop_u64() sets the value of the named property in the given
- * node to the given 64-bit integer value (converting to big-endian if
- * necessary), or creates a new property with that value if it does
- * not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
- uint64_t val)
-{
- fdt64_t tmp = cpu_to_fdt64(val);
- return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_cell - set a property to a single cell value
- *
- * This is an alternative name for fdt_setprop_u32()
- */
-static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
- uint32_t val)
-{
- return fdt_setprop_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_setprop_string - set a property to a string value
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @str: string value for the property
- *
- * fdt_setprop_string() sets the value of the named property in the
- * given node to the given string value (using the length of the
- * string to determine the new length of the property), or creates a
- * new property with that value if it does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_setprop_string(fdt, nodeoffset, name, str) \
- fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
-
-
-/**
- * fdt_setprop_empty - set a property to an empty value
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- *
- * fdt_setprop_empty() sets the value of the named property in the
- * given node to an empty (zero length) value, or creates a new empty
- * property if it does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_setprop_empty(fdt, nodeoffset, name) \
- fdt_setprop((fdt), (nodeoffset), (name), NULL, 0)
-
-/**
- * fdt_appendprop - append to or create a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to append to
- * @val: pointer to data to append to the property value
- * @len: length of the data to append to the property value
- *
- * fdt_appendprop() appends the value to the named property in the
- * given node, creating the property if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
- const void *val, int len);
-
-/**
- * fdt_appendprop_u32 - append a 32-bit integer value to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value to append to the property (native endian)
- *
- * fdt_appendprop_u32() appends the given 32-bit integer value
- * (converting to big-endian if necessary) to the value of the named
- * property in the given node, or creates a new property with that
- * value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
- const char *name, uint32_t val)
-{
- fdt32_t tmp = cpu_to_fdt32(val);
- return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_appendprop_u64 - append a 64-bit integer value to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value to append to the property (native endian)
- *
- * fdt_appendprop_u64() appends the given 64-bit integer value
- * (converting to big-endian if necessary) to the value of the named
- * property in the given node, or creates a new property with that
- * value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
- const char *name, uint64_t val)
-{
- fdt64_t tmp = cpu_to_fdt64(val);
- return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_appendprop_cell - append a single cell value to a property
- *
- * This is an alternative name for fdt_appendprop_u32()
- */
-static inline int fdt_appendprop_cell(void *fdt, int nodeoffset,
- const char *name, uint32_t val)
-{
- return fdt_appendprop_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_appendprop_string - append a string to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @str: string value to append to the property
- *
- * fdt_appendprop_string() appends the given string to the value of
- * the named property in the given node, or creates a new property
- * with that value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- * contain the new property value
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_appendprop_string(fdt, nodeoffset, name, str) \
- fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
-
-/**
- * fdt_delprop - delete a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to nop
- * @name: name of the property to nop
- *
- * fdt_del_property() will delete the given property.
- *
- * This function will delete data from the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOTFOUND, node does not have the named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_delprop(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_add_subnode_namelen - creates a new node based on substring
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_add_subnode(), but use only the first namelen
- * characters of name as the name of the new node. This is useful for
- * creating subnodes based on a portion of a larger string, such as a
- * full path.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_add_subnode_namelen(void *fdt, int parentoffset,
- const char *name, int namelen);
-#endif
-
-/**
- * fdt_add_subnode - creates a new node
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- *
- * fdt_add_subnode() creates a new node as a subnode of the node at
- * structure block offset parentoffset, with the given name (which
- * should include the unit address, if any).
- *
- * This function will insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
-
- * returns:
- * structure block offset of the created nodeequested subnode (>=0), on
- * success
- * -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
- * tag
- * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
- * the given name
- * -FDT_ERR_NOSPACE, if there is insufficient free space in the
- * blob to contain the new node
- * -FDT_ERR_NOSPACE
- * -FDT_ERR_BADLAYOUT
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
-
-/**
- * fdt_del_node - delete a node (subtree)
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to nop
- *
- * fdt_del_node() will remove the given node, including all its
- * subnodes if any, from the blob.
- *
- * This function will delete data from the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_del_node(void *fdt, int nodeoffset);
-
-/**
- * fdt_overlay_apply - Applies a DT overlay on a base DT
- * @fdt: pointer to the base device tree blob
- * @fdto: pointer to the device tree overlay blob
- *
- * fdt_overlay_apply() will apply the given device tree overlay on the
- * given base device tree.
- *
- * Expect the base device tree to be modified, even if the function
- * returns an error.
- *
- * returns:
- * 0, on success
- * -FDT_ERR_NOSPACE, there's not enough space in the base device tree
- * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or
- * properties in the base DT
- * -FDT_ERR_BADPHANDLE,
- * -FDT_ERR_BADOVERLAY,
- * -FDT_ERR_NOPHANDLES,
- * -FDT_ERR_INTERNAL,
- * -FDT_ERR_BADLAYOUT,
- * -FDT_ERR_BADMAGIC,
- * -FDT_ERR_BADOFFSET,
- * -FDT_ERR_BADPATH,
- * -FDT_ERR_BADVERSION,
- * -FDT_ERR_BADSTRUCTURE,
- * -FDT_ERR_BADSTATE,
- * -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_overlay_apply(void *fdt, void *fdto);
-
-/**********************************************************************/
-/* Debugging / informational functions */
-/**********************************************************************/
-
-#ifndef SWIG /* Not available in Python */
-const char *fdt_strerror(int errval);
-
-/**
- * fdt_remove_unused_strings() - Remove any unused strings from an FDT
- *
- * This creates a new device tree in @new with unused strings removed. The
- * called can then use fdt_pack() to minimise the space consumed.
- *
- * @old: Old device tree blog
- * @new: Place to put new device tree blob, which must be as large as
- * @old
- * @return
- * 0, on success
- * -FDT_ERR_BADOFFSET, corrupt device tree
- * -FDT_ERR_NOSPACE, out of space, which should not happen unless there
- * is something very wrong with the device tree input
- */
-int fdt_remove_unused_strings(const void *old, void *new);
-
-struct fdt_region {
- int offset;
- int size;
-};
-
-/*
- * Flags for fdt_find_regions()
- *
- * Add a region for the string table (always the last region)
- */
-#define FDT_REG_ADD_STRING_TAB (1 << 0)
-
-/*
- * Add all supernodes of a matching node/property, useful for creating a
- * valid subset tree
- */
-#define FDT_REG_SUPERNODES (1 << 1)
-
-/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */
-#define FDT_REG_DIRECT_SUBNODES (1 << 2)
-
-/* Add all subnodes of a matching node */
-#define FDT_REG_ALL_SUBNODES (1 << 3)
-
-/* Add a region for the mem_rsvmap table (always the first region) */
-#define FDT_REG_ADD_MEM_RSVMAP (1 << 4)
-
-/* Indicates what an fdt part is (node, property, value) */
-#define FDT_IS_NODE (1 << 0)
-#define FDT_IS_PROP (1 << 1)
-#define FDT_IS_VALUE (1 << 2) /* not supported */
-#define FDT_IS_COMPAT (1 << 3) /* used internally */
-#define FDT_NODE_HAS_PROP (1 << 4) /* node contains prop */
-
-#define FDT_ANY_GLOBAL (FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \
- FDT_IS_COMPAT)
-#define FDT_IS_ANY 0x1f /* all the above */
-
-/* We set a reasonable limit on the number of nested nodes */
-#define FDT_MAX_DEPTH 32
-
-/* Decribes what we want to include from the current tag */
-enum want_t {
- WANT_NOTHING,
- WANT_NODES_ONLY, /* No properties */
- WANT_NODES_AND_PROPS, /* Everything for one level */
- WANT_ALL_NODES_AND_PROPS /* Everything for all levels */
-};
-
-/* Keeps track of the state at parent nodes */
-struct fdt_subnode_stack {
- int offset; /* Offset of node */
- enum want_t want; /* The 'want' value here */
- int included; /* 1 if we included this node, 0 if not */
-};
-
-struct fdt_region_ptrs {
- int depth; /* Current tree depth */
- int done; /* What we have completed scanning */
- enum want_t want; /* What we are currently including */
- char *end; /* Pointer to end of full node path */
- int nextoffset; /* Next node offset to check */
-};
-
-/* The state of our finding algortihm */
-struct fdt_region_state {
- struct fdt_subnode_stack stack[FDT_MAX_DEPTH]; /* node stack */
- struct fdt_region *region; /* Contains list of regions found */
- int count; /* Numnber of regions found */
- const void *fdt; /* FDT blob */
- int max_regions; /* Maximum regions to find */
- int can_merge; /* 1 if we can merge with previous region */
- int start; /* Start position of current region */
- struct fdt_region_ptrs ptrs; /* Pointers for what we are up to */
-};
-
-/**
- * fdt_find_regions() - find regions in device tree
- *
- * Given a list of nodes to include and properties to exclude, find
- * the regions of the device tree which describe those included parts.
- *
- * The intent is to get a list of regions which will be invariant provided
- * those parts are invariant. For example, if you request a list of regions
- * for all nodes but exclude the property "data", then you will get the
- * same region contents regardless of any change to "data" properties.
- *
- * This function can be used to produce a byte-stream to send to a hashing
- * function to verify that critical parts of the FDT have not changed.
- *
- * Nodes which are given in 'inc' are included in the region list, as
- * are the names of the immediate subnodes nodes (but not the properties
- * or subnodes of those subnodes).
- *
- * For eaxample "/" means to include the root node, all root properties
- * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter
- * ensures that we capture the names of the subnodes. In a hashing situation
- * it prevents the root node from changing at all Any change to non-excluded
- * properties, names of subnodes or number of subnodes would be detected.
- *
- * When used with FITs this provides the ability to hash and sign parts of
- * the FIT based on different configurations in the FIT. Then it is
- * impossible to change anything about that configuration (include images
- * attached to the configuration), but it may be possible to add new
- * configurations, new images or new signatures within the existing
- * framework.
- *
- * Adding new properties to a device tree may result in the string table
- * being extended (if the new property names are different from those
- * already added). This function can optionally include a region for
- * the string table so that this can be part of the hash too.
- *
- * The device tree header is not included in the list.
- *
- * @fdt: Device tree to check
- * @inc: List of node paths to included
- * @inc_count: Number of node paths in list
- * @exc_prop: List of properties names to exclude
- * @exc_prop_count: Number of properties in exclude list
- * @region: Returns list of regions
- * @max_region: Maximum length of region list
- * @path: Pointer to a temporary string for the function to use for
- * building path names
- * @path_len: Length of path, must be large enough to hold the longest
- * path in the tree
- * @add_string_tab: 1 to add a region for the string table
- * @return number of regions in list. If this is >max_regions then the
- * region array was exhausted. You should increase max_regions and try
- * the call again.
- */
-int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
- char * const exc_prop[], int exc_prop_count,
- struct fdt_region region[], int max_regions,
- char *path, int path_len, int add_string_tab);
-
-/**
- * fdt_first_region() - find regions in device tree
- *
- * Given a nodes and properties to include and properties to exclude, find
- * the regions of the device tree which describe those included parts.
- *
- * The use for this function is twofold. Firstly it provides a convenient
- * way of performing a structure-aware grep of the tree. For example it is
- * possible to grep for a node and get all the properties associated with
- * that node. Trees can be subsetted easily, by specifying the nodes that
- * are required, and then writing out the regions returned by this function.
- * This is useful for small resource-constrained systems, such as boot
- * loaders, which want to use an FDT but do not need to know about all of
- * it.
- *
- * Secondly it makes it easy to hash parts of the tree and detect changes.
- * The intent is to get a list of regions which will be invariant provided
- * those parts are invariant. For example, if you request a list of regions
- * for all nodes but exclude the property "data", then you will get the
- * same region contents regardless of any change to "data" properties.
- *
- * This function can be used to produce a byte-stream to send to a hashing
- * function to verify that critical parts of the FDT have not changed.
- * Note that semantically null changes in order could still cause false
- * hash misses. Such reordering might happen if the tree is regenerated
- * from source, and nodes are reordered (the bytes-stream will be emitted
- * in a different order and mnay hash functions will detect this). However
- * if an existing tree is modified using libfdt functions, such as
- * fdt_add_subnode() and fdt_setprop(), then this problem is avoided.
- *
- * The nodes/properties to include/exclude are defined by a function
- * provided by the caller. This function is called for each node and
- * property, and must return:
- *
- * 0 - to exclude this part
- * 1 - to include this part
- * -1 - for FDT_IS_PROP only: no information is available, so include
- * if its containing node is included
- *
- * The last case is only used to deal with properties. Often a property is
- * included if its containing node is included - this is the case where
- * -1 is returned.. However if the property is specifically required to be
- * included/excluded, then 0 or 1 can be returned. Note that including a
- * property when the FDT_REG_SUPERNODES flag is given will force its
- * containing node to be included since it is not valid to have a property
- * that is not in a node.
- *
- * Using the information provided, the inclusion of a node can be controlled
- * either by a node name or its compatible string, or any other property
- * that the function can determine.
- *
- * As an example, including node "/" means to include the root node and all
- * root properties. A flag provides a way of also including supernodes (of
- * which there is none for the root node), and another flag includes
- * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and
- * FDT_END_NODE of all subnodes of /.
- *
- * The subnode feature helps in a hashing situation since it prevents the
- * root node from changing at all. Any change to non-excluded properties,
- * names of subnodes or number of subnodes would be detected.
- *
- * When used with FITs this provides the ability to hash and sign parts of
- * the FIT based on different configurations in the FIT. Then it is
- * impossible to change anything about that configuration (include images
- * attached to the configuration), but it may be possible to add new
- * configurations, new images or new signatures within the existing
- * framework.
- *
- * Adding new properties to a device tree may result in the string table
- * being extended (if the new property names are different from those
- * already added). This function can optionally include a region for
- * the string table so that this can be part of the hash too. This is always
- * the last region.
- *
- * The FDT also has a mem_rsvmap table which can also be included, and is
- * always the first region if so.
- *
- * The device tree header is not included in the region list. Since the
- * contents of the FDT are changing (shrinking, often), the caller will need
- * to regenerate the header anyway.
- *
- * @fdt: Device tree to check
- * @h_include: Function to call to determine whether to include a part or
- * not:
- *
- * @priv: Private pointer as passed to fdt_find_regions()
- * @fdt: Pointer to FDT blob
- * @offset: Offset of this node / property
- * @type: Type of this part, FDT_IS_...
- * @data: Pointer to data (node name, property name, compatible
- * string, value (not yet supported)
- * @size: Size of data, or 0 if none
- * @return 0 to exclude, 1 to include, -1 if no information is
- * available
- * @priv: Private pointer passed to h_include
- * @region: Returns list of regions, sorted by offset
- * @max_regions: Maximum length of region list
- * @path: Pointer to a temporary string for the function to use for
- * building path names
- * @path_len: Length of path, must be large enough to hold the longest
- * path in the tree
- * @flags: Various flags that control the region algortihm, see
- * FDT_REG_...
- * @return number of regions in list. If this is >max_regions then the
- * region array was exhausted. You should increase max_regions and try
- * the call again. Only the first max_regions elements are available in the
- * array.
- *
- * On error a -ve value is return, which can be:
- *
- * -FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags
- * -FDT_ERR_BADLAYOUT
- * -FDT_ERR_NOSPACE (path area is too small)
- */
-int fdt_first_region(const void *fdt,
- int (*h_include)(void *priv, const void *fdt, int offset,
- int type, const char *data, int size),
- void *priv, struct fdt_region *region,
- char *path, int path_len, int flags,
- struct fdt_region_state *info);
-
-/** fdt_next_region() - find next region
- *
- * See fdt_first_region() for full description. This function finds the
- * next region according to the provided parameters, which must be the same
- * as passed to fdt_first_region().
- *
- * This function can additionally return -FDT_ERR_NOTFOUND when there are no
- * more regions
- */
-int fdt_next_region(const void *fdt,
- int (*h_include)(void *priv, const void *fdt, int offset,
- int type, const char *data, int size),
- void *priv, struct fdt_region *region,
- char *path, int path_len, int flags,
- struct fdt_region_state *info);
-
-/**
- * fdt_add_alias_regions() - find aliases that point to existing regions
- *
- * Once a device tree grep is complete some of the nodes will be present
- * and some will have been dropped. This function checks all the alias nodes
- * to figure out which points point to nodes which are still present. These
- * aliases need to be kept, along with the nodes they reference.
- *
- * Given a list of regions function finds the aliases that still apply and
- * adds more regions to the list for these. This function is called after
- * fdt_next_region() has finished returning regions and requires the same
- * state.
- *
- * @fdt: Device tree file to reference
- * @region: List of regions that will be kept
- * @count: Number of regions
- * @max_regions: Number of entries that can fit in @region
- * @info: Region state as returned from fdt_next_region()
- * @return new number of regions in @region (i.e. count + the number added)
- * or -FDT_ERR_NOSPACE if there was not enough space.
- */
-int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
- int max_regions, struct fdt_region_state *info);
-#endif /* SWIG */
-
-#endif /* _LIBFDT_H */
* from hush: simple_itoa() was lifted from boa-0.93.15
*/
-#include <stdarg.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-
#include <common.h>
#include <charset.h>
+#include <efi_loader.h>
+#include <div64.h>
#include <uuid.h>
+#include <stdarg.h>
+#include <linux/ctype.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/string.h>
-#include <div64.h>
#define noinline __attribute__((noinline))
/* we use this so that we can do without the ctype library */
return buf;
}
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+static char *device_path_string(char *buf, char *end, void *dp, int field_width,
+ int precision, int flags)
+{
+ u16 *str;
+
+ /* If dp == NULL output the string '<NULL>' */
+ if (!dp)
+ return string16(buf, end, dp, field_width, precision, flags);
+
+ str = efi_dp_str((struct efi_device_path *)dp);
+ if (!str)
+ return ERR_PTR(-ENOMEM);
+
+ buf = string16(buf, end, str, field_width, precision, flags);
+ efi_free_pool(str);
+ return buf;
+}
+#endif
+
#ifdef CONFIG_CMD_NET
static const char hex_asc[] = "0123456789abcdef";
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
#endif
switch (*fmt) {
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+ case 'D':
+ return device_path_string(buf, end, ptr, field_width,
+ precision, flags);
+#endif
#ifdef CONFIG_CMD_NET
case 'a':
flags |= SPECIAL | ZEROPAD;
str = pointer(fmt + 1, str, end,
va_arg(args, void *),
field_width, precision, flags);
+ if (IS_ERR(str))
+ return PTR_ERR(str);
/* Skip all alphanumeric pointer suffixes */
while (isalnum(fmt[1]))
fmt++;
i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
va_end(args);
+ /* Handle error */
+ if (i <= 0)
+ return i;
/* Print the string */
puts(printbuffer);
return i;
*/
i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+ /* Handle error */
+ if (i <= 0)
+ return i;
/* Print the string */
puts(printbuffer);
return i;
CONFIG_ADDR_AUTO_INCR_BIT
CONFIG_ADDR_MAP
CONFIG_ADNPESC1
-CONFIG_ADP_AG101P
CONFIG_AEABI
CONFIG_AEMIF_CNTRL_BASE
CONFIG_ALTERA_SPI_IDLE_VAL
CONFIG_AM335X_USB1
CONFIG_AM335X_USB1_MODE
CONFIG_AM437X_USB2PHY2_HOST
-CONFIG_AMCORE
CONFIG_ANDES_PCU
CONFIG_ANDES_PCU_BASE
CONFIG_APBH_DMA
CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
CONFIG_ARM_THUMB
CONFIG_ARP_TIMEOUT
-CONFIG_ASTRO5373L
CONFIG_ASTRO_COFDMDUOS2
CONFIG_ASTRO_TWIN7S2
CONFIG_ASTRO_V512
CONFIG_BCH_CONST_PARAMS
CONFIG_BCH_CONST_T
CONFIG_BCM2835_GPIO
-CONFIG_BCM283X_MU_SERIAL
CONFIG_BIOSEMU
CONFIG_BITBANGMII_MULTI
CONFIG_BL1_OFFSET
CONFIG_CTL_JTAG
CONFIG_CTL_TBE
CONFIG_CUSTOMER_BOARD_SUPPORT
-CONFIG_CYRUS
CONFIG_D2NET_V2
CONFIG_DA850_AM18X_EVM
CONFIG_DA850_EVM_MAX_CPU_CLK
-CONFIG_DA850_LOWLEVEL
CONFIG_DA8XX_GPIO
-CONFIG_DAVINCI_SPI
CONFIG_DBAU1000
CONFIG_DBAU1X00
CONFIG_DBGU
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
-CONFIG_EXT4_WRITE
CONFIG_EXTRA_BOOTARGS
CONFIG_EXTRA_CLOCK
CONFIG_EXTRA_ENV
CONFIG_FSMC_NAND_BASE
CONFIG_FSMTDBLK
CONFIG_FSNOTIFY
-CONFIG_FS_EXT4
CONFIG_FS_POSIX_ACL
CONFIG_FTAHBC020S
CONFIG_FTAHBC020S_BASE
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
CONFIG_IDE_SWAP_IO
-CONFIG_IDS8313
CONFIG_IDT8T49N222A
CONFIG_ID_EEPROM
CONFIG_IMA
CONFIG_LYNXKDI
CONFIG_M41T94_SPI_CS
CONFIG_M520x
-CONFIG_M52277EVB
-CONFIG_M5253DEMO
-CONFIG_M5253EVBE
-CONFIG_M5275EVB
CONFIG_M5301x
-CONFIG_M54418TWR
CONFIG_M54451EVB
CONFIG_M54455EVB
CONFIG_MACB0_PHY
CONFIG_MACB2_PHY
CONFIG_MACB3_PHY
CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_DAVINCI_DA850_EVM
CONFIG_MACH_OMAPL138_LCDK
-CONFIG_MACH_SPECIFIC
CONFIG_MACH_TYPE
CONFIG_MACH_TYPE_COMPAT_REV
CONFIG_MACRESET_TIMEOUT
CONFIG_MONITOR_IS_IN_RAM
CONFIG_MP
CONFIG_MPC8308
-CONFIG_MPC8308RDB
-CONFIG_MPC8308_P1M
CONFIG_MPC8309
CONFIG_MPC830x
CONFIG_MPC8313
CONFIG_MPC832XEMDS
CONFIG_MPC832x
CONFIG_MPC8349
-CONFIG_MPC8349EMDS
CONFIG_MPC8349ITX
-CONFIG_MPC8349ITXGP
CONFIG_MPC834x
CONFIG_MPC8360
CONFIG_MPC837XEMDS
CONFIG_ODROID_REV_AIN
CONFIG_OFF_PADCONF
CONFIG_OF_
-CONFIG_OF_SPI
-CONFIG_OF_SPI_FLASH
CONFIG_OF_STDOUT_PATH
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
CONFIG_OMAP_USB2PHY2_HOST
CONFIG_OMAP_USB3PHY1_HOST
-CONFIG_OMAP_USB_PHY
CONFIG_ORIGEN
CONFIG_OS1_ENV_ADDR
CONFIG_OS2_ENV_ADDR
CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI
CONFIG_PIXIS_BRDCFG1_TDM
CONFIG_PIXIS_SGMII_CMD
-CONFIG_PL010_SERIAL
CONFIG_PL011_CLOCK
-CONFIG_PL011_SERIAL
CONFIG_PL011_SERIAL_RLCR
-CONFIG_PL01X_SERIAL
CONFIG_PL01x_PORTS
CONFIG_PLATFORM_ENV_SETTINGS
CONFIG_PLATINUM_BOARD
CONFIG_R8A66597_ENDIAN
CONFIG_R8A66597_LDRV
CONFIG_R8A66597_XTAL
-CONFIG_R8A7740
-CONFIG_R8A7790
-CONFIG_R8A7791
-CONFIG_R8A7792
-CONFIG_R8A7793
-CONFIG_R8A7794
CONFIG_RAMBOOT
CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOTCOMMAND_TFTP
CONFIG_ROCKCHIP_CHIP_TAG
CONFIG_ROCKCHIP_MAX_INIT_SIZE
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
-CONFIG_ROCKCHIP_USB2_PHY
CONFIG_ROM_STUBS
CONFIG_ROOTFS_OFFSET
CONFIG_ROOTPATH
CONFIG_SATA1
CONFIG_SATA2
CONFIG_SATA_ULI5288
-CONFIG_SBC8349
-CONFIG_SBC8548
-CONFIG_SBC8641D
CONFIG_SCF0403_LCD
CONFIG_SCIF
CONFIG_SCIF_A
CONFIG_SOC_AU1500
CONFIG_SOC_AU1550
CONFIG_SOC_AU1X00
-CONFIG_SOC_DA850
-CONFIG_SOC_DA8XX
CONFIG_SOC_DM355
CONFIG_SOC_DM365
CONFIG_SOC_DM644X
CONFIG_STM32_HSE_HZ
CONFIG_STM32_HZ
CONFIG_STM32_SERIAL
-CONFIG_STMARK2
CONFIG_STRIDER
CONFIG_STRIDER_CON
CONFIG_STRIDER_CON_DP
CONFIG_SUPPORT_EMMC_BOOT
CONFIG_SUPPORT_EMMC_RPMB
CONFIG_SUPPORT_RAW_INITRD
-CONFIG_SUPPORT_VFAT
CONFIG_SUVD3
CONFIG_SXNI855T
CONFIG_SYSFLAGS_ADDR
CONFIG_SYS_BOOTPARAMS_LEN
CONFIG_SYS_BOOTSZ
CONFIG_SYS_BOOT_BLOCK
-CONFIG_SYS_BOOT_GET_CMDLINE
-CONFIG_SYS_BOOT_GET_KBD
CONFIG_SYS_BOOT_RAMDISK_HIGH
CONFIG_SYS_BR0_64M
CONFIG_SYS_BR0_8M
CONFIG_SYS_DA850_DDR2_SDRCR
CONFIG_SYS_DA850_DDR2_SDTIMR
CONFIG_SYS_DA850_DDR2_SDTIMR2
-CONFIG_SYS_DA850_PLL0_PLLDIV1
-CONFIG_SYS_DA850_PLL0_PLLDIV2
-CONFIG_SYS_DA850_PLL0_PLLDIV3
-CONFIG_SYS_DA850_PLL0_PLLDIV4
-CONFIG_SYS_DA850_PLL0_PLLDIV5
-CONFIG_SYS_DA850_PLL0_PLLDIV6
-CONFIG_SYS_DA850_PLL0_PLLDIV7
CONFIG_SYS_DA850_PLL0_PLLM
-CONFIG_SYS_DA850_PLL0_POSTDIV
CONFIG_SYS_DA850_PLL0_PREDIV
-CONFIG_SYS_DA850_PLL1_PLLDIV1
-CONFIG_SYS_DA850_PLL1_PLLDIV2
-CONFIG_SYS_DA850_PLL1_PLLDIV3
CONFIG_SYS_DA850_PLL1_PLLM
-CONFIG_SYS_DA850_PLL1_POSTDIV
CONFIG_SYS_DA850_SYSCFG_SUSPSRC
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
CONFIG_SYS_DAVINCI_I2C_SLAVE
CONFIG_SYS_DSPI_CTAR5
CONFIG_SYS_DSPI_CTAR6
CONFIG_SYS_DSPI_CTAR7
-CONFIG_SYS_DV_CLKMODE
CONFIG_SYS_DV_NOR_BOOT_CFG
CONFIG_SYS_EBI_CFGR_VAL
CONFIG_SYS_EBI_CSA_VAL
CONFIG_SYS_OBIR
CONFIG_SYS_OHCI_BE_CONTROLLER
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-CONFIG_SYS_OMAP24_I2C_SLAVE
CONFIG_SYS_OMAP24_I2C_SLAVE1
CONFIG_SYS_OMAP24_I2C_SLAVE2
CONFIG_SYS_OMAP24_I2C_SLAVE3
CONFIG_SYS_OMAP24_I2C_SLAVE4
-CONFIG_SYS_OMAP24_I2C_SPEED
CONFIG_SYS_OMAP24_I2C_SPEED1
CONFIG_SYS_OMAP24_I2C_SPEED2
CONFIG_SYS_OMAP24_I2C_SPEED3
CONFIG_SYS_PCMCIA_IO_BASE
CONFIG_SYS_PCMCIA_MEM_ADDR
CONFIG_SYS_PCMCIA_MEM_SIZE
-CONFIG_SYS_PCMCIA_PBR0
-CONFIG_SYS_PCMCIA_PBR1
-CONFIG_SYS_PCMCIA_PBR2
-CONFIG_SYS_PCMCIA_PBR3
-CONFIG_SYS_PCMCIA_PBR4
-CONFIG_SYS_PCMCIA_PBR5
-CONFIG_SYS_PCMCIA_PBR6
-CONFIG_SYS_PCMCIA_PBR7
-CONFIG_SYS_PCMCIA_POR0
-CONFIG_SYS_PCMCIA_POR1
-CONFIG_SYS_PCMCIA_POR2
-CONFIG_SYS_PCMCIA_POR3
-CONFIG_SYS_PCMCIA_POR4
-CONFIG_SYS_PCMCIA_POR5
-CONFIG_SYS_PCMCIA_POR6
-CONFIG_SYS_PCMCIA_POR7
CONFIG_SYS_PDCNT
CONFIG_SYS_PEHLPAR
CONFIG_SYS_PEPAR
CONFIG_TPL_PAD_TO
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TPS6586X_POWER
-CONFIG_TQM834X
CONFIG_TRACE
CONFIG_TRACE_BUFFER_SIZE
CONFIG_TRACE_EARLY
CONFIG_TWL4030_INPUT
CONFIG_TWL4030_KEYPAD
CONFIG_TWL4030_LED
-CONFIG_TWL4030_USB
CONFIG_TWL6030_INPUT
CONFIG_TWL6030_POWER
CONFIG_TWR
CONFIG_USBID_ADDR
CONFIG_USBNET_DEV_ADDR
CONFIG_USBTTY
-CONFIG_USB_AM35X
CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_INVENTRA_DMA
CONFIG_USB_ISP1301_I2C_ADDR
CONFIG_USB_MAX_CONTROLLER_COUNT
-CONFIG_USB_MUSB_AM35X
CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-CONFIG_USB_MUSB_DSPS
-CONFIG_USB_MUSB_HCD
-CONFIG_USB_MUSB_OMAP2PLUS
-CONFIG_USB_MUSB_PIO_ONLY
CONFIG_USB_MUSB_TIMEOUT
CONFIG_USB_MUSB_TUSB6010
-CONFIG_USB_MUSB_UDC
CONFIG_USB_OHCI
CONFIG_USB_OHCI_EP93XX
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
CONFIG_USB_OHCI_SUNXI
-CONFIG_USB_OMAP3
CONFIG_USB_OTG
CONFIG_USB_OTG_BLACKLIST_HUB
CONFIG_USB_PHY_CFG_BASE
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
CONFIG_VCT_NOR
-CONFIG_VE8313
CONFIG_VERY_BIG_RAM
CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
CONFIG_XILINX_LL_TEMAC_CLK
CONFIG_XILINX_SPI_IDLE_VAL
CONFIG_XILINX_TB_WATCHDOG
-CONFIG_XPEDITE5140
-CONFIG_XPEDITE5200
-CONFIG_XPEDITE550X
CONFIG_XR16L2751
CONFIG_XSENGINE
CONFIG_XTFPGA
-#!/usr/bin/env python
+#!/usr/bin/env python2
"""
setup.py file for SWIG libfdt
data->targets[k] = pos->target;
k++;
} else {
- strcpy(header, " ");
+ sprintf(header, " ");
}
memcpy(buf + pos->offset, header, sizeof(header) - 1);
-#!/usr/bin/env python
+#!/usr/bin/env python2
#
# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com>
#
#define DEBUG
#include <common.h>
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+#include <efi_api.h>
+#endif
#include <display_options.h>
#include <version.h>
#define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
"and a lot more text to come"
+/* Test efi_loader specific printing */
+static void efi_ut_print(void)
+{
+#if defined(CONFIG_EFI_LOADER) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+ char str[10];
+ u8 buf[sizeof(struct efi_device_path_sd_mmc_path) +
+ sizeof(struct efi_device_path)];
+ u8 *pos = buf;
+ struct efi_device_path *dp_end;
+ struct efi_device_path_sd_mmc_path *dp_sd =
+ (struct efi_device_path_sd_mmc_path *)pos;
+
+ /* Create a device path for an SD card */
+ dp_sd->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp_sd->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SD;
+ dp_sd->dp.length = sizeof(struct efi_device_path_sd_mmc_path);
+ dp_sd->slot_number = 3;
+ pos += sizeof(struct efi_device_path_sd_mmc_path);
+ /* Append end node */
+ dp_end = (struct efi_device_path *)pos;
+ dp_end->type = DEVICE_PATH_TYPE_END;
+ dp_end->sub_type = DEVICE_PATH_SUB_TYPE_END;
+ dp_end->length = sizeof(struct efi_device_path);
+
+ snprintf(str, sizeof(str), "_%pD_", buf);
+ assert(!strcmp("_/SD(3)_", str));
+
+ /* NULL device path */
+ snprintf(str, sizeof(str), "_%pD_", NULL);
+ assert(!strcmp("_<NULL>_", str));
+#endif
+}
+
static int do_ut_print(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
assert(!strncmp(FAKE_BUILD_TAG, s + 9 + len, 12));
assert(!strcmp("\n\n", s + big_str_len - 3));
+ /* Test efi_loader specific printing */
+ efi_ut_print();
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
-#!/usr/bin/env python
+#!/usr/bin/env python2
# Copyright (c) 2015 Stephen Warren
# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
/easylogo/easylogo
/envcrc
/fdtgrep
+/file2include
/fit_check_sign
/fit_info
/gdb/gdbcont
hostprogs-y += dumpimage mkimage
hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
+hostprogs-$(CONFIG_CMD_BOOTEFI_SELFTEST) += file2include
+
FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
# The following files are synced with upstream DTC.
# Use synced versions from scripts/dtc/libfdt/.
-LIBFDT_SRCS_SYNCED := fdt.c fdt_wip.c fdt_sw.c fdt_strerror.c fdt_empty_tree.c \
- fdt_addresses.c fdt_overlay.c
+LIBFDT_SRCS_SYNCED := fdt.c fdt_wip.c fdt_sw.c fdt_rw.c \
+ fdt_strerror.c fdt_empty_tree.c fdt_addresses.c fdt_overlay.c
# The following files are locally modified for U-Boot (unfotunately).
# Use U-Boot own versions from lib/libfdt/.
-LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_rw.c fdt_region.c
+LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_region.c
LIBFDT_OBJS := $(addprefix libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_SYNCED))) \
$(addprefix lib/libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_UNSYNCED)))
mkimage-objs := $(dumpimage-mkimage-objs) mkimage.o
fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o
fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
+file2include-objs := file2include.o
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
# Define _GNU_SOURCE to obtain the getline prototype from stdio.h
#
-HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \
+HOST_EXTRACFLAGS += -include $(srctree)/include/compiler.h \
$(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \
-I$(srctree)/lib/libfdt \
-I$(srctree)/tools \
-#!/usr/bin/env python
+#!/usr/bin/env python2
#
# Copyright (c) 2012 The Chromium OS Authors.
#
-#!/usr/bin/python
+#!/usr/bin/env python2
#
# Copyright (C) 2016 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
int fw_env_flush(struct env_opts *opts)
{
- int ret;
-
if (!opts)
opts = &default_opts;
#include "../include/libfdt.h"
#include "../include/fdt_support.h"
+/**
+ * fdt_remove_unused_strings() - Remove any unused strings from an FDT
+ *
+ * This creates a new device tree in @new with unused strings removed. The
+ * called can then use fdt_pack() to minimise the space consumed.
+ *
+ * @old: Old device tree blog
+ * @new: Place to put new device tree blob, which must be as large as
+ * @old
+ * @return
+ * 0, on success
+ * -FDT_ERR_BADOFFSET, corrupt device tree
+ * -FDT_ERR_NOSPACE, out of space, which should not happen unless there
+ * is something very wrong with the device tree input
+ */
+int fdt_remove_unused_strings(const void *old, void *new);
+
int fit_check_sign(const void *working_fdt, const void *key);
#endif /* __FDT_HOST_H__ */
#include <assert.h>
#include <ctype.h>
+#include <errno.h>
#include <getopt.h>
+#include <fcntl.h>
+#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
-#include "../include/libfdt.h"
+#include "fdt_host.h"
#include "libfdt_internal.h"
/* Define DEBUG to get some debugging output on stderr */
--- /dev/null
+/*
+ * Convert a file image to a C define
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For testing EFI disk management we need an in memory image of
+ * a disk.
+ *
+ * The tool file2include converts a file to a C include. The file
+ * is separated into strings of 8 bytes. Only the non-zero strings
+ * are written to the include. The output format has been designed
+ * to maintain readability.
+ *
+ * As the disk image needed for testing contains mostly zeroes a high
+ * compression ratio can be attained.
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <malloc.h>
+
+/* Size of the blocks written to the compressed file */
+#define BLOCK_SIZE 8
+
+int main(int argc, char *argv[])
+{
+ FILE *file;
+ int ret;
+ unsigned char *buf;
+ size_t count, i, j;
+
+ /* Provide usage help */
+ if (argc != 2) {
+ printf("Usage:\n%s FILENAME\n", argv[0]);
+ return EXIT_FAILURE;
+ }
+ /* Open file */
+ file = fopen(argv[1], "r");
+ if (!file) {
+ perror("fopen");
+ return EXIT_FAILURE;
+ }
+ /* Get file length */
+ ret = fseek(file, 0, SEEK_END);
+ if (ret < 0) {
+ perror("fseek");
+ return EXIT_FAILURE;
+ }
+ count = ftell(file);
+ if (!count) {
+ fprintf(stderr, "File %s has length 0\n", argv[1]);
+ return EXIT_FAILURE;
+ }
+ rewind(file);
+ /* Read file */
+ buf = malloc(count);
+ if (!buf) {
+ perror("calloc");
+ return EXIT_FAILURE;
+ }
+ count = fread(buf, 1, count, file);
+
+ /* Generate output */
+ printf("/*\n");
+ printf(" * Non-zero %u byte strings of a disk image\n", BLOCK_SIZE);
+ printf(" *\n");
+ printf(" * Generated with tools/file2include\n");
+ printf(" *\n");
+ printf(" * SPDX-License-Identifier: GPL-2.0+\n");
+ printf(" */\n\n");
+ printf("#define EFI_ST_DISK_IMG { 0x%08zx, { \\\n", count);
+
+ for (i = 0; i < count; i += BLOCK_SIZE) {
+ int c = 0;
+
+ for (j = i; j < i + BLOCK_SIZE && j < count; ++j) {
+ if (buf[j])
+ c = 1;
+ }
+ if (!c)
+ continue;
+ printf("\t{0x%08zx, \"", i);
+ for (j = i; j < i + BLOCK_SIZE && j < count; ++j)
+ printf("\\x%02x", buf[j]);
+ printf("\"}, /* ");
+ for (j = i; j < i + BLOCK_SIZE && j < count; ++j) {
+ if (buf[j] >= 0x20 && buf[j] <= 0x7e)
+ printf("%c", buf[j]);
+ else
+ printf(".");
+ }
+ printf(" */ \\\n");
+ }
+ printf("\t{0, NULL} } }\n");
+
+ /* Release resources */
+ free(buf);
+ ret = fclose(file);
+ if (ret) {
+ perror("fclose");
+ return EXIT_FAILURE;
+ }
+ return EXIT_SUCCESS;
+}
*/
#include <ctype.h>
+#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <fcntl.h>
#include <getopt.h>
+#include <stdbool.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "os_support.h"
#include <errno.h>
#include <fcntl.h>
+#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */
+#include "fdt_host.h"
+#include "../../scripts/dtc/libfdt/fdt_rw.c"
+
+int fdt_remove_unused_strings(const void *old, void *new)
+{
+ const struct fdt_property *old_prop;
+ struct fdt_property *new_prop;
+ int size = fdt_totalsize(old);
+ int next_offset, offset;
+ const char *str;
+ int ret;
+ int tag = FDT_PROP;
+
+ /* Make a copy and remove the strings */
+ memcpy(new, old, size);
+ fdt_set_size_dt_strings(new, 0);
+
+ /* Add every property name back into the new string table */
+ for (offset = 0; tag != FDT_END; offset = next_offset) {
+ tag = fdt_next_tag(old, offset, &next_offset);
+ if (tag != FDT_PROP)
+ continue;
+ old_prop = fdt_get_property_by_offset(old, offset, NULL);
+ new_prop = (struct fdt_property *)(unsigned long)
+ fdt_get_property_by_offset(new, offset, NULL);
+ str = fdt_string(old, fdt32_to_cpu(old_prop->nameoff));
+ ret = _fdt_find_add_string(new, str);
+ if (ret < 0)
+ return ret;
+ new_prop->nameoff = cpu_to_fdt32(ret);
+ }
+
+ return 0;
+}
-#!/usr/bin/env python
+#!/usr/bin/env python2
#
# Copyright (c) 2014 Google, Inc
#
#include <errno.h>
#include <fcntl.h>
#include <limits.h>
+#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
echo -e "\nMarvell recovery image downloader for Armada SoC family."
echo -e "Command syntax:"
echo -e "\t$(basename $0) <port> <file> [2|4|8]"
- echo -e "\tport - serial port the target board connected to"
+ echo -e "\tport - serial port the target board is connected to"
echo -e "\tfile - recovery boot image for target download"
echo -e "\t2|4|8 - times to increase the default serial port speed by"
echo -e "For example - load the image over ttyUSB0 @ 460800 baud:"
echo -e "$(basename $0) /dev/ttyUSB0 /tmp/flash-image.bin 4\n"
echo -e "=====WARNING====="
- echo -e "- The speed-up option is not awailable in SoC families prior to A8K+"
+ echo -e "- The speed-up option is not available in SoC families prior to A8K+"
echo -e "- This utility is not compatible with Armada 37xx SoC family\n"
fi
sx -vv $file > $port < $port
#sx-at91 $port $file
-# return the port to the default speed
+# Return the port to the default speed
stty -F $port raw ignbrk time 5 $default_baudrate
# Optional - fire up Minicom
-minicom -D $port
+minicom -D $port -b $default_baudrate
toc++;
memset(toc, 0xff, sizeof(*toc));
- gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE,
+ gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE,
params->addr, 0);
if (strncmp(params->imagename, "byteswap", 8) == 0) {
return []
stdout = command.Output(get_maintainer, '--norolestats', fname)
- return stdout.splitlines()
+ lines = stdout.splitlines()
+ return [ x.replace('"', '') for x in lines ]
-#!/usr/bin/env python
+#!/usr/bin/env python2
#
# Copyright (c) 2011 The Chromium OS Authors.
#
-#!/usr/bin/python
+#!/usr/bin/env python2
# Script to create enums from datasheet register tables
#
projects / platform / kernel / u-boot.git / commitdiff