VERSION = 2023
PATCHLEVEL = 04
SUBLEVEL =
- EXTRAVERSION = -rc4
+ EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
ubootversion backup tests check pcheck qcheck tcheck \
- pylint pylint_err
+ pylint pylint_err _pip pip pip_test pip_release
config-targets := 0
mixed-targets := 0
# See modpost pattern 2
KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
+KBUILD_CFLAGS += $(call cc-disable-warning, deprecated-non-prototype)
endif
# These warnings generated too much noise in a regular build.
# Always append INPUTS so that arch config.mk's can add custom ones
INPUTS-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
-INPUTS-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
INPUTS-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
F=`basename $(srctree)` ; cd .. ; \
gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
+PHONY += _pip pip pip_release
+
+pip_release: PIP_ARGS="--real"
+pip_test: PIP_ARGS=""
+pip: PIP_ARGS="-n"
+
+pip pip_test pip_release: _pip
+
+_pip:
+ scripts/make_pip.sh u_boot_pylib ${PIP_ARGS}
+ scripts/make_pip.sh patman ${PIP_ARGS}
+ scripts/make_pip.sh buildman ${PIP_ARGS}
+ scripts/make_pip.sh dtoc ${PIP_ARGS}
+ scripts/make_pip.sh binman ${PIP_ARGS}
+
help:
@echo 'Cleaning targets:'
@echo ' clean - Remove most generated files but keep the config'
@echo " cfg - Don't build, just create the .cfg files"
@echo " envtools - Build only the target-side environment tools"
@echo ''
+ @echo 'PyPi / pip targets:'
+ @echo ' pip - Check building of PyPi packages'
+ @echo ' pip_test - Build PyPi pakages and upload to test server'
+ @echo ' pip_release - Build PyPi pakages and upload to release server'
+ @echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'
@echo ' coccicheck - Execute static code analysis with Coccinelle'
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
+ select ARCH_EARLY_INIT_R if ARM64
select DM
select DM_SERIAL
select DM_SPI
config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
select ARM_TWD_TIMER
+ select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
select CLK
select CLK_ZYNQ
select CPU_V7A
select SPL_TIMER if SPL
select SUPPORT_SPL
select TIMER
- imply ARCH_EARLY_INIT_R
imply BOARD_LATE_INIT
imply CMD_CLK
imply CMD_DM
imply ADC
imply CMD_DM
imply DEBUG_UART_BOARD_INIT
- imply DISTRO_DEFAULTS
+ imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399
+ imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS
imply FAT_WRITE
imply SARADC_ROCKCHIP
imply SPL_SYSRESET
config {
u-boot,boot-led = "rock:red:power";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cru {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmc {
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer3 {
- compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
clock-frequency = <24000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
chosen {
- u-boot,spl-boot-order = &sdhci, &sdmmc0;
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
};
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
};
- &combphy1 {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-rates;
- };
-
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmucru {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&sdhci {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
&sdmmc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
flash: is25lp128@1 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <60000000>;
reg = <1>;
};
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
- reg = <0x006e0000 0x00010000>;
+ reg = <0x005e0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
+ reg = <0x005f0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
+ reg = <0x005f0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x0200f310 0x0 0x0 0x0 0x0>;
reg-shift = <2>;
clock-frequency = <58982400>;
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
+ reg = <0x005f0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
+ reg = <0x005f0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
help
Utilities for parsing PXE file formats.
+ config BOOT_DEFAULTS
+ bool # Common defaults for standard boot and distroboot
+ imply USE_BOOTCOMMAND
+ select CMD_ENV_EXISTS
+ select CMD_EXT2
+ select CMD_EXT4
+ select CMD_FAT
+ select CMD_FS_GENERIC
+ select CMD_PART if PARTITIONS
+ select CMD_DHCP if CMD_NET
+ select CMD_PING if CMD_NET
+ select CMD_PXE if CMD_NET
+ select SUPPORT_RAW_INITRD
+ select ENV_VARS_UBOOT_CONFIG
+ select CMD_BOOTI if ARM64
+ select CMD_BOOTZ if ARM && !ARM64
+ imply CMD_MII if NET
+ imply USB_STORAGE
+ imply EFI_PARTITION
+ imply ISO_PARTITION
+ help
+ These are not required but are commonly needed to support a good
+ selection of booting methods. Enable this to improve the capability
+ of U-Boot to boot various images. Currently much functionality is
+ tied to enabling the command that exercises it.
+
config BOOTSTD
bool "Standard boot support"
default y
as well as the "boot_targets" environment variable
config SPL_BOOTSTD
- bool "Standard boot support in VPL"
+ bool "Standard boot support in SPL"
depends on SPL && SPL_DM && SPL_OF_CONTROL && SPL_BLK
default y if VPL
help
bool "Select some common defaults for standard boot"
depends on BOOTSTD
imply USE_BOOTCOMMAND
- # Bring in some defaults which are generally needed. Boards can drop
- # these as needed to save code space. Bootstd does not generally require
- # the commands themselves to be enabled, but this is how some of the
- # functionality is controlled at present
- imply CMD_EXT2
- imply CMD_EXT4
- imply CMD_FAT
- imply CMD_FS_GENERIC
- imply CMD_PART
- imply CMD_DHCP if NET
- imply CMD_MII if NET
- imply CMD_PING if NET
- imply CMD_PXE if NET
- imply USB_STORAGE
- imply SUPPORT_RAW_INITRD
- imply ENV_VARS_UBOOT_CONFIG
- imply EFI_PARTITION
- imply ISO_PARTITION
+ select BOOT_DEFAULTS
help
These are not required but are commonly needed to support a good
selection of booting methods. Enable this to improve the capability
if BOOTMETH_VBE
+config BOOTMETH_VBE_REQUEST
+ bool "Support for serving VBE OS requests"
+ default y
+ help
+ Enables support for looking that the requests made by the
+ Operating System being booted. These requests result in additions to
+ the device tree /chosen node, added during the device tree fixup
+ phase.
+
+config SPL_BOOTMETH_VBE_REQUEST
+ bool "Support for serving VBE OS requests (SPL)"
+ depends on SPL
+ help
+ Enables support for looking that the requests made by the
+ Operating System being booted. These requests result in additions to
+ the device tree /chosen node, added during the device tree fixup
+ phase.
+
+ This is only useful if you are booting an OS direct from SPL.
+
config BOOTMETH_VBE_SIMPLE
bool "Bootdev support for VBE 'simple' method"
default y
depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ
depends on !(NIOS2 || SANDBOX || SH || XTENSA)
def_bool y
+ select LMB
help
Enable initrd_high functionality. If defined then the initrd_high
feature is enabled and the boot* ramdisk subcommand is enabled.
endmenu # Boot images
+ config DISTRO_DEFAULTS
+ bool "Select defaults suitable for booting general purpose Linux distributions"
+ select BOOT_DEFAULTS
+ select AUTO_COMPLETE
+ select CMDLINE_EDITING
+ select CMD_SYSBOOT
+ select HUSH_PARSER
+ select SYS_LONGHELP
+ help
+ Select this to enable various options and commands which are suitable
+ for building u-boot for booting general purpose Linux distributions.
+
menu "Boot timing"
config BOOTSTAGE
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=524288
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
-CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SYS_LOAD_ADDR=0x202000000
CONFIG_SYS_MEMTEST_START=0x200800000
CONFIG_SYS_MEMTEST_END=0x200ffffff
- CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_MEMTEST=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
+CONFIG_CMD_WRITE=y
CONFIG_CMD_CAT=y
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_TFTPPUT=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_RSASSA_PSS=y
CONFIG_FIT_CIPHER=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
+CONFIG_CMD_WRITE=y
CONFIG_CMD_AXI=y
CONFIG_CMD_CAT=y
CONFIG_CMD_SETEXPR_FMT=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_FONT_SUN12X22=y
CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_FONT_SUN12X22=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
- CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run scsi_init;usb start"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SMC=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
struct cpg_mssr_info *info, struct clk *parent)
{
const struct cpg_core_clk *core;
+ u8 shift;
int ret;
if (!renesas_clk_is_mod(clk)) {
return ret;
if (core->type == CLK_TYPE_GEN3_MDSEL) {
+ shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
parent->dev = clk->dev;
- parent->id = core->parent >> (priv->sscg ? 16 : 0);
+ parent->id = core->parent >> shift;
parent->id &= 0xffff;
return 0;
}
priv->cpg_pll_config;
u32 value, div;
u64 rate = 0;
+ u8 shift;
int ret;
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
"FIXED");
case CLK_TYPE_GEN3_MDSEL:
- div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
+ shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
+ div = (core->div >> shift) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div;
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
- __func__, __LINE__,
- (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
+ __func__, __LINE__, (core->parent >> shift) & 0xffff,
div, rate);
return rate;
struct cpg_mssr_info *info =
(struct cpg_mssr_info *)dev_get_driver_data(dev);
fdt_addr_t rst_base;
- u32 cpg_mode;
int ret;
priv->base = dev_read_addr_ptr(dev);
if (rst_base == FDT_ADDR_T_NONE)
return -EINVAL;
- cpg_mode = readl(rst_base + info->reset_modemr_offset);
+ priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config =
- (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
+ (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;
- priv->sscg = !(cpg_mode & BIT(12));
-
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
priv->info->status_regs = mstpsr;
priv->info->control_regs = smstpcr;
{
struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
struct gen3_clk_priv *priv = dev_get_priv(cdev);
- unsigned int reg = reset_ctl->id / 32;
- unsigned int bit = reset_ctl->id % 32;
+ unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
+ unsigned int reg = packed_id / 32;
+ unsigned int bit = packed_id % 32;
u32 bitmask = BIT(bit);
writel(bitmask, priv->base + priv->info->reset_regs[reg]);
{
struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
struct gen3_clk_priv *priv = dev_get_priv(cdev);
- unsigned int reg = reset_ctl->id / 32;
- unsigned int bit = reset_ctl->id % 32;
+ unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
+ unsigned int reg = packed_id / 32;
+ unsigned int bit = packed_id % 32;
u32 bitmask = BIT(bit);
writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]);
projects / platform / kernel / u-boot.git / commitdiff