1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
416 config SYS_THUMB_BUILD
417 bool "Build U-Boot using the Thumb instruction set"
420 Use this flag to build U-Boot using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config SPL_SYS_THUMB_BUILD
426 bool "Build SPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on !ARM64 && SPL
430 Use this flag to build SPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
435 config TPL_SYS_THUMB_BUILD
436 bool "Build TPL using the Thumb instruction set"
437 default y if SYS_THUMB_BUILD
438 depends on TPL && !ARM64
440 Use this flag to build TPL using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
446 bool "ARM PL310 L2 cache controller"
448 Enable support for ARM PL310 L2 cache controller in U-Boot
450 config SPL_SYS_L2_PL310
451 bool "ARM PL310 L2 cache controller in SPL"
453 Enable support for ARM PL310 L2 cache controller in SPL
455 config SYS_L2CACHE_OFF
458 If SoC does not support L2CACHE or one does not want to enable
459 L2CACHE, choose this option.
461 config ENABLE_ARM_SOC_BOOT0_HOOK
462 bool "prepare BOOT0 header"
464 If the SoC's BOOT0 requires a header area filled with (magic)
465 values, then choose this option, and create a file included as
466 <asm/arch/boot0.h> which contains the required assembler code.
468 config USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy"
471 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config SPL_USE_ARCH_MEMCPY
478 bool "Use an assembly optimized implementation of memcpy for SPL"
479 default y if USE_ARCH_MEMCPY
482 Enable the generation of an optimized version of memcpy.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config TPL_USE_ARCH_MEMCPY
487 bool "Use an assembly optimized implementation of memcpy for TPL"
488 default y if USE_ARCH_MEMCPY
491 Enable the generation of an optimized version of memcpy.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config USE_ARCH_MEMMOVE
496 bool "Use an assembly optimized implementation of memmove" if !ARM64
497 default USE_ARCH_MEMCPY if ARM64
500 Enable the generation of an optimized version of memmove.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SPL_USE_ARCH_MEMMOVE
505 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
506 default SPL_USE_ARCH_MEMCPY if ARM64
507 depends on SPL && ARM64
509 Enable the generation of an optimized version of memmove.
510 Such an implementation may be faster under some conditions
511 but may increase the binary size.
513 config TPL_USE_ARCH_MEMMOVE
514 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
515 default TPL_USE_ARCH_MEMCPY if ARM64
516 depends on TPL && ARM64
518 Enable the generation of an optimized version of memmove.
519 Such an implementation may be faster under some conditions
520 but may increase the binary size.
522 config USE_ARCH_MEMSET
523 bool "Use an assembly optimized implementation of memset"
525 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
527 Enable the generation of an optimized version of memset.
528 Such an implementation may be faster under some conditions
529 but may increase the binary size.
531 config SPL_USE_ARCH_MEMSET
532 bool "Use an assembly optimized implementation of memset for SPL"
533 default y if USE_ARCH_MEMSET
536 Enable the generation of an optimized version of memset.
537 Such an implementation may be faster under some conditions
538 but may increase the binary size.
540 config TPL_USE_ARCH_MEMSET
541 bool "Use an assembly optimized implementation of memset for TPL"
542 default y if USE_ARCH_MEMSET
545 Enable the generation of an optimized version of memset.
546 Such an implementation may be faster under some conditions
547 but may increase the binary size.
549 config ARM64_SUPPORT_AARCH32
550 bool "ARM64 system support AArch32 execution state"
552 default y if !TARGET_THUNDERX_88XX
554 This ARM64 system supports AArch32 execution state.
560 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
563 prompt "Target select"
568 select GPIO_EXTRA_HEADER
569 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
570 select SPL_SEPARATE_BSS if SPL
575 select GPIO_EXTRA_HEADER
576 select SPL_DM_SPI if SPL
579 Support for TI's DaVinci platform.
582 bool "Marvell Kirkwood"
583 select ARCH_MISC_INIT
584 select BOARD_EARLY_INIT_F
586 select GPIO_EXTRA_HEADER
590 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
591 select ARCH_EARLY_INIT_R if ARM64
596 select GPIO_EXTRA_HEADER
597 select SPL_DM_SPI if SPL
598 select SPL_DM_SPI_FLASH if SPL
599 select SPL_TIMER if SPL
600 select TIMER if !ARM64
609 select GPIO_EXTRA_HEADER
610 select SPL_SEPARATE_BSS if SPL
613 config TARGET_STV0991
614 bool "Support stv0991"
620 select GPIO_EXTRA_HEADER
627 bool "Broadcom BCM283X family"
631 select GPIO_EXTRA_HEADER
634 select SERIAL_SEARCH_ALL
639 bool "Broadcom BCM7XXX family"
642 select GPIO_EXTRA_HEADER
645 imply OF_HAS_PRIOR_STAGE
647 This enables support for Broadcom ARM-based set-top box
648 chipsets, including the 7445 family of chips.
651 bool "Broadcom broadband chip family"
656 config TARGET_VEXPRESS_CA9X4
657 bool "Support vexpress_ca9x4"
661 config TARGET_BCMCYGNUS
662 bool "Support bcmcygnus"
664 select GPIO_EXTRA_HEADER
667 imply BCM_SF2_ETH_GMAC
675 bool "Support Broadcom Northstar2"
677 select GPIO_EXTRA_HEADER
679 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
680 ARMv8 Cortex-A57 processors targeting a broad range of networking
684 bool "Support Broadcom NS3"
686 select BOARD_LATE_INIT
688 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
689 ARMv8 Cortex-A72 processors targeting a broad range of networking
693 bool "Samsung EXYNOS"
702 select GPIO_EXTRA_HEADER
703 imply SYS_THUMB_BUILD
708 bool "Samsung S5PC1XX"
714 select GPIO_EXTRA_HEADER
718 bool "Calxeda Highbank"
730 imply OF_HAS_PRIOR_STAGE
732 config ARCH_INTEGRATOR
733 bool "ARM Ltd. Integrator family"
736 select GPIO_EXTRA_HEADER
741 bool "Qualcomm IPQ40xx SoCs"
747 select GPIO_EXTRA_HEADER
761 select SYS_ARCH_TIMER
762 select SYS_THUMB_BUILD
768 bool "Texas Instruments' K3 Architecture"
773 config ARCH_OMAP2PLUS
776 select GPIO_EXTRA_HEADER
777 select SPL_BOARD_INIT if SPL
778 select SPL_STACK_R if SPL
780 imply TI_SYSC if DM && OF_CONTROL
782 imply SPL_SEPARATE_BSS
786 select GPIO_EXTRA_HEADER
787 imply DISTRO_DEFAULTS
790 Support for the Meson SoC family developed by Amlogic Inc.,
791 targeted at media players and tablet computers. We currently
792 support the S905 (GXBaby) 64-bit SoC.
797 select GPIO_EXTRA_HEADER
800 select SPL_LIBCOMMON_SUPPORT if SPL
801 select SPL_LIBGENERIC_SUPPORT if SPL
802 select SPL_OF_CONTROL if SPL
805 Support for the MediaTek SoCs family developed by MediaTek Inc.
806 Please refer to doc/README.mediatek for more information.
809 bool "NXP LPC32xx platform"
814 select GPIO_EXTRA_HEADER
820 bool "NXP i.MX8 platform"
822 select SYS_FSL_HAS_SEC
823 select SYS_FSL_SEC_COMPAT_4
824 select SYS_FSL_SEC_LE
827 select GPIO_EXTRA_HEADER
830 select ENABLE_ARM_SOC_BOOT0_HOOK
833 bool "NXP i.MX8M platform"
835 select GPIO_EXTRA_HEADER
837 select SYS_FSL_HAS_SEC
838 select SYS_FSL_SEC_COMPAT_4
839 select SYS_FSL_SEC_LE
842 select DM_EVENT if CLK
847 bool "NXP i.MX8ULP platform"
854 select GPIO_EXTRA_HEADER
860 bool "NXP i.MX9 platform"
866 select GPIO_EXTRA_HEADER
872 bool "NXP i.MXRT platform"
876 select GPIO_EXTRA_HEADER
882 bool "NXP i.MX23 family"
884 select GPIO_EXTRA_HEADER
890 bool "NXP i.MX28 family"
892 select GPIO_EXTRA_HEADER
898 bool "NXP i.MX31 family"
900 select GPIO_EXTRA_HEADER
905 select BOARD_POSTCLK_INIT
907 select GPIO_EXTRA_HEADER
909 select SYS_FSL_HAS_SEC
910 select SYS_FSL_SEC_COMPAT_4
911 select SYS_FSL_SEC_LE
912 select ROM_UNIFIED_SECTIONS
914 imply SYS_THUMB_BUILD
918 select ARCH_MISC_INIT
920 select GPIO_EXTRA_HEADER
923 select SYS_FSL_HAS_SEC
924 select SYS_FSL_SEC_COMPAT_4
925 select SYS_FSL_SEC_LE
926 imply BOARD_EARLY_INIT_F
928 imply SYS_THUMB_BUILD
932 select BOARD_POSTCLK_INIT
934 select GPIO_EXTRA_HEADER
937 select SYS_FSL_HAS_SEC
938 select SYS_FSL_SEC_COMPAT_4
939 select SYS_FSL_SEC_LE
940 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
942 imply SYS_THUMB_BUILD
943 imply SPL_SEPARATE_BSS
947 select BOARD_EARLY_INIT_F
949 select GPIO_EXTRA_HEADER
954 bool "Nexell S5P4418/S5P6818 SoC"
955 select ENABLE_ARM_SOC_BOOT0_HOOK
957 select GPIO_EXTRA_HEADER
960 bool "Support Nuvoton SoCs"
981 select LINUX_KERNEL_IMAGE_HEADER
982 select OF_BOARD_SETUP
986 select POSITION_INDEPENDENT
992 select SYSRESET_WATCHDOG
993 select SYSRESET_WATCHDOG_AUTO
997 imply DISTRO_DEFAULTS
998 imply OF_HAS_PRIOR_STAGE
1001 bool "Actions Semi OWL SoCs"
1004 select GPIO_EXTRA_HEADER
1009 select SYS_RELOC_GD_ENV_ADDR
1013 bool "QEMU Virtual Platform"
1022 imply OF_HAS_PRIOR_STAGE
1025 bool "Renesas ARM SoCs"
1028 select GPIO_EXTRA_HEADER
1029 imply BOARD_EARLY_INIT_F
1032 imply SYS_THUMB_BUILD
1033 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1035 config ARCH_SNAPDRAGON
1036 bool "Qualcomm Snapdragon SoCs"
1041 select GPIO_EXTRA_HEADER
1050 bool "Altera SOCFPGA family"
1051 select ARCH_EARLY_INIT_R
1052 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1053 select ARM64 if TARGET_SOCFPGA_SOC64
1054 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1058 select GPIO_EXTRA_HEADER
1059 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1061 select SPL_DM_RESET if DM_RESET
1062 select SPL_DM_SERIAL
1063 select SPL_LIBCOMMON_SUPPORT
1064 select SPL_LIBGENERIC_SUPPORT
1065 select SPL_OF_CONTROL
1066 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1072 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1074 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1075 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1085 imply SPL_DM_SPI_FLASH
1086 imply SPL_LIBDISK_SUPPORT
1088 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1089 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1090 imply SPL_SPI_FLASH_SUPPORT
1095 bool "Support sunxi (Allwinner) SoCs"
1098 select CMD_MMC if MMC
1099 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1103 select DM_I2C if I2C
1104 select DM_SPI if SPI
1105 select DM_SPI_FLASH if SPI
1107 select DM_MMC if MMC
1108 select DM_SCSI if SCSI
1110 select GPIO_EXTRA_HEADER
1111 select OF_BOARD_SETUP
1115 select SPECIFY_CONSOLE_INDEX
1116 select SPL_SEPARATE_BSS if SPL
1117 select SPL_STACK_R if SPL
1118 select SPL_SYS_MALLOC_SIMPLE if SPL
1119 select SPL_SYS_THUMB_BUILD if !ARM64
1122 select SYS_THUMB_BUILD if !ARM64
1123 select USB if DISTRO_DEFAULTS
1124 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1125 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1126 select SPL_USE_TINY_PRINTF
1128 select SYS_RELOC_GD_ENV_ADDR
1129 imply BOARD_LATE_INIT
1132 imply CMD_UBI if MTD_RAW_NAND
1133 imply DISTRO_DEFAULTS
1136 imply OF_LIBFDT_OVERLAY
1137 imply PRE_CONSOLE_BUFFER
1139 imply SPL_LIBCOMMON_SUPPORT
1140 imply SPL_LIBGENERIC_SUPPORT
1141 imply SPL_MMC if MMC
1145 imply SYSRESET_WATCHDOG
1146 imply SYSRESET_WATCHDOG_AUTO
1151 bool "ST-Ericsson U8500 Series"
1155 select DM_MMC if MMC
1157 select DM_USB_GADGET if DM_USB
1161 imply AB8500_USB_PHY
1162 imply ARM_PL180_MMCI
1167 imply NOMADIK_MTU_TIMER
1172 imply SYS_THUMB_BUILD
1173 imply SYSRESET_SYSCON
1176 bool "Support Xilinx Versal Platform"
1180 select DM_MMC if MMC
1185 imply BOARD_LATE_INIT
1186 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1188 config ARCH_VERSAL_NET
1189 bool "Support Xilinx Versal NET Platform"
1193 select DM_MMC if MMC
1196 imply BOARD_LATE_INIT
1197 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1200 bool "Freescale Vybrid"
1202 select GPIO_EXTRA_HEADER
1203 select IOMUX_SHARE_CONF_REG
1205 select SYS_FSL_ERRATUM_ESDHC111
1210 bool "Xilinx Zynq based platform"
1211 select ARM_TWD_TIMER
1212 select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
1216 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1218 select DM_MMC if MMC
1224 select SPL_BOARD_INIT if SPL
1225 select SPL_CLK if SPL
1226 select SPL_DM if SPL
1227 select SPL_DM_SPI if SPL
1228 select SPL_DM_SPI_FLASH if SPL
1229 select SPL_OF_CONTROL if SPL
1230 select SPL_SEPARATE_BSS if SPL
1231 select SPL_TIMER if SPL
1234 imply BOARD_LATE_INIT
1238 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1241 config ARCH_ZYNQMP_R5
1242 bool "Xilinx ZynqMP R5 based platform"
1246 select DM_MMC if MMC
1253 bool "Xilinx ZynqMP based platform"
1257 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1259 select DM_MMC if MMC
1261 select DM_SPI if SPI
1262 select DM_SPI_FLASH if DM_SPI
1266 select SPL_BOARD_INIT if SPL
1267 select SPL_CLK if SPL
1268 select SPL_DM if SPL
1269 select SPL_DM_SPI if SPI && SPL_DM
1270 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1271 select SPL_DM_MAILBOX if SPL
1272 imply SPL_FIRMWARE if SPL
1273 select SPL_SEPARATE_BSS if SPL
1275 imply ZYNQMP_IPI if DM_MAILBOX
1277 imply BOARD_LATE_INIT
1279 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1283 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1287 select GPIO_EXTRA_HEADER
1288 imply DISTRO_DEFAULTS
1290 imply SPL_TIMER if SPL
1292 config ARCH_VEXPRESS64
1293 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1301 select MTD_NOR_FLASH if MTD
1302 select FLASH_CFI_DRIVER if MTD
1303 select ENV_IS_IN_FLASH if MTD
1304 imply DISTRO_DEFAULTS
1306 config TARGET_CORSTONE1000
1307 bool "Support Corstone1000 Platform"
1312 config TARGET_TOTAL_COMPUTE
1313 bool "Support Total Compute Platform"
1321 config TARGET_LS2080A_EMU
1322 bool "Support ls2080a_emu"
1325 select ARMV8_MULTIENTRY
1326 select FSL_DDR_SYNC_REFRESH
1327 select GPIO_EXTRA_HEADER
1329 Support for Freescale LS2080A_EMU platform.
1330 The LS2080A Development System (EMULATOR) is a pre-silicon
1331 development platform that supports the QorIQ LS2080A
1332 Layerscape Architecture processor.
1334 config TARGET_LS1088AQDS
1335 bool "Support ls1088aqds"
1338 select ARMV8_MULTIENTRY
1339 select ARCH_SUPPORT_TFABOOT
1340 select BOARD_LATE_INIT
1341 select GPIO_EXTRA_HEADER
1343 select FSL_DDR_INTERACTIVE if !SD_BOOT
1345 Support for NXP LS1088AQDS platform.
1346 The LS1088A Development System (QDS) is a high-performance
1347 development platform that supports the QorIQ LS1088A
1348 Layerscape Architecture processor.
1350 config TARGET_LS2080AQDS
1351 bool "Support ls2080aqds"
1354 select ARMV8_MULTIENTRY
1355 select ARCH_SUPPORT_TFABOOT
1356 select BOARD_LATE_INIT
1357 select GPIO_EXTRA_HEADER
1362 select FSL_DDR_INTERACTIVE if !SPL
1364 Support for Freescale LS2080AQDS platform.
1365 The LS2080A Development System (QDS) is a high-performance
1366 development platform that supports the QorIQ LS2080A
1367 Layerscape Architecture processor.
1369 config TARGET_LS2080ARDB
1370 bool "Support ls2080ardb"
1373 select ARMV8_MULTIENTRY
1374 select ARCH_SUPPORT_TFABOOT
1375 select BOARD_LATE_INIT
1378 select FSL_DDR_INTERACTIVE if !SPL
1379 select GPIO_EXTRA_HEADER
1383 Support for Freescale LS2080ARDB platform.
1384 The LS2080A Reference design board (RDB) is a high-performance
1385 development platform that supports the QorIQ LS2080A
1386 Layerscape Architecture processor.
1388 config TARGET_LS2081ARDB
1389 bool "Support ls2081ardb"
1392 select ARMV8_MULTIENTRY
1393 select BOARD_LATE_INIT
1394 select GPIO_EXTRA_HEADER
1397 Support for Freescale LS2081ARDB platform.
1398 The LS2081A Reference design board (RDB) is a high-performance
1399 development platform that supports the QorIQ LS2081A/LS2041A
1400 Layerscape Architecture processor.
1402 config TARGET_LX2160ARDB
1403 bool "Support lx2160ardb"
1406 select ARMV8_MULTIENTRY
1407 select ARCH_SUPPORT_TFABOOT
1408 select BOARD_LATE_INIT
1409 select GPIO_EXTRA_HEADER
1411 Support for NXP LX2160ARDB platform.
1412 The lx2160ardb (LX2160A Reference design board (RDB)
1413 is a high-performance development platform that supports the
1414 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1416 config TARGET_LX2160AQDS
1417 bool "Support lx2160aqds"
1420 select ARMV8_MULTIENTRY
1421 select ARCH_SUPPORT_TFABOOT
1422 select BOARD_LATE_INIT
1423 select GPIO_EXTRA_HEADER
1425 Support for NXP LX2160AQDS platform.
1426 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1427 is a high-performance development platform that supports the
1428 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1430 config TARGET_LX2162AQDS
1431 bool "Support lx2162aqds"
1433 select ARCH_MISC_INIT
1435 select ARMV8_MULTIENTRY
1436 select ARCH_SUPPORT_TFABOOT
1437 select BOARD_LATE_INIT
1438 select GPIO_EXTRA_HEADER
1440 Support for NXP LX2162AQDS platform.
1441 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1444 bool "Support HiKey 96boards Consumer Edition Platform"
1449 select GPIO_EXTRA_HEADER
1452 select SPECIFY_CONSOLE_INDEX
1455 Support for HiKey 96boards platform. It features a HI6220
1456 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1458 config TARGET_HIKEY960
1459 bool "Support HiKey960 96boards Consumer Edition Platform"
1463 select GPIO_EXTRA_HEADER
1468 Support for HiKey960 96boards platform. It features a HI3660
1469 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1471 config TARGET_POPLAR
1472 bool "Support Poplar 96boards Enterprise Edition Platform"
1476 select GPIO_EXTRA_HEADER
1481 Support for Poplar 96boards EE platform. It features a HI3798cv200
1482 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1483 making it capable of running any commercial set-top solution based on
1486 config TARGET_LS1012AQDS
1487 bool "Support ls1012aqds"
1490 select ARCH_SUPPORT_TFABOOT
1491 select BOARD_LATE_INIT
1492 select GPIO_EXTRA_HEADER
1494 Support for Freescale LS1012AQDS platform.
1495 The LS1012A Development System (QDS) is a high-performance
1496 development platform that supports the QorIQ LS1012A
1497 Layerscape Architecture processor.
1499 config TARGET_LS1012ARDB
1500 bool "Support ls1012ardb"
1503 select ARCH_SUPPORT_TFABOOT
1504 select BOARD_LATE_INIT
1505 select GPIO_EXTRA_HEADER
1509 Support for Freescale LS1012ARDB platform.
1510 The LS1012A Reference design board (RDB) is a high-performance
1511 development platform that supports the QorIQ LS1012A
1512 Layerscape Architecture processor.
1514 config TARGET_LS1012A2G5RDB
1515 bool "Support ls1012a2g5rdb"
1518 select ARCH_SUPPORT_TFABOOT
1519 select BOARD_LATE_INIT
1520 select GPIO_EXTRA_HEADER
1523 Support for Freescale LS1012A2G5RDB platform.
1524 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1525 development platform that supports the QorIQ LS1012A
1526 Layerscape Architecture processor.
1528 config TARGET_LS1012AFRWY
1529 bool "Support ls1012afrwy"
1532 select ARCH_SUPPORT_TFABOOT
1533 select BOARD_LATE_INIT
1534 select GPIO_EXTRA_HEADER
1538 Support for Freescale LS1012AFRWY platform.
1539 The LS1012A FRWY board (FRWY) is a high-performance
1540 development platform that supports the QorIQ LS1012A
1541 Layerscape Architecture processor.
1543 config TARGET_LS1012AFRDM
1544 bool "Support ls1012afrdm"
1547 select ARCH_SUPPORT_TFABOOT
1548 select GPIO_EXTRA_HEADER
1550 Support for Freescale LS1012AFRDM platform.
1551 The LS1012A Freedom board (FRDM) is a high-performance
1552 development platform that supports the QorIQ LS1012A
1553 Layerscape Architecture processor.
1555 config TARGET_LS1028AQDS
1556 bool "Support ls1028aqds"
1559 select ARMV8_MULTIENTRY
1560 select ARCH_SUPPORT_TFABOOT
1561 select BOARD_LATE_INIT
1562 select GPIO_EXTRA_HEADER
1564 Support for Freescale LS1028AQDS platform
1565 The LS1028A Development System (QDS) is a high-performance
1566 development platform that supports the QorIQ LS1028A
1567 Layerscape Architecture processor.
1569 config TARGET_LS1028ARDB
1570 bool "Support ls1028ardb"
1573 select ARMV8_MULTIENTRY
1574 select ARCH_SUPPORT_TFABOOT
1575 select BOARD_LATE_INIT
1576 select GPIO_EXTRA_HEADER
1578 Support for Freescale LS1028ARDB platform
1579 The LS1028A Development System (RDB) is a high-performance
1580 development platform that supports the QorIQ LS1028A
1581 Layerscape Architecture processor.
1583 config TARGET_LS1088ARDB
1584 bool "Support ls1088ardb"
1587 select ARMV8_MULTIENTRY
1588 select ARCH_SUPPORT_TFABOOT
1589 select BOARD_LATE_INIT
1591 select FSL_DDR_INTERACTIVE if !SD_BOOT
1592 select GPIO_EXTRA_HEADER
1594 Support for NXP LS1088ARDB platform.
1595 The LS1088A Reference design board (RDB) is a high-performance
1596 development platform that supports the QorIQ LS1088A
1597 Layerscape Architecture processor.
1599 config TARGET_LS1021AQDS
1600 bool "Support ls1021aqds"
1602 select ARCH_SUPPORT_PSCI
1603 select BOARD_EARLY_INIT_F
1604 select BOARD_LATE_INIT
1606 select CPU_V7_HAS_NONSEC
1607 select CPU_V7_HAS_VIRT
1608 select LS1_DEEP_SLEEP
1609 select PEN_ADDR_BIG_ENDIAN
1612 select FSL_DDR_INTERACTIVE
1613 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1614 select GPIO_EXTRA_HEADER
1615 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1618 config TARGET_LS1021ATWR
1619 bool "Support ls1021atwr"
1621 select ARCH_SUPPORT_PSCI
1622 select BOARD_EARLY_INIT_F
1623 select BOARD_LATE_INIT
1625 select CPU_V7_HAS_NONSEC
1626 select CPU_V7_HAS_VIRT
1627 select LS1_DEEP_SLEEP
1628 select PEN_ADDR_BIG_ENDIAN
1630 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1631 select GPIO_EXTRA_HEADER
1634 config TARGET_PG_WCOM_SELI8
1635 bool "Support Hitachi-Powergrids SELI8 service unit card"
1637 select ARCH_SUPPORT_PSCI
1638 select BOARD_EARLY_INIT_F
1639 select BOARD_LATE_INIT
1641 select CPU_V7_HAS_NONSEC
1642 select CPU_V7_HAS_VIRT
1644 select FSL_DDR_INTERACTIVE
1645 select GPIO_EXTRA_HEADER
1649 Support for Hitachi-Powergrids SELI8 service unit card.
1650 SELI8 is a QorIQ LS1021a based service unit card used
1651 in XMC20 and FOX615 product families.
1653 config TARGET_PG_WCOM_EXPU1
1654 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1656 select ARCH_SUPPORT_PSCI
1657 select BOARD_EARLY_INIT_F
1658 select BOARD_LATE_INIT
1660 select CPU_V7_HAS_NONSEC
1661 select CPU_V7_HAS_VIRT
1663 select FSL_DDR_INTERACTIVE
1667 Support for Hitachi-Powergrids EXPU1 service unit card.
1668 EXPU1 is a QorIQ LS1021a based service unit card used
1669 in XMC20 and FOX615 product families.
1671 config TARGET_LS1021ATSN
1672 bool "Support ls1021atsn"
1674 select ARCH_SUPPORT_PSCI
1675 select BOARD_EARLY_INIT_F
1676 select BOARD_LATE_INIT
1678 select CPU_V7_HAS_NONSEC
1679 select CPU_V7_HAS_VIRT
1680 select LS1_DEEP_SLEEP
1682 select GPIO_EXTRA_HEADER
1685 config TARGET_LS1021AIOT
1686 bool "Support ls1021aiot"
1688 select ARCH_SUPPORT_PSCI
1689 select BOARD_LATE_INIT
1691 select CPU_V7_HAS_NONSEC
1692 select CPU_V7_HAS_VIRT
1693 select PEN_ADDR_BIG_ENDIAN
1695 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1696 select GPIO_EXTRA_HEADER
1699 Support for Freescale LS1021AIOT platform.
1700 The LS1021A Freescale board (IOT) is a high-performance
1701 development platform that supports the QorIQ LS1021A
1702 Layerscape Architecture processor.
1704 config TARGET_LS1043AQDS
1705 bool "Support ls1043aqds"
1708 select ARMV8_MULTIENTRY
1709 select ARCH_SUPPORT_TFABOOT
1710 select BOARD_EARLY_INIT_F
1711 select BOARD_LATE_INIT
1713 select FSL_DDR_INTERACTIVE if !SPL
1714 select FSL_DSPI if !SPL_NO_DSPI
1715 select DM_SPI_FLASH if FSL_DSPI
1716 select GPIO_EXTRA_HEADER
1720 Support for Freescale LS1043AQDS platform.
1722 config TARGET_LS1043ARDB
1723 bool "Support ls1043ardb"
1726 select ARMV8_MULTIENTRY
1727 select ARCH_SUPPORT_TFABOOT
1728 select BOARD_EARLY_INIT_F
1729 select BOARD_LATE_INIT
1731 select FSL_DSPI if !SPL_NO_DSPI
1732 select DM_SPI_FLASH if FSL_DSPI
1733 select GPIO_EXTRA_HEADER
1735 Support for Freescale LS1043ARDB platform.
1737 config TARGET_LS1046AQDS
1738 bool "Support ls1046aqds"
1741 select ARMV8_MULTIENTRY
1742 select ARCH_SUPPORT_TFABOOT
1743 select BOARD_EARLY_INIT_F
1744 select BOARD_LATE_INIT
1745 select DM_SPI_FLASH if DM_SPI
1747 select FSL_DDR_BIST if !SPL
1748 select FSL_DDR_INTERACTIVE if !SPL
1749 select FSL_DDR_INTERACTIVE if !SPL
1750 select GPIO_EXTRA_HEADER
1753 Support for Freescale LS1046AQDS platform.
1754 The LS1046A Development System (QDS) is a high-performance
1755 development platform that supports the QorIQ LS1046A
1756 Layerscape Architecture processor.
1758 config TARGET_LS1046ARDB
1759 bool "Support ls1046ardb"
1762 select ARMV8_MULTIENTRY
1763 select ARCH_SUPPORT_TFABOOT
1764 select BOARD_EARLY_INIT_F
1765 select BOARD_LATE_INIT
1766 select DM_SPI_FLASH if DM_SPI
1767 select POWER_MC34VR500
1770 select FSL_DDR_INTERACTIVE if !SPL
1771 select GPIO_EXTRA_HEADER
1774 Support for Freescale LS1046ARDB platform.
1775 The LS1046A Reference Design Board (RDB) is a high-performance
1776 development platform that supports the QorIQ LS1046A
1777 Layerscape Architecture processor.
1779 config TARGET_LS1046AFRWY
1780 bool "Support ls1046afrwy"
1783 select ARMV8_MULTIENTRY
1784 select ARCH_SUPPORT_TFABOOT
1785 select BOARD_EARLY_INIT_F
1786 select BOARD_LATE_INIT
1787 select DM_SPI_FLASH if DM_SPI
1788 select GPIO_EXTRA_HEADER
1791 Support for Freescale LS1046AFRWY platform.
1792 The LS1046A Freeway Board (FRWY) is a high-performance
1793 development platform that supports the QorIQ LS1046A
1794 Layerscape Architecture processor.
1800 select ARMV8_MULTIENTRY
1815 select GPIO_EXTRA_HEADER
1816 select SPL_DM if SPL
1817 select SPL_DM_SPI if SPL
1818 select SPL_DM_SPI_FLASH if SPL
1819 select SPL_DM_I2C if SPL
1820 select SPL_DM_MMC if SPL
1821 select SPL_DM_SERIAL if SPL
1823 Support for Kontron SMARC-sAL28 board.
1826 bool "Support ten64"
1828 select ARCH_MISC_INIT
1830 select ARMV8_MULTIENTRY
1831 select ARCH_SUPPORT_TFABOOT
1832 select BOARD_LATE_INIT
1834 select FSL_DDR_INTERACTIVE if !SD_BOOT
1835 select GPIO_EXTRA_HEADER
1837 Support for Traverse Technologies Ten64 board, based
1840 config ARCH_UNIPHIER
1841 bool "Socionext UniPhier SoCs"
1842 select BOARD_LATE_INIT
1850 select OF_BOARD_SETUP
1854 select SPL_BOARD_INIT if SPL
1855 select SPL_DM if SPL
1856 select SPL_LIBCOMMON_SUPPORT if SPL
1857 select SPL_LIBGENERIC_SUPPORT if SPL
1858 select SPL_OF_CONTROL if SPL
1859 select SPL_PINCTRL if SPL
1862 imply DISTRO_DEFAULTS
1865 Support for UniPhier SoC family developed by Socionext Inc.
1866 (formerly, System LSI Business Division of Panasonic Corporation)
1868 config ARCH_SYNQUACER
1869 bool "Socionext SynQuacer SoCs"
1875 select SYSRESET_PSCI
1878 Support for SynQuacer SoC family developed by Socionext Inc.
1879 This SoC is used on 96boards EE DeveloperBox.
1882 bool "Support STMicroelectronics STM32 MCU with cortex M"
1889 bool "Support STMicroelectronics SoCs"
1898 Support for STMicroelectronics STiH407/10 SoC family.
1899 This SoC is used on Linaro 96Board STiH410-B2260
1902 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1903 select ARCH_MISC_INIT
1904 select ARCH_SUPPORT_TFABOOT
1905 select BOARD_LATE_INIT
1914 select OF_SYSTEM_SETUP
1919 select SYS_THUMB_BUILD
1923 imply OF_LIBFDT_OVERLAY
1924 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1928 Support for STM32MP SoC family developed by STMicroelectronics,
1929 MPUs based on ARM cortex A core
1930 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1931 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1933 SPL is the unsecure FSBL for the basic boot chain.
1935 config ARCH_ROCKCHIP
1936 bool "Support Rockchip SoCs"
1938 select BINMAN if SPL_OPTEE || SPL
1948 select ENABLE_ARM_SOC_BOOT0_HOOK
1951 select SPL_DM if SPL
1952 select SPL_DM_SPI if SPL
1953 select SPL_DM_SPI_FLASH if SPL
1955 select SYS_THUMB_BUILD if !ARM64
1958 imply DEBUG_UART_BOARD_INIT
1959 imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399
1960 imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS
1962 imply SARADC_ROCKCHIP
1964 imply SPL_SYS_MALLOC_SIMPLE
1967 imply USB_FUNCTION_FASTBOOT
1969 config ARCH_OCTEONTX
1970 bool "Support OcteonTX SoCs"
1973 select GPIO_EXTRA_HEADER
1977 select BOARD_LATE_INIT
1978 select SYS_CACHE_SHIFT_7
1979 select SYS_PCI_64BIT if PCI
1980 imply OF_HAS_PRIOR_STAGE
1982 config ARCH_OCTEONTX2
1983 bool "Support OcteonTX2 SoCs"
1986 select GPIO_EXTRA_HEADER
1990 select BOARD_LATE_INIT
1991 select SYS_CACHE_SHIFT_7
1992 select SYS_PCI_64BIT if PCI
1993 imply OF_HAS_PRIOR_STAGE
1995 config TARGET_THUNDERX_88XX
1996 bool "Support ThunderX 88xx"
1998 select GPIO_EXTRA_HEADER
2001 select SYS_CACHE_SHIFT_7
2004 bool "Support Aspeed SoCs"
2009 config TARGET_DURIAN
2010 bool "Support Phytium Durian Platform"
2012 select GPIO_EXTRA_HEADER
2014 Support for durian platform.
2015 It has 2GB Sdram, uart and pcie.
2017 config TARGET_POMELO
2018 bool "Support Phytium Pomelo Platform"
2032 Support for pomelo platform.
2033 It has 8GB Sdram, uart and pcie.
2035 config TARGET_PRESIDIO_ASIC
2036 bool "Support Cortina Presidio ASIC Platform"
2040 config TARGET_XENGUEST_ARM64
2041 bool "Xen guest ARM64"
2045 select LINUX_KERNEL_IMAGE_HEADER
2048 imply OF_HAS_PRIOR_STAGE
2051 bool "Support HPE GXP SoCs"
2058 config SUPPORT_PASSING_ATAGS
2059 bool "Support pre-devicetree ATAG-based booting"
2061 imply SETUP_MEMORY_TAGS
2063 Support for booting older Linux kernels, using ATAGs rather than
2064 passing a devicetree. This is option is rarely used, and the
2065 semantics are defined at
2066 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2068 config SETUP_MEMORY_TAGS
2069 bool "Pass memory size information via ATAG"
2070 depends on SUPPORT_PASSING_ATAGS
2073 bool "Pass Linux kernel cmdline via ATAG"
2074 depends on SUPPORT_PASSING_ATAGS
2077 bool "Pass initrd starting point and size via ATAG"
2078 depends on SUPPORT_PASSING_ATAGS
2081 bool "Pass system revision via ATAG"
2082 depends on SUPPORT_PASSING_ATAGS
2085 bool "Pass system serial number via ATAG"
2086 depends on SUPPORT_PASSING_ATAGS
2088 config STATIC_MACH_TYPE
2089 bool "Statically define the Machine ID number"
2090 default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2092 When booting via ATAGs, enable this option if we know the correct
2093 machine ID number to use at compile time. Some systems will be
2094 passed the number dynamically by whatever loads U-Boot.
2097 int "Machine ID number"
2098 depends on STATIC_MACH_TYPE
2099 default 527 if TARGET_DS109
2100 default 1955 if TARGET_NOKIA_RX51
2101 default 3036 if TARGET_DS414
2102 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2104 When booting via ATAGs, the machine type must be passed as a number.
2105 For the full list see https://www.arm.linux.org.uk/developer/machines
2107 config ARCH_SUPPORT_TFABOOT
2111 bool "Support for booting from TF-A"
2112 depends on ARCH_SUPPORT_TFABOOT
2114 Some platforms support the setup of secure registers (for instance
2115 for CPU errata handling) or provide secure services like PSCI.
2116 Those services could also be provided by other firmware parts
2117 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2118 does not need to (and cannot) execute this code.
2119 Enabling this option will make a U-Boot binary that is relying
2120 on other firmware layers to provide secure functionality.
2122 config TI_SECURE_DEVICE
2123 bool "HS Device Type Support"
2124 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2126 If a high secure (HS) device type is being used, this config
2127 must be set. This option impacts various aspects of the
2128 build system (to create signed boot images that can be
2129 authenticated) and the code. See the doc/README.ti-secure
2130 file for further details.
2132 config SYS_KWD_CONFIG
2133 string "kwbimage config file path"
2134 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2135 default "arch/arm/mach-mvebu/kwbimage.cfg"
2137 Path within the source directory to the kwbimage.cfg file to use
2138 when packaging the U-Boot image for use.
2140 source "arch/arm/mach-apple/Kconfig"
2142 source "arch/arm/mach-aspeed/Kconfig"
2144 source "arch/arm/mach-at91/Kconfig"
2146 source "arch/arm/mach-bcm283x/Kconfig"
2148 source "arch/arm/mach-bcmbca/Kconfig"
2150 source "arch/arm/mach-bcmstb/Kconfig"
2152 source "arch/arm/mach-davinci/Kconfig"
2154 source "arch/arm/mach-exynos/Kconfig"
2156 source "arch/arm/mach-hpe/gxp/Kconfig"
2158 source "arch/arm/mach-highbank/Kconfig"
2160 source "arch/arm/mach-integrator/Kconfig"
2162 source "arch/arm/mach-ipq40xx/Kconfig"
2164 source "arch/arm/mach-k3/Kconfig"
2166 source "arch/arm/mach-keystone/Kconfig"
2168 source "arch/arm/mach-kirkwood/Kconfig"
2170 source "arch/arm/mach-lpc32xx/Kconfig"
2172 source "arch/arm/mach-mvebu/Kconfig"
2174 source "arch/arm/mach-octeontx/Kconfig"
2176 source "arch/arm/mach-octeontx2/Kconfig"
2178 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2180 source "arch/arm/mach-imx/mx3/Kconfig"
2182 source "arch/arm/mach-imx/mx5/Kconfig"
2184 source "arch/arm/mach-imx/mx6/Kconfig"
2186 source "arch/arm/mach-imx/mx7/Kconfig"
2188 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2190 source "arch/arm/mach-imx/imx8/Kconfig"
2192 source "arch/arm/mach-imx/imx8m/Kconfig"
2194 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2196 source "arch/arm/mach-imx/imx9/Kconfig"
2198 source "arch/arm/mach-imx/imxrt/Kconfig"
2200 source "arch/arm/mach-imx/mxs/Kconfig"
2202 source "arch/arm/mach-omap2/Kconfig"
2204 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2206 source "arch/arm/mach-orion5x/Kconfig"
2208 source "arch/arm/mach-owl/Kconfig"
2210 source "arch/arm/mach-rmobile/Kconfig"
2212 source "arch/arm/mach-meson/Kconfig"
2214 source "arch/arm/mach-mediatek/Kconfig"
2216 source "arch/arm/mach-qemu/Kconfig"
2218 source "arch/arm/mach-rockchip/Kconfig"
2220 source "arch/arm/mach-s5pc1xx/Kconfig"
2222 source "arch/arm/mach-snapdragon/Kconfig"
2224 source "arch/arm/mach-socfpga/Kconfig"
2226 source "arch/arm/mach-sti/Kconfig"
2228 source "arch/arm/mach-stm32/Kconfig"
2230 source "arch/arm/mach-stm32mp/Kconfig"
2232 source "arch/arm/mach-sunxi/Kconfig"
2234 source "arch/arm/mach-tegra/Kconfig"
2236 source "arch/arm/mach-u8500/Kconfig"
2238 source "arch/arm/mach-uniphier/Kconfig"
2240 source "arch/arm/cpu/armv7/vf610/Kconfig"
2242 source "arch/arm/mach-zynq/Kconfig"
2244 source "arch/arm/mach-zynqmp/Kconfig"
2246 source "arch/arm/mach-versal/Kconfig"
2248 source "arch/arm/mach-versal-net/Kconfig"
2250 source "arch/arm/mach-zynqmp-r5/Kconfig"
2252 source "arch/arm/cpu/armv7/Kconfig"
2254 source "arch/arm/cpu/armv8/Kconfig"
2256 source "arch/arm/mach-imx/Kconfig"
2258 source "arch/arm/mach-nexell/Kconfig"
2260 source "arch/arm/mach-npcm/Kconfig"
2262 source "board/armltd/total_compute/Kconfig"
2263 source "board/armltd/corstone1000/Kconfig"
2264 source "board/bosch/shc/Kconfig"
2265 source "board/bosch/guardian/Kconfig"
2266 source "board/Marvell/octeontx/Kconfig"
2267 source "board/Marvell/octeontx2/Kconfig"
2268 source "board/armltd/vexpress/Kconfig"
2269 source "board/armltd/vexpress64/Kconfig"
2270 source "board/cortina/presidio-asic/Kconfig"
2271 source "board/broadcom/bcmns3/Kconfig"
2272 source "board/cavium/thunderx/Kconfig"
2273 source "board/eets/pdu001/Kconfig"
2274 source "board/emulation/qemu-arm/Kconfig"
2275 source "board/freescale/ls2080aqds/Kconfig"
2276 source "board/freescale/ls2080ardb/Kconfig"
2277 source "board/freescale/ls1088a/Kconfig"
2278 source "board/freescale/ls1028a/Kconfig"
2279 source "board/freescale/ls1021aqds/Kconfig"
2280 source "board/freescale/ls1043aqds/Kconfig"
2281 source "board/freescale/ls1021atwr/Kconfig"
2282 source "board/freescale/ls1021atsn/Kconfig"
2283 source "board/freescale/ls1021aiot/Kconfig"
2284 source "board/freescale/ls1046aqds/Kconfig"
2285 source "board/freescale/ls1043ardb/Kconfig"
2286 source "board/freescale/ls1046ardb/Kconfig"
2287 source "board/freescale/ls1046afrwy/Kconfig"
2288 source "board/freescale/ls1012aqds/Kconfig"
2289 source "board/freescale/ls1012ardb/Kconfig"
2290 source "board/freescale/ls1012afrdm/Kconfig"
2291 source "board/freescale/lx2160a/Kconfig"
2292 source "board/grinn/chiliboard/Kconfig"
2293 source "board/hisilicon/hikey/Kconfig"
2294 source "board/hisilicon/hikey960/Kconfig"
2295 source "board/hisilicon/poplar/Kconfig"
2296 source "board/isee/igep003x/Kconfig"
2297 source "board/kontron/sl28/Kconfig"
2298 source "board/myir/mys_6ulx/Kconfig"
2299 source "board/samsung/common/Kconfig"
2300 source "board/siemens/common/Kconfig"
2301 source "board/seeed/npi_imx6ull/Kconfig"
2302 source "board/socionext/developerbox/Kconfig"
2303 source "board/st/stv0991/Kconfig"
2304 source "board/tcl/sl50/Kconfig"
2305 source "board/traverse/ten64/Kconfig"
2306 source "board/variscite/dart_6ul/Kconfig"
2307 source "board/vscom/baltos/Kconfig"
2308 source "board/phytium/durian/Kconfig"
2309 source "board/phytium/pomelo/Kconfig"
2310 source "board/xen/xenguest_arm64/Kconfig"
2312 source "arch/arm/Kconfig.debug"