mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE

CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index b3cbf9f..5ca307c 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -281,7 +281,7 @@ long int spd_sdram()
        /*
         * Set up LAWBAR for all of DDR.
         */
-       ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
        debug("DDR:bar=0x%08x\n", ecm->bar);
        debug("DDR:ar=0x%08x\n", ecm->ar);

diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
index e64b310..317e63e 100644 (file)
--- a/board/freescale/mpc8308rdb/sdram.c
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -33,7 +33,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                       CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+                       CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        sync();
 
-       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+       return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 5e074e3..090412d 100644 (file)
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -47,7 +47,7 @@ static long fixed_sdram(void)
        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
@@ -57,12 +57,12 @@ static long fixed_sdram(void)
         */
        __udelay(50000);
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[0].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
                        CSBNDS_EA);
        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 

diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index b9f94c8..2f0f29a 100644 (file)
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -44,7 +44,7 @@ static long fixed_sdram(void)
        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ea018e5..f14276f 100644 (file)
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -91,7 +91,7 @@ int fixed_sdram(void)
        u32 ddr_size = msize << 20;     /* DDR size in bytes */
        u32 ddr_size_log2 = __ilog2(ddr_size);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
@@ -112,12 +112,12 @@ int fixed_sdram(void)
        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[2].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
                                CSBNDS_EA_SHIFT) & CSBNDS_EA);
        im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index aaaea7c..81b3f00 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -37,14 +37,14 @@ int fixed_sdram(void)
 
        im->sysconf.ddrlaw[0].ar =
            LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[0].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
                                CSBNDS_EA_SHIFT) & CSBNDS_EA);
        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 

diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 09a046d..1692208 100644 (file)
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -252,7 +252,7 @@ int fixed_sdram(void)
        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
 #if (CONFIG_SYS_DDR_SIZE != 512)

diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index d9a47b9..18f396a 100644 (file)
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -95,7 +95,7 @@ int fixed_sdram(void)
        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;

diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 5ced8eb..3eb0e37 100644 (file)
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c
@@ -34,7 +34,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+                CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -62,7 +62,7 @@ static long fixed_sdram(void)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        sync();
 
-       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+       return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index a37ca8a..a66234a 100644 (file)
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+                (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
        sync();

diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
index 4118c01..baf70d8 100644 (file)
--- a/board/mpc8308_p1m/sdram.c
+++ b/board/mpc8308_p1m/sdram.c
@@ -29,7 +29,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-                       CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+                       CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
        out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -57,7 +57,7 @@ static long fixed_sdram(void)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        sync();
 
-       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+       return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 5584b3d..e51eeae 100644 (file)
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -79,19 +79,19 @@ int fixed_sdram(void)
        u32 ddr_size = msize << 20;     /* DDR size in bytes */
        u32 ddr_size_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        im->ddr.csbnds[2].csbnds =
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
                                CSBNDS_EA_SHIFT) & CSBNDS_EA);
        im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 609585b..f4148a2 100644 (file)
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -38,7 +38,7 @@ static long fixed_sdram(void)
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-               (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+               (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
        out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
        out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -48,12 +48,12 @@ static long fixed_sdram(void)
         */
        __udelay(50000);
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
        out_be32(&im->ddr.csbnds[0].csbnds,
-               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-               (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+               ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
                        CSBNDS_EA));
        out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 6d018fd..e1f69a1 100644 (file)
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -23,8 +23,12 @@
  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  */
 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#else
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
 #endif
+#endif
 
 #ifdef CONFIG_PPC
 #include <asm/fsl_law.h>

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index d9361fd..5d31d4a 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -37,7 +37,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 08c8399..6f100fc 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -87,7 +87,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 169cc09..0f246dc 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -59,7 +59,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index c5a229d..0b94b0c 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -35,7 +35,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 3e6febf..a90a9a8 100644 (file)
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -24,7 +24,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 4b3f70c..88b6f87 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -21,7 +21,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDRCDR      0x73000002      /* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 1a96be0..fdbd15e 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -53,7 +53,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 311f87b..1e0e297 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -53,7 +53,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index bb3bcfc..388910a 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -143,7 +143,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_MEMTEST_START       0x1000  /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x2000

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index e34a36c..61f9eaf 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -36,7 +36,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE                (DDRCDR_DHC_EN \

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 33d4ced..07b206f 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -59,7 +59,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 53fac4d..0da34d0 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -25,7 +25,6 @@
  */
                                /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE  0x00000000
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define DDR_CASLAT_25          /* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC          /* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM       /* do not use SPD EEPROM for DDR setup */

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index f14e5fa..928136f 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index ae3fcfd..d73e848 100644 (file)
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -25,7 +25,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 504a136..155815a 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -52,7 +52,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters,

diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index 5c4df18..847996f 100644 (file)
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -46,7 +46,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 2e8affb..290108d 100644 (file)
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index 3be5328..0759604 100644 (file)
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index 74e719c..319e3bc 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index c691383..85e9101 100644 (file)
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -58,7 +58,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 4af8619..6ec944f 100644 (file)
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index d8f4d26..d7cbdde 100644 (file)
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -50,7 +50,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 8836b70..0392c3e 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -40,7 +40,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 709387e..b4ae7b7 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -47,7 +47,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/include/configs/strider.h b/include/configs/strider.h
index c01531c..e92bd1e 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -25,7 +25,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 3521de8..8b3b454 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -48,7 +48,6 @@
 #define CONFIG_SYS_SDRAM_BASE  0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 86e402a..5dc9e89 100644 (file)
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index ec1ac39..9f8c855 100644 (file)
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index cd6c686..2116d6b 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -35,7 +35,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 14a84fa..1bce6c7 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING