board/freescale/mpc8349itx/mpc8349itx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 #include <common.h>
   7 #include <ioports.h>
   8 #include <mpc83xx.h>
   9 #include <i2c.h>
  10 #include <miiphy.h>
  11 #include <vsc7385.h>
  12 #ifdef CONFIG_PCI
  13 #include <asm/mpc8349_pci.h>
  14 #include <pci.h>
  15 #endif
  16 #include <spd_sdram.h>
  17 #include <asm/mmu.h>
  18 #if defined(CONFIG_OF_LIBFDT)
  19 #include <linux/libfdt.h>
  20 #endif
  21
  22 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  23 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifndef CONFIG_SPD_EEPROM
  28 /*************************************************************************
  29  *  fixed sdram init -- doesn't use serial presence detect.
  30  ************************************************************************/
  31 int fixed_sdram(void)
  32 {
  33         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  34         /* The size of RAM, in bytes */
  35         u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  36         u32 ddr_size_log2 = __ilog2(ddr_size);
  37
  38         im->sysconf.ddrlaw[0].ar =
  39             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  40         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
  41
  42 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
  43 #warning Chip select bounds is only configurable in 16MB increments
  44 #endif
  45         im->ddr.csbnds[0].csbnds =
  46                 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  47                 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
  48                                 CSBNDS_EA_SHIFT) & CSBNDS_EA);
  49         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  50
  51         /* Only one CS for DDR */
  52         im->ddr.cs_config[1] = 0;
  53         im->ddr.cs_config[2] = 0;
  54         im->ddr.cs_config[3] = 0;
  55
  56         debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  57         debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  58
  59         debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  60         debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  61
  62         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  63         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  64         im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  65         im->ddr.sdram_mode =
  66             (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  67         im->ddr.sdram_interval =
  68             (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  69                                                        SDRAM_INTERVAL_BSTOPRE_SHIFT);
  70         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  71
  72         udelay(200);
  73
  74         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  75
  76         debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  77         debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  78         debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  79         debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  80         debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  81
  82         return CONFIG_SYS_DDR_SIZE;
  83 }
  84 #endif
  85
  86 #ifdef CONFIG_PCI
  87 /*
  88  * Initialize PCI Devices, report devices found
  89  */
  90 #ifndef CONFIG_PCI_PNP
  91 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  92         {
  93          PCI_ANY_ID,
  94          PCI_ANY_ID,
  95          PCI_ANY_ID,
  96          PCI_ANY_ID,
  97          0x0f,
  98          PCI_ANY_ID,
  99          pci_cfgfunc_config_device,
 100          {
 101           PCI_ENET0_IOADDR,
 102           PCI_ENET0_MEMADDR,
 103           PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
 104          },
 105         {}
 106 }
 107 #endif
 108
 109 volatile static struct pci_controller hose[] = {
 110         {
 111 #ifndef CONFIG_PCI_PNP
 112               config_table:pci_mpc83xxmitx_config_table,
 113 #endif
 114          },
 115         {
 116 #ifndef CONFIG_PCI_PNP
 117               config_table:pci_mpc83xxmitx_config_table,
 118 #endif
 119          }
 120 };
 121 #endif                          /* CONFIG_PCI */
 122
 123 int dram_init(void)
 124 {
 125         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 126         u32 msize = 0;
 127 #ifdef CONFIG_DDR_ECC
 128         volatile ddr83xx_t *ddr = &im->ddr;
 129 #endif
 130
 131         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 132                 return -ENXIO;
 133
 134         /* DDR SDRAM - Main SODIMM */
 135         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 136 #ifdef CONFIG_SPD_EEPROM
 137         msize = spd_sdram();
 138 #else
 139         msize = fixed_sdram();
 140 #endif
 141
 142 #ifdef CONFIG_DDR_ECC
 143         if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
 144                 /* Unlike every other board, on the 83xx spd_sdram() returns
 145                    megabytes instead of just bytes.  That's why we need to
 146                    multiple by 1MB when calling ddr_enable_ecc(). */
 147                 ddr_enable_ecc(msize * 1048576);
 148 #endif
 149
 150         /* return total bus RAM size(bytes) */
 151         gd->ram_size = msize * 1024 * 1024;
 152
 153         return 0;
 154 }
 155
 156 int checkboard(void)
 157 {
 158 #ifdef CONFIG_TARGET_MPC8349ITX
 159         puts("Board: Freescale MPC8349E-mITX\n");
 160 #else
 161         puts("Board: Freescale MPC8349E-mITX-GP\n");
 162 #endif
 163
 164         return 0;
 165 }
 166
 167 /*
 168  * Implement a work-around for a hardware problem with compact
 169  * flash.
 170  *
 171  * Program the UPM if compact flash is enabled.
 172  */
 173 int misc_init_f(void)
 174 {
 175 #ifdef CONFIG_VSC7385_ENET
 176         volatile u32 *vsc7385_cpuctrl;
 177
 178         /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
 179            default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
 180            means it is 0 when the IRQ is not active.  This makes the wire-AND
 181            logic always assert IRQ7 to CPU even if there is no request from the
 182            switch.  Since the compact flash and the switch share the same IRQ,
 183            the Linux kernel will think that the compact flash is requesting irq
 184            and get stuck when it tries to clear the IRQ.  Thus we need to set
 185            the L2_IRQ0 and L2_IRQ1 to active low.
 186
 187            The following code sets the L1_IRQ and L2_IRQ polarity to active low.
 188            Without this code, compact flash will not work in Linux because
 189            unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
 190            don't enable compact flash for U-Boot.
 191          */
 192
 193         vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
 194         *vsc7385_cpuctrl |= 0x0c;
 195 #endif
 196
 197 #ifdef CONFIG_COMPACT_FLASH
 198         /* UPM Table Configuration Code */
 199         static uint UPMATable[] = {
 200                 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
 201                 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
 202                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 203                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 204                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
 205                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 206                 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
 207                 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
 208                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 209                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 210                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 211                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 212                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 213                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 214                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 215                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 216         };
 217         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 218
 219         set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 220         set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 221
 222         /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 223            GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 224          */
 225         immap->im_lbc.mamr = 0x08404440;
 226
 227         upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 228
 229         puts("UPMA:  Configured for compact flash\n");
 230 #endif
 231
 232         return 0;
 233 }
 234
 235 /*
 236  * Miscellaneous late-boot configurations
 237  *
 238  * Make sure the EEPROM has the HRCW correctly programmed.
 239  * Make sure the RTC is correctly programmed.
 240  *
 241  * The MPC8349E-mITX can be configured to load the HRCW from
 242  * EEPROM instead of flash.  This is controlled via jumpers
 243  * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
 244  * jumpered), but if they're set to 001 or 010, then the HRCW is
 245  * read from the "I2C EEPROM".
 246  *
 247  * This function makes sure that the I2C EEPROM is programmed
 248  * correctly.
 249  *
 250  * If a VSC7385 microcode image is present, then upload it.
 251  */
 252 int misc_init_r(void)
 253 {
 254         int rc = 0;
 255
 256 #if defined(CONFIG_SYS_I2C)
 257         unsigned int orig_bus = i2c_get_bus_num();
 258         u8 i2c_data;
 259
 260 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 261         u8 ds1339_data[17];
 262 #endif
 263
 264 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 265         static u8 eeprom_data[] =       /* HRCW data */
 266         {
 267                 0xAA, 0x55, 0xAA,       /* Preamble */
 268                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 269                 0x02, 0x40,             /* RCWL ADDR=0x0_0900 */
 270                 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
 271                 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
 272                 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
 273                 CONFIG_SYS_HRCW_LOW & 0xFF,
 274                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 275                 0x02, 0x41,             /* RCWH ADDR=0x0_0904 */
 276                 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
 277                 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
 278                 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
 279                 CONFIG_SYS_HRCW_HIGH & 0xFF
 280         };
 281
 282         u8 data[sizeof(eeprom_data)];
 283 #endif
 284
 285         printf("Board revision: ");
 286         i2c_set_bus_num(1);
 287         if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 288                 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 289         else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 290                 printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 291         else {
 292                 printf("Unknown\n");
 293                 rc = 1;
 294         }
 295
 296 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 297         i2c_set_bus_num(0);
 298
 299         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
 300                 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
 301                         if (i2c_write
 302                             (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
 303                              sizeof(eeprom_data)) != 0) {
 304                                 puts("Failure writing the HRCW to EEPROM via I2C.\n");
 305                                 rc = 1;
 306                         }
 307                 }
 308         } else {
 309                 puts("Failure reading the HRCW from EEPROM via I2C.\n");
 310                 rc = 1;
 311         }
 312 #endif
 313
 314 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 315         i2c_set_bus_num(1);
 316
 317         if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
 318             == 0) {
 319
 320                 /* Work-around for MPC8349E-mITX bug #13601.
 321                    If the RTC does not contain valid register values, the DS1339
 322                    Linux driver will not work.
 323                  */
 324
 325                 /* Make sure status register bits 6-2 are zero */
 326                 ds1339_data[0x0f] &= ~0x7c;
 327
 328                 /* Check for a valid day register value */
 329                 ds1339_data[0x03] &= ~0xf8;
 330                 if (ds1339_data[0x03] == 0) {
 331                         ds1339_data[0x03] = 1;
 332                 }
 333
 334                 /* Check for a valid date register value */
 335                 ds1339_data[0x04] &= ~0xc0;
 336                 if ((ds1339_data[0x04] == 0) ||
 337                     ((ds1339_data[0x04] & 0x0f) > 9) ||
 338                     (ds1339_data[0x04] >= 0x32)) {
 339                         ds1339_data[0x04] = 1;
 340                 }
 341
 342                 /* Check for a valid month register value */
 343                 ds1339_data[0x05] &= ~0x60;
 344
 345                 if ((ds1339_data[0x05] == 0) ||
 346                     ((ds1339_data[0x05] & 0x0f) > 9) ||
 347                     ((ds1339_data[0x05] >= 0x13)
 348                      && (ds1339_data[0x05] <= 0x19))) {
 349                         ds1339_data[0x05] = 1;
 350                 }
 351
 352                 /* Enable Oscillator and rate select */
 353                 ds1339_data[0x0e] = 0x1c;
 354
 355                 /* Work-around for MPC8349E-mITX bug #13330.
 356                    Ensure that the RTC control register contains the value 0x1c.
 357                    This affects SATA performance.
 358                  */
 359
 360                 if (i2c_write
 361                     (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
 362                      sizeof(ds1339_data))) {
 363                         puts("Failure writing to the RTC via I2C.\n");
 364                         rc = 1;
 365                 }
 366         } else {
 367                 puts("Failure reading from the RTC via I2C.\n");
 368                 rc = 1;
 369         }
 370 #endif
 371
 372         i2c_set_bus_num(orig_bus);
 373 #endif
 374
 375 #ifdef CONFIG_VSC7385_IMAGE
 376         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 377                 CONFIG_VSC7385_IMAGE_SIZE)) {
 378                 puts("Failure uploading VSC7385 microcode.\n");
 379                 rc = 1;
 380         }
 381 #endif
 382
 383         return rc;
 384 }
 385
 386 #if defined(CONFIG_OF_BOARD_SETUP)
 387 int ft_board_setup(void *blob, bd_t *bd)
 388 {
 389         ft_cpu_setup(blob, bd);
 390 #ifdef CONFIG_PCI
 391         ft_pci_setup(blob, bd);
 392 #endif
 393
 394         return 0;
 395 }
 396 #endif