include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRL                0x00000000
  22
  23 /*
  24  * DDR Setup
  25  */
  26 #define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory */
  27 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_SDRAM_BASE
  28
  29 #undef CONFIG_SPD_EEPROM
  30 #if defined(CONFIG_SPD_EEPROM)
  31 /* Determine DDR configuration from I2C interface
  32  */
  33 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  34 #else
  35 /* Manually set up DDR parameters
  36  */
  37 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  38 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  39                                 | CSCONFIG_ROW_BIT_13 \
  40                                 | CSCONFIG_COL_BIT_9)
  41                                 /* 0x80010101 */
  42 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  43                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  44                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  45                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  46                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  47                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  48                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  49                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  50                                 /* 0x00220802 */
  51 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  52                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  53                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  54                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  55                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  56                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  57                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  58                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  59                                 /* 0x26253222 */
  60 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  61                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  62                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  63                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  64                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  65                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  66                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  67                                 /* 0x1f9048c7 */
  68 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  69 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  70                                 /* 0x02000000 */
  71 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  72                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  73                                 /* 0x44480232 */
  74 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  75 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  76                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  77                                 /* 0x03200064 */
  78 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  79 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  80                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  81                                 | SDRAM_CFG_32_BE)
  82                                 /* 0x43080000 */
  83 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  84 #endif
  85
  86 /*
  87  * Memory test
  88  */
  89 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  90 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
  91 #define CONFIG_SYS_MEMTEST_END          0x03f00000
  92
  93 /*
  94  * The reserved memory
  95  */
  96 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  97
  98 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  99 #define CONFIG_SYS_RAMBOOT
 100 #else
 101 #undef  CONFIG_SYS_RAMBOOT
 102 #endif
 103
 104 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 105 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 106 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 107
 108 /*
 109  * Initial RAM Base Address Setup
 110  */
 111 #define CONFIG_SYS_INIT_RAM_LOCK        1
 112 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 113 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 114 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 115                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 116
 117 /*
 118  * Local Bus Configuration & Clock Setup
 119  */
 120 #define CONFIG_SYS_LBC_LBCR             0x00000000
 121
 122 /*
 123  * FLASH on the Local Bus
 124  */
 125 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 126 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 127
 128
 129
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 132
 133 #undef CONFIG_SYS_FLASH_CHECKSUM
 134
 135 /*
 136  * Serial Port
 137  */
 138 #define CONFIG_SYS_NS16550_SERIAL
 139 #define CONFIG_SYS_NS16550_REG_SIZE     1
 140 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 141
 142 #define CONFIG_SYS_BAUDRATE_TABLE  \
 143                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 144
 145 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 146 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 147
 148 /* I2C */
 149 #define CONFIG_SYS_I2C
 150 #define CONFIG_SYS_I2C_FSL
 151 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 152 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 153 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 154 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 155
 156 /*
 157  * Config on-board EEPROM
 158  */
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 163
 164 /*
 165  * General PCI
 166  * Addresses are mapped 1-1.
 167  */
 168 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 169 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 170 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 171 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 172 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 173 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 174 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 175 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 176 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 177
 178 #ifdef CONFIG_PCI
 179 #define CONFIG_PCI_INDIRECT_BRIDGE
 180 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 181
 182 #undef CONFIG_EEPRO100
 183 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 184 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 185
 186 #endif  /* CONFIG_PCI */
 187
 188 /*
 189  * QE UEC ethernet configuration
 190  */
 191 #define CONFIG_UEC_ETH
 192 #define CONFIG_ETHPRIME         "UEC0"
 193
 194 #define CONFIG_UEC_ETH1         /* ETH3 */
 195
 196 #ifdef CONFIG_UEC_ETH1
 197 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 198 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 199 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 200 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 201 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 202 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 203 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 204 #endif
 205
 206 #define CONFIG_UEC_ETH2         /* ETH4 */
 207
 208 #ifdef CONFIG_UEC_ETH2
 209 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 210 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 211 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 212 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 213 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 214 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 215 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 216 #endif
 217
 218 /*
 219  * Environment
 220  */
 221 #ifndef CONFIG_SYS_RAMBOOT
 222         #define CONFIG_ENV_ADDR         \
 223                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 224         #define CONFIG_ENV_SECT_SIZE    0x20000
 225         #define CONFIG_ENV_SIZE         0x2000
 226 #else
 227         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 228         #define CONFIG_ENV_SIZE         0x2000
 229 #endif
 230
 231 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 232 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 233
 234 /*
 235  * BOOTP options
 236  */
 237 #define CONFIG_BOOTP_BOOTFILESIZE
 238
 239 /*
 240  * Command line configuration.
 241  */
 242
 243 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 244
 245 /*
 246  * Miscellaneous configurable options
 247  */
 248 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 249
 250 /*
 251  * For booting Linux, the board info and command line data
 252  * have to be in the first 256 MB of memory, since this is
 253  * the maximum mapped by the Linux kernel during initialization.
 254  */
 255                                         /* Initial Memory map for Linux */
 256 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 257 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 258
 259 #if (CONFIG_CMD_KGDB)
 260 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 261 #endif
 262
 263 /*
 264  * Environment Configuration
 265  */
 266 #define CONFIG_ENV_OVERWRITE
 267
 268 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 269 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 270
 271 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 272  * (see CONFIG_SYS_I2C_EEPROM) */
 273                                         /* MAC address offset in I2C EEPROM */
 274 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 275
 276 #define CONFIG_NETDEV           "eth1"
 277
 278 #define CONFIG_HOSTNAME         "mpc8323erdb"
 279 #define CONFIG_ROOTPATH         "/nfsroot"
 280 #define CONFIG_BOOTFILE         "uImage"
 281                                 /* U-Boot image on TFTP server */
 282 #define CONFIG_UBOOTPATH        "u-boot.bin"
 283 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 284 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 285
 286                                 /* default location for tftp and bootm */
 287 #define CONFIG_LOADADDR         800000
 288
 289 #define CONFIG_EXTRA_ENV_SETTINGS \
 290         "netdev=" CONFIG_NETDEV "\0"                                    \
 291         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 292         "tftpflash=tftp $loadaddr $uboot;"                              \
 293                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 294                         " +$filesize; " \
 295                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 296                         " +$filesize; " \
 297                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 298                         " $filesize; "  \
 299                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 300                         " +$filesize; " \
 301                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 302                         " $filesize\0"  \
 303         "fdtaddr=780000\0"                                              \
 304         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 305         "ramdiskaddr=1000000\0"                                         \
 306         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 307         "console=ttyS0\0"                                               \
 308         "setbootargs=setenv bootargs "                                  \
 309                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 310         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 311                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 312                                                                 "$netdev:off "\
 313                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 314
 315 #define CONFIG_NFSBOOTCOMMAND                                           \
 316         "setenv rootdev /dev/nfs;"                                      \
 317         "run setbootargs;"                                              \
 318         "run setipargs;"                                                \
 319         "tftp $loadaddr $bootfile;"                                     \
 320         "tftp $fdtaddr $fdtfile;"                                       \
 321         "bootm $loadaddr - $fdtaddr"
 322
 323 #define CONFIG_RAMBOOTCOMMAND                                           \
 324         "setenv rootdev /dev/ram;"                                      \
 325         "run setbootargs;"                                              \
 326         "tftp $ramdiskaddr $ramdiskfile;"                               \
 327         "tftp $loadaddr $bootfile;"                                     \
 328         "tftp $fdtaddr $fdtfile;"                                       \
 329         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 330
 331 #endif  /* __CONFIG_H */