include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #define CONFIG_FSL_SATA_V2
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #ifdef CONFIG_RAMBOOT_PBL
  27 #define CONFIG_SPL_FLUSH_IMAGE
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32 #ifdef CONFIG_SPL_BUILD
  33 #define CONFIG_SPL_SKIP_RELOCATE
  34 #define CONFIG_SPL_COMMON_INIT_DDR
  35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  36 #endif
  37
  38 #ifdef CONFIG_MTD_RAW_NAND
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  42 #endif
  43
  44 #ifdef CONFIG_SPIFLASH
  45 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  46 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  51 #ifndef CONFIG_SPL_BUILD
  52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  53 #endif
  54 #endif
  55
  56 #ifdef CONFIG_SDCARD
  57 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  58 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  59 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  60 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  61 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #endif
  66
  67 #endif /* CONFIG_RAMBOOT_PBL */
  68
  69 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  70 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  71 /* Set 1M boot space */
  72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  74                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  75 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  76 #endif
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 /*
  83  * These can be toggled for performance analysis, otherwise use default.
  84  */
  85 #define CONFIG_SYS_CACHE_STASHING
  86 #ifdef CONFIG_DDR_ECC
  87 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  88 #endif
  89
  90 /*
  91  * Config the L3 Cache as L3 SRAM
  92  */
  93 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  94 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  95 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  96 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  97 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  98 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  99 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 100
 101 #define CONFIG_SYS_DCSRBAR      0xf0000000
 102 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 103
 104 /* EEPROM */
 105 #define CONFIG_SYS_I2C_EEPROM_NXID
 106 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 107
 108 /*
 109  * DDR Setup
 110  */
 111 #define CONFIG_VERY_BIG_RAM
 112 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 113 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 114 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 115 #define CONFIG_SYS_SPD_BUS_NUM  0
 116 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 117 #define SPD_EEPROM_ADDRESS1     0x51
 118 #define SPD_EEPROM_ADDRESS2     0x52
 119 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 120 #define CTRL_INTLV_PREFERED     cacheline
 121
 122 /*
 123  * IFC Definitions
 124  */
 125 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 126 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 127 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 128 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 129                                 CSPR_PORT_SIZE_16 | \
 130                                 CSPR_MSEL_NOR | \
 131                                 CSPR_V)
 132 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 133
 134 /* NOR Flash Timing Params */
 135 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 136
 137 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 138                                 FTIM0_NOR_TEADC(0x5) | \
 139                                 FTIM0_NOR_TEAHC(0x5))
 140 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 141                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 142                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 143 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 144                                 FTIM2_NOR_TCH(0x4) | \
 145                                 FTIM2_NOR_TWPH(0x0E) | \
 146                                 FTIM2_NOR_TWP(0x1c))
 147 #define CONFIG_SYS_NOR_FTIM3    0x0
 148
 149 #define CONFIG_SYS_FLASH_QUIET_TEST
 150 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 151
 152 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 153 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 154 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 155 #define CONFIG_SYS_FLASH_EMPTY_INFO
 156 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 157
 158 /* CPLD on IFC */
 159 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 160 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 161 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 162 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 163                                 | CSPR_PORT_SIZE_8 \
 164                                 | CSPR_MSEL_GPCM \
 165                                 | CSPR_V)
 166 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 167 #define CONFIG_SYS_CSOR2        0x0
 168
 169 /* CPLD Timing parameters for IFC CS2 */
 170 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 171                                         FTIM0_GPCM_TEADC(0x0e) | \
 172                                         FTIM0_GPCM_TEAHC(0x0e))
 173 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 174                                         FTIM1_GPCM_TRAD(0x1f))
 175 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 176                                         FTIM2_GPCM_TCH(0x8) | \
 177                                         FTIM2_GPCM_TWP(0x1f))
 178 #define CONFIG_SYS_CS2_FTIM3            0x0
 179
 180 /* NAND Flash on IFC */
 181 #define CONFIG_SYS_NAND_BASE            0xff800000
 182 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 183
 184 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 185 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 186                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 187                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 188                                 | CSPR_V)
 189 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 190
 191 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 192                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 193                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 194                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 195                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 196                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 197                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 198
 199 /* ONFI NAND Flash mode0 Timing Params */
 200 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 201                                         FTIM0_NAND_TWP(0x18)    | \
 202                                         FTIM0_NAND_TWCHT(0x07)  | \
 203                                         FTIM0_NAND_TWH(0x0a))
 204 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 205                                         FTIM1_NAND_TWBE(0x39)   | \
 206                                         FTIM1_NAND_TRR(0x0e)    | \
 207                                         FTIM1_NAND_TRP(0x18))
 208 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 209                                         FTIM2_NAND_TREH(0x0a)   | \
 210                                         FTIM2_NAND_TWHRE(0x1e))
 211 #define CONFIG_SYS_NAND_FTIM3           0x0
 212
 213 #define CONFIG_SYS_NAND_DDR_LAW         11
 214 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 215 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 216
 217 #if defined(CONFIG_MTD_RAW_NAND)
 218 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 219 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 220 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 221 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 222 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 223 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 224 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 225 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 226 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 227 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 228 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 229 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 230 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 231 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 232 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 233 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 234 #else
 235 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 236 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 237 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 238 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 239 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 240 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 241 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 242 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 243 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 244 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 245 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 246 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 247 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 248 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 249 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 250 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 251 #endif
 252
 253 #if defined(CONFIG_RAMBOOT_PBL)
 254 #define CONFIG_SYS_RAMBOOT
 255 #endif
 256
 257 #define CONFIG_HWCONFIG
 258
 259 /* define to use L1 as initial stack */
 260 #define CONFIG_L1_INIT_RAM
 261 #define CONFIG_SYS_INIT_RAM_LOCK
 262 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 264 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 265 /* The assembler doesn't like typecast */
 266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 267                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 268                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 269 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 270 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 271                                                 GENERATED_GBL_DATA_SIZE)
 272 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 273 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 274
 275 /*
 276  * Serial Port
 277  */
 278 #define CONFIG_SYS_NS16550_SERIAL
 279 #define CONFIG_SYS_NS16550_REG_SIZE     1
 280 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 281 #define CONFIG_SYS_BAUDRATE_TABLE       \
 282         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 283 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 284 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 285 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 286 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 287
 288 /*
 289  * I2C
 290  */
 291
 292 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 293 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 294 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 295 #define I2C_MUX_CH_DEFAULT      0x8
 296
 297 #define I2C_MUX_CH_VOL_MONITOR  0xa
 298
 299 /* The lowest and highest voltage allowed for T208xRDB */
 300 #define VDD_MV_MIN                      819
 301 #define VDD_MV_MAX                      1212
 302
 303 /*
 304  * RapidIO
 305  */
 306 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 307 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 308 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 309 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 310 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 311 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 312 /*
 313  * for slave u-boot IMAGE instored in master memory space,
 314  * PHYS must be aligned based on the SIZE
 315  */
 316 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 317 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 318 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 319 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 320 /*
 321  * for slave UCODE and ENV instored in master memory space,
 322  * PHYS must be aligned based on the SIZE
 323  */
 324 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 325 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 326 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 327
 328 /* slave core release by master*/
 329 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 330 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 331
 332 /*
 333  * SRIO_PCIE_BOOT - SLAVE
 334  */
 335 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 336 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 337 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 338                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 339 #endif
 340
 341 /*
 342  * eSPI - Enhanced SPI
 343  */
 344
 345 /*
 346  * General PCI
 347  * Memory space is mapped 1-1, but I/O space must start from 0.
 348  */
 349 #define CONFIG_PCIE1            /* PCIE controller 1 */
 350 #define CONFIG_PCIE2            /* PCIE controller 2 */
 351 #define CONFIG_PCIE3            /* PCIE controller 3 */
 352 #define CONFIG_PCIE4            /* PCIE controller 4 */
 353 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 354 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 355 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 356 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 357 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 358
 359 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 360 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 361 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 362 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 363 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 364
 365 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 366 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 367 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 368 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 369 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 370
 371 /* controller 4, Base address 203000 */
 372 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 373 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 374 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 375
 376 #ifdef CONFIG_PCI
 377 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 378 #endif
 379
 380 /* Qman/Bman */
 381 #ifndef CONFIG_NOBQFMAN
 382 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 383 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 384 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 385 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 386 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 387 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 388 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 389 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 390 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 391                                         CONFIG_SYS_BMAN_CENA_SIZE)
 392 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 393 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 394 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 395 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 396 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 397 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 398 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 399 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 400 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 401 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 402 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 403                                         CONFIG_SYS_QMAN_CENA_SIZE)
 404 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 405 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 406
 407 #define CONFIG_SYS_DPAA_FMAN
 408 #define CONFIG_SYS_DPAA_PME
 409 #define CONFIG_SYS_PMAN
 410 #define CONFIG_SYS_DPAA_DCE
 411 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 412 #define CONFIG_SYS_INTERLAKEN
 413
 414 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 415 #endif /* CONFIG_NOBQFMAN */
 416
 417 #ifdef CONFIG_SYS_DPAA_FMAN
 418 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 419 #define RGMII_PHY2_ADDR         0x02
 420 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 421 #define CORTINA_PHY_ADDR2       0x0d
 422 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 423 #define FM1_10GEC3_PHY_ADDR     0x00
 424 #define FM1_10GEC4_PHY_ADDR     0x01
 425 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 426 #define AQR113C_PHY_ADDR1       0x00
 427 #define AQR113C_PHY_ADDR2       0x08
 428 #endif
 429
 430 /*
 431  * SATA
 432  */
 433 #ifdef CONFIG_FSL_SATA_V2
 434 #define CONFIG_SATA1
 435 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 436 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 437 #define CONFIG_SATA2
 438 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 439 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 440 #define CONFIG_LBA48
 441 #endif
 442
 443 /*
 444  * USB
 445  */
 446 #ifdef CONFIG_USB_EHCI_HCD
 447 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 448 #define CONFIG_HAS_FSL_DR_USB
 449 #endif
 450
 451 /*
 452  * SDHC
 453  */
 454 #ifdef CONFIG_MMC
 455 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 456 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 457 #endif
 458
 459 /*
 460  * Dynamic MTD Partition support with mtdparts
 461  */
 462
 463 /*
 464  * Environment
 465  */
 466
 467 /*
 468  * Miscellaneous configurable options
 469  */
 470
 471 /*
 472  * For booting Linux, the board info and command line data
 473  * have to be in the first 64 MB of memory, since this is
 474  * the maximum mapped by the Linux kernel during initialization.
 475  */
 476 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 477 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 478
 479 /*
 480  * Environment Configuration
 481  */
 482 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 483 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 484
 485 #define __USB_PHY_TYPE          utmi
 486
 487 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 488         "hwconfig=fsl_ddr:"                                     \
 489         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 490         "bank_intlv=auto;"                                      \
 491         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 492         "netdev=eth0\0"                                         \
 493         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 494         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 495         "tftpflash=tftpboot $loadaddr $uboot && "               \
 496         "protect off $ubootaddr +$filesize && "                 \
 497         "erase $ubootaddr +$filesize && "                       \
 498         "cp.b $loadaddr $ubootaddr $filesize && "               \
 499         "protect on $ubootaddr +$filesize && "                  \
 500         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 501         "consoledev=ttyS0\0"                                    \
 502         "ramdiskaddr=2000000\0"                                 \
 503         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 504         "fdtaddr=1e00000\0"                                     \
 505         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 506         "bdev=sda3\0"
 507
 508 /*
 509  * For emulation this causes u-boot to jump to the start of the
 510  * proof point app code automatically
 511  */
 512 #define PROOF_POINTS                            \
 513         "setenv bootargs root=/dev/$bdev rw "           \
 514         "console=$consoledev,$baudrate $othbootargs;"   \
 515         "cpu 1 release 0x29000000 - - -;"               \
 516         "cpu 2 release 0x29000000 - - -;"               \
 517         "cpu 3 release 0x29000000 - - -;"               \
 518         "cpu 4 release 0x29000000 - - -;"               \
 519         "cpu 5 release 0x29000000 - - -;"               \
 520         "cpu 6 release 0x29000000 - - -;"               \
 521         "cpu 7 release 0x29000000 - - -;"               \
 522         "go 0x29000000"
 523
 524 #define HVBOOT                          \
 525         "setenv bootargs config-addr=0x60000000; "      \
 526         "bootm 0x01000000 - 0x00f00000"
 527
 528 #define ALU                             \
 529         "setenv bootargs root=/dev/$bdev rw "           \
 530         "console=$consoledev,$baudrate $othbootargs;"   \
 531         "cpu 1 release 0x01000000 - - -;"               \
 532         "cpu 2 release 0x01000000 - - -;"               \
 533         "cpu 3 release 0x01000000 - - -;"               \
 534         "cpu 4 release 0x01000000 - - -;"               \
 535         "cpu 5 release 0x01000000 - - -;"               \
 536         "cpu 6 release 0x01000000 - - -;"               \
 537         "cpu 7 release 0x01000000 - - -;"               \
 538         "go 0x01000000"
 539
 540 #include <asm/fsl_secure_boot.h>
 541
 542 #endif  /* __T2080RDB_H */