Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians...

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers

diff --cc MAINTAINERS
Simple merge

diff --cc configs/xilinx_zynqmp_virt_defconfig
Simple merge

diff --cc include/configs/xilinx_versal.h
index 60df795,9088b31..80e9411
--- 1/include/configs/xilinx_versal.h
--- 2/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@@ -43,8 -43,10 +43,8 @@@
  # define PHY_ANEG_TIMEOUT       20000
  #endif
  
- #define CONFIG_SYS_BOOTM_LEN  (60 * 1024 * 1024)
+ #define CONFIG_SYS_BOOTM_LEN  (100 * 1024 * 1024)
  
 -#define CONFIG_CLOCKS
 -
  #define ENV_MEM_LAYOUT_SETTINGS \
        "fdt_addr_r=0x40000000\0" \
        "fdt_size_r=0x400000\0" \

diff --cc include/configs/xilinx_zynqmp.h
index a063c01,d1abe44..1985a09
--- 1/include/configs/xilinx_zynqmp.h
--- 2/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@@ -58,8 -58,10 +58,8 @@@
  # define PHY_ANEG_TIMEOUT       20000
  #endif
  
- #define CONFIG_SYS_BOOTM_LEN  (60 * 1024 * 1024)
+ #define CONFIG_SYS_BOOTM_LEN  (100 * 1024 * 1024)
  
 -#define CONFIG_CLOCKS
 -
  #define ENV_MEM_LAYOUT_SETTINGS \
        "fdt_addr_r=0x40000000\0" \
        "fdt_size_r=0x400000\0" \