platform/kernel/u-boot.git
2 years agoAdd a default for TPL_TEXT_BASE
Simon Glass [Mon, 28 Feb 2022 19:08:30 +0000 (12:08 -0700)]
Add a default for TPL_TEXT_BASE

If this value is not provided it causes a hang in the build. Add a default
value to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agodisk: Correct the conditions for SPL
Simon Glass [Mon, 28 Feb 2022 19:08:29 +0000 (12:08 -0700)]
disk: Correct the conditions for SPL

These filesystems may have different settings for SPL and TPL. Use the
correct Makefile variable to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agospi: Avoid checking console in SPL
Simon Glass [Mon, 28 Feb 2022 19:08:28 +0000 (12:08 -0700)]
spi: Avoid checking console in SPL

When SPI flash is used in SPL there is no console, so ctrlc() cannot be
called. Add a condition to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agocros_ec: Complete the comment for cros_ec_read_batt_charge()
Simon Glass [Mon, 28 Feb 2022 19:08:27 +0000 (12:08 -0700)]
cros_ec: Complete the comment for cros_ec_read_batt_charge()

Add the missing 'Return' information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agocbfs: Add some more definititions
Simon Glass [Mon, 28 Feb 2022 19:08:26 +0000 (12:08 -0700)]
cbfs: Add some more definititions

Add definitions for a payload or 'self', which is like an unpacked ELF
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agolzma: Tidy up the function prototype
Simon Glass [Mon, 28 Feb 2022 19:08:25 +0000 (12:08 -0700)]
lzma: Tidy up the function prototype

This should use a const pointer for the input stream. Fix this and also
add a proper comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agofdt: sandbox: Avoid looking for an appended device tree
Simon Glass [Mon, 28 Feb 2022 19:08:24 +0000 (12:08 -0700)]
fdt: sandbox: Avoid looking for an appended device tree

We don't use an appended tree for sandbox and the required symbols are
not present. Add a condition to avoid a build error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agofdt: Correct condition for SEPARATE_BSS
Simon Glass [Mon, 28 Feb 2022 19:08:23 +0000 (12:08 -0700)]
fdt: Correct condition for SEPARATE_BSS

This may have different settings for SPL and TPL. Correct the condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoabuf: Correct a corner case with abuf_realloc()
Simon Glass [Mon, 28 Feb 2022 19:08:22 +0000 (12:08 -0700)]
abuf: Correct a corner case with abuf_realloc()

If the buffer is empty and not allocated, then abuf_realloc() tries to
copy invalid data. This happens because an incorrect change to use
memdup() was added after the original code was written.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoerrno: Avoid including strings in SPL
Simon Glass [Mon, 28 Feb 2022 19:08:21 +0000 (12:08 -0700)]
errno: Avoid including strings in SPL

At present the header file defines this function in SPL but the file may
not actually be built. This causes a build error if the option is enabled.

Fix the condition in the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agobinman: Correct Chromium OS entry types
Simon Glass [Mon, 28 Feb 2022 19:08:20 +0000 (12:08 -0700)]
binman: Correct Chromium OS entry types

The conversion to bintools broke the invocation of the utility, since
the arguments are not correct. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Wed, 6 Apr 2022 15:52:17 +0000 (11:52 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

2 years agoMerge branch '2022-04-06-assorted-updates'
Tom Rini [Wed, 6 Apr 2022 15:51:00 +0000 (11:51 -0400)]
Merge branch '2022-04-06-assorted-updates'

- Add DM_PMIC support to TPS65217 and migrate some platforms to it.
- mkimage verification fixes
- DM rST fix, add missing flag when linking u-boot-elf.o

2 years agodm: fix function documentation in include/dm/ofnode.h
Heinrich Schuchardt [Thu, 24 Mar 2022 15:22:32 +0000 (16:22 +0100)]
dm: fix function documentation in include/dm/ofnode.h

We use Sphinx style comments to describe functions.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2 years agotools: mkimage: Call verify_header after writing image to disk
Pali Rohár [Fri, 14 Jan 2022 17:34:43 +0000 (18:34 +0100)]
tools: mkimage: Call verify_header after writing image to disk

If image backend provides verify_header callback then call it after writing
image to disk. This ensures that written image is correct.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agotools: mkimage: No need to verify_header for header_v2
Yi Liu [Wed, 30 Mar 2022 10:05:59 +0000 (18:05 +0800)]
tools: mkimage: No need to verify_header for header_v2

rockchip header_v2 do not have a spl_hdr, so remove the verify.

Signed-off-by: Yi Liu <liuyi@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2 years agoMakefile: add endian link flag to u-boot-elf.o
Du Huanpeng [Wed, 30 Mar 2022 18:41:42 +0000 (02:41 +0800)]
Makefile: add endian link flag to u-boot-elf.o

fix compile error when using a little-endian to build with configs:
sfr_nb4-ser_ram_defconfig
comtrend_wap5813n_ram_defconfig
comtrend_ar5387un_ram_defconfig
comtrend_ct5361_ram_defconfig
comtrend_vr3032u_ram_defconfig
comtrend_ar5315u_ram_defconfig
huawei_hg556a_ram_defconfig
netgear_dgnd3700v2_ram_defconfig

Signed-off-by: Du Huanpeng <dhu@hodcarrier.org>
2 years agoriscv: alloc space exhausted
Heinrich Schuchardt [Tue, 5 Apr 2022 14:47:15 +0000 (16:47 +0200)]
riscv: alloc space exhausted

When trying to run qemu-riscv64_smode_defconfig with 32 harts booting
fails. The debug UART shows a message

    alloc space exhausted

32 is the current maximum number of harts for machine virt in QEMU 7.0.

Raise the default for SYS_MALLOC_F_LEN to 16 KiB.

Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for
other architectures too.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2 years agoriscv: enable CONFIG_CMD_SBI for QEMU boards
Heinrich Schuchardt [Wed, 23 Mar 2022 21:46:43 +0000 (22:46 +0100)]
riscv: enable CONFIG_CMD_SBI for QEMU boards

Let CONFIG_TARGET_QEMU_VIRT imply CONFIG_CMD_SBI.

The sbi command provides detailed information about the SBI.
It is useful to test the discovery of extensions.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2 years agocmd/sbi: add missing SBI information
Heinrich Schuchardt [Thu, 17 Mar 2022 06:36:15 +0000 (07:36 +0100)]
cmd/sbi: add missing SBI information

Let the sbi command display:

* machine vendor ID
* machine architecture ID
* machine implementation ID

With this patch the output for the HiFive Unmatched looks like

    => sbi
    SBI 0.3
    OpenSBI 0.9
    Machine:
      Vendor ID 489
      Architecture ID 8000000000000007
      Implementation ID 20181004
    Extensions:
      sbi_set_timer
      sbi_console_putchar
      sbi_console_getchar
      sbi_clear_ipi
      sbi_send_ipi
      sbi_remote_fence_i
      sbi_remote_sfence_vma
      sbi_remote_sfence_vma_asid
      sbi_shutdown
      SBI Base Functionality
      Timer Extension
      IPI Extension
      RFENCE Extension
      Hart State Management Extension
      System Reset Extension

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2 years agoriscv: provide missing base extension functions
Heinrich Schuchardt [Thu, 17 Mar 2022 06:36:14 +0000 (07:36 +0100)]
riscv: provide missing base extension functions

Provide library functions to read:

* machine vendor ID
* machine architecture ID
* machine implementation ID

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2 years agocmd: sbi: add Performance Monitoring Unit Extension
Heinrich Schuchardt [Wed, 16 Mar 2022 20:21:18 +0000 (21:21 +0100)]
cmd: sbi: add Performance Monitoring Unit Extension

Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification
has added the Performance Monitoring Unit Extension.

The sbi command should be able to detect it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2 years agopower: pmic: Provide DM_PMIC support for tps65217 driver
Lukasz Majewski [Sat, 12 Mar 2022 07:11:11 +0000 (08:11 +0100)]
power: pmic: Provide DM_PMIC support for tps65217 driver

The tps65217 PMIC driver is used with am335x SoC based designs.

It is used in the SPL (MLO) as well, so the DM conversion only is
for u-boot proper.

This driver only allows simple reading/writing/dumping of the content
of its registers and requires the DM_I2C for proper operation.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2 years agopower: Rename CONFIG_POWER_TPS65217 with CONFIG_PMIC_TPS65217
Lukasz Majewski [Sat, 12 Mar 2022 07:11:10 +0000 (08:11 +0100)]
power: Rename CONFIG_POWER_TPS65217 with CONFIG_PMIC_TPS65217

Up till now the CONFIG_POWER_TPS65217 has been defined in several header
files for am335x SoC.

This patch renames it to CONFIG_PMIC_TPS65217, which better reflects the
role of this IC circuit.

Moreover, new CONFIG_PMIC_TPS65217 has been introduced in Kconfig
to be used with boards, which both support DM_PMIC and DM_I2C.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Migrate all other platforms as well]
Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge branch '2022-04-04-platform-updates'
Tom Rini [Tue, 5 Apr 2022 17:45:22 +0000 (13:45 -0400)]
Merge branch '2022-04-04-platform-updates'

- Updates for exynos78x0 and TI K3 platforms

2 years agoMerge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians...
Tom Rini [Tue, 5 Apr 2022 15:27:39 +0000 (11:27 -0400)]
Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers

2 years agonet: zynq_gem: Add SGMII dynamic config support
T Karthik Reddy [Wed, 30 Mar 2022 09:07:58 +0000 (11:07 +0200)]
net: zynq_gem: Add SGMII dynamic config support

Add support for SGMII dynamic configuration which will takes care of
configuring SGMII in the GEM secure (GEM_CLK_CTRL) configuration
register.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/a8915186e44015959978d080a31de652f544cd4a.1648631275.git.michal.simek@xilinx.com
2 years agofirmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config api
T Karthik Reddy [Wed, 30 Mar 2022 09:07:57 +0000 (11:07 +0200)]
firmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config api

Add zynqmp_pm_set_gem_config() api to configure GEM secure registers.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/f69e32355c6a6be7d2780663353c52757530207d.1648631275.git.michal.simek@xilinx.com
2 years agogpio: slg7xl45106: Update gpio desc flags from DT
T Karthik Reddy [Wed, 30 Mar 2022 09:07:56 +0000 (11:07 +0200)]
gpio: slg7xl45106: Update gpio desc flags from DT

In current slg7xl45106 gpio driver xlate() function we are not updating
gpio flags from DT. Read the given flag from DT and update the gpio desc
flags variable with required gpio direction state.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/a8d7b4799337bd99f61ace509889f02b192a9414.1648631275.git.michal.simek@xilinx.com
2 years agonet: zynq_gem: Move ethernet info print statement
T Karthik Reddy [Wed, 30 Mar 2022 09:07:55 +0000 (11:07 +0200)]
net: zynq_gem: Move ethernet info print statement

As we are not reading the PHY address in case of CONFIG_ETH_PHY in plat
function, phy address always prints as -1. So move the ethernet info
print statement to probe function, to display proper phy address.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/f6efc6719d767b1bebe65987c22c6d52329f4225.1648631275.git.michal.simek@xilinx.com
2 years agonet: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabled
T Karthik Reddy [Wed, 30 Mar 2022 09:07:54 +0000 (11:07 +0200)]
net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabled

If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the
eth-phy-uclass driver, so use the PHY gpio reset functionality from
ethernet_id file when this config is disabled to reset the PHY.
Use debug() print instead of dev_err() to avoid warning incase if phy-id
compatible string is not present.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/4d0fd3f9f886c1d943776025e5efb5438b0eb389.1648631275.git.michal.simek@xilinx.com
2 years agonet: zynq_gem: Use shared MDIO bus support for zynqmp
Michal Simek [Wed, 30 Mar 2022 09:07:53 +0000 (11:07 +0200)]
net: zynq_gem: Use shared MDIO bus support for zynqmp

CONFIG_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Link: https://lore.kernel.org/r/337b1a38ba36cde1951739af62fb3d2736d97f53.1648631275.git.michal.simek@xilinx.com
2 years agodt-bindings: xilinx: Add missing ids for PD
Michal Simek [Wed, 30 Mar 2022 07:56:23 +0000 (09:56 +0200)]
dt-bindings: xilinx: Add missing ids for PD

There are some new power domain IDs which are used in Linux kernel that's
why add them here too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/e6092e1d3766c0ac11bf620820739c93ab677a85.1648626981.git.michal.simek@xilinx.com
2 years agoarm64: zynqmp: Record ID code for XCZU1EG device
Michal Simek [Wed, 30 Mar 2022 05:51:58 +0000 (07:51 +0200)]
arm64: zynqmp: Record ID code for XCZU1EG device

Add ID code for 1eg device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5b6c9f6a25bba076f304bc4699f6f676a929a683.1648619516.git.michal.simek@xilinx.com
2 years agonet: phy: Fix rgmii-id phy reset timeout issue
T Karthik Reddy [Tue, 29 Mar 2022 14:05:57 +0000 (16:05 +0200)]
net: phy: Fix rgmii-id phy reset timeout issue

While creating a phy device using phy_device_create(), we need to
provide a valid phyaddr instead of 0 causing phy address being
registered as 0 with mdio bus and shows mdio phy list as below

ZynqMP>  mdio list
eth0:
0 - TI DP83867 <--> ethernet@ff0b0000
eth1:
0 - TI DP83867 <--> ethernet@ff0c0000

Also PHY soft reset is being requested on 0 instead of valid
address causing "PHY reset timed out" error.

So add phyaddr argument to phy_connect_phy_id() and to its prototype
to create phy device with valid phyaddress.

Fixes: a744a284e354 ("net: phy: Add support for ethernet-phy-id with gpio reset")
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Link: https://lore.kernel.org/r/fe35fddb9faa5af577ffdfabaec6879c935a30f8.1648562755.git.michal.simek@xilinx.com
2 years agoclk: zynqmp: Add support for for DP audio/video clocks
Michal Simek [Tue, 29 Mar 2022 11:13:56 +0000 (13:13 +0200)]
clk: zynqmp: Add support for for DP audio/video clocks

Add support for getting rate for DP audio and video clocks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8792efe1fd9715f7c8a2e1e24f0454fb5b25d833.1648552434.git.michal.simek@xilinx.com
2 years agoMerge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Tom Rini [Tue, 5 Apr 2022 12:33:32 +0000 (08:33 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).

2 years agoxilinx: Increase max size of image from 60 to 100MB
Michal Simek [Tue, 29 Mar 2022 10:54:41 +0000 (12:54 +0200)]
xilinx: Increase max size of image from 60 to 100MB

Recently big Linux kernels can have more then 60MB that's why increase this
limit to also cover these large kernels.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/f52f7c8ea419d69b248ba1460a96d1635194e128.1648551279.git.michal.simek@xilinx.com
2 years agosunxi: defconfig: enable eMMC boot partition support
Andre Przywara [Mon, 12 Jul 2021 10:06:51 +0000 (11:06 +0100)]
sunxi: defconfig: enable eMMC boot partition support

Now that the SPL can safely detect whether it was loaded from an eMMC
boot partition or the normal user data partition, let's enable this
feature on some boards that feature eMMC storage.

That covers the boards where I could test this on, and allows the same
build to be written to an SD card, eMMC user partition, eMMC boot
partition, or into SPI NOR flash.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: eMMC: Improve automatic boot source detection
Andre Przywara [Mon, 12 Jul 2021 10:06:50 +0000 (11:06 +0100)]
sunxi: eMMC: Improve automatic boot source detection

When the Allwinner BROM loads the SPL from an eMMC boot partition, it
sets the boot source byte to the same value as when booting from the
user data partition. This prevents us from determining the boot source
to load U-Boot proper from the proper partition for sure.

The generic SPL MMC code already looks at the enabled boot partition
number, to load U-Boot proper from the same partition, but this fails
if there is nothing bootable in this partition, as the BROM then
silently falls back to the user data partition, which the SPL misses.

To learn about the actual boot source anyway, we repeat the algorithm
the BROM used to select the boot partition in the first place:
- Test EXT_CSD[179] to check if an eMMC boot partition is enabled.
- Test EXT_CSD[177] to check for valid MMC interface settings.
- Check if BOOT_ACK is enabled.
- Check the beginning of the first sector for a valid eGON signature.
- Load the whole SPL.
- Recalculate the checksum to verify the SPL is valid.

If one of those steps fails, we bail out and continue loading from the
user data partition. Otherwise we load from the selected boot partition.

Since the boot source is needed twice in the boot process, we cache the
result of this test to avoid doing this costly test multiple times.

This allows the very same image file to be put onto an SD card, into the
eMMC user data partition or into the eMMC boot partition, and safely
loads the whole of U-Boot from there.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoram: k3-am654: Make VTT regulator optional
Christian Gmeiner [Wed, 23 Mar 2022 15:04:28 +0000 (16:04 +0100)]
ram: k3-am654: Make VTT regulator optional

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoram: k3-am654: Write all configuration values
Dominic Rath [Wed, 23 Mar 2022 15:04:27 +0000 (16:04 +0100)]
ram: k3-am654: Write all configuration values

Makes it possible to use 16-bit DDR memory.

Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoconfigs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig
Dave Gerlach [Thu, 17 Mar 2022 17:03:46 +0000 (12:03 -0500)]
configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig

Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed
to calculate the size of DDR that is available.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoarm: dts: k3-am64-ddr: Add ss_cfg reg entry
Dave Gerlach [Thu, 17 Mar 2022 17:03:45 +0000 (12:03 -0500)]
arm: dts: k3-am64-ddr: Add ss_cfg reg entry

Add 'ss_cfg' memory region for memorycontroller node which is required
to enable ECC.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoboard: ti: am64x: Account for DDR size fixups if ECC is enabled
Dave Gerlach [Thu, 17 Mar 2022 17:03:44 +0000 (12:03 -0500)]
board: ti: am64x: Account for DDR size fixups if ECC is enabled

Call into k3-ddrss driver to fixup device tree and resize the available
amount of DDR if ECC is enabled.

A second fixup is required from A53 SPL to take the fixup as done from
R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes
this to the OS.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoram: k3-ddrss: Introduce ECC Functionality for full memory space
Dave Gerlach [Thu, 17 Mar 2022 17:03:43 +0000 (12:03 -0500)]
ram: k3-ddrss: Introduce ECC Functionality for full memory space

Introduce ECC Functionality for full memory space as implemented in the
DDRSS. The following is done to accomplish this:

 * Introduce a memory region "ss" to allow dt to provide DDRSS region,
   which is not the same as "ctl" which is the controller region.

 * Introduce a "ti,ecc-enable" flag which allows a memorycontroller
   instance to enable ecc.

 * Introduce functionality to properly program the DDRSS registers to
   enable ECC for the full DDR memory space if enabled with above flag.

 * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to
   account from DDR memory that must be reserved for ECC operation.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs
Dave Gerlach [Thu, 17 Mar 2022 17:03:42 +0000 (12:03 -0500)]
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs

The current address being read from dt actually represents the ddrss_ctl
memory region, while ddrss_ss region is something else. Introduce
ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper
purpose later so that we can avoid confusion.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agodt-bindings: memory-controller: Add information about ECC bindings
Dave Gerlach [Thu, 17 Mar 2022 17:03:41 +0000 (12:03 -0500)]
dt-bindings: memory-controller: Add information about ECC bindings

Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoboard: ti: am64x: Use fdt functions for ram and bank init
Dave Gerlach [Thu, 17 Mar 2022 17:03:40 +0000 (12:03 -0500)]
board: ti: am64x: Use fdt functions for ram and bank init

Use the appropriate fdtdec_setup_mem_size_base and
fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull
these values from DT, where they are already available, instead of
hardcoding them.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoarm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-spl
Dave Gerlach [Thu, 17 Mar 2022 17:03:39 +0000 (12:03 -0500)]
arm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-spl

Mark the memory node with u-boot,dm-spl so we can use it from early SPL.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoARM: dts: k3-am642: Correct timer frequency
Vignesh Raghavendra [Fri, 11 Mar 2022 15:53:22 +0000 (21:23 +0530)]
ARM: dts: k3-am642: Correct timer frequency

Timer0 runs at 200MHz,and the clock-frequency defined in DT is
incorrect. Fix it.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-By: Nishanth Menon <nm@ti.com>
2 years agoconfigs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick provider
Vignesh Raghavendra [Fri, 11 Mar 2022 15:53:21 +0000 (21:23 +0530)]
configs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick provider

On arm64 systems, recommendation is to use per-cpu timer for time
keeping. Currently AM64 ends up using DM timer as tick timer as driver
is enabled in the config. Drop OMAP DM Timer related configs, this will
switch to using armv8 per-cpu timer as tick timer for A53 SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-By: Nishanth Menon <nm@ti.com>
2 years agoconfigs: am64x_evm_r5_defconfig: Add support for ESM
Hari Nagalla [Wed, 9 Mar 2022 20:42:31 +0000 (14:42 -0600)]
configs: am64x_evm_r5_defconfig: Add support for ESM

Enable ESM driver for AM64x R5 SPL/u-boot builds.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoarch: arm: mach-k3: am642_init: Probe ESM nodes
Hari Nagalla [Wed, 9 Mar 2022 20:42:30 +0000 (14:42 -0600)]
arch: arm: mach-k3: am642_init: Probe ESM nodes

On AM64x devices, it is possible to route Main ESM0 error events to MCU
ESM. MCU ESM high error output can trigger the reset logic to reset the
device. So, for these devices we expect two ESM device nodes in the
device tree, one for Main ESM and the another MCU ESM in the device tree.
 When these ESM device nodes are properly configired it is possible to
route the Main RTI0 WWDT output to the MCU ESM high output through Main
ESM and trigger a device reset when
CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.

On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node
configurations.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoarm: dts: k3-am64: Add support for ESM device nodes
Hari Nagalla [Wed, 9 Mar 2022 20:42:29 +0000 (14:42 -0600)]
arm: dts: k3-am64: Add support for ESM device nodes

Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM
nodes to the AM64 device tree.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agomisc: k3_esm: Add functionality to set and route error events within K3SoC
Hari Nagalla [Wed, 9 Mar 2022 20:42:28 +0000 (14:42 -0600)]
misc: k3_esm: Add functionality to set and route error events within K3SoC

Add functionality to enable, set priority to the input events and to
route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main
ESM0 error events to MCU ESM. When these error events are routed to MCU
ESM high output, it can trigger the reset logic to reset the device,
when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.

K3 based J7 devices (ex: J721e) also have ESM modules, and the changes
to the driver does not impact those devices.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoboard: axy17lte: get board usable - add bootcmd and docs
Dzmitry Sankouski [Tue, 22 Feb 2022 18:49:54 +0000 (21:49 +0300)]
board: axy17lte: get board usable - add bootcmd and docs

U-boot is intended to replace linux kernel in android boot image(ABL), and
it's FIT payload to replace initramfs file. The boot process is similar to
boot image with linux:
- android bootloader (ABL) unpacks android boot image
- ABL sets `linux,initrd-start property` in chosen node in unpacked FDT
- ABL sets x0 register to FDT address, and passes control to u-boot
- u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable
- u-boot reads `linux,initrd-start` property,
and stores it in `prevbl_initrd_start_addr`

In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env
variable, and boils down to `bootm $prevbl_initrd_start_addr`.
If more control on boot process is desired, pack a boot script in
FIT image, and put it to default configuration

What done:
- Rearrange defconfig option order
- Add CONFIG_SAVE_PREV_BL_* options
- Doc updates:
  - remove wrong SBOOT memory corruption note, because
  memory is changed during u-boot bringup process,
  not by SBOOT
  - put payload on ramdisk place in abl boot image
  creation step

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
2 years agospl: mmc: extend spl_mmc_boot_mode() to take mmc argument
Andre Przywara [Mon, 12 Jul 2021 10:06:49 +0000 (11:06 +0100)]
spl: mmc: extend spl_mmc_boot_mode() to take mmc argument

Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.

Pass the pointer to the mmc struct to that function, so implementations
can make use of that.

Compile-tested for all users changed.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA)
Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3)
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agosunxi: clock: H6: Adjust PLL LDO before clock setup
Jernej Skrabec [Sun, 30 Jan 2022 14:27:15 +0000 (15:27 +0100)]
sunxi: clock: H6: Adjust PLL LDO before clock setup

BSP boot0 adjust PLL LDO regulator before clocks are initialized.
Let's do that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: clock: H6/H616: Add resistor calibration
Jernej Skrabec [Sun, 30 Jan 2022 14:27:14 +0000 (15:27 +0100)]
sunxi: clock: H6/H616: Add resistor calibration

BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: prcm: Add a few registers
Jernej Skrabec [Sun, 30 Jan 2022 14:27:13 +0000 (15:27 +0100)]
sunxi: prcm: Add a few registers

H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: H3: fix non working console on uart2
Angelo Dureghello [Sat, 9 Oct 2021 12:18:59 +0000 (14:18 +0200)]
sunxi: H3: fix non working console on uart2

Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.

Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoAdd ethernet0 alias in Nanopi NEO's device tree
Baltazár Radics [Sat, 26 Mar 2022 12:09:10 +0000 (13:09 +0100)]
Add ethernet0 alias in Nanopi NEO's device tree

This syncs the sun8i-h3-nanopi-neo.dts from the Linux tree, from tag
v5.18-rc1.
The alias is required to enable automatic MAC address generation.

Signed-off-by: Baltazár Radics <baltazar.radics@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoi2c: sun8i_rsb: Add support for DM clocks and resets
Samuel Holland [Fri, 18 Mar 2022 04:52:36 +0000 (23:52 -0500)]
i2c: sun8i_rsb: Add support for DM clocks and resets

Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.

This also has the added benefit of picking the right clock/reset
bits for H6 and new SoCs that have a rearranged PRCM MMIO space.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoi2c: sun8i_rsb: Initialize chips in .child_pre_probe
Samuel Holland [Fri, 18 Mar 2022 04:52:35 +0000 (23:52 -0500)]
i2c: sun8i_rsb: Initialize chips in .child_pre_probe

Chips attached to the RSB bus require an initialization command before
they can be used. (Specifically, this command programs the chip's
runtime address.) The driver does this in its .probe_chip hook, under
the assumption that .probe_chip is called during child probe. This is
not the case; .probe_chip is only called by dm_i2c_probe, which is
intended for use by board-level code, not for chips with OF nodes.

Since this initialization command must be run before a child chip can be
used, do it before probing each child.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoi2c: sun6i_p2wi: Add support for DM clocks and resets
Samuel Holland [Fri, 18 Mar 2022 04:52:34 +0000 (23:52 -0500)]
i2c: sun6i_p2wi: Add support for DM clocks and resets

Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoi2c: sun6i_p2wi: Initialize chips in .child_pre_probe
Samuel Holland [Fri, 18 Mar 2022 04:52:33 +0000 (23:52 -0500)]
i2c: sun6i_p2wi: Initialize chips in .child_pre_probe

Chips attached to the P2WI bus require an initialization command before
they can be used. (Specifically, this switches the chip from I2C mode
to P2WI mode.) The driver does this in its .probe_chip hook, under the
assumption that .probe_chip is called during child probe. This is not
the case; .probe_chip is only called by dm_i2c_probe, which is intended
for use by board-level code, not for chips with OF nodes.

Since this initialization command must be run before a child chip can be
used, do it before probing each child.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: Support building a SPL as a TOC0 image
Samuel Holland [Fri, 18 Mar 2022 05:00:45 +0000 (00:00 -0500)]
sunxi: Support building a SPL as a TOC0 image

Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: Support SPL in both eGON and TOC0 images
Samuel Holland [Fri, 18 Mar 2022 05:00:44 +0000 (00:00 -0500)]
sunxi: Support SPL in both eGON and TOC0 images

SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agotools: mkimage: Add Allwinner TOC0 support
Samuel Holland [Fri, 18 Mar 2022 05:00:43 +0000 (00:00 -0500)]
tools: mkimage: Add Allwinner TOC0 support

Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
completely different image type, known as TOC0.

A TOC0 image is composed of a header and two or more items. One item
is the firmware binary. The others form a chain linking the firmware
signature to the root-of-trust public key (ROTPK), which has its hash
burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256.

The pseudo-ASN.1 structure is manually assembled; this is done to work
around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0
implementation has been verified to work with the A50, A64, H5, H6,
and H616 SBROMs, and it may work with other SoCs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: specify architecture when generating SPL boot image
Icenowy Zheng [Fri, 15 Oct 2021 01:53:07 +0000 (20:53 -0500)]
sunxi: specify architecture when generating SPL boot image

As mkimage -T sunxi_egon now gains support for -A parameter, specify the
architecture when generating SPL boot image for sunxi.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agomkimage: sunxi_egon: add support for riscv
Icenowy Zheng [Fri, 15 Oct 2021 01:53:06 +0000 (20:53 -0500)]
mkimage: sunxi_egon: add support for riscv

There's now a sun20i family in sunxi, which uses RISC-V CPU.

Add support for making eGON.BT0 image for RISC-V.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agomkimage: sunxi_egon: refactor for multi-architecture support
Icenowy Zheng [Fri, 15 Oct 2021 01:53:05 +0000 (20:53 -0500)]
mkimage: sunxi_egon: refactor for multi-architecture support

Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agomkimage: add a flag to describe whether -A is specified
Icenowy Zheng [Fri, 15 Oct 2021 01:53:04 +0000 (20:53 -0500)]
mkimage: add a flag to describe whether -A is specified

The sunxi_egon type used to take no -A argument (because we assume sunxi
targets are all ARM). However, as Allwinner D1 appears as the first
RISC-V sunxi target, we need to support -A; in addition, as external
projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we
need to keep compatibility with command line without -A.

As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agospi: sun4i_spi: Remove non-DM pin setup
Samuel Holland [Sat, 28 Aug 2021 16:50:28 +0000 (11:50 -0500)]
spi: sun4i_spi: Remove non-DM pin setup

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add SPI0 pinmuxes
Samuel Holland [Sat, 28 Aug 2021 22:05:35 +0000 (17:05 -0500)]
pinctrl: sunxi: Add SPI0 pinmuxes

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopwm: sunxi: Remove non-DM pin setup
Samuel Holland [Sat, 28 Aug 2021 16:50:51 +0000 (11:50 -0500)]
pwm: sunxi: Remove non-DM pin setup

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add the A64 PWM pinmux
Samuel Holland [Sat, 28 Aug 2021 20:52:52 +0000 (15:52 -0500)]
pinctrl: sunxi: Add the A64 PWM pinmux

This is the only possible mux setting for the A64's PWM peripheral.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: Remove non-DM MMC pin setup
Samuel Holland [Sat, 28 Aug 2021 16:49:03 +0000 (11:49 -0500)]
sunxi: Remove non-DM MMC pin setup

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add MMC pinmuxes
Samuel Holland [Sat, 28 Aug 2021 21:51:03 +0000 (16:51 -0500)]
pinctrl: sunxi: Add MMC pinmuxes

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoi2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
Samuel Holland [Thu, 21 Oct 2021 04:01:29 +0000 (23:01 -0500)]
i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoi2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
Samuel Holland [Thu, 21 Oct 2021 04:01:29 +0000 (23:01 -0500)]
i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C

When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: Remove options and setup code for I2C2-I2C4
Samuel Holland [Thu, 21 Oct 2021 03:55:06 +0000 (22:55 -0500)]
sunxi: Remove options and setup code for I2C2-I2C4

These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add I2C pinmuxes
Samuel Holland [Sat, 28 Aug 2021 20:17:32 +0000 (15:17 -0500)]
pinctrl: sunxi: Add I2C pinmuxes

Where multiple options were available, the one matching board.c and the
device trees was chosen.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fixup H5 I2C1 pinmux]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agonet: sun8i_emac: Remove non-DM pin setup
Samuel Holland [Sat, 28 Aug 2021 16:49:40 +0000 (11:49 -0500)]
net: sun8i_emac: Remove non-DM pin setup

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add sun8i EMAC pinmuxes
Samuel Holland [Sat, 28 Aug 2021 18:34:29 +0000 (13:34 -0500)]
pinctrl: sunxi: Add sun8i EMAC pinmuxes

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: Remove non-DM GMAC pin setup
Samuel Holland [Sat, 28 Aug 2021 18:16:44 +0000 (13:16 -0500)]
sunxi: Remove non-DM GMAC pin setup

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add sunxi GMAC pinmuxes
Samuel Holland [Sat, 28 Aug 2021 18:13:52 +0000 (13:13 -0500)]
pinctrl: sunxi: Add sunxi GMAC pinmuxes

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agonet: sunxi_emac: Remove non-DM pin setup
Samuel Holland [Sat, 28 Aug 2021 18:22:41 +0000 (13:22 -0500)]
net: sunxi_emac: Remove non-DM pin setup

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add sun4i EMAC pinmuxes
Samuel Holland [Sat, 28 Aug 2021 18:21:36 +0000 (13:21 -0500)]
pinctrl: sunxi: Add sun4i EMAC pinmuxes

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agopinctrl: sunxi: Add UART pinmuxes
Samuel Holland [Sat, 28 Aug 2021 18:00:45 +0000 (13:00 -0500)]
pinctrl: sunxi: Add UART pinmuxes

This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: pinctrl: Implement pin configuration
Samuel Holland [Sun, 29 Aug 2021 02:10:47 +0000 (21:10 -0500)]
sunxi: pinctrl: Implement pin configuration

The sunxi pinctrl hardware has bias and drive control. Add driver
support for configuring those options.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: pinctrl: Implement get_pin_muxing function
Samuel Holland [Tue, 17 Aug 2021 05:52:00 +0000 (00:52 -0500)]
sunxi: pinctrl: Implement get_pin_muxing function

The pinmux command uses this function to display pinmux status.

Since the driver cannot map pin numbers to a list of supported
functions, only functions which are common across all pins can be
reported by name.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: pinctrl: Implement pin muxing functions
Samuel Holland [Tue, 17 Aug 2021 04:56:47 +0000 (23:56 -0500)]
sunxi: pinctrl: Implement pin muxing functions

Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.

We assume all pins associated with a function use the same mux value for
that function. This is generally true within a group of pins on a single
port, but generally false when some peripheral can be muxed to multiple
ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
But all of the port D pins use the same mux value, and so do all of the
port H pins. This applies even when the pins for some function are not
contiguous, and when the lower-numbered mux values are unused. A good
example of both of these cases is SPI0 on most SoCs.

This strategy saves a lot of space (which is especially important for
SPL), but where the mux value for a certain function differs across
ports, it forces us to choose a single port for that function at build
time. Since almost all boards use the default (i.e. reference design)
pin muxes[1], this is unlikely to be a problem.

[1]: See commit dda9fa734f81 ("sunxi: Simplify MMC pinmux selection")

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: add comment summarising the commit message]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: pinctrl: Create the driver skeleton
Samuel Holland [Fri, 13 Aug 2021 01:09:43 +0000 (20:09 -0500)]
sunxi: pinctrl: Create the driver skeleton

Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoboard: starqltechn: get board usable - add bootcmd and docs
Dzmitry Sankouski [Tue, 22 Feb 2022 18:49:53 +0000 (21:49 +0300)]
board: starqltechn: get board usable - add bootcmd and docs

U-boot is intended to replace linux kernel in android boot image(ABL), and
it's FIT payload to replace initramfs file. The boot process is similar to
boot image with linux:
- android bootloader (ABL) unpacks android boot image
- ABL sets `linux,initrd-start property` in chosen node in unpacked FDT
- ABL sets x0 register to FDT address, and passes control to u-boot
- u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable
- u-boot reads `linux,initrd-start` property,
and stores it in `prevbl_initrd_start_addr`

In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env
variable, and boils down to `bootm $prevbl_initrd_start_addr`.
If more control on boot process is desired, pack a boot script in
FIT image, and put it to default configuration

What done:
- strip unneeded config options
- add FIT image support
- add framebuffer node, u-boot logo and video console
- increase LMB_MAX_REGIONS, to store all linux dtb reserved memory regions
- add linux kernel image header

Uart driver causes hang, when u-boot is used in android boot image instead
of linux. Temporary disable console driver, until investigated and fixed.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
2 years agoarm: init: save previous bootloader data
Dzmitry Sankouski [Tue, 22 Feb 2022 18:49:52 +0000 (21:49 +0300)]
arm: init: save previous bootloader data

When u-boot is used as a chain-loaded bootloader (replacing OS kernel),
previous bootloader leaves data in RAM, that can be reused.

For example, on recent arm linux system, when chainloading u-boot,
there are initramfs and fdt in RAM prepared for OS booting. Initramfs
may be modified to store u-boot's payload, thus providing the ability to
use chainloaded u-boot to boot OS without any storage support.

Two config options added:
- SAVE_PREV_BL_INITRAMFS_START_ADDR
  saves initramfs start address to 'prevbl_initrd_start_addr' environment
  variable
- SAVE_PREV_BL_FDT_ADDR
  saves fdt address to 'prevbl_fdt_addr' environment variable

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2 years agoqemu-arm: Enable NVMe for distro boot
Alexander Graf [Sun, 27 Feb 2022 12:20:32 +0000 (13:20 +0100)]
qemu-arm: Enable NVMe for distro boot

We already support the NVMe commands and PCIe backend in the QEMU target,
so let's make it easy for anyone to consume them and enable NVMe distro
boot along the way!

With this patch, I can put an NVMe backed disk image into my QEMU VM and
have it automatically load a UEFI target blob.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2 years agoMerge branch 'next'
Tom Rini [Mon, 4 Apr 2022 14:45:33 +0000 (10:45 -0400)]
Merge branch 'next'

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoPrepare v2022.04
Tom Rini [Mon, 4 Apr 2022 14:31:32 +0000 (10:31 -0400)]
Prepare v2022.04

Signed-off-by: Tom Rini <trini@konsulko.com>