radeon: pad CS to 8 DW

Aligns the IB to 8 DWs.  The aligns the IB to the
CP fetch size.  r6xx also require at least 4 DW
alignment to avoid a hw bug.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
index b963140..b87c6b1 100644 (file)
--- a/radeon/radeon_cs_gem.c
+++ b/radeon/radeon_cs_gem.c
@@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs)
     unsigned i;
     int r;
 
+    while (cs->cdw & 7)
+       radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000);
+
 #if CS_BOF_DUMP
     cs_gem_dump_bof(cs);
 #endif