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(parent: 8a2e0fa) | patch
radeon: pad CS to 8 DW
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 6 Sep 2013 19:58:56 +0000 (15:58 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 6 Sep 2013 19:58:56 +0000 (15:58 -0400)
commit58d008883165ba35c83041fa9ed84937163d5f76
tree9c77d3d3484009b78a91d3e549db1a136113e130tree | snapshot
parent8a2e0fa917996e72bfc0dbdf228fc0bfb433d279commit | diff
radeon: pad CS to 8 DW

Aligns the IB to 8 DWs.  The aligns the IB to the
CP fetch size.  r6xx also require at least 4 DW
alignment to avoid a hw bug.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeon/radeon_cs_gem.c diff | blob | history
Domain: System / Kernel;