--- /dev/null
+NOP PHY driver
+
+This driver is used to stub PHY operations in a driver (USB, SATA).
+This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework
+and there is no actual PHY harwdare to drive.
+
+Required properties:
+- compatible : must contain "nop-phy"
+- #phy-cells : must contain <0>
+
+Example:
+
+nop_phy {
+ compatible = "nop-phy";
+ #phy-cells = <0>;
+};
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config SPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in spl before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
#
VERSION = 2017
-PATCHLEVEL = 07
+PATCHLEVEL = 09
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
else \
return 42; \
fi; \
LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
fi)
endef
CONFIG_CMD_MISC Misc functions like sleep etc
CONFIG_CMD_MMC * MMC memory mapped support
CONFIG_CMD_MII * MII utility commands
- CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_NFS NFS support
CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC
+ select USE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
+ select OF_CONTROL
select DM
- select DM_KEYBOARD
- select DM_SERIAL
- select DM_GPIO
- select DM_SPI
- select DM_SPI_FLASH
- select USB_EHCI_HCD
+ select DM_PCI
+ select PCI
+ select TIMER
+ select X86_TSC_TIMER
+ imply BLK
+ imply DM_ETH
+ imply DM_GPIO
+ imply DM_KEYBOARD
+ imply DM_MMC
+ imply DM_RTC
+ imply DM_SERIAL
+ imply DM_SCSI
+ imply DM_SPI
+ imply DM_SPI_FLASH
+ imply DM_USB
+ imply DM_VIDEO
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
imply CMD_IO
--- /dev/null
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
&uart2 {
status = "okay";
};
+
+&usb20_otg {
+ status = "okay";
+};
status = "disabled";
};
+ usb20_otg: usb@30040000 {
+ compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
+ "snps,dwc2";
+ reg = <0x30040000 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ hnp-srp-disable;
+ dr_mode = "otg";
+ status = "disabled";
+ };
+
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rk818;
+ eeprom0 = &i2c_eeprom_id;
};
ext_gmac: external-gmac-clock {
pagesize = <32>;
};
+ /* M24C32-D Identification page */
+ i2c_eeprom_id: eeprom@58 {
+ compatible = "atmel,24c32";
+ reg = <0x58>;
+ pagesize = <32>;
+ };
+
vdd_cpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
-#include "rk3399-sdram-ddr3-1333.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
+ regulator-init-microvolt = <950000>;
};
vccadc_ref: vccadc-ref {
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
config {
- u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */
+ u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
+ u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
cd-inverted;
status = "okay";
};
aliases {
console = &uarta;
- stdout-path = &uarta;
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
usb2 = "/usb@7d004000";
};
+ chosen {
+ stdout-path = &uarta;
+ };
+
host1x@50000000 {
dc@54200000 {
display-timings {
+
/*
* Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
*/
#ifdef CONFIG_SPL_BUILD
- .space 0x4 /* space for the 'RK33' */
+ /*
+ * We need to add 4 bytes of space for the 'RK33' at the
+ * beginning of the executable. However, as we want to keep
+ * this generic and make it applicable to builds that are like
+ * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
+ * TPL, but extra space needed in the SPL), we simply repeat
+ * the 'b reset' with the expectation that the first one will
+ * be overwritten, if this is the first stage contained in the
+ * final image created with mkimage)...
+ */
+ b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
#endif
b reset
struct rk3368_clk_priv {
struct rk3368_cru *cru;
- ulong rate;
- bool has_bwadj;
};
enum {
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
struct rk3399_cru *cru;
- ulong rate;
};
struct rk3399_pmuclk_priv {
struct rk3399_pmucru *pmucru;
- ulong rate;
};
struct rk3399_pmucru {
#define PWM_DUTY_POSTIVE (1 << 3)
#define PWM_DUTY_NEGATIVE (0 << 3)
+#define PWM_DUTY_MASK (1 << 3)
#define PWM_INACTIVE_POSTIVE (1 << 4)
#define PWM_INACTIVE_NEGATIVE (0 << 4)
+#define PWM_INACTIVE_MASK (1 << 4)
#define PWM_OUTPUT_LEFT (0 << 5)
#define PWM_OUTPUT_CENTER (1 << 5)
#define __ASM_ARCH_TIMER_H
struct rk_timer {
- unsigned int timer_load_count0;
- unsigned int timer_load_count1;
- unsigned int timer_curr_value0;
- unsigned int timer_curr_value1;
- unsigned int timer_ctrl_reg;
- unsigned int timer_int_status;
+ u32 timer_load_count0;
+ u32 timer_load_count1;
+ u32 timer_curr_value0;
+ u32 timer_curr_value1;
+ u32 timer_ctrl_reg;
+ u32 timer_int_status;
};
void rockchip_timer_init(void);
* @param node Node to look at
* @return peripheral ID, or PERIPH_ID_NONE if none
*/
-enum periph_id clock_decode_periph_id(const void *blob, int node);
+int clock_decode_periph_id(struct udevice *dev);
/**
* Checks if the oscillator bypass is enabled (XOBP bit)
TEGRA_SOC_UNKNOWN = -1,
};
+/* Tegra system controller (SYSCON) devices */
+enum {
+ TEGRA_SYSCON_PMC,
+};
+
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
*/
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
-void tegra_xusb_padctl_init(const void *fdt);
+void tegra_xusb_padctl_init(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
OMAP_EHCI_PORT_MODE_HSIC,
};
-#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
-#define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
-#else
#define OMAP_HS_USB_PORTS 3
-#endif
#define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY)
#define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL)
/* Perform cache writeback on input buffer */
flush_dcache_range(
- (u32)*image,
- (u32)*image + roundup(*size, ARCH_DMA_MINALIGN));
+ rounddown((u32)*image, ARCH_DMA_MINALIGN),
+ roundup((u32)*image + *size, ARCH_DMA_MINALIGN));
cert_addr = (uint32_t)*image;
sig_addr = find_sig_start((char *)*image, *size);
/* Perform cache writeback on output buffer */
flush_dcache_range(
- (u32)*image,
- (u32)*image + roundup(*size, ARCH_DMA_MINALIGN));
+ rounddown((u32)*image, ARCH_DMA_MINALIGN),
+ roundup((u32)*image + *size, ARCH_DMA_MINALIGN));
auth_exit:
if (result != 0) {
select SUPPORT_SPL
select SPL
select SPL_SEPARATE_BSS
+ select SPL_SERIAL_SUPPORT
+ select SPL_DRIVERS_MISC_SUPPORT
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
help
void back_to_bootrom(void)
{
-#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD)
- printf("Returning to boot ROM...");
+#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
+ puts("Returning to boot ROM...");
#endif
_back_to_bootrom_s();
}
while (1)
;
}
-
-void hang(void)
-{
- while (1)
- ;
-}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <asm/arch/timer.h>
#include <asm/io.h>
-#include <common.h>
#include <linux/types.h>
struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
obj-y += board.o
obj-y += clock_manager.o
-obj-y += fpga_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
+obj-y += fpga_manager.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
#include <altera.h>
-struct socfpga_fpga_manager {
- /* FPGA Manager Module */
- u32 stat; /* 0x00 */
- u32 ctrl;
- u32 dclkcnt;
- u32 dclkstat;
- u32 gpo; /* 0x10 */
- u32 gpi;
- u32 misci; /* 0x18 */
- u32 _pad_0x1c_0x82c[517];
-
- /* Configuration Monitor (MON) Registers */
- u32 gpio_inten; /* 0x830 */
- u32 gpio_intmask;
- u32 gpio_inttype_level;
- u32 gpio_int_polarity;
- u32 gpio_intstatus; /* 0x840 */
- u32 gpio_raw_intstatus;
- u32 _pad_0x848;
- u32 gpio_porta_eoi;
- u32 gpio_ext_porta; /* 0x850 */
- u32 _pad_0x854_0x85c[3];
- u32 gpio_1s_sync; /* 0x860 */
- u32 _pad_0x864_0x868[2];
- u32 gpio_ver_id_code;
- u32 gpio_config_reg2; /* 0x870 */
- u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
+#endif
/* FPGA CD Ratio Value */
#define CDRATIO_x1 0x0
#define CDRATIO_x4 0x2
#define CDRATIO_x8 0x3
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ u32 _pad_0x0_0x7[2];
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo;
+ u32 gpi;
+ u32 misci;
+ u32 _pad_0x1c_0x2f[5];
+ u32 emr_data0;
+ u32 emr_data1;
+ u32 emr_data2;
+ u32 emr_data3;
+ u32 emr_data4;
+ u32 emr_data5;
+ u32 emr_valid;
+ u32 emr_en;
+ u32 jtag_config;
+ u32 jtag_status;
+ u32 jtag_kick;
+ u32 _pad_0x5c_0x5f;
+ u32 jtag_data_w;
+ u32 jtag_data_r;
+ u32 _pad_0x68_0x6f[2];
+ u32 imgcfg_ctrl_00;
+ u32 imgcfg_ctrl_01;
+ u32 imgcfg_ctrl_02;
+ u32 _pad_0x7c_0x7f;
+ u32 imgcfg_stat;
+ u32 intr_masked_status;
+ u32 intr_mask;
+ u32 intr_polarity;
+ u32 dma_config;
+ u32 imgcfg_fifo_status;
+};
+
+/* Functions */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
+int fpgamgr_program_finish(void);
+int is_fpgamgr_user_mode(void);
+int fpgamgr_wait_early_user_mode(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_ARRIA10_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
+
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
+#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
+#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ /* FPGA Manager Module */
+ u32 stat; /* 0x00 */
+ u32 ctrl;
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo; /* 0x10 */
+ u32 gpi;
+ u32 misci; /* 0x18 */
+ u32 _pad_0x1c_0x82c[517];
+
+ /* Configuration Monitor (MON) Registers */
+ u32 gpio_inten; /* 0x830 */
+ u32 gpio_intmask;
+ u32 gpio_inttype_level;
+ u32 gpio_int_polarity;
+ u32 gpio_intstatus; /* 0x840 */
+ u32 gpio_raw_intstatus;
+ u32 _pad_0x848;
+ u32 gpio_porta_eoi;
+ u32 gpio_ext_porta; /* 0x850 */
+ u32 _pad_0x854_0x85c[3];
+ u32 gpio_1s_sync; /* 0x860 */
+ u32 _pad_0x864_0x868[2];
+ u32 gpio_ver_id_code;
+ u32 gpio_config_reg2; /* 0x870 */
+ u32 gpio_config_reg1;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_GEN5_H_ */
void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
struct socfpga_reset_manager {
u32 stat;
}
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
/* For SoCFPGA-VT, this is NOP. */
return 0;
}
#else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
int ret;
bool "Tegra124 family"
select TEGRA_ARMV7_COMMON
imply ENV_IS_IN_MMC
+ imply REGMAP
+ imply SYSCON
config TEGRA210
bool "Tegra210 family"
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include <asm/arch/emc.h>
#endif
-#include <power/as3722.h>
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
-#ifdef CONFIG_PMIC_AS3722
- err = as3722_init(NULL);
- if (err && err != -ENODEV)
- return err;
-#endif
#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_nand();
#endif
- tegra_xusb_padctl_init(gd->fdt_blob);
+ tegra_xusb_padctl_init();
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-int clock_decode_periph_id(const void *blob, int node)
+int clock_decode_periph_id(struct udevice *dev)
{
enum periph_id id;
u32 cell[2];
int err;
- err = fdtdec_get_int_array(blob, node, "clocks", cell,
- ARRAY_SIZE(cell));
+ err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
if (err)
return -1;
id = clk_id_to_periph_id(cell[1]);
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <debug_uart.h>
#include <spl.h>
#include <asm/io.h>
gpio_early_init_uart();
clock_early_init();
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
preloader_console_init();
}
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
+obj-y += pmc.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id tegra124_syscon_ids[] = {
+ { .compatible = "nvidia,tegra124-pmc", .data = TEGRA_SYSCON_PMC },
+};
+
+U_BOOT_DRIVER(syscon_tegra124) = {
+ .name = "tegra124_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = tegra124_syscon_ids,
+};
#include <common.h>
#include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
#include "../xusb-padctl-common.h"
.num_phys = ARRAY_SIZE(tegra124_phys),
};
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
{
- int count, nodes[1];
+ ofnode nodes[1];
+ int count = 0;
+ int ret;
+
+ debug("%s: start\n", __func__);
+ if (of_live_active()) {
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra124-xusb-padctl");
+
+ debug("np=%p\n", np);
+ if (np) {
+ nodes[0] = np_to_ofnode(np);
+ count = 1;
+ }
+ } else {
+ int node_offsets[1];
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+ node_offsets, ARRAY_SIZE(node_offsets));
+ for (i = 0; i < count; i++)
+ nodes[i] = offset_to_ofnode(node_offsets[i]);
+ }
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata))
- return;
+ ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
+ debug("%s: done, ret=%d\n", __func__, ret);
}
#include <common.h>
#include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
#include "../xusb-padctl-common.h"
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+DECLARE_GLOBAL_DATA_PTR;
+
enum tegra210_function {
TEGRA210_FUNC_SNPS,
TEGRA210_FUNC_XUSB,
.num_phys = ARRAY_SIZE(tegra210_phys),
};
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
{
- int count, nodes[1];
-
- debug("> %s(fdt=%p)\n", __func__, fdt);
-
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
- return;
+ ofnode nodes[1];
+ int count = 0;
+ int ret;
+
+ debug("%s: start\n", __func__);
+ if (of_live_active()) {
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra210-xusb-padctl");
+
+ debug("np=%p\n", np);
+ if (np) {
+ nodes[0] = np_to_ofnode(np);
+ count = 1;
+ }
+ } else {
+ int node_offsets[1];
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+ node_offsets, ARRAY_SIZE(node_offsets));
+ for (i = 0; i < count; i++)
+ nodes[i] = offset_to_ofnode(node_offsets[i]);
+ }
- debug("< %s()\n", __func__);
+ ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
+ debug("%s: done, ret=%d\n", __func__, ret);
}
static int
tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
struct tegra_xusb_padctl_group *group,
- const void *fdt, int node)
+ ofnode node)
{
unsigned int i;
- int len;
+ int len, ret;
- group->name = fdt_get_name(fdt, node, &len);
+ group->name = ofnode_get_name(node);
- len = fdt_stringlist_count(fdt, node, "nvidia,lanes");
+ len = ofnode_read_string_count(node, "nvidia,lanes");
if (len < 0) {
error("failed to parse \"nvidia,lanes\" property");
return -EINVAL;
group->num_pins = len;
for (i = 0; i < group->num_pins; i++) {
- group->pins[i] = fdt_stringlist_get(fdt, node, "nvidia,lanes",
- i, NULL);
- if (!group->pins[i]) {
+ ret = ofnode_read_string_index(node, "nvidia,lanes", i,
+ &group->pins[i]);
+ if (ret) {
error("failed to read string from \"nvidia,lanes\" property");
return -EINVAL;
}
group->num_pins = len;
- group->func = fdt_stringlist_get(fdt, node, "nvidia,function", 0, NULL);
- if (!group->func) {
+ ret = ofnode_read_string_index(node, "nvidia,function", 0,
+ &group->func);
+ if (ret) {
error("failed to parse \"nvidia,func\" property");
return -EINVAL;
}
- group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
+ group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
return 0;
}
static int
tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
struct tegra_xusb_padctl_config *config,
- const void *fdt, int node)
+ ofnode node)
{
- int subnode;
+ ofnode subnode;
- config->name = fdt_get_name(fdt, node, NULL);
+ config->name = ofnode_get_name(node);
- fdt_for_each_subnode(subnode, fdt, node) {
+ for (subnode = ofnode_first_subnode(node);
+ ofnode_valid(subnode);
+ subnode = ofnode_next_subnode(subnode)) {
struct tegra_xusb_padctl_group *group;
int err;
group = &config->groups[config->num_groups];
- err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
- subnode);
+ err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
if (err < 0) {
error("failed to parse group %s", group->name);
return err;
}
static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
- const void *fdt, int node)
+ ofnode node)
{
- int subnode, err;
+ ofnode subnode;
+ int err;
- err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
+ err = ofnode_read_resource(node, 0, &padctl->regs);
if (err < 0) {
error("registers not found");
return err;
}
- fdt_for_each_subnode(subnode, fdt, node) {
+ for (subnode = ofnode_first_subnode(node);
+ ofnode_valid(subnode);
+ subnode = ofnode_next_subnode(subnode)) {
struct tegra_xusb_padctl_config *config = &padctl->config;
- err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
+ debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
+ err = tegra_xusb_padctl_config_parse_dt(padctl, config,
subnode);
if (err < 0) {
error("failed to parse entry %s: %d",
continue;
}
}
+ debug("%s: done\n", __func__);
return 0;
}
struct tegra_xusb_padctl padctl;
-int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
- const struct tegra_xusb_padctl_soc *socdata)
+int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
+ const struct tegra_xusb_padctl_soc *socdata)
{
unsigned int i;
int err;
+ debug("%s: count=%d\n", __func__, count);
for (i = 0; i < count; i++) {
- if (!fdtdec_get_is_enabled(fdt, nodes[i]))
+ debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
+ if (!ofnode_is_available(nodes[i]))
continue;
padctl.socdata = socdata;
- err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]);
+ err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
if (err < 0) {
error("failed to parse DT: %d", err);
continue;
/* only a single instance is supported */
break;
}
+ debug("%s: done\n", __func__);
return 0;
}
#include <common.h>
#include <fdtdec.h>
+#include <dm/ofnode.h>
#include <asm/io.h>
#include <asm/arch-tegra/xusb-padctl.h>
+#include <linux/ioport.h>
struct tegra_xusb_padctl_lane {
const char *name;
struct tegra_xusb_padctl {
const struct tegra_xusb_padctl_soc *socdata;
struct tegra_xusb_padctl_config config;
- struct fdt_resource regs;
+ struct resource regs;
unsigned int enable;
};
writel(value, padctl->regs.start + offset);
}
-int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
- const struct tegra_xusb_padctl_soc *socdata);
+int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
+ const struct tegra_xusb_padctl_soc *socdata);
#endif
return -ENOSYS;
}
-void __weak tegra_xusb_padctl_init(const void *fdt)
+void __weak tegra_xusb_padctl_init(void)
{
}
mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
#else
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
- addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
#endif
#ifndef CONFIG_SPL_BUILD
or r5, r0, r0 /* flags - empty */
addi r31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET
swi r6, r31, GD_MALLOC_BASE
#endif
brai board_init_f
#else
addi r31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r6, r0, CONFIG_SPL_STACK_ADDR
swi r6, r31, GD_MALLOC_BASE
#endif
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
- li t2, CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
blt t0, t1, 1b
PTR_ADDIU t0, PTRSIZE
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
.endm
cmplw r3, r4
bne 1b
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* r3 = new stack pointer / pre-reloc malloc area */
- subi r3, r3, CONFIG_SYS_MALLOC_F_LEN
+ subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
/* Set pointer to pre-reloc malloc area in GD */
stw r3, GD_MALLOC_BASE(r4)
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_NAND
config ARCH_B4860
bool
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_NAND
config ARCH_BSC9131
bool
select SYS_FSL_SEC_COMPAT_4
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_NAND
config ARCH_BSC9132
bool
select FSL_IFC
imply CMD_EEPROM
imply CMD_MTDPARTS
+ imply CMD_NAND
config ARCH_C29X
bool
select SYS_FSL_SEC_COMPAT_6
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
+ imply CMD_NAND
config ARCH_MPC8536
bool
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply CMD_NAND
imply CMD_SATA
config ARCH_MPC8540
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select FSL_ELBC
+ imply CMD_NAND
config ARCH_MPC8572
bool
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply CMD_NAND
imply ENV_IS_IN_FLASH
config ARCH_P1010
select FSL_IFC
imply CMD_EEPROM
imply CMD_MTDPARTS
+ imply CMD_NAND
imply CMD_SATA
config ARCH_P1011
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply CMD_NAND
imply CMD_SATA
config ARCH_P1021
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply CMD_NAND
imply CMD_SATA
config ARCH_P1022
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
imply CMD_EEPROM
+ imply CMD_NAND
imply CMD_SATA
config ARCH_P1025
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
imply CMD_EEPROM
+ imply CMD_NAND
config ARCH_P2041
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
+ imply CMD_NAND
config ARCH_P3041
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
+ imply CMD_NAND
imply CMD_SATA
config ARCH_P4080
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_NAND
config ARCH_T1024
bool
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_NAND
imply CMD_MTDPARTS
config ARCH_T1040
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
imply CMD_MTDPARTS
+ imply CMD_NAND
imply CMD_SATA
config ARCH_T1042
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
imply CMD_MTDPARTS
+ imply CMD_NAND
imply CMD_SATA
config ARCH_T2080
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
+ imply CMD_NAND
config ARCH_T2081
bool
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
+ imply CMD_NAND
config ARCH_T4160
bool
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
+ imply CMD_NAND
config ARCH_T4240
bool
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
+ imply CMD_NAND
config BOOKE
bool
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* Leave 16+ byte for back chain termination and NULL return address */
- subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+ subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
#endif
/* End of RAM */
cmplw r4,r3
bne 1b
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
return 0;
}
-void os_putc(int ch)
-{
- putchar(ch);
-}
-
-void os_puts(const char *str)
-{
- while (*str)
- os_putc(*str++);
-}
-
int os_write_ram_buf(const char *fname)
{
struct sandbox_state *state = state_get_current();
memset(&data, '\0', sizeof(data));
gd = &data;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
setup_ram_buf(state);
source "arch/x86/cpu/qemu/Kconfig"
source "arch/x86/cpu/quark/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"
+source "arch/x86/cpu/tangier/Kconfig"
# architecture-specific options below
address of 0xfff90000 indicates that the image will be put at offset
0x90000 from the beginning of a 1MB flash device.
+config ROM_TABLE_ADDR
+ hex
+ default 0xf0000
+ help
+ All x86 tables happen to like the address range from 0x0f0000
+ to 0x100000. We use 0xf0000 as the starting address to store
+ those tables, including PIRQ routing table, Multi-Processor
+ table and ACPI table.
+
+config ROM_TABLE_SIZE
+ hex
+ default 0x10000
+
menu "System tables"
depends on !EFI && !SYS_COREBOOT
PLATFORM_CPPFLAGS += -fno-strict-aliasing
PLATFORM_CPPFLAGS += -fomit-frame-pointer
PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \
- $(call cc-option, -fno-unit-at-a-time)) \
- $(call cc-option, -mpreferred-stack-boundary=2)
+ $(call cc-option, -fno-unit-at-a-time))
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
ifeq ($(IS_32BIT),y)
PLATFORM_CPPFLAGS += -march=i386 -m32
else
-PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common
+PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -m64
endif
PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
+obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-y += lapic.o ioapic.o
obj-y += irq.o
ifndef CONFIG_$(SPL_)X86_64
config INTEL_BAYTRAIL
bool
select HAVE_FSP if !EFI
+ select ARCH_MISC_INIT if !EFI
+ imply HAVE_INTEL_ME if !EFI
+ imply ENABLE_MRC_CACHE
imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply INTEL_ICH6_GPIO
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply SCSI
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
+ imply USB_XHCI_HCD
+ imply VIDEO_VESA
if INTEL_BAYTRAIL
config INTERNAL_UART
#include <asm/acpi_s3.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
-#include <asm/ioapic.h>
-#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
header->checksum = table_compute_checksum(fadt, header->length);
}
-static int acpi_create_madt_irq_overrides(u32 current)
-{
- struct acpi_madt_irqoverride *irqovr;
- u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
- int length = 0;
-
- irqovr = (void *)current;
- length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
- irqovr = (void *)(current + length);
- length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
-
- return length;
-}
-
-u32 acpi_fill_madt(u32 current)
-{
- current += acpi_create_madt_lapics(current);
-
- current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
- io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irq_overrides(current);
-
- return current;
-}
-
void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
struct udevice *dev;
#include <asm/mrccache.h>
#include <asm/post.h>
-static struct pci_device_id mmc_supported[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
- {},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
- return pci_mmc_init("ValleyView SDHCI", mmc_supported);
-}
-
#ifndef CONFIG_EFI_APP
int arch_cpu_init(void)
{
config INTEL_BROADWELL
bool
select CACHE_MRC_BIN
+ select ARCH_EARLY_INIT_R
+ imply HAVE_INTEL_ME
+ imply ENABLE_MRC_CACHE
+ imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply INTEL_BROADWELL_GPIO
+ imply SCSI
+ imply SPI_FLASH
+ imply USB
+ imply USB_EHCI_HCD
+ imply VIDEO_BROADWELL_IGD
if INTEL_BROADWELL
uint32_t padding[4];
} __packed;
-int cpu_run_reference_code(void)
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCH). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+static int cpu_run_reference_code(void)
{
struct pei_data _pei_data __aligned(8);
struct pei_data *pei_data = &_pei_data;
return 0;
}
+
+int arch_early_init_r(void)
+{
+ return cpu_run_reference_code();
+}
config SYS_COREBOOT
bool
default y
+ imply ENV_IS_NOWHERE
+ imply AHCI_PCI
+ imply E1000
+ imply ICH_SPI
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
+ imply USB_XHCI_HCD
+ imply VIDEO_COREBOOT
imply CMD_CBFS
imply FS_CBFS
return x86_cpu_init_f();
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int checkcpu(void)
{
return 0;
{
return 0;
}
-
-int arch_misc_init(void)
-{
- return 0;
-}
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int checkcpu(void)
{
return 0;
{
return 0;
}
-
-int arch_misc_init(void)
-{
- return 0;
-}
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
select CACHE_MRC_BIN if HAVE_MRC
+ imply HAVE_INTEL_ME
+ imply ENABLE_MRC_CACHE
+ imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply INTEL_ICH6_GPIO
+ imply SCSI
+ imply SPI_FLASH
+ imply USB
+ imply USB_EHCI_HCD
+ imply VIDEO_VESA
if NORTHBRIDGE_INTEL_IVYBRIDGE
bd82x6x_sata_enable(dev);
else {
bd82x6x_sata_init(dev, pch);
- ret = ahci_probe_scsi(dev);
+ ret = ahci_probe_scsi_pci(dev);
if (ret)
return ret;
}
uint32_t tseg_base, uma_size, tolud;
uint64_t tom, me_base, touud;
uint64_t uma_memory_base = 0;
- uint64_t uma_memory_size;
unsigned long long tomk;
uint16_t ggc;
u32 val;
tolud += uma_size << 10;
/* UMA starts at old TOLUD */
uma_memory_base = tomk * 1024ULL;
- uma_memory_size = uma_size * 1024ULL;
debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
}
debug("%uM UMA", uma_size >> 10);
tomk -= uma_size;
uma_memory_base = tomk * 1024ULL;
- uma_memory_size += uma_size * 1024ULL;
/* GTT Graphics Stolen Memory Size (GGMS) */
uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
tomk -= uma_size;
uma_memory_base = tomk * 1024ULL;
- uma_memory_size += uma_size * 1024ULL;
debug(" and %uM GTT\n", uma_size >> 10);
}
uma_size = (uma_memory_base - tseg_base) >> 10;
tomk -= uma_size;
uma_memory_base = tomk * 1024ULL;
- uma_memory_size += uma_size * 1024ULL;
debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
debug("Available memory below 4GB: %lluM\n", tomk >> 10);
config QEMU
bool
+ select ARCH_EARLY_INIT_R
+ imply ENV_IS_NOWHERE
+ imply AHCI_PCI
+ imply E1000
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
+ imply VIDEO_VESA
if QEMU
config INTEL_QUARK
bool
select HAVE_RMU
+ select ARCH_EARLY_INIT_R
+ select ARCH_MISC_INIT
+ imply ENABLE_MRC_CACHE
+ imply ENV_IS_IN_SPI_FLASH
+ imply ETH_DESIGNWARE
+ imply ICH_SPI
+ imply INTEL_ICH6_GPIO
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
if INTEL_QUARK
#include <common.h>
#include <asm/acpi_table.h>
-#include <asm/ioapic.h>
-#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
header->checksum = table_compute_checksum(fadt, header->length);
}
-static int acpi_create_madt_irq_overrides(u32 current)
-{
- struct acpi_madt_irqoverride *irqovr;
- u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
- int length = 0;
-
- irqovr = (void *)current;
- length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
- irqovr = (void *)(current + length);
- length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
-
- return length;
-}
-
-u32 acpi_fill_madt(u32 current)
-{
- current += acpi_create_madt_lapics(current);
-
- current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
- io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irq_overrides(current);
-
- return current;
-}
-
void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
/* quark is a uni-processor */
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
-static struct pci_device_id mmc_supported[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
- {},
-};
-
static void quark_setup_mtrr(void)
{
u32 base, mask;
return 0;
}
-int cpu_mmc_init(bd_t *bis)
-{
- return pci_mmc_init("Quark SDHCI", mmc_supported);
-}
-
int arch_misc_init(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
bool
select HAVE_FSP
select HAVE_CMC
+ select ARCH_EARLY_INIT_R
+ imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply INTEL_ICH6_GPIO
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply PCH_GBE
+ imply SCSI
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
+ imply VIDEO_VESA
if INTEL_QUEENSBAY
#
obj-y += fsp_configs.o irq.o
-obj-y += tnc.o topcliff.o
+obj-y += tnc.o
+++ /dev/null
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <pci_ids.h>
-
-static struct pci_device_id mmc_supported[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
- {},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
- return pci_mmc_init("Topcliff SDHCI", mmc_supported);
-}
--- /dev/null
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_TANGIER
+ bool
+ depends on INTEL_MID
+ imply INTEL_MID_SERIAL
+ imply MMC
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply MMC_SDHCI_TANGIER
+ imply TANGIER_WATCHDOG
+ imply USB
+ imply USB_DWC3
+
+config SYS_CAR_ADDR
+ hex
+ default 0x19200000
+
+config SYS_CAR_SIZE
+ hex
+ default 0x4000
+ help
+ Space in bytes in eSRAM used as Cache-As-RAM (CAR).
+ Note this size must not exceed eSRAM's total size.
+
+config SYS_USB_OTG_BASE
+ hex
+ default 0xf9100000
--- /dev/null
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += car.o tangier.o sdram.o
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.section .text
+
+.globl car_init
+car_init:
+ jmp car_init_ret
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+#include <asm/global_data.h>
+#include <asm/sfi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * SFI tables are part of the first stage bootloader.
+ *
+ * U-Boot finds the System Table by searching 16-byte boundaries between
+ * physical address 0x000E0000 and 0x000FFFFF. U-Boot shall search this region
+ * starting at the low address and shall stop searching when the 1st valid SFI
+ * System Table is found.
+ */
+#define SFI_BASE_ADDR 0x000E0000
+#define SFI_LENGTH 0x00020000
+#define SFI_TABLE_LENGTH 16
+
+static int sfi_table_check(struct sfi_table_header *sbh)
+{
+ char chksum = 0;
+ char *pos = (char *)sbh;
+ u32 i;
+
+ if (sbh->len < SFI_TABLE_LENGTH)
+ return -ENXIO;
+
+ if (sbh->len > SFI_LENGTH)
+ return -ENXIO;
+
+ for (i = 0; i < sbh->len; i++)
+ chksum += *pos++;
+
+ if (chksum)
+ error("sfi: Invalid checksum\n");
+
+ /* Checksum is OK if zero */
+ return chksum ? -EILSEQ : 0;
+}
+
+static int sfi_table_is_type(struct sfi_table_header *sbh, const char *signature)
+{
+ return !strncmp(sbh->sig, signature, SFI_SIGNATURE_SIZE) &&
+ !sfi_table_check(sbh);
+}
+
+static struct sfi_table_simple *sfi_get_table_by_sig(unsigned long addr,
+ const char *signature)
+{
+ struct sfi_table_simple *sb;
+ u32 i;
+
+ for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) {
+ sb = (struct sfi_table_simple *)(addr + i);
+ if (sfi_table_is_type(&sb->header, signature))
+ return sb;
+ }
+
+ return NULL;
+}
+
+static struct sfi_table_simple *sfi_search_mmap(void)
+{
+ struct sfi_table_header *sbh;
+ struct sfi_table_simple *sb;
+ u32 sys_entry_cnt;
+ u32 i;
+
+ /* Find SYST table */
+ sb = sfi_get_table_by_sig(SFI_BASE_ADDR, SFI_SIG_SYST);
+ if (!sb) {
+ error("sfi: failed to locate SYST table\n");
+ return NULL;
+ }
+
+ sys_entry_cnt = (sb->header.len - sizeof(*sbh)) / 8;
+
+ /* Search through each SYST entry for MMAP table */
+ for (i = 0; i < sys_entry_cnt; i++) {
+ sbh = (struct sfi_table_header *)(unsigned long)sb->pentry[i];
+
+ if (sfi_table_is_type(sbh, SFI_SIG_MMAP))
+ return (struct sfi_table_simple *)sbh;
+ }
+
+ error("sfi: failed to locate SFI MMAP table\n");
+ return NULL;
+}
+
+#define sfi_for_each_mentry(i, sb, mentry) \
+ for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry; \
+ i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry); \
+ i++, mentry++) \
+
+static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries)
+{
+ struct sfi_table_simple *sb;
+ struct sfi_mem_entry *mentry;
+ unsigned long long start, end, size;
+ int type, total = 0;
+ u32 i;
+
+ sb = sfi_search_mmap();
+ if (!sb)
+ return 0;
+
+ sfi_for_each_mentry(i, sb, mentry) {
+ start = mentry->phys_start;
+ size = mentry->pages << 12;
+ end = start + size;
+
+ if (start > end)
+ continue;
+
+ /* translate SFI mmap type to E820 map type */
+ switch (mentry->type) {
+ case SFI_MEM_CONV:
+ type = E820_RAM;
+ break;
+ case SFI_MEM_UNUSABLE:
+ case SFI_RUNTIME_SERVICE_DATA:
+ continue;
+ default:
+ type = E820_RESERVED;
+ }
+
+ if (total == E820MAX)
+ break;
+ entries[total].addr = start;
+ entries[total].size = size;
+ entries[total].type = type;
+
+ total++;
+ }
+
+ return total;
+}
+
+static int sfi_get_bank_size(void)
+{
+ struct sfi_table_simple *sb;
+ struct sfi_mem_entry *mentry;
+ int bank = 0;
+ u32 i;
+
+ sb = sfi_search_mmap();
+ if (!sb)
+ return 0;
+
+ sfi_for_each_mentry(i, sb, mentry) {
+ if (mentry->type != SFI_MEM_CONV)
+ continue;
+
+ gd->bd->bi_dram[bank].start = mentry->phys_start;
+ gd->bd->bi_dram[bank].size = mentry->pages << 12;
+ bank++;
+ }
+
+ return bank;
+}
+
+static phys_size_t sfi_get_ram_size(void)
+{
+ struct sfi_table_simple *sb;
+ struct sfi_mem_entry *mentry;
+ phys_size_t ram = 0;
+ u32 i;
+
+ sb = sfi_search_mmap();
+ if (!sb)
+ return 0;
+
+ sfi_for_each_mentry(i, sb, mentry) {
+ if (mentry->type != SFI_MEM_CONV)
+ continue;
+
+ ram += mentry->pages << 12;
+ }
+
+ debug("sfi: RAM size %llu\n", ram);
+ return ram;
+}
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+ return sfi_setup_e820(max_entries, entries);
+}
+
+int dram_init_banksize(void)
+{
+ sfi_get_bank_size();
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = sfi_get_ram_size();
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int arch_cpu_init(void)
+{
+ return x86_cpu_init_f();
+}
+
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
+}
cougarcanyon2.dtb \
crownbay.dtb \
dfi-bt700-q7x-151.dtb \
+ edison.dtb \
efi.dtb \
galileo.dtb \
minnowmax.dtb \
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+ fsp,enable-xhci;
+#endif
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
pad-offset = <0x3a0>;
mode-func = <1>;
};
+
+ xhci_hub_reset: usb_ulpi_stp@0 {
+ gpio-offset = <0xa0 10>;
+ pad-offset = <0x23b0>;
+ mode-func = <0>;
+ mode-gpio;
+ output-value = <1>;
+ direction = <PIN_OUTPUT>;
+ };
};
chosen {
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+ fsp,enable-xhci;
+#endif
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "Intel Edison";
+ compatible = "intel,edison";
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <1>;
+ intel,apic-id = <2>;
+ };
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+ 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+ };
+
+ serial0: serial@ff010180 {
+ compatible = "intel,mid-uart";
+ reg = <0xff010180 0x100>;
+ reg-shift = <0>;
+ clock-frequency = <29491200>;
+ current-speed = <115200>;
+ };
+
+ emmc: mmc@ff3fc000 {
+ compatible = "intel,sdhci-tangier";
+ reg = <0xff3fc000 0x1000>;
+ };
+
+/*
+ * FIXME: For now U-Boot DM model doesn't allow to power up this controller.
+ * Enabling it will make U-Boot hang.
+ *
+ sdcard: mmc@ff3fa000 {
+ compatible = "intel,sdhci-tangier";
+ reg = <0xff3fa000 0x1000>;
+ };
+ */
+
+ pmu: power@ff00b000 {
+ compatible = "intel,pmu-mid";
+ reg = <0xff00b000 0x1000>;
+ };
+
+ scu: ipc@ff009000 {
+ compatible = "intel,scu-ipc";
+ reg = <0xff009000 0x1000>;
+ };
+};
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+ fsp,enable-xhci;
+#endif
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
u32 flags;
struct acpi_gen_regaddr reset_reg;
u8 reset_value;
- u8 res3;
- u8 res4;
- u8 res5;
+ u16 arm_boot_arch;
+ u8 minor_revision;
u32 x_firmware_ctl_l;
u32 x_firmware_ctl_h;
u32 x_dsdt_l;
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
u8 cpu, u16 flags, u8 lint);
u32 acpi_fill_madt(u32 current);
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end);
+u32 acpi_fill_mcfg(u32 current);
void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
/**
* enter_acpi_mode() - enter into ACPI mode
*/
u32 cpu_get_stepping(void);
-/**
- * cpu_run_reference_code() - Run the platform reference code
- *
- * Some platforms require a binary blob to be executed once SDRAM is
- * available. This is used to set up various platform features, such as the
- * platform controller hub (PCH). This function should be implemented by the
- * CPU-specific code.
- *
- * @return 0 on success, -ve on failure
- */
-int cpu_run_reference_code(void);
-
#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_X86_DMA_MAPPING_H
+#define __ASM_X86_DMA_MAPPING_H
+
+#define dma_mapping_error(x, y) 0
+
+enum dma_data_direction {
+ DMA_BIDIRECTIONAL = 0,
+ DMA_TO_DEVICE = 1,
+ DMA_FROM_DEVICE = 2,
+};
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+ free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+}
+
+#endif /* __ASM_X86_DMA_MAPPING_H */
u64 attrib;
};
+/* Memory type definitions */
+enum sfi_mem_type {
+ SFI_MEM_RESERVED,
+ SFI_LOADER_CODE,
+ SFI_LOADER_DATA,
+ SFI_BOOT_SERVICE_CODE,
+ SFI_BOOT_SERVICE_DATA,
+ SFI_RUNTIME_SERVICE_CODE,
+ SFI_RUNTIME_SERVICE_DATA,
+ SFI_MEM_CONV,
+ SFI_MEM_UNUSABLE,
+ SFI_ACPI_RECLAIM,
+ SFI_ACPI_NVS,
+ SFI_MEM_MMIO,
+ SFI_MEM_IOPORT,
+ SFI_PAL_CODE,
+ SFI_MEM_TYPEMAX,
+};
+
struct __packed sfi_cpu_table_entry {
u32 apic_id;
};
#include <tables_csum.h>
-/*
- * All x86 tables happen to like the address range from 0xf0000 to 0x100000.
- * We use 0xf0000 as the starting address to store those tables, including
- * PIRQ routing table, Multi-Processor table and ACPI table.
- */
-#define ROM_TABLE_ADDR 0xf0000
-#define ROM_TABLE_END 0xfffff
+#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR
+#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
#define ROM_TABLE_ALIGN 1024
#include <cpu.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <version.h>
#include <asm/acpi/global_nvs.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/lapic.h>
+#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
memcpy(header->signature, signature, 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+ header->oem_revision = U_BOOT_BUILD_DATE;
memcpy(header->aslc_id, ASLC_ID, 4);
}
return lapic_nmi->length;
}
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+ struct acpi_madt_irqoverride *irqovr;
+ u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+ int length = 0;
+
+ irqovr = (void *)current;
+ length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+ irqovr = (void *)(current + length);
+ length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+ return length;
+}
+
+__weak u32 acpi_fill_madt(u32 current)
+{
+ current += acpi_create_madt_lapics(current);
+
+ current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+ io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irq_overrides(current);
+
+ return current;
+}
+
static void acpi_create_madt(struct acpi_madt *madt)
{
struct acpi_table_header *header = &(madt->header);
header->checksum = table_compute_checksum((void *)madt, header->length);
}
-static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
- u32 base, u16 seg_nr, u8 start, u8 end)
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end)
{
memset(mmconfig, 0, sizeof(*mmconfig));
mmconfig->base_address_l = base;
return sizeof(struct acpi_mcfg_mmconfig);
}
-static u32 acpi_fill_mcfg(u32 current)
+__weak u32 acpi_fill_mcfg(u32 current)
{
current += acpi_create_mcfg_mmconfig
((struct acpi_mcfg_mmconfig *)current,
debug("ACPI: done\n");
+ /* Don't touch ACPI hardware on HW reduced platforms */
+ if (fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)
+ return current;
+
/*
* Other than waiting for OSPM to request us to switch to ACPI mode,
* do it by ourselves, since SMI will not be triggered.
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select BOARD_EARLY_INIT_F
+ select SPI_FLASH_MACRONIX
config PCIE_ECAM_BASE
default 0xe0000000
return 0;
}
-
-int arch_early_init_r(void)
-{
- return 0;
-}
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
+/* TODO: Convert to driver model
struct udevice *pmic;
int err;
error("failed to set SD4 voltage: %d\n", err);
return err;
}
+*/
return 0;
}
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select SPI_FLASH_STMICRO
config PCIE_ECAM_BASE
default 0xe0000000
return 0;
}
-int arch_early_init_r(void)
-{
- return 0;
-}
-
int board_late_init(void)
{
struct udevice *dev;
config SYS_TEXT_BASE
default 0x01110000
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ imply SPI_FLASH_ATMEL
+ imply SPI_FLASH_EON
+ imply SPI_FLASH_GIGADEVICE
+ imply SPI_FLASH_MACRONIX
+ imply SPI_FLASH_SPANSION
+ imply SPI_FLASH_STMICRO
+ imply SPI_FLASH_SST
+ imply SPI_FLASH_WINBOND
+
comment "coreboot-specific options"
config SYS_CONFIG_NAME
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += coreboot_start.o coreboot.o
+obj-y += coreboot_start.o
+++ /dev/null
-/*
- * Copyright (C) 2013 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <cros_ec.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
- return 0;
-}
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select SPI_FLASH_STMICRO
config PCIE_ECAM_BASE
default 0xe0000000
return 0;
}
+
+int board_late_init(void)
+{
+ struct gpio_desc desc;
+ int ret;
+
+ ret = dm_gpio_lookup_name("F10", &desc);
+ if (ret)
+ debug("gpio ret=%d\n", ret);
+ ret = dm_gpio_request(&desc, "xhci_hub_reset");
+ if (ret)
+ debug("gpio_request ret=%d\n", ret);
+ ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ if (ret)
+ debug("gpio dir ret=%d\n", ret);
+
+ /* Pull xHCI hub reset to low (active low) */
+ dm_gpio_set_value(&desc, 0);
+
+ /* Wait at least 5 ms, so lets choose 10 to be safe */
+ mdelay(10);
+
+ /* Pull xHCI hub reset to high (active low) */
+ dm_gpio_set_value(&desc, 1);
+
+ return 0;
+}
*/
#include <common.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
- return 0;
-}
select NORTHBRIDGE_INTEL_IVYBRIDGE
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xf0000000
*/
#include <common.h>
-#include <cros_ec.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
- return 0;
-}
-
-int board_early_init_f(void)
-{
- return 0;
-}
select INTEL_BROADWELL
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xf0000000
*/
#include <common.h>
-#include <asm/cpu.h>
-
-int arch_early_init_r(void)
-{
- return cpu_run_reference_code();
-}
-
-int board_early_init_f(void)
-{
- return 0;
-}
select NORTHBRIDGE_INTEL_IVYBRIDGE
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config SYS_CAR_ADDR
hex
*/
#include <common.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
- return 0;
-}
-
-int board_early_init_f(void)
-{
- return 0;
-}
Intel Platform Controller Hub EG20T, other system components and
peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+config TARGET_EDISON
+ bool "Edison"
+ help
+ This is the Intel Edison Compute Module. It contains a dual core Intel
+ Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB
+ eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
+
config TARGET_GALILEO
bool "Galileo"
help
source "board/intel/bayleybay/Kconfig"
source "board/intel/cougarcanyon2/Kconfig"
source "board/intel/crownbay/Kconfig"
+source "board/intel/edison/Kconfig"
source "board/intel/galileo/Kconfig"
source "board/intel/minnowmax/Kconfig"
select X86_RESET_VECTOR
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xe0000000
select NORTHBRIDGE_INTEL_IVYBRIDGE
select HAVE_FSP
select BOARD_ROMSIZE_KB_2048
+ select BOARD_EARLY_INIT_F
+ select SPI_FLASH_WINBOND
endif
select X86_RESET_VECTOR
select INTEL_QUEENSBAY
select BOARD_ROMSIZE_KB_1024
+ select BOARD_EARLY_INIT_F
+ select SPI_FLASH_SST
endif
--- /dev/null
+if TARGET_EDISON
+
+config SYS_BOARD
+ default "edison"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "tangier"
+
+config SYS_CONFIG_NAME
+ default "edison"
+
+config SYS_TEXT_BASE
+ default 0x01101000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_LOAD_FROM_32_BIT
+ select INTEL_MID
+ select INTEL_TANGIER
+ select BOARD_LATE_INIT
+ select MD5
+
+endif
--- /dev/null
+Intel Edison Board
+M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+S: Maintained
+F: board/intel/edison
+F: include/configs/edison.h
+F: configs/edison_defconfig
--- /dev/null
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += start.o edison.o
--- /dev/null
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
+#
+
+# Add 4096 bytes of zeroes to u-boot.bin
+quiet_cmd_mkalign_eds = EDSALGN $@
+cmd_mkalign_eds = \
+ dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \
+ mv $@ $^
+
+ALL-y += u-boot-align.bin
+u-boot-align.bin: u-boot.bin
+ $(call if_changed,mkalign_eds)
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <mmc.h>
+#include <u-boot/md5.h>
+#include <usb.h>
+#include <watchdog.h>
+
+#include <linux/usb/gadget.h>
+
+#include <asm/cache.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_USB_OTG_BASE,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+int usb_gadget_handle_interrupts(int controller_index)
+{
+ dwc3_uboot_handle_interrupt(controller_index);
+ WATCHDOG_RESET();
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ if (index == 0 && init == USB_INIT_DEVICE)
+ return dwc3_uboot_init(&dwc3_device_data);
+ return -EINVAL;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_uboot_exit(index);
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static void assign_serial(void)
+{
+ struct mmc *mmc = find_mmc_device(0);
+ unsigned char ssn[16];
+ char usb0addr[18];
+ char serial[33];
+ int i;
+
+ if (!mmc)
+ return;
+
+ md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn);
+
+ snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x",
+ ssn[13], ssn[14], ssn[15]);
+ setenv("usb0addr", usb0addr);
+
+ for (i = 0; i < 16; i++)
+ snprintf(&serial[2 * i], 3, "%02x", ssn[i]);
+ setenv("serial#", serial);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ saveenv();
+#endif
+}
+
+static void assign_hardware_id(void)
+{
+ struct ipc_ifwi_version v;
+ char hardware_id[4];
+ int ret;
+
+ ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4);
+ if (ret < 0)
+ printf("Can't retrieve hardware revision\n");
+
+ snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id);
+ setenv("hardware_id", hardware_id);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ saveenv();
+#endif
+}
+
+int board_late_init(void)
+{
+ if (!getenv("serial#"))
+ assign_serial();
+
+ if (!getenv("hardware_id"))
+ assign_hardware_id();
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp early_board_init_ret
select X86_RESET_VECTOR
select INTEL_QUARK
select BOARD_ROMSIZE_KB_1024
+ select SPI_FLASH_WINBOND
config SMBIOS_PRODUCT_NAME
default "GalileoGen2"
#include <asm/arch/device.h>
#include <asm/arch/quark.h>
-int board_early_init_f(void)
-{
- return 0;
-}
-
/*
* Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
*
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_STMICRO
config PCIE_ECAM_BASE
default 0xe0000000
#define GPIO_BANKE_NAME "gpioe"
-int arch_early_init_r(void)
-{
- return 0;
-}
-
int misc_init_r(void)
{
struct udevice *dev;
*/
#include <common.h>
+#include <dm.h>
#include <power/as3722.h>
+#include <power/pmic.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
}
#ifdef CONFIG_PCI_TEGRA
-int tegra_pcie_board_init(void)
+/* TODO: Convert to driver model */
+static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
{
- struct udevice *pmic;
int err;
- err = as3722_init(&pmic);
+ if (sd > 6)
+ return -EINVAL;
+
+ err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
if (err) {
- error("failed to initialize AS3722 PMIC: %d\n", err);
+ error("failed to update SD control register: %d", err);
return err;
}
- err = as3722_sd_enable(pmic, 4);
- if (err < 0) {
- error("failed to enable SD4: %d\n", err);
- return err;
+ return 0;
+}
+
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_as3722), &dev);
+ if (ret) {
+ debug("%s: Failed to find PMIC\n", __func__);
+ return ret;
}
- err = as3722_sd_set_voltage(pmic, 4, 0x24);
- if (err < 0) {
- error("failed to set SD4 voltage: %d\n", err);
- return err;
+ ret = as3722_sd_enable(dev, 4);
+ if (ret < 0) {
+ error("failed to enable SD4: %d\n", ret);
+ return ret;
+ }
+
+ ret = as3722_sd_set_voltage(dev, 4, 0x24);
+ if (ret < 0) {
+ error("failed to set SD4 voltage: %d\n", ret);
+ return ret;
}
return 0;
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
int tegra_lcd_pmic_init(int board_id)
{
- struct udevice *pmic;
+ struct udevice *dev;
int ret;
- ret = as3722_get(&pmic);
- if (ret)
- return -ENOENT;
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_as3722), &dev);
+ if (ret) {
+ debug("%s: Failed to find PMIC\n", __func__);
+ return ret;
+ }
if (board_id == 0)
- as3722_write(pmic, 0x00, 0x3c);
+ pmic_reg_write(dev, 0x00, 0x3c);
else
- as3722_write(pmic, 0x00, 0x50);
- as3722_write(pmic, 0x12, 0x10);
- as3722_write(pmic, 0x0c, 0x07);
- as3722_write(pmic, 0x20, 0x10);
+ pmic_reg_write(dev, 0x00, 0x50);
+ pmic_reg_write(dev, 0x12, 0x10);
+ pmic_reg_write(dev, 0x0c, 0x07);
+ pmic_reg_write(dev, 0x20, 0x10);
return 0;
}
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SUNXI_AHCI) += ahci.o
+endif
obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o
#include <common.h>
#include <ahci.h>
+#include <dm.h>
#include <scsi.h>
#include <errno.h>
#include <asm/io.h>
/* This magic PHY initialisation was taken from the Allwinner releases
* and Linux driver, but is completely undocumented.
*/
-static int sunxi_ahci_phy_init(u32 base)
+static int sunxi_ahci_phy_init(u8 *reg_base)
{
- u8 *reg_base = (u8 *)base;
u32 reg_val;
int timeout;
return 0;
}
+#ifndef CONFIG_DM_SCSI
void scsi_init(void)
{
- if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
+ if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0)
return;
ahci_init((void __iomem *)SUNXI_SATA_BASE);
}
+#else
+static int sunxi_sata_probe(struct udevice *dev)
+{
+ ulong base;
+ u8 *reg;
+ int ret;
+
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE) {
+ debug("%s: Failed to find address (err=%d\n)", __func__, ret);
+ return -EINVAL;
+ }
+ reg = (u8 *)base;
+ ret = sunxi_ahci_phy_init(reg);
+ if (ret) {
+ debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
+ return ret;
+ }
+ ret = ahci_probe_scsi(dev, base);
+ if (ret) {
+ debug("%s: Failed to probe (err=%d\n)", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sunxi_sata_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+ int ret;
+
+ ret = ahci_bind_scsi(dev, &scsi_dev);
+ if (ret) {
+ debug("%s: Failed to bind (err=%d\n)", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id sunxi_ahci_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(ahci_sunxi_drv) = {
+ .name = "ahci_sunxi",
+ .id = UCLASS_AHCI,
+ .of_match = sunxi_ahci_ids,
+ .bind = sunxi_sata_bind,
+ .probe = sunxi_sata_probe,
+};
+#endif
#include <ram.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
-#include <misc.h>
#include <asm/setup.h>
#include <asm/arch/periph.h>
#include <power/regulator.h>
#include <u-boot/sha256.h>
-#define RK3399_CPUID_OFF 0x7
-#define RK3399_CPUID_LEN 0x10
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define RK3399_CPUID_OFF 0x7
-#define RK3399_CPUID_LEN 0x10
-
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
static void setup_serial(void)
{
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+
struct udevice *dev;
int ret, i;
- u8 cpuid[RK3399_CPUID_LEN];
- u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2];
- char cpuid_str[RK3399_CPUID_LEN * 2 + 1];
+ u8 cpuid[cpuid_length];
+ u8 low[cpuid_length/2], high[cpuid_length/2];
+ char cpuid_str[cpuid_length * 2 + 1];
u64 serialno;
char serialno_str[16];
}
/* read the cpu_id range from the efuses */
- ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid));
+ ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid));
if (ret) {
debug("%s: reading cpuid from the efuses failed\n",
__func__);
imply CMD_SPI
imply CMD_TIME
imply CMD_USB if USB
+ imply ENV_IS_IN_FAT if MMC_OMAP_HS
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
+ /* TODO: Convert to driver model
struct udevice *pmic;
int err;
error("failed to set GPIO#2 high: %d\n", err);
return err;
}
+ */
/* Reset I210 Gigabit Ethernet Controller */
gpio_request(LAN_RESET_N, "LAN_RESET_N");
gpio_direction_output(TEGRA_GPIO(O, 6), 0);
/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
+ /* TODO: Convert to driver model
err = as3722_ldo_enable(pmic, 9);
if (err < 0) {
error("failed to enable LDO9: %d\n", err);
error("failed to set LDO10 voltage: %d\n", err);
return err;
}
+ */
mdelay(100);
gpio_set_value(TEGRA_GPIO(O, 6), 1);
/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
+ /* TODO: Convert to driver model
err = as3722_ldo_set_voltage(pmic, 9, 0xff);
if (err < 0) {
error("failed to set LDO9 voltage: %d\n", err);
error("failed to set LDO10 voltage: %d\n", err);
return err;
}
+ */
mdelay(100);
gpio_set_value(LAN_RESET_N, 1);
#ifdef CONFIG_BOARD_TYPES
printf("Board Type = %ld\n", gd->board_type);
#endif
-#ifdef CONFIG_SYS_MALLOC_F
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
- CONFIG_SYS_MALLOC_F_LEN);
+ CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
if (gd->fdt_blob)
printf("fdt_blob = %p\n", gd->fdt_blob);
DECLARE_GLOBAL_DATA_PTR;
+static uint8_t efi_obj_list_initalized;
+
/*
* When booting using the "bootefi" command, we don't know which
* physical device the file came from. So we create a pseudo-device
}
};
-static efi_status_t EFIAPI bootefi_open_dp(void *handle, efi_guid_t *protocol,
- void **protocol_interface, void *agent_handle,
- void *controller_handle, uint32_t attributes)
-{
- *protocol_interface = bootefi_device_path;
- return EFI_SUCCESS;
-}
-
/* The EFI loaded_image interface for the image executed via "bootefi" */
static struct efi_loaded_image loaded_image_info = {
.device_handle = bootefi_device_path,
* return handle which points to loaded_image_info
*/
.guid = &efi_guid_loaded_image,
- .open = &efi_return_handle,
+ .protocol_interface = &loaded_image_info,
},
{
/*
* bootefi_device_path
*/
.guid = &efi_guid_device_path,
- .open = &bootefi_open_dp,
+ .protocol_interface = bootefi_device_path,
+ },
+ {
+ .guid = &efi_guid_console_control,
+ .protocol_interface = (void *) &efi_console_control
+ },
+ {
+ .guid = &efi_guid_device_path_to_text_protocol,
+ .protocol_interface = (void *) &efi_device_path_to_text
},
},
};
/* When asking for the device path interface, return
* bootefi_device_path */
.guid = &efi_guid_device_path,
- .open = &bootefi_open_dp,
+ .protocol_interface = bootefi_device_path
}
},
};
+/* Initialize and populate EFI object list */
+static void efi_init_obj_list(void)
+{
+ efi_obj_list_initalized = 1;
+
+ list_add_tail(&loaded_image_info_obj.link, &efi_obj_list);
+ list_add_tail(&bootefi_device_obj.link, &efi_obj_list);
+ efi_console_register();
+#ifdef CONFIG_PARTITIONS
+ efi_disk_register();
+#endif
+#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
+ efi_gop_register();
+#endif
+#ifdef CONFIG_NET
+ void *nethandle = loaded_image_info.device_handle;
+ efi_net_register(&nethandle);
+
+ if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
+ loaded_image_info.device_handle = nethandle;
+ else
+ loaded_image_info.device_handle = bootefi_device_path;
+#endif
+#ifdef CONFIG_GENERATE_SMBIOS_TABLE
+ efi_smbios_register();
+#endif
+
+ /* Initialize EFI runtime services */
+ efi_reset_system_init();
+ efi_get_time_init();
+}
+
static void *copy_fdt(void *fdt)
{
u64 fdt_size = fdt_totalsize(fdt);
return new_fdt;
}
+static ulong efi_do_enter(void *image_handle,
+ struct efi_system_table *st,
+ asmlinkage ulong (*entry)(void *image_handle,
+ struct efi_system_table *st))
+{
+ efi_status_t ret = EFI_LOAD_ERROR;
+
+ if (entry)
+ ret = entry(image_handle, st);
+ st->boottime->exit(image_handle, ret, 0, NULL);
+ return ret;
+}
+
#ifdef CONFIG_ARM64
-static unsigned long efi_run_in_el2(ulong (*entry)(void *image_handle,
- struct efi_system_table *st), void *image_handle,
- struct efi_system_table *st)
+static unsigned long efi_run_in_el2(asmlinkage ulong (*entry)(
+ void *image_handle, struct efi_system_table *st),
+ void *image_handle, struct efi_system_table *st)
{
/* Enable caches again */
dcache_enable();
- return entry(image_handle, st);
+ return efi_do_enter(image_handle, st, entry);
}
#endif
ulong (*entry)(void *image_handle, struct efi_system_table *st)
asmlinkage;
ulong fdt_pages, fdt_size, fdt_start, fdt_end;
+ const efi_guid_t fdt_guid = EFI_FDT_GUID;
bootm_headers_t img = { 0 };
/*
}
/* Link to it in the efi tables */
- systab.tables[0].guid = EFI_FDT_GUID;
- systab.tables[0].table = fdt;
- systab.nr_tables = 1;
+ efi_install_configuration_table(&fdt_guid, fdt);
/* And reserve the space in the memory map */
fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
EFI_BOOT_SERVICES_DATA, true);
} else {
printf("WARNING: Invalid device tree, expect boot to fail\n");
- systab.nr_tables = 0;
+ efi_install_configuration_table(&fdt_guid, NULL);
}
/* Load the EFI payload */
return -ENOENT;
/* Initialize and populate EFI object list */
- INIT_LIST_HEAD(&efi_obj_list);
- list_add_tail(&loaded_image_info_obj.link, &efi_obj_list);
- list_add_tail(&bootefi_device_obj.link, &efi_obj_list);
-#ifdef CONFIG_PARTITIONS
- efi_disk_register();
-#endif
-#ifdef CONFIG_LCD
- efi_gop_register();
-#endif
-#ifdef CONFIG_NET
- void *nethandle = loaded_image_info.device_handle;
- efi_net_register(&nethandle);
-
- if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
- loaded_image_info.device_handle = nethandle;
- else
- loaded_image_info.device_handle = bootefi_device_path;
-#endif
-#ifdef CONFIG_GENERATE_SMBIOS_TABLE
- efi_smbios_register();
-#endif
-
- /* Initialize EFI runtime services */
- efi_reset_system_init();
- efi_get_time_init();
+ if (!efi_obj_list_initalized)
+ efi_init_obj_list();
/* Call our payload! */
debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
if (setjmp(&loaded_image_info.exit_jmp)) {
- efi_status_t status = loaded_image_info.exit_status;
- return status == EFI_SUCCESS ? 0 : -EINVAL;
+ return loaded_image_info.exit_status;
}
#ifdef CONFIG_ARM64
}
#endif
- return entry(&loaded_image_info, &systab);
+ return efi_do_enter(&loaded_image_info, &systab, entry);
}
{
char *saddr, *sfdt;
unsigned long addr, fdt_addr = 0;
- int r = 0;
+ unsigned long r;
if (argc < 2)
return CMD_RET_USAGE;
printf("## Starting EFI application at %08lx ...\n", addr);
r = do_bootefi_exec((void *)addr, (void*)fdt_addr);
- printf("## Application terminated, r = %d\n", r);
+ printf("## Application terminated, r = %lu\n",
+ r & ~EFI_ERROR_MASK);
- if (r != 0)
- r = 1;
-
- return r;
+ if (r != EFI_SUCCESS)
+ return 1;
+ else
+ return 0;
}
#ifdef CONFIG_SYS_LONGHELP
{
__maybe_unused struct blk_desc *desc;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
- char *colon;
+ char *colon, *s;
#if defined(CONFIG_BLK) || CONFIG_IS_ENABLED(ISO_PARTITION)
desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
} else {
snprintf(devname, sizeof(devname), "%s", path);
}
+ /* DOS style file path: */
+ s = devname;
+ while ((s = strchr(s, '/')))
+ *s++ = '\\';
ascii2unicode(bootefi_image_path[0].str, devname);
}
case 2:
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nReset SCSI\n");
+#ifndef CONFIG_DM_SCSI
scsi_bus_reset(NULL);
+#endif
ret = scsi_scan(true);
if (ret)
return CMD_RET_FAILURE;
static void usb_display_desc(struct usb_device *dev)
{
+ uint packet_size = dev->descriptor.bMaxPacketSize0;
+
if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
printf("%d: %s, USB Revision %x.%x\n", dev->devnum,
usb_get_class_desc(dev->config.if_desc[0].desc.bInterfaceClass),
usb_get_class_desc(
dev->config.if_desc[0].desc.bInterfaceClass));
}
+ if (dev->descriptor.bcdUSB >= cpu_to_le16(0x0300))
+ packet_size = 1 << packet_size;
printf(" - PacketSize: %d Configurations: %d\n",
- dev->descriptor.bMaxPacketSize0,
- dev->descriptor.bNumConfigurations);
+ packet_size, dev->descriptor.bNumConfigurations);
printf(" - Vendor: 0x%04x Product 0x%04x Version %d.%d\n",
dev->descriptor.idVendor, dev->descriptor.idProduct,
(dev->descriptor.bcdDevice>>8) & 0xff,
config ENV_IS_IN_FAT
bool "Environment is in a FAT filesystem"
depends on !CHAIN_OF_TRUST
+ select FAT_WRITE
help
Define this if you want to use the FAT file system for the environment.
- - FAT_ENV_INTERFACE:
-
- Define this to a string that is the name of the block device.
-
- - FAT_ENV_DEVICE_AND_PART:
-
- Define this to a string to specify the partition of the device. It can
- be as following:
-
- "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
- - "D:P": device D partition P. Error occurs if device D has no
- partition table.
- - "D:0": device D.
- - "D" or "D:": device D partition 1 if device D has partition
- table, or the whole device D if has no partition
- table.
- - "D:auto": first partition in device D with bootable flag set.
- If none, first valid partition in device D. If no
- partition table then means device D.
-
- - FAT_ENV_FILE:
-
- It's a string of the FAT file name. This file use to store the
- environment.
- CONFIG_FAT_WRITE:
This must be enabled. Otherwise it cannot save the environment file.
Define this if you don't want to or can't have an environment stored
on a storage medium
+config ENV_FAT_INTERFACE
+ string "Name of the block device for the environment"
+ depends on ENV_IS_IN_FAT
+ default "mmc" if TI_COMMON_CMD_OPTIONS || ARCH_ZYNQMP || ARCH_AT91
+ help
+ Define this to a string that is the name of the block device.
+
+config ENV_FAT_DEVICE_AND_PART
+ string "Device and partition for where to store the environemt in FAT"
+ depends on ENV_IS_IN_FAT
+ default "0:1" if TI_COMMON_CMD_OPTIONS
+ default "0:auto" if ARCH_ZYNQMP
+ default "0" if ARCH_AT91
+ help
+ Define this to a string to specify the partition of the device. It can
+ be as following:
+
+ "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+ - "D:P": device D partition P. Error occurs if device D has no
+ partition table.
+ - "D:0": device D.
+ - "D" or "D:": device D partition 1 if device D has partition
+ table, or the whole device D if has no partition
+ table.
+ - "D:auto": first partition in device D with bootable flag set.
+ If none, first valid partition in device D. If no
+ partition table then means device D.
+
+config ENV_FAT_FILE
+ string "Name of the FAT file to use for the environemnt"
+ depends on ENV_IS_IN_FAT
+ default "uboot.env"
+ help
+ It's a string of the FAT file name. This file use to store the
+ environment.
+
if ARCH_SUNXI
config ENV_OFFSET
config ARCH_EARLY_INIT_R
bool "Call arch-specific init soon after relocation"
- default y if X86
help
With this option U-Boot will call arch_early_init_r() soon after
relocation. Driver model is running by this point, and the cache
config BOARD_EARLY_INIT_F
bool "Call board-specific init before relocation"
- default y if X86
help
Some boards need to perform initialisation as soon as possible
after boot. With this option, U-Boot calls board_early_init_f()
endif
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
-ifdef CONFIG_SYS_MALLOC_F_LEN
+ifdef CONFIG_SYS_MALLOC_F
+ifneq ($(CONFIG_$(SPL_)SYS_MALLOC_F_LEN),0)
obj-y += malloc_simple.o
endif
+endif
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
static int initf_console_record(void)
{
-#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
return console_record_init();
#else
return 0;
static int initf_dm(void)
{
-#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
int ret;
bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
{
ulong malloc_start;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
#include <common.h>
#include <console.h>
#include <debug_uart.h>
+#include <dm.h>
#include <stdarg.h>
#include <iomux.h>
#include <malloc.h>
return error;
}
+/**
+ * console_dev_is_serial() - Check if a stdio device is a serial device
+ *
+ * @sdev: Device to check
+ * @return true if this device is in the serial uclass (or for pre-driver-model,
+ * whether it is called "serial".
+ */
+static bool console_dev_is_serial(struct stdio_dev *sdev)
+{
+ bool is_serial;
+
+#ifdef CONFIG_DM_SERIAL
+ if (sdev->flags & DEV_FLAGS_DM) {
+ struct udevice *dev = sdev->priv;
+
+ is_serial = device_get_uclass_id(dev) == UCLASS_SERIAL;
+ } else
+#endif
+ is_serial = !strcmp(sdev->name, "serial");
+
+ return is_serial;
+}
+
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
/** Console I/O multiplexing *******************************************/
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
- if (dev->puts != NULL && strcmp(dev->name, "serial") != 0)
+ if (dev->puts != NULL && !console_dev_is_serial(dev))
dev->puts(dev, s);
}
}
static inline void console_puts_noserial(int file, const char *s)
{
- if (strcmp(stdio_devices[file]->name, "serial") != 0)
+ if (!console_dev_is_serial(stdio_devices[file]))
stdio_devices[file]->puts(stdio_devices[file], s);
}
unmap_sysmem(buffer);
}
-static void pre_console_puts(const char *s)
-{
- while (*s)
- pre_console_putc(*s++);
-}
-
static void print_pre_console_buffer(int flushpoint)
{
unsigned long in = 0, out = 0;
}
#else
static inline void pre_console_putc(const char c) {}
-static inline void pre_console_puts(const char *s) {}
static inline void print_pre_console_buffer(int flushpoint) {}
#endif
void puts(const char *s)
{
-#ifdef CONFIG_DEBUG_UART
- if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
- while (*s) {
- int ch = *s++;
-
- printch(ch);
- }
- return;
- }
-#endif
-#ifdef CONFIG_CONSOLE_RECORD
- if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start)
- membuff_put(&gd->console_out, s, strlen(s));
-#endif
-#ifdef CONFIG_SILENT_CONSOLE
- if (gd->flags & GD_FLG_SILENT)
- return;
-#endif
-
-#ifdef CONFIG_DISABLE_CONSOLE
- if (gd->flags & GD_FLG_DISABLE_CONSOLE)
- return;
-#endif
-
- if (!gd->have_console)
- return pre_console_puts(s);
-
- if (gd->flags & GD_FLG_DEVINIT) {
- /* Send to the standard output */
- fputs(stdout, s);
- } else {
- /* Send directly to the handler */
- pre_console_puts(s);
- serial_puts(s);
- }
+ while (*s)
+ putc(*s++);
}
#ifdef CONFIG_CONSOLE_RECORD
INTERNAL_SIZE_T nb;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return malloc_simple(bytes);
#endif
mchunkptr fwd; /* misc temp for linking */
int islr; /* track whether merging with last_remainder */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* free() is a no-op - all the memory will be freed on relocation */
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return;
/* realloc of null is supposed to be same as malloc */
if (oldmem == NULL) return mALLOc(bytes);
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
/* This is harder to support and should not be needed */
panic("pre-reloc realloc() is not supported");
return NULL;
else
{
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
MALLOC_ZERO(mem, sz);
return mem;
int initf_malloc(void)
{
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
assert(gd->malloc_base); /* Set up by crt0.S */
- gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
gd->malloc_ptr = 0;
#endif
if (err)
return err;
- part = blk_get_device_part_str(FAT_ENV_INTERFACE,
- FAT_ENV_DEVICE_AND_PART,
+ part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
+ CONFIG_ENV_FAT_DEVICE_AND_PART,
&dev_desc, &info, 1);
if (part < 0)
return 1;
dev = dev_desc->devnum;
if (fat_set_blk_dev(dev_desc, &info) != 0) {
printf("\n** Unable to use %s %d:%d for saveenv **\n",
- FAT_ENV_INTERFACE, dev, part);
+ CONFIG_ENV_FAT_INTERFACE, dev, part);
return 1;
}
- err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, 0, sizeof(env_t),
+ err = file_fat_write(CONFIG_ENV_FAT_FILE, (void *)&env_new, 0, sizeof(env_t),
&size);
if (err == -1) {
printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
- FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
+ CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part);
return 1;
}
int dev, part;
int err;
- part = blk_get_device_part_str(FAT_ENV_INTERFACE,
- FAT_ENV_DEVICE_AND_PART,
+ part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
+ CONFIG_ENV_FAT_DEVICE_AND_PART,
&dev_desc, &info, 1);
if (part < 0)
goto err_env_relocate;
dev = dev_desc->devnum;
if (fat_set_blk_dev(dev_desc, &info) != 0) {
printf("\n** Unable to use %s %d:%d for loading the env **\n",
- FAT_ENV_INTERFACE, dev, part);
+ CONFIG_ENV_FAT_INTERFACE, dev, part);
goto err_env_relocate;
}
- err = file_fat_read(FAT_ENV_FILE, buf, CONFIG_ENV_SIZE);
+ err = file_fat_read(CONFIG_ENV_FAT_FILE, buf, CONFIG_ENV_SIZE);
if (err == -1) {
printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
- FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
+ CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part);
goto err_env_relocate;
}
u64 fdt_get_base_address(const void *fdt, int node)
{
int size;
- u32 naddr;
const fdt32_t *prop;
- naddr = fdt_address_cells(fdt, node);
+ prop = fdt_getprop(fdt, node, "reg", &size);
- prop = fdt_getprop(fdt, node, "ranges", &size);
-
- return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0;
+ return prop ? fdt_translate_address(fdt, node, prop) : 0;
}
/*
ulong board_init_f_alloc_reserve(ulong top)
{
/* Reserve early malloc arena */
-#if defined(CONFIG_SYS_MALLOC_F)
- top -= CONFIG_SYS_MALLOC_F_LEN;
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ top -= CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
/* LAST : reserve GD (rounded up to a multiple of 16 bytes) */
top = rounddown(top-sizeof(struct global_data), 16);
* Use gd as it is now properly set for all architectures.
*/
-#if defined(CONFIG_SYS_MALLOC_F)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
/* next alloc will be higher by one 'early malloc arena' size */
- base += CONFIG_SYS_MALLOC_F_LEN;
+ base += CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
}
debug("spl_early_init()\n");
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (setup_malloc) {
#ifdef CONFIG_MALLOC_F_ADDR
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
- gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
gd->malloc_ptr = 0;
}
#endif
default:
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
-#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
gd_t *new_gd;
ulong ptr = CONFIG_SPL_STACK_R_ADDR;
-#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
+#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_SPL_SYS_MALLOC_F_LEN
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
{
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev;
#endif
int err, mmc_dev;
return err;
}
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
err = uclass_get_device(UCLASS_MMC, mmc_dev, &dev);
if (!err)
*mmcp = mmc_get_mmc_dev(dev);
struct list_head list;
};
-/* TODO(sjg@chromium.org): Remove this when CONFIG_DM_USB is defined */
-static struct usb_hub_device hub_dev[USB_MAX_HUB];
-static int usb_hub_index;
static LIST_HEAD(usb_scan_list);
__weak void usb_hub_reset_devices(int port)
return;
}
+static inline bool usb_hub_is_superspeed(struct usb_device *hdev)
+{
+ return hdev->descriptor.bDeviceProtocol == 3;
+}
+
+#ifdef CONFIG_DM_USB
+bool usb_hub_is_root_hub(struct udevice *hub)
+{
+ if (device_get_uclass_id(hub->parent) != UCLASS_USB_HUB)
+ return true;
+
+ return false;
+}
+
+static int usb_set_hub_depth(struct usb_device *dev, int depth)
+{
+ if (depth < 0 || depth > 4)
+ return -EINVAL;
+
+ return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+ USB_REQ_SET_HUB_DEPTH, USB_DIR_OUT | USB_RT_HUB,
+ depth, 0, NULL, 0, USB_CNTL_TIMEOUT);
+}
+#endif
+
static int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size)
{
+ unsigned short dtype = USB_DT_HUB;
+
+ if (usb_hub_is_superspeed(dev))
+ dtype = USB_DT_SS_HUB;
+
return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB,
- USB_DT_HUB << 8, 0, data, size, USB_CNTL_TIMEOUT);
+ dtype << 8, 0, data, size, USB_CNTL_TIMEOUT);
}
static int usb_clear_port_feature(struct usb_device *dev, int port, int feature)
int usb_get_port_status(struct usb_device *dev, int port, void *data)
{
- return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+ int ret;
+
+ ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port,
- data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT);
+ data, sizeof(struct usb_port_status), USB_CNTL_TIMEOUT);
+
+#ifdef CONFIG_DM_USB
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Translate the USB 3.0 hub port status field into the old version
+ * that U-Boot understands. Do this only when the hub is not root hub.
+ * For root hub, the port status field has already been translated
+ * in the host controller driver (see xhci_submit_root() in xhci.c).
+ *
+ * Note: this only supports driver model.
+ */
+
+ if (!usb_hub_is_root_hub(dev->dev) && usb_hub_is_superspeed(dev)) {
+ struct usb_port_status *status = (struct usb_port_status *)data;
+ u16 tmp = (status->wPortStatus) & USB_SS_PORT_STAT_MASK;
+
+ if (status->wPortStatus & USB_SS_PORT_STAT_POWER)
+ tmp |= USB_PORT_STAT_POWER;
+ if ((status->wPortStatus & USB_SS_PORT_STAT_SPEED) ==
+ USB_SS_PORT_STAT_SPEED_5GBPS)
+ tmp |= USB_PORT_STAT_SUPER_SPEED;
+
+ status->wPortStatus = tmp;
+ }
+#endif
+
+ return ret;
}
max(100, (int)pgood_delay) + 1000);
}
+#ifndef CONFIG_DM_USB
+static struct usb_hub_device hub_dev[USB_MAX_HUB];
+static int usb_hub_index;
+
void usb_hub_reset(void)
{
usb_hub_index = 0;
printf("ERROR: USB_MAX_HUB (%d) reached\n", USB_MAX_HUB);
return NULL;
}
+#endif
#define MAX_TRIES 5
return speed_str;
}
-int legacy_hub_port_reset(struct usb_device *dev, int port,
- unsigned short *portstat)
+/**
+ * usb_hub_port_reset() - reset a port given its usb_device pointer
+ *
+ * Reset a hub port and see if a device is present on that port, providing
+ * sufficient time for it to show itself. The port status is returned.
+ *
+ * @dev: USB device to reset
+ * @port: Port number to reset (note ports are numbered from 0 here)
+ * @portstat: Returns port status
+ */
+static int usb_hub_port_reset(struct usb_device *dev, int port,
+ unsigned short *portstat)
{
int err, tries;
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
return 0;
}
-#ifdef CONFIG_DM_USB
-int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat)
-{
- struct usb_device *udev = dev_get_parent_priv(dev);
-
- return legacy_hub_port_reset(udev, port, portstat);
-}
-#endif
-
int usb_hub_port_connect_change(struct usb_device *dev, int port)
{
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
}
/* Reset the port */
- ret = legacy_hub_port_reset(dev, port, &portstatus);
+ ret = usb_hub_port_reset(dev, port, &portstatus);
if (ret < 0) {
if (ret != -ENXIO)
printf("cannot reset port %i!?\n", port + 1);
portchange = le16_to_cpu(portsts->wPortChange);
debug("Port %d Status %X Change %X\n", i + 1, portstatus, portchange);
- /* No connection change happened, wait a bit more. */
- if (!(portchange & USB_PORT_STAT_C_CONNECTION)) {
+ /*
+ * No connection change happened, wait a bit more.
+ *
+ * For some situation, the hub reports no connection change but a
+ * device is connected to the port (eg: CCS bit is set but CSC is not
+ * in the PORTSC register of a root hub), ignore such case.
+ */
+ if (!(portchange & USB_PORT_STAT_C_CONNECTION) &&
+ !(portstatus & USB_PORT_STAT_CONNECTION)) {
if (get_timer(0) >= hub->connect_timeout) {
debug("devnum=%d port=%d: timeout\n",
dev->devnum, i + 1);
return 0;
}
- /* Test if the connection came up, and if not exit */
- if (!(portstatus & USB_PORT_STAT_CONNECTION))
- return 0;
-
/* A new USB device is ready at this point */
debug("devnum=%d port=%d: USB dev found\n", dev->devnum, i + 1);
return ret;
}
+static struct usb_hub_device *usb_get_hub_device(struct usb_device *dev)
+{
+ struct usb_hub_device *hub;
+
+#ifndef CONFIG_DM_USB
+ /* "allocate" Hub device */
+ hub = usb_hub_allocate();
+#else
+ hub = dev_get_uclass_priv(dev->dev);
+#endif
+
+ return hub;
+}
+
static int usb_hub_configure(struct usb_device *dev)
{
int i, length;
__maybe_unused struct usb_hub_status *hubsts;
int ret;
- /* "allocate" Hub device */
- hub = usb_hub_allocate();
+ hub = usb_get_hub_device(dev);
if (hub == NULL)
return -ENOMEM;
hub->pusb_dev = dev;
+
/* Get the the hub descriptor */
ret = usb_get_hub_descriptor(dev, buffer, 4);
if (ret < 0) {
&descriptor->wHubCharacteristics)),
&hub->desc.wHubCharacteristics);
/* set the bitmap */
- bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0];
+ bitmap = (unsigned char *)&hub->desc.u.hs.DeviceRemovable[0];
/* devices not removable by default */
memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8);
- bitmap = (unsigned char *)&hub->desc.PortPowerCtrlMask[0];
+ bitmap = (unsigned char *)&hub->desc.u.hs.PortPowerCtrlMask[0];
memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */
for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
- hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i];
+ hub->desc.u.hs.DeviceRemovable[i] =
+ descriptor->u.hs.DeviceRemovable[i];
for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
- hub->desc.PortPowerCtrlMask[i] = descriptor->PortPowerCtrlMask[i];
+ hub->desc.u.hs.PortPowerCtrlMask[i] =
+ descriptor->u.hs.PortPowerCtrlMask[i];
dev->maxchild = descriptor->bNbrPorts;
debug("%d ports detected\n", dev->maxchild);
break;
}
+ switch (dev->descriptor.bDeviceProtocol) {
+ case USB_HUB_PR_FS:
+ break;
+ case USB_HUB_PR_HS_SINGLE_TT:
+ debug("Single TT\n");
+ break;
+ case USB_HUB_PR_HS_MULTI_TT:
+ ret = usb_set_interface(dev, 0, 1);
+ if (ret == 0) {
+ debug("TT per port\n");
+ hub->tt.multi = true;
+ } else {
+ debug("Using single TT (err %d)\n", ret);
+ }
+ break;
+ case USB_HUB_PR_SS:
+ /* USB 3.0 hubs don't have a TT */
+ break;
+ default:
+ debug("Unrecognized hub protocol %d\n",
+ dev->descriptor.bDeviceProtocol);
+ break;
+ }
+
+ /* Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns */
+ switch (hubCharacteristics & HUB_CHAR_TTTT) {
+ case HUB_TTTT_8_BITS:
+ if (dev->descriptor.bDeviceProtocol != 0) {
+ hub->tt.think_time = 666;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 8, hub->tt.think_time);
+ }
+ break;
+ case HUB_TTTT_16_BITS:
+ hub->tt.think_time = 666 * 2;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 16, hub->tt.think_time);
+ break;
+ case HUB_TTTT_24_BITS:
+ hub->tt.think_time = 666 * 3;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 24, hub->tt.think_time);
+ break;
+ case HUB_TTTT_32_BITS:
+ hub->tt.think_time = 666 * 4;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 32, hub->tt.think_time);
+ break;
+ }
+
debug("power on to power good time: %dms\n",
descriptor->bPwrOn2PwrGood * 2);
debug("hub controller current requirement: %dmA\n",
for (i = 0; i < dev->maxchild; i++)
debug("port %d is%s removable\n", i + 1,
- hub->desc.DeviceRemovable[(i + 1) / 8] & \
+ hub->desc.u.hs.DeviceRemovable[(i + 1) / 8] & \
(1 << ((i + 1) % 8)) ? " not" : "");
if (sizeof(struct usb_hub_status) > USB_BUFSIZ) {
debug("%sover-current condition exists\n",
(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \
"" : "no ");
+
+#ifdef CONFIG_DM_USB
+ /*
+ * Update USB host controller's internal representation of this hub
+ * after the hub descriptor is fetched.
+ */
+ ret = usb_update_hub_device(dev);
+ if (ret < 0 && ret != -ENOSYS) {
+ debug("%s: failed to update hub device for HCD (%x)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /*
+ * A maximum of seven tiers are allowed in a USB topology, and the
+ * root hub occupies the first tier. The last tier ends with a normal
+ * USB device. USB 3.0 hubs use a 20-bit field called 'route string'
+ * to route packets to the designated downstream port. The hub uses a
+ * hub depth value multiplied by four as an offset into the 'route
+ * string' to locate the bits it uses to determine the downstream
+ * port number.
+ */
+ if (usb_hub_is_root_hub(dev->dev)) {
+ hub->hub_depth = -1;
+ } else {
+ struct udevice *hdev;
+ int depth = 0;
+
+ hdev = dev->dev->parent;
+ while (!usb_hub_is_root_hub(hdev)) {
+ depth++;
+ hdev = hdev->parent;
+ }
+
+ hub->hub_depth = depth;
+
+ if (usb_hub_is_superspeed(dev)) {
+ debug("set hub (%p) depth to %d\n", dev, depth);
+ /*
+ * This request sets the value that the hub uses to
+ * determine the index into the 'route string index'
+ * for this hub.
+ */
+ ret = usb_set_hub_depth(dev, depth);
+ if (ret < 0) {
+ debug("%s: failed to set hub depth (%lX)\n",
+ __func__, dev->status);
+ return ret;
+ }
+ }
+ }
+#endif
+
usb_hub_power_on(hub);
/*
.child_pre_probe = usb_child_pre_probe,
.per_child_auto_alloc_size = sizeof(struct usb_device),
.per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata),
+ .per_device_auto_alloc_size = sizeof(struct usb_hub_device),
};
static const struct usb_device_id hub_id_table[] = {
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SCSI=y
+# CONFIG_SPL_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+# CONFIG_SPL_DM_MMC_OPS is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTDELAY=6
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTDELAY=6
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_SATA=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
+CONFIG_SCSI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_RTL8139=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_EEPROM is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
CONFIG_NOR=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x81000000
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_NOR=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NOR_BOOT=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_SPI_BOOT=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_DFU_MMC=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_YMODEM_SUPPORT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_FAT_WRITE=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
+CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_FPGA_ALTERA=y
CONFIG_MTD_NOR_FLASH=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_FPGA is not set
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_DEFAULT_DEVICE_TREE="axs101"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_DEFAULT_DEVICE_TREE="axs103"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
CONFIG_TARGET_BAYLEYBAY=y
CONFIG_INTERNAL_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
-CONFIG_ARCH_MISC_INIT=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
+CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK64=y
CONFIG_DEBUG_UART=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI_SUPPORT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_VIDEO_IVYBRIDGE_IGD=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_DEBUG_UART=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_VIDEO_IVYBRIDGE_IGD=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_TARGET_CHROMEBOOK_SAMUS=y
CONFIG_DEBUG_UART=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_INTEL_BROADWELL_GPIO=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_VIDEO_BROADWELL_IGD=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
CONFIG_TARGET_CHROMEBOX_PANTHER=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_BLK=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_RTL8169=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_TORTURE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
CONFIG_INTERNAL_UART=y
CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_EFI_PARTITION=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_IDE=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_COREBOOT=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
CONFIG_TARGET_COUGARCANYON2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_CONSOLE_MUX=y
+# CONFIG_ENABLE_MRC_CACHE is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+# CONFIG_VIDEO_VESA is not set
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_PCH_GBE=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_NAND is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
CONFIG_TARGET_DFI_BT700=y
CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="edison"
+CONFIG_TARGET_EDISON=y
+CONFIG_SMP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_ENV_CALLBACK=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_CPU=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Intel"
+CONFIG_G_DNL_VENDOR_NUM=0x8087
+CONFIG_G_DNL_PRODUCT_NUM=0x0a99
+CONFIG_FAT_WRITE=y
+CONFIG_SHA1=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_ENV_IS_NOWHERE=y
-CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
-CONFIG_DM_PCI=y
+# CONFIG_DM_ETH is not set
CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
CONFIG_EFI=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
CONFIG_DEBUG_UART=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SPL_DM_SERIAL is not set
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEYBOARD=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="flea3 U-Boot > "
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="galileo"
CONFIG_TARGET_GALILEO=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
-# CONFIG_MMC is not set
CONFIG_SCSI=y
+# CONFIG_MMC is not set
CONFIG_OF_LIBFDT=y
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
-CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_CLK_FREQ=1000000000
CONFIG_DEFAULT_DEVICE_TREE="hsdk"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="hsdk# "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_PROMPT="iconnect => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_DELAY_STR="ids"
CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
+CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DTB_RESELECT=y
CONFIG_FIT_EMBED=y
CONFIG_TARGET_K2G_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
-CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_DM_REGULATOR_FIXED=y
+# CONFIG_SPL_DM_SERIAL is not set
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_SATA=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_TARGET_MINNOWMAX=y
CONFIG_INTERNAL_UART=y
CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_RTL8169=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_FPGA_LOADMK=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_SPL=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_DEBUG_UART_BASE=0x70006000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
# CONFIG_CMD_USB is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
+CONFIG_SCSI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DIAG=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIVE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="PogoE02> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_MAX_CPUS=2
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_X86_RUN_64BIT=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_EFI=y
CONFIG_EFI_STUB=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_EFI=y
CONFIG_EFI_STUB=y
CONFIG_EFI_STUB_64BIT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_FAT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_FAT=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
-CONFIG_FAT_WRITE=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
CONFIG_SPL=y
+CONFIG_SPL_FPGA_SUPPORT=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_LED_STATUS=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_SOM_DB5800_SOM_6867=y
CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_PINCTRL_STM32=y
CONFIG_RAM=y
CONFIG_STM32_SDRAM=y
+CONFIG_STM32X7_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
CONFIG_TARGET_DFI_BT700=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTDELAY=6
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="woodburn U-Boot > "
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="woodburn U-Boot > "
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_FPGA_LOADMK=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
-CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
work with minimal adjustments on other x86 boards since coreboot deals with
most of the low-level details.
+U-Boot is a main bootloader on Intel Edison board.
+
U-Boot also supports booting directly from x86 reset vector, without coreboot.
In this case, known as bare mode, from the fact that it runs on the
'bare metal', U-Boot acts like a BIOS replacement. The following platforms
to point to a new board. You can also change the Cache-As-RAM (CAR) related
settings here if the default values do not fit your new board.
+Build Instructions for U-Boot as main bootloader
+------------------------------------------------
+
+Intel Edison instructions:
+
+Simple you can build U-Boot and obtain u-boot.bin
+
+$ make edison_defconfig
+$ make all
+
Build Instructions for U-Boot as BIOS replacement (bare mode)
-------------------------------------------------------------
Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
=> zboot 01000000 - 04000000 1b1ab50
+Updating U-Boot on Edison
+-------------------------
+By default Intel Edison boards are shipped with preinstalled heavily
+patched U-Boot v2014.04. Though it supports DFU which we may be able to
+use.
+
+1. Prepare u-boot.bin as described in chapter above. You still need one
+more step (if and only if you have original U-Boot), i.e. run the
+following command:
+
+$ truncate -s %4096 u-boot.bin
+
+2. Run your board and interrupt booting to U-Boot console. In the console
+call:
+
+ => run do_force_flash_os
+
+3. Wait for few seconds, it will prepare environment variable and runs
+DFU. Run DFU command from the host system:
+
+$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
+
+4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
+reset the board:
+
+ => reset
+
CPU Microcode
-------------
Modern CPUs usually require a special bit stream called microcode [8] to be
obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
endif
ifdef CONFIG_TPL_BUILD
See also CMD_SATA which provides command-line support.
-config SCSI
- bool "Support SCSI controllers"
- help
- This enables support for SCSI (Small Computer System Interface),
- a parallel interface widely used with storage peripherals such as
- hard drives and optical drives. The SCSI standards define physical
- interfaces as well as protocols for controlling devices and
- tranferring data.
-
-config DM_SCSI
- bool "Support SCSI controllers with driver model"
- depends on BLK
- help
- This option enables the SCSI (Small Computer System Interface) uclass
- which supports SCSI and SATA HDDs. For every device configuration
- (IDs/LUNs) a block device is created with RAW read/write and
- filesystem support.
-
menu "SATA/SCSI device support"
+config AHCI_PCI
+ bool "Support for PCI-based AHCI controller"
+ depends on DM_SCSI
+ help
+ Enables support for the PCI-based AHCI controller.
+
config SATA_CEVA
bool "Ceva Sata controller"
depends on AHCI
obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
obj-$(CONFIG_AHCI) += ahci-uclass.o
+obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <dm.h>
+#include <pci.h>
+
+static int ahci_pci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int ahci_pci_probe(struct udevice *dev)
+{
+ return ahci_probe_scsi(dev);
+}
+
+static const struct udevice_id ahci_pci_ids[] = {
+ { .compatible = "ahci-pci" },
+ { }
+};
+
+U_BOOT_DRIVER(ahci_pci) = {
+ .name = "ahci_pci",
+ .id = UCLASS_AHCI,
+ .of_match = ahci_pci_ids,
+ .bind = ahci_pci_bind,
+ .probe = ahci_pci_probe,
+};
+
+static struct pci_device_id ahci_pci_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(ahci_pci, ahci_pci_supported);
*/
#include <common.h>
+#include <ahci.h>
#include <dm.h>
UCLASS_DRIVER(ahci) = {
.id = UCLASS_AHCI,
.name = "ahci",
+ .per_device_auto_alloc_size = sizeof(struct ahci_uc_priv),
};
cap2 & (1 << 0) ? "boh " : "");
}
-#ifndef CONFIG_SCSI_AHCI_PLAT
+#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
# else
{
struct ahci_uc_priv *uc_priv;
#ifdef CONFIG_DM_SCSI
- uc_priv = dev_get_uclass_priv(dev);
+ uc_priv = dev_get_uclass_priv(dev->parent);
#else
uc_priv = probe_ent;
#endif
return 0;
}
-int ahci_probe_scsi(struct udevice *ahci_dev)
+int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- return -ENOSYS; /* TODO(sjg@chromium.org): Support non-PCI AHCI */
-#else
struct ahci_uc_priv *uc_priv;
struct scsi_platdata *uc_plat;
struct udevice *dev;
if (!dev)
return -ENODEV;
uc_plat = dev_get_uclass_platdata(dev);
- uc_plat->base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
- PCI_REGION_MEM);
+ uc_plat->base = base;
uc_plat->max_lun = 1;
uc_plat->max_id = 2;
- uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv = dev_get_uclass_priv(ahci_dev);
ret = ahci_init_one(uc_priv, dev);
if (ret)
return ret;
if (ret)
return ret;
- debug("Scanning %s\n", dev->name);
- ret = scsi_scan_dev(dev, true);
- if (ret)
- return ret;
-#endif
-
return 0;
}
+#ifdef CONFIG_DM_PCI
+int ahci_probe_scsi_pci(struct udevice *ahci_dev)
+{
+ ulong base;
+
+ base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
+ PCI_REGION_MEM);
+
+ return ahci_probe_scsi(ahci_dev, base);
+}
+#endif
+
struct scsi_ops scsi_ops = {
.exec = ahci_scsi_exec,
.bus_reset = ahci_scsi_bus_reset,
be partitioned into several areas, called 'partitions' in U-Boot.
A filesystem can be placed in each partition.
+config SPL_BLK
+ bool "Support block devices in SPL"
+ depends on SPL_DM && BLK
+ default y
+ help
+ Enable support for block devices, such as SCSI, MMC and USB
+ flash sticks. These provide a block-level interface which permits
+ reading, writing and (in some cases) erasing blocks. Block
+ devices often have a partition table which allows the device to
+ be partitioned into several areas, called 'partitions' in U-Boot.
+ A filesystem can be placed in each partition.
+
config BLOCK_CACHE
bool "Use block device cache"
default n
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_BLK) += blk-uclass.o
+obj-$(CONFIG_$(SPL_)BLK) += blk-uclass.o
-ifndef CONFIG_BLK
+ifndef CONFIG_$(SPL_)BLK
obj-y += blk_legacy.o
endif
device = dev_desc->devnum;
dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
+#ifndef CONFIG_BLK
dev_desc->block_read = atapi_read;
+#endif
memset(ccb, 0, sizeof(ccb));
memset(iobuf, 0, sizeof(iobuf));
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(clk);
+ clk->dev = NULL;
+
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
index, &args);
if (ret) {
int index;
debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
+ clk->dev = NULL;
index = dev_read_stringlist_search(dev, "clock-names", name);
if (index < 0) {
return clk_get_by_index(dev, index, clk);
}
+
+int clk_release_all(struct clk *clk, int count)
+{
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
+
+ /* check if clock has been previously requested */
+ if (!clk[i].dev)
+ continue;
+
+ ret = clk_disable(&clk[i]);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ ret = clk_free(&clk[i]);
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
#endif /* OF_CONTROL */
int clk_request(struct udevice *dev, struct clk *clk)
.name = "rockchip_rk3368_cru",
.id = UCLASS_CLK,
.of_match = rk3368_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3368_cru),
+ .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
.ops = &rk3368_clk_ops,
.bind = rk3368_clk_bind,
suitable malloc() implementation. If you are not using the
full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+ must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
and devices in SPL, so 1KB should be enable. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
+ CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
config TPL_DM
bool "Enable Driver Model for TPL"
suitable malloc() implementation. If you are not using the
full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+ must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
and devices in SPL, so 1KB should be enough. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
+ CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
Disable this for very small implementations.
config DM_WARN
index, out_args);
}
+int of_count_phandle_with_args(const struct device_node *np,
+ const char *list_name, const char *cells_name)
+{
+ return __of_parse_phandle_with_args(np, list_name, cells_name, 0,
+ -1, NULL);
+}
+
static void of_alias_add(struct alias_prop *ap, struct device_node *np,
int id, const char *stem, int stem_len)
{
#include <dm/of_addr.h>
#include <dm/ofnode.h>
#include <linux/err.h>
+#include <linux/ioport.h>
int ofnode_read_u32(ofnode node, const char *propname, u32 *outp)
{
const __be32 *prop_val;
uint flags;
u64 size;
+ int na;
- prop_val = of_get_address(
- (struct device_node *)ofnode_to_np(node), index,
- &size, &flags);
+ prop_val = of_get_address(ofnode_to_np(node), index, &size,
+ &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
- return be32_to_cpup(prop_val);
+ na = of_n_addr_cells(ofnode_to_np(node));
+ return of_read_number(prop_val, na);
} else {
return fdt_get_base_address(gd->fdt_blob,
ofnode_to_offset(node));
return 0;
}
+int ofnode_count_phandle_with_args(ofnode node, const char *list_name,
+ const char *cells_name)
+{
+ if (ofnode_is_np(node))
+ return of_count_phandle_with_args(ofnode_to_np(node),
+ list_name, cells_name);
+ else
+ return fdtdec_parse_phandle_with_args(gd->fdt_blob,
+ ofnode_to_offset(node), list_name, cells_name,
+ 0, -1, NULL);
+}
+
ofnode ofnode_path(const char *path)
{
if (of_live_active())
return false;
}
+
+int ofnode_read_resource(ofnode node, uint index, struct resource *res)
+{
+ if (ofnode_is_np(node)) {
+ return of_address_to_resource(ofnode_to_np(node), index, res);
+ } else {
+ struct fdt_resource fres;
+ int ret;
+
+ ret = fdt_get_resource(gd->fdt_blob, ofnode_to_offset(node),
+ "reg", index, &fres);
+ if (ret < 0)
+ return -EINVAL;
+ memset(res, '\0', sizeof(*res));
+ res->start = fres.start;
+ res->end = fres.end;
+
+ return 0;
+ }
+}
return fdt_get_phandle(gd->fdt_blob, ofnode_to_offset(node));
}
-const u32 *dev_read_prop(struct udevice *dev, const char *propname, int *lenp)
+const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp)
{
return ofnode_get_property(dev_ofnode(dev), propname, lenp);
}
return fdtdec_get_is_enabled(gd->fdt_blob,
ofnode_to_offset(node));
}
+
+int dev_read_resource(struct udevice *dev, uint index, struct resource *res)
+{
+ return ofnode_read_resource(dev_ofnode(dev), index, res);
+}
#include <dm/read.h>
#include <linux/ioport.h>
-int dev_read_resource(struct udevice *dev, uint index, struct resource *res)
-{
- ofnode node = dev_ofnode(dev);
-
-#ifdef CONFIG_OF_LIVE
- if (ofnode_is_np(node)) {
- return of_address_to_resource(ofnode_to_np(node), index, res);
- } else
-#endif
- {
- struct fdt_resource fres;
- int ret;
-
- ret = fdt_get_resource(gd->fdt_blob, ofnode_to_offset(node),
- "reg", index, &fres);
- if (ret < 0)
- return -EINVAL;
- memset(res, '\0', sizeof(*res));
- res->start = fres.start;
- res->end = fres.end;
-
- return 0;
- }
-}
+/* This file can hold non-inlined dev_read_...() functions */
return ret;
}
-void dfu_write_transaction_cleanup(struct dfu_entity *dfu)
+void dfu_transaction_cleanup(struct dfu_entity *dfu)
{
/* clear everything */
dfu->crc = 0;
dfu->offset = 0;
dfu->i_blk_seq_num = 0;
- dfu->i_buf_start = dfu_buf;
- dfu->i_buf_end = dfu_buf;
+ dfu->i_buf_start = dfu_get_buf(dfu);
+ dfu->i_buf_end = dfu->i_buf_start;
dfu->i_buf = dfu->i_buf_start;
+ dfu->r_left = 0;
+ dfu->b_left = 0;
+ dfu->bad_skip = 0;
+
dfu->inited = 0;
}
+int dfu_transaction_initiate(struct dfu_entity *dfu, bool read)
+{
+ int ret = 0;
+
+ if (dfu->inited)
+ return 0;
+
+ dfu_transaction_cleanup(dfu);
+
+ if (dfu->i_buf_start == NULL)
+ return -ENOMEM;
+
+ dfu->i_buf_end = dfu->i_buf_start + dfu_get_buf_size();
+
+ if (read) {
+ ret = dfu->get_medium_size(dfu, &dfu->r_left);
+ if (ret < 0)
+ return ret;
+ debug("%s: %s %lld [B]\n", __func__, dfu->name, dfu->r_left);
+ }
+
+ dfu->inited = 1;
+
+ return 0;
+}
+
int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
{
int ret = 0;
printf("\nDFU complete %s: 0x%08x\n", dfu_hash_algo->name,
dfu->crc);
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return ret;
}
__func__, dfu->name, buf, size, blk_seq_num, dfu->offset,
(unsigned long)(dfu->i_buf - dfu->i_buf_start));
- if (!dfu->inited) {
- /* initial state */
- dfu->crc = 0;
- dfu->offset = 0;
- dfu->bad_skip = 0;
- dfu->i_blk_seq_num = 0;
- dfu->i_buf_start = dfu_get_buf(dfu);
- if (dfu->i_buf_start == NULL)
- return -ENOMEM;
- dfu->i_buf_end = dfu_get_buf(dfu) + dfu_buf_size;
- dfu->i_buf = dfu->i_buf_start;
-
- dfu->inited = 1;
- }
+ ret = dfu_transaction_initiate(dfu, false);
+ if (ret < 0)
+ return ret;
if (dfu->i_blk_seq_num != blk_seq_num) {
printf("%s: Wrong sequence number! [%d] [%d]\n",
__func__, dfu->i_blk_seq_num, blk_seq_num);
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return -1;
}
if ((dfu->i_buf + size) > dfu->i_buf_end) {
ret = dfu_write_buffer_drain(dfu);
if (ret) {
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return ret;
}
}
if ((dfu->i_buf + size) > dfu->i_buf_end) {
error("Buffer overflow! (0x%p + 0x%x > 0x%p)\n", dfu->i_buf,
size, dfu->i_buf_end);
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return -1;
}
if (size == 0 || (dfu->i_buf + size) > dfu->i_buf_end) {
ret = dfu_write_buffer_drain(dfu);
if (ret) {
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return ret;
}
}
debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n",
__func__, dfu->name, buf, size, blk_seq_num, dfu->i_buf);
- if (!dfu->inited) {
- dfu->i_buf_start = dfu_get_buf(dfu);
- if (dfu->i_buf_start == NULL)
- return -ENOMEM;
-
- dfu->r_left = dfu->get_medium_size(dfu);
- if (dfu->r_left < 0)
- return dfu->r_left;
-
- debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left);
-
- dfu->i_blk_seq_num = 0;
- dfu->crc = 0;
- dfu->offset = 0;
- dfu->i_buf_end = dfu_get_buf(dfu) + dfu_buf_size;
- dfu->i_buf = dfu->i_buf_start;
- dfu->b_left = 0;
-
- dfu->bad_skip = 0;
-
- dfu->inited = 1;
- }
+ ret = dfu_transaction_initiate(dfu, true);
+ if (ret < 0)
+ return ret;
if (dfu->i_blk_seq_num != blk_seq_num) {
printf("%s: Wrong sequence number! [%d] [%d]\n",
dfu_hash_algo->name, dfu->crc);
puts("\nUPLOAD ... done\nCtrl+C to exit ...\n");
- dfu->i_blk_seq_num = 0;
- dfu->crc = 0;
- dfu->offset = 0;
- dfu->i_buf_start = dfu_buf;
- dfu->i_buf_end = dfu_buf;
- dfu->i_buf = dfu->i_buf_start;
- dfu->b_left = 0;
-
- dfu->bad_skip = 0;
-
- dfu->inited = 0;
+ dfu_transaction_cleanup(dfu);
}
return ret;
#include <mmc.h>
static unsigned char *dfu_file_buf;
-static long dfu_file_buf_len;
+static u64 dfu_file_buf_len;
static long dfu_file_buf_filled;
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
}
static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu,
- void *buf, long *len)
+ void *buf, u64 *len)
{
const char *fsname, *opname;
char cmd_buf[DFU_CMD_BUF_SIZE];
sprintf(cmd_buf + strlen(cmd_buf), " %s", dfu->name);
if (op == DFU_OP_WRITE)
- sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len);
+ sprintf(cmd_buf + strlen(cmd_buf), " %llx", *len);
debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
return ret;
}
-long dfu_get_medium_size_mmc(struct dfu_entity *dfu)
+int dfu_get_medium_size_mmc(struct dfu_entity *dfu, u64 *size)
{
int ret;
- long len;
switch (dfu->layout) {
case DFU_RAW_ADDR:
- return dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size;
+ *size = dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size;
+ return 0;
case DFU_FS_FAT:
case DFU_FS_EXT4:
dfu_file_buf_filled = -1;
- ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, &len);
+ ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, size);
if (ret < 0)
return ret;
- if (len > CONFIG_SYS_DFU_MAX_FILE_SIZE)
+ if (*size > CONFIG_SYS_DFU_MAX_FILE_SIZE)
return -1;
- return len;
+ return 0;
default:
printf("%s: Layout (%s) not (yet) supported!\n", __func__,
dfu_get_layout(dfu->layout));
long *len)
{
int ret;
- long file_len;
+ u64 file_len;
if (dfu_file_buf_filled == -1) {
ret = mmc_file_op(DFU_OP_READ, dfu, dfu_file_buf, &file_len);
return ret;
}
-long dfu_get_medium_size_nand(struct dfu_entity *dfu)
+int dfu_get_medium_size_nand(struct dfu_entity *dfu, u64 *size)
{
- return dfu->data.nand.size;
+ *size = dfu->data.nand.size;
+
+ return 0;
}
static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf,
return dfu_transfer_medium_ram(DFU_OP_WRITE, dfu, offset, buf, len);
}
-long dfu_get_medium_size_ram(struct dfu_entity *dfu)
+int dfu_get_medium_size_ram(struct dfu_entity *dfu, u64 *size)
{
- return dfu->data.ram.size;
+ *size = dfu->data.ram.size;
+
+ return 0;
}
static int dfu_read_medium_ram(struct dfu_entity *dfu, u64 offset,
#include <spi.h>
#include <spi_flash.h>
-static long dfu_get_medium_size_sf(struct dfu_entity *dfu)
+static int dfu_get_medium_size_sf(struct dfu_entity *dfu, u64 *size)
{
- return dfu->data.sf.size;
+ *size = dfu->data.sf.size;
+
+ return 0;
}
static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf,
Enable Altera FPGA specific functions which includes bitstream
(in BIT format), fpga and device validation.
+config FPGA_SOCFPGA
+ bool "Enable Gen5 and Arria10 common FPGA drivers"
+ select FPGA_ALTERA
+ help
+ Say Y here to enable the Gen5 and Arria10 common FPGA driver
+
+ This provides common functionality for Gen5 and Arria10 devices.
+
config FPGA_CYCLON2
bool "Enable Altera FPGA driver for Cyclone II"
depends on FPGA_ALTERA
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
endif
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Set CD ratio */
-static void fpgamgr_set_cd_ratio(unsigned long ratio)
-{
- clrsetbits_le32(&fpgamgr_regs->ctrl,
- 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
- (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
-}
-
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
+int fpgamgr_dclkcnt_set(unsigned long cnt)
{
unsigned long i;
return -ETIMEDOUT;
}
-/* Start the FPGA programming by initialize the FPGA Manager */
-static int fpgamgr_program_init(void)
-{
- unsigned long msel, i;
-
- /* Get the MSEL value */
- msel = readl(&fpgamgr_regs->stat);
- msel &= FPGAMGRREGS_STAT_MSEL_MASK;
- msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
-
- /*
- * Set the cfg width
- * If MSEL[3] = 1, cfg width = 32 bit
- */
- if (msel & 0x8) {
- setbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- /* MSEL[1:0] = 2, CD Ratio = 8 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x8);
-
- } else { /* MSEL[3] = 0 */
- clrbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 2 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x2);
- /* MSEL[1:0] = 2, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- }
-
- /* To enable FPGA Manager configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
-
- /* To enable FPGA Manager drive over configuration line */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- /* Put FPGA into reset phase */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (1) wait until FPGA enter reset phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
- break;
- }
-
- /* If not in reset state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
- puts("FPGA: Could not reset\n");
- return -1;
- }
-
- /* Release FPGA from reset phase */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (2) wait until FPGA enter configuration phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
- puts("FPGA: Could not configure\n");
- return -2;
- }
-
- /* Clear all interrupts in CB Monitor */
- writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
-
- /* Enable AXI configuration */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
/* Write the RBF data to FPGA Manager */
-static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
{
uint32_t src = (uint32_t)rbf_data;
uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
-/* Ensure the FPGA entering config done */
-static int fpgamgr_program_poll_cd(void)
-{
- const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
- FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
- unsigned long reg, i;
-
- /* (3) wait until full config done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- reg = readl(&fpgamgr_regs->gpio_ext_porta);
-
- /* Config error */
- if (!(reg & mask)) {
- printf("FPGA: Configuration error.\n");
- return -3;
- }
-
- /* Config done without error */
- if (reg & mask)
- break;
- }
-
- /* Timeout happened, return error */
- if (i == FPGA_TIMEOUT_CNT) {
- printf("FPGA: Timeout waiting for program.\n");
- return -4;
- }
-
- /* Disable AXI configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Ensure the FPGA entering init phase */
-static int fpgamgr_program_poll_initphase(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to enter initialization phase */
- if (fpgamgr_dclkcnt_set(0x4))
- return -5;
-
- /* (4) wait until FPGA enter init phase or user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
- break;
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -6;
-
- return 0;
-}
-
-/* Ensure the FPGA entering user mode */
-static int fpgamgr_program_poll_usermode(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to exit initialization phase */
- if (fpgamgr_dclkcnt_set(0x5000))
- return -7;
-
- /* (5) wait until FPGA enter user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -8;
-
- /* To release FPGA Manager drive over configuration line */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- return 0;
-}
-
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
-int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
-{
- unsigned long status;
-
- if ((uint32_t)rbf_data & 0x3) {
- puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
- return -EINVAL;
- }
-
- /* Prior programming the FPGA, all bridges need to be shut off */
-
- /* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
-
- /* Disable all signals from FPGA to HPS SDRAM */
-#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
- writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
-
- /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
- socfpga_bridges_reset(1);
-
- /* Unmap the bridges from NIC-301 */
- writel(0x1, SOCFPGA_L3REGS_ADDRESS);
-
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init();
- if (status)
- return status;
-
- /* Write the RBF data to FPGA Manager */
- fpgamgr_program_write(rbf_data, rbf_size);
-
- /* Ensure the FPGA entering config done */
- status = fpgamgr_program_poll_cd();
- if (status)
- return status;
-
- /* Ensure the FPGA entering init phase */
- status = fpgamgr_program_poll_initphase();
- if (status)
- return status;
-
- /* Ensure the FPGA entering user mode */
- return fpgamgr_program_poll_usermode();
-}
--- /dev/null
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32 1
+#define MIN_BITSTREAM_SIZECHECK 230
+#define ENCRYPTION_OFFSET 69
+#define COMPRESSION_OFFSET 229
+#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+ (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+ u32 reg;
+
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+ return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+ if (width)
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+ else
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+}
+
+int is_fpgamgr_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
+}
+
+static int wait_for_user_mode(void)
+{
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+ u32 sync_data = 0xffffffff;
+ u32 i = 0;
+ unsigned start = get_timer(0);
+ unsigned long cd_ratio;
+
+ /* Getting existing CDRATIO */
+ cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+ /* Using CDRATIO_X1 for better compatibility */
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+ while (!is_fpgamgr_early_user_mode()) {
+ if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+ return -ETIMEDOUT;
+ fpgamgr_program_write((const long unsigned int *)&sync_data,
+ sizeof(sync_data));
+ udelay(FPGA_TIMEOUT_MSEC);
+ i++;
+ }
+
+ debug("Additional %i sync word needed\n", i);
+
+ /* restoring original CDRATIO */
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+ unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
+
+ /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
+ * timeout at 1000ms
+ */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ mask,
+ false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+ /* Poll until f2s to specific value, timeout at 1000ms */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+ value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+
+/* get the MSEL value, verify we are set for FPP configuration mode */
+static int fpgamgr_verify_msel(void)
+{
+ u32 msel = fpgamgr_get_msel();
+
+ if (msel & ~BIT(0)) {
+ printf("Fail: read msel=%d\n", msel);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
+ size_t rbf_size)
+{
+ unsigned int cd_ratio;
+ bool encrypt, compress;
+
+ /*
+ * According to the bitstream specification,
+ * both encryption and compression status are
+ * in location before offset 230 of the buffer.
+ */
+ if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+ return -EINVAL;
+
+ encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+ encrypt = encrypt != 0;
+
+ compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+ compress = !compress;
+
+ debug("header word %d = %08x\n", 69, rbf_data[69]);
+ debug("header word %d = %08x\n", 229, rbf_data[229]);
+ debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+
+ /*
+ * from the register map description of cdratio in imgcfg_ctrl_02:
+ * Normal Configuration : 32bit Passive Parallel
+ * Partial Reconfiguration : 16bit Passive Parallel
+ */
+
+ /*
+ * cd ratio is dependent on cfg width and whether the bitstream
+ * is encrypted and/or compressed.
+ *
+ * | width | encr. | compr. | cd ratio |
+ * | 16 | 0 | 0 | 1 |
+ * | 16 | 0 | 1 | 4 |
+ * | 16 | 1 | 0 | 2 |
+ * | 16 | 1 | 1 | 4 |
+ * | 32 | 0 | 0 | 1 |
+ * | 32 | 0 | 1 | 8 |
+ * | 32 | 1 | 0 | 4 |
+ * | 32 | 1 | 1 | 8 |
+ */
+ if (!compress && !encrypt) {
+ cd_ratio = CDRATIO_x1;
+ } else {
+ if (compress)
+ cd_ratio = CDRATIO_x4;
+ else
+ cd_ratio = CDRATIO_x2;
+
+ /* if 32 bit, double the cd ratio (so register
+ field setting is incremented) */
+ if (cfg_width == CFGWDTH_32)
+ cd_ratio += 1;
+ }
+
+ fpgamgr_set_cfgwdth(cfg_width);
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+static int fpgamgr_reset(void)
+{
+ unsigned long reg;
+
+ /* S2F_NCONFIG = 0 */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 0 */
+ if (wait_for_f2s_nstatus_pin(0))
+ return -ETIME;
+
+ /* S2F_NCONFIG = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 1 */
+ if (wait_for_f2s_nstatus_pin(1))
+ return -ETIME;
+
+ /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
+ return -EPERM;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
+ return -EPERM;
+
+ return 0;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ /* Step 1 */
+ if (fpgamgr_verify_msel())
+ return -EPERM;
+
+ /* Step 2 */
+ if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
+ return -EPERM;
+
+ /*
+ * Step 3:
+ * Make sure no other external devices are trying to interfere with
+ * programming:
+ */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /*
+ * Step 4:
+ * Deassert the signal drives from HPS
+ *
+ * S2F_NCE = 1
+ * S2F_PR_REQUEST = 0
+ * EN_CFG_CTRL = 0
+ * EN_CFG_DATA = 0
+ * S2F_NCONFIG = 1
+ * S2F_NSTATUS_OE = 0
+ * S2F_CONDONE_OE = 0
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
+
+ /*
+ * Step 5:
+ * Enable overrides
+ * S2F_NENABLE_CONFIG = 0
+ * S2F_NENABLE_NCONFIG = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /*
+ * Disable driving signals that HPS doesn't need to drive.
+ * S2F_NENABLE_NSTATUS = 1
+ * S2F_NENABLE_CONDONE = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
+
+ /*
+ * Step 6:
+ * Drive chip select S2F_NCE = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /* Step 7 */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /* Step 8 */
+ ret = fpgamgr_reset();
+
+ if (ret)
+ return ret;
+
+ /*
+ * Step 9:
+ * EN_CFG_CTRL and EN_CFG_DATA = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ unsigned long reg, i;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
+ return 0;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
+ printf("nstatus == 0 while waiting for condone\n");
+ return -EPERM;
+ }
+ }
+
+ if (i == FPGA_TIMEOUT_CNT)
+ return -ETIME;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long reg;
+ int ret = 0;
+
+ if (fpgamgr_dclkcnt_set(0xf))
+ return -ETIME;
+
+ ret = wait_for_user_mode();
+ if (ret < 0) {
+ printf("%s: Failed to enter user mode with ", __func__);
+ printf("error code %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Step 14:
+ * Stop DATA path and Dclk
+ * EN_CFG_CTRL and EN_CFG_DATA = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ /*
+ * Step 15:
+ * Disable overrides
+ * S2F_NENABLE_CONFIG = 1
+ * S2F_NENABLE_NCONFIG = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /* Disable chip select S2F_NCE = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /*
+ * Step 16:
+ * Final check
+ */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
+ return -EPERM;
+
+ return 0;
+}
+
+int fpgamgr_program_finish(void)
+{
+ /* Ensure the FPGA entering config done */
+ int status = fpgamgr_program_poll_cd();
+
+ if (status) {
+ printf("FPGA: Poll CD failed with error code %d\n", status);
+ return -EPERM;
+ }
+ WATCHDOG_RESET();
+
+ /* Ensure the FPGA entering user mode */
+ status = fpgamgr_program_poll_usermode();
+ if (status) {
+ printf("FPGA: Poll usermode failed with error code %d\n",
+ status);
+ return -EPERM;
+ }
+
+ printf("Full Configuration Succeeded.\n");
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ /* disable all signals from hps peripheral controller to fpga */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ return fpgamgr_program_finish();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrsetbits_le32(&fpgamgr_regs->ctrl,
+ 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
+ (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+static int fpgamgr_program_init(void)
+{
+ unsigned long msel, i;
+
+ /* Get the MSEL value */
+ msel = readl(&fpgamgr_regs->stat);
+ msel &= FPGAMGRREGS_STAT_MSEL_MASK;
+ msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
+
+ /*
+ * Set the cfg width
+ * If MSEL[3] = 1, cfg width = 32 bit
+ */
+ if (msel & 0x8) {
+ setbits_le32(&fpgamgr_regs->ctrl,
+ FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+ /* To determine the CD ratio */
+ /* MSEL[1:0] = 0, CD Ratio = 1 */
+ if ((msel & 0x3) == 0x0)
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+ /* MSEL[1:0] = 1, CD Ratio = 4 */
+ else if ((msel & 0x3) == 0x1)
+ fpgamgr_set_cd_ratio(CDRATIO_x4);
+ /* MSEL[1:0] = 2, CD Ratio = 8 */
+ else if ((msel & 0x3) == 0x2)
+ fpgamgr_set_cd_ratio(CDRATIO_x8);
+
+ } else { /* MSEL[3] = 0 */
+ clrbits_le32(&fpgamgr_regs->ctrl,
+ FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+ /* To determine the CD ratio */
+ /* MSEL[1:0] = 0, CD Ratio = 1 */
+ if ((msel & 0x3) == 0x0)
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+ /* MSEL[1:0] = 1, CD Ratio = 2 */
+ else if ((msel & 0x3) == 0x1)
+ fpgamgr_set_cd_ratio(CDRATIO_x2);
+ /* MSEL[1:0] = 2, CD Ratio = 4 */
+ else if ((msel & 0x3) == 0x2)
+ fpgamgr_set_cd_ratio(CDRATIO_x4);
+ }
+
+ /* To enable FPGA Manager configuration */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
+
+ /* To enable FPGA Manager drive over configuration line */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+ /* Put FPGA into reset phase */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+ /* (1) wait until FPGA enter reset phase */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
+ break;
+ }
+
+ /* If not in reset state, return error */
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
+ puts("FPGA: Could not reset\n");
+ return -1;
+ }
+
+ /* Release FPGA from reset phase */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+ /* (2) wait until FPGA enter configuration phase */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
+ break;
+ }
+
+ /* If not in configuration state, return error */
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
+ puts("FPGA: Could not configure\n");
+ return -2;
+ }
+
+ /* Clear all interrupts in CB Monitor */
+ writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
+
+ /* Enable AXI configuration */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
+ FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
+ unsigned long reg, i;
+
+ /* (3) wait until full config done */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpgamgr_regs->gpio_ext_porta);
+
+ /* Config error */
+ if (!(reg & mask)) {
+ printf("FPGA: Configuration error.\n");
+ return -3;
+ }
+
+ /* Config done without error */
+ if (reg & mask)
+ break;
+ }
+
+ /* Timeout happened, return error */
+ if (i == FPGA_TIMEOUT_CNT) {
+ printf("FPGA: Timeout waiting for program.\n");
+ return -4;
+ }
+
+ /* Disable AXI configuration */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering init phase */
+static int fpgamgr_program_poll_initphase(void)
+{
+ unsigned long i;
+
+ /* Additional clocks for the CB to enter initialization phase */
+ if (fpgamgr_dclkcnt_set(0x4))
+ return -5;
+
+ /* (4) wait until FPGA enter init phase or user mode */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
+ break;
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ }
+
+ /* If not in configuration state, return error */
+ if (i == FPGA_TIMEOUT_CNT)
+ return -6;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long i;
+
+ /* Additional clocks for the CB to exit initialization phase */
+ if (fpgamgr_dclkcnt_set(0x5000))
+ return -7;
+
+ /* (5) wait until FPGA enter user mode */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ }
+ /* If not in configuration state, return error */
+ if (i == FPGA_TIMEOUT_CNT)
+ return -8;
+
+ /* To release FPGA Manager drive over configuration line */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ if ((uint32_t)rbf_data & 0x3) {
+ puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
+ return -EINVAL;
+ }
+
+ /* Prior programming the FPGA, all bridges need to be shut off */
+
+ /* Disable all signals from hps peripheral controller to fpga */
+ writel(0, &sysmgr_regs->fpgaintfgrp_module);
+
+ /* Disable all signals from FPGA to HPS SDRAM */
+#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
+ writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
+
+ /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset(1);
+
+ /* Unmap the bridges from NIC-301 */
+ writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init();
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_poll_cd();
+ if (status)
+ return status;
+
+ /* Ensure the FPGA entering init phase */
+ status = fpgamgr_program_poll_initphase();
+ if (status)
+ return status;
+
+ /* Ensure the FPGA entering user mode */
+ return fpgamgr_program_poll_usermode();
+}
driver from the common Intel ICH6 driver. It supports a total of
95 GPIOs which can be configured from the device tree.
+config INTEL_ICH6_GPIO
+ bool "Intel ICH6 compatible legacy GPIO driver"
+ depends on DM_GPIO
+ help
+ Say yes here to select Intel ICH6 compatible legacy GPIO driver.
+
config IMX_RGPIO2P
bool "i.MX7ULP RGPIO2P driver"
depends on DM
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
*/
- if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
- &len))
- return -EINVAL;
+ len = dev_read_size(parent, "interrupts");
+ if (len < 0)
+ return len;
bank_count = len / 3 / sizeof(u32);
- ctlr = (struct gpio_ctlr *)devfdt_get_addr(parent);
+ ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
+ if ((ulong)ctlr == FDT_ADDR_T_NONE)
+ return -EINVAL;
}
#endif
for (bank = 0; bank < bank_count; bank++) {
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
#include <clk.h>
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
- i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
+ i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+ if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot get regs address\n", __func__);
+ return -EINVAL;
+ }
ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
if (ret) {
{
struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
- plat->base = (void *)devfdt_get_addr(dev);
+ plat->base = (void *)dev_read_addr(dev);
return 0;
}
option will be removed as soon as all DM_MMC drivers use it, as it
will the only supported behaviour.
+config SPL_DM_MMC
+ bool "Enable MMC controllers using Driver Model in SPL"
+ depends on SPL_DM && DM_MMC
+ default y
+ help
+ This enables the MultiMediaCard (MMC) uclass which supports MMC and
+ Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
+ and non-removable (e.g. eMMC chip) devices are supported. These
+ appear as block devices in U-Boot and can support filesystems such
+ as EXT4 and FAT.
+
+config SPL_DM_MMC_OPS
+ bool "Support MMC controller operations using Driver Model in SPL"
+ depends on SPL_DM && DM_MMC_OPS
+ default y
+ help
+ Driver model provides a means of supporting device operations. This
+ option moves MMC operations under the control of driver model. The
+ option will be removed as soon as all DM_MMC drivers use it, as it
+ will the only supported behaviour.
+
if MMC
config SPL_MMC_TINY
#
obj-y += mmc.o
-obj-$(CONFIG_DM_MMC) += mmc-uclass.o
+obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o
-ifndef CONFIG_BLK
+ifndef CONFIG_$(SPL_)BLK
obj-y += mmc_legacy.o
endif
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_DM_MMC_OPS
+#if CONFIG_IS_ENABLED(DM_MMC_OPS)
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
return upriv->mmc;
}
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct mmc *find_mmc_device(int dev_num)
{
struct udevice *dev, *mmc_dev;
struct udevice *bdev;
int ret, devnum = -1;
-#ifdef CONFIG_DM_MMC_OPS
+#if CONFIG_IS_ENABLED(DM_MMC_OPS)
if (!mmc_get_ops(dev))
return -ENOSYS;
#endif
}
#endif
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
__weak int board_mmc_getwp(struct mmc *mmc)
{
return -1;
}
#endif
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
int ret;
return blkcnt;
}
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
#else
ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
void *dst)
#endif
{
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
int dev_num = block_dev->devnum;
return 0;
}
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
int mmc_getcd(struct mmc *mmc)
{
int cd;
80,
};
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
static void mmc_set_ios(struct mmc *mmc)
{
if (mmc->cfg->ops->set_ios)
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
/* board-specific MMC power initializations. */
__weak void board_mmc_power_init(void)
{
static int mmc_power_init(struct mmc *mmc)
{
-#if defined(CONFIG_DM_MMC)
+#if CONFIG_IS_ENABLED(DM_MMC)
#if defined(CONFIG_DM_REGULATOR) && !defined(CONFIG_SPL_BUILD)
struct udevice *vmmc_supply;
int ret;
/* we pretend there's no card when init is NULL */
no_card = mmc_getcd(mmc) == 0;
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
no_card = no_card || (mmc->cfg->ops->init == NULL);
#endif
if (no_card) {
if (err)
return err;
-#ifdef CONFIG_DM_MMC_OPS
+#if CONFIG_IS_ENABLED(DM_MMC_OPS)
/* The device has already been probed ready for use */
#else
/* made sure it's not NULL earlier */
{
int err = 0;
__maybe_unused unsigned start;
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
upriv->mmc = mmc;
mmc->preinit = preinit;
}
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
static int mmc_probe(bd_t *bis)
{
return 0;
}
-#elif defined(CONFIG_DM_MMC)
+#elif CONFIG_IS_ENABLED(DM_MMC)
static int mmc_probe(bd_t *bis)
{
int ret, i;
return 0;
initialized = 1;
-#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(BLK)
#if !CONFIG_IS_ENABLED(MMC_TINY)
mmc_list_init();
#endif
cfg->f_max == 0 || cfg->b_max == 0)
return NULL;
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
if (cfg->ops == NULL || cfg->ops->send_cmd == NULL)
return NULL;
#endif
void mmc_adapter_card_type_ident(void);
#endif
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
void *dst);
#else
#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV))
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
const void *src);
ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
/* declare dummies to reduce code size. */
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
static inline unsigned long mmc_berase(struct udevice *dev,
lbaint_t start, lbaint_t blkcnt)
{
struct omap_hsmmc_data {
struct hsmmc *base_addr;
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
struct mmc_config cfg;
#endif
#ifdef OMAP_HSMMC_USE_GPIO
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
bool cd_inverted;
static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
{
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
return dev_get_priv(mmc->dev);
#else
return (struct omap_hsmmc_data *)mmc->priv;
}
static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
{
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
return &plat->cfg;
#else
#endif
}
- #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
+#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
static int omap_mmc_setup_gpio_in(int gpio, const char *label)
{
int ret;
}
}
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_set_ios(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
}
#ifdef OMAP_HSMMC_USE_GPIO
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_getcd(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
#endif
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
static const struct dm_mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
};
#endif
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <mapmem.h>
#include <sdhci.h>
#include <asm/pci.h>
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
+struct pci_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct pci_mmc_priv {
+ struct sdhci_host host;
+ void *base;
+};
+
+static int pci_mmc_probe(struct udevice *dev)
{
- struct sdhci_host *mmc_host;
- u32 iobase;
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct pci_mmc_plat *plat = dev_get_platdata(dev);
+ struct pci_mmc_priv *priv = dev_get_priv(dev);
+ struct sdhci_host *host = &priv->host;
+ u32 ioaddr;
int ret;
- int i;
-
- for (i = 0; ; i++) {
- struct udevice *dev;
-
- ret = pci_find_device_id(mmc_supported, i, &dev);
- if (ret)
- return ret;
- mmc_host = malloc(sizeof(struct sdhci_host));
- if (!mmc_host)
- return -ENOMEM;
-
- mmc_host->name = name;
- dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
- mmc_host->ioaddr = (void *)(ulong)iobase;
- mmc_host->quirks = 0;
- mmc_host->max_clk = 0;
- ret = add_sdhci(mmc_host, 0, 0);
- if (ret)
- return ret;
- }
-
- return 0;
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &ioaddr);
+ host->ioaddr = map_sysmem(ioaddr, 0);
+ host->name = dev->name;
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+ if (ret)
+ return ret;
+ host->mmc = &plat->mmc;
+ host->mmc->priv = &priv->host;
+ host->mmc->dev = dev;
+ upriv->mmc = host->mmc;
+
+ return sdhci_probe(dev);
}
+
+static int pci_mmc_bind(struct udevice *dev)
+{
+ struct pci_mmc_plat *plat = dev_get_platdata(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+U_BOOT_DRIVER(pci_mmc) = {
+ .name = "pci_mmc",
+ .id = UCLASS_MMC,
+ .bind = pci_mmc_bind,
+ .probe = pci_mmc_probe,
+ .ops = &sdhci_ops,
+ .priv_auto_alloc_size = sizeof(struct pci_mmc_priv),
+ .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat),
+};
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported);
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/arch/mmc.h>
#include <asm-generic/gpio.h>
-struct sunxi_mmc_host {
+struct sunxi_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct sunxi_mmc_priv {
unsigned mmc_no;
uint32_t *mclkreg;
unsigned fatal_err;
+ struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct sunxi_mmc *reg;
struct mmc_config cfg;
};
+#if !CONFIG_IS_ENABLED(DM_MMC)
/* support 4 mmc hosts */
-struct sunxi_mmc_host mmc_host[4];
+struct sunxi_mmc_priv mmc_host[4];
static int sunxi_mmc_getcd_gpio(int sdc_no)
{
static int mmc_resource_init(int sdc_no)
{
- struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
+ struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int cd_pin, ret = 0;
switch (sdc_no) {
case 0:
- mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
- mmchost->mclkreg = &ccm->sd0_clk_cfg;
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
+ priv->mclkreg = &ccm->sd0_clk_cfg;
break;
case 1:
- mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
- mmchost->mclkreg = &ccm->sd1_clk_cfg;
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
+ priv->mclkreg = &ccm->sd1_clk_cfg;
break;
case 2:
- mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
- mmchost->mclkreg = &ccm->sd2_clk_cfg;
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
+ priv->mclkreg = &ccm->sd2_clk_cfg;
break;
case 3:
- mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
- mmchost->mclkreg = &ccm->sd3_clk_cfg;
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
+ priv->mclkreg = &ccm->sd3_clk_cfg;
break;
default:
printf("Wrong mmc number %d\n", sdc_no);
return -1;
}
- mmchost->mmc_no = sdc_no;
+ priv->mmc_no = sdc_no;
cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
if (cd_pin >= 0) {
return ret;
}
+#endif
-static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
+static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
{
unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
}
if (n > 3) {
- printf("mmc %u error cannot set clock to %u\n",
- mmchost->mmc_no, hz);
+ printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
+ hz);
return -1;
}
writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
- CCM_MMC_CTRL_M(div), mmchost->mclkreg);
+ CCM_MMC_CTRL_M(div), priv->mclkreg);
debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
- mmchost->mmc_no, hz, pll_hz, 1u << n, div,
- pll_hz / (1u << n) / div);
+ priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
return 0;
}
-static int mmc_clk_io_on(int sdc_no)
+static int mmc_update_clk(struct sunxi_mmc_priv *priv)
{
- struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- debug("init mmc %d clock and io\n", sdc_no);
-
- /* config ahb clock */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
-
-#ifdef CONFIG_SUNXI_GEN_SUN6I
- /* unassert reset */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
-#endif
-#if defined(CONFIG_MACH_SUN9I)
- /* sun9i has a mmc-common module, also set the gate and reset there */
- writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
- SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
-#endif
-
- return mmc_set_mod_clk(mmchost, 24000000);
-}
-
-static int mmc_update_clk(struct mmc *mmc)
-{
- struct sunxi_mmc_host *mmchost = mmc->priv;
unsigned int cmd;
unsigned timeout_msecs = 2000;
cmd = SUNXI_MMC_CMD_START |
SUNXI_MMC_CMD_UPCLK_ONLY |
SUNXI_MMC_CMD_WAIT_PRE_OVER;
- writel(cmd, &mmchost->reg->cmd);
- while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
+ writel(cmd, &priv->reg->cmd);
+ while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
if (!timeout_msecs--)
return -1;
udelay(1000);
}
/* clock update sets various irq status bits, clear these */
- writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
+ writel(readl(&priv->reg->rint), &priv->reg->rint);
return 0;
}
-static int mmc_config_clock(struct mmc *mmc)
+static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
- unsigned rval = readl(&mmchost->reg->clkcr);
+ unsigned rval = readl(&priv->reg->clkcr);
/* Disable Clock */
rval &= ~SUNXI_MMC_CLK_ENABLE;
- writel(rval, &mmchost->reg->clkcr);
- if (mmc_update_clk(mmc))
+ writel(rval, &priv->reg->clkcr);
+ if (mmc_update_clk(priv))
return -1;
/* Set mod_clk to new rate */
- if (mmc_set_mod_clk(mmchost, mmc->clock))
+ if (mmc_set_mod_clk(priv, mmc->clock))
return -1;
/* Clear internal divider */
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
- writel(rval, &mmchost->reg->clkcr);
+ writel(rval, &priv->reg->clkcr);
/* Re-enable Clock */
rval |= SUNXI_MMC_CLK_ENABLE;
- writel(rval, &mmchost->reg->clkcr);
- if (mmc_update_clk(mmc))
+ writel(rval, &priv->reg->clkcr);
+ if (mmc_update_clk(priv))
return -1;
return 0;
}
-static int sunxi_mmc_set_ios(struct mmc *mmc)
+static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
+ struct mmc *mmc)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
-
debug("set ios: bus_width: %x, clock: %d\n",
mmc->bus_width, mmc->clock);
/* Change clock first */
- if (mmc->clock && mmc_config_clock(mmc) != 0) {
- mmchost->fatal_err = 1;
+ if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
+ priv->fatal_err = 1;
return -EINVAL;
}
/* Change bus width */
if (mmc->bus_width == 8)
- writel(0x2, &mmchost->reg->width);
+ writel(0x2, &priv->reg->width);
else if (mmc->bus_width == 4)
- writel(0x1, &mmchost->reg->width);
+ writel(0x1, &priv->reg->width);
else
- writel(0x0, &mmchost->reg->width);
+ writel(0x0, &priv->reg->width);
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int sunxi_mmc_core_init(struct mmc *mmc)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
+ struct sunxi_mmc_priv *priv = mmc->priv;
/* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
+ writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
udelay(1000);
return 0;
}
+#endif
-static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
+static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
+ struct mmc_data *data)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
const int reading = !!(data->flags & MMC_DATA_READ);
const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
SUNXI_MMC_STATUS_FIFO_FULL;
timeout_usecs = 2000000;
/* Always read / write data through the CPU */
- setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
+ setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
for (i = 0; i < (byte_cnt >> 2); i++) {
- while (readl(&mmchost->reg->status) & status_bit) {
+ while (readl(&priv->reg->status) & status_bit) {
if (!timeout_usecs--)
return -1;
udelay(1);
}
if (reading)
- buff[i] = readl(&mmchost->reg->fifo);
+ buff[i] = readl(&priv->reg->fifo);
else
- writel(buff[i], &mmchost->reg->fifo);
+ writel(buff[i], &priv->reg->fifo);
}
return 0;
}
-static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
- unsigned int done_bit, const char *what)
+static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
+ uint timeout_msecs, uint done_bit, const char *what)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
unsigned int status;
do {
- status = readl(&mmchost->reg->rint);
+ status = readl(&priv->reg->rint);
if (!timeout_msecs-- ||
(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
debug("%s timeout %x\n", what,
return 0;
}
-static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
+ struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
unsigned int cmdval = SUNXI_MMC_CMD_START;
unsigned int timeout_msecs;
int error = 0;
unsigned int status = 0;
unsigned int bytecnt = 0;
- if (mmchost->fatal_err)
+ if (priv->fatal_err)
return -1;
if (cmd->resp_type & MMC_RSP_BUSY)
debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
cmdval |= SUNXI_MMC_CMD_WRITE;
if (data->blocks > 1)
cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
- writel(data->blocksize, &mmchost->reg->blksz);
- writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
+ writel(data->blocksize, &priv->reg->blksz);
+ writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
}
- debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
+ debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
- writel(cmd->cmdarg, &mmchost->reg->arg);
+ writel(cmd->cmdarg, &priv->reg->arg);
if (!data)
- writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+ writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
/*
* transfer data and check status
bytecnt = data->blocksize * data->blocks;
debug("trans data %d bytes\n", bytecnt);
- writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
- ret = mmc_trans_data_by_cpu(mmc, data);
+ writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
+ ret = mmc_trans_data_by_cpu(priv, mmc, data);
if (ret) {
- error = readl(&mmchost->reg->rint) & \
+ error = readl(&priv->reg->rint) &
SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
error = -ETIMEDOUT;
goto out;
}
}
- error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
+ error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
+ "cmd");
if (error)
goto out;
if (data) {
timeout_msecs = 120;
debug("cacl timeout %x msec\n", timeout_msecs);
- error = mmc_rint_wait(mmc, timeout_msecs,
+ error = mmc_rint_wait(priv, mmc, timeout_msecs,
data->blocks > 1 ?
SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
SUNXI_MMC_RINT_DATA_OVER,
if (cmd->resp_type & MMC_RSP_BUSY) {
timeout_msecs = 2000;
do {
- status = readl(&mmchost->reg->status);
+ status = readl(&priv->reg->status);
if (!timeout_msecs--) {
debug("busy timeout\n");
error = -ETIMEDOUT;
}
if (cmd->resp_type & MMC_RSP_136) {
- cmd->response[0] = readl(&mmchost->reg->resp3);
- cmd->response[1] = readl(&mmchost->reg->resp2);
- cmd->response[2] = readl(&mmchost->reg->resp1);
- cmd->response[3] = readl(&mmchost->reg->resp0);
+ cmd->response[0] = readl(&priv->reg->resp3);
+ cmd->response[1] = readl(&priv->reg->resp2);
+ cmd->response[2] = readl(&priv->reg->resp1);
+ cmd->response[3] = readl(&priv->reg->resp0);
debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
cmd->response[3], cmd->response[2],
cmd->response[1], cmd->response[0]);
} else {
- cmd->response[0] = readl(&mmchost->reg->resp0);
+ cmd->response[0] = readl(&priv->reg->resp0);
debug("mmc resp 0x%08x\n", cmd->response[0]);
}
out:
if (error < 0) {
- writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
- mmc_update_clk(mmc);
+ writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
+ mmc_update_clk(priv);
}
- writel(0xffffffff, &mmchost->reg->rint);
- writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
- &mmchost->reg->gctrl);
+ writel(0xffffffff, &priv->reg->rint);
+ writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
+ &priv->reg->gctrl);
return error;
}
-static int sunxi_mmc_getcd(struct mmc *mmc)
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
{
- struct sunxi_mmc_host *mmchost = mmc->priv;
+ struct sunxi_mmc_priv *priv = mmc->priv;
+
+ return sunxi_mmc_set_ios_common(priv, mmc);
+}
+
+static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sunxi_mmc_priv *priv = mmc->priv;
+
+ return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
+{
+ struct sunxi_mmc_priv *priv = mmc->priv;
int cd_pin;
- cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
+ cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
if (cd_pin < 0)
return 1;
}
static const struct mmc_ops sunxi_mmc_ops = {
- .send_cmd = sunxi_mmc_send_cmd,
- .set_ios = sunxi_mmc_set_ios,
+ .send_cmd = sunxi_mmc_send_cmd_legacy,
+ .set_ios = sunxi_mmc_set_ios_legacy,
.init = sunxi_mmc_core_init,
- .getcd = sunxi_mmc_getcd,
+ .getcd = sunxi_mmc_getcd_legacy,
};
struct mmc *sunxi_mmc_init(int sdc_no)
{
- struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+ struct mmc_config *cfg = &priv->cfg;
+ int ret;
- memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
+ memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
cfg->name = "SUNXI SD/MMC";
cfg->ops = &sunxi_mmc_ops;
if (mmc_resource_init(sdc_no) != 0)
return NULL;
- mmc_clk_io_on(sdc_no);
+ /* config ahb clock */
+ debug("init mmc %d clock and io\n", sdc_no);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
- return mmc_create(cfg, &mmc_host[sdc_no]);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ /* unassert reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+#if defined(CONFIG_MACH_SUN9I)
+ /* sun9i has a mmc-common module, also set the gate and reset there */
+ writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
+ SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
+ ret = mmc_set_mod_clk(priv, 24000000);
+ if (ret)
+ return NULL;
+
+ return mmc_create(cfg, mmc_host);
+}
+#else
+
+static int sunxi_mmc_set_ios(struct udevice *dev)
+{
+ struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_priv *priv = dev_get_priv(dev);
+
+ return sunxi_mmc_set_ios_common(priv, &plat->mmc);
}
+
+static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_priv *priv = dev_get_priv(dev);
+
+ return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int sunxi_mmc_getcd(struct udevice *dev)
+{
+ struct sunxi_mmc_priv *priv = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
+
+ return 1;
+}
+
+static const struct dm_mmc_ops sunxi_mmc_ops = {
+ .send_cmd = sunxi_mmc_send_cmd,
+ .set_ios = sunxi_mmc_set_ios,
+ .get_cd = sunxi_mmc_getcd,
+};
+
+static int sunxi_mmc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_priv *priv = dev_get_priv(dev);
+ struct mmc_config *cfg = &plat->cfg;
+ struct ofnode_phandle_args args;
+ u32 *gate_reg;
+ int bus_width, ret;
+
+ cfg->name = dev->name;
+ bus_width = dev_read_u32_default(dev, "bus-width", 1);
+
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->host_caps = 0;
+ if (bus_width == 8)
+ cfg->host_caps |= MMC_MODE_8BIT;
+ if (bus_width >= 4)
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+ cfg->f_min = 400000;
+ cfg->f_max = 52000000;
+
+ priv->reg = (void *)dev_read_addr(dev);
+
+ /* We don't have a sunxi clock driver so find the clock address here */
+ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+ 1, &args);
+ if (ret)
+ return ret;
+ priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
+
+ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+ 0, &args);
+ if (ret)
+ return ret;
+ gate_reg = (u32 *)ofnode_get_addr(args.node);
+ setbits_le32(gate_reg, 1 << args.args[0]);
+ priv->mmc_no = args.args[0] - 8;
+
+ ret = mmc_set_mod_clk(priv, 24000000);
+ if (ret)
+ return ret;
+
+ /* This GPIO is optional */
+ if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN)) {
+ int cd_pin = gpio_get_number(&priv->cd_gpio);
+
+ sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
+ }
+
+ upriv->mmc = &plat->mmc;
+
+ /* Reset controller */
+ writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
+ udelay(1000);
+
+ return 0;
+}
+
+static int sunxi_mmc_bind(struct udevice *dev)
+{
+ struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id sunxi_mmc_ids[] = {
+ { .compatible = "allwinner,sun5i-a13-mmc" },
+ { }
+};
+
+U_BOOT_DRIVER(sunxi_mmc_drv) = {
+ .name = "sunxi_mmc",
+ .id = UCLASS_MMC,
+ .of_match = sunxi_mmc_ids,
+ .bind = sunxi_mmc_bind,
+ .probe = sunxi_mmc_probe,
+ .ops = &sunxi_mmc_ops,
+ .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
+ .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
+};
+#endif
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <mmc.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch-tegra/tegra_mmc.h>
-#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
cfg->name = dev->name;
- bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 1);
+ bus_width = dev_read_u32_default(dev, "bus-width", 1);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = 0;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- priv->reg = (void *)devfdt_get_addr(dev);
+ priv->reg = (void *)dev_read_addr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {
return ret;
/* These GPIOs are optional */
- gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
- GPIOD_IS_IN);
- gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
- GPIOD_IS_IN);
- gpio_request_by_name(dev, "power-gpios", 0,
- &priv->pwr_gpio, GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
+ GPIOD_IS_OUT);
if (dm_gpio_is_valid(&priv->pwr_gpio))
dm_gpio_set_value(&priv->pwr_gpio, 1);
config NAND_DENALI
bool "Support Denali NAND controller"
select SYS_NAND_SELF_INIT
+ imply CMD_NAND
help
Enable support for the Denali NAND controller.
config NAND_VF610_NFC
bool "Support for Freescale NFC for VF610"
select SYS_NAND_SELF_INIT
+ imply CMD_NAND
help
Enables support for NAND Flash Controller on some Freescale
processors like the VF610, MCF54418 or Kinetis K70.
config NAND_PXA3XX
bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
select SYS_NAND_SELF_INIT
+ imply CMD_NAND
help
This enables the driver for the NAND flash device found on
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
select SYS_NAND_SELF_INIT
select SYS_NAND_U_BOOT_LOCATIONS
+ imply CMD_NAND
---help---
Enable support for NAND. This option enables the standard and
SPL drivers.
config NAND_ARASAN
bool "Configure Arasan Nand"
+ imply CMD_NAND
help
This enables Nand driver support for Arasan nand flash
controller. This uses the hardware ECC for read and
config NAND_MXS
bool "MXS NAND support"
depends on MX6 || MX7
+ imply CMD_NAND
help
This enables NAND driver for the NAND flash controller on the
MXS processors.
config NAND_ZYNQ
bool "Support for Zynq Nand controller"
select SYS_NAND_SELF_INIT
+ imply CMD_NAND
help
This enables Nand driver support for Nand flash controller
found on Zynq SoC.
menuconfig PCI
bool "PCI support"
- default y if PPC || X86
+ default y if PPC
help
Enable support for PCI (Peripheral Interconnect Bus), a type of bus
used on some devices to allow the CPU to communicate with its
#include <clk.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <malloc.h>
#include <pci.h>
#include <power-domain.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <linux/ioport.h>
#include <linux/list.h>
#ifndef CONFIG_TEGRA186
struct tegra_pcie {
struct pci_controller hose;
- struct fdt_resource pads;
- struct fdt_resource afi;
- struct fdt_resource cs;
+ struct resource pads;
+ struct resource afi;
+ struct resource cs;
struct list_head ports;
unsigned long xbar;
return 0;
}
-static int tegra_pcie_port_parse_dt(const void *fdt, int node,
- struct tegra_pcie_port *port)
+static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
{
const u32 *addr;
int len;
- addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
+ addr = ofnode_get_property(node, "assigned-addresses", &len);
if (!addr) {
error("property \"assigned-addresses\" not found");
return -FDT_ERR_NOTFOUND;
return 0;
}
-static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
+static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
enum tegra_pci_id id, unsigned long *xbar)
{
switch (id) {
return -FDT_ERR_NOTFOUND;
}
-static int tegra_pcie_parse_port_info(const void *fdt, int node,
- unsigned int *index,
- unsigned int *lanes)
+static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
{
struct fdt_pci_addr addr;
int err;
- err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
+ err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
if (err < 0) {
error("failed to parse \"nvidia,num-lanes\" property");
return err;
*lanes = err;
- err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
+ err = ofnode_read_pci_addr(node, 0, "reg", &addr);
if (err < 0) {
error("failed to parse \"reg\" property");
return err;
return 0;
}
-static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
+static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
struct tegra_pcie *pcie)
{
- int err, subnode;
+ ofnode subnode;
u32 lanes = 0;
+ int err;
- err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
- &pcie->pads);
+ err = dev_read_resource(dev, 0, &pcie->pads);
if (err < 0) {
error("resource \"pads\" not found");
return err;
}
- err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
- &pcie->afi);
+ err = dev_read_resource(dev, 1, &pcie->afi);
if (err < 0) {
error("resource \"afi\" not found");
return err;
}
- err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
- &pcie->cs);
+ err = dev_read_resource(dev, 2, &pcie->cs);
if (err < 0) {
error("resource \"cs\" not found");
return err;
}
#endif
- fdt_for_each_subnode(subnode, fdt, node) {
+ dev_for_each_subnode(subnode, dev) {
unsigned int index = 0, num_lanes = 0;
struct tegra_pcie_port *port;
- err = tegra_pcie_parse_port_info(fdt, subnode, &index,
- &num_lanes);
+ err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
if (err < 0) {
error("failed to obtain root port info");
continue;
lanes |= num_lanes << (index << 3);
- if (!fdtdec_get_is_enabled(fdt, subnode))
+ if (!ofnode_is_available(subnode))
continue;
port = malloc(sizeof(*port));
port->num_lanes = num_lanes;
port->index = index;
- err = tegra_pcie_port_parse_dt(fdt, subnode, port);
+ err = tegra_pcie_port_parse_dt(subnode, port);
if (err < 0) {
free(port);
continue;
port->pcie = pcie;
}
- err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
+ err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
+ &pcie->xbar);
if (err < 0) {
error("invalid lane configuration");
return err;
/* BAR 0: type 1 extended configuration space */
fpci = 0xfe100000;
- size = fdt_resource_size(&pcie->cs);
+ size = resource_size(&pcie->cs);
axi = pcie->cs.start;
afi_writel(pcie, axi, AFI_AXI_BAR0_START);
INIT_LIST_HEAD(&pcie->ports);
- if (tegra_pcie_parse_dt(gd->fdt_blob, dev_of_offset(dev), id, pcie))
+ if (tegra_pcie_parse_dt(dev, id, pcie))
return -EINVAL;
return 0;
This select a dummy sandbox PHY driver. It used only to implement
the unit tests for the phy framework
+config NOP_PHY
+ bool "NOP PHY driver"
+ depends on PHY
+ help
+ Support for a no-op PHY driver (stubbed PHY driver).
+
+ This is useful when a driver uses the PHY framework but no real PHY
+ hardware exists.
+
+config SPL_NOP_PHY
+ bool "NOP PHY driver in SPL"
+ depends on SPL_PHY
+ help
+ Support for a no-op PHY driver (stubbed PHY driver) in the SPL.
+
+ This is useful when a driver uses the PHY framework but no real PHY
+ hardware exists.
+
config PIPE3_PHY
bool "Support omap's PIPE3 PHY"
depends on PHY && ARCH_OMAP2PLUS
#
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
+obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <generic-phy.h>
+
+static const struct udevice_id nop_phy_ids[] = {
+ { .compatible = "nop-phy" },
+ { }
+};
+
+static struct phy_ops nop_phy_ops = {
+};
+
+U_BOOT_DRIVER(nop_phy) = {
+ .name = "nop_phy",
+ .id = UCLASS_PHY,
+ .of_match = nop_phy_ids,
+ .ops = &nop_phy_ops,
+};
debug("%s(dev=%p, index=%d, phy=%p)\n", __func__, dev, index, phy);
assert(phy);
+ phy->dev = NULL;
ret = dev_read_phandle_with_args(dev, "phys", "#phy-cells", 0, index,
&args);
if (ret) {
framework.
config SPL_PINCTRL
- bool "Support pin controlloers in SPL"
+ bool "Support pin controllers in SPL"
depends on SPL && SPL_DM
help
This option is an SPL-variant of the PINCTRL option.
(GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
(GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
+ rk_clrsetreg(&grf->gpio4bl_iomux,
+ GPIO4B1_MASK << GPIO4B1_SHIFT,
+ GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT);
+
/* switch GPIO4B1 to 12ma drive-strength */
rk_clrsetreg(&grf->gpio1_e[3][1],
GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
- /* Set pull normal for GPIO4B1, pull up for GPIO4B0 */
+ /* Set pull normal for GPIO4B1 */
rk_clrsetreg(&grf->gpio1_p[3][1],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
(GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
- (GPIO_PULL_UP << GPIO_PULL_SHIFT(0)) |
(GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
break;
value |= (mask << (shift + 16)) | (muxval << shift);
writel(value, addr);
- /* Handle pullup/pulldown */
+ /* Handle pullup/pulldown/drive-strength */
if (flags) {
uint val = 0;
val = 1;
else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
val = 2;
+ else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
+ val = 3;
+
shift = (index & 7) * 2;
ind = index >> 3;
if (banknum == 0)
addr = &priv->pmu->gpio0pull[ind];
+ else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
+ addr = &priv->grf->gpio1_e[banknum - 1][ind];
else
addr = &priv->grf->gpio1_p[banknum - 1][ind];
debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
if (flags < 0)
return flags;
+ if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12)
+ flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH;
+
ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
flags);
if (ret)
int ret;
/*
* Currently valid for the dra7xx_evm board:
- * Set TPS659038 LDO1 to 3.0 V
+ * Set TPS659038 LDO1 to 3.0 V or 1.8V
*/
- val = LDO_VOLT_3V0;
- ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val);
+ ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, voltage);
if (ret) {
printf("tps65903x: could not set LDO1 voltage.\n");
return ret;
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
-obj-$(CONFIG_PMIC_AS3722) += as3722.o
+obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o
#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
-
+#include <dm/lists.h>
#include <power/as3722.h>
+#include <power/pmic.h>
-#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
-#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
-#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
-#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
-#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
-#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
-#define AS3722_GPIO_SIGNAL_OUT 0x20
-#define AS3722_SD_CONTROL 0x4d
-#define AS3722_LDO_CONTROL 0x4e
-#define AS3722_ASIC_ID1 0x90
-#define AS3722_DEVICE_ID 0x0c
-#define AS3722_ASIC_ID2 0x91
-
-int as3722_read(struct udevice *pmic, u8 reg, u8 *value)
-{
- int err;
-
- err = dm_i2c_read(pmic, reg, value, 1);
- if (err < 0)
- return err;
-
- return 0;
-}
+#define AS3722_NUM_OF_REGS 0x92
-int as3722_write(struct udevice *pmic, u8 reg, u8 value)
+static int as3722_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
{
- int err;
+ int ret;
- err = dm_i2c_write(pmic, reg, &value, 1);
- if (err < 0)
- return err;
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret < 0)
+ return ret;
return 0;
}
-static int as3722_read_id(struct udevice *pmic, u8 *id, u8 *revision)
+static int as3722_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
{
- int err;
+ int ret;
- err = as3722_read(pmic, AS3722_ASIC_ID1, id);
- if (err) {
- error("failed to read ID1 register: %d", err);
- return err;
- }
-
- err = as3722_read(pmic, AS3722_ASIC_ID2, revision);
- if (err) {
- error("failed to read ID2 register: %d", err);
- return err;
- }
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret < 0)
+ return ret;
return 0;
}
-int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
+static int as3722_read_id(struct udevice *dev, uint *idp, uint *revisionp)
{
- u8 value;
- int err;
-
- if (sd > 6)
- return -EINVAL;
+ int ret;
- err = as3722_read(pmic, AS3722_SD_CONTROL, &value);
- if (err) {
- error("failed to read SD control register: %d", err);
- return err;
+ ret = pmic_reg_read(dev, AS3722_ASIC_ID1);
+ if (ret < 0) {
+ error("failed to read ID1 register: %d", ret);
+ return ret;
}
+ *idp = ret;
- value |= 1 << sd;
-
- err = as3722_write(pmic, AS3722_SD_CONTROL, value);
- if (err < 0) {
- error("failed to write SD control register: %d", err);
- return err;
+ ret = pmic_reg_read(dev, AS3722_ASIC_ID2);
+ if (ret < 0) {
+ error("failed to read ID2 register: %d", ret);
+ return ret;
}
+ *revisionp = ret;
return 0;
}
-int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value)
+/* TODO(treding@nvidia.com): Add proper regulator support to avoid this */
+int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value)
{
- int err;
+ int ret;
if (sd > 6)
return -EINVAL;
- err = as3722_write(pmic, AS3722_SD_VOLTAGE(sd), value);
- if (err < 0) {
- error("failed to write SD%u voltage register: %d", sd, err);
- return err;
+ ret = pmic_reg_write(dev, AS3722_SD_VOLTAGE(sd), value);
+ if (ret < 0) {
+ error("failed to write SD%u voltage register: %d", sd, ret);
+ return ret;
}
return 0;
}
-int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
+int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value)
{
- u8 value;
- int err;
+ int ret;
if (ldo > 11)
return -EINVAL;
- err = as3722_read(pmic, AS3722_LDO_CONTROL, &value);
- if (err) {
- error("failed to read LDO control register: %d", err);
- return err;
- }
-
- value |= 1 << ldo;
-
- err = as3722_write(pmic, AS3722_LDO_CONTROL, value);
- if (err < 0) {
- error("failed to write LDO control register: %d", err);
- return err;
- }
-
- return 0;
-}
-
-int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value)
-{
- int err;
-
- if (ldo > 11)
- return -EINVAL;
-
- err = as3722_write(pmic, AS3722_LDO_VOLTAGE(ldo), value);
- if (err < 0) {
+ ret = pmic_reg_write(dev, AS3722_LDO_VOLTAGE(ldo), value);
+ if (ret < 0) {
error("failed to write LDO%u voltage register: %d", ldo,
- err);
- return err;
+ ret);
+ return ret;
}
return 0;
}
-int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
- unsigned long flags)
+static int as3722_probe(struct udevice *dev)
{
- u8 value = 0;
- int err;
+ uint id, revision;
+ int ret;
- if (flags & AS3722_GPIO_OUTPUT_VDDH)
- value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
-
- if (flags & AS3722_GPIO_INVERT)
- value |= AS3722_GPIO_CONTROL_INVERT;
-
- err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
- if (err) {
- error("failed to configure GPIO#%u: %d", gpio, err);
- return err;
+ ret = as3722_read_id(dev, &id, &revision);
+ if (ret < 0) {
+ error("failed to read ID: %d", ret);
+ return ret;
}
- return 0;
-}
-
-static int as3722_gpio_set(struct udevice *pmic, unsigned int gpio,
- unsigned int level)
-{
- const char *l;
- u8 value;
- int err;
-
- if (gpio > 7)
- return -EINVAL;
-
- err = as3722_read(pmic, AS3722_GPIO_SIGNAL_OUT, &value);
- if (err < 0) {
- error("failed to read GPIO signal out register: %d", err);
- return err;
- }
-
- if (level == 0) {
- value &= ~(1 << gpio);
- l = "low";
- } else {
- value |= 1 << gpio;
- l = "high";
+ if (id != AS3722_DEVICE_ID) {
+ error("unknown device");
+ return -ENOENT;
}
- err = as3722_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
- if (err) {
- error("failed to set GPIO#%u %s: %d", gpio, l, err);
- return err;
- }
+ debug("AS3722 revision %#x found on I2C bus %s\n", revision, dev->name);
return 0;
}
-int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
- unsigned int level)
-{
- u8 value;
- int err;
-
- if (gpio > 7)
- return -EINVAL;
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "sd", .driver = "as3722_stepdown"},
+ { .prefix = "ldo", .driver = "as3722_ldo"},
+ { },
+};
- if (level == 0)
- value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
- else
- value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+static int as3722_bind(struct udevice *dev)
+{
+ struct udevice *gpio_dev;
+ ofnode regulators_node;
+ int children;
+ int ret;
- err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
- if (err) {
- error("failed to configure GPIO#%u as output: %d", gpio, err);
- return err;
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found\n", __func__,
+ dev->name);
+ return -ENXIO;
}
- err = as3722_gpio_set(pmic, gpio, level);
- if (err < 0) {
- error("failed to set GPIO#%u high: %d", gpio, err);
- return err;
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+ ret = device_bind_driver(dev, "gpio_as3722", "gpio_as3722", &gpio_dev);
+ if (ret) {
+ debug("%s: Cannot bind GPIOs (ret=%d)\n", __func__, ret);
+ return ret;
}
return 0;
}
+#endif
-/* Temporary function until we get the pmic framework */
-int as3722_get(struct udevice **devp)
+static int as3722_reg_count(struct udevice *dev)
{
- int bus = 0;
- int address = 0x40;
-
- return i2c_get_chip_for_busnum(bus, address, 1, devp);
+ return AS3722_NUM_OF_REGS;
}
-int as3722_init(struct udevice **devp)
-{
- struct udevice *pmic;
- u8 id, revision;
- const unsigned int bus = 0;
- const unsigned int address = 0x40;
- int err;
-
- err = i2c_get_chip_for_busnum(bus, address, 1, &pmic);
- if (err)
- return err;
- err = as3722_read_id(pmic, &id, &revision);
- if (err < 0) {
- error("failed to read ID: %d", err);
- return err;
- }
-
- if (id != AS3722_DEVICE_ID) {
- error("unknown device");
- return -ENOENT;
- }
-
- debug("AS3722 revision %#x found on I2C bus %u, address %#x\n",
- revision, bus, address);
- if (devp)
- *devp = pmic;
-
- return 0;
-}
+static struct dm_pmic_ops as3722_ops = {
+ .reg_count = as3722_reg_count,
+ .read = as3722_read,
+ .write = as3722_write,
+};
+
+static const struct udevice_id as3722_ids[] = {
+ { .compatible = "ams,as3722" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_as3722) = {
+ .name = "as3722_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = as3722_ids,
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+ .bind = as3722_bind,
+#endif
+ .probe = as3722_probe,
+ .ops = &as3722_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+
+#define NUM_GPIOS 8
+
+int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
+ unsigned long flags)
+{
+ u8 value = 0;
+ int err;
+
+ if (flags & AS3722_GPIO_OUTPUT_VDDH)
+ value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ if (flags & AS3722_GPIO_INVERT)
+ value |= AS3722_GPIO_CONTROL_INVERT;
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio,
+ int level)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ const char *l;
+ u8 value;
+ int err;
+
+ if (gpio >= NUM_GPIOS)
+ return -EINVAL;
+
+ err = pmic_reg_read(pmic, AS3722_GPIO_SIGNAL_OUT);
+ if (err < 0) {
+ error("failed to read GPIO signal out register: %d", err);
+ return err;
+ }
+ value = err;
+
+ if (level == 0) {
+ value &= ~(1 << gpio);
+ l = "low";
+ } else {
+ value |= 1 << gpio;
+ l = "high";
+ }
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
+ if (err) {
+ error("failed to set GPIO#%u %s: %d", gpio, l, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_gpio_direction_output(struct udevice *dev, unsigned int gpio,
+ int value)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int err;
+
+ if (gpio > 7)
+ return -EINVAL;
+
+ if (value == 0)
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
+ else
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u as output: %d", gpio, err);
+ return err;
+ }
+
+ err = as3722_gpio_set_value(pmic, gpio, value);
+ if (err < 0) {
+ error("failed to set GPIO#%u high: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = NUM_GPIOS;
+ uc_priv->bank_name = "as3722_";
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_as3722_ops = {
+ .direction_output = as3722_gpio_direction_output,
+ .set_value = as3722_gpio_set_value,
+};
+
+U_BOOT_DRIVER(gpio_as3722) = {
+ .name = "gpio_as3722",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_as3722_ops,
+ .probe = as3722_gpio_probe,
+};
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
+config REGULATOR_AS3722
+ bool "Enable driver for AS7322 regulator"
+ depends on DM_REGULATOR && PMIC_AS3722
+ help
+ Enable support for the regulator functions of the AS3722. The
+ driver implements enable/disable for step-down bucks and LDOs,
+ but does not yet support change voltages. Currently this must be
+ done using direct register writes to the PMIC.
+
config DM_REGULATOR_PFUZE100
bool "Enable Driver Model for REGULATOR PFUZE100"
depends on DM_REGULATOR && DM_PMIC_PFUZE100
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
+obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Placeholder regulator driver for as3722.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+static int stepdown_get_value(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static int stepdown_set_value(struct udevice *dev, int uvolt)
+{
+ return -ENOSYS;
+}
+
+static int stepdown_set_enable(struct udevice *dev, bool enable)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int sd = dev->driver_data;
+ int ret;
+
+ ret = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
+ if (ret < 0) {
+ debug("%s: failed to write SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stepdown_get_enable(struct udevice *dev)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int sd = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(pmic, AS3722_SD_CONTROL);
+ if (ret < 0) {
+ debug("%s: failed to read SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return ret & (1 << sd) ? true : false;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static int ldo_set_value(struct udevice *dev, int uvolt)
+{
+ return -ENOSYS;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ldo = dev->driver_data;
+ int ret;
+
+ ret = pmic_clrsetbits(pmic, AS3722_LDO_CONTROL, 0, 1 << ldo);
+ if (ret < 0) {
+ debug("%s: failed to write LDO control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ldo = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(pmic, AS3722_LDO_CONTROL);
+ if (ret < 0) {
+ debug("%s: failed to read SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return ret & (1 << ldo) ? true : false;
+}
+
+static int as3722_stepdown_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ return 0;
+}
+
+static int as3722_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ return 0;
+}
+
+static const struct dm_regulator_ops as3722_stepdown_ops = {
+ .get_value = stepdown_get_value,
+ .set_value = stepdown_set_value,
+ .get_enable = stepdown_get_enable,
+ .set_enable = stepdown_set_enable,
+};
+
+static const struct dm_regulator_ops as3722_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(as3722_stepdown) = {
+ .name = "as3722_stepdown",
+ .id = UCLASS_REGULATOR,
+ .ops = &as3722_stepdown_ops,
+ .probe = as3722_stepdown_probe,
+};
+
+U_BOOT_DRIVER(as3722_ldo) = {
+ .name = "as3722_ldo",
+ .id = UCLASS_REGULATOR,
+ .ops = &as3722_ldo_ops,
+ .probe = as3722_ldo_probe,
+};
return pmic_reg_write(dev->parent, adr, ret);
}
+static int palmas_ldo_bypass_enable(struct udevice *dev, bool enabled)
+{
+ int type = dev_get_driver_data(dev_get_parent(dev));
+ struct dm_regulator_uclass_platdata *p;
+ unsigned int adr;
+ int reg;
+
+ if (type == TPS65917) {
+ /* bypass available only on LDO1 and LDO2 */
+ if (dev->driver_data > 2)
+ return -ENOTSUPP;
+ } else if (type == TPS659038) {
+ /* bypass available only on LDO9 */
+ if (dev->driver_data != 9)
+ return -ENOTSUPP;
+ }
+
+ p = dev_get_uclass_platdata(dev);
+ adr = p->ctrl_reg;
+
+ reg = pmic_reg_read(dev->parent, adr);
+ if (reg < 0)
+ return reg;
+
+ if (enabled)
+ reg |= PALMAS_LDO_BYPASS_EN;
+ else
+ reg &= ~PALMAS_LDO_BYPASS_EN;
+
+ return pmic_reg_write(dev->parent, adr, reg);
+}
+
static int palmas_ldo_enable(struct udevice *dev, int op, bool *enable)
{
int ret;
ret = pmic_reg_write(dev->parent, adr, ret);
if (ret)
return ret;
+
+ ret = palmas_ldo_bypass_enable(dev, false);
+ if (ret && (ret != -ENOTSUPP))
+ return ret;
}
return 0;
}
ret = pwm_set_config(priv->pwm, priv->pwm_id,
- (priv->period_ns / 100) * duty_cycle, priv->period_ns);
+ priv->period_ns, (priv->period_ns / 100) * duty_cycle);
if (ret) {
dev_err(dev, "Failed to configure PWM\n");
return ret;
}
- ret = pwm_set_enable(priv->pwm, priv->pwm_id, true);
- if (ret) {
- dev_err(dev, "Failed to enable PWM\n");
- return ret;
- }
priv->volt_uV = uvolt;
+
return ret;
}
if (priv->init_voltage)
pwm_regulator_set_voltage(dev, priv->init_voltage);
- pwm_regulator_enable(dev, 1);
-
return 0;
}
struct rk_pwm_priv *priv = dev_get_priv(dev);
debug("%s: polarity=%u\n", __func__, polarity);
+ priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
if (polarity)
priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
else
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct pwm_ctlr *)devfdt_get_addr(dev);
+ priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
return 0;
}
debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
reset_ctl);
+ reset_ctl->dev = NULL;
ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
index, &args);
debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
reset_ctl);
+ reset_ctl->dev = NULL;
index = dev_read_stringlist_search(dev, "reset-names", name);
if (index < 0) {
return reset_get_by_index(dev, index, reset_ctl);
}
+int reset_request(struct reset_ctl *reset_ctl)
+{
+ struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+ debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+ return ops->request(reset_ctl);
+}
+
int reset_free(struct reset_ctl *reset_ctl)
{
struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
return ops->rst_deassert(reset_ctl);
}
+int reset_release_all(struct reset_ctl *reset_ctl, int count)
+{
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ debug("%s(reset_ctl[%d]=%p)\n", __func__, i, &reset_ctl[i]);
+
+ /* check if reset has been previously requested */
+ if (!reset_ctl[i].dev)
+ continue;
+
+ ret = reset_assert(&reset_ctl[i]);
+ if (ret)
+ return ret;
+
+ ret = reset_free(&reset_ctl[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(reset) = {
.id = UCLASS_RESET,
.name = "reset",
dev_desc->product[0] = 0;
dev_desc->revision[0] = 0;
dev_desc->removable = false;
-#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(BLK)
dev_desc->block_read = scsi_read;
dev_desc->block_write = scsi_write;
#endif
on STiH410 SoC. This is a basic implementation, it supports
following baudrate 9600, 19200, 38400, 57600 and 115200.
+config STM32X7_SERIAL
+ bool "STMicroelectronics STM32 SoCs on-chip UART"
+ depends on DM_SERIAL && STM32F7
+ help
+ If you have a machine based on a STM32 F7 you can enable its
+ onboard serial ports, say Y to this option. If unsure, say N.
+
config MPC8XX_CONS
bool "Console driver for MPC8XX"
depends on 8xx
*/
static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
-#ifndef CONFIG_SYS_MALLOC_F_LEN
-#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work"
+#if !CONFIG_VAL(SYS_MALLOC_F_LEN)
+#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work"
#endif
static int serial_check_stdout(const void *blob, struct udevice **devp)
memset(&sdev, '\0', sizeof(sdev));
strncpy(sdev.name, dev->name, sizeof(sdev.name));
- sdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
+ sdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_DM;
sdev.priv = dev;
sdev.putc = serial_stub_putc;
sdev.puts = serial_stub_puts;
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <spi.h>
-#include <fdtdec.h>
#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->base = dev_read_addr(bus);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
}
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
- "spi-deactivate-delay", 0);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
+ "spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
config X86_TSC_TIMER
bool "x86 Time-Stamp Counter (TSC) timer support"
depends on TIMER && X86
- default y if X86
help
Select this to enable Time-Stamp Counter (TSC) timer for x86.
#include <dm.h>
#include <malloc.h>
#include <timer.h>
+#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/i8254.h>
#include <asm/ibmpc.h>
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
-/* CPU reference clock frequency: in KHz */
-#define FREQ_83 83200
-#define FREQ_100 99840
-#define FREQ_133 133200
-#define FREQ_166 166400
-
#define MAX_NUM_FREQS 8
DECLARE_GLOBAL_DATA_PTR;
static struct freq_desc freq_desc_tables[] = {
/* PNW */
- { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
/* CLV+ */
- { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
- /* TNG */
- { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
- /* VLV2 */
- { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+ { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
+ /* TNG - Intel Atom processor Z3400 series */
+ { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
+ /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
+ { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
+ /* ANN - Intel Atom processor Z3500 series */
+ { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
/* Ivybridge */
{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
- /* ANN */
- { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
};
static int match_cpu(u8 family, u8 model)
(freq_desc_tables[cpu_index].freqs[freq_id])
/*
- * Do MSR calibration only for known/supported CPUs.
+ * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
+ * reliable and the frequency is known (provided by HW).
+ *
+ * On these platforms PIT/HPET is generally not available so calibration won't
+ * work at all and there is no other clocksource to act as a watchdog for the
+ * TSC, so we have no other choice than to trust it.
*
- * Returns the calibration value or 0 if MSR calibration failed.
+ * Returns the TSC frequency in MHz or 0 if HW does not provide it.
*/
-static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
+static unsigned long __maybe_unused cpu_mhz_from_msr(void)
{
u32 lo, hi, ratio, freq_id, freq;
unsigned long res;
int cpu_index;
+ if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+ return 0;
+
cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
if (cpu_index < 0)
return 0;
if (freq_desc_tables[cpu_index].msr_plat) {
rdmsr(MSR_PLATFORM_INFO, lo, hi);
- ratio = (lo >> 8) & 0x1f;
+ ratio = (lo >> 8) & 0xff;
} else {
rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
ratio = (hi >> 8) & 0x1f;
}
debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
- if (!ratio)
- goto fail;
-
if (freq_desc_tables[cpu_index].msr_plat == 2) {
/* TODO: Figure out how best to deal with this */
- freq = FREQ_100;
+ freq = 100000;
debug("Using frequency: %u KHz\n", freq);
} else {
/* Get FSB FREQ ID */
debug("Resolved frequency ID: %u, frequency: %u KHz\n",
freq_id, freq);
}
- if (!freq)
- goto fail;
/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
res = freq * ratio / 1000;
debug("TSC runs at %lu MHz\n", res);
return res;
-
-fail:
- debug("Fast TSC calibration using MSR failed\n");
- return 0;
}
/*
if (!uc_priv->clock_rate) {
unsigned long fast_calibrate;
- fast_calibrate = try_msr_calibrate_tsc();
+ fast_calibrate = cpu_mhz_from_msr();
if (!fast_calibrate) {
fast_calibrate = quick_pit_calibrate();
if (!fast_calibrate)
1 << 7),
.bPwrOn2PwrGood = 2,
.bHubContrCurrent = 5,
- .DeviceRemovable = {0, 0xff}, /* all ports removeable */
+ {
+ {
+ /* all ports removeable */
+ .DeviceRemovable = {0, 0xff}
+ }
+ }
#if SANDBOX_NUM_PORTS > 8
#error "This code sets up an incorrect mask"
#endif
}
if (dev->out_ep->driver_data) {
+ free(dev->out_req->buf);
dev->out_req->buf = NULL;
usb_ep_free_request(dev->out_ep, dev->out_req);
usb_ep_disable(dev->out_ep);
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_PCI
+ bool "Support for PCI-based xHCI USB controller"
+ depends on DM_USB
+ default y if X86
+ help
+ Enables support for the PCI-based xHCI controller.
+
config USB_XHCI_ROCKCHIP
bool "Support for Rockchip on-chip xHCI USB controller"
depends on ARCH_ROCKCHIP
#include <common.h>
#include <clk.h>
+#include <dm/ofnode.h>
+#include <generic-phy.h>
#include <reset.h>
#include <asm/io.h>
#include <dm.h>
*/
struct generic_ehci {
struct ehci_ctrl ctrl;
+ struct clk *clocks;
+ struct reset_ctl *resets;
+ struct phy phy;
+ int clock_count;
+ int reset_count;
};
static int ehci_usb_probe(struct udevice *dev)
{
+ struct generic_ehci *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- int i;
-
- for (i = 0; ; i++) {
- struct clk clk;
- int ret;
-
- ret = clk_get_by_index(dev, i, &clk);
- if (ret < 0)
- break;
- if (clk_enable(&clk))
- printf("failed to enable clock %d\n", i);
- clk_free(&clk);
+ int i, err, ret, clock_nb, reset_nb;
+
+ err = 0;
+ priv->clock_count = 0;
+ clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
+ "#clock-cells");
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+
+ if (err < 0)
+ break;
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ error("failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ } else {
+ if (clock_nb != -ENOENT) {
+ error("failed to get clock phandle(%d)\n", clock_nb);
+ return clock_nb;
+ }
+ }
+
+ priv->reset_count = 0;
+ reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
+ "#reset-cells");
+ if (reset_nb > 0) {
+ priv->resets = devm_kcalloc(dev, reset_nb,
+ sizeof(struct reset_ctl),
+ GFP_KERNEL);
+ if (!priv->resets)
+ return -ENOMEM;
+
+ for (i = 0; i < reset_nb; i++) {
+ err = reset_get_by_index(dev, i, &priv->resets[i]);
+ if (err < 0)
+ break;
+
+ if (reset_deassert(&priv->resets[i])) {
+ error("failed to deassert reset %d\n", i);
+ reset_free(&priv->resets[i]);
+ goto reset_err;
+ }
+ priv->reset_count++;
+ }
+ } else {
+ if (reset_nb != -ENOENT) {
+ error("failed to get reset phandle(%d)\n", reset_nb);
+ goto clk_err;
+ }
}
- for (i = 0; ; i++) {
- struct reset_ctl reset;
- int ret;
+ err = generic_phy_get_by_index(dev, 0, &priv->phy);
+ if (err) {
+ if (err != -ENOENT) {
+ error("failed to get usb phy\n");
+ goto reset_err;
+ }
+ } else {
- ret = reset_get_by_index(dev, i, &reset);
- if (ret < 0)
- break;
- if (reset_deassert(&reset))
- printf("failed to deassert reset %d\n", i);
- reset_free(&reset);
+ err = generic_phy_init(&priv->phy);
+ if (err) {
+ error("failed to init usb phy\n");
+ goto reset_err;
+ }
}
hccr = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+ err = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+ if (err)
+ goto phy_err;
+
+ return 0;
+
+phy_err:
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ error("failed to release phy\n");
+ }
+
+reset_err:
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ error("failed to assert all resets\n");
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ error("failed to disable all clocks\n");
+
+ return err;
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+ struct generic_ehci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = ehci_deregister(dev);
+ if (ret)
+ return ret;
+
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ return ret;
+ }
+
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ return ret;
+
+ return clk_release_all(priv->clocks, priv->clock_count);
}
static const struct udevice_id ehci_usb_ids[] = {
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
.probe = ehci_usb_probe,
- .remove = ehci_deregister,
+ .remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
.priv_auto_alloc_size = sizeof(struct generic_ehci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
0, /* wHubCharacteristics */
10, /* bPwrOn2PwrGood */
0, /* bHubCntrCurrent */
- {}, /* Device removable */
- {} /* at most 7 ports! XXX */
+ { /* Device removable */
+ } /* at most 7 ports! XXX */
},
{
0x12, /* bLength */
static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
{
- if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+ int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
+
+ if (port < 0 || port >= max_ports) {
/* Printing the message would cause a scan failure! */
- debug("The request port(%u) is not configured\n", port);
+ debug("The request port(%u) exceeds maximum port number\n",
+ port);
return NULL;
}
{
int i, ret = 0;
uint32_t cmd, reg;
+ int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
if (!ctrl || !ctrl->hcor)
return -EINVAL;
100 * 1000);
if (!ret) {
- for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
+ for (i = 0; i < max_ports; i++) {
reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
reg |= EHCI_PS_SUSP;
ehci_writel(&ctrl->hcor->or_portsc[i], reg);
return -1;
}
-const struct ehci_ops default_ehci_ops = {
+static const struct ehci_ops default_ehci_ops = {
.set_usb_mode = ehci_set_usbmode,
.get_port_speed = ehci_get_port_speed,
.powerup_fixup = ehci_powerup_fixup,
#include <usb.h>
#include <usb/ulpi.h>
#include <libfdt.h>
-#include <fdtdec.h>
#include "ehci.h"
static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
const char *phy, *mode;
- config->reg = (struct usb_ctlr *)devfdt_get_addr(dev);
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ config->reg = (struct usb_ctlr *)dev_read_addr(dev);
+ debug("reg=%p\n", config->reg);
+ mode = dev_read_string(dev, "dr_mode");
if (mode) {
if (0 == strcmp(mode, "host"))
config->dr_mode = DR_MODE_HOST;
config->dr_mode = DR_MODE_HOST;
}
- phy = fdt_getprop(blob, node, "phy_type", NULL);
+ phy = dev_read_string(dev, "phy_type");
config->utmi = phy && 0 == strcmp("utmi", phy);
config->ulpi = phy && 0 == strcmp("ulpi", phy);
- config->enabled = fdtdec_get_is_enabled(blob, node);
- config->has_legacy_mode = fdtdec_get_bool(blob, node,
- "nvidia,has-legacy-mode");
- config->periph_id = clock_decode_periph_id(blob, node);
+ config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
+ config->periph_id = clock_decode_periph_id(dev);
if (config->periph_id == PERIPH_ID_NONE) {
debug("%s: Missing/invalid peripheral ID\n", __func__);
return -EINVAL;
}
- gpio_request_by_name_nodev(offset_to_ofnode(node), "nvidia,vbus-gpio",
- 0, &config->vbus_gpio, GPIOD_IS_OUT);
- gpio_request_by_name_nodev(offset_to_ofnode(node),
- "nvidia,phy-reset-gpio", 0,
- &config->phy_reset_gpio, GPIOD_IS_OUT);
- debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
- "vbus=%d, phy_reset=%d, dr_mode=%d\n",
- config->enabled, config->has_legacy_mode, config->utmi,
- config->ulpi, config->periph_id,
- gpio_get_number(&config->vbus_gpio),
- gpio_get_number(&config->phy_reset_gpio), config->dr_mode);
+ gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
+ GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
+ &config->phy_reset_gpio, GPIOD_IS_OUT);
+ debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n",
+ config->has_legacy_mode, config->utmi, config->ulpi,
+ config->periph_id, gpio_get_number(&config->vbus_gpio),
+ gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
+ config->reg);
return 0;
}
#include <usb.h>
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-#endif
+/* Section 2.2.3 - N_PORTS */
+#define MAX_HC_PORTS 15
/*
* Register Space.
uint32_t _reserved_1_[6];
uint32_t or_configflag;
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
- uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+ uint32_t or_portsc[MAX_HC_PORTS];
#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
#define PORTSC_PSPD_FS 0x0
#define PORTSC_PSPD_LS 0x1
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
+#include <dm/ofnode.h>
+#include <generic-phy.h>
+#include <reset.h>
#include "ohci.h"
#if !defined(CONFIG_USB_OHCI_NEW)
struct generic_ohci {
ohci_t ohci;
+ struct clk *clocks; /* clock list */
+ struct reset_ctl *resets; /* reset list */
+ struct phy phy;
+ int clock_count; /* number of clock in clock list */
+ int reset_count; /* number of reset in reset list */
};
static int ohci_usb_probe(struct udevice *dev)
{
struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int i, err, ret, clock_nb, reset_nb;
- return ohci_register(dev, regs);
+ err = 0;
+ priv->clock_count = 0;
+ clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+ if (err < 0)
+ break;
+
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ error("failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ } else if (clock_nb != -ENOENT) {
+ error("failed to get clock phandle(%d)\n", clock_nb);
+ return clock_nb;
+ }
+
+ priv->reset_count = 0;
+ reset_nb = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
+ if (reset_nb > 0) {
+ priv->resets = devm_kcalloc(dev, reset_nb,
+ sizeof(struct reset_ctl),
+ GFP_KERNEL);
+ if (!priv->resets)
+ return -ENOMEM;
+
+ for (i = 0; i < reset_nb; i++) {
+ err = reset_get_by_index(dev, i, &priv->resets[i]);
+ if (err < 0)
+ break;
+
+ err = reset_deassert(&priv->resets[i]);
+ if (err) {
+ error("failed to deassert reset %d\n", i);
+ reset_free(&priv->resets[i]);
+ goto reset_err;
+ }
+ priv->reset_count++;
+ }
+ } else if (reset_nb != -ENOENT) {
+ error("failed to get reset phandle(%d)\n", reset_nb);
+ goto clk_err;
+ }
+
+ err = generic_phy_get_by_index(dev, 0, &priv->phy);
+ if (err) {
+ if (err != -ENOENT) {
+ error("failed to get usb phy\n");
+ goto reset_err;
+ }
+ } else {
+
+ err = generic_phy_init(&priv->phy);
+ if (err) {
+ error("failed to init usb phy\n");
+ goto reset_err;
+ }
+ }
+
+ err = ohci_register(dev, regs);
+ if (err)
+ goto phy_err;
+
+ return 0;
+
+phy_err:
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ error("failed to release phy\n");
+ }
+
+reset_err:
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ error("failed to assert all resets\n");
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ error("failed to disable all clocks\n");
+
+ return err;
}
static int ohci_usb_remove(struct udevice *dev)
{
- return ohci_deregister(dev);
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = ohci_deregister(dev);
+ if (ret)
+ return ret;
+
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ return ret;
+ }
+
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ return ret;
+
+ return clk_release_all(priv->clocks, priv->clock_count);
}
static const struct udevice_id ohci_usb_ids[] = {
return ops->reset_root_port(bus, udev);
}
+int usb_update_hub_device(struct usb_device *udev)
+{
+ struct udevice *bus = udev->controller_dev;
+ struct dm_usb_ops *ops = usb_get_ops(bus);
+
+ if (!ops->update_hub_device)
+ return -ENOSYS;
+
+ return ops->update_hub_device(bus, udev);
+}
+
int usb_stop(void)
{
struct udevice *bus;
#ifdef CONFIG_USB_STORAGE
usb_stor_reset();
#endif
- usb_hub_reset();
uc_priv->companion_device_count = 0;
usb_started = 0;
int ret;
asynch_allowed = 1;
- usb_hub_reset();
ret = uclass_get(UCLASS_USB, &uc);
if (ret)
}
/* returns 0 if no match, 1 if match */
-int usb_match_device(const struct usb_device_descriptor *desc,
- const struct usb_device_id *id)
+static int usb_match_device(const struct usb_device_descriptor *desc,
+ const struct usb_device_id *id)
{
if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
id->idVendor != le16_to_cpu(desc->idVendor))
}
/* returns 0 if no match, 1 if match */
-int usb_match_one_id_intf(const struct usb_device_descriptor *desc,
- const struct usb_interface_descriptor *int_desc,
- const struct usb_device_id *id)
+static int usb_match_one_id_intf(const struct usb_device_descriptor *desc,
+ const struct usb_interface_descriptor *int_desc,
+ const struct usb_device_id *id)
{
/* The interface class, subclass, protocol and number should never be
* checked for a match if the device class is Vendor Specific,
}
/* returns 0 if no match, 1 if match */
-int usb_match_one_id(struct usb_device_descriptor *desc,
- struct usb_interface_descriptor *int_desc,
- const struct usb_device_id *id)
+static int usb_match_one_id(struct usb_device_descriptor *desc,
+ struct usb_interface_descriptor *int_desc,
+ const struct usb_device_id *id)
{
if (!usb_match_device(desc, id))
return 0;
return change;
}
-int usb_child_post_bind(struct udevice *dev)
+static int usb_child_post_bind(struct udevice *dev)
{
struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
int val;
*/
#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <generic-phy.h>
+#include <usb.h>
+
+#include "xhci.h"
#include <asm/io.h>
#include <linux/usb/dwc3.h>
+#include <linux/usb/otg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct xhci_dwc3_platdata {
+ struct phy usb_phy;
+};
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
DWC3_GCTL_PRTCAPDIR(mode));
}
-void dwc3_phy_reset(struct dwc3 *dwc3_reg)
+static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
{
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
GFLADJ_30MHZ(val));
}
+
+#ifdef CONFIG_DM_USB
+static int xhci_dwc3_probe(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ struct dwc3 *dwc3_reg;
+ enum usb_dr_mode dr_mode;
+ int ret;
+
+ hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+ hcor = (struct xhci_hcor *)((uintptr_t)hccr +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+ ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
+ if (ret) {
+ if (ret != -ENOENT) {
+ error("Failed to get USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ } else {
+ ret = generic_phy_init(&plat->usb_phy);
+ if (ret) {
+ error("Can't init USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
+ dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
+
+ dwc3_core_init(dwc3_reg);
+
+ dr_mode = usb_get_dr_mode(dev_of_offset(dev));
+ if (dr_mode == USB_DR_MODE_UNKNOWN)
+ /* by default set dual role mode to HOST */
+ dr_mode = USB_DR_MODE_HOST;
+
+ dwc3_set_mode(dwc3_reg, dr_mode);
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_dwc3_remove(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ if (generic_phy_valid(&plat->usb_phy)) {
+ ret = generic_phy_exit(&plat->usb_phy);
+ if (ret) {
+ error("Can't deinit USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_dwc3_ids[] = {
+ { .compatible = "snps,dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(xhci_dwc3) = {
+ .name = "xhci-dwc3",
+ .id = UCLASS_USB,
+ .of_match = xhci_dwc3_ids,
+ .probe = xhci_dwc3_probe,
+ .remove = xhci_dwc3_remove,
+ .ops = &xhci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
+ .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
}
/**
+ * Free the scratchpad buffer array and scratchpad buffers
+ *
+ * @ctrl host controller data structure
+ * @return none
+ */
+static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
+{
+ if (!ctrl->scratchpad)
+ return;
+
+ ctrl->dcbaa->dev_context_ptrs[0] = 0;
+
+ free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]);
+ free(ctrl->scratchpad->sp_array);
+ free(ctrl->scratchpad);
+ ctrl->scratchpad = NULL;
+}
+
+/**
* frees the "xhci_container_ctx" pointer passed
*
* @param ptr pointer to "xhci_container_ctx" to be freed
{
xhci_ring_free(ctrl->event_ring);
xhci_ring_free(ctrl->cmd_ring);
+ xhci_scratchpad_free(ctrl);
xhci_free_virt_devices(ctrl);
free(ctrl->erst.entries);
free(ctrl->dcbaa);
}
/**
+ * Set up the scratchpad buffer array and scratchpad buffers
+ *
+ * @ctrl host controller data structure
+ * @return -ENOMEM if buffer allocation fails, 0 on success
+ */
+static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
+{
+ struct xhci_hccr *hccr = ctrl->hccr;
+ struct xhci_hcor *hcor = ctrl->hcor;
+ struct xhci_scratchpad *scratchpad;
+ int num_sp;
+ uint32_t page_size;
+ void *buf;
+ int i;
+
+ num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
+ if (!num_sp)
+ return 0;
+
+ scratchpad = malloc(sizeof(*scratchpad));
+ if (!scratchpad)
+ goto fail_sp;
+ ctrl->scratchpad = scratchpad;
+
+ scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
+ if (!scratchpad->sp_array)
+ goto fail_sp2;
+ ctrl->dcbaa->dev_context_ptrs[0] =
+ cpu_to_le64((uintptr_t)scratchpad->sp_array);
+
+ page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
+ for (i = 0; i < 16; i++) {
+ if ((0x1 & page_size) != 0)
+ break;
+ page_size = page_size >> 1;
+ }
+ BUG_ON(i == 16);
+
+ page_size = 1 << (i + 12);
+ buf = memalign(page_size, num_sp * page_size);
+ if (!buf)
+ goto fail_sp3;
+ memset(buf, '\0', num_sp * page_size);
+ xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
+
+ for (i = 0; i < num_sp; i++) {
+ uintptr_t ptr = (uintptr_t)buf + i * page_size;
+ scratchpad->sp_array[i] = cpu_to_le64(ptr);
+ }
+
+ return 0;
+
+fail_sp3:
+ free(scratchpad->sp_array);
+
+fail_sp2:
+ free(scratchpad);
+ ctrl->scratchpad = NULL;
+
+fail_sp:
+ return -ENOMEM;
+}
+
+/**
* Allocates the Container context
*
* @param ctrl Host controller data structure
xhci_writeq(&ctrl->ir_set->erst_base, val_64);
+ /* set up the scratchpad buffer array and scratchpad buffers */
+ xhci_scratchpad_alloc(ctrl);
+
/* initializing the virtual devices to NULL */
for (i = 0; i < MAX_HC_SLOTS; ++i)
ctrl->devs[i] = NULL;
* @param udev pointer to the Device Data Structure
* @return returns negative value on failure else 0 on success
*/
-void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, int slot_id,
- int speed, int hop_portnr)
+void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
+ struct usb_device *udev, int hop_portnr)
{
struct xhci_virt_device *virt_dev;
struct xhci_ep_ctx *ep0_ctx;
struct xhci_slot_ctx *slot_ctx;
u32 port_num = 0;
u64 trb_64 = 0;
+ int slot_id = udev->slot_id;
+ int speed = udev->speed;
+ int route = 0;
+#ifdef CONFIG_DM_USB
+ struct usb_device *dev = udev;
+ struct usb_hub_device *hub;
+#endif
virt_dev = ctrl->devs[slot_id];
slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
/* Only the control endpoint is valid - one endpoint context */
- slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | 0);
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
+
+#ifdef CONFIG_DM_USB
+ /* Calculate the route string for this device */
+ port_num = dev->portnr;
+ while (!usb_hub_is_root_hub(dev->dev)) {
+ hub = dev_get_uclass_priv(dev->dev);
+ /*
+ * Each hub in the topology is expected to have no more than
+ * 15 ports in order for the route string of a device to be
+ * unique. SuperSpeed hubs are restricted to only having 15
+ * ports, but FS/LS/HS hubs are not. The xHCI specification
+ * says that if the port number the device is greater than 15,
+ * that portion of the route string shall be set to 15.
+ */
+ if (port_num > 15)
+ port_num = 15;
+ route |= port_num << (hub->hub_depth * 4);
+ dev = dev_get_parent_priv(dev->dev);
+ port_num = dev->portnr;
+ dev = dev_get_parent_priv(dev->dev->parent);
+ }
+
+ debug("route string %x\n", route);
+#endif
+ slot_ctx->dev_info |= route;
switch (speed) {
case USB_SPEED_SUPER:
BUG();
}
+#ifdef CONFIG_DM_USB
+ /* Set up TT fields to support FS/LS devices */
+ if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
+ dev = dev_get_parent_priv(udev->dev);
+ if (dev->speed == USB_SPEED_HIGH) {
+ hub = dev_get_uclass_priv(udev->dev);
+ if (hub->tt.multi)
+ slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
+ slot_ctx->tt_info |= cpu_to_le32(TT_PORT(udev->portnr));
+ slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
+ }
+ }
+#endif
+
port_num = hop_portnr;
debug("port_num = %d\n", port_num);
#include <common.h>
#include <dm.h>
-#include <errno.h>
#include <pci.h>
#include <usb.h>
-
#include "xhci.h"
-#ifndef CONFIG_DM_USB
-
-/*
- * Create the appropriate control structures to manage a new XHCI host
- * controller.
- */
-int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
- struct xhci_hcor **ret_hcor)
-{
- struct xhci_hccr *hccr;
- struct xhci_hcor *hcor;
- pci_dev_t pdev;
- uint32_t cmd;
- int len;
-
- pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
- if (pdev < 0) {
- printf("XHCI host controller not found\n");
- return -1;
- }
-
- hccr = (struct xhci_hccr *)pci_map_bar(pdev,
- PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
- hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
-
- debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor, len);
-
- *ret_hccr = hccr;
- *ret_hcor = hcor;
-
- /* enable busmaster */
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER;
- pci_write_config_dword(pdev, PCI_COMMAND, cmd);
-
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding * to the XHCI host
- * controller
- */
-void xhci_hcd_stop(int index)
-{
-}
-
-#else
-
-struct xhci_pci_priv {
- struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
-};
-
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
{
return xhci_register(dev, hccr, hcor);
}
-static int xhci_pci_remove(struct udevice *dev)
-{
- int ret;
-
- ret = xhci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id xhci_pci_ids[] = {
{ .compatible = "xhci-pci" },
{ }
.name = "xhci_pci",
.id = UCLASS_USB,
.probe = xhci_pci_probe,
- .remove = xhci_pci_remove,
+ .remove = xhci_deregister,
.of_match = xhci_pci_ids,
.ops = &xhci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct xhci_pci_priv),
+ .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
};
U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported);
-
-#endif /* CONFIG_DM_USB */
fields[0] = lower_32_bits(val_64);
fields[1] = upper_32_bits(val_64);
fields[2] = 0;
- fields[3] = TRB_TYPE(cmd) | EP_ID_FOR_TRB(ep_index) |
- SLOT_ID_FOR_TRB(slot_id) | ctrl->cmd_ring->cycle_state;
+ fields[3] = TRB_TYPE(cmd) | SLOT_ID_FOR_TRB(slot_id) |
+ ctrl->cmd_ring->cycle_state;
+
+ /*
+ * Only 'reset endpoint', 'stop endpoint' and 'set TR dequeue pointer'
+ * commands need endpoint id encoded.
+ */
+ if (cmd >= TRB_RESET_EP && cmd <= TRB_SET_DEQ)
+ fields[3] |= EP_ID_FOR_TRB(ep_index);
queue_trb(ctrl, ctrl->cmd_ring, false, fields);
cpu_to_le16(0x8), /* wHubCharacteristics */
10, /* bPwrOn2PwrGood */
0, /* bHubCntrCurrent */
- {}, /* Device removable */
- {} /* at most 7 ports! XXX */
+ { /* Device removable */
+ } /* at most 7 ports! XXX */
},
{
0x12, /* bLength */
* @param hcor pointer to host controller operation registers
* @return -EBUSY if XHCI Controller is not halted else status of handshake
*/
-int xhci_reset(struct xhci_hcor *hcor)
+static int xhci_reset(struct xhci_hcor *hcor)
{
u32 cmd;
u32 state;
ifdesc = &udev->config.if_desc[0];
ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
- /* Zero the input context control */
- ctrl_ctx->add_flags = 0;
+ /* Initialize the input context control */
+ ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
ctrl_ctx->drop_flags = 0;
/* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
* so setting up the slot context.
*/
debug("Setting up addressable devices %p\n", ctrl->dcbaa);
- xhci_setup_addressable_virt_dev(ctrl, udev->slot_id, udev->speed,
- root_portnr);
+ xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
* @param udev pointer to the Device Data Structure
* @return Returns 0 on succes else return error code on failure
*/
-int _xhci_alloc_device(struct usb_device *udev)
+static int _xhci_alloc_device(struct usb_device *udev)
{
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
union xhci_trb *event;
uint32_t reg;
volatile uint32_t *status_reg;
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
+ struct xhci_hccr *hccr = ctrl->hccr;
struct xhci_hcor *hcor = ctrl->hcor;
+ int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
if ((req->requesttype & USB_RT_PORT) &&
- le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
- printf("The request port(%d) is not configured\n",
- le16_to_cpu(req->index) - 1);
+ le16_to_cpu(req->index) > max_ports) {
+ printf("The request port(%d) exceeds maximum port number\n",
+ le16_to_cpu(req->index) - 1);
return -EINVAL;
}
case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
switch (le16_to_cpu(req->value) >> 8) {
case USB_DT_HUB:
+ case USB_DT_SS_HUB:
debug("USB_DT_HUB config\n");
srcptr = &descriptor.hub;
srclen = 0x8;
#endif /* CONFIG_DM_USB */
#ifdef CONFIG_DM_USB
-/*
-static struct usb_device *get_usb_device(struct udevice *dev)
-{
- struct usb_device *udev;
-
- if (device_get_uclass_id(dev) == UCLASS_USB)
- udev = dev_get_uclass_priv(dev);
- else
- udev = dev_get_parent_priv(dev);
-
- return udev;
-}
-*/
-static bool is_root_hub(struct udevice *dev)
-{
- if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB)
- return true;
-
- return false;
-}
static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
hub = udev->dev;
if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
/* Figure out our port number on the root hub */
- if (is_root_hub(hub)) {
+ if (usb_hub_is_root_hub(hub)) {
root_portnr = udev->portnr;
} else {
- while (!is_root_hub(hub->parent))
+ while (!usb_hub_is_root_hub(hub->parent))
hub = hub->parent;
uhop = dev_get_parent_priv(hub);
root_portnr = uhop->portnr;
return _xhci_alloc_device(udev);
}
+static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
+{
+ struct xhci_ctrl *ctrl = dev_get_priv(dev);
+ struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
+ struct xhci_virt_device *virt_dev;
+ struct xhci_input_control_ctx *ctrl_ctx;
+ struct xhci_container_ctx *out_ctx;
+ struct xhci_container_ctx *in_ctx;
+ struct xhci_slot_ctx *slot_ctx;
+ int slot_id = udev->slot_id;
+ unsigned think_time;
+
+ debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
+
+ /* Ignore root hubs */
+ if (usb_hub_is_root_hub(udev->dev))
+ return 0;
+
+ virt_dev = ctrl->devs[slot_id];
+ BUG_ON(!virt_dev);
+
+ out_ctx = virt_dev->out_ctx;
+ in_ctx = virt_dev->in_ctx;
+
+ ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
+ /* Initialize the input context control */
+ ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
+ ctrl_ctx->drop_flags = 0;
+
+ xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
+
+ /* slot context */
+ xhci_slot_copy(ctrl, in_ctx, out_ctx);
+ slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
+
+ /* Update hub related fields */
+ slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
+ if (hub->tt.multi && udev->speed == USB_SPEED_HIGH)
+ slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
+ slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
+ /*
+ * Set TT think time - convert from ns to FS bit times.
+ * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
+ *
+ * 0 = 8 FS bit times, 1 = 16 FS bit times,
+ * 2 = 24 FS bit times, 3 = 32 FS bit times.
+ *
+ * This field shall be 0 if the device is not a high-spped hub.
+ */
+ think_time = hub->tt.think_time;
+ if (think_time != 0)
+ think_time = (think_time / 666) - 1;
+ if (udev->speed == USB_SPEED_HIGH)
+ slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
+
+ return xhci_configure_endpoints(udev, false);
+}
+
int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
struct xhci_hcor *hcor)
{
.bulk = xhci_submit_bulk_msg,
.interrupt = xhci_submit_int_msg,
.alloc_device = xhci_alloc_device,
+ .update_hub_device = xhci_update_hub_device,
};
#endif
/* Max number of USB devices for any host controller - limit in section 6.1 */
#define MAX_HC_SLOTS 256
/* Section 5.3.3 - MaxPorts */
-#define MAX_HC_PORTS 127
+#define MAX_HC_PORTS 255
/* Up to 16 ms to halt an HC */
#define XHCI_MAX_HALT_USEC (16*1000)
#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
#define HCS_MAX_PORTS_SHIFT 24
-#define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT)
-#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
+#define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT)
+#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff)
/* HCSPARAMS2 - hcs_params2 - bitmasks */
/* bits 0:3, frames or uframes that SW needs to queue transactions
#define HCS_IST(p) (((p) >> 0) & 0xf)
/* bits 4:7, max number of Event Ring segments */
#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
+/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
-/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
-#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
+/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
+#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
/* HCSPARAMS3 - hcs_params3 - bitmasks */
/* bits 0:7, Max U1 to U0 latency for the roothub ports */
volatile uint64_t or_dcbaap;
volatile uint32_t or_config;
volatile uint32_t reserved_2[241];
- struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS];
-
- uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254];
+ struct xhci_hcor_port_regs portregs[MAX_HC_PORTS];
};
/* USBCMD - USB command - command bitmasks */
* @type: Type of context. Used to calculated offsets to contained contexts.
* @size: Size of the context data
* @bytes: The raw context data given to HW
- * @dma: dma address of the bytes
*
* Represents either a Device or Input context. Holds a pointer to the raw
- * memory used for the context (bytes) and dma address of it (dma).
+ * memory used for the context (bytes).
*/
struct xhci_container_ctx {
unsigned type;
* The Slot ID of the hub that isolates the high speed signaling from
* this low or full-speed device. '0' if attached to root hub port.
*/
-#define TT_SLOT (0xff)
+#define TT_SLOT(p) (((p) & 0xff) << 0)
/*
* The number of the downstream facing port of the high-speed hub
* '0' if the device is not low or full speed.
*/
-#define TT_PORT (0xff << 8)
+#define TT_PORT(p) (((p) & 0xff) << 8)
#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
/* dev_state bitmasks */
unsigned int erst_size;
};
+struct xhci_scratchpad {
+ u64 *sp_array;
+};
+
/*
* Each segment table entry is 4*32bits long. 1K seems like an ok size:
* (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
struct xhci_intr_reg *ir_set;
struct xhci_erst erst;
struct xhci_erst_entry entry[ERST_NUM_SEGS];
+ struct xhci_scratchpad *scratchpad;
struct xhci_virt_device *devs[MAX_HC_SLOTS];
int rootdev;
};
void xhci_slot_copy(struct xhci_ctrl *ctrl,
struct xhci_container_ctx *in_ctx,
struct xhci_container_ctx *out_ctx);
-void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, int slot_id,
- int speed, int hop_portnr);
+void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
+ struct usb_device *udev, int hop_portnr);
void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
u32 slot_id, u32 ep_index, trb_type cmd);
void xhci_acknowledge_event(struct xhci_ctrl *ctrl);
#include <errno.h>
#include <display.h>
#include <edid.h>
-#include <fdtdec.h>
#include <lcd.h>
#include <video.h>
#include <asm/gpio.h>
{
struct display_plat *disp_uc_plat;
struct dc_ctlr *dc_ctlr;
- const void *blob = gd->fdt_blob;
struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */
return ret;
}
- dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
- "reg");
- if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
+ dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+ if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
debug("dc: failed to update window\n");
return ret;
}
+ debug("%s: ready\n", __func__);
return 0;
}
#include <dm.h>
#include <div64.h>
#include <errno.h>
-#include <fdtdec.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch-tegra/dc.h>
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
- plat->base = devfdt_get_addr(dev);
+ plat->base = dev_read_addr(dev);
return 0;
}
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <malloc.h>
#include <panel.h>
+#include <syscon.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
const struct display_timing *timing)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
u32 reg_val;
- int node;
/* Use the first display controller */
debug("%s\n", __func__);
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE];
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
unsigned long dc_int_mask;
- int node;
int ret;
debug("%s\n", __func__);
/* Use the first display controller */
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
/* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node;
int ret;
- priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ priv->base = (void *)dev_read_addr(dev);
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
- if (node < 0) {
- debug("%s: Cannot find PMC\n", __func__);
- return -ENOENT;
- }
- priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
+ priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
+ if (IS_ERR(priv->pmc_base))
+ return PTR_ERR(priv->pmc_base);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);
default y if AM33XX
help
Say Y here to enable the OMAP3+ watchdog driver.
-
+
+config TANGIER_WATCHDOG
+ bool "Intel Tangier watchdog"
+ depends on INTEL_MID
+ select HW_WATCHDOG
+ help
+ This enables support for watchdog controller available on
+ Intel Tangier SoC. If you're using a board with Intel Tangier
+ SoC, say Y here.
+
config ULP_WATCHDOG
bool "i.MX7ULP watchdog"
help
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_TANGIER_WATCHDOG) += tangier_wdt.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
obj-$(CONFIG_WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <watchdog.h>
+#include <asm/scu.h>
+
+/* Hardware timeout in seconds */
+#define WDT_PRETIMEOUT 15
+#define WDT_TIMEOUT_MIN (1 + WDT_PRETIMEOUT)
+#define WDT_TIMEOUT_MAX 170
+#define WDT_DEFAULT_TIMEOUT 90
+
+#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define WATCHDOG_HEARTBEAT 60000
+#else
+#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_TIMEOUT_MSECS
+#endif
+
+enum {
+ SCU_WATCHDOG_START = 0,
+ SCU_WATCHDOG_STOP = 1,
+ SCU_WATCHDOG_KEEPALIVE = 2,
+ SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT = 3,
+};
+
+void hw_watchdog_reset(void)
+{
+ static unsigned long last;
+ unsigned long now;
+
+ if (gd->timer)
+ now = timer_get_us();
+ else
+ now = rdtsc() / 1000;
+
+ /* Do not flood SCU */
+ if (last > now)
+ last = 0;
+
+ if (unlikely((now - last) > (WDT_PRETIMEOUT / 2) * 1000000)) {
+ last = now;
+ scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE);
+ }
+}
+
+int hw_watchdog_disable(void)
+{
+ return scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_STOP);
+}
+
+void hw_watchdog_init(void)
+{
+ u32 timeout = WATCHDOG_HEARTBEAT / 1000;
+ int in_size;
+ struct ipc_wd_start {
+ u32 pretimeout;
+ u32 timeout;
+ } ipc_wd_start = { timeout - WDT_PRETIMEOUT, timeout };
+
+ /*
+ * SCU expects the input size for watchdog IPC
+ * to be based on 4 bytes
+ */
+ in_size = DIV_ROUND_UP(sizeof(ipc_wd_start), 4);
+
+ scu_ipc_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_START,
+ (u32 *)&ipc_wd_start, in_size, NULL, 0);
+}
* devices it finds.
*
* @ahci_dev: AHCI parent device
+ * @base: Base address of AHCI port
* @return 0 if OK, -ve on error
*/
-int ahci_probe_scsi(struct udevice *ahci_dev);
+int ahci_probe_scsi(struct udevice *ahci_dev, ulong base);
+
+/**
+ * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI
+ *
+ * Note that the SCSI device will itself bind block devices for any storage
+ * devices it finds.
+ *
+ * @ahci_dev: AHCI parent device
+ * @return 0 if OK, -ve on error
+ */
+int ahci_probe_scsi_pci(struct udevice *ahci_dev);
#endif
#endif
unsigned int timebase_h;
unsigned int timebase_l;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
unsigned long malloc_base; /* base address of early malloc() */
unsigned long malloc_limit; /* limit address */
unsigned long malloc_ptr; /* current address */
char vendor[40+1]; /* IDE model, SCSI Vendor */
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
/*
* For now we have a few functions which take struct blk_desc as a
* parameter. This field allows them to look up the associated
#endif
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct udevice;
/* Operations on block devices */
* @return 0 if OK, or a negative error code.
*/
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
+
+/**
+ * clk_release_all() - Disable (turn off)/Free an array of previously
+ * requested clocks.
+ *
+ * For each clock contained in the clock array, this function will check if
+ * clock has been previously requested and then will disable and free it.
+ *
+ * @clk: A clock struct array that was previously successfully
+ * requested by clk_request/get_by_*().
+ * @count Number of clock contained in the array
+ * @return zero on success, or -ve error code.
+ */
+int clk_release_all(struct clk *clk, int count);
+
#else
static inline int clk_get_by_index(struct udevice *dev, int index,
struct clk *clk)
{
return -ENOSYS;
}
+
+static inline int clk_release_all(struct clk *clk, int count)
+{
+ return -ENOSYS;
+}
+
#endif
/**
*/
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
-#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_ONENAND /* OneNAND support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_PCMCIA /* PCMCIA support */
#define CONFIG_FS_FAT
#endif
-#if defined(CONFIG_ENV_IS_IN_FAT) && !defined(CONFIG_FAT_WRITE)
-#define CONFIG_FAT_WRITE
-#endif
-
#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
!defined(CONFIG_FS_EXT4)
#define CONFIG_FS_EXT4
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_DDR_LAW 11
/* NAND */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
-#ifdef CONFIG_NANDFLASH_SIZE
-# define CONFIG_CMD_NAND
-#endif
-
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFFEC
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
-#ifdef CONFIG_NANDFLASH_SIZE
-# define CONFIG_CMD_NAND
-#endif
-
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFFEC
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/* Command line configuration */
-#undef CONFIG_CMD_NAND
-
/*
* NAND FLASH
*/
"mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
"mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_CMD_NAND 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_FSL_ELBC 1
CONFIG_SYS_NAND_BASE + 0x80000, \
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
CONFIG_SYS_NAND_BASE + 0x80000,\
CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_MAX_OOBFREE 5
#define CONFIG_USB_EHCI_PCI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_EHCI_DEVICE 0
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#if defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#if defined(CONFIG_NAND)
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#if defined(CONFIG_NAND)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_ENV_OFFSET 0x001c0000
#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#elif !defined(CONFIG_ENV_IS_NOWHERE)
-/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
#endif
/* SPI flash. */
#endif /* CONFIG_USB_AM35X */
-/* commands to include */
-
-#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#endif /* CONFIG_USB_MUSB_AM35X */
-/* commands to include */
-#define CONFIG_CMD_NAND
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
-
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* SPL USB Support */
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
/*
- * U-Boot Commands
- */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK
-#define CONFIG_CMD_NAND_TRIMFFS
-
-/*
* Memory configurations
*/
#define CONFIG_NR_DRAM_POPULATED 1
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
-/* U-Boot Commands */
-
-#define CONFIG_CMD_NAND
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
/* NAND stuff */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
/* u-boot env in sd/mmc card */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_SIZE 0x4000
#endif
#define CONFIG_BOOTP_HOSTNAME 1
/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND 1
-
-/*
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND 1
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_NAND
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
"root=/dev/mtdblock7 rw rootfstype=jffs2"
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env + linux in mmc */
-#define FAT_ENV_INTERFACE "mmc"
-/*
- * We don't specify the part number, if device 0 has partition table, it means
- * the first partition; it no partition table, then take whole device as a
- * FAT file system.
- */
-#define FAT_ENV_DEVICE_AND_PART "0"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND
-
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
+#endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
-#define CONFIG_CMD_NAND_TRIMFFS
-
-#endif
-
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=atmel_nand"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
/* Use file in FAT file to save environment */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_FILE "uboot.env"
-#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#endif
/* Let board_init_f handle the framebuffer allocation */
#undef CONFIG_FB_ADDR
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_NAND 1
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_FILE "uboot.env"
-#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \
"fatload mmc 0:1 0x22000000 zImage; " \
#define CONFIG_BOOTP_HOSTNAME
/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND
-
-/*
* define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
* NB: in this case, USB 1.1 devices won't be recognized.
*/
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#endif
+
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC 1
#define CONFIG_ATMEL_NAND_HW_PMECC 1
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_CMD_NAND_TRIMFFS
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#endif
-
/* USB */
#ifdef CONFIG_CMD_USB
#ifndef CONFIG_USB_EHCI_HCD
"bootm 0x22000000"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_FILE "uboot.env"
-#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#endif
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-/*
- * Commands still not supported in Kconfig
- */
-#define CONFIG_CMD_NAND
-
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_CMDLINE_EDITING
* Environment settings
*/
#define CONFIG_ENV_SIZE SZ_16K
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
/*
* Environment configuration
/* NAND support */
#ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x006ff000
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
-/* U-Boot Commands */
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
/* NAND */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#undef CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-#define CONFIG_CMD_NAND
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
"1m(u-boot),1m(u-boot-env)," \
"1920k(u-boot),256k(u-boot-env),"\
"4m(kernel),-(fs)"
-#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
"1920k(u-boot),256k(u-boot-env),"\
"4m(kernel),-(fs)"
-#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* USB support */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */
#endif
#define CONFIG_NAND_MXS
-#define CONFIG_CMD_NAND_TRIMFFS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
-#define CONFIG_CMD_NAND_TORTURE
/* Dynamic MTD partition support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LCD_LOGO
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
"stdout=serial\0" \
"stderr=serial\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91_WANTS_COMMON_PHY
-/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x5ff000
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
#endif
#ifdef CONFIG_USE_NAND
-#define CONFIG_CMD_NAND
-
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
/*
* Commands configuration
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
/* I2C */
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_CMD_NAND
-
/*
* USB
*/
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
-/* commands to include */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-
#undef CONFIG_SUPPORT_RAW_INITRD
/* BOOTP/DHCP options */
"stdout=serial\0" \
"stderr=serial\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
/*
* Commands configuration
*/
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_MVFS
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
- * Commands configuration
- */
-#define CONFIG_CMD_NAND
-/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
#if 0
#undef CONFIG_DM_USB
#define CONFIG_USB_XHCI_PCI
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#if !defined(CONFIG_USB_XHCI_HCD)
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
/* NAND Setup */
#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/ibmpc.h>
+
+/* Boot */
+#define CONFIG_CMD_ZBOOT
+#define CONFIG_BOOTCOMMAND "run bootcmd"
+
+/* DISK Partition support */
+#define CONFIG_RANDOM_UUID
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_AUTO_COMPLETE
+
+/* Memory */
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_PHYSMEM
+
+#define CONFIG_NR_DRAM_BANKS 3
+
+#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define CONFIG_ENV_SIZE (64 * 1024)
+#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024)
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* PCI */
+#define CONFIG_CMD_PCI
+
+/* RTC */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+#define CONFIG_RTC_MC146818
+
+#endif
#undef CONFIG_TPM_TIS_BASE_ADDRESS
#undef CONFIG_SCSI_AHCI
-#undef CONFIG_INTEL_ICH6_GPIO
#undef CONFIG_USB_EHCI_PCI
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
/* Misc. hardware drivers */
#define CONFIG_AT91_GPIO
-/* Command line configuration */
-#define CONFIG_CMD_NAND
-
#ifndef MINIMAL_LOADER
#define CONFIG_CMD_REISER
#define CONFIG_CMD_SAVES
/* Enable Time Command */
/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS \
- "stdin=serial,cros-ec-keyb\0" \
+ "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
+ "stderr=serial,vidconsole\0" \
+ "preboot=usb start\0"
#include <configs/rk3288_common.h>
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
-#define CONFIG_CMD_NAND
-
#define CONFIG_NET_RETRY_COUNT 100
* Commands configuration
*/
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */
/*
#elif defined(CONFIG_SPL_NAND_SUPPORT)
/* Enable NAND support */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Preserve environment on sd card */
#define CONFIG_ENV_SIZE 0x1000
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "1:1"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_VARS_UBOOT_CONFIG
/* Monitor Command Prompt */
* Environment settings
*/
#define CONFIG_ENV_SIZE SZ_16K
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
/*
* Environment configuration
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_NAND
/*
* mv-common.h should be defined after CMD configs since it used them
/*
* U-Boot environment setup
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMDLINE_EDITING
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
"bootm ${loadaddr} - ${fdtaddr}"
/* UBI Support */
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_MTD_PARTITIONS
/* bootcount support */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
-/*
- * U-Boot commands
- */
-#define CONFIG_CMD_NAND
-
-
#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
/* NAND stuff */
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#ifndef CONFIG_DRIVER_TI_EMAC
#endif
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_CS 0
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#define CONFIG_CMD_NAND
-
/* SPI NOR Flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 8100000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_BCH
#define CONFIG_HOSTNAME kmcoge5ne
#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
-#define CONFIG_CMD_NAND
#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH
#define CONFIG_NAND_KMETER1
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_CMD_MEMINFO
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/* MMC */
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/*
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/*
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/*
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#endif
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#endif
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-/* U-Boot Commands */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
- * U-Boot Commands
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
-/*
* Memory configurations
*/
#define CONFIG_NR_DRAM_BANKS 2
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* USB device */
#define CONFIG_USB_ETHER
/* EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
/* commands to include */
-#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Command line configuration.
- */
-
-#ifdef CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_CMD_NAND
-#endif
-
/* LED */
#define CONFIG_AT91_LED
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_SMSC_LPC47M
#define CONFIG_MISC_INIT_R
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
"stdout=vidconsole,serial\0" \
- "stderr=vidconsole,serial\0"
-
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
+ "stderr=vidconsole,serial\0" \
+ "usb_pgood_delay=40\0"
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_NET_RETRY_COUNT 50
#define CONFIG_PHY_MARVELL
-/* USB 2.0 */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
-/* USB 3.0 */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
-
-#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \
- CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
/* USB ethernet */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50
-/* USB 2.0 */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
-/* USB 3.0 */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
-
-#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \
- CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
/* USB ethernet */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
-/* U-Boot Commands */
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_CMD_NAND
-
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
-#define CONFIG_CMD_NAND
-
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_SYS_NAND_LARGEPAGE
/* EHCI driver */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_MXC
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_CMD_NAND
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* NAND flash command */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* NAND stuff */
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* NAND flash command */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* NAND stuff */
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
* to support nand, since emmc has pin conflicts with nand
*/
#ifdef CONFIG_NAND_MXS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/*
* Commands configuration
*/
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
/* USB */
#define CONFIG_USB_EHCI_EXYNOS
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
"1920k(u-boot),128k(u-boot-env),"\
"4m(kernel),-(fs)"
-#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
/*
#define CONFIG_NAND
-/* commands to include */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK
-
/*
* TWL4030
*/
#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
- * Supported U-Boot commands
- * ----------------------------------------------------------------------------
- */
-
-#define CONFIG_CMD_NAND
-
-/* ----------------------------------------------------------------------------
* Supported U-Boot features
* ----------------------------------------------------------------------------
*/
#define CONFIG_USB_OMAP3
-/* commands to include */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-
/* I2C */
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* TWL4030 */
-#define CONFIG_TWL4030_PWM
#define CONFIG_TWL4030_USB
/* Board NAND Info. */
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* commands to include */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#endif
-#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#endif
#undef CONFIG_SYS_I2C_OMAP24XX
*/
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
/* ENV related config options */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_OVERWRITE
#endif /* __CONFIG_PANDA_H */
#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
#endif
#ifdef CONFIG_USE_NAND
-#define CONFIG_CMD_NAND
-
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_NAND
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#else
#define CONFIG_ENV_OVERWRITE
/* NAND support */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_I2C_SPEED 100000
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_NAND
/* Enable NAND support */
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* SPL */
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
-/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#ifdef CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env + linux in mmc */
-#define FAT_ENV_INTERFACE "mmc"
-/*
- * We don't specify the part number, if device 0 has partition table, it means
- * the first partition; it no partition table, then take whole device as a
- * FAT file system.
- */
-#define FAT_ENV_DEVICE_AND_PART "0"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
#include "mx6_common.h"
/*
- * Console configuration
- */
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
-/*
* Hardware configuration
*/
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND 1
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND 1
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND 1
-
#define CONFIG_JFFS2_CMDLINE 1
#define CONFIG_JFFS2_NAND 1
#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_NAND
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_PL01X_SERIAL
/* USB configuration */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_USB_HOST_ETHER
* ATA/SATA support for QEMU x86 targets
* - Only legacy IDE controller is supported for QEMU '-M pc' target
* - AHCI controller is supported for QEMU '-M q35' target
- *
- * Default configuraion is to support the QEMU default x86 target
- * Undefine CONFIG_IDE to support q35 target
*/
-#ifdef CONFIG_IDE
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 4
#define CONFIG_SYS_ATA_BASE_ADDR 0
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_ATAPI
-#undef CONFIG_SCSI_AHCI
-#else
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
-#endif
-
-/* GPIO is not supported */
-#undef CONFIG_INTEL_ICH6_GPIO
-
/* SPI is not supported */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-/* xhci host */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#if defined(CONFIG_SPL_SPI_SUPPORT)
#define CONFIG_SPL_SPI_LOAD
#endif
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_RTL8152
-/* rockchip xhci host driver */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
#endif
#endif
#define CONFIG_RANDOM_UUID
+
+#ifdef CONFIG_ARM64
+#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
+#else
+#define ROOT_UUID "69DAD710-2CE4-4E3C-B16C-21A1D49ABED3;\0"
+#endif
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
"name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \
"name=atf,size=4M,uuid=${uuid_gpt_atf};" \
"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
- "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+ "name=rootfs,size=-,uuid="ROOT_UUID
#endif
/* Environment */
#define CONFIG_ENV_SIZE SZ_16K
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_PREBOOT "usb start"
#ifdef CONFIG_SYS_USE_NAND
/* Nand Flash Configs */
-#define CONFIG_CMD_NAND
#define CONFIG_JFFS2_NAND
#define MTD_NAND_FSL_NFC_SWECC 1
#define CONFIG_NAND_FSL_NFC
#endif
/* NAND flash */
-#define CONFIG_CMD_NAND
-
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_CMD_NAND_TRIMFFS
#endif
/* USB */
#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-#endif
-
/* USB device */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
-/* NAND flash */
-#undef CONFIG_CMD_NAND
-
/* I2C */
#define AT24MAC_ADDR 0x5c
#define AT24MAC_REG 0x9a
#ifdef CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env in sd card */
-#undef FAT_ENV_DEVICE_AND_PART
#undef CONFIG_BOOTCOMMAND
-#define FAT_ENV_DEVICE_AND_PART "1"
#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \
"fatload mmc 1:1 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
#endif
/* NAND flash */
-#define CONFIG_CMD_NAND
-
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_CMD_NAND_TRIMFFS
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#endif
/* USB */
#endif
/* NAND flash */
-#define CONFIG_CMD_NAND
-
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_CMD_NAND_TRIMFFS
-#endif
#define CONFIG_PHY_MICREL_KSZ9021
#endif
/* NAND flash */
-#define CONFIG_CMD_NAND
-
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
/* NAND flash */
-#define CONFIG_CMD_NAND
-
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_KEYBOARD
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
/* Max number of NAND devices */
#define CONFIG_NAND
/* NAND support */
#ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
-
/* UBI Support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_MTD_PARTITIONS
\
"mtdparts="MTDPARTS_DEFAULT"\0"
-/* Command line & features configuration */
-
-#define CONFIG_CMD_NAND
-
-#ifdef CONFIG_MACB
-#else
-#endif /* CONFIG_MACB */
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x301000
#define CONFIG_SPL_STACK_R
/***********************************************************
* Command definition
***********************************************************/
-#undef CONFIG_CMD_NAND
-
#define CONFIG_CMD_ONENAND
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
/* Command line configuration */
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_TFTP_PORT
#define CONFIG_TFTP_TSIZE
-/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-
/* MMC */
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
#endif /* __CONFIG_H */
/*
* FPGA Driver
*/
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
#define CONFIG_FPGA_COUNT 1
#endif
-#endif
+
/*
* L4 OSC1 Timer 0
*/
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_MISC_INIT_R
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
/*
* Command support defines
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_SAVES
/*
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_STM32_FLASH
-#define CONFIG_STM32X7_SERIAL
#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_OHCI_SUNXI
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif
#ifdef CONFIG_USB_MUSB_SUNXI
#define CONFIG_ENV_ADDR 0xF0100000
#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_CMD_NAND
#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH
#define CONFIG_NAND_KMETER1
115200}
/* EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
-/* commands to include */
-#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
"1920k(u-boot),128k(u-boot-env),"\
"4m(kernel),-(fs)"
-#define CONFIG_CMD_NAND /* NAND support */
-
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND
-
-/*
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA114_COMMON_H_ */
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
/* GPU needs setup */
#define CONFIG_TEGRA_GPU
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
/* GPU needs setup */
#define CONFIG_TEGRA_GPU
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA30_COMMON_H_ */
#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
/* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_STRATIX_V
/*
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
#define CONFIG_SYS_NAND_BASE 0x8000000
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#endif
/* Now for the remaining common defines */
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Enable NAND support */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
#ifdef CONFIG_CMD_NAND
/* NAND stuff */
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-/* commands to include */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-
/* needed for ubi */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* USB */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
-
/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_NAND
-
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#endif /* CONFIG_CMD_USB */
-#if defined(CONFIG_VCT_NAND)
-#define CONFIG_CMD_NAND
-#endif
-
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_CMD_ONENAND
#endif
*/
#define CONFIG_SYS_NAND_BASE 0x61000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_ENV_OVERWRITE
/* NAND support */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
#endif
-/* USB */
-
-#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-#endif
-
/* USB device */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
-#define CONFIG_CMD_NAND
-
#define CONFIG_MXC_GPIO
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
#define CONFIG_NAND_LPC32XX_MLC
-#define CONFIG_CMD_NAND
-
/*
* GPIO
*/
/*
* Command support defines
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_SAVES
/* Filesystem support (for USB key) */
#define CONFIG_X86_REFCODE_ADDR 0xffea0000
#define CONFIG_X86_REFCODE_RUN_ADDR 0
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_SUPPORT_VFAT
-/* x86 GPIOs are accessed through a PCI device */
-#define CONFIG_INTEL_ICH6_GPIO
-
/*-----------------------------------------------------------------------
* Command line configuration.
*/
* USB configuration
*/
#define CONFIG_USB_EHCI_PCI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_USB_HOST_ETHER
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
-# define FAT_ENV_DEVICE_AND_PART "0:auto"
-# define FAT_ENV_FILE "uboot.env"
-# define FAT_ENV_INTERFACE "mmc"
#endif
#ifdef CONFIG_NAND_ARASAN
-# define CONFIG_CMD_NAND_LOCK_UNLOCK
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_SELF_INIT
# define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_USB_CABLE_CHECK
/*
* Command configuration.
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
/*
* Command configuration.
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
/*
* Command configuration.
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
/*
* Command configuration.
*/
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_NAND_ZYNQ
-#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_MTD_DEVICE
struct sf_internal_data sf;
} data;
- long (*get_medium_size)(struct dfu_entity *dfu);
+ int (*get_medium_size)(struct dfu_entity *dfu, u64 *size);
int (*read_medium)(struct dfu_entity *dfu,
u64 offset, void *buf, long *len);
u8 *i_buf;
u8 *i_buf_start;
u8 *i_buf_end;
- long r_left;
+ u64 r_left;
long b_left;
u32 bad_skip; /* for nand use */
int index, struct of_phandle_args *out_args);
/**
+ * of_count_phandle_with_args() - Count the number of phandle in a list
+ *
+ * @np: pointer to a device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @return number of phandle found, -ENOENT if
+ * @list_name does not exist, -EINVAL if a phandle was not found,
+ * @cells_name could not be found, the arguments were truncated or there
+ * were too many arguments.
+ *
+ * Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ *
+ */
+int of_count_phandle_with_args(const struct device_node *np,
+ const char *list_name, const char *cells_name);
+
+/**
* of_alias_scan() - Scan all properties of the 'aliases' node
*
* The function scans all the properties of the 'aliases' node and populates
/* Enable checks to protect against invalid calls */
#undef OF_CHECKS
+struct resource;
+
/**
* ofnode - reference to a device tree node
*
struct ofnode_phandle_args *out_args);
/**
+ * ofnode_count_phandle_with_args() - Count number of phandle in a list
+ *
+ * This function is useful to count phandles into a list.
+ * Returns number of phandle on success, on error returns appropriate
+ * errno value.
+ *
+ * @node: device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @return number of phandle on success, -ENOENT if @list_name does not
+ * exist, -EINVAL if a phandle was not found, @cells_name could not
+ * be found.
+ */
+int ofnode_count_phandle_with_args(ofnode node, const char *list_name,
+ const char *cells_name);
+
+/**
* ofnode_path() - find a node by full path
*
* @path: Full path to node, e.g. "/bus/spi@1"
*/
bool ofnode_pre_reloc(ofnode node);
+int ofnode_read_resource(ofnode node, uint index, struct resource *res);
+
#endif
return ofnode_valid(dev_ofnode(dev));
}
-/**
- * dev_read_resource() - obtain an indexed resource from a device.
- *
- * @dev: devuce to examine
- * @index index of the resource to retrieve (0 = first)
- * @res returns the resource
- * @return 0 if ok, negative on error
- */
-int dev_read_resource(struct udevice *dev, uint index, struct resource *res);
-
#ifndef CONFIG_DM_DEV_READ_INLINE
/**
* dev_read_u32_default() - read a 32-bit integer from a device's DT property
struct ofnode_phandle_args *out_args);
/**
+ * dev_count_phandle_with_args() - Return phandle number in a list
+ *
+ * This function is usefull to get phandle number contained in a property list.
+ * For example, this allows to allocate the right amount of memory to keep
+ * clock's reference contained into the "clocks" property.
+ *
+ *
+ * @dev: device whose node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ */
+
+int dev_count_phandle_with_args(struct udevice *dev, const char *list_name,
+ const char *cells_name);
+
+/**
* dev_read_addr_cells() - Get the number of address cells for a device's node
*
* This walks back up the tree to find the closest #address-cells property
* @lenp: place to put length on success
* @return pointer to property, or NULL if not found
*/
-const u32 *dev_read_prop(struct udevice *dev, const char *propname, int *lenp);
+const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp);
/**
* dev_read_alias_seq() - Get the alias sequence number of a node
*/
int dev_read_enabled(struct udevice *dev);
+/**
+ * dev_read_resource() - obtain an indexed resource from a device.
+ *
+ * @dev: devuce to examine
+ * @index index of the resource to retrieve (0 = first)
+ * @res returns the resource
+ * @return 0 if ok, negative on error
+ */
+int dev_read_resource(struct udevice *dev, uint index, struct resource *res);
+
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
static inline int dev_read_u32_default(struct udevice *dev,
out_args);
}
+static inline int dev_count_phandle_with_args(struct udevice *dev,
+ const char *list_name, const char *cells_name)
+{
+ return ofnode_count_phandle_with_args(dev_ofnode(dev), list_name,
+ cells_name);
+}
+
static inline int dev_read_addr_cells(struct udevice *dev)
{
/* NOTE: this call should walk up the parent stack */
return fdt_get_phandle(gd->fdt_blob, dev_of_offset(dev));
}
-static inline const u32 *dev_read_prop(struct udevice *dev,
- const char *propname, int *lenp)
+static inline const void *dev_read_prop(struct udevice *dev,
+ const char *propname, int *lenp)
{
return ofnode_get_property(dev_ofnode(dev), propname, lenp);
}
return fdtdec_get_is_enabled(gd->fdt_blob, dev_of_offset(dev));
}
+static inline int dev_read_resource(struct udevice *dev, uint index,
+ struct resource *res)
+{
+ return ofnode_read_resource(dev_ofnode(dev), index, res);
+}
+
#endif /* CONFIG_DM_DEV_READ_INLINE */
/**
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __DT_STTUCTS
-#define __DT_STTUCTS
+#ifndef __DT_STRUCTS
+#define __DT_STRUCTS
/* These structures may only be used in SPL */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
#define EFI_BITS_PER_LONG 64
#endif
-#define EFI_SUCCESS 0
-#define EFI_LOAD_ERROR (1 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_INVALID_PARAMETER (2 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_UNSUPPORTED (3 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_BAD_BUFFER_SIZE (4 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_BUFFER_TOO_SMALL (5 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_NOT_READY (6 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_DEVICE_ERROR (7 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_WRITE_PROTECTED (8 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_OUT_OF_RESOURCES (9 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_NOT_FOUND (14 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_ACCESS_DENIED (15 | (1UL << (EFI_BITS_PER_LONG - 1)))
-#define EFI_SECURITY_VIOLATION (26 | (1UL << (EFI_BITS_PER_LONG - 1)))
+/* Bit mask for EFI status code with error */
+#define EFI_ERROR_MASK (1UL << (EFI_BITS_PER_LONG - 1))
+/* Status codes returned by EFI protocols */
+#define EFI_SUCCESS 0
+#define EFI_LOAD_ERROR (EFI_ERROR_MASK | 1)
+#define EFI_INVALID_PARAMETER (EFI_ERROR_MASK | 2)
+#define EFI_UNSUPPORTED (EFI_ERROR_MASK | 3)
+#define EFI_BAD_BUFFER_SIZE (EFI_ERROR_MASK | 4)
+#define EFI_BUFFER_TOO_SMALL (EFI_ERROR_MASK | 5)
+#define EFI_NOT_READY (EFI_ERROR_MASK | 6)
+#define EFI_DEVICE_ERROR (EFI_ERROR_MASK | 7)
+#define EFI_WRITE_PROTECTED (EFI_ERROR_MASK | 8)
+#define EFI_OUT_OF_RESOURCES (EFI_ERROR_MASK | 9)
+#define EFI_VOLUME_CORRUPTED (EFI_ERROR_MASK | 10)
+#define EFI_VOLUME_FULL (EFI_ERROR_MASK | 11)
+#define EFI_NO_MEDIA (EFI_ERROR_MASK | 12)
+#define EFI_MEDIA_CHANGED (EFI_ERROR_MASK | 13)
+#define EFI_NOT_FOUND (EFI_ERROR_MASK | 14)
+#define EFI_ACCESS_DENIED (EFI_ERROR_MASK | 15)
+#define EFI_NO_RESPONSE (EFI_ERROR_MASK | 16)
+#define EFI_NO_MAPPING (EFI_ERROR_MASK | 17)
+#define EFI_TIMEOUT (EFI_ERROR_MASK | 18)
+#define EFI_NOT_STARTED (EFI_ERROR_MASK | 19)
+#define EFI_ALREADY_STARTED (EFI_ERROR_MASK | 20)
+#define EFI_ABORTED (EFI_ERROR_MASK | 21)
+#define EFI_ICMP_ERROR (EFI_ERROR_MASK | 22)
+#define EFI_TFTP_ERROR (EFI_ERROR_MASK | 23)
+#define EFI_PROTOCOL_ERROR (EFI_ERROR_MASK | 24)
+#define EFI_INCOMPATIBLE_VERSION (EFI_ERROR_MASK | 25)
+#define EFI_SECURITY_VIOLATION (EFI_ERROR_MASK | 26)
+#define EFI_CRC_ERROR (EFI_ERROR_MASK | 27)
+#define EFI_END_OF_MEDIA (EFI_ERROR_MASK | 28)
+#define EFI_END_OF_FILE (EFI_ERROR_MASK | 31)
+#define EFI_INVALID_LANGUAGE (EFI_ERROR_MASK | 32)
+#define EFI_COMPROMISED_DATA (EFI_ERROR_MASK | 33)
+#define EFI_IP_ADDRESS_CONFLICT (EFI_ERROR_MASK | 34)
+#define EFI_HTTP_ERROR (EFI_ERROR_MASK | 35)
typedef unsigned long efi_status_t;
typedef u64 efi_physical_addr_t;
#endif
/* Types and defines for EFI CreateEvent */
-enum efi_event_type {
+enum efi_timer_delay {
EFI_TIMER_STOP = 0,
EFI_TIMER_PERIODIC = 1,
EFI_TIMER_RELATIVE = 2
};
-#define EVT_NOTIFY_WAIT 0x00000100
-#define EVT_NOTIFY_SIGNAL 0x00000200
+#define UINTN size_t
+
+#define EVT_TIMER 0x80000000
+#define EVT_RUNTIME 0x40000000
+#define EVT_NOTIFY_WAIT 0x00000100
+#define EVT_NOTIFY_SIGNAL 0x00000200
+#define EVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201
+#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202
+
+#define TPL_APPLICATION 0x04
+#define TPL_CALLBACK 0x08
+#define TPL_NOTIFY 0x10
+#define TPL_HIGH_LEVEL 0x1F
+
+struct efi_event;
/* EFI Boot Services table */
struct efi_boot_services {
struct efi_table_hdr hdr;
- efi_status_t (EFIAPI *raise_tpl)(unsigned long new_tpl);
- void (EFIAPI *restore_tpl)(unsigned long old_tpl);
+ efi_status_t (EFIAPI *raise_tpl)(UINTN new_tpl);
+ void (EFIAPI *restore_tpl)(UINTN old_tpl);
efi_status_t (EFIAPI *allocate_pages)(int, int, unsigned long,
efi_physical_addr_t *);
efi_status_t (EFIAPI *allocate_pool)(int, unsigned long, void **);
efi_status_t (EFIAPI *free_pool)(void *);
- efi_status_t (EFIAPI *create_event)(enum efi_event_type type,
- unsigned long notify_tpl,
- void (EFIAPI *notify_function) (void *event,
- void *context),
- void *notify_context, void **event);
- efi_status_t (EFIAPI *set_timer)(void *event, int type,
- uint64_t trigger_time);
+ efi_status_t (EFIAPI *create_event)(uint32_t type,
+ UINTN notify_tpl,
+ void (EFIAPI *notify_function) (
+ struct efi_event *event,
+ void *context),
+ void *notify_context, struct efi_event **event);
+ efi_status_t (EFIAPI *set_timer)(struct efi_event *event,
+ enum efi_timer_delay type,
+ uint64_t trigger_time);
efi_status_t (EFIAPI *wait_for_event)(unsigned long number_of_events,
- void *event, unsigned long *index);
- efi_status_t (EFIAPI *signal_event)(void *event);
- efi_status_t (EFIAPI *close_event)(void *event);
- efi_status_t (EFIAPI *check_event)(void *event);
-
+ struct efi_event **event, unsigned long *index);
+ efi_status_t (EFIAPI *signal_event)(struct efi_event *event);
+ efi_status_t (EFIAPI *close_event)(struct efi_event *event);
+ efi_status_t (EFIAPI *check_event)(struct efi_event *event);
+#define EFI_NATIVE_INTERFACE 0x00000000
efi_status_t (EFIAPI *install_protocol_interface)(
void **handle, efi_guid_t *protocol,
int protocol_interface_type, void *protocol_interface);
void **);
void *reserved;
efi_status_t (EFIAPI *register_protocol_notify)(
- efi_guid_t *protocol, void *event,
+ efi_guid_t *protocol, struct efi_event *event,
void **registration);
efi_status_t (EFIAPI *locate_handle)(
enum efi_locate_search_type search_type,
bool cursor_visible;
};
+
+#define EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID \
+ EFI_GUID(0x387477c2, 0x69c7, 0x11d2, \
+ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
struct efi_simple_text_output_protocol {
void *reset;
efi_status_t (EFIAPI *output_string)(
s16 unicode_char;
};
+#define EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID \
+ EFI_GUID(0x387477c1, 0x69c7, 0x11d2, \
+ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
struct efi_simple_input_interface {
efi_status_t(EFIAPI *reset)(struct efi_simple_input_interface *this,
bool ExtendedVerification);
efi_status_t(EFIAPI *read_key_stroke)(
struct efi_simple_input_interface *this,
struct efi_input_key *key);
- void *wait_for_key;
+ struct efi_event *wait_for_key;
};
#define CONSOLE_CONTROL_GUID \
uint16_t *password);
};
+#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \
+ EFI_GUID(0x8b843e20, 0x8132, 0x4852, \
+ 0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c)
+
+struct efi_device_path_protocol
+{
+ uint8_t type;
+ uint8_t sub_type;
+ uint16_t length;
+ uint8_t data[];
+};
+
+struct efi_device_path_to_text_protocol
+{
+ uint16_t *(EFIAPI *convert_device_node_to_text)(
+ struct efi_device_path_protocol *device_node,
+ bool display_only,
+ bool allow_shortcuts);
+ uint16_t *(EFIAPI *convert_device_path_to_text)(
+ struct efi_device_path_protocol *device_path,
+ bool display_only,
+ bool allow_shortcuts);
+};
+
#define EFI_GOP_GUID \
EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \
0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a)
#include <linux/list.h>
+int __efi_entry_check(void);
+int __efi_exit_check(void);
+const char *__efi_nesting_inc(void);
+const char *__efi_nesting_dec(void);
+
+/*
+ * Enter the u-boot world from UEFI:
+ */
#define EFI_ENTRY(format, ...) do { \
- efi_restore_gd(); \
- debug("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
+ assert(__efi_entry_check()); \
+ debug("%sEFI: Entry %s(" format ")\n", __efi_nesting_inc(), \
+ __func__, ##__VA_ARGS__); \
} while(0)
-#define EFI_EXIT(ret) efi_exit_func(ret);
+/*
+ * Exit the u-boot world back to UEFI:
+ */
+#define EFI_EXIT(ret) ({ \
+ efi_status_t _r = ret; \
+ debug("%sEFI: Exit: %s: %u\n", __efi_nesting_dec(), \
+ __func__, (u32)(_r & ~EFI_ERROR_MASK)); \
+ assert(__efi_exit_check()); \
+ _r; \
+ })
+
+/*
+ * Callback into UEFI world from u-boot:
+ */
+#define EFI_CALL(exp) do { \
+ debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \
+ assert(__efi_exit_check()); \
+ exp; \
+ assert(__efi_entry_check()); \
+ debug("%sEFI: Return From: %s\n", __efi_nesting_dec(), #exp); \
+ } while(0)
extern struct efi_runtime_services efi_runtime_services;
extern struct efi_system_table systab;
extern const struct efi_simple_text_output_protocol efi_con_out;
-extern const struct efi_simple_input_interface efi_con_in;
+extern struct efi_simple_input_interface efi_con_in;
extern const struct efi_console_control_protocol efi_console_control;
+extern const struct efi_device_path_to_text_protocol efi_device_path_to_text;
extern const efi_guid_t efi_guid_console_control;
extern const efi_guid_t efi_guid_device_path;
extern const efi_guid_t efi_guid_loaded_image;
+extern const efi_guid_t efi_guid_device_path_to_text_protocol;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
/*
- * While UEFI objects can have callbacks, you can also call functions on
- * protocols (classes) themselves. This struct maps a protocol GUID to its
- * interface (usually a struct with callback functions).
- */
-struct efi_class_map {
- const efi_guid_t *guid;
- const void *interface;
-};
-
-/*
* When the UEFI payload wants to open a protocol on an object to get its
* interface (usually a struct with callback functions), this struct maps the
- * protocol GUID to the respective protocol handler open function for that
- * object protocol combination.
- */
+ * protocol GUID to the respective protocol interface */
struct efi_handler {
const efi_guid_t *guid;
- efi_status_t (EFIAPI *open)(void *handle,
- efi_guid_t *protocol, void **protocol_interface,
- void *agent_handle, void *controller_handle,
- uint32_t attributes);
+ void *protocol_interface;
};
/*
struct efi_object {
/* Every UEFI object is part of a global object list */
struct list_head link;
- /* We support up to 4 "protocols" an object can be accessed through */
- struct efi_handler protocols[4];
+ /* We support up to 8 "protocols" an object can be accessed through */
+ struct efi_handler protocols[8];
/* The object spawner can either use this for data or as identifier */
void *handle;
};
+#define EFI_PROTOCOL_OBJECT(_guid, _protocol) (struct efi_object){ \
+ .protocols = {{ \
+ .guid = &(_guid), \
+ .protocol_interface = (void *)(_protocol), \
+ }}, \
+ .handle = (void *)(_protocol), \
+}
+
+/**
+ * struct efi_event
+ *
+ * @type: Type of event, see efi_create_event
+ * @notify_tpl: Task priority level of notifications
+ * @trigger_time: Period of the timer
+ * @trigger_next: Next time to trigger the timer
+ * @nofify_function: Function to call when the event is triggered
+ * @notify_context: Data to be passed to the notify function
+ * @trigger_type: Type of timer, see efi_set_timer
+ * @signaled: The notify function was already called
+ */
+struct efi_event {
+ uint32_t type;
+ UINTN notify_tpl;
+ void (EFIAPI *notify_function)(struct efi_event *event, void *context);
+ void *notify_context;
+ u64 trigger_next;
+ u64 trigger_time;
+ enum efi_timer_delay trigger_type;
+ int signaled;
+};
+
+
/* This list contains all UEFI objects we know of */
extern struct list_head efi_obj_list;
+/* Called by bootefi to make console interface available */
+int efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
int efi_disk_register(void);
/* Called by bootefi to make GOP (graphical) interface available */
/* Called by networking code to memorize the dhcp ack package */
void efi_net_set_dhcp_ack(void *pkt, int len);
-/*
- * Stub implementation for a protocol opener that just returns the handle as
- * interface
- */
-efi_status_t EFIAPI efi_return_handle(void *handle,
- efi_guid_t *protocol, void **protocol_interface,
- void *agent_handle, void *controller_handle,
- uint32_t attributes);
/* Called from places to check whether a timer expired */
void efi_timer_check(void);
/* PE loader implementation */
void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info);
/* Called once to store the pristine gd pointer */
void efi_save_gd(void);
-/* Called from EFI_ENTRY on callback entry to put gd into the gd register */
+/* Special case handler for error/abort that just tries to dtrt to get
+ * back to u-boot world */
void efi_restore_gd(void);
-/* Called from EFI_EXIT on callback exit to restore the gd register */
-efi_status_t efi_exit_func(efi_status_t ret);
/* Call this to relocate the runtime section to an address space */
void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
/* Call this to set the current device name */
void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
+/* Call this to create an event */
+efi_status_t efi_create_event(uint32_t type, UINTN notify_tpl,
+ void (EFIAPI *notify_function) (
+ struct efi_event *event,
+ void *context),
+ void *notify_context, struct efi_event **event);
+/* Call this to set a timer */
+efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
+ uint64_t trigger_time);
+/* Call this to signal an event */
+void efi_signal_event(struct efi_event *event);
/* Generic EFI memory allocator, call this to get memory */
void *efi_alloc(uint64_t len, int memory_type);
*(unicode++) = *(ascii++);
}
+static inline int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2)
+{
+ return memcmp(g1, g2, sizeof(efi_guid_t));
+}
+
/*
* Use these to indicate that your code / data should go into the EFI runtime
* section and thus still be available when the OS is running
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
- COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
- COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */
- COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
- COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
- COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
- COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
/* Tegra124 XUSB pad controller */
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
int (*power_off)(struct phy *phy);
};
+#ifdef CONFIG_PHY
/**
* generic_phy_init() - initialize the PHY port
int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
struct phy *phy);
+#else /* CONFIG_PHY */
+
+static inline int generic_phy_init(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_exit(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_reset(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_power_on(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_power_off(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_get_by_index(struct udevice *user, int index,
+ struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
+ struct phy *phy)
+{
+ return 0;
+}
+
+#endif /* CONFIG_PHY */
+
+/**
+ * generic_phy_valid() - check if PHY port is valid
+ *
+ * @phy: the PHY port to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool generic_phy_valid(struct phy *phy)
+{
+ return phy->dev != NULL;
+}
+
#endif /*__GENERIC_PHY_H */
/* forward decl. */
struct mmc;
-#ifdef CONFIG_DM_MMC_OPS
+#if CONFIG_IS_ENABLED(DM_MMC_OPS)
struct dm_mmc_ops {
/**
* send_cmd() - Send a command to the MMC device
struct mmc_config {
const char *name;
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
const struct mmc_ops *ops;
#endif
uint host_caps;
* TODO struct mmc should be in mmc_private but it's hard to fix right now
*/
struct mmc {
-#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(BLK)
struct list_head link;
#endif
const struct mmc_config *cfg; /* provided configuration */
u64 capacity_gp[4];
u64 enh_user_start;
u64 enh_user_size;
-#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(BLK)
struct blk_desc block_dev;
#endif
char op_cond_pending; /* 1 if we are waiting on an op_cond command */
char init_in_progress; /* 1 if we have done mmc_start_init() */
char preinit; /* start init as early as possible */
int ddr_mode;
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev; /* Device for this MMC controller */
#endif
};
int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
enum mmc_hwpart_conf_mode mode);
-#ifndef CONFIG_DM_MMC_OPS
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
int mmc_getcd(struct mmc *mmc);
int board_mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
int mmc_get_env_dev(void);
-struct pci_device_id;
-
-/**
- * pci_mmc_init() - set up PCI MMC devices
- *
- * This finds all the matching PCI IDs and sets them up as MMC devices.
- *
- * @name: Name to use for devices
- * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
- */
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
-
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
int os_get_filesize(const char *fname, loff_t *size);
/**
- * Write a character to the controlling OS terminal
- *
- * This bypasses the U-Boot console support and writes directly to the OS
- * stdout file descriptor.
- *
- * @param ch Character to write
- */
-void os_putc(int ch);
-
-/**
- * Write a string to the controlling OS terminal
- *
- * This bypasses the U-Boot console support and writes directly to the OS
- * stdout file descriptor.
- *
- * @param str String to write (note that \n is not appended)
- */
-void os_puts(const char *str);
-
-/**
* Write the sandbox RAM buffer to a existing file
*
* @param fname Filename to write memory to (simple binary format)
#ifndef __POWER_AS3722_H__
#define __POWER_AS3722_H__
-#include <asm/types.h>
-
#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
#define AS3722_GPIO_INVERT (1 << 1)
-struct udevice;
+#define AS3722_DEVICE_ID 0x0c
+#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
+#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
+#define AS3722_SD_CONTROL 0x4d
+#define AS3722_LDO_CONTROL 0x4e
+#define AS3722_ASIC_ID1 0x90
+#define AS3722_ASIC_ID2 0x91
+
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_SIGNAL_OUT 0x20
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
-int as3722_init(struct udevice **devp);
-int as3722_sd_enable(struct udevice *pmic, unsigned int sd);
-int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value);
-int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo);
-int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value);
-int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
- unsigned long flags);
-int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
- unsigned int level);
-int as3722_read(struct udevice *pmic, u8 reg, u8 *value);
-int as3722_write(struct udevice *pmic, u8 reg, u8 value);
-int as3722_get(struct udevice **devp);
+int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value);
#endif /* __POWER_AS3722_H__ */
#define PALMAS_LDO_VOLT_MAX 3300000
#define PALMAS_LDO_MODE_MASK 0x1
#define PALMAS_LDO_STATUS_MASK 0x10
+#define PALMAS_LDO_BYPASS_EN 0x40
struct reset_ctl *reset_ctl);
/**
+ * reset_request - Request a reset signal.
+ *
+ * @reset_ctl: A reset control struct.
+ *
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_request(struct reset_ctl *reset_ctl);
+
+/**
* reset_free - Free a previously requested reset signal.
*
* @reset_ctl: A reset control struct that was previously successfully
*/
int reset_deassert(struct reset_ctl *reset_ctl);
+/**
+ * reset_release_all - Assert/Free an array of previously requested resets.
+ *
+ * For each reset contained in the reset array, this function will check if
+ * reset has been previously requested and then will assert and free it.
+ *
+ * @reset_ctl: A reset struct array that was previously successfully
+ * requested by reset_get_by_*().
+ * @count Number of reset contained in the array
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_release_all(struct reset_ctl *reset_ctl, int count);
#else
static inline int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl)
{
return 0;
}
+
+static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
+{
+ return 0;
+}
+
#endif
#endif
#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */
#define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */
+#define DEV_FLAGS_DM 0x00000004 /* Device priv is a struct udevice * */
/* Device information */
struct stdio_dev {
unsigned short wHubChange;
} __attribute__ ((packed));
+/*
+ * Hub Device descriptor
+ * USB Hub class device protocols
+ */
+#define USB_HUB_PR_FS 0 /* Full speed hub */
+#define USB_HUB_PR_HS_NO_TT 0 /* Hi-speed hub without TT */
+#define USB_HUB_PR_HS_SINGLE_TT 1 /* Hi-speed hub with single TT */
+#define USB_HUB_PR_HS_MULTI_TT 2 /* Hi-speed hub with multiple TT */
+#define USB_HUB_PR_SS 3 /* Super speed hub */
+
+/* Transaction Translator Think Times, in bits */
+#define HUB_TTTT_8_BITS 0x00
+#define HUB_TTTT_16_BITS 0x20
+#define HUB_TTTT_24_BITS 0x40
+#define HUB_TTTT_32_BITS 0x60
/* Hub descriptor */
struct usb_hub_descriptor {
unsigned short wHubCharacteristics;
unsigned char bPwrOn2PwrGood;
unsigned char bHubContrCurrent;
- unsigned char DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
- unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
- /* DeviceRemovable and PortPwrCtrlMask want to be variable-length
- bitmaps that hold max 255 entries. (bit0 is ignored) */
+ /* 2.0 and 3.0 hubs differ here */
+ union {
+ struct {
+ /* add 1 bit for hub status change; round to bytes */
+ __u8 DeviceRemovable[(USB_MAXCHILDREN + 1 + 7) / 8];
+ __u8 PortPowerCtrlMask[(USB_MAXCHILDREN + 1 + 7) / 8];
+ } __attribute__ ((packed)) hs;
+
+ struct {
+ __u8 bHubHdrDecLat;
+ __le16 wHubDelay;
+ __le16 DeviceRemovable;
+ } __attribute__ ((packed)) ss;
+ } u;
} __attribute__ ((packed));
ulong connect_timeout; /* Device connection timeout in ms */
ulong query_delay; /* Device query delay in ms */
int overcurrent_count[USB_MAXCHILDREN]; /* Over-current counter */
+ int hub_depth; /* USB 3.0 hub depth */
+ struct usb_tt tt; /* Transaction Translator */
};
#ifdef CONFIG_DM_USB
* reset_root_port() - Reset usb root port
*/
int (*reset_root_port)(struct udevice *bus, struct usb_device *udev);
+
+ /**
+ * update_hub_device() - Update HCD's internal representation of hub
+ *
+ * After a hub descriptor is fetched, notify HCD so that its internal
+ * representation of this hub can be updated (xHCI)
+ */
+ int (*update_hub_device)(struct udevice *bus, struct usb_device *udev);
};
#define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops)
struct usb_device *parent);
/**
+ * usb_hub_is_root_hub() - Test whether a hub device is root hub or not
+ *
+ * @hub: USB hub device to test
+ * @return: true if the hub device is root hub, false otherwise.
+ */
+bool usb_hub_is_root_hub(struct udevice *hub);
+
+/**
* usb_hub_scan() - Scan a hub and find its devices
*
* @hub: Hub device to scan
int usb_hub_probe(struct usb_device *dev, int ifnum);
void usb_hub_reset(void);
-/**
- * legacy_hub_port_reset() - reset a port given its usb_device pointer
- *
- * Reset a hub port and see if a device is present on that port, providing
- * sufficient time for it to show itself. The port status is returned.
- *
- * With driver model this moves to hub_port_reset() and is passed a struct
- * udevice.
- *
- * @dev: USB device to reset
- * @port: Port number to reset (note ports are numbered from 0 here)
- * @portstat: Returns port status
- */
-int legacy_hub_port_reset(struct usb_device *dev, int port,
- unsigned short *portstat);
-
-int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat);
-
/*
* usb_find_usb2_hub_address_port() - Get hub address and port for TT setting
*
int usb_alloc_device(struct usb_device *dev);
/**
+ * update_hub_device() - Update HCD's internal representation of hub
+ *
+ * After a hub descriptor is fetched, notify HCD so that its internal
+ * representation of this hub can be updated.
+ *
+ * @dev: Hub device
+ * @return 0 if OK, -ve on error
+ */
+int usb_update_hub_device(struct usb_device *dev);
+
+/**
* usb_emul_setup_device() - Set up a new USB device emulation
*
* This is normally called when a new emulation device is bound. It tells
* @desc_list: List of points or USB descriptors, terminated by NULL.
* The first entry must be struct usb_device_descriptor,
* and others follow on after that.
- * @return 0 if OK, -ve on error
+ * @return 0 if OK, -ENOSYS if not implemented, other -ve on error
*/
int usb_emul_setup_device(struct udevice *dev, int maxpacketsize,
struct usb_string *strings, void **desc_list);
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
+#define USB_DT_SS_HUB (USB_TYPE_CLASS | 0x0a)
/* Descriptor sizes per descriptor type */
#define USB_DT_DEVICE_SIZE 18
/*
* Changes to wPortStatus bit field in USB 3.0
- * See USB 3.0 spec Table 10-11
+ * See USB 3.0 spec Table 10-10
*/
#define USB_SS_PORT_STAT_LINK_STATE 0x01e0
#define USB_SS_PORT_STAT_POWER 0x0200
#define USB_SS_PORT_STAT_SPEED 0x1c00
#define USB_SS_PORT_STAT_SPEED_5GBPS 0x0000
+/* Bits that are the same from USB 2.0 */
+#define USB_SS_PORT_STAT_MASK (USB_PORT_STAT_CONNECTION | \
+ USB_PORT_STAT_ENABLE | \
+ USB_PORT_STAT_OVERCURRENT | \
+ USB_PORT_STAT_RESET)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
+#define HUB_CHAR_TTTT 0x0060 /* TT Think Time mask */
/*
* Hub Status & Hub Change bit masks
/* Mask for wIndex in get/set port feature */
#define USB_HUB_PORT_MASK 0xf
+/* Hub class request codes */
+#define USB_REQ_SET_HUB_DEPTH 0x0c
+
+/*
+ * As of USB 2.0, full/low speed devices are segregated into trees.
+ * One type grows from USB 1.1 host controllers (OHCI, UHCI etc).
+ * The other type grows from high speed hubs when they connect to
+ * full/low speed devices using "Transaction Translators" (TTs).
+ */
+struct usb_tt {
+ bool multi; /* true means one TT per port */
+ unsigned think_time; /* think time in ns */
+};
+
/*
* CBI style
*/
DEFINE(GD_SIZE, sizeof(struct global_data));
DEFINE(GD_BD, offsetof(struct global_data, bd));
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
return ret;
memset(gd, '\0', sizeof(*gd));
- gd->malloc_base = (ulong)efi_malloc(priv, CONFIG_SYS_MALLOC_F_LEN,
+ gd->malloc_base = (ulong)efi_malloc(priv, CONFIG_VAL(SYS_MALLOC_F_LEN),
&ret);
if (!gd->malloc_base)
return ret;
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
-obj-y += efi_memory.o
+obj-y += efi_memory.o efi_device_path_to_text.o
obj-$(CONFIG_LCD) += efi_gop.o
+obj-$(CONFIG_DM_VIDEO) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
obj-$(CONFIG_NET) += efi_net.o
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
static volatile void *efi_gd, *app_gd;
#endif
+static int entry_count;
+static int nesting_level;
+
+/* Called on every callback entry */
+int __efi_entry_check(void)
+{
+ int ret = entry_count++ == 0;
+#ifdef CONFIG_ARM
+ assert(efi_gd);
+ app_gd = gd;
+ gd = efi_gd;
+#endif
+ return ret;
+}
+
+/* Called on every callback exit */
+int __efi_exit_check(void)
+{
+ int ret = --entry_count == 0;
+#ifdef CONFIG_ARM
+ gd = app_gd;
+#endif
+ return ret;
+}
+
/* Called from do_bootefi_exec() */
void efi_save_gd(void)
{
#endif
}
-/* Called on every callback entry */
+/*
+ * Special case handler for error/abort that just forces things back
+ * to u-boot world so we can dump out an abort msg, without any care
+ * about returning back to UEFI world.
+ */
void efi_restore_gd(void)
{
#ifdef CONFIG_ARM
/* Only restore if we're already in EFI context */
if (!efi_gd)
return;
-
- if (gd != efi_gd)
- app_gd = gd;
gd = efi_gd;
#endif
}
-/* Called on every callback exit */
-efi_status_t efi_exit_func(efi_status_t ret)
+/*
+ * Two spaces per indent level, maxing out at 10.. which ought to be
+ * enough for anyone ;-)
+ */
+static const char *indent_string(int level)
{
-#ifdef CONFIG_ARM
- gd = app_gd;
-#endif
+ const char *indent = " ";
+ const int max = strlen(indent);
+ level = min(max, level * 2);
+ return &indent[max - level];
+}
+
+const char *__efi_nesting_inc(void)
+{
+ return indent_string(nesting_level++);
+}
+const char *__efi_nesting_dec(void)
+{
+ return indent_string(--nesting_level);
+}
+
+/* Low 32 bit */
+#define EFI_LOW32(a) (a & 0xFFFFFFFFULL)
+/* High 32 bit */
+#define EFI_HIGH32(a) (a >> 32)
+
+/*
+ * 64bit division by 10 implemented as multiplication by 1 / 10
+ *
+ * Decimals of one tenth: 0x1 / 0xA = 0x0.19999...
+ */
+#define EFI_TENTH 0x199999999999999A
+static u64 efi_div10(u64 a)
+{
+ u64 prod;
+ u64 rem;
+ u64 ret;
+
+ ret = EFI_HIGH32(a) * EFI_HIGH32(EFI_TENTH);
+ prod = EFI_HIGH32(a) * EFI_LOW32(EFI_TENTH);
+ rem = EFI_LOW32(prod);
+ ret += EFI_HIGH32(prod);
+ prod = EFI_LOW32(a) * EFI_HIGH32(EFI_TENTH);
+ rem += EFI_LOW32(prod);
+ ret += EFI_HIGH32(prod);
+ prod = EFI_LOW32(a) * EFI_LOW32(EFI_TENTH);
+ rem += EFI_HIGH32(prod);
+ ret += EFI_HIGH32(rem);
+ /* Round to nearest integer */
+ if (rem >= (1 << 31))
+ ++ret;
return ret;
}
-static efi_status_t efi_unsupported(const char *funcname)
+void efi_signal_event(struct efi_event *event)
{
- debug("EFI: App called into unimplemented function %s\n", funcname);
- return EFI_EXIT(EFI_UNSUPPORTED);
+ if (event->signaled)
+ return;
+ event->signaled = 1;
+ if (event->type & EVT_NOTIFY_SIGNAL) {
+ EFI_CALL(event->notify_function(event, event->notify_context));
+ }
}
-static int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2)
+static efi_status_t efi_unsupported(const char *funcname)
{
- return memcmp(g1, g2, sizeof(efi_guid_t));
+ debug("EFI: App called into unimplemented function %s\n", funcname);
+ return EFI_EXIT(EFI_UNSUPPORTED);
}
-static unsigned long EFIAPI efi_raise_tpl(unsigned long new_tpl)
+static unsigned long EFIAPI efi_raise_tpl(UINTN new_tpl)
{
- EFI_ENTRY("0x%lx", new_tpl);
+ EFI_ENTRY("0x%zx", new_tpl);
return EFI_EXIT(0);
}
-static void EFIAPI efi_restore_tpl(unsigned long old_tpl)
+static void EFIAPI efi_restore_tpl(UINTN old_tpl)
{
- EFI_ENTRY("0x%lx", old_tpl);
- EFI_EXIT(efi_unsupported(__func__));
+ EFI_ENTRY("0x%zx", old_tpl);
+ efi_unsupported(__func__);
}
static efi_status_t EFIAPI efi_allocate_pages_ext(int type, int memory_type,
}
/*
- * Our event capabilities are very limited. Only support a single
- * event to exist, so we don't need to maintain lists.
+ * Our event capabilities are very limited. Only a small limited
+ * number of events is allowed to coexist.
*/
-static struct {
- enum efi_event_type type;
- u32 trigger_type;
- u32 trigger_time;
- u64 trigger_next;
- unsigned long notify_tpl;
- void (EFIAPI *notify_function) (void *event, void *context);
- void *notify_context;
-} efi_event = {
- /* Disable timers on bootup */
- .trigger_next = -1ULL,
-};
+static struct efi_event efi_events[16];
-static efi_status_t EFIAPI efi_create_event(
- enum efi_event_type type, ulong notify_tpl,
- void (EFIAPI *notify_function) (void *event,
- void *context),
- void *notify_context, void **event)
+efi_status_t efi_create_event(uint32_t type, UINTN notify_tpl,
+ void (EFIAPI *notify_function) (
+ struct efi_event *event,
+ void *context),
+ void *notify_context, struct efi_event **event)
{
- EFI_ENTRY("%d, 0x%lx, %p, %p", type, notify_tpl, notify_function,
- notify_context);
- if (efi_event.notify_function) {
- /* We only support one event at a time */
- return EFI_EXIT(EFI_OUT_OF_RESOURCES);
- }
+ int i;
if (event == NULL)
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
if ((type & EVT_NOTIFY_SIGNAL) && (type & EVT_NOTIFY_WAIT))
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
if ((type & (EVT_NOTIFY_SIGNAL|EVT_NOTIFY_WAIT)) &&
notify_function == NULL)
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
- efi_event.type = type;
- efi_event.notify_tpl = notify_tpl;
- efi_event.notify_function = notify_function;
- efi_event.notify_context = notify_context;
- *event = &efi_event;
+ for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
+ if (efi_events[i].type)
+ continue;
+ efi_events[i].type = type;
+ efi_events[i].notify_tpl = notify_tpl;
+ efi_events[i].notify_function = notify_function;
+ efi_events[i].notify_context = notify_context;
+ /* Disable timers on bootup */
+ efi_events[i].trigger_next = -1ULL;
+ efi_events[i].signaled = 0;
+ *event = &efi_events[i];
+ return EFI_SUCCESS;
+ }
+ return EFI_OUT_OF_RESOURCES;
+}
- return EFI_EXIT(EFI_SUCCESS);
+static efi_status_t EFIAPI efi_create_event_ext(
+ uint32_t type, UINTN notify_tpl,
+ void (EFIAPI *notify_function) (
+ struct efi_event *event,
+ void *context),
+ void *notify_context, struct efi_event **event)
+{
+ EFI_ENTRY("%d, 0x%zx, %p, %p", type, notify_tpl, notify_function,
+ notify_context);
+ return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function,
+ notify_context, event));
}
+
/*
* Our timers have to work without interrupts, so we check whenever keyboard
* input or disk accesses happen if enough time elapsed for it to fire.
*/
void efi_timer_check(void)
{
+ int i;
u64 now = timer_get_us();
- if (now >= efi_event.trigger_next) {
- /* Triggering! */
- if (efi_event.trigger_type == EFI_TIMER_PERIODIC)
- efi_event.trigger_next += efi_event.trigger_time / 10;
- if (efi_event.type & (EVT_NOTIFY_WAIT | EVT_NOTIFY_SIGNAL))
- efi_event.notify_function(&efi_event,
- efi_event.notify_context);
+ for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
+ if (!efi_events[i].type ||
+ !(efi_events[i].type & EVT_TIMER) ||
+ efi_events[i].trigger_type == EFI_TIMER_STOP ||
+ now < efi_events[i].trigger_next)
+ continue;
+ if (efi_events[i].trigger_type == EFI_TIMER_PERIODIC) {
+ efi_events[i].trigger_next +=
+ efi_events[i].trigger_time;
+ efi_events[i].signaled = 0;
+ }
+ efi_signal_event(&efi_events[i]);
}
-
WATCHDOG_RESET();
}
-static efi_status_t EFIAPI efi_set_timer(void *event, int type,
- uint64_t trigger_time)
+efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
+ uint64_t trigger_time)
{
- /* We don't have 64bit division available everywhere, so limit timer
- * distances to 32bit bits. */
- u32 trigger32 = trigger_time;
-
- EFI_ENTRY("%p, %d, %"PRIx64, event, type, trigger_time);
+ int i;
- if (trigger32 < trigger_time) {
- printf("WARNING: Truncating timer from %"PRIx64" to %x\n",
- trigger_time, trigger32);
- }
+ /*
+ * The parameter defines a multiple of 100ns.
+ * We use multiples of 1000ns. So divide by 10.
+ */
+ trigger_time = efi_div10(trigger_time);
- if (event != &efi_event) {
- /* We only support one event at a time */
- return EFI_EXIT(EFI_INVALID_PARAMETER);
- }
+ for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
+ if (event != &efi_events[i])
+ continue;
- switch (type) {
- case EFI_TIMER_STOP:
- efi_event.trigger_next = -1ULL;
- break;
- case EFI_TIMER_PERIODIC:
- case EFI_TIMER_RELATIVE:
- efi_event.trigger_next = timer_get_us() + (trigger32 / 10);
- break;
- default:
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ if (!(event->type & EVT_TIMER))
+ break;
+ switch (type) {
+ case EFI_TIMER_STOP:
+ event->trigger_next = -1ULL;
+ break;
+ case EFI_TIMER_PERIODIC:
+ case EFI_TIMER_RELATIVE:
+ event->trigger_next =
+ timer_get_us() + trigger_time;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+ event->trigger_type = type;
+ event->trigger_time = trigger_time;
+ return EFI_SUCCESS;
}
- efi_event.trigger_type = type;
- efi_event.trigger_time = trigger_time;
+ return EFI_INVALID_PARAMETER;
+}
- return EFI_EXIT(EFI_SUCCESS);
+static efi_status_t EFIAPI efi_set_timer_ext(struct efi_event *event,
+ enum efi_timer_delay type,
+ uint64_t trigger_time)
+{
+ EFI_ENTRY("%p, %d, %"PRIx64, event, type, trigger_time);
+ return EFI_EXIT(efi_set_timer(event, type, trigger_time));
}
static efi_status_t EFIAPI efi_wait_for_event(unsigned long num_events,
- void *event, unsigned long *index)
+ struct efi_event **event,
+ unsigned long *index)
{
- u64 now;
+ int i, j;
EFI_ENTRY("%ld, %p, %p", num_events, event, index);
- now = timer_get_us();
- while (now < efi_event.trigger_next) { }
- efi_timer_check();
+ /* Check parameters */
+ if (!num_events || !event)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ for (i = 0; i < num_events; ++i) {
+ for (j = 0; j < ARRAY_SIZE(efi_events); ++j) {
+ if (event[i] == &efi_events[j])
+ goto known_event;
+ }
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+known_event:
+ if (!event[i]->type || event[i]->type & EVT_NOTIFY_SIGNAL)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ }
+
+ /* Wait for signal */
+ for (;;) {
+ for (i = 0; i < num_events; ++i) {
+ if (event[i]->signaled)
+ goto out;
+ }
+ /* Allow events to occur. */
+ efi_timer_check();
+ }
+
+out:
+ /*
+ * Reset the signal which is passed to the caller to allow periodic
+ * events to occur.
+ */
+ event[i]->signaled = 0;
+ if (index)
+ *index = i;
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t EFIAPI efi_signal_event(void *event)
+static efi_status_t EFIAPI efi_signal_event_ext(struct efi_event *event)
{
+ int i;
+
EFI_ENTRY("%p", event);
+ for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
+ if (event != &efi_events[i])
+ continue;
+ efi_signal_event(event);
+ break;
+ }
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t EFIAPI efi_close_event(void *event)
+static efi_status_t EFIAPI efi_close_event(struct efi_event *event)
{
+ int i;
+
EFI_ENTRY("%p", event);
- efi_event.trigger_next = -1ULL;
- return EFI_EXIT(EFI_SUCCESS);
+ for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
+ if (event == &efi_events[i]) {
+ event->type = 0;
+ event->trigger_next = -1ULL;
+ event->signaled = 0;
+ return EFI_EXIT(EFI_SUCCESS);
+ }
+ }
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
}
-static efi_status_t EFIAPI efi_check_event(void *event)
+static efi_status_t EFIAPI efi_check_event(struct efi_event *event)
{
+ int i;
+
EFI_ENTRY("%p", event);
- return EFI_EXIT(EFI_NOT_READY);
+ efi_timer_check();
+ for (i = 0; i < ARRAY_SIZE(efi_events); ++i) {
+ if (event != &efi_events[i])
+ continue;
+ if (!event->type || event->type & EVT_NOTIFY_SIGNAL)
+ break;
+ if (event->signaled)
+ return EFI_EXIT(EFI_SUCCESS);
+ return EFI_EXIT(EFI_NOT_READY);
+ }
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
}
static efi_status_t EFIAPI efi_install_protocol_interface(void **handle,
efi_guid_t *protocol, int protocol_interface_type,
void *protocol_interface)
{
+ struct list_head *lhandle;
+ int i;
+ efi_status_t r;
+
+ if (!handle || !protocol ||
+ protocol_interface_type != EFI_NATIVE_INTERFACE) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* Create new handle if requested. */
+ if (!*handle) {
+ r = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+ /* Find object. */
+ list_for_each(lhandle, &efi_obj_list) {
+ struct efi_object *efiobj;
+ efiobj = list_entry(lhandle, struct efi_object, link);
+
+ if (efiobj->handle != *handle)
+ continue;
+ /* Check if protocol is already installed on the handle. */
+ for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+ struct efi_handler *handler = &efiobj->protocols[i];
+
+ if (!handler->guid)
+ continue;
+ if (!guidcmp(handler->guid, protocol)) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ }
+ /* Install protocol in first empty slot. */
+ for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+ struct efi_handler *handler = &efiobj->protocols[i];
+
+ if (handler->guid)
+ continue;
+
+ handler->guid = protocol;
+ handler->protocol_interface = protocol_interface;
+ r = EFI_SUCCESS;
+ goto out;
+ }
+ r = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+ r = EFI_INVALID_PARAMETER;
+out:
+ return r;
+}
+
+static efi_status_t EFIAPI efi_install_protocol_interface_ext(void **handle,
+ efi_guid_t *protocol, int protocol_interface_type,
+ void *protocol_interface)
+{
EFI_ENTRY("%p, %p, %d, %p", handle, protocol, protocol_interface_type,
protocol_interface);
- return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+
+ return EFI_EXIT(efi_install_protocol_interface(handle, protocol,
+ protocol_interface_type,
+ protocol_interface));
}
+
static efi_status_t EFIAPI efi_reinstall_protocol_interface(void *handle,
efi_guid_t *protocol, void *old_interface,
void *new_interface)
static efi_status_t EFIAPI efi_uninstall_protocol_interface(void *handle,
efi_guid_t *protocol, void *protocol_interface)
{
+ struct list_head *lhandle;
+ int i;
+ efi_status_t r = EFI_NOT_FOUND;
+
+ if (!handle || !protocol) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ list_for_each(lhandle, &efi_obj_list) {
+ struct efi_object *efiobj;
+ efiobj = list_entry(lhandle, struct efi_object, link);
+
+ if (efiobj->handle != handle)
+ continue;
+
+ for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+ struct efi_handler *handler = &efiobj->protocols[i];
+ const efi_guid_t *hprotocol = handler->guid;
+
+ if (!hprotocol)
+ continue;
+ if (!guidcmp(hprotocol, protocol)) {
+ if (handler->protocol_interface) {
+ r = EFI_ACCESS_DENIED;
+ } else {
+ handler->guid = 0;
+ r = EFI_SUCCESS;
+ }
+ goto out;
+ }
+ }
+ }
+
+out:
+ return r;
+}
+
+static efi_status_t EFIAPI efi_uninstall_protocol_interface_ext(void *handle,
+ efi_guid_t *protocol, void *protocol_interface)
+{
EFI_ENTRY("%p, %p, %p", handle, protocol, protocol_interface);
- return EFI_EXIT(EFI_NOT_FOUND);
+
+ return EFI_EXIT(efi_uninstall_protocol_interface(handle, protocol,
+ protocol_interface));
}
static efi_status_t EFIAPI efi_register_protocol_notify(efi_guid_t *protocol,
- void *event,
+ struct efi_event *event,
void **registration)
{
EFI_ENTRY("%p, %p, %p", protocol, event, registration);
struct list_head *lhandle;
unsigned long size = 0;
- EFI_ENTRY("%d, %p, %p, %p, %p", search_type, protocol, search_key,
- buffer_size, buffer);
-
/* Count how much space we need */
list_for_each(lhandle, &efi_obj_list) {
struct efi_object *efiobj;
if (*buffer_size < size) {
*buffer_size = size;
- return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ return EFI_BUFFER_TOO_SMALL;
}
/* Then fill the array */
}
*buffer_size = size;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI efi_locate_handle_ext(
+ enum efi_locate_search_type search_type,
+ efi_guid_t *protocol, void *search_key,
+ unsigned long *buffer_size, efi_handle_t *buffer)
+{
+ EFI_ENTRY("%d, %p, %p, %p, %p", search_type, protocol, search_key,
+ buffer_size, buffer);
+
+ return EFI_EXIT(efi_locate_handle(search_type, protocol, search_key,
+ buffer_size, buffer));
}
static efi_status_t EFIAPI efi_locate_device_path(efi_guid_t *protocol,
return EFI_EXIT(EFI_NOT_FOUND);
}
+/* Collapses configuration table entries, removing index i */
+static void efi_remove_configuration_table(int i)
+{
+ struct efi_configuration_table *this = &efi_conf_table[i];
+ struct efi_configuration_table *next = &efi_conf_table[i+1];
+ struct efi_configuration_table *end = &efi_conf_table[systab.nr_tables];
+
+ memmove(this, next, (ulong)end - (ulong)next);
+ systab.nr_tables--;
+}
+
efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table)
{
int i;
/* Check for guid override */
for (i = 0; i < systab.nr_tables; i++) {
if (!guidcmp(guid, &efi_conf_table[i].guid)) {
- efi_conf_table[i].table = table;
+ if (table)
+ efi_conf_table[i].table = table;
+ else
+ efi_remove_configuration_table(i);
return EFI_SUCCESS;
}
}
+ if (!table)
+ return EFI_NOT_FOUND;
+
/* No override, check for overflow */
if (i >= ARRAY_SIZE(efi_conf_table))
return EFI_OUT_OF_RESOURCES;
.protocols = {
{
.guid = &efi_guid_loaded_image,
- .open = &efi_return_handle,
},
},
};
EFI_ENTRY("%d, %p, %p, %p, %ld, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
info = malloc(sizeof(*info));
+ loaded_image_info_obj.protocols[0].protocol_interface = info;
obj = malloc(sizeof(loaded_image_info_obj));
memset(info, 0, sizeof(*info));
memcpy(obj, &loaded_image_info_obj, sizeof(loaded_image_info_obj));
return EFI_EXIT(info->exit_status);
}
+ __efi_nesting_dec();
+ __efi_exit_check();
entry(image_handle, &systab);
+ __efi_entry_check();
+ __efi_nesting_inc();
/* Should usually never get here */
return EFI_EXIT(EFI_SUCCESS);
{
EFI_ENTRY("%ld, 0x%"PRIx64", %ld, %p", timeout, watchdog_code,
data_size, watchdog_data);
- return EFI_EXIT(efi_unsupported(__func__));
+ return efi_unsupported(__func__);
}
static efi_status_t EFIAPI efi_connect_controller(
efi_guid_t ***protocol_buffer,
unsigned long *protocol_buffer_count)
{
+ unsigned long buffer_size;
+ struct efi_object *efiobj;
+ unsigned long i, j;
+ struct list_head *lhandle;
+ efi_status_t r;
+
EFI_ENTRY("%p, %p, %p", handle, protocol_buffer,
protocol_buffer_count);
- return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+
+ if (!handle || !protocol_buffer || !protocol_buffer_count)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ *protocol_buffer = NULL;
+ *protocol_buffer_count = 0;
+ list_for_each(lhandle, &efi_obj_list) {
+ efiobj = list_entry(lhandle, struct efi_object, link);
+
+ if (efiobj->handle != handle)
+ continue;
+
+ /* Count protocols */
+ for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+ if (efiobj->protocols[i].guid)
+ ++*protocol_buffer_count;
+ }
+ /* Copy guids */
+ if (*protocol_buffer_count) {
+ buffer_size = sizeof(efi_guid_t *) *
+ *protocol_buffer_count;
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES,
+ buffer_size,
+ (void **)protocol_buffer);
+ if (r != EFI_SUCCESS)
+ return EFI_EXIT(r);
+ j = 0;
+ for (i = 0; i < ARRAY_SIZE(efiobj->protocols); ++i) {
+ if (efiobj->protocols[i].guid) {
+ (*protocol_buffer)[j] = (void *)
+ efiobj->protocols[i].guid;
+ ++j;
+ }
+ }
+ }
+ break;
+ }
+
+ return EFI_EXIT(EFI_SUCCESS);
}
static efi_status_t EFIAPI efi_locate_handle_buffer(
efi_guid_t *protocol, void *search_key,
unsigned long *no_handles, efi_handle_t **buffer)
{
+ efi_status_t r;
+ unsigned long buffer_size = 0;
+
EFI_ENTRY("%d, %p, %p, %p, %p", search_type, protocol, search_key,
no_handles, buffer);
- return EFI_EXIT(EFI_NOT_FOUND);
-}
-static struct efi_class_map efi_class_maps[] = {
- {
- .guid = &efi_guid_console_control,
- .interface = &efi_console_control
- },
-};
+ if (!no_handles || !buffer) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ *no_handles = 0;
+ *buffer = NULL;
+ r = efi_locate_handle(search_type, protocol, search_key, &buffer_size,
+ *buffer);
+ if (r != EFI_BUFFER_TOO_SMALL)
+ goto out;
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, buffer_size,
+ (void **)buffer);
+ if (r != EFI_SUCCESS)
+ goto out;
+ r = efi_locate_handle(search_type, protocol, search_key, &buffer_size,
+ *buffer);
+ if (r == EFI_SUCCESS)
+ *no_handles = buffer_size / sizeof(void *);
+out:
+ return EFI_EXIT(r);
+}
static efi_status_t EFIAPI efi_locate_protocol(efi_guid_t *protocol,
void *registration,
void **protocol_interface)
{
+ struct list_head *lhandle;
int i;
EFI_ENTRY("%p, %p, %p", protocol, registration, protocol_interface);
- for (i = 0; i < ARRAY_SIZE(efi_class_maps); i++) {
- struct efi_class_map *curmap = &efi_class_maps[i];
- if (!guidcmp(protocol, curmap->guid)) {
- *protocol_interface = (void*)curmap->interface;
- return EFI_EXIT(EFI_SUCCESS);
+
+ if (!protocol || !protocol_interface)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ list_for_each(lhandle, &efi_obj_list) {
+ struct efi_object *efiobj;
+
+ efiobj = list_entry(lhandle, struct efi_object, link);
+ for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+ struct efi_handler *handler = &efiobj->protocols[i];
+
+ if (!handler->guid)
+ continue;
+ if (!guidcmp(handler->guid, protocol)) {
+ *protocol_interface =
+ handler->protocol_interface;
+ return EFI_EXIT(EFI_SUCCESS);
+ }
}
}
+ *protocol_interface = NULL;
return EFI_EXIT(EFI_NOT_FOUND);
}
void **handle, ...)
{
EFI_ENTRY("%p", handle);
- return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+
+ va_list argptr;
+ efi_guid_t *protocol;
+ void *protocol_interface;
+ efi_status_t r = EFI_SUCCESS;
+ int i = 0;
+
+ if (!handle)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ va_start(argptr, handle);
+ for (;;) {
+ protocol = va_arg(argptr, efi_guid_t*);
+ if (!protocol)
+ break;
+ protocol_interface = va_arg(argptr, void*);
+ r = efi_install_protocol_interface(handle, protocol,
+ EFI_NATIVE_INTERFACE,
+ protocol_interface);
+ if (r != EFI_SUCCESS)
+ break;
+ i++;
+ }
+ va_end(argptr);
+ if (r == EFI_SUCCESS)
+ return EFI_EXIT(r);
+
+ /* If an error occured undo all changes. */
+ va_start(argptr, handle);
+ for (; i; --i) {
+ protocol = va_arg(argptr, efi_guid_t*);
+ protocol_interface = va_arg(argptr, void*);
+ efi_uninstall_protocol_interface(handle, protocol,
+ protocol_interface);
+ }
+ va_end(argptr);
+
+ return EFI_EXIT(r);
}
static efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces(
{
struct list_head *lhandle;
int i;
- efi_status_t r = EFI_UNSUPPORTED;
+ efi_status_t r = EFI_INVALID_PARAMETER;
EFI_ENTRY("%p, %p, %p, %p, %p, 0x%x", handle, protocol,
protocol_interface, agent_handle, controller_handle,
attributes);
+
+ if (!handle || !protocol ||
+ (!protocol_interface && attributes !=
+ EFI_OPEN_PROTOCOL_TEST_PROTOCOL)) {
+ goto out;
+ }
+
+ switch (attributes) {
+ case EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL:
+ case EFI_OPEN_PROTOCOL_GET_PROTOCOL:
+ case EFI_OPEN_PROTOCOL_TEST_PROTOCOL:
+ break;
+ case EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER:
+ if (controller_handle == handle)
+ goto out;
+ case EFI_OPEN_PROTOCOL_BY_DRIVER:
+ case EFI_OPEN_PROTOCOL_BY_DRIVER | EFI_OPEN_PROTOCOL_EXCLUSIVE:
+ if (controller_handle == NULL)
+ goto out;
+ case EFI_OPEN_PROTOCOL_EXCLUSIVE:
+ if (agent_handle == NULL)
+ goto out;
+ break;
+ default:
+ goto out;
+ }
+
list_for_each(lhandle, &efi_obj_list) {
struct efi_object *efiobj;
efiobj = list_entry(lhandle, struct efi_object, link);
struct efi_handler *handler = &efiobj->protocols[i];
const efi_guid_t *hprotocol = handler->guid;
if (!hprotocol)
- break;
+ continue;
if (!guidcmp(hprotocol, protocol)) {
- r = handler->open(handle, protocol,
- protocol_interface, agent_handle,
- controller_handle, attributes);
+ if (attributes !=
+ EFI_OPEN_PROTOCOL_TEST_PROTOCOL) {
+ *protocol_interface =
+ handler->protocol_interface;
+ }
+ r = EFI_SUCCESS;
goto out;
}
}
+ goto unsupported;
}
+unsupported:
+ r = EFI_UNSUPPORTED;
out:
return EFI_EXIT(r);
}
.get_memory_map = efi_get_memory_map_ext,
.allocate_pool = efi_allocate_pool_ext,
.free_pool = efi_free_pool_ext,
- .create_event = efi_create_event,
- .set_timer = efi_set_timer,
+ .create_event = efi_create_event_ext,
+ .set_timer = efi_set_timer_ext,
.wait_for_event = efi_wait_for_event,
- .signal_event = efi_signal_event,
+ .signal_event = efi_signal_event_ext,
.close_event = efi_close_event,
.check_event = efi_check_event,
- .install_protocol_interface = efi_install_protocol_interface,
+ .install_protocol_interface = efi_install_protocol_interface_ext,
.reinstall_protocol_interface = efi_reinstall_protocol_interface,
- .uninstall_protocol_interface = efi_uninstall_protocol_interface,
+ .uninstall_protocol_interface = efi_uninstall_protocol_interface_ext,
.handle_protocol = efi_handle_protocol,
.reserved = NULL,
.register_protocol_notify = efi_register_protocol_notify,
- .locate_handle = efi_locate_handle,
+ .locate_handle = efi_locate_handle_ext,
.locate_device_path = efi_locate_device_path,
.install_configuration_table = efi_install_configuration_table_ext,
.load_image = efi_load_image,
return EFI_EXIT(EFI_SUCCESS);
}
-const struct efi_simple_input_interface efi_con_in = {
+struct efi_simple_input_interface efi_con_in = {
.reset = efi_cin_reset,
.read_key_stroke = efi_cin_read_key_stroke,
.wait_for_key = NULL,
};
+
+static struct efi_event *console_timer_event;
+
+static void EFIAPI efi_key_notify(struct efi_event *event, void *context)
+{
+}
+
+static void EFIAPI efi_console_timer_notify(struct efi_event *event,
+ void *context)
+{
+ EFI_ENTRY("%p, %p", event, context);
+ if (tstc())
+ efi_signal_event(efi_con_in.wait_for_key);
+ EFI_EXIT(EFI_SUCCESS);
+}
+
+
+static struct efi_object efi_console_control_obj =
+ EFI_PROTOCOL_OBJECT(efi_guid_console_control, &efi_console_control);
+static struct efi_object efi_console_output_obj =
+ EFI_PROTOCOL_OBJECT(EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID, &efi_con_out);
+static struct efi_object efi_console_input_obj =
+ EFI_PROTOCOL_OBJECT(EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID, &efi_con_in);
+
+/* This gets called from do_bootefi_exec(). */
+int efi_console_register(void)
+{
+ efi_status_t r;
+
+ /* Hook up to the device list */
+ list_add_tail(&efi_console_control_obj.link, &efi_obj_list);
+ list_add_tail(&efi_console_output_obj.link, &efi_obj_list);
+ list_add_tail(&efi_console_input_obj.link, &efi_obj_list);
+
+ r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK,
+ efi_key_notify, NULL, &efi_con_in.wait_for_key);
+ if (r != EFI_SUCCESS) {
+ printf("ERROR: Failed to register WaitForKey event\n");
+ return r;
+ }
+ r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
+ efi_console_timer_notify, NULL,
+ &console_timer_event);
+ if (r != EFI_SUCCESS) {
+ printf("ERROR: Failed to register console event\n");
+ return r;
+ }
+ /* 5000 ns cycle is sufficient for 2 MBaud */
+ r = efi_set_timer(console_timer_event, EFI_TIMER_PERIODIC, 50);
+ if (r != EFI_SUCCESS)
+ printf("ERROR: Failed to set console timer\n");
+ return r;
+}
--- /dev/null
+/*
+ * EFI device path interface
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+
+#define MAC_OUTPUT_LEN 22
+#define UNKNOWN_OUTPUT_LEN 23
+
+const efi_guid_t efi_guid_device_path_to_text_protocol =
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID;
+
+static uint16_t *efi_convert_device_node_to_text(
+ struct efi_device_path_protocol *device_node,
+ bool display_only,
+ bool allow_shortcuts)
+{
+ unsigned long buffer_size;
+ efi_status_t r;
+ uint16_t *buffer = NULL;
+ int i;
+
+ switch (device_node->type) {
+ case DEVICE_PATH_TYPE_END:
+ return NULL;
+ case DEVICE_PATH_TYPE_MESSAGING_DEVICE:
+ switch (device_node->sub_type) {
+ case DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR: {
+ struct efi_device_path_mac_addr *dp =
+ (struct efi_device_path_mac_addr *)device_node;
+
+ if (dp->if_type != 0 && dp->if_type != 1)
+ break;
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES,
+ 2 * MAC_OUTPUT_LEN,
+ (void **)&buffer);
+ if (r != EFI_SUCCESS)
+ return NULL;
+ sprintf((char *)buffer,
+ "MAC(%02x%02x%02x%02x%02x%02x,0x%1x)",
+ dp->mac.addr[0], dp->mac.addr[1],
+ dp->mac.addr[2], dp->mac.addr[3],
+ dp->mac.addr[4], dp->mac.addr[5],
+ dp->if_type);
+ for (i = MAC_OUTPUT_LEN - 1; i >= 0; --i)
+ buffer[i] = ((uint8_t *)buffer)[i];
+ break;
+ }
+ }
+ break;
+ case DEVICE_PATH_TYPE_MEDIA_DEVICE:
+ switch (device_node->sub_type) {
+ case DEVICE_PATH_SUB_TYPE_FILE_PATH:
+ buffer_size = device_node->length - 4;
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES,
+ buffer_size, (void **) &buffer);
+ if (r != EFI_SUCCESS)
+ return NULL;
+ memcpy(buffer, device_node->data, buffer_size);
+ break;
+ }
+ break;
+ }
+
+ /*
+ * For all node types that we do not yet support return
+ * 'UNKNOWN(type,subtype)'.
+ */
+ if (!buffer) {
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES,
+ 2 * UNKNOWN_OUTPUT_LEN,
+ (void **)&buffer);
+ if (r != EFI_SUCCESS)
+ return NULL;
+ sprintf((char *)buffer,
+ "UNKNOWN(%04x,%04x)",
+ device_node->type,
+ device_node->sub_type);
+ for (i = UNKNOWN_OUTPUT_LEN - 1; i >= 0; --i)
+ buffer[i] = ((uint8_t *)buffer)[i];
+ }
+
+ return buffer;
+}
+
+static uint16_t EFIAPI *efi_convert_device_node_to_text_ext(
+ struct efi_device_path_protocol *device_node,
+ bool display_only,
+ bool allow_shortcuts)
+{
+ uint16_t *buffer;
+
+ EFI_ENTRY("%p, %d, %d", device_node, display_only, allow_shortcuts);
+
+ buffer = efi_convert_device_node_to_text(device_node, display_only,
+ allow_shortcuts);
+
+ EFI_EXIT(EFI_SUCCESS);
+ return buffer;
+}
+
+static uint16_t EFIAPI *efi_convert_device_path_to_text(
+ struct efi_device_path_protocol *device_path,
+ bool display_only,
+ bool allow_shortcuts)
+{
+ uint16_t *buffer;
+
+ EFI_ENTRY("%p, %d, %d", device_path, display_only, allow_shortcuts);
+
+ /*
+ * Our device paths are all of depth one. So its is sufficient to
+ * to convert the first node.
+ */
+ buffer = efi_convert_device_node_to_text(device_path, display_only,
+ allow_shortcuts);
+
+ EFI_EXIT(EFI_SUCCESS);
+ return buffer;
+}
+
+const struct efi_device_path_to_text_protocol efi_device_path_to_text = {
+ .convert_device_node_to_text = efi_convert_device_node_to_text_ext,
+ .convert_device_path_to_text = efi_convert_device_path_to_text,
+};
const struct blk_desc *desc;
};
-static efi_status_t EFIAPI efi_disk_open_block(void *handle,
- efi_guid_t *protocol, void **protocol_interface,
- void *agent_handle, void *controller_handle,
- uint32_t attributes)
-{
- struct efi_disk_obj *diskobj = handle;
-
- *protocol_interface = &diskobj->ops;
-
- return EFI_SUCCESS;
-}
-
-static efi_status_t EFIAPI efi_disk_open_dp(void *handle, efi_guid_t *protocol,
- void **protocol_interface, void *agent_handle,
- void *controller_handle, uint32_t attributes)
-{
- struct efi_disk_obj *diskobj = handle;
-
- *protocol_interface = diskobj->dp;
-
- return EFI_SUCCESS;
-}
-
static efi_status_t EFIAPI efi_disk_reset(struct efi_block_io *this,
char extended_verification)
{
/* We only support full block access */
if (buffer_size & (blksz - 1))
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ return EFI_DEVICE_ERROR;
if (direction == EFI_DISK_READ)
n = blk_dread(desc, lba, blocks, buffer);
debug("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
if (n != blocks)
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ return EFI_DEVICE_ERROR;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_SUCCESS;
}
static efi_status_t EFIAPI efi_disk_read_blocks(struct efi_block_io *this,
diskobj = calloc(1, objlen);
/* Fill in object data */
+ dp = (void *)&diskobj[1];
diskobj->parent.protocols[0].guid = &efi_block_io_guid;
- diskobj->parent.protocols[0].open = efi_disk_open_block;
+ diskobj->parent.protocols[0].protocol_interface = &diskobj->ops;
diskobj->parent.protocols[1].guid = &efi_guid_device_path;
- diskobj->parent.protocols[1].open = efi_disk_open_dp;
+ diskobj->parent.protocols[1].protocol_interface = dp;
diskobj->parent.handle = diskobj;
diskobj->ops = block_io_disk_template;
diskobj->ifname = if_typename;
diskobj->ops.media = &diskobj->media;
/* Fill in device path */
- dp = (void*)&diskobj[1];
diskobj->dp = dp;
dp[0].dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
dp[0].dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH;
#ifdef CONFIG_BLK
struct udevice *dev;
- for (uclass_first_device(UCLASS_BLK, &dev);
+ for (uclass_first_device_check(UCLASS_BLK, &dev);
dev;
- uclass_next_device(&dev)) {
+ uclass_next_device_check(&dev)) {
struct blk_desc *desc = dev_get_uclass_platdata(dev);
const char *if_typename = dev->driver->name;
struct efi_gop_mode mode;
/* Fields we only have acces to during init */
u32 bpix;
+ void *fb;
};
static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number,
if (operation != EFI_BLT_BUFFER_TO_VIDEO)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- fb = (void*)gd->fb_base;
+ fb = gopobj->fb;
line_len16 = gopobj->info.width * sizeof(u16);
line_len32 = gopobj->info.width * sizeof(u32);
struct efi_gop_obj *gopobj;
u32 bpix, col, row;
u64 fb_base, fb_size;
+ void *fb;
#ifdef CONFIG_DM_VIDEO
struct udevice *vdev;
row = video_get_ysize(vdev);
fb_base = (uintptr_t)priv->fb;
fb_size = priv->fb_size;
+ fb = priv->fb;
#else
int line_len;
row = panel_info.vl_row;
fb_base = gd->fb_base;
fb_size = lcd_get_size(&line_len);
+ fb = (void*)gd->fb_base;
#endif
switch (bpix) {
/* Fill in object data */
gopobj->parent.protocols[0].guid = &efi_gop_guid;
- gopobj->parent.protocols[0].open = efi_return_handle;
+ gopobj->parent.protocols[0].protocol_interface = &gopobj->ops;
gopobj->parent.handle = &gopobj->ops;
gopobj->ops.query_mode = gop_query_mode;
gopobj->ops.set_mode = gop_set_mode;
gopobj->info.pixels_per_scanline = col;
gopobj->bpix = bpix;
+ gopobj->fb = fb;
/* Hook up to the device list */
list_add_tail(&gopobj->parent.link, &efi_obj_list);
const efi_guid_t efi_guid_device_path = DEVICE_PATH_GUID;
const efi_guid_t efi_guid_loaded_image = LOADED_IMAGE_GUID;
-efi_status_t EFIAPI efi_return_handle(void *handle, efi_guid_t *protocol,
- void **protocol_interface, void *agent_handle,
- void *controller_handle, uint32_t attributes)
-{
- *protocol_interface = handle;
- return EFI_SUCCESS;
-}
-
static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
unsigned long rel_size, void *efi_reloc)
{
efi_status_t r;
struct efi_pool_allocation *alloc;
+ if (buffer == NULL)
+ return EFI_INVALID_PARAMETER;
+
alloc = container_of(buffer, struct efi_pool_allocation, data);
/* Sanity check, was the supplied address returned by allocate_pool */
assert(((uintptr_t)alloc & EFI_PAGE_MASK) == 0);
*memory_map_size = map_size;
+ if (provided_map_size < map_size)
+ return EFI_BUFFER_TOO_SMALL;
+
if (descriptor_size)
*descriptor_size = sizeof(struct efi_mem_desc);
if (descriptor_version)
*descriptor_version = EFI_MEMORY_DESCRIPTOR_VERSION;
- if (provided_map_size < map_size)
- return EFI_BUFFER_TOO_SMALL;
-
/* Copy list into array */
if (memory_map) {
/* Return the list in ascending order */
}
}
+ *map_key = 0;
+
return EFI_SUCCESS;
}
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t EFIAPI efi_net_open_dp(void *handle, efi_guid_t *protocol,
- void **protocol_interface, void *agent_handle,
- void *controller_handle, uint32_t attributes)
-{
- struct efi_simple_network *net = handle;
- struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
-
- *protocol_interface = &netobj->dp_mac;
-
- return EFI_SUCCESS;
-}
-
-static efi_status_t EFIAPI efi_net_open_pxe(void *handle, efi_guid_t *protocol,
- void **protocol_interface, void *agent_handle,
- void *controller_handle, uint32_t attributes)
-{
- struct efi_simple_network *net = handle;
- struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
-
- *protocol_interface = &netobj->pxe;
-
- return EFI_SUCCESS;
-}
-
void efi_net_set_dhcp_ack(void *pkt, int len)
{
int maxsize = sizeof(*dhcp_ack);
/* Fill in object data */
netobj->parent.protocols[0].guid = &efi_net_guid;
- netobj->parent.protocols[0].open = efi_return_handle;
+ netobj->parent.protocols[0].protocol_interface = &netobj->net;
netobj->parent.protocols[1].guid = &efi_guid_device_path;
- netobj->parent.protocols[1].open = efi_net_open_dp;
+ netobj->parent.protocols[1].protocol_interface = &netobj->dp_mac;
netobj->parent.protocols[2].guid = &efi_pxe_guid;
- netobj->parent.protocols[2].open = efi_net_open_pxe;
+ netobj->parent.protocols[2].protocol_interface = &netobj->pxe;
netobj->parent.handle = &netobj->net;
netobj->net.start = efi_net_start;
netobj->net.stop = efi_net_stop;
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
- COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
- COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
- COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
- COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
- COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
- COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
quiet_cmd_acpi_c_asl= ASL $<
cmd_acpi_c_asl= \
$(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
- iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
+ iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \
mv $(patsubst %.asl,%.hex,$<) $@
$(obj)/dsdt.c: $(src)/dsdt.asl
CONFIG_ENV_VARS_UBOOT_CONFIG
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
CONFIG_ENV_VERSION
-CONFIG_ENV_xxx
CONFIG_EP9301
CONFIG_EP9302
CONFIG_EP9307
CONFIG_FORMIKE
CONFIG_FPGA_COUNT
CONFIG_FPGA_DELAY
-CONFIG_FPGA_SOCFPGA
CONFIG_FPGA_SPARTAN3
CONFIG_FPGA_STRATIX_V
CONFIG_FPGA_ZYNQPL
CONFIG_INI_MAX_NAME
CONFIG_INI_MAX_SECTION
CONFIG_INTEGRITY
-CONFIG_INTEL_ICH6_GPIO
CONFIG_INTERRUPTS
CONFIG_IO
CONFIG_IO64
CONFIG_SCIF_USE_EXT_CLK
CONFIG_SCSI_AHCI
CONFIG_SCSI_AHCI_PLAT
-CONFIG_SCSI_DEV_ID
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
CONFIG_STATIC_RELA
CONFIG_STD_DEVICES_SETTINGS
CONFIG_STM32F4DISCOVERY
-CONFIG_STM32X7_SERIAL
CONFIG_STM32_FLASH
CONFIG_STM32_GPIO
CONFIG_STM32_HSE_HZ
CONFIG_SYS_BOOT_RAMDISK_HIGH
CONFIG_SYS_BR0_64M
CONFIG_SYS_BR0_8M
-CONFIG_SYS_BR0_PRELIM
-CONFIG_SYS_BR1_PRELIM
-CONFIG_SYS_BR2_PRELIM
-CONFIG_SYS_BR3_PRELIM
-CONFIG_SYS_BR4_PRELIM
-CONFIG_SYS_BR5_PRELIM
CONFIG_SYS_BR6_64M
CONFIG_SYS_BR6_8M
-CONFIG_SYS_BR6_PRELIM
-CONFIG_SYS_BR7_PRELIM
CONFIG_SYS_BUSCLK
CONFIG_SYS_CACHELINE_SHIFT
CONFIG_SYS_CACHE_ACR0
CONFIG_SYS_ETHOC_BUFFER_ADDR
CONFIG_SYS_ETVPE_CLK
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-CONFIG_SYS_EXTBDINFO
CONFIG_SYS_EXTRA_ENV_RELOC
CONFIG_SYS_FAST_CLK
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
CONFIG_SYS_ID_EEPROM
CONFIG_SYS_IFC_ADDR
CONFIG_SYS_IFC_CCR
-CONFIG_SYS_IMMR
CONFIG_SYS_INIT_DBCR
CONFIG_SYS_INIT_L2CSR0
CONFIG_SYS_INIT_L2_ADDR
CONFIG_SYS_ONENAND_PAGE_SIZE
CONFIG_SYS_OR0_64M
CONFIG_SYS_OR0_8M
-CONFIG_SYS_OR0_PRELIM
CONFIG_SYS_OR0_REMAP
-CONFIG_SYS_OR1_PRELIM
CONFIG_SYS_OR1_REMAP
-CONFIG_SYS_OR2_PRELIM
-CONFIG_SYS_OR3_PRELIM
-CONFIG_SYS_OR4_PRELIM
-CONFIG_SYS_OR5_PRELIM
CONFIG_SYS_OR6_64M
CONFIG_SYS_OR6_8M
-CONFIG_SYS_OR6_PRELIM
-CONFIG_SYS_OR7_PRELIM
CONFIG_SYS_OR_TIMING_FLASH
CONFIG_SYS_OR_TIMING_MRAM
CONFIG_SYS_OSCIN_FREQ
CONFIG_SYS_SCSI_MAX_DEVICE
CONFIG_SYS_SCSI_MAX_LUN
CONFIG_SYS_SCSI_MAX_SCSI_ID
-CONFIG_SYS_SCSI_SPIN_UP_TIME
CONFIG_SYS_SDHC_CLK
CONFIG_SYS_SDHC_CLK_2_PLL
CONFIG_SYS_SDIO0
CONFIG_SYS_USBCTRL
CONFIG_SYS_USBD_BASE
CONFIG_SYS_USB_EHCI_CPU_INIT
-CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_EHCI_REGS_BASE
CONFIG_SYS_USB_FAT_BOOT_PARTITION
CONFIG_SYS_USB_HOST
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_OHCI_REGS_BASE
CONFIG_SYS_USB_OHCI_SLOT_NAME
-CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
CONFIG_SYS_USER_SWITCHES_BASE
CONFIG_SYS_USE_BOOT_NORFLASH
CONFIG_SYS_USE_DATAFLASH
CONFIG_SYS_USE_NORFLASH
CONFIG_SYS_USE_SERIALFLASH
CONFIG_SYS_USE_SPIFLASH
-CONFIG_SYS_USE_UBI
CONFIG_SYS_USR_EXCEP
CONFIG_SYS_U_BOOT_OFFS
CONFIG_SYS_VA_BITS
CONFIG_TWL4030_INPUT
CONFIG_TWL4030_KEYPAD
CONFIG_TWL4030_LED
-CONFIG_TWL4030_PWM
CONFIG_TWL4030_USB
CONFIG_TWL6030_INPUT
CONFIG_TWL6030_POWER
CONFIG_USB_XHCI_FSL
CONFIG_USB_XHCI_KEYSTONE
CONFIG_USB_XHCI_OMAP
-CONFIG_USB_XHCI_PCI
CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_FDT
CONFIG_USE_INTERRUPT
projects / platform / kernel / u-boot.git / commitdiff